1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
54 #include <bitset>
55 #include <numeric>
56 #include <cctype>
57 using namespace llvm;
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
67 cl::Hidden);
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(false),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
72 cl::Hidden);
74 // Forward declarations.
75 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
76 SDValue V2);
78 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
79 SelectionDAG &DAG, SDLoc dl,
80 unsigned vectorWidth) {
81 assert((vectorWidth == 128 || vectorWidth == 256) &&
82 "Unsupported vector width");
83 EVT VT = Vec.getValueType();
84 EVT ElVT = VT.getVectorElementType();
85 unsigned Factor = VT.getSizeInBits()/vectorWidth;
86 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
87 VT.getVectorNumElements()/Factor);
89 // Extract from UNDEF is UNDEF.
90 if (Vec.getOpcode() == ISD::UNDEF)
91 return DAG.getUNDEF(ResultVT);
93 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
94 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
96 // This is the index of the first element of the vectorWidth-bit chunk
97 // we want.
98 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
99 * ElemsPerChunk);
101 // If the input is a buildvector just emit a smaller one.
102 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
103 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
104 makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
105 ElemsPerChunk));
107 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
108 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
109 VecIdx);
111 return Result;
113 }
114 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
115 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
116 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
117 /// instructions or a simple subregister reference. Idx is an index in the
118 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
119 /// lowering EXTRACT_VECTOR_ELT operations easier.
120 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
121 SelectionDAG &DAG, SDLoc dl) {
122 assert((Vec.getValueType().is256BitVector() ||
123 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
124 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
125 }
127 /// Generate a DAG to grab 256-bits from a 512-bit vector.
128 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
129 SelectionDAG &DAG, SDLoc dl) {
130 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
131 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
132 }
134 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
135 unsigned IdxVal, SelectionDAG &DAG,
136 SDLoc dl, unsigned vectorWidth) {
137 assert((vectorWidth == 128 || vectorWidth == 256) &&
138 "Unsupported vector width");
139 // Inserting UNDEF is Result
140 if (Vec.getOpcode() == ISD::UNDEF)
141 return Result;
142 EVT VT = Vec.getValueType();
143 EVT ElVT = VT.getVectorElementType();
144 EVT ResultVT = Result.getValueType();
146 // Insert the relevant vectorWidth bits.
147 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
149 // This is the index of the first element of the vectorWidth-bit chunk
150 // we want.
151 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
152 * ElemsPerChunk);
154 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
155 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
156 VecIdx);
157 }
158 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
159 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
160 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
161 /// simple superregister reference. Idx is an index in the 128 bits
162 /// we want. It need not be aligned to a 128-bit bounday. That makes
163 /// lowering INSERT_VECTOR_ELT operations easier.
164 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
165 unsigned IdxVal, SelectionDAG &DAG,
166 SDLoc dl) {
167 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
168 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
169 }
171 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
172 unsigned IdxVal, SelectionDAG &DAG,
173 SDLoc dl) {
174 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
175 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
176 }
178 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
179 /// instructions. This is used because creating CONCAT_VECTOR nodes of
180 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
181 /// large BUILD_VECTORS.
182 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
183 unsigned NumElems, SelectionDAG &DAG,
184 SDLoc dl) {
185 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
186 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
187 }
189 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
190 unsigned NumElems, SelectionDAG &DAG,
191 SDLoc dl) {
192 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
193 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
194 }
196 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
197 if (TT.isOSBinFormatMachO()) {
198 if (TT.getArch() == Triple::x86_64)
199 return new X86_64MachoTargetObjectFile();
200 return new TargetLoweringObjectFileMachO();
201 }
203 if (TT.isOSLinux())
204 return new X86LinuxTargetObjectFile();
205 if (TT.isOSBinFormatELF())
206 return new TargetLoweringObjectFileELF();
207 if (TT.isKnownWindowsMSVCEnvironment())
208 return new X86WindowsTargetObjectFile();
209 if (TT.isOSBinFormatCOFF())
210 return new TargetLoweringObjectFileCOFF();
211 llvm_unreachable("unknown subtarget type");
212 }
214 // FIXME: This should stop caching the target machine as soon as
215 // we can remove resetOperationActions et al.
216 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
217 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
218 Subtarget = &TM.getSubtarget<X86Subtarget>();
219 X86ScalarSSEf64 = Subtarget->hasSSE2();
220 X86ScalarSSEf32 = Subtarget->hasSSE1();
221 TD = getDataLayout();
223 resetOperationActions();
224 }
226 void X86TargetLowering::resetOperationActions() {
227 const TargetMachine &TM = getTargetMachine();
228 static bool FirstTimeThrough = true;
230 // If none of the target options have changed, then we don't need to reset the
231 // operation actions.
232 if (!FirstTimeThrough && TO == TM.Options) return;
234 if (!FirstTimeThrough) {
235 // Reinitialize the actions.
236 initActions();
237 FirstTimeThrough = false;
238 }
240 TO = TM.Options;
242 // Set up the TargetLowering object.
243 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
245 // X86 is weird, it always uses i8 for shift amounts and setcc results.
246 setBooleanContents(ZeroOrOneBooleanContent);
247 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
248 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
250 // For 64-bit since we have so many registers use the ILP scheduler, for
251 // 32-bit code use the register pressure specific scheduling.
252 // For Atom, always use ILP scheduling.
253 if (Subtarget->isAtom())
254 setSchedulingPreference(Sched::ILP);
255 else if (Subtarget->is64Bit())
256 setSchedulingPreference(Sched::ILP);
257 else
258 setSchedulingPreference(Sched::RegPressure);
259 const X86RegisterInfo *RegInfo =
260 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
261 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
263 // Bypass expensive divides on Atom when compiling with O2
264 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
265 addBypassSlowDiv(32, 8);
266 if (Subtarget->is64Bit())
267 addBypassSlowDiv(64, 16);
268 }
270 if (Subtarget->isTargetKnownWindowsMSVC()) {
271 // Setup Windows compiler runtime calls.
272 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
273 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
274 setLibcallName(RTLIB::SREM_I64, "_allrem");
275 setLibcallName(RTLIB::UREM_I64, "_aullrem");
276 setLibcallName(RTLIB::MUL_I64, "_allmul");
277 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
278 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
279 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
280 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
281 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
283 // The _ftol2 runtime function has an unusual calling conv, which
284 // is modeled by a special pseudo-instruction.
285 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
286 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
287 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
288 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
289 }
291 if (Subtarget->isTargetDarwin()) {
292 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
293 setUseUnderscoreSetJmp(false);
294 setUseUnderscoreLongJmp(false);
295 } else if (Subtarget->isTargetWindowsGNU()) {
296 // MS runtime is weird: it exports _setjmp, but longjmp!
297 setUseUnderscoreSetJmp(true);
298 setUseUnderscoreLongJmp(false);
299 } else {
300 setUseUnderscoreSetJmp(true);
301 setUseUnderscoreLongJmp(true);
302 }
304 // Set up the register classes.
305 addRegisterClass(MVT::i8, &X86::GR8RegClass);
306 addRegisterClass(MVT::i16, &X86::GR16RegClass);
307 addRegisterClass(MVT::i32, &X86::GR32RegClass);
308 if (Subtarget->is64Bit())
309 addRegisterClass(MVT::i64, &X86::GR64RegClass);
311 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
313 // We don't accept any truncstore of integer registers.
314 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
315 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
316 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
317 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
318 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
319 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
321 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
323 // SETOEQ and SETUNE require checking two conditions.
324 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
325 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
326 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
327 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
328 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
329 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
331 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
332 // operation.
333 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
334 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
335 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
337 if (Subtarget->is64Bit()) {
338 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
339 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
340 } else if (!TM.Options.UseSoftFloat) {
341 // We have an algorithm for SSE2->double, and we turn this into a
342 // 64-bit FILD followed by conditional FADD for other targets.
343 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
344 // We have an algorithm for SSE2, and we turn this into a 64-bit
345 // FILD for other targets.
346 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
347 }
349 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
350 // this operation.
351 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
352 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
354 if (!TM.Options.UseSoftFloat) {
355 // SSE has no i16 to fp conversion, only i32
356 if (X86ScalarSSEf32) {
357 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
358 // f32 and f64 cases are Legal, f80 case is not
359 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
360 } else {
361 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
362 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
363 }
364 } else {
365 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
366 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
367 }
369 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
370 // are Legal, f80 is custom lowered.
371 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
372 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
374 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
375 // this operation.
376 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
377 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
379 if (X86ScalarSSEf32) {
380 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
381 // f32 and f64 cases are Legal, f80 case is not
382 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
383 } else {
384 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
385 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
386 }
388 // Handle FP_TO_UINT by promoting the destination to a larger signed
389 // conversion.
390 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
391 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
392 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
394 if (Subtarget->is64Bit()) {
395 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
396 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
397 } else if (!TM.Options.UseSoftFloat) {
398 // Since AVX is a superset of SSE3, only check for SSE here.
399 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
400 // Expand FP_TO_UINT into a select.
401 // FIXME: We would like to use a Custom expander here eventually to do
402 // the optimal thing for SSE vs. the default expansion in the legalizer.
403 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
404 else
405 // With SSE3 we can use fisttpll to convert to a signed i64; without
406 // SSE, we're stuck with a fistpll.
407 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
408 }
410 if (isTargetFTOL()) {
411 // Use the _ftol2 runtime function, which has a pseudo-instruction
412 // to handle its weird calling convention.
413 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
414 }
416 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
417 if (!X86ScalarSSEf64) {
418 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
419 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
420 if (Subtarget->is64Bit()) {
421 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
422 // Without SSE, i64->f64 goes through memory.
423 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
424 }
425 }
427 // Scalar integer divide and remainder are lowered to use operations that
428 // produce two results, to match the available instructions. This exposes
429 // the two-result form to trivial CSE, which is able to combine x/y and x%y
430 // into a single instruction.
431 //
432 // Scalar integer multiply-high is also lowered to use two-result
433 // operations, to match the available instructions. However, plain multiply
434 // (low) operations are left as Legal, as there are single-result
435 // instructions for this in x86. Using the two-result multiply instructions
436 // when both high and low results are needed must be arranged by dagcombine.
437 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
438 MVT VT = IntVTs[i];
439 setOperationAction(ISD::MULHS, VT, Expand);
440 setOperationAction(ISD::MULHU, VT, Expand);
441 setOperationAction(ISD::SDIV, VT, Expand);
442 setOperationAction(ISD::UDIV, VT, Expand);
443 setOperationAction(ISD::SREM, VT, Expand);
444 setOperationAction(ISD::UREM, VT, Expand);
446 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
447 setOperationAction(ISD::ADDC, VT, Custom);
448 setOperationAction(ISD::ADDE, VT, Custom);
449 setOperationAction(ISD::SUBC, VT, Custom);
450 setOperationAction(ISD::SUBE, VT, Custom);
451 }
453 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
454 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
455 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
456 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
457 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
458 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
459 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
460 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
461 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
462 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
463 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
464 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
465 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
466 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
467 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
468 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
469 if (Subtarget->is64Bit())
470 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
471 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
472 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
473 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
474 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
475 setOperationAction(ISD::FREM , MVT::f32 , Expand);
476 setOperationAction(ISD::FREM , MVT::f64 , Expand);
477 setOperationAction(ISD::FREM , MVT::f80 , Expand);
478 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
480 // Promote the i8 variants and force them on up to i32 which has a shorter
481 // encoding.
482 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
483 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
484 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
485 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
486 if (Subtarget->hasBMI()) {
487 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
488 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
489 if (Subtarget->is64Bit())
490 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
491 } else {
492 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
493 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
494 if (Subtarget->is64Bit())
495 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
496 }
498 if (Subtarget->hasLZCNT()) {
499 // When promoting the i8 variants, force them to i32 for a shorter
500 // encoding.
501 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
502 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
503 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
504 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
505 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
506 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
507 if (Subtarget->is64Bit())
508 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
509 } else {
510 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
511 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
512 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
513 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
514 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
515 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
516 if (Subtarget->is64Bit()) {
517 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
518 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
519 }
520 }
522 // Special handling for half-precision floating point conversions.
523 // If we don't have F16C support, then lower half float conversions
524 // into library calls.
525 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
526 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
527 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
528 }
530 // There's never any support for operations beyond MVT::f32.
531 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
532 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
533 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
534 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
536 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
537 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
538 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
539 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
541 if (Subtarget->hasPOPCNT()) {
542 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
543 } else {
544 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
545 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
546 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
547 if (Subtarget->is64Bit())
548 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
549 }
551 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
553 if (!Subtarget->hasMOVBE())
554 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
556 // These should be promoted to a larger select which is supported.
557 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
558 // X86 wants to expand cmov itself.
559 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
560 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
561 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
562 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
563 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
564 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
565 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
566 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
567 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
568 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
569 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
570 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
571 if (Subtarget->is64Bit()) {
572 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
573 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
574 }
575 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
576 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
577 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
578 // support continuation, user-level threading, and etc.. As a result, no
579 // other SjLj exception interfaces are implemented and please don't build
580 // your own exception handling based on them.
581 // LLVM/Clang supports zero-cost DWARF exception handling.
582 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
583 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
585 // Darwin ABI issue.
586 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
587 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
588 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
589 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
590 if (Subtarget->is64Bit())
591 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
592 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
593 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
594 if (Subtarget->is64Bit()) {
595 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
596 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
597 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
598 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
599 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
600 }
601 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
602 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
603 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
604 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
605 if (Subtarget->is64Bit()) {
606 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
607 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
608 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
609 }
611 if (Subtarget->hasSSE1())
612 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
614 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
616 // Expand certain atomics
617 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
618 MVT VT = IntVTs[i];
619 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
620 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
621 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
622 }
624 if (Subtarget->hasCmpxchg16b()) {
625 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
626 }
628 // FIXME - use subtarget debug flags
629 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
630 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
631 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
632 }
634 if (Subtarget->is64Bit()) {
635 setExceptionPointerRegister(X86::RAX);
636 setExceptionSelectorRegister(X86::RDX);
637 } else {
638 setExceptionPointerRegister(X86::EAX);
639 setExceptionSelectorRegister(X86::EDX);
640 }
641 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
642 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
644 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
645 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
647 setOperationAction(ISD::TRAP, MVT::Other, Legal);
648 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
650 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
651 setOperationAction(ISD::VASTART , MVT::Other, Custom);
652 setOperationAction(ISD::VAEND , MVT::Other, Expand);
653 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
654 // TargetInfo::X86_64ABIBuiltinVaList
655 setOperationAction(ISD::VAARG , MVT::Other, Custom);
656 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
657 } else {
658 // TargetInfo::CharPtrBuiltinVaList
659 setOperationAction(ISD::VAARG , MVT::Other, Expand);
660 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
661 }
663 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
664 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
666 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
668 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
669 // f32 and f64 use SSE.
670 // Set up the FP register classes.
671 addRegisterClass(MVT::f32, &X86::FR32RegClass);
672 addRegisterClass(MVT::f64, &X86::FR64RegClass);
674 // Use ANDPD to simulate FABS.
675 setOperationAction(ISD::FABS , MVT::f64, Custom);
676 setOperationAction(ISD::FABS , MVT::f32, Custom);
678 // Use XORP to simulate FNEG.
679 setOperationAction(ISD::FNEG , MVT::f64, Custom);
680 setOperationAction(ISD::FNEG , MVT::f32, Custom);
682 // Use ANDPD and ORPD to simulate FCOPYSIGN.
683 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
684 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
686 // Lower this to FGETSIGNx86 plus an AND.
687 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
688 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
690 // We don't support sin/cos/fmod
691 setOperationAction(ISD::FSIN , MVT::f64, Expand);
692 setOperationAction(ISD::FCOS , MVT::f64, Expand);
693 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
694 setOperationAction(ISD::FSIN , MVT::f32, Expand);
695 setOperationAction(ISD::FCOS , MVT::f32, Expand);
696 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
698 // Expand FP immediates into loads from the stack, except for the special
699 // cases we handle.
700 addLegalFPImmediate(APFloat(+0.0)); // xorpd
701 addLegalFPImmediate(APFloat(+0.0f)); // xorps
702 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
703 // Use SSE for f32, x87 for f64.
704 // Set up the FP register classes.
705 addRegisterClass(MVT::f32, &X86::FR32RegClass);
706 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
708 // Use ANDPS to simulate FABS.
709 setOperationAction(ISD::FABS , MVT::f32, Custom);
711 // Use XORP to simulate FNEG.
712 setOperationAction(ISD::FNEG , MVT::f32, Custom);
714 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
716 // Use ANDPS and ORPS to simulate FCOPYSIGN.
717 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
718 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
720 // We don't support sin/cos/fmod
721 setOperationAction(ISD::FSIN , MVT::f32, Expand);
722 setOperationAction(ISD::FCOS , MVT::f32, Expand);
723 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
725 // Special cases we handle for FP constants.
726 addLegalFPImmediate(APFloat(+0.0f)); // xorps
727 addLegalFPImmediate(APFloat(+0.0)); // FLD0
728 addLegalFPImmediate(APFloat(+1.0)); // FLD1
729 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
730 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
732 if (!TM.Options.UnsafeFPMath) {
733 setOperationAction(ISD::FSIN , MVT::f64, Expand);
734 setOperationAction(ISD::FCOS , MVT::f64, Expand);
735 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
736 }
737 } else if (!TM.Options.UseSoftFloat) {
738 // f32 and f64 in x87.
739 // Set up the FP register classes.
740 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
741 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
743 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
744 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
745 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
746 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
748 if (!TM.Options.UnsafeFPMath) {
749 setOperationAction(ISD::FSIN , MVT::f64, Expand);
750 setOperationAction(ISD::FSIN , MVT::f32, Expand);
751 setOperationAction(ISD::FCOS , MVT::f64, Expand);
752 setOperationAction(ISD::FCOS , MVT::f32, Expand);
753 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
754 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
755 }
756 addLegalFPImmediate(APFloat(+0.0)); // FLD0
757 addLegalFPImmediate(APFloat(+1.0)); // FLD1
758 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
759 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
760 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
761 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
762 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
763 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
764 }
766 // We don't support FMA.
767 setOperationAction(ISD::FMA, MVT::f64, Expand);
768 setOperationAction(ISD::FMA, MVT::f32, Expand);
770 // Long double always uses X87.
771 if (!TM.Options.UseSoftFloat) {
772 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
773 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
774 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
775 {
776 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
777 addLegalFPImmediate(TmpFlt); // FLD0
778 TmpFlt.changeSign();
779 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
781 bool ignored;
782 APFloat TmpFlt2(+1.0);
783 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
784 &ignored);
785 addLegalFPImmediate(TmpFlt2); // FLD1
786 TmpFlt2.changeSign();
787 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
788 }
790 if (!TM.Options.UnsafeFPMath) {
791 setOperationAction(ISD::FSIN , MVT::f80, Expand);
792 setOperationAction(ISD::FCOS , MVT::f80, Expand);
793 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
794 }
796 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
797 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
798 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
799 setOperationAction(ISD::FRINT, MVT::f80, Expand);
800 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
801 setOperationAction(ISD::FMA, MVT::f80, Expand);
802 }
804 // Always use a library call for pow.
805 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
806 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
807 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
809 setOperationAction(ISD::FLOG, MVT::f80, Expand);
810 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
811 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
812 setOperationAction(ISD::FEXP, MVT::f80, Expand);
813 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
815 // First set operation action for all vector types to either promote
816 // (for widening) or expand (for scalarization). Then we will selectively
817 // turn on ones that can be effectively codegen'd.
818 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
819 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
820 MVT VT = (MVT::SimpleValueType)i;
821 setOperationAction(ISD::ADD , VT, Expand);
822 setOperationAction(ISD::SUB , VT, Expand);
823 setOperationAction(ISD::FADD, VT, Expand);
824 setOperationAction(ISD::FNEG, VT, Expand);
825 setOperationAction(ISD::FSUB, VT, Expand);
826 setOperationAction(ISD::MUL , VT, Expand);
827 setOperationAction(ISD::FMUL, VT, Expand);
828 setOperationAction(ISD::SDIV, VT, Expand);
829 setOperationAction(ISD::UDIV, VT, Expand);
830 setOperationAction(ISD::FDIV, VT, Expand);
831 setOperationAction(ISD::SREM, VT, Expand);
832 setOperationAction(ISD::UREM, VT, Expand);
833 setOperationAction(ISD::LOAD, VT, Expand);
834 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
835 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
836 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
837 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
838 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
839 setOperationAction(ISD::FABS, VT, Expand);
840 setOperationAction(ISD::FSIN, VT, Expand);
841 setOperationAction(ISD::FSINCOS, VT, Expand);
842 setOperationAction(ISD::FCOS, VT, Expand);
843 setOperationAction(ISD::FSINCOS, VT, Expand);
844 setOperationAction(ISD::FREM, VT, Expand);
845 setOperationAction(ISD::FMA, VT, Expand);
846 setOperationAction(ISD::FPOWI, VT, Expand);
847 setOperationAction(ISD::FSQRT, VT, Expand);
848 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
849 setOperationAction(ISD::FFLOOR, VT, Expand);
850 setOperationAction(ISD::FCEIL, VT, Expand);
851 setOperationAction(ISD::FTRUNC, VT, Expand);
852 setOperationAction(ISD::FRINT, VT, Expand);
853 setOperationAction(ISD::FNEARBYINT, VT, Expand);
854 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
855 setOperationAction(ISD::MULHS, VT, Expand);
856 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
857 setOperationAction(ISD::MULHU, VT, Expand);
858 setOperationAction(ISD::SDIVREM, VT, Expand);
859 setOperationAction(ISD::UDIVREM, VT, Expand);
860 setOperationAction(ISD::FPOW, VT, Expand);
861 setOperationAction(ISD::CTPOP, VT, Expand);
862 setOperationAction(ISD::CTTZ, VT, Expand);
863 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
864 setOperationAction(ISD::CTLZ, VT, Expand);
865 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
866 setOperationAction(ISD::SHL, VT, Expand);
867 setOperationAction(ISD::SRA, VT, Expand);
868 setOperationAction(ISD::SRL, VT, Expand);
869 setOperationAction(ISD::ROTL, VT, Expand);
870 setOperationAction(ISD::ROTR, VT, Expand);
871 setOperationAction(ISD::BSWAP, VT, Expand);
872 setOperationAction(ISD::SETCC, VT, Expand);
873 setOperationAction(ISD::FLOG, VT, Expand);
874 setOperationAction(ISD::FLOG2, VT, Expand);
875 setOperationAction(ISD::FLOG10, VT, Expand);
876 setOperationAction(ISD::FEXP, VT, Expand);
877 setOperationAction(ISD::FEXP2, VT, Expand);
878 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
879 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
880 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
881 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
882 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
883 setOperationAction(ISD::TRUNCATE, VT, Expand);
884 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
885 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
886 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
887 setOperationAction(ISD::VSELECT, VT, Expand);
888 setOperationAction(ISD::SELECT_CC, VT, Expand);
889 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
890 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
891 setTruncStoreAction(VT,
892 (MVT::SimpleValueType)InnerVT, Expand);
893 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
894 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
896 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
897 // we have to deal with them whether we ask for Expansion or not. Setting
898 // Expand causes its own optimisation problems though, so leave them legal.
899 if (VT.getVectorElementType() == MVT::i1)
900 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
901 }
903 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
904 // with -msoft-float, disable use of MMX as well.
905 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
906 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
907 // No operations on x86mmx supported, everything uses intrinsics.
908 }
910 // MMX-sized vectors (other than x86mmx) are expected to be expanded
911 // into smaller operations.
912 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
913 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
914 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
915 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
916 setOperationAction(ISD::AND, MVT::v8i8, Expand);
917 setOperationAction(ISD::AND, MVT::v4i16, Expand);
918 setOperationAction(ISD::AND, MVT::v2i32, Expand);
919 setOperationAction(ISD::AND, MVT::v1i64, Expand);
920 setOperationAction(ISD::OR, MVT::v8i8, Expand);
921 setOperationAction(ISD::OR, MVT::v4i16, Expand);
922 setOperationAction(ISD::OR, MVT::v2i32, Expand);
923 setOperationAction(ISD::OR, MVT::v1i64, Expand);
924 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
925 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
926 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
927 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
928 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
929 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
930 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
931 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
932 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
933 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
934 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
935 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
936 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
937 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
938 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
939 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
940 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
942 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
943 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
945 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
946 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
947 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
948 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
949 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
950 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
951 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
952 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
953 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
954 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
955 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
956 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
957 }
959 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
960 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
962 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
963 // registers cannot be used even for integer operations.
964 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
965 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
966 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
967 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
969 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
970 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
971 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
972 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
973 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
974 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
975 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
976 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
977 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
978 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
979 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
980 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
981 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
982 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
983 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
984 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
985 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
986 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
987 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
988 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
989 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
990 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
992 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
993 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
994 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
995 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
997 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
998 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
999 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1000 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1001 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1003 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
1004 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1005 MVT VT = (MVT::SimpleValueType)i;
1006 // Do not attempt to custom lower non-power-of-2 vectors
1007 if (!isPowerOf2_32(VT.getVectorNumElements()))
1008 continue;
1009 // Do not attempt to custom lower non-128-bit vectors
1010 if (!VT.is128BitVector())
1011 continue;
1012 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1013 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1014 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1015 }
1017 // We support custom legalizing of sext and anyext loads for specific
1018 // memory vector types which we can load as a scalar (or sequence of
1019 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1020 // loads these must work with a single scalar load.
1021 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1022 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1023 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1024 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1025 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1026 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1027 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1028 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1029 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1031 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1032 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1033 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1034 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1035 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1036 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1038 if (Subtarget->is64Bit()) {
1039 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1040 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1041 }
1043 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1044 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1045 MVT VT = (MVT::SimpleValueType)i;
1047 // Do not attempt to promote non-128-bit vectors
1048 if (!VT.is128BitVector())
1049 continue;
1051 setOperationAction(ISD::AND, VT, Promote);
1052 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1053 setOperationAction(ISD::OR, VT, Promote);
1054 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1055 setOperationAction(ISD::XOR, VT, Promote);
1056 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1057 setOperationAction(ISD::LOAD, VT, Promote);
1058 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1059 setOperationAction(ISD::SELECT, VT, Promote);
1060 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1061 }
1063 // Custom lower v2i64 and v2f64 selects.
1064 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1065 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1066 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1067 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1069 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1070 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1072 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1073 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1074 // As there is no 64-bit GPR available, we need build a special custom
1075 // sequence to convert from v2i32 to v2f32.
1076 if (!Subtarget->is64Bit())
1077 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1079 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1080 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1082 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1084 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1085 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1086 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1087 }
1089 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1090 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1091 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1092 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1093 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1094 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1095 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1096 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1097 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1098 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1099 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1101 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1102 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1103 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1104 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1105 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1106 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1107 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1108 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1109 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1110 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1112 // FIXME: Do we need to handle scalar-to-vector here?
1113 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1115 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1116 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1117 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1118 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1119 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1120 // There is no BLENDI for byte vectors. We don't need to custom lower
1121 // some vselects for now.
1122 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1124 // SSE41 brings specific instructions for doing vector sign extend even in
1125 // cases where we don't have SRA.
1126 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1127 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1128 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1130 // i8 and i16 vectors are custom because the source register and source
1131 // source memory operand types are not the same width. f32 vectors are
1132 // custom since the immediate controlling the insert encodes additional
1133 // information.
1134 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1135 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1136 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1137 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1139 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1140 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1141 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1142 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1144 // FIXME: these should be Legal, but that's only for the case where
1145 // the index is constant. For now custom expand to deal with that.
1146 if (Subtarget->is64Bit()) {
1147 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1148 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1149 }
1150 }
1152 if (Subtarget->hasSSE2()) {
1153 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1154 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1156 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1157 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1159 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1160 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1162 // In the customized shift lowering, the legal cases in AVX2 will be
1163 // recognized.
1164 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1165 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1167 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1168 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1170 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1171 }
1173 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1174 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1175 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1176 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1177 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1178 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1179 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1181 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1182 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1183 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1185 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1186 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1187 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1188 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1189 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1190 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1191 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1192 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1193 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1194 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1195 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1196 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1198 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1199 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1200 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1201 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1202 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1203 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1204 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1205 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1206 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1207 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1208 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1209 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1211 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1212 // even though v8i16 is a legal type.
1213 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1214 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1215 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1217 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1218 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1219 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1221 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1222 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1224 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1226 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1227 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1229 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1230 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1232 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1233 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1235 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1236 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1237 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1238 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1240 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1241 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1242 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1244 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1245 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1246 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1247 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1249 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1250 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1251 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1252 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1253 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1254 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1255 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1256 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1257 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1258 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1259 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1260 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1262 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1263 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1264 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1265 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1266 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1267 setOperationAction(ISD::FMA, MVT::f32, Legal);
1268 setOperationAction(ISD::FMA, MVT::f64, Legal);
1269 }
1271 if (Subtarget->hasInt256()) {
1272 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1273 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1274 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1275 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1277 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1278 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1279 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1280 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1282 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1283 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1284 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1285 // Don't lower v32i8 because there is no 128-bit byte mul
1287 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1288 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1289 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1290 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1292 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1293 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1294 } else {
1295 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1296 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1297 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1298 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1300 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1301 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1302 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1303 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1305 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1306 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1307 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1308 // Don't lower v32i8 because there is no 128-bit byte mul
1309 }
1311 // In the customized shift lowering, the legal cases in AVX2 will be
1312 // recognized.
1313 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1314 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1316 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1317 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1319 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1321 // Custom lower several nodes for 256-bit types.
1322 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1323 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1324 MVT VT = (MVT::SimpleValueType)i;
1326 // Extract subvector is special because the value type
1327 // (result) is 128-bit but the source is 256-bit wide.
1328 if (VT.is128BitVector())
1329 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1331 // Do not attempt to custom lower other non-256-bit vectors
1332 if (!VT.is256BitVector())
1333 continue;
1335 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1336 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1337 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1338 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1339 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1340 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1341 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1342 }
1344 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1345 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1346 MVT VT = (MVT::SimpleValueType)i;
1348 // Do not attempt to promote non-256-bit vectors
1349 if (!VT.is256BitVector())
1350 continue;
1352 setOperationAction(ISD::AND, VT, Promote);
1353 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1354 setOperationAction(ISD::OR, VT, Promote);
1355 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1356 setOperationAction(ISD::XOR, VT, Promote);
1357 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1358 setOperationAction(ISD::LOAD, VT, Promote);
1359 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1360 setOperationAction(ISD::SELECT, VT, Promote);
1361 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1362 }
1363 }
1365 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1366 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1367 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1368 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1369 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1371 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1372 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1373 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1375 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1376 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1377 setOperationAction(ISD::XOR, MVT::i1, Legal);
1378 setOperationAction(ISD::OR, MVT::i1, Legal);
1379 setOperationAction(ISD::AND, MVT::i1, Legal);
1380 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1381 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1382 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1383 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1384 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1385 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1387 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1388 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1389 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1390 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1391 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1392 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1394 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1395 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1396 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1397 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1398 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1399 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1400 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1401 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1403 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1404 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1405 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1406 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1407 if (Subtarget->is64Bit()) {
1408 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1409 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1410 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1411 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1412 }
1413 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1414 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1415 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1416 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1417 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1418 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1419 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1420 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1421 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1422 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1424 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1425 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1426 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1427 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1428 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1429 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1430 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1431 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1432 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1433 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1434 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1438 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1439 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1440 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1441 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1442 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1443 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1445 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1446 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1448 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1450 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1451 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1452 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1453 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1454 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1455 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1456 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1457 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1458 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1460 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1461 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1463 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1464 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1466 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1468 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1469 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1471 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1472 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1474 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1475 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1477 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1478 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1479 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1480 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1481 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1482 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1484 if (Subtarget->hasCDI()) {
1485 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1486 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1487 }
1489 // Custom lower several nodes.
1490 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1491 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1492 MVT VT = (MVT::SimpleValueType)i;
1494 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1495 // Extract subvector is special because the value type
1496 // (result) is 256/128-bit but the source is 512-bit wide.
1497 if (VT.is128BitVector() || VT.is256BitVector())
1498 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1500 if (VT.getVectorElementType() == MVT::i1)
1501 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1503 // Do not attempt to custom lower other non-512-bit vectors
1504 if (!VT.is512BitVector())
1505 continue;
1507 if ( EltSize >= 32) {
1508 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1509 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1510 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1511 setOperationAction(ISD::VSELECT, VT, Legal);
1512 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1513 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1514 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1515 }
1516 }
1517 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1518 MVT VT = (MVT::SimpleValueType)i;
1520 // Do not attempt to promote non-256-bit vectors
1521 if (!VT.is512BitVector())
1522 continue;
1524 setOperationAction(ISD::SELECT, VT, Promote);
1525 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1526 }
1527 }// has AVX-512
1529 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1530 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1531 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1533 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1534 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1536 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1537 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1538 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1539 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1541 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1542 const MVT VT = (MVT::SimpleValueType)i;
1544 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1546 // Do not attempt to promote non-256-bit vectors
1547 if (!VT.is512BitVector())
1548 continue;
1550 if ( EltSize < 32) {
1551 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1552 setOperationAction(ISD::VSELECT, VT, Legal);
1553 }
1554 }
1555 }
1557 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1558 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1559 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1561 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1562 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1563 }
1565 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1566 // of this type with custom code.
1567 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1568 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1569 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1570 Custom);
1571 }
1573 // We want to custom lower some of our intrinsics.
1574 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1575 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1576 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1577 if (!Subtarget->is64Bit())
1578 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1580 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1581 // handle type legalization for these operations here.
1582 //
1583 // FIXME: We really should do custom legalization for addition and
1584 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1585 // than generic legalization for 64-bit multiplication-with-overflow, though.
1586 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1587 // Add/Sub/Mul with overflow operations are custom lowered.
1588 MVT VT = IntVTs[i];
1589 setOperationAction(ISD::SADDO, VT, Custom);
1590 setOperationAction(ISD::UADDO, VT, Custom);
1591 setOperationAction(ISD::SSUBO, VT, Custom);
1592 setOperationAction(ISD::USUBO, VT, Custom);
1593 setOperationAction(ISD::SMULO, VT, Custom);
1594 setOperationAction(ISD::UMULO, VT, Custom);
1595 }
1597 // There are no 8-bit 3-address imul/mul instructions
1598 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1599 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1601 if (!Subtarget->is64Bit()) {
1602 // These libcalls are not available in 32-bit.
1603 setLibcallName(RTLIB::SHL_I128, nullptr);
1604 setLibcallName(RTLIB::SRL_I128, nullptr);
1605 setLibcallName(RTLIB::SRA_I128, nullptr);
1606 }
1608 // Combine sin / cos into one node or libcall if possible.
1609 if (Subtarget->hasSinCos()) {
1610 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1611 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1612 if (Subtarget->isTargetDarwin()) {
1613 // For MacOSX, we don't want to the normal expansion of a libcall to
1614 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1615 // traffic.
1616 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1617 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1618 }
1619 }
1621 if (Subtarget->isTargetWin64()) {
1622 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1623 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1624 setOperationAction(ISD::SREM, MVT::i128, Custom);
1625 setOperationAction(ISD::UREM, MVT::i128, Custom);
1626 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1627 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1628 }
1630 // We have target-specific dag combine patterns for the following nodes:
1631 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1632 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1633 setTargetDAGCombine(ISD::VSELECT);
1634 setTargetDAGCombine(ISD::SELECT);
1635 setTargetDAGCombine(ISD::SHL);
1636 setTargetDAGCombine(ISD::SRA);
1637 setTargetDAGCombine(ISD::SRL);
1638 setTargetDAGCombine(ISD::OR);
1639 setTargetDAGCombine(ISD::AND);
1640 setTargetDAGCombine(ISD::ADD);
1641 setTargetDAGCombine(ISD::FADD);
1642 setTargetDAGCombine(ISD::FSUB);
1643 setTargetDAGCombine(ISD::FMA);
1644 setTargetDAGCombine(ISD::SUB);
1645 setTargetDAGCombine(ISD::LOAD);
1646 setTargetDAGCombine(ISD::STORE);
1647 setTargetDAGCombine(ISD::ZERO_EXTEND);
1648 setTargetDAGCombine(ISD::ANY_EXTEND);
1649 setTargetDAGCombine(ISD::SIGN_EXTEND);
1650 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1651 setTargetDAGCombine(ISD::TRUNCATE);
1652 setTargetDAGCombine(ISD::SINT_TO_FP);
1653 setTargetDAGCombine(ISD::SETCC);
1654 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1655 setTargetDAGCombine(ISD::BUILD_VECTOR);
1656 if (Subtarget->is64Bit())
1657 setTargetDAGCombine(ISD::MUL);
1658 setTargetDAGCombine(ISD::XOR);
1660 computeRegisterProperties();
1662 // On Darwin, -Os means optimize for size without hurting performance,
1663 // do not reduce the limit.
1664 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1665 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1666 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1667 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1668 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1669 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1670 setPrefLoopAlignment(4); // 2^4 bytes.
1672 // Predictable cmov don't hurt on atom because it's in-order.
1673 PredictableSelectIsExpensive = !Subtarget->isAtom();
1675 setPrefFunctionAlignment(4); // 2^4 bytes.
1677 verifyIntrinsicTables();
1678 }
1680 // This has so far only been implemented for 64-bit MachO.
1681 bool X86TargetLowering::useLoadStackGuardNode() const {
1682 return Subtarget->getTargetTriple().getObjectFormat() == Triple::MachO &&
1683 Subtarget->is64Bit();
1684 }
1686 TargetLoweringBase::LegalizeTypeAction
1687 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1688 if (ExperimentalVectorWideningLegalization &&
1689 VT.getVectorNumElements() != 1 &&
1690 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1691 return TypeWidenVector;
1693 return TargetLoweringBase::getPreferredVectorAction(VT);
1694 }
1696 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1697 if (!VT.isVector())
1698 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1700 const unsigned NumElts = VT.getVectorNumElements();
1701 const EVT EltVT = VT.getVectorElementType();
1702 if (VT.is512BitVector()) {
1703 if (Subtarget->hasAVX512())
1704 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1705 EltVT == MVT::f32 || EltVT == MVT::f64)
1706 switch(NumElts) {
1707 case 8: return MVT::v8i1;
1708 case 16: return MVT::v16i1;
1709 }
1710 if (Subtarget->hasBWI())
1711 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1712 switch(NumElts) {
1713 case 32: return MVT::v32i1;
1714 case 64: return MVT::v64i1;
1715 }
1716 }
1718 if (VT.is256BitVector() || VT.is128BitVector()) {
1719 if (Subtarget->hasVLX())
1720 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1721 EltVT == MVT::f32 || EltVT == MVT::f64)
1722 switch(NumElts) {
1723 case 2: return MVT::v2i1;
1724 case 4: return MVT::v4i1;
1725 case 8: return MVT::v8i1;
1726 }
1727 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1728 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1729 switch(NumElts) {
1730 case 8: return MVT::v8i1;
1731 case 16: return MVT::v16i1;
1732 case 32: return MVT::v32i1;
1733 }
1734 }
1736 return VT.changeVectorElementTypeToInteger();
1737 }
1739 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1740 /// the desired ByVal argument alignment.
1741 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1742 if (MaxAlign == 16)
1743 return;
1744 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1745 if (VTy->getBitWidth() == 128)
1746 MaxAlign = 16;
1747 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1748 unsigned EltAlign = 0;
1749 getMaxByValAlign(ATy->getElementType(), EltAlign);
1750 if (EltAlign > MaxAlign)
1751 MaxAlign = EltAlign;
1752 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1753 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1754 unsigned EltAlign = 0;
1755 getMaxByValAlign(STy->getElementType(i), EltAlign);
1756 if (EltAlign > MaxAlign)
1757 MaxAlign = EltAlign;
1758 if (MaxAlign == 16)
1759 break;
1760 }
1761 }
1762 }
1764 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1765 /// function arguments in the caller parameter area. For X86, aggregates
1766 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1767 /// are at 4-byte boundaries.
1768 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1769 if (Subtarget->is64Bit()) {
1770 // Max of 8 and alignment of type.
1771 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1772 if (TyAlign > 8)
1773 return TyAlign;
1774 return 8;
1775 }
1777 unsigned Align = 4;
1778 if (Subtarget->hasSSE1())
1779 getMaxByValAlign(Ty, Align);
1780 return Align;
1781 }
1783 /// getOptimalMemOpType - Returns the target specific optimal type for load
1784 /// and store operations as a result of memset, memcpy, and memmove
1785 /// lowering. If DstAlign is zero that means it's safe to destination
1786 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1787 /// means there isn't a need to check it against alignment requirement,
1788 /// probably because the source does not need to be loaded. If 'IsMemset' is
1789 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1790 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1791 /// source is constant so it does not need to be loaded.
1792 /// It returns EVT::Other if the type should be determined using generic
1793 /// target-independent logic.
1794 EVT
1795 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1796 unsigned DstAlign, unsigned SrcAlign,
1797 bool IsMemset, bool ZeroMemset,
1798 bool MemcpyStrSrc,
1799 MachineFunction &MF) const {
1800 const Function *F = MF.getFunction();
1801 if ((!IsMemset || ZeroMemset) &&
1802 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1803 Attribute::NoImplicitFloat)) {
1804 if (Size >= 16 &&
1805 (Subtarget->isUnalignedMemAccessFast() ||
1806 ((DstAlign == 0 || DstAlign >= 16) &&
1807 (SrcAlign == 0 || SrcAlign >= 16)))) {
1808 if (Size >= 32) {
1809 if (Subtarget->hasInt256())
1810 return MVT::v8i32;
1811 if (Subtarget->hasFp256())
1812 return MVT::v8f32;
1813 }
1814 if (Subtarget->hasSSE2())
1815 return MVT::v4i32;
1816 if (Subtarget->hasSSE1())
1817 return MVT::v4f32;
1818 } else if (!MemcpyStrSrc && Size >= 8 &&
1819 !Subtarget->is64Bit() &&
1820 Subtarget->hasSSE2()) {
1821 // Do not use f64 to lower memcpy if source is string constant. It's
1822 // better to use i32 to avoid the loads.
1823 return MVT::f64;
1824 }
1825 }
1826 if (Subtarget->is64Bit() && Size >= 8)
1827 return MVT::i64;
1828 return MVT::i32;
1829 }
1831 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1832 if (VT == MVT::f32)
1833 return X86ScalarSSEf32;
1834 else if (VT == MVT::f64)
1835 return X86ScalarSSEf64;
1836 return true;
1837 }
1839 bool
1840 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1841 unsigned,
1842 unsigned,
1843 bool *Fast) const {
1844 if (Fast)
1845 *Fast = Subtarget->isUnalignedMemAccessFast();
1846 return true;
1847 }
1849 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1850 /// current function. The returned value is a member of the
1851 /// MachineJumpTableInfo::JTEntryKind enum.
1852 unsigned X86TargetLowering::getJumpTableEncoding() const {
1853 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1854 // symbol.
1855 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1856 Subtarget->isPICStyleGOT())
1857 return MachineJumpTableInfo::EK_Custom32;
1859 // Otherwise, use the normal jump table encoding heuristics.
1860 return TargetLowering::getJumpTableEncoding();
1861 }
1863 const MCExpr *
1864 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1865 const MachineBasicBlock *MBB,
1866 unsigned uid,MCContext &Ctx) const{
1867 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1868 Subtarget->isPICStyleGOT());
1869 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1870 // entries.
1871 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1872 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1873 }
1875 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1876 /// jumptable.
1877 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1878 SelectionDAG &DAG) const {
1879 if (!Subtarget->is64Bit())
1880 // This doesn't have SDLoc associated with it, but is not really the
1881 // same as a Register.
1882 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1883 return Table;
1884 }
1886 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1887 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1888 /// MCExpr.
1889 const MCExpr *X86TargetLowering::
1890 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1891 MCContext &Ctx) const {
1892 // X86-64 uses RIP relative addressing based on the jump table label.
1893 if (Subtarget->isPICStyleRIPRel())
1894 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1896 // Otherwise, the reference is relative to the PIC base.
1897 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1898 }
1900 // FIXME: Why this routine is here? Move to RegInfo!
1901 std::pair<const TargetRegisterClass*, uint8_t>
1902 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1903 const TargetRegisterClass *RRC = nullptr;
1904 uint8_t Cost = 1;
1905 switch (VT.SimpleTy) {
1906 default:
1907 return TargetLowering::findRepresentativeClass(VT);
1908 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1909 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1910 break;
1911 case MVT::x86mmx:
1912 RRC = &X86::VR64RegClass;
1913 break;
1914 case MVT::f32: case MVT::f64:
1915 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1916 case MVT::v4f32: case MVT::v2f64:
1917 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1918 case MVT::v4f64:
1919 RRC = &X86::VR128RegClass;
1920 break;
1921 }
1922 return std::make_pair(RRC, Cost);
1923 }
1925 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1926 unsigned &Offset) const {
1927 if (!Subtarget->isTargetLinux())
1928 return false;
1930 if (Subtarget->is64Bit()) {
1931 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1932 Offset = 0x28;
1933 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1934 AddressSpace = 256;
1935 else
1936 AddressSpace = 257;
1937 } else {
1938 // %gs:0x14 on i386
1939 Offset = 0x14;
1940 AddressSpace = 256;
1941 }
1942 return true;
1943 }
1945 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1946 unsigned DestAS) const {
1947 assert(SrcAS != DestAS && "Expected different address spaces!");
1949 return SrcAS < 256 && DestAS < 256;
1950 }
1952 //===----------------------------------------------------------------------===//
1953 // Return Value Calling Convention Implementation
1954 //===----------------------------------------------------------------------===//
1956 #include "X86GenCallingConv.inc"
1958 bool
1959 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1960 MachineFunction &MF, bool isVarArg,
1961 const SmallVectorImpl<ISD::OutputArg> &Outs,
1962 LLVMContext &Context) const {
1963 SmallVector<CCValAssign, 16> RVLocs;
1964 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1965 return CCInfo.CheckReturn(Outs, RetCC_X86);
1966 }
1968 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1969 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1970 return ScratchRegs;
1971 }
1973 SDValue
1974 X86TargetLowering::LowerReturn(SDValue Chain,
1975 CallingConv::ID CallConv, bool isVarArg,
1976 const SmallVectorImpl<ISD::OutputArg> &Outs,
1977 const SmallVectorImpl<SDValue> &OutVals,
1978 SDLoc dl, SelectionDAG &DAG) const {
1979 MachineFunction &MF = DAG.getMachineFunction();
1980 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1982 SmallVector<CCValAssign, 16> RVLocs;
1983 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1984 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1986 SDValue Flag;
1987 SmallVector<SDValue, 6> RetOps;
1988 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1989 // Operand #1 = Bytes To Pop
1990 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1991 MVT::i16));
1993 // Copy the result values into the output registers.
1994 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1995 CCValAssign &VA = RVLocs[i];
1996 assert(VA.isRegLoc() && "Can only return in registers!");
1997 SDValue ValToCopy = OutVals[i];
1998 EVT ValVT = ValToCopy.getValueType();
2000 // Promote values to the appropriate types
2001 if (VA.getLocInfo() == CCValAssign::SExt)
2002 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2003 else if (VA.getLocInfo() == CCValAssign::ZExt)
2004 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2005 else if (VA.getLocInfo() == CCValAssign::AExt)
2006 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2007 else if (VA.getLocInfo() == CCValAssign::BCvt)
2008 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2010 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2011 "Unexpected FP-extend for return value.");
2013 // If this is x86-64, and we disabled SSE, we can't return FP values,
2014 // or SSE or MMX vectors.
2015 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2016 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2017 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2018 report_fatal_error("SSE register return with SSE disabled");
2019 }
2020 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2021 // llvm-gcc has never done it right and no one has noticed, so this
2022 // should be OK for now.
2023 if (ValVT == MVT::f64 &&
2024 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2025 report_fatal_error("SSE2 register return with SSE2 disabled");
2027 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2028 // the RET instruction and handled by the FP Stackifier.
2029 if (VA.getLocReg() == X86::FP0 ||
2030 VA.getLocReg() == X86::FP1) {
2031 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2032 // change the value to the FP stack register class.
2033 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2034 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2035 RetOps.push_back(ValToCopy);
2036 // Don't emit a copytoreg.
2037 continue;
2038 }
2040 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2041 // which is returned in RAX / RDX.
2042 if (Subtarget->is64Bit()) {
2043 if (ValVT == MVT::x86mmx) {
2044 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2045 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2046 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2047 ValToCopy);
2048 // If we don't have SSE2 available, convert to v4f32 so the generated
2049 // register is legal.
2050 if (!Subtarget->hasSSE2())
2051 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2052 }
2053 }
2054 }
2056 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2057 Flag = Chain.getValue(1);
2058 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2059 }
2061 // The x86-64 ABIs require that for returning structs by value we copy
2062 // the sret argument into %rax/%eax (depending on ABI) for the return.
2063 // Win32 requires us to put the sret argument to %eax as well.
2064 // We saved the argument into a virtual register in the entry block,
2065 // so now we copy the value out and into %rax/%eax.
2066 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2067 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2068 MachineFunction &MF = DAG.getMachineFunction();
2069 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2070 unsigned Reg = FuncInfo->getSRetReturnReg();
2071 assert(Reg &&
2072 "SRetReturnReg should have been set in LowerFormalArguments().");
2073 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2075 unsigned RetValReg
2076 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2077 X86::RAX : X86::EAX;
2078 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2079 Flag = Chain.getValue(1);
2081 // RAX/EAX now acts like a return value.
2082 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2083 }
2085 RetOps[0] = Chain; // Update chain.
2087 // Add the flag if we have it.
2088 if (Flag.getNode())
2089 RetOps.push_back(Flag);
2091 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2092 }
2094 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2095 if (N->getNumValues() != 1)
2096 return false;
2097 if (!N->hasNUsesOfValue(1, 0))
2098 return false;
2100 SDValue TCChain = Chain;
2101 SDNode *Copy = *N->use_begin();
2102 if (Copy->getOpcode() == ISD::CopyToReg) {
2103 // If the copy has a glue operand, we conservatively assume it isn't safe to
2104 // perform a tail call.
2105 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2106 return false;
2107 TCChain = Copy->getOperand(0);
2108 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2109 return false;
2111 bool HasRet = false;
2112 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2113 UI != UE; ++UI) {
2114 if (UI->getOpcode() != X86ISD::RET_FLAG)
2115 return false;
2116 // If we are returning more than one value, we can definitely
2117 // not make a tail call see PR19530
2118 if (UI->getNumOperands() > 4)
2119 return false;
2120 if (UI->getNumOperands() == 4 &&
2121 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2122 return false;
2123 HasRet = true;
2124 }
2126 if (!HasRet)
2127 return false;
2129 Chain = TCChain;
2130 return true;
2131 }
2133 EVT
2134 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2135 ISD::NodeType ExtendKind) const {
2136 MVT ReturnMVT;
2137 // TODO: Is this also valid on 32-bit?
2138 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2139 ReturnMVT = MVT::i8;
2140 else
2141 ReturnMVT = MVT::i32;
2143 EVT MinVT = getRegisterType(Context, ReturnMVT);
2144 return VT.bitsLT(MinVT) ? MinVT : VT;
2145 }
2147 /// LowerCallResult - Lower the result values of a call into the
2148 /// appropriate copies out of appropriate physical registers.
2149 ///
2150 SDValue
2151 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2152 CallingConv::ID CallConv, bool isVarArg,
2153 const SmallVectorImpl<ISD::InputArg> &Ins,
2154 SDLoc dl, SelectionDAG &DAG,
2155 SmallVectorImpl<SDValue> &InVals) const {
2157 // Assign locations to each value returned by this call.
2158 SmallVector<CCValAssign, 16> RVLocs;
2159 bool Is64Bit = Subtarget->is64Bit();
2160 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2161 *DAG.getContext());
2162 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2164 // Copy all of the result registers out of their specified physreg.
2165 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2166 CCValAssign &VA = RVLocs[i];
2167 EVT CopyVT = VA.getValVT();
2169 // If this is x86-64, and we disabled SSE, we can't return FP values
2170 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2171 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2172 report_fatal_error("SSE register return with SSE disabled");
2173 }
2175 // If we prefer to use the value in xmm registers, copy it out as f80 and
2176 // use a truncate to move it from fp stack reg to xmm reg.
2177 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2178 isScalarFPTypeInSSEReg(VA.getValVT()))
2179 CopyVT = MVT::f80;
2181 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2182 CopyVT, InFlag).getValue(1);
2183 SDValue Val = Chain.getValue(0);
2185 if (CopyVT != VA.getValVT())
2186 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2187 // This truncation won't change the value.
2188 DAG.getIntPtrConstant(1));
2190 InFlag = Chain.getValue(2);
2191 InVals.push_back(Val);
2192 }
2194 return Chain;
2195 }
2197 //===----------------------------------------------------------------------===//
2198 // C & StdCall & Fast Calling Convention implementation
2199 //===----------------------------------------------------------------------===//
2200 // StdCall calling convention seems to be standard for many Windows' API
2201 // routines and around. It differs from C calling convention just a little:
2202 // callee should clean up the stack, not caller. Symbols should be also
2203 // decorated in some fancy way :) It doesn't support any vector arguments.
2204 // For info on fast calling convention see Fast Calling Convention (tail call)
2205 // implementation LowerX86_32FastCCCallTo.
2207 /// CallIsStructReturn - Determines whether a call uses struct return
2208 /// semantics.
2209 enum StructReturnType {
2210 NotStructReturn,
2211 RegStructReturn,
2212 StackStructReturn
2213 };
2214 static StructReturnType
2215 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2216 if (Outs.empty())
2217 return NotStructReturn;
2219 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2220 if (!Flags.isSRet())
2221 return NotStructReturn;
2222 if (Flags.isInReg())
2223 return RegStructReturn;
2224 return StackStructReturn;
2225 }
2227 /// ArgsAreStructReturn - Determines whether a function uses struct
2228 /// return semantics.
2229 static StructReturnType
2230 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2231 if (Ins.empty())
2232 return NotStructReturn;
2234 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2235 if (!Flags.isSRet())
2236 return NotStructReturn;
2237 if (Flags.isInReg())
2238 return RegStructReturn;
2239 return StackStructReturn;
2240 }
2242 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2243 /// by "Src" to address "Dst" with size and alignment information specified by
2244 /// the specific parameter attribute. The copy will be passed as a byval
2245 /// function parameter.
2246 static SDValue
2247 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2248 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2249 SDLoc dl) {
2250 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2252 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2253 /*isVolatile*/false, /*AlwaysInline=*/true,
2254 MachinePointerInfo(), MachinePointerInfo());
2255 }
2257 /// IsTailCallConvention - Return true if the calling convention is one that
2258 /// supports tail call optimization.
2259 static bool IsTailCallConvention(CallingConv::ID CC) {
2260 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2261 CC == CallingConv::HiPE);
2262 }
2264 /// \brief Return true if the calling convention is a C calling convention.
2265 static bool IsCCallConvention(CallingConv::ID CC) {
2266 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2267 CC == CallingConv::X86_64_SysV);
2268 }
2270 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2271 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2272 return false;
2274 CallSite CS(CI);
2275 CallingConv::ID CalleeCC = CS.getCallingConv();
2276 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2277 return false;
2279 return true;
2280 }
2282 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2283 /// a tailcall target by changing its ABI.
2284 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2285 bool GuaranteedTailCallOpt) {
2286 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2287 }
2289 SDValue
2290 X86TargetLowering::LowerMemArgument(SDValue Chain,
2291 CallingConv::ID CallConv,
2292 const SmallVectorImpl<ISD::InputArg> &Ins,
2293 SDLoc dl, SelectionDAG &DAG,
2294 const CCValAssign &VA,
2295 MachineFrameInfo *MFI,
2296 unsigned i) const {
2297 // Create the nodes corresponding to a load from this parameter slot.
2298 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2299 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2300 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2301 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2302 EVT ValVT;
2304 // If value is passed by pointer we have address passed instead of the value
2305 // itself.
2306 if (VA.getLocInfo() == CCValAssign::Indirect)
2307 ValVT = VA.getLocVT();
2308 else
2309 ValVT = VA.getValVT();
2311 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2312 // changed with more analysis.
2313 // In case of tail call optimization mark all arguments mutable. Since they
2314 // could be overwritten by lowering of arguments in case of a tail call.
2315 if (Flags.isByVal()) {
2316 unsigned Bytes = Flags.getByValSize();
2317 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2318 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2319 return DAG.getFrameIndex(FI, getPointerTy());
2320 } else {
2321 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2322 VA.getLocMemOffset(), isImmutable);
2323 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2324 return DAG.getLoad(ValVT, dl, Chain, FIN,
2325 MachinePointerInfo::getFixedStack(FI),
2326 false, false, false, 0);
2327 }
2328 }
2330 // FIXME: Get this from tablegen.
2331 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2332 const X86Subtarget *Subtarget) {
2333 assert(Subtarget->is64Bit());
2335 if (Subtarget->isCallingConvWin64(CallConv)) {
2336 static const MCPhysReg GPR64ArgRegsWin64[] = {
2337 X86::RCX, X86::RDX, X86::R8, X86::R9
2338 };
2339 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2340 }
2342 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2343 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2344 };
2345 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2346 }
2348 // FIXME: Get this from tablegen.
2349 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2350 CallingConv::ID CallConv,
2351 const X86Subtarget *Subtarget) {
2352 assert(Subtarget->is64Bit());
2353 if (Subtarget->isCallingConvWin64(CallConv)) {
2354 // The XMM registers which might contain var arg parameters are shadowed
2355 // in their paired GPR. So we only need to save the GPR to their home
2356 // slots.
2357 // TODO: __vectorcall will change this.
2358 return None;
2359 }
2361 const Function *Fn = MF.getFunction();
2362 bool NoImplicitFloatOps = Fn->getAttributes().
2363 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2364 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2365 "SSE register cannot be used when SSE is disabled!");
2366 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2367 !Subtarget->hasSSE1())
2368 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2369 // registers.
2370 return None;
2372 static const MCPhysReg XMMArgRegs64Bit[] = {
2373 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2374 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2375 };
2376 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2377 }
2379 SDValue
2380 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2381 CallingConv::ID CallConv,
2382 bool isVarArg,
2383 const SmallVectorImpl<ISD::InputArg> &Ins,
2384 SDLoc dl,
2385 SelectionDAG &DAG,
2386 SmallVectorImpl<SDValue> &InVals)
2387 const {
2388 MachineFunction &MF = DAG.getMachineFunction();
2389 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2391 const Function* Fn = MF.getFunction();
2392 if (Fn->hasExternalLinkage() &&
2393 Subtarget->isTargetCygMing() &&
2394 Fn->getName() == "main")
2395 FuncInfo->setForceFramePointer(true);
2397 MachineFrameInfo *MFI = MF.getFrameInfo();
2398 bool Is64Bit = Subtarget->is64Bit();
2399 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2401 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2402 "Var args not supported with calling convention fastcc, ghc or hipe");
2404 // Assign locations to all of the incoming arguments.
2405 SmallVector<CCValAssign, 16> ArgLocs;
2406 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2408 // Allocate shadow area for Win64
2409 if (IsWin64)
2410 CCInfo.AllocateStack(32, 8);
2412 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2414 unsigned LastVal = ~0U;
2415 SDValue ArgValue;
2416 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2417 CCValAssign &VA = ArgLocs[i];
2418 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2419 // places.
2420 assert(VA.getValNo() != LastVal &&
2421 "Don't support value assigned to multiple locs yet");
2422 (void)LastVal;
2423 LastVal = VA.getValNo();
2425 if (VA.isRegLoc()) {
2426 EVT RegVT = VA.getLocVT();
2427 const TargetRegisterClass *RC;
2428 if (RegVT == MVT::i32)
2429 RC = &X86::GR32RegClass;
2430 else if (Is64Bit && RegVT == MVT::i64)
2431 RC = &X86::GR64RegClass;
2432 else if (RegVT == MVT::f32)
2433 RC = &X86::FR32RegClass;
2434 else if (RegVT == MVT::f64)
2435 RC = &X86::FR64RegClass;
2436 else if (RegVT.is512BitVector())
2437 RC = &X86::VR512RegClass;
2438 else if (RegVT.is256BitVector())
2439 RC = &X86::VR256RegClass;
2440 else if (RegVT.is128BitVector())
2441 RC = &X86::VR128RegClass;
2442 else if (RegVT == MVT::x86mmx)
2443 RC = &X86::VR64RegClass;
2444 else if (RegVT == MVT::i1)
2445 RC = &X86::VK1RegClass;
2446 else if (RegVT == MVT::v8i1)
2447 RC = &X86::VK8RegClass;
2448 else if (RegVT == MVT::v16i1)
2449 RC = &X86::VK16RegClass;
2450 else if (RegVT == MVT::v32i1)
2451 RC = &X86::VK32RegClass;
2452 else if (RegVT == MVT::v64i1)
2453 RC = &X86::VK64RegClass;
2454 else
2455 llvm_unreachable("Unknown argument type!");
2457 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2458 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2460 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2461 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2462 // right size.
2463 if (VA.getLocInfo() == CCValAssign::SExt)
2464 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2465 DAG.getValueType(VA.getValVT()));
2466 else if (VA.getLocInfo() == CCValAssign::ZExt)
2467 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2468 DAG.getValueType(VA.getValVT()));
2469 else if (VA.getLocInfo() == CCValAssign::BCvt)
2470 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2472 if (VA.isExtInLoc()) {
2473 // Handle MMX values passed in XMM regs.
2474 if (RegVT.isVector())
2475 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2476 else
2477 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2478 }
2479 } else {
2480 assert(VA.isMemLoc());
2481 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2482 }
2484 // If value is passed via pointer - do a load.
2485 if (VA.getLocInfo() == CCValAssign::Indirect)
2486 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2487 MachinePointerInfo(), false, false, false, 0);
2489 InVals.push_back(ArgValue);
2490 }
2492 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2493 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2494 // The x86-64 ABIs require that for returning structs by value we copy
2495 // the sret argument into %rax/%eax (depending on ABI) for the return.
2496 // Win32 requires us to put the sret argument to %eax as well.
2497 // Save the argument into a virtual register so that we can access it
2498 // from the return points.
2499 if (Ins[i].Flags.isSRet()) {
2500 unsigned Reg = FuncInfo->getSRetReturnReg();
2501 if (!Reg) {
2502 MVT PtrTy = getPointerTy();
2503 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2504 FuncInfo->setSRetReturnReg(Reg);
2505 }
2506 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2507 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2508 break;
2509 }
2510 }
2511 }
2513 unsigned StackSize = CCInfo.getNextStackOffset();
2514 // Align stack specially for tail calls.
2515 if (FuncIsMadeTailCallSafe(CallConv,
2516 MF.getTarget().Options.GuaranteedTailCallOpt))
2517 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2519 // If the function takes variable number of arguments, make a frame index for
2520 // the start of the first vararg value... for expansion of llvm.va_start. We
2521 // can skip this if there are no va_start calls.
2522 if (MFI->hasVAStart() &&
2523 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2524 CallConv != CallingConv::X86_ThisCall))) {
2525 FuncInfo->setVarArgsFrameIndex(
2526 MFI->CreateFixedObject(1, StackSize, true));
2527 }
2529 // 64-bit calling conventions support varargs and register parameters, so we
2530 // have to do extra work to spill them in the prologue or forward them to
2531 // musttail calls.
2532 if (Is64Bit && isVarArg &&
2533 (MFI->hasVAStart() || MFI->hasMustTailInVarArgFunc())) {
2534 // Find the first unallocated argument registers.
2535 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2536 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2537 unsigned NumIntRegs =
2538 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2539 unsigned NumXMMRegs =
2540 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2541 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2542 "SSE register cannot be used when SSE is disabled!");
2544 // Gather all the live in physical registers.
2545 SmallVector<SDValue, 6> LiveGPRs;
2546 SmallVector<SDValue, 8> LiveXMMRegs;
2547 SDValue ALVal;
2548 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2549 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2550 LiveGPRs.push_back(
2551 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2552 }
2553 if (!ArgXMMs.empty()) {
2554 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2555 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2556 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2557 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2558 LiveXMMRegs.push_back(
2559 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2560 }
2561 }
2563 // Store them to the va_list returned by va_start.
2564 if (MFI->hasVAStart()) {
2565 if (IsWin64) {
2566 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2567 // Get to the caller-allocated home save location. Add 8 to account
2568 // for the return address.
2569 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2570 FuncInfo->setRegSaveFrameIndex(
2571 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2572 // Fixup to set vararg frame on shadow area (4 x i64).
2573 if (NumIntRegs < 4)
2574 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2575 } else {
2576 // For X86-64, if there are vararg parameters that are passed via
2577 // registers, then we must store them to their spots on the stack so
2578 // they may be loaded by deferencing the result of va_next.
2579 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2580 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2581 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2582 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2583 }
2585 // Store the integer parameter registers.
2586 SmallVector<SDValue, 8> MemOps;
2587 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2588 getPointerTy());
2589 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2590 for (SDValue Val : LiveGPRs) {
2591 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2592 DAG.getIntPtrConstant(Offset));
2593 SDValue Store =
2594 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2595 MachinePointerInfo::getFixedStack(
2596 FuncInfo->getRegSaveFrameIndex(), Offset),
2597 false, false, 0);
2598 MemOps.push_back(Store);
2599 Offset += 8;
2600 }
2602 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2603 // Now store the XMM (fp + vector) parameter registers.
2604 SmallVector<SDValue, 12> SaveXMMOps;
2605 SaveXMMOps.push_back(Chain);
2606 SaveXMMOps.push_back(ALVal);
2607 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2608 FuncInfo->getRegSaveFrameIndex()));
2609 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2610 FuncInfo->getVarArgsFPOffset()));
2611 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2612 LiveXMMRegs.end());
2613 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2614 MVT::Other, SaveXMMOps));
2615 }
2617 if (!MemOps.empty())
2618 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2619 } else {
2620 // Add all GPRs, al, and XMMs to the list of forwards. We will add then
2621 // to the liveout set on a musttail call.
2622 assert(MFI->hasMustTailInVarArgFunc());
2623 auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
2624 typedef X86MachineFunctionInfo::Forward Forward;
2626 for (unsigned I = 0, E = LiveGPRs.size(); I != E; ++I) {
2627 unsigned VReg =
2628 MF.getRegInfo().createVirtualRegister(&X86::GR64RegClass);
2629 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveGPRs[I]);
2630 Forwards.push_back(Forward(VReg, ArgGPRs[NumIntRegs + I], MVT::i64));
2631 }
2633 if (!ArgXMMs.empty()) {
2634 unsigned ALVReg =
2635 MF.getRegInfo().createVirtualRegister(&X86::GR8RegClass);
2636 Chain = DAG.getCopyToReg(Chain, dl, ALVReg, ALVal);
2637 Forwards.push_back(Forward(ALVReg, X86::AL, MVT::i8));
2639 for (unsigned I = 0, E = LiveXMMRegs.size(); I != E; ++I) {
2640 unsigned VReg =
2641 MF.getRegInfo().createVirtualRegister(&X86::VR128RegClass);
2642 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveXMMRegs[I]);
2643 Forwards.push_back(
2644 Forward(VReg, ArgXMMs[NumXMMRegs + I], MVT::v4f32));
2645 }
2646 }
2647 }
2648 }
2650 // Some CCs need callee pop.
2651 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2652 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2653 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2654 } else {
2655 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2656 // If this is an sret function, the return should pop the hidden pointer.
2657 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2658 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2659 argsAreStructReturn(Ins) == StackStructReturn)
2660 FuncInfo->setBytesToPopOnReturn(4);
2661 }
2663 if (!Is64Bit) {
2664 // RegSaveFrameIndex is X86-64 only.
2665 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2666 if (CallConv == CallingConv::X86_FastCall ||
2667 CallConv == CallingConv::X86_ThisCall)
2668 // fastcc functions can't have varargs.
2669 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2670 }
2672 FuncInfo->setArgumentStackSize(StackSize);
2674 return Chain;
2675 }
2677 SDValue
2678 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2679 SDValue StackPtr, SDValue Arg,
2680 SDLoc dl, SelectionDAG &DAG,
2681 const CCValAssign &VA,
2682 ISD::ArgFlagsTy Flags) const {
2683 unsigned LocMemOffset = VA.getLocMemOffset();
2684 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2685 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2686 if (Flags.isByVal())
2687 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2689 return DAG.getStore(Chain, dl, Arg, PtrOff,
2690 MachinePointerInfo::getStack(LocMemOffset),
2691 false, false, 0);
2692 }
2694 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2695 /// optimization is performed and it is required.
2696 SDValue
2697 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2698 SDValue &OutRetAddr, SDValue Chain,
2699 bool IsTailCall, bool Is64Bit,
2700 int FPDiff, SDLoc dl) const {
2701 // Adjust the Return address stack slot.
2702 EVT VT = getPointerTy();
2703 OutRetAddr = getReturnAddressFrameIndex(DAG);
2705 // Load the "old" Return address.
2706 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2707 false, false, false, 0);
2708 return SDValue(OutRetAddr.getNode(), 1);
2709 }
2711 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2712 /// optimization is performed and it is required (FPDiff!=0).
2713 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2714 SDValue Chain, SDValue RetAddrFrIdx,
2715 EVT PtrVT, unsigned SlotSize,
2716 int FPDiff, SDLoc dl) {
2717 // Store the return address to the appropriate stack slot.
2718 if (!FPDiff) return Chain;
2719 // Calculate the new stack slot for the return address.
2720 int NewReturnAddrFI =
2721 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2722 false);
2723 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2724 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2725 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2726 false, false, 0);
2727 return Chain;
2728 }
2730 SDValue
2731 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2732 SmallVectorImpl<SDValue> &InVals) const {
2733 SelectionDAG &DAG = CLI.DAG;
2734 SDLoc &dl = CLI.DL;
2735 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2736 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2737 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2738 SDValue Chain = CLI.Chain;
2739 SDValue Callee = CLI.Callee;
2740 CallingConv::ID CallConv = CLI.CallConv;
2741 bool &isTailCall = CLI.IsTailCall;
2742 bool isVarArg = CLI.IsVarArg;
2744 MachineFunction &MF = DAG.getMachineFunction();
2745 bool Is64Bit = Subtarget->is64Bit();
2746 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2747 StructReturnType SR = callIsStructReturn(Outs);
2748 bool IsSibcall = false;
2749 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2751 if (MF.getTarget().Options.DisableTailCalls)
2752 isTailCall = false;
2754 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2755 if (IsMustTail) {
2756 // Force this to be a tail call. The verifier rules are enough to ensure
2757 // that we can lower this successfully without moving the return address
2758 // around.
2759 isTailCall = true;
2760 } else if (isTailCall) {
2761 // Check if it's really possible to do a tail call.
2762 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2763 isVarArg, SR != NotStructReturn,
2764 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2765 Outs, OutVals, Ins, DAG);
2767 // Sibcalls are automatically detected tailcalls which do not require
2768 // ABI changes.
2769 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2770 IsSibcall = true;
2772 if (isTailCall)
2773 ++NumTailCalls;
2774 }
2776 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2777 "Var args not supported with calling convention fastcc, ghc or hipe");
2779 // Analyze operands of the call, assigning locations to each operand.
2780 SmallVector<CCValAssign, 16> ArgLocs;
2781 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2783 // Allocate shadow area for Win64
2784 if (IsWin64)
2785 CCInfo.AllocateStack(32, 8);
2787 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2789 // Get a count of how many bytes are to be pushed on the stack.
2790 unsigned NumBytes = CCInfo.getNextStackOffset();
2791 if (IsSibcall)
2792 // This is a sibcall. The memory operands are available in caller's
2793 // own caller's stack.
2794 NumBytes = 0;
2795 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2796 IsTailCallConvention(CallConv))
2797 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2799 int FPDiff = 0;
2800 if (isTailCall && !IsSibcall && !IsMustTail) {
2801 // Lower arguments at fp - stackoffset + fpdiff.
2802 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2804 FPDiff = NumBytesCallerPushed - NumBytes;
2806 // Set the delta of movement of the returnaddr stackslot.
2807 // But only set if delta is greater than previous delta.
2808 if (FPDiff < X86Info->getTCReturnAddrDelta())
2809 X86Info->setTCReturnAddrDelta(FPDiff);
2810 }
2812 unsigned NumBytesToPush = NumBytes;
2813 unsigned NumBytesToPop = NumBytes;
2815 // If we have an inalloca argument, all stack space has already been allocated
2816 // for us and be right at the top of the stack. We don't support multiple
2817 // arguments passed in memory when using inalloca.
2818 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2819 NumBytesToPush = 0;
2820 if (!ArgLocs.back().isMemLoc())
2821 report_fatal_error("cannot use inalloca attribute on a register "
2822 "parameter");
2823 if (ArgLocs.back().getLocMemOffset() != 0)
2824 report_fatal_error("any parameter with the inalloca attribute must be "
2825 "the only memory argument");
2826 }
2828 if (!IsSibcall)
2829 Chain = DAG.getCALLSEQ_START(
2830 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2832 SDValue RetAddrFrIdx;
2833 // Load return address for tail calls.
2834 if (isTailCall && FPDiff)
2835 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2836 Is64Bit, FPDiff, dl);
2838 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2839 SmallVector<SDValue, 8> MemOpChains;
2840 SDValue StackPtr;
2842 // Walk the register/memloc assignments, inserting copies/loads. In the case
2843 // of tail call optimization arguments are handle later.
2844 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2845 DAG.getSubtarget().getRegisterInfo());
2846 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2847 // Skip inalloca arguments, they have already been written.
2848 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2849 if (Flags.isInAlloca())
2850 continue;
2852 CCValAssign &VA = ArgLocs[i];
2853 EVT RegVT = VA.getLocVT();
2854 SDValue Arg = OutVals[i];
2855 bool isByVal = Flags.isByVal();
2857 // Promote the value if needed.
2858 switch (VA.getLocInfo()) {
2859 default: llvm_unreachable("Unknown loc info!");
2860 case CCValAssign::Full: break;
2861 case CCValAssign::SExt:
2862 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2863 break;
2864 case CCValAssign::ZExt:
2865 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2866 break;
2867 case CCValAssign::AExt:
2868 if (RegVT.is128BitVector()) {
2869 // Special case: passing MMX values in XMM registers.
2870 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2871 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2872 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2873 } else
2874 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2875 break;
2876 case CCValAssign::BCvt:
2877 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2878 break;
2879 case CCValAssign::Indirect: {
2880 // Store the argument.
2881 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2882 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2883 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2884 MachinePointerInfo::getFixedStack(FI),
2885 false, false, 0);
2886 Arg = SpillSlot;
2887 break;
2888 }
2889 }
2891 if (VA.isRegLoc()) {
2892 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2893 if (isVarArg && IsWin64) {
2894 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2895 // shadow reg if callee is a varargs function.
2896 unsigned ShadowReg = 0;
2897 switch (VA.getLocReg()) {
2898 case X86::XMM0: ShadowReg = X86::RCX; break;
2899 case X86::XMM1: ShadowReg = X86::RDX; break;
2900 case X86::XMM2: ShadowReg = X86::R8; break;
2901 case X86::XMM3: ShadowReg = X86::R9; break;
2902 }
2903 if (ShadowReg)
2904 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2905 }
2906 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2907 assert(VA.isMemLoc());
2908 if (!StackPtr.getNode())
2909 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2910 getPointerTy());
2911 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2912 dl, DAG, VA, Flags));
2913 }
2914 }
2916 if (!MemOpChains.empty())
2917 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2919 if (Subtarget->isPICStyleGOT()) {
2920 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2921 // GOT pointer.
2922 if (!isTailCall) {
2923 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2924 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2925 } else {
2926 // If we are tail calling and generating PIC/GOT style code load the
2927 // address of the callee into ECX. The value in ecx is used as target of
2928 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2929 // for tail calls on PIC/GOT architectures. Normally we would just put the
2930 // address of GOT into ebx and then call target@PLT. But for tail calls
2931 // ebx would be restored (since ebx is callee saved) before jumping to the
2932 // target@PLT.
2934 // Note: The actual moving to ECX is done further down.
2935 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2936 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2937 !G->getGlobal()->hasProtectedVisibility())
2938 Callee = LowerGlobalAddress(Callee, DAG);
2939 else if (isa<ExternalSymbolSDNode>(Callee))
2940 Callee = LowerExternalSymbol(Callee, DAG);
2941 }
2942 }
2944 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2945 // From AMD64 ABI document:
2946 // For calls that may call functions that use varargs or stdargs
2947 // (prototype-less calls or calls to functions containing ellipsis (...) in
2948 // the declaration) %al is used as hidden argument to specify the number
2949 // of SSE registers used. The contents of %al do not need to match exactly
2950 // the number of registers, but must be an ubound on the number of SSE
2951 // registers used and is in the range 0 - 8 inclusive.
2953 // Count the number of XMM registers allocated.
2954 static const MCPhysReg XMMArgRegs[] = {
2955 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2956 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2957 };
2958 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2959 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2960 && "SSE registers cannot be used when SSE is disabled");
2962 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2963 DAG.getConstant(NumXMMRegs, MVT::i8)));
2964 }
2966 if (Is64Bit && isVarArg && IsMustTail) {
2967 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2968 for (const auto &F : Forwards) {
2969 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2970 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
2971 }
2972 }
2974 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2975 // don't need this because the eligibility check rejects calls that require
2976 // shuffling arguments passed in memory.
2977 if (!IsSibcall && isTailCall) {
2978 // Force all the incoming stack arguments to be loaded from the stack
2979 // before any new outgoing arguments are stored to the stack, because the
2980 // outgoing stack slots may alias the incoming argument stack slots, and
2981 // the alias isn't otherwise explicit. This is slightly more conservative
2982 // than necessary, because it means that each store effectively depends
2983 // on every argument instead of just those arguments it would clobber.
2984 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2986 SmallVector<SDValue, 8> MemOpChains2;
2987 SDValue FIN;
2988 int FI = 0;
2989 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2990 CCValAssign &VA = ArgLocs[i];
2991 if (VA.isRegLoc())
2992 continue;
2993 assert(VA.isMemLoc());
2994 SDValue Arg = OutVals[i];
2995 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2996 // Skip inalloca arguments. They don't require any work.
2997 if (Flags.isInAlloca())
2998 continue;
2999 // Create frame index.
3000 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3001 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3002 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3003 FIN = DAG.getFrameIndex(FI, getPointerTy());
3005 if (Flags.isByVal()) {
3006 // Copy relative to framepointer.
3007 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3008 if (!StackPtr.getNode())
3009 StackPtr = DAG.getCopyFromReg(Chain, dl,
3010 RegInfo->getStackRegister(),
3011 getPointerTy());
3012 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3014 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3015 ArgChain,
3016 Flags, DAG, dl));
3017 } else {
3018 // Store relative to framepointer.
3019 MemOpChains2.push_back(
3020 DAG.getStore(ArgChain, dl, Arg, FIN,
3021 MachinePointerInfo::getFixedStack(FI),
3022 false, false, 0));
3023 }
3024 }
3026 if (!MemOpChains2.empty())
3027 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3029 // Store the return address to the appropriate stack slot.
3030 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3031 getPointerTy(), RegInfo->getSlotSize(),
3032 FPDiff, dl);
3033 }
3035 // Build a sequence of copy-to-reg nodes chained together with token chain
3036 // and flag operands which copy the outgoing args into registers.
3037 SDValue InFlag;
3038 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3039 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3040 RegsToPass[i].second, InFlag);
3041 InFlag = Chain.getValue(1);
3042 }
3044 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3045 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3046 // In the 64-bit large code model, we have to make all calls
3047 // through a register, since the call instruction's 32-bit
3048 // pc-relative offset may not be large enough to hold the whole
3049 // address.
3050 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3051 // If the callee is a GlobalAddress node (quite common, every direct call
3052 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3053 // it.
3055 // We should use extra load for direct calls to dllimported functions in
3056 // non-JIT mode.
3057 const GlobalValue *GV = G->getGlobal();
3058 if (!GV->hasDLLImportStorageClass()) {
3059 unsigned char OpFlags = 0;
3060 bool ExtraLoad = false;
3061 unsigned WrapperKind = ISD::DELETED_NODE;
3063 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3064 // external symbols most go through the PLT in PIC mode. If the symbol
3065 // has hidden or protected visibility, or if it is static or local, then
3066 // we don't need to use the PLT - we can directly call it.
3067 if (Subtarget->isTargetELF() &&
3068 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3069 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3070 OpFlags = X86II::MO_PLT;
3071 } else if (Subtarget->isPICStyleStubAny() &&
3072 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3073 (!Subtarget->getTargetTriple().isMacOSX() ||
3074 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3075 // PC-relative references to external symbols should go through $stub,
3076 // unless we're building with the leopard linker or later, which
3077 // automatically synthesizes these stubs.
3078 OpFlags = X86II::MO_DARWIN_STUB;
3079 } else if (Subtarget->isPICStyleRIPRel() &&
3080 isa<Function>(GV) &&
3081 cast<Function>(GV)->getAttributes().
3082 hasAttribute(AttributeSet::FunctionIndex,
3083 Attribute::NonLazyBind)) {
3084 // If the function is marked as non-lazy, generate an indirect call
3085 // which loads from the GOT directly. This avoids runtime overhead
3086 // at the cost of eager binding (and one extra byte of encoding).
3087 OpFlags = X86II::MO_GOTPCREL;
3088 WrapperKind = X86ISD::WrapperRIP;
3089 ExtraLoad = true;
3090 }
3092 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3093 G->getOffset(), OpFlags);
3095 // Add a wrapper if needed.
3096 if (WrapperKind != ISD::DELETED_NODE)
3097 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3098 // Add extra indirection if needed.
3099 if (ExtraLoad)
3100 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3101 MachinePointerInfo::getGOT(),
3102 false, false, false, 0);
3103 }
3104 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3105 unsigned char OpFlags = 0;
3107 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3108 // external symbols should go through the PLT.
3109 if (Subtarget->isTargetELF() &&
3110 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3111 OpFlags = X86II::MO_PLT;
3112 } else if (Subtarget->isPICStyleStubAny() &&
3113 (!Subtarget->getTargetTriple().isMacOSX() ||
3114 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3115 // PC-relative references to external symbols should go through $stub,
3116 // unless we're building with the leopard linker or later, which
3117 // automatically synthesizes these stubs.
3118 OpFlags = X86II::MO_DARWIN_STUB;
3119 }
3121 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3122 OpFlags);
3123 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3124 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3125 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3126 }
3128 // Returns a chain & a flag for retval copy to use.
3129 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3130 SmallVector<SDValue, 8> Ops;
3132 if (!IsSibcall && isTailCall) {
3133 Chain = DAG.getCALLSEQ_END(Chain,
3134 DAG.getIntPtrConstant(NumBytesToPop, true),
3135 DAG.getIntPtrConstant(0, true), InFlag, dl);
3136 InFlag = Chain.getValue(1);
3137 }
3139 Ops.push_back(Chain);
3140 Ops.push_back(Callee);
3142 if (isTailCall)
3143 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3145 // Add argument registers to the end of the list so that they are known live
3146 // into the call.
3147 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3148 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3149 RegsToPass[i].second.getValueType()));
3151 // Add a register mask operand representing the call-preserved registers.
3152 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3153 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3154 assert(Mask && "Missing call preserved mask for calling convention");
3155 Ops.push_back(DAG.getRegisterMask(Mask));
3157 if (InFlag.getNode())
3158 Ops.push_back(InFlag);
3160 if (isTailCall) {
3161 // We used to do:
3162 //// If this is the first return lowered for this function, add the regs
3163 //// to the liveout set for the function.
3164 // This isn't right, although it's probably harmless on x86; liveouts
3165 // should be computed from returns not tail calls. Consider a void
3166 // function making a tail call to a function returning int.
3167 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3168 }
3170 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3171 InFlag = Chain.getValue(1);
3173 // Create the CALLSEQ_END node.
3174 unsigned NumBytesForCalleeToPop;
3175 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3176 DAG.getTarget().Options.GuaranteedTailCallOpt))
3177 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3178 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3179 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3180 SR == StackStructReturn)
3181 // If this is a call to a struct-return function, the callee
3182 // pops the hidden struct pointer, so we have to push it back.
3183 // This is common for Darwin/X86, Linux & Mingw32 targets.
3184 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3185 NumBytesForCalleeToPop = 4;
3186 else
3187 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3189 // Returns a flag for retval copy to use.
3190 if (!IsSibcall) {
3191 Chain = DAG.getCALLSEQ_END(Chain,
3192 DAG.getIntPtrConstant(NumBytesToPop, true),
3193 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3194 true),
3195 InFlag, dl);
3196 InFlag = Chain.getValue(1);
3197 }
3199 // Handle result values, copying them out of physregs into vregs that we
3200 // return.
3201 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3202 Ins, dl, DAG, InVals);
3203 }
3205 //===----------------------------------------------------------------------===//
3206 // Fast Calling Convention (tail call) implementation
3207 //===----------------------------------------------------------------------===//
3209 // Like std call, callee cleans arguments, convention except that ECX is
3210 // reserved for storing the tail called function address. Only 2 registers are
3211 // free for argument passing (inreg). Tail call optimization is performed
3212 // provided:
3213 // * tailcallopt is enabled
3214 // * caller/callee are fastcc
3215 // On X86_64 architecture with GOT-style position independent code only local
3216 // (within module) calls are supported at the moment.
3217 // To keep the stack aligned according to platform abi the function
3218 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3219 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3220 // If a tail called function callee has more arguments than the caller the
3221 // caller needs to make sure that there is room to move the RETADDR to. This is
3222 // achieved by reserving an area the size of the argument delta right after the
3223 // original RETADDR, but before the saved framepointer or the spilled registers
3224 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3225 // stack layout:
3226 // arg1
3227 // arg2
3228 // RETADDR
3229 // [ new RETADDR
3230 // move area ]
3231 // (possible EBP)
3232 // ESI
3233 // EDI
3234 // local1 ..
3236 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3237 /// for a 16 byte align requirement.
3238 unsigned
3239 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3240 SelectionDAG& DAG) const {
3241 MachineFunction &MF = DAG.getMachineFunction();
3242 const TargetMachine &TM = MF.getTarget();
3243 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3244 TM.getSubtargetImpl()->getRegisterInfo());
3245 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3246 unsigned StackAlignment = TFI.getStackAlignment();
3247 uint64_t AlignMask = StackAlignment - 1;
3248 int64_t Offset = StackSize;
3249 unsigned SlotSize = RegInfo->getSlotSize();
3250 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3251 // Number smaller than 12 so just add the difference.
3252 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3253 } else {
3254 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3255 Offset = ((~AlignMask) & Offset) + StackAlignment +
3256 (StackAlignment-SlotSize);
3257 }
3258 return Offset;
3259 }
3261 /// MatchingStackOffset - Return true if the given stack call argument is
3262 /// already available in the same position (relatively) of the caller's
3263 /// incoming argument stack.
3264 static
3265 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3266 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3267 const X86InstrInfo *TII) {
3268 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3269 int FI = INT_MAX;
3270 if (Arg.getOpcode() == ISD::CopyFromReg) {
3271 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3272 if (!TargetRegisterInfo::isVirtualRegister(VR))
3273 return false;
3274 MachineInstr *Def = MRI->getVRegDef(VR);
3275 if (!Def)
3276 return false;
3277 if (!Flags.isByVal()) {
3278 if (!TII->isLoadFromStackSlot(Def, FI))
3279 return false;
3280 } else {
3281 unsigned Opcode = Def->getOpcode();
3282 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3283 Def->getOperand(1).isFI()) {
3284 FI = Def->getOperand(1).getIndex();
3285 Bytes = Flags.getByValSize();
3286 } else
3287 return false;
3288 }
3289 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3290 if (Flags.isByVal())
3291 // ByVal argument is passed in as a pointer but it's now being
3292 // dereferenced. e.g.
3293 // define @foo(%struct.X* %A) {
3294 // tail call @bar(%struct.X* byval %A)
3295 // }
3296 return false;
3297 SDValue Ptr = Ld->getBasePtr();
3298 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3299 if (!FINode)
3300 return false;
3301 FI = FINode->getIndex();
3302 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3303 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3304 FI = FINode->getIndex();
3305 Bytes = Flags.getByValSize();
3306 } else
3307 return false;
3309 assert(FI != INT_MAX);
3310 if (!MFI->isFixedObjectIndex(FI))
3311 return false;
3312 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3313 }
3315 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3316 /// for tail call optimization. Targets which want to do tail call
3317 /// optimization should implement this function.
3318 bool
3319 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3320 CallingConv::ID CalleeCC,
3321 bool isVarArg,
3322 bool isCalleeStructRet,
3323 bool isCallerStructRet,
3324 Type *RetTy,
3325 const SmallVectorImpl<ISD::OutputArg> &Outs,
3326 const SmallVectorImpl<SDValue> &OutVals,
3327 const SmallVectorImpl<ISD::InputArg> &Ins,
3328 SelectionDAG &DAG) const {
3329 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3330 return false;
3332 // If -tailcallopt is specified, make fastcc functions tail-callable.
3333 const MachineFunction &MF = DAG.getMachineFunction();
3334 const Function *CallerF = MF.getFunction();
3336 // If the function return type is x86_fp80 and the callee return type is not,
3337 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3338 // perform a tailcall optimization here.
3339 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3340 return false;
3342 CallingConv::ID CallerCC = CallerF->getCallingConv();
3343 bool CCMatch = CallerCC == CalleeCC;
3344 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3345 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3347 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3348 if (IsTailCallConvention(CalleeCC) && CCMatch)
3349 return true;
3350 return false;
3351 }
3353 // Look for obvious safe cases to perform tail call optimization that do not
3354 // require ABI changes. This is what gcc calls sibcall.
3356 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3357 // emit a special epilogue.
3358 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3359 DAG.getSubtarget().getRegisterInfo());
3360 if (RegInfo->needsStackRealignment(MF))
3361 return false;
3363 // Also avoid sibcall optimization if either caller or callee uses struct
3364 // return semantics.
3365 if (isCalleeStructRet || isCallerStructRet)
3366 return false;
3368 // An stdcall/thiscall caller is expected to clean up its arguments; the
3369 // callee isn't going to do that.
3370 // FIXME: this is more restrictive than needed. We could produce a tailcall
3371 // when the stack adjustment matches. For example, with a thiscall that takes
3372 // only one argument.
3373 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3374 CallerCC == CallingConv::X86_ThisCall))
3375 return false;
3377 // Do not sibcall optimize vararg calls unless all arguments are passed via
3378 // registers.
3379 if (isVarArg && !Outs.empty()) {
3381 // Optimizing for varargs on Win64 is unlikely to be safe without
3382 // additional testing.
3383 if (IsCalleeWin64 || IsCallerWin64)
3384 return false;
3386 SmallVector<CCValAssign, 16> ArgLocs;
3387 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3388 *DAG.getContext());
3390 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3391 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3392 if (!ArgLocs[i].isRegLoc())
3393 return false;
3394 }
3396 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3397 // stack. Therefore, if it's not used by the call it is not safe to optimize
3398 // this into a sibcall.
3399 bool Unused = false;
3400 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3401 if (!Ins[i].Used) {
3402 Unused = true;
3403 break;
3404 }
3405 }
3406 if (Unused) {
3407 SmallVector<CCValAssign, 16> RVLocs;
3408 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3409 *DAG.getContext());
3410 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3411 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3412 CCValAssign &VA = RVLocs[i];
3413 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3414 return false;
3415 }
3416 }
3418 // If the calling conventions do not match, then we'd better make sure the
3419 // results are returned in the same way as what the caller expects.
3420 if (!CCMatch) {
3421 SmallVector<CCValAssign, 16> RVLocs1;
3422 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3423 *DAG.getContext());
3424 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3426 SmallVector<CCValAssign, 16> RVLocs2;
3427 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3428 *DAG.getContext());
3429 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3431 if (RVLocs1.size() != RVLocs2.size())
3432 return false;
3433 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3434 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3435 return false;
3436 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3437 return false;
3438 if (RVLocs1[i].isRegLoc()) {
3439 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3440 return false;
3441 } else {
3442 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3443 return false;
3444 }
3445 }
3446 }
3448 // If the callee takes no arguments then go on to check the results of the
3449 // call.
3450 if (!Outs.empty()) {
3451 // Check if stack adjustment is needed. For now, do not do this if any
3452 // argument is passed on the stack.
3453 SmallVector<CCValAssign, 16> ArgLocs;
3454 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3455 *DAG.getContext());
3457 // Allocate shadow area for Win64
3458 if (IsCalleeWin64)
3459 CCInfo.AllocateStack(32, 8);
3461 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3462 if (CCInfo.getNextStackOffset()) {
3463 MachineFunction &MF = DAG.getMachineFunction();
3464 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3465 return false;
3467 // Check if the arguments are already laid out in the right way as
3468 // the caller's fixed stack objects.
3469 MachineFrameInfo *MFI = MF.getFrameInfo();
3470 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3471 const X86InstrInfo *TII =
3472 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3473 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3474 CCValAssign &VA = ArgLocs[i];
3475 SDValue Arg = OutVals[i];
3476 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3477 if (VA.getLocInfo() == CCValAssign::Indirect)
3478 return false;
3479 if (!VA.isRegLoc()) {
3480 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3481 MFI, MRI, TII))
3482 return false;
3483 }
3484 }
3485 }
3487 // If the tailcall address may be in a register, then make sure it's
3488 // possible to register allocate for it. In 32-bit, the call address can
3489 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3490 // callee-saved registers are restored. These happen to be the same
3491 // registers used to pass 'inreg' arguments so watch out for those.
3492 if (!Subtarget->is64Bit() &&
3493 ((!isa<GlobalAddressSDNode>(Callee) &&
3494 !isa<ExternalSymbolSDNode>(Callee)) ||
3495 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3496 unsigned NumInRegs = 0;
3497 // In PIC we need an extra register to formulate the address computation
3498 // for the callee.
3499 unsigned MaxInRegs =
3500 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3502 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3503 CCValAssign &VA = ArgLocs[i];
3504 if (!VA.isRegLoc())
3505 continue;
3506 unsigned Reg = VA.getLocReg();
3507 switch (Reg) {
3508 default: break;
3509 case X86::EAX: case X86::EDX: case X86::ECX:
3510 if (++NumInRegs == MaxInRegs)
3511 return false;
3512 break;
3513 }
3514 }
3515 }
3516 }
3518 return true;
3519 }
3521 FastISel *
3522 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3523 const TargetLibraryInfo *libInfo) const {
3524 return X86::createFastISel(funcInfo, libInfo);
3525 }
3527 //===----------------------------------------------------------------------===//
3528 // Other Lowering Hooks
3529 //===----------------------------------------------------------------------===//
3531 static bool MayFoldLoad(SDValue Op) {
3532 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3533 }
3535 static bool MayFoldIntoStore(SDValue Op) {
3536 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3537 }
3539 static bool isTargetShuffle(unsigned Opcode) {
3540 switch(Opcode) {
3541 default: return false;
3542 case X86ISD::BLENDI:
3543 case X86ISD::PSHUFB:
3544 case X86ISD::PSHUFD:
3545 case X86ISD::PSHUFHW:
3546 case X86ISD::PSHUFLW:
3547 case X86ISD::SHUFP:
3548 case X86ISD::PALIGNR:
3549 case X86ISD::MOVLHPS:
3550 case X86ISD::MOVLHPD:
3551 case X86ISD::MOVHLPS:
3552 case X86ISD::MOVLPS:
3553 case X86ISD::MOVLPD:
3554 case X86ISD::MOVSHDUP:
3555 case X86ISD::MOVSLDUP:
3556 case X86ISD::MOVDDUP:
3557 case X86ISD::MOVSS:
3558 case X86ISD::MOVSD:
3559 case X86ISD::UNPCKL:
3560 case X86ISD::UNPCKH:
3561 case X86ISD::VPERMILPI:
3562 case X86ISD::VPERM2X128:
3563 case X86ISD::VPERMI:
3564 return true;
3565 }
3566 }
3568 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3569 SDValue V1, SelectionDAG &DAG) {
3570 switch(Opc) {
3571 default: llvm_unreachable("Unknown x86 shuffle node");
3572 case X86ISD::MOVSHDUP:
3573 case X86ISD::MOVSLDUP:
3574 case X86ISD::MOVDDUP:
3575 return DAG.getNode(Opc, dl, VT, V1);
3576 }
3577 }
3579 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3580 SDValue V1, unsigned TargetMask,
3581 SelectionDAG &DAG) {
3582 switch(Opc) {
3583 default: llvm_unreachable("Unknown x86 shuffle node");
3584 case X86ISD::PSHUFD:
3585 case X86ISD::PSHUFHW:
3586 case X86ISD::PSHUFLW:
3587 case X86ISD::VPERMILPI:
3588 case X86ISD::VPERMI:
3589 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3590 }
3591 }
3593 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3594 SDValue V1, SDValue V2, unsigned TargetMask,
3595 SelectionDAG &DAG) {
3596 switch(Opc) {
3597 default: llvm_unreachable("Unknown x86 shuffle node");
3598 case X86ISD::PALIGNR:
3599 case X86ISD::VALIGN:
3600 case X86ISD::SHUFP:
3601 case X86ISD::VPERM2X128:
3602 return DAG.getNode(Opc, dl, VT, V1, V2,
3603 DAG.getConstant(TargetMask, MVT::i8));
3604 }
3605 }
3607 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3608 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3609 switch(Opc) {
3610 default: llvm_unreachable("Unknown x86 shuffle node");
3611 case X86ISD::MOVLHPS:
3612 case X86ISD::MOVLHPD:
3613 case X86ISD::MOVHLPS:
3614 case X86ISD::MOVLPS:
3615 case X86ISD::MOVLPD:
3616 case X86ISD::MOVSS:
3617 case X86ISD::MOVSD:
3618 case X86ISD::UNPCKL:
3619 case X86ISD::UNPCKH:
3620 return DAG.getNode(Opc, dl, VT, V1, V2);
3621 }
3622 }
3624 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3625 MachineFunction &MF = DAG.getMachineFunction();
3626 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3627 DAG.getSubtarget().getRegisterInfo());
3628 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3629 int ReturnAddrIndex = FuncInfo->getRAIndex();
3631 if (ReturnAddrIndex == 0) {
3632 // Set up a frame object for the return address.
3633 unsigned SlotSize = RegInfo->getSlotSize();
3634 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3635 -(int64_t)SlotSize,
3636 false);
3637 FuncInfo->setRAIndex(ReturnAddrIndex);
3638 }
3640 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3641 }
3643 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3644 bool hasSymbolicDisplacement) {
3645 // Offset should fit into 32 bit immediate field.
3646 if (!isInt<32>(Offset))
3647 return false;
3649 // If we don't have a symbolic displacement - we don't have any extra
3650 // restrictions.
3651 if (!hasSymbolicDisplacement)
3652 return true;
3654 // FIXME: Some tweaks might be needed for medium code model.
3655 if (M != CodeModel::Small && M != CodeModel::Kernel)
3656 return false;
3658 // For small code model we assume that latest object is 16MB before end of 31
3659 // bits boundary. We may also accept pretty large negative constants knowing
3660 // that all objects are in the positive half of address space.
3661 if (M == CodeModel::Small && Offset < 16*1024*1024)
3662 return true;
3664 // For kernel code model we know that all object resist in the negative half
3665 // of 32bits address space. We may not accept negative offsets, since they may
3666 // be just off and we may accept pretty large positive ones.
3667 if (M == CodeModel::Kernel && Offset > 0)
3668 return true;
3670 return false;
3671 }
3673 /// isCalleePop - Determines whether the callee is required to pop its
3674 /// own arguments. Callee pop is necessary to support tail calls.
3675 bool X86::isCalleePop(CallingConv::ID CallingConv,
3676 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3677 switch (CallingConv) {
3678 default:
3679 return false;
3680 case CallingConv::X86_StdCall:
3681 case CallingConv::X86_FastCall:
3682 case CallingConv::X86_ThisCall:
3683 return !is64Bit;
3684 case CallingConv::Fast:
3685 case CallingConv::GHC:
3686 case CallingConv::HiPE:
3687 if (IsVarArg)
3688 return false;
3689 return TailCallOpt;
3690 }
3691 }
3693 /// \brief Return true if the condition is an unsigned comparison operation.
3694 static bool isX86CCUnsigned(unsigned X86CC) {
3695 switch (X86CC) {
3696 default: llvm_unreachable("Invalid integer condition!");
3697 case X86::COND_E: return true;
3698 case X86::COND_G: return false;
3699 case X86::COND_GE: return false;
3700 case X86::COND_L: return false;
3701 case X86::COND_LE: return false;
3702 case X86::COND_NE: return true;
3703 case X86::COND_B: return true;
3704 case X86::COND_A: return true;
3705 case X86::COND_BE: return true;
3706 case X86::COND_AE: return true;
3707 }
3708 llvm_unreachable("covered switch fell through?!");
3709 }
3711 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3712 /// specific condition code, returning the condition code and the LHS/RHS of the
3713 /// comparison to make.
3714 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3715 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3716 if (!isFP) {
3717 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3718 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3719 // X > -1 -> X == 0, jump !sign.
3720 RHS = DAG.getConstant(0, RHS.getValueType());
3721 return X86::COND_NS;
3722 }
3723 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3724 // X < 0 -> X == 0, jump on sign.
3725 return X86::COND_S;
3726 }
3727 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3728 // X < 1 -> X <= 0
3729 RHS = DAG.getConstant(0, RHS.getValueType());
3730 return X86::COND_LE;
3731 }
3732 }
3734 switch (SetCCOpcode) {
3735 default: llvm_unreachable("Invalid integer condition!");
3736 case ISD::SETEQ: return X86::COND_E;
3737 case ISD::SETGT: return X86::COND_G;
3738 case ISD::SETGE: return X86::COND_GE;
3739 case ISD::SETLT: return X86::COND_L;
3740 case ISD::SETLE: return X86::COND_LE;
3741 case ISD::SETNE: return X86::COND_NE;
3742 case ISD::SETULT: return X86::COND_B;
3743 case ISD::SETUGT: return X86::COND_A;
3744 case ISD::SETULE: return X86::COND_BE;
3745 case ISD::SETUGE: return X86::COND_AE;
3746 }
3747 }
3749 // First determine if it is required or is profitable to flip the operands.
3751 // If LHS is a foldable load, but RHS is not, flip the condition.
3752 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3753 !ISD::isNON_EXTLoad(RHS.getNode())) {
3754 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3755 std::swap(LHS, RHS);
3756 }
3758 switch (SetCCOpcode) {
3759 default: break;
3760 case ISD::SETOLT:
3761 case ISD::SETOLE:
3762 case ISD::SETUGT:
3763 case ISD::SETUGE:
3764 std::swap(LHS, RHS);
3765 break;
3766 }
3768 // On a floating point condition, the flags are set as follows:
3769 // ZF PF CF op
3770 // 0 | 0 | 0 | X > Y
3771 // 0 | 0 | 1 | X < Y
3772 // 1 | 0 | 0 | X == Y
3773 // 1 | 1 | 1 | unordered
3774 switch (SetCCOpcode) {
3775 default: llvm_unreachable("Condcode should be pre-legalized away");
3776 case ISD::SETUEQ:
3777 case ISD::SETEQ: return X86::COND_E;
3778 case ISD::SETOLT: // flipped
3779 case ISD::SETOGT:
3780 case ISD::SETGT: return X86::COND_A;
3781 case ISD::SETOLE: // flipped
3782 case ISD::SETOGE:
3783 case ISD::SETGE: return X86::COND_AE;
3784 case ISD::SETUGT: // flipped
3785 case ISD::SETULT:
3786 case ISD::SETLT: return X86::COND_B;
3787 case ISD::SETUGE: // flipped
3788 case ISD::SETULE:
3789 case ISD::SETLE: return X86::COND_BE;
3790 case ISD::SETONE:
3791 case ISD::SETNE: return X86::COND_NE;
3792 case ISD::SETUO: return X86::COND_P;
3793 case ISD::SETO: return X86::COND_NP;
3794 case ISD::SETOEQ:
3795 case ISD::SETUNE: return X86::COND_INVALID;
3796 }
3797 }
3799 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3800 /// code. Current x86 isa includes the following FP cmov instructions:
3801 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3802 static bool hasFPCMov(unsigned X86CC) {
3803 switch (X86CC) {
3804 default:
3805 return false;
3806 case X86::COND_B:
3807 case X86::COND_BE:
3808 case X86::COND_E:
3809 case X86::COND_P:
3810 case X86::COND_A:
3811 case X86::COND_AE:
3812 case X86::COND_NE:
3813 case X86::COND_NP:
3814 return true;
3815 }
3816 }
3818 /// isFPImmLegal - Returns true if the target can instruction select the
3819 /// specified FP immediate natively. If false, the legalizer will
3820 /// materialize the FP immediate as a load from a constant pool.
3821 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3822 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3823 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3824 return true;
3825 }
3826 return false;
3827 }
3829 /// \brief Returns true if it is beneficial to convert a load of a constant
3830 /// to just the constant itself.
3831 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3832 Type *Ty) const {
3833 assert(Ty->isIntegerTy());
3835 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3836 if (BitSize == 0 || BitSize > 64)
3837 return false;
3838 return true;
3839 }
3841 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3842 /// the specified range (L, H].
3843 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3844 return (Val < 0) || (Val >= Low && Val < Hi);
3845 }
3847 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3848 /// specified value.
3849 static bool isUndefOrEqual(int Val, int CmpVal) {
3850 return (Val < 0 || Val == CmpVal);
3851 }
3853 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3854 /// from position Pos and ending in Pos+Size, falls within the specified
3855 /// sequential range (L, L+Pos]. or is undef.
3856 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3857 unsigned Pos, unsigned Size, int Low) {
3858 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3859 if (!isUndefOrEqual(Mask[i], Low))
3860 return false;
3861 return true;
3862 }
3864 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3865 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3866 /// the second operand.
3867 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3868 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3869 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3870 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3871 return (Mask[0] < 2 && Mask[1] < 2);
3872 return false;
3873 }
3875 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3876 /// is suitable for input to PSHUFHW.
3877 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3878 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3879 return false;
3881 // Lower quadword copied in order or undef.
3882 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3883 return false;
3885 // Upper quadword shuffled.
3886 for (unsigned i = 4; i != 8; ++i)
3887 if (!isUndefOrInRange(Mask[i], 4, 8))
3888 return false;
3890 if (VT == MVT::v16i16) {
3891 // Lower quadword copied in order or undef.
3892 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3893 return false;
3895 // Upper quadword shuffled.
3896 for (unsigned i = 12; i != 16; ++i)
3897 if (!isUndefOrInRange(Mask[i], 12, 16))
3898 return false;
3899 }
3901 return true;
3902 }
3904 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3905 /// is suitable for input to PSHUFLW.
3906 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3907 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3908 return false;
3910 // Upper quadword copied in order.
3911 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3912 return false;
3914 // Lower quadword shuffled.
3915 for (unsigned i = 0; i != 4; ++i)
3916 if (!isUndefOrInRange(Mask[i], 0, 4))
3917 return false;
3919 if (VT == MVT::v16i16) {
3920 // Upper quadword copied in order.
3921 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3922 return false;
3924 // Lower quadword shuffled.
3925 for (unsigned i = 8; i != 12; ++i)
3926 if (!isUndefOrInRange(Mask[i], 8, 12))
3927 return false;
3928 }
3930 return true;
3931 }
3933 /// \brief Return true if the mask specifies a shuffle of elements that is
3934 /// suitable for input to intralane (palignr) or interlane (valign) vector
3935 /// right-shift.
3936 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3937 unsigned NumElts = VT.getVectorNumElements();
3938 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3939 unsigned NumLaneElts = NumElts/NumLanes;
3941 // Do not handle 64-bit element shuffles with palignr.
3942 if (NumLaneElts == 2)
3943 return false;
3945 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3946 unsigned i;
3947 for (i = 0; i != NumLaneElts; ++i) {
3948 if (Mask[i+l] >= 0)
3949 break;
3950 }
3952 // Lane is all undef, go to next lane
3953 if (i == NumLaneElts)
3954 continue;
3956 int Start = Mask[i+l];
3958 // Make sure its in this lane in one of the sources
3959 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3960 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3961 return false;
3963 // If not lane 0, then we must match lane 0
3964 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3965 return false;
3967 // Correct second source to be contiguous with first source
3968 if (Start >= (int)NumElts)
3969 Start -= NumElts - NumLaneElts;
3971 // Make sure we're shifting in the right direction.
3972 if (Start <= (int)(i+l))
3973 return false;
3975 Start -= i;
3977 // Check the rest of the elements to see if they are consecutive.
3978 for (++i; i != NumLaneElts; ++i) {
3979 int Idx = Mask[i+l];
3981 // Make sure its in this lane
3982 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3983 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3984 return false;
3986 // If not lane 0, then we must match lane 0
3987 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3988 return false;
3990 if (Idx >= (int)NumElts)
3991 Idx -= NumElts - NumLaneElts;
3993 if (!isUndefOrEqual(Idx, Start+i))
3994 return false;
3996 }
3997 }
3999 return true;
4000 }
4002 /// \brief Return true if the node specifies a shuffle of elements that is
4003 /// suitable for input to PALIGNR.
4004 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4005 const X86Subtarget *Subtarget) {
4006 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4007 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4008 VT.is512BitVector())
4009 // FIXME: Add AVX512BW.
4010 return false;
4012 return isAlignrMask(Mask, VT, false);
4013 }
4015 /// \brief Return true if the node specifies a shuffle of elements that is
4016 /// suitable for input to VALIGN.
4017 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4018 const X86Subtarget *Subtarget) {
4019 // FIXME: Add AVX512VL.
4020 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4021 return false;
4022 return isAlignrMask(Mask, VT, true);
4023 }
4025 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4026 /// the two vector operands have swapped position.
4027 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4028 unsigned NumElems) {
4029 for (unsigned i = 0; i != NumElems; ++i) {
4030 int idx = Mask[i];
4031 if (idx < 0)
4032 continue;
4033 else if (idx < (int)NumElems)
4034 Mask[i] = idx + NumElems;
4035 else
4036 Mask[i] = idx - NumElems;
4037 }
4038 }
4040 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4041 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4042 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4043 /// reverse of what x86 shuffles want.
4044 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4046 unsigned NumElems = VT.getVectorNumElements();
4047 unsigned NumLanes = VT.getSizeInBits()/128;
4048 unsigned NumLaneElems = NumElems/NumLanes;
4050 if (NumLaneElems != 2 && NumLaneElems != 4)
4051 return false;
4053 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4054 bool symetricMaskRequired =
4055 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4057 // VSHUFPSY divides the resulting vector into 4 chunks.
4058 // The sources are also splitted into 4 chunks, and each destination
4059 // chunk must come from a different source chunk.
4060 //
4061 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4062 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4063 //
4064 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4065 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4066 //
4067 // VSHUFPDY divides the resulting vector into 4 chunks.
4068 // The sources are also splitted into 4 chunks, and each destination
4069 // chunk must come from a different source chunk.
4070 //
4071 // SRC1 => X3 X2 X1 X0
4072 // SRC2 => Y3 Y2 Y1 Y0
4073 //
4074 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4075 //
4076 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4077 unsigned HalfLaneElems = NumLaneElems/2;
4078 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4079 for (unsigned i = 0; i != NumLaneElems; ++i) {
4080 int Idx = Mask[i+l];
4081 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4082 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4083 return false;
4084 // For VSHUFPSY, the mask of the second half must be the same as the
4085 // first but with the appropriate offsets. This works in the same way as
4086 // VPERMILPS works with masks.
4087 if (!symetricMaskRequired || Idx < 0)
4088 continue;
4089 if (MaskVal[i] < 0) {
4090 MaskVal[i] = Idx - l;
4091 continue;
4092 }
4093 if ((signed)(Idx - l) != MaskVal[i])
4094 return false;
4095 }
4096 }
4098 return true;
4099 }
4101 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4102 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4103 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4104 if (!VT.is128BitVector())
4105 return false;
4107 unsigned NumElems = VT.getVectorNumElements();
4109 if (NumElems != 4)
4110 return false;
4112 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4113 return isUndefOrEqual(Mask[0], 6) &&
4114 isUndefOrEqual(Mask[1], 7) &&
4115 isUndefOrEqual(Mask[2], 2) &&
4116 isUndefOrEqual(Mask[3], 3);
4117 }
4119 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4120 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4121 /// <2, 3, 2, 3>
4122 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4123 if (!VT.is128BitVector())
4124 return false;
4126 unsigned NumElems = VT.getVectorNumElements();
4128 if (NumElems != 4)
4129 return false;
4131 return isUndefOrEqual(Mask[0], 2) &&
4132 isUndefOrEqual(Mask[1], 3) &&
4133 isUndefOrEqual(Mask[2], 2) &&
4134 isUndefOrEqual(Mask[3], 3);
4135 }
4137 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4138 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4139 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4140 if (!VT.is128BitVector())
4141 return false;
4143 unsigned NumElems = VT.getVectorNumElements();
4145 if (NumElems != 2 && NumElems != 4)
4146 return false;
4148 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4149 if (!isUndefOrEqual(Mask[i], i + NumElems))
4150 return false;
4152 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4153 if (!isUndefOrEqual(Mask[i], i))
4154 return false;
4156 return true;
4157 }
4159 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4160 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4161 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4162 if (!VT.is128BitVector())
4163 return false;
4165 unsigned NumElems = VT.getVectorNumElements();
4167 if (NumElems != 2 && NumElems != 4)
4168 return false;
4170 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4171 if (!isUndefOrEqual(Mask[i], i))
4172 return false;
4174 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4175 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4176 return false;
4178 return true;
4179 }
4181 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4182 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4183 /// i. e: If all but one element come from the same vector.
4184 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4185 // TODO: Deal with AVX's VINSERTPS
4186 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4187 return false;
4189 unsigned CorrectPosV1 = 0;
4190 unsigned CorrectPosV2 = 0;
4191 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4192 if (Mask[i] == -1) {
4193 ++CorrectPosV1;
4194 ++CorrectPosV2;
4195 continue;
4196 }
4198 if (Mask[i] == i)
4199 ++CorrectPosV1;
4200 else if (Mask[i] == i + 4)
4201 ++CorrectPosV2;
4202 }
4204 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4205 // We have 3 elements (undefs count as elements from any vector) from one
4206 // vector, and one from another.
4207 return true;
4209 return false;
4210 }
4212 //
4213 // Some special combinations that can be optimized.
4214 //
4215 static
4216 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4217 SelectionDAG &DAG) {
4218 MVT VT = SVOp->getSimpleValueType(0);
4219 SDLoc dl(SVOp);
4221 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4222 return SDValue();
4224 ArrayRef<int> Mask = SVOp->getMask();
4226 // These are the special masks that may be optimized.
4227 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4228 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4229 bool MatchEvenMask = true;
4230 bool MatchOddMask = true;
4231 for (int i=0; i<8; ++i) {
4232 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4233 MatchEvenMask = false;
4234 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4235 MatchOddMask = false;
4236 }
4238 if (!MatchEvenMask && !MatchOddMask)
4239 return SDValue();
4241 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4243 SDValue Op0 = SVOp->getOperand(0);
4244 SDValue Op1 = SVOp->getOperand(1);
4246 if (MatchEvenMask) {
4247 // Shift the second operand right to 32 bits.
4248 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4249 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4250 } else {
4251 // Shift the first operand left to 32 bits.
4252 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4253 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4254 }
4255 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4256 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4257 }
4259 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4260 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4261 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4262 bool HasInt256, bool V2IsSplat = false) {
4264 assert(VT.getSizeInBits() >= 128 &&
4265 "Unsupported vector type for unpckl");
4267 unsigned NumElts = VT.getVectorNumElements();
4268 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4269 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4270 return false;
4272 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4273 "Unsupported vector type for unpckh");
4275 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4276 unsigned NumLanes = VT.getSizeInBits()/128;
4277 unsigned NumLaneElts = NumElts/NumLanes;
4279 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4280 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4281 int BitI = Mask[l+i];
4282 int BitI1 = Mask[l+i+1];
4283 if (!isUndefOrEqual(BitI, j))
4284 return false;
4285 if (V2IsSplat) {
4286 if (!isUndefOrEqual(BitI1, NumElts))
4287 return false;
4288 } else {
4289 if (!isUndefOrEqual(BitI1, j + NumElts))
4290 return false;
4291 }
4292 }
4293 }
4295 return true;
4296 }
4298 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4299 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4300 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4301 bool HasInt256, bool V2IsSplat = false) {
4302 assert(VT.getSizeInBits() >= 128 &&
4303 "Unsupported vector type for unpckh");
4305 unsigned NumElts = VT.getVectorNumElements();
4306 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4307 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4308 return false;
4310 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4311 "Unsupported vector type for unpckh");
4313 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4314 unsigned NumLanes = VT.getSizeInBits()/128;
4315 unsigned NumLaneElts = NumElts/NumLanes;
4317 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4318 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4319 int BitI = Mask[l+i];
4320 int BitI1 = Mask[l+i+1];
4321 if (!isUndefOrEqual(BitI, j))
4322 return false;
4323 if (V2IsSplat) {
4324 if (isUndefOrEqual(BitI1, NumElts))
4325 return false;
4326 } else {
4327 if (!isUndefOrEqual(BitI1, j+NumElts))
4328 return false;
4329 }
4330 }
4331 }
4332 return true;
4333 }
4335 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4336 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4337 /// <0, 0, 1, 1>
4338 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4339 unsigned NumElts = VT.getVectorNumElements();
4340 bool Is256BitVec = VT.is256BitVector();
4342 if (VT.is512BitVector())
4343 return false;
4344 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4345 "Unsupported vector type for unpckh");
4347 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4348 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4349 return false;
4351 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4352 // FIXME: Need a better way to get rid of this, there's no latency difference
4353 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4354 // the former later. We should also remove the "_undef" special mask.
4355 if (NumElts == 4 && Is256BitVec)
4356 return false;
4358 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4359 // independently on 128-bit lanes.
4360 unsigned NumLanes = VT.getSizeInBits()/128;
4361 unsigned NumLaneElts = NumElts/NumLanes;
4363 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4364 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4365 int BitI = Mask[l+i];
4366 int BitI1 = Mask[l+i+1];
4368 if (!isUndefOrEqual(BitI, j))
4369 return false;
4370 if (!isUndefOrEqual(BitI1, j))
4371 return false;
4372 }
4373 }
4375 return true;
4376 }
4378 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4379 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4380 /// <2, 2, 3, 3>
4381 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4382 unsigned NumElts = VT.getVectorNumElements();
4384 if (VT.is512BitVector())
4385 return false;
4387 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4388 "Unsupported vector type for unpckh");
4390 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4391 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4392 return false;
4394 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4395 // independently on 128-bit lanes.
4396 unsigned NumLanes = VT.getSizeInBits()/128;
4397 unsigned NumLaneElts = NumElts/NumLanes;
4399 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4400 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4401 int BitI = Mask[l+i];
4402 int BitI1 = Mask[l+i+1];
4403 if (!isUndefOrEqual(BitI, j))
4404 return false;
4405 if (!isUndefOrEqual(BitI1, j))
4406 return false;
4407 }
4408 }
4409 return true;
4410 }
4412 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4413 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4414 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4415 if (!VT.is512BitVector())
4416 return false;
4418 unsigned NumElts = VT.getVectorNumElements();
4419 unsigned HalfSize = NumElts/2;
4420 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4421 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4422 *Imm = 1;
4423 return true;
4424 }
4425 }
4426 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4427 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4428 *Imm = 0;
4429 return true;
4430 }
4431 }
4432 return false;
4433 }
4435 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4436 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4437 /// MOVSD, and MOVD, i.e. setting the lowest element.
4438 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4439 if (VT.getVectorElementType().getSizeInBits() < 32)
4440 return false;
4441 if (!VT.is128BitVector())
4442 return false;
4444 unsigned NumElts = VT.getVectorNumElements();
4446 if (!isUndefOrEqual(Mask[0], NumElts))
4447 return false;
4449 for (unsigned i = 1; i != NumElts; ++i)
4450 if (!isUndefOrEqual(Mask[i], i))
4451 return false;
4453 return true;
4454 }
4456 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4457 /// as permutations between 128-bit chunks or halves. As an example: this
4458 /// shuffle bellow:
4459 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4460 /// The first half comes from the second half of V1 and the second half from the
4461 /// the second half of V2.
4462 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4463 if (!HasFp256 || !VT.is256BitVector())
4464 return false;
4466 // The shuffle result is divided into half A and half B. In total the two
4467 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4468 // B must come from C, D, E or F.
4469 unsigned HalfSize = VT.getVectorNumElements()/2;
4470 bool MatchA = false, MatchB = false;
4472 // Check if A comes from one of C, D, E, F.
4473 for (unsigned Half = 0; Half != 4; ++Half) {
4474 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4475 MatchA = true;
4476 break;
4477 }
4478 }
4480 // Check if B comes from one of C, D, E, F.
4481 for (unsigned Half = 0; Half != 4; ++Half) {
4482 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4483 MatchB = true;
4484 break;
4485 }
4486 }
4488 return MatchA && MatchB;
4489 }
4491 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4492 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4493 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4494 MVT VT = SVOp->getSimpleValueType(0);
4496 unsigned HalfSize = VT.getVectorNumElements()/2;
4498 unsigned FstHalf = 0, SndHalf = 0;
4499 for (unsigned i = 0; i < HalfSize; ++i) {
4500 if (SVOp->getMaskElt(i) > 0) {
4501 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4502 break;
4503 }
4504 }
4505 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4506 if (SVOp->getMaskElt(i) > 0) {
4507 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4508 break;
4509 }
4510 }
4512 return (FstHalf | (SndHalf << 4));
4513 }
4515 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4516 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4517 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4518 if (EltSize < 32)
4519 return false;
4521 unsigned NumElts = VT.getVectorNumElements();
4522 Imm8 = 0;
4523 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4524 for (unsigned i = 0; i != NumElts; ++i) {
4525 if (Mask[i] < 0)
4526 continue;
4527 Imm8 |= Mask[i] << (i*2);
4528 }
4529 return true;
4530 }
4532 unsigned LaneSize = 4;
4533 SmallVector<int, 4> MaskVal(LaneSize, -1);
4535 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4536 for (unsigned i = 0; i != LaneSize; ++i) {
4537 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4538 return false;
4539 if (Mask[i+l] < 0)
4540 continue;
4541 if (MaskVal[i] < 0) {
4542 MaskVal[i] = Mask[i+l] - l;
4543 Imm8 |= MaskVal[i] << (i*2);
4544 continue;
4545 }
4546 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4547 return false;
4548 }
4549 }
4550 return true;
4551 }
4553 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4554 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4555 /// Note that VPERMIL mask matching is different depending whether theunderlying
4556 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4557 /// to the same elements of the low, but to the higher half of the source.
4558 /// In VPERMILPD the two lanes could be shuffled independently of each other
4559 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4560 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4561 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4562 if (VT.getSizeInBits() < 256 || EltSize < 32)
4563 return false;
4564 bool symetricMaskRequired = (EltSize == 32);
4565 unsigned NumElts = VT.getVectorNumElements();
4567 unsigned NumLanes = VT.getSizeInBits()/128;
4568 unsigned LaneSize = NumElts/NumLanes;
4569 // 2 or 4 elements in one lane
4571 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4572 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4573 for (unsigned i = 0; i != LaneSize; ++i) {
4574 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4575 return false;
4576 if (symetricMaskRequired) {
4577 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4578 ExpectedMaskVal[i] = Mask[i+l] - l;
4579 continue;
4580 }
4581 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4582 return false;
4583 }
4584 }
4585 }
4586 return true;
4587 }
4589 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4590 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4591 /// element of vector 2 and the other elements to come from vector 1 in order.
4592 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4593 bool V2IsSplat = false, bool V2IsUndef = false) {
4594 if (!VT.is128BitVector())
4595 return false;
4597 unsigned NumOps = VT.getVectorNumElements();
4598 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4599 return false;
4601 if (!isUndefOrEqual(Mask[0], 0))
4602 return false;
4604 for (unsigned i = 1; i != NumOps; ++i)
4605 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4606 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4607 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4608 return false;
4610 return true;
4611 }
4613 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4614 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4615 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4616 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4617 const X86Subtarget *Subtarget) {
4618 if (!Subtarget->hasSSE3())
4619 return false;
4621 unsigned NumElems = VT.getVectorNumElements();
4623 if ((VT.is128BitVector() && NumElems != 4) ||
4624 (VT.is256BitVector() && NumElems != 8) ||
4625 (VT.is512BitVector() && NumElems != 16))
4626 return false;
4628 // "i+1" is the value the indexed mask element must have
4629 for (unsigned i = 0; i != NumElems; i += 2)
4630 if (!isUndefOrEqual(Mask[i], i+1) ||
4631 !isUndefOrEqual(Mask[i+1], i+1))
4632 return false;
4634 return true;
4635 }
4637 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4638 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4639 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4640 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4641 const X86Subtarget *Subtarget) {
4642 if (!Subtarget->hasSSE3())
4643 return false;
4645 unsigned NumElems = VT.getVectorNumElements();
4647 if ((VT.is128BitVector() && NumElems != 4) ||
4648 (VT.is256BitVector() && NumElems != 8) ||
4649 (VT.is512BitVector() && NumElems != 16))
4650 return false;
4652 // "i" is the value the indexed mask element must have
4653 for (unsigned i = 0; i != NumElems; i += 2)
4654 if (!isUndefOrEqual(Mask[i], i) ||
4655 !isUndefOrEqual(Mask[i+1], i))
4656 return false;
4658 return true;
4659 }
4661 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4662 /// specifies a shuffle of elements that is suitable for input to 256-bit
4663 /// version of MOVDDUP.
4664 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4665 if (!HasFp256 || !VT.is256BitVector())
4666 return false;
4668 unsigned NumElts = VT.getVectorNumElements();
4669 if (NumElts != 4)
4670 return false;
4672 for (unsigned i = 0; i != NumElts/2; ++i)
4673 if (!isUndefOrEqual(Mask[i], 0))
4674 return false;
4675 for (unsigned i = NumElts/2; i != NumElts; ++i)
4676 if (!isUndefOrEqual(Mask[i], NumElts/2))
4677 return false;
4678 return true;
4679 }
4681 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4682 /// specifies a shuffle of elements that is suitable for input to 128-bit
4683 /// version of MOVDDUP.
4684 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4685 if (!VT.is128BitVector())
4686 return false;
4688 unsigned e = VT.getVectorNumElements() / 2;
4689 for (unsigned i = 0; i != e; ++i)
4690 if (!isUndefOrEqual(Mask[i], i))
4691 return false;
4692 for (unsigned i = 0; i != e; ++i)
4693 if (!isUndefOrEqual(Mask[e+i], i))
4694 return false;
4695 return true;
4696 }
4698 /// isVEXTRACTIndex - Return true if the specified
4699 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4700 /// suitable for instruction that extract 128 or 256 bit vectors
4701 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4702 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4703 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4704 return false;
4706 // The index should be aligned on a vecWidth-bit boundary.
4707 uint64_t Index =
4708 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4710 MVT VT = N->getSimpleValueType(0);
4711 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4712 bool Result = (Index * ElSize) % vecWidth == 0;
4714 return Result;
4715 }
4717 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4718 /// operand specifies a subvector insert that is suitable for input to
4719 /// insertion of 128 or 256-bit subvectors
4720 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4721 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4722 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4723 return false;
4724 // The index should be aligned on a vecWidth-bit boundary.
4725 uint64_t Index =
4726 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4728 MVT VT = N->getSimpleValueType(0);
4729 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4730 bool Result = (Index * ElSize) % vecWidth == 0;
4732 return Result;
4733 }
4735 bool X86::isVINSERT128Index(SDNode *N) {
4736 return isVINSERTIndex(N, 128);
4737 }
4739 bool X86::isVINSERT256Index(SDNode *N) {
4740 return isVINSERTIndex(N, 256);
4741 }
4743 bool X86::isVEXTRACT128Index(SDNode *N) {
4744 return isVEXTRACTIndex(N, 128);
4745 }
4747 bool X86::isVEXTRACT256Index(SDNode *N) {
4748 return isVEXTRACTIndex(N, 256);
4749 }
4751 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4752 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4753 /// Handles 128-bit and 256-bit.
4754 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4755 MVT VT = N->getSimpleValueType(0);
4757 assert((VT.getSizeInBits() >= 128) &&
4758 "Unsupported vector type for PSHUF/SHUFP");
4760 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4761 // independently on 128-bit lanes.
4762 unsigned NumElts = VT.getVectorNumElements();
4763 unsigned NumLanes = VT.getSizeInBits()/128;
4764 unsigned NumLaneElts = NumElts/NumLanes;
4766 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4767 "Only supports 2, 4 or 8 elements per lane");
4769 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4770 unsigned Mask = 0;
4771 for (unsigned i = 0; i != NumElts; ++i) {
4772 int Elt = N->getMaskElt(i);
4773 if (Elt < 0) continue;
4774 Elt &= NumLaneElts - 1;
4775 unsigned ShAmt = (i << Shift) % 8;
4776 Mask |= Elt << ShAmt;
4777 }
4779 return Mask;
4780 }
4782 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4783 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4784 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4785 MVT VT = N->getSimpleValueType(0);
4787 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4788 "Unsupported vector type for PSHUFHW");
4790 unsigned NumElts = VT.getVectorNumElements();
4792 unsigned Mask = 0;
4793 for (unsigned l = 0; l != NumElts; l += 8) {
4794 // 8 nodes per lane, but we only care about the last 4.
4795 for (unsigned i = 0; i < 4; ++i) {
4796 int Elt = N->getMaskElt(l+i+4);
4797 if (Elt < 0) continue;
4798 Elt &= 0x3; // only 2-bits.
4799 Mask |= Elt << (i * 2);
4800 }
4801 }
4803 return Mask;
4804 }
4806 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4807 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4808 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4809 MVT VT = N->getSimpleValueType(0);
4811 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4812 "Unsupported vector type for PSHUFHW");
4814 unsigned NumElts = VT.getVectorNumElements();
4816 unsigned Mask = 0;
4817 for (unsigned l = 0; l != NumElts; l += 8) {
4818 // 8 nodes per lane, but we only care about the first 4.
4819 for (unsigned i = 0; i < 4; ++i) {
4820 int Elt = N->getMaskElt(l+i);
4821 if (Elt < 0) continue;
4822 Elt &= 0x3; // only 2-bits
4823 Mask |= Elt << (i * 2);
4824 }
4825 }
4827 return Mask;
4828 }
4830 /// \brief Return the appropriate immediate to shuffle the specified
4831 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4832 /// VALIGN (if Interlane is true) instructions.
4833 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4834 bool InterLane) {
4835 MVT VT = SVOp->getSimpleValueType(0);
4836 unsigned EltSize = InterLane ? 1 :
4837 VT.getVectorElementType().getSizeInBits() >> 3;
4839 unsigned NumElts = VT.getVectorNumElements();
4840 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4841 unsigned NumLaneElts = NumElts/NumLanes;
4843 int Val = 0;
4844 unsigned i;
4845 for (i = 0; i != NumElts; ++i) {
4846 Val = SVOp->getMaskElt(i);
4847 if (Val >= 0)
4848 break;
4849 }
4850 if (Val >= (int)NumElts)
4851 Val -= NumElts - NumLaneElts;
4853 assert(Val - i > 0 && "PALIGNR imm should be positive");
4854 return (Val - i) * EltSize;
4855 }
4857 /// \brief Return the appropriate immediate to shuffle the specified
4858 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4859 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4860 return getShuffleAlignrImmediate(SVOp, false);
4861 }
4863 /// \brief Return the appropriate immediate to shuffle the specified
4864 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4865 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4866 return getShuffleAlignrImmediate(SVOp, true);
4867 }
4870 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4871 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4872 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4873 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4875 uint64_t Index =
4876 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4878 MVT VecVT = N->getOperand(0).getSimpleValueType();
4879 MVT ElVT = VecVT.getVectorElementType();
4881 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4882 return Index / NumElemsPerChunk;
4883 }
4885 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4886 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4887 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4888 llvm_unreachable("Illegal insert subvector for VINSERT");
4890 uint64_t Index =
4891 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4893 MVT VecVT = N->getSimpleValueType(0);
4894 MVT ElVT = VecVT.getVectorElementType();
4896 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4897 return Index / NumElemsPerChunk;
4898 }
4900 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4901 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4902 /// and VINSERTI128 instructions.
4903 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4904 return getExtractVEXTRACTImmediate(N, 128);
4905 }
4907 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4908 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4909 /// and VINSERTI64x4 instructions.
4910 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4911 return getExtractVEXTRACTImmediate(N, 256);
4912 }
4914 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4915 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4916 /// and VINSERTI128 instructions.
4917 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4918 return getInsertVINSERTImmediate(N, 128);
4919 }
4921 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4922 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4923 /// and VINSERTI64x4 instructions.
4924 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4925 return getInsertVINSERTImmediate(N, 256);
4926 }
4928 /// isZero - Returns true if Elt is a constant integer zero
4929 static bool isZero(SDValue V) {
4930 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4931 return C && C->isNullValue();
4932 }
4934 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4935 /// constant +0.0.
4936 bool X86::isZeroNode(SDValue Elt) {
4937 if (isZero(Elt))
4938 return true;
4939 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4940 return CFP->getValueAPF().isPosZero();
4941 return false;
4942 }
4944 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4945 /// match movhlps. The lower half elements should come from upper half of
4946 /// V1 (and in order), and the upper half elements should come from the upper
4947 /// half of V2 (and in order).
4948 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4949 if (!VT.is128BitVector())
4950 return false;
4951 if (VT.getVectorNumElements() != 4)
4952 return false;
4953 for (unsigned i = 0, e = 2; i != e; ++i)
4954 if (!isUndefOrEqual(Mask[i], i+2))
4955 return false;
4956 for (unsigned i = 2; i != 4; ++i)
4957 if (!isUndefOrEqual(Mask[i], i+4))
4958 return false;
4959 return true;
4960 }
4962 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4963 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4964 /// required.
4965 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4966 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4967 return false;
4968 N = N->getOperand(0).getNode();
4969 if (!ISD::isNON_EXTLoad(N))
4970 return false;
4971 if (LD)
4972 *LD = cast<LoadSDNode>(N);
4973 return true;
4974 }
4976 // Test whether the given value is a vector value which will be legalized
4977 // into a load.
4978 static bool WillBeConstantPoolLoad(SDNode *N) {
4979 if (N->getOpcode() != ISD::BUILD_VECTOR)
4980 return false;
4982 // Check for any non-constant elements.
4983 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4984 switch (N->getOperand(i).getNode()->getOpcode()) {
4985 case ISD::UNDEF:
4986 case ISD::ConstantFP:
4987 case ISD::Constant:
4988 break;
4989 default:
4990 return false;
4991 }
4993 // Vectors of all-zeros and all-ones are materialized with special
4994 // instructions rather than being loaded.
4995 return !ISD::isBuildVectorAllZeros(N) &&
4996 !ISD::isBuildVectorAllOnes(N);
4997 }
4999 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
5000 /// match movlp{s|d}. The lower half elements should come from lower half of
5001 /// V1 (and in order), and the upper half elements should come from the upper
5002 /// half of V2 (and in order). And since V1 will become the source of the
5003 /// MOVLP, it must be either a vector load or a scalar load to vector.
5004 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5005 ArrayRef<int> Mask, MVT VT) {
5006 if (!VT.is128BitVector())
5007 return false;
5009 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5010 return false;
5011 // Is V2 is a vector load, don't do this transformation. We will try to use
5012 // load folding shufps op.
5013 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5014 return false;
5016 unsigned NumElems = VT.getVectorNumElements();
5018 if (NumElems != 2 && NumElems != 4)
5019 return false;
5020 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5021 if (!isUndefOrEqual(Mask[i], i))
5022 return false;
5023 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5024 if (!isUndefOrEqual(Mask[i], i+NumElems))
5025 return false;
5026 return true;
5027 }
5029 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5030 /// to an zero vector.
5031 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5032 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5033 SDValue V1 = N->getOperand(0);
5034 SDValue V2 = N->getOperand(1);
5035 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5036 for (unsigned i = 0; i != NumElems; ++i) {
5037 int Idx = N->getMaskElt(i);
5038 if (Idx >= (int)NumElems) {
5039 unsigned Opc = V2.getOpcode();
5040 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5041 continue;
5042 if (Opc != ISD::BUILD_VECTOR ||
5043 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5044 return false;
5045 } else if (Idx >= 0) {
5046 unsigned Opc = V1.getOpcode();
5047 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5048 continue;
5049 if (Opc != ISD::BUILD_VECTOR ||
5050 !X86::isZeroNode(V1.getOperand(Idx)))
5051 return false;
5052 }
5053 }
5054 return true;
5055 }
5057 /// getZeroVector - Returns a vector of specified type with all zero elements.
5058 ///
5059 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5060 SelectionDAG &DAG, SDLoc dl) {
5061 assert(VT.isVector() && "Expected a vector type");
5063 // Always build SSE zero vectors as <4 x i32> bitcasted
5064 // to their dest type. This ensures they get CSE'd.
5065 SDValue Vec;
5066 if (VT.is128BitVector()) { // SSE
5067 if (Subtarget->hasSSE2()) { // SSE2
5068 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5069 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5070 } else { // SSE1
5071 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5072 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5073 }
5074 } else if (VT.is256BitVector()) { // AVX
5075 if (Subtarget->hasInt256()) { // AVX2
5076 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5077 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5078 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5079 } else {
5080 // 256-bit logic and arithmetic instructions in AVX are all
5081 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5082 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5083 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5084 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5085 }
5086 } else if (VT.is512BitVector()) { // AVX-512
5087 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5088 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5089 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5090 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5091 } else if (VT.getScalarType() == MVT::i1) {
5092 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5093 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5094 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5095 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5096 } else
5097 llvm_unreachable("Unexpected vector type");
5099 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5100 }
5102 /// getOnesVector - Returns a vector of specified type with all bits set.
5103 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5104 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5105 /// Then bitcast to their original type, ensuring they get CSE'd.
5106 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5107 SDLoc dl) {
5108 assert(VT.isVector() && "Expected a vector type");
5110 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
5111 SDValue Vec;
5112 if (VT.is256BitVector()) {
5113 if (HasInt256) { // AVX2
5114 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5115 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5116 } else { // AVX
5117 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5118 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5119 }
5120 } else if (VT.is128BitVector()) {
5121 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5122 } else
5123 llvm_unreachable("Unexpected vector type");
5125 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5126 }
5128 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5129 /// that point to V2 points to its first element.
5130 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5131 for (unsigned i = 0; i != NumElems; ++i) {
5132 if (Mask[i] > (int)NumElems) {
5133 Mask[i] = NumElems;
5134 }
5135 }
5136 }
5138 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5139 /// operation of specified width.
5140 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5141 SDValue V2) {
5142 unsigned NumElems = VT.getVectorNumElements();
5143 SmallVector<int, 8> Mask;
5144 Mask.push_back(NumElems);
5145 for (unsigned i = 1; i != NumElems; ++i)
5146 Mask.push_back(i);
5147 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5148 }
5150 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5151 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5152 SDValue V2) {
5153 unsigned NumElems = VT.getVectorNumElements();
5154 SmallVector<int, 8> Mask;
5155 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5156 Mask.push_back(i);
5157 Mask.push_back(i + NumElems);
5158 }
5159 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5160 }
5162 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5163 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5164 SDValue V2) {
5165 unsigned NumElems = VT.getVectorNumElements();
5166 SmallVector<int, 8> Mask;
5167 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5168 Mask.push_back(i + Half);
5169 Mask.push_back(i + NumElems + Half);
5170 }
5171 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5172 }
5174 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5175 // a generic shuffle instruction because the target has no such instructions.
5176 // Generate shuffles which repeat i16 and i8 several times until they can be
5177 // represented by v4f32 and then be manipulated by target suported shuffles.
5178 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5179 MVT VT = V.getSimpleValueType();
5180 int NumElems = VT.getVectorNumElements();
5181 SDLoc dl(V);
5183 while (NumElems > 4) {
5184 if (EltNo < NumElems/2) {
5185 V = getUnpackl(DAG, dl, VT, V, V);
5186 } else {
5187 V = getUnpackh(DAG, dl, VT, V, V);
5188 EltNo -= NumElems/2;
5189 }
5190 NumElems >>= 1;
5191 }
5192 return V;
5193 }
5195 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5196 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5197 MVT VT = V.getSimpleValueType();
5198 SDLoc dl(V);
5200 if (VT.is128BitVector()) {
5201 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5202 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5203 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5204 &SplatMask[0]);
5205 } else if (VT.is256BitVector()) {
5206 // To use VPERMILPS to splat scalars, the second half of indicies must
5207 // refer to the higher part, which is a duplication of the lower one,
5208 // because VPERMILPS can only handle in-lane permutations.
5209 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5210 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5212 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5213 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5214 &SplatMask[0]);
5215 } else
5216 llvm_unreachable("Vector size not supported");
5218 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5219 }
5221 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5222 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5223 MVT SrcVT = SV->getSimpleValueType(0);
5224 SDValue V1 = SV->getOperand(0);
5225 SDLoc dl(SV);
5227 int EltNo = SV->getSplatIndex();
5228 int NumElems = SrcVT.getVectorNumElements();
5229 bool Is256BitVec = SrcVT.is256BitVector();
5231 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5232 "Unknown how to promote splat for type");
5234 // Extract the 128-bit part containing the splat element and update
5235 // the splat element index when it refers to the higher register.
5236 if (Is256BitVec) {
5237 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5238 if (EltNo >= NumElems/2)
5239 EltNo -= NumElems/2;
5240 }
5242 // All i16 and i8 vector types can't be used directly by a generic shuffle
5243 // instruction because the target has no such instruction. Generate shuffles
5244 // which repeat i16 and i8 several times until they fit in i32, and then can
5245 // be manipulated by target suported shuffles.
5246 MVT EltVT = SrcVT.getVectorElementType();
5247 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5248 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5250 // Recreate the 256-bit vector and place the same 128-bit vector
5251 // into the low and high part. This is necessary because we want
5252 // to use VPERM* to shuffle the vectors
5253 if (Is256BitVec) {
5254 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5255 }
5257 return getLegalSplat(DAG, V1, EltNo);
5258 }
5260 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5261 /// vector of zero or undef vector. This produces a shuffle where the low
5262 /// element of V2 is swizzled into the zero/undef vector, landing at element
5263 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5264 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5265 bool IsZero,
5266 const X86Subtarget *Subtarget,
5267 SelectionDAG &DAG) {
5268 MVT VT = V2.getSimpleValueType();
5269 SDValue V1 = IsZero
5270 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5271 unsigned NumElems = VT.getVectorNumElements();
5272 SmallVector<int, 16> MaskVec;
5273 for (unsigned i = 0; i != NumElems; ++i)
5274 // If this is the insertion idx, put the low elt of V2 here.
5275 MaskVec.push_back(i == Idx ? NumElems : i);
5276 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5277 }
5279 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5280 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5281 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5282 /// shuffles which use a single input multiple times, and in those cases it will
5283 /// adjust the mask to only have indices within that single input.
5284 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5285 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5286 unsigned NumElems = VT.getVectorNumElements();
5287 SDValue ImmN;
5289 IsUnary = false;
5290 bool IsFakeUnary = false;
5291 switch(N->getOpcode()) {
5292 case X86ISD::BLENDI:
5293 ImmN = N->getOperand(N->getNumOperands()-1);
5294 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5295 break;
5296 case X86ISD::SHUFP:
5297 ImmN = N->getOperand(N->getNumOperands()-1);
5298 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5299 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5300 break;
5301 case X86ISD::UNPCKH:
5302 DecodeUNPCKHMask(VT, Mask);
5303 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5304 break;
5305 case X86ISD::UNPCKL:
5306 DecodeUNPCKLMask(VT, Mask);
5307 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5308 break;
5309 case X86ISD::MOVHLPS:
5310 DecodeMOVHLPSMask(NumElems, Mask);
5311 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5312 break;
5313 case X86ISD::MOVLHPS:
5314 DecodeMOVLHPSMask(NumElems, Mask);
5315 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5316 break;
5317 case X86ISD::PALIGNR:
5318 ImmN = N->getOperand(N->getNumOperands()-1);
5319 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5320 break;
5321 case X86ISD::PSHUFD:
5322 case X86ISD::VPERMILPI:
5323 ImmN = N->getOperand(N->getNumOperands()-1);
5324 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5325 IsUnary = true;
5326 break;
5327 case X86ISD::PSHUFHW:
5328 ImmN = N->getOperand(N->getNumOperands()-1);
5329 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5330 IsUnary = true;
5331 break;
5332 case X86ISD::PSHUFLW:
5333 ImmN = N->getOperand(N->getNumOperands()-1);
5334 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5335 IsUnary = true;
5336 break;
5337 case X86ISD::PSHUFB: {
5338 IsUnary = true;
5339 SDValue MaskNode = N->getOperand(1);
5340 while (MaskNode->getOpcode() == ISD::BITCAST)
5341 MaskNode = MaskNode->getOperand(0);
5343 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5344 // If we have a build-vector, then things are easy.
5345 EVT VT = MaskNode.getValueType();
5346 assert(VT.isVector() &&
5347 "Can't produce a non-vector with a build_vector!");
5348 if (!VT.isInteger())
5349 return false;
5351 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5353 SmallVector<uint64_t, 32> RawMask;
5354 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5355 SDValue Op = MaskNode->getOperand(i);
5356 if (Op->getOpcode() == ISD::UNDEF) {
5357 RawMask.push_back((uint64_t)SM_SentinelUndef);
5358 continue;
5359 }
5360 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
5361 if (!CN)
5362 return false;
5363 APInt MaskElement = CN->getAPIntValue();
5365 // We now have to decode the element which could be any integer size and
5366 // extract each byte of it.
5367 for (int j = 0; j < NumBytesPerElement; ++j) {
5368 // Note that this is x86 and so always little endian: the low byte is
5369 // the first byte of the mask.
5370 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5371 MaskElement = MaskElement.lshr(8);
5372 }
5373 }
5374 DecodePSHUFBMask(RawMask, Mask);
5375 break;
5376 }
5378 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5379 if (!MaskLoad)
5380 return false;
5382 SDValue Ptr = MaskLoad->getBasePtr();
5383 if (Ptr->getOpcode() == X86ISD::Wrapper)
5384 Ptr = Ptr->getOperand(0);
5386 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5387 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5388 return false;
5390 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
5391 // FIXME: Support AVX-512 here.
5392 Type *Ty = C->getType();
5393 if (!Ty->isVectorTy() || (Ty->getVectorNumElements() != 16 &&
5394 Ty->getVectorNumElements() != 32))
5395 return false;
5397 DecodePSHUFBMask(C, Mask);
5398 break;
5399 }
5401 return false;
5402 }
5403 case X86ISD::VPERMI:
5404 ImmN = N->getOperand(N->getNumOperands()-1);
5405 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5406 IsUnary = true;
5407 break;
5408 case X86ISD::MOVSS:
5409 case X86ISD::MOVSD: {
5410 // The index 0 always comes from the first element of the second source,
5411 // this is why MOVSS and MOVSD are used in the first place. The other
5412 // elements come from the other positions of the first source vector
5413 Mask.push_back(NumElems);
5414 for (unsigned i = 1; i != NumElems; ++i) {
5415 Mask.push_back(i);
5416 }
5417 break;
5418 }
5419 case X86ISD::VPERM2X128:
5420 ImmN = N->getOperand(N->getNumOperands()-1);
5421 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5422 if (Mask.empty()) return false;
5423 break;
5424 case X86ISD::MOVSLDUP:
5425 DecodeMOVSLDUPMask(VT, Mask);
5426 break;
5427 case X86ISD::MOVSHDUP:
5428 DecodeMOVSHDUPMask(VT, Mask);
5429 break;
5430 case X86ISD::MOVDDUP:
5431 case X86ISD::MOVLHPD:
5432 case X86ISD::MOVLPD:
5433 case X86ISD::MOVLPS:
5434 // Not yet implemented
5435 return false;
5436 default: llvm_unreachable("unknown target shuffle node");
5437 }
5439 // If we have a fake unary shuffle, the shuffle mask is spread across two
5440 // inputs that are actually the same node. Re-map the mask to always point
5441 // into the first input.
5442 if (IsFakeUnary)
5443 for (int &M : Mask)
5444 if (M >= (int)Mask.size())
5445 M -= Mask.size();
5447 return true;
5448 }
5450 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5451 /// element of the result of the vector shuffle.
5452 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5453 unsigned Depth) {
5454 if (Depth == 6)
5455 return SDValue(); // Limit search depth.
5457 SDValue V = SDValue(N, 0);
5458 EVT VT = V.getValueType();
5459 unsigned Opcode = V.getOpcode();
5461 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5462 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5463 int Elt = SV->getMaskElt(Index);
5465 if (Elt < 0)
5466 return DAG.getUNDEF(VT.getVectorElementType());
5468 unsigned NumElems = VT.getVectorNumElements();
5469 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5470 : SV->getOperand(1);
5471 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5472 }
5474 // Recurse into target specific vector shuffles to find scalars.
5475 if (isTargetShuffle(Opcode)) {
5476 MVT ShufVT = V.getSimpleValueType();
5477 unsigned NumElems = ShufVT.getVectorNumElements();
5478 SmallVector<int, 16> ShuffleMask;
5479 bool IsUnary;
5481 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5482 return SDValue();
5484 int Elt = ShuffleMask[Index];
5485 if (Elt < 0)
5486 return DAG.getUNDEF(ShufVT.getVectorElementType());
5488 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5489 : N->getOperand(1);
5490 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5491 Depth+1);
5492 }
5494 // Actual nodes that may contain scalar elements
5495 if (Opcode == ISD::BITCAST) {
5496 V = V.getOperand(0);
5497 EVT SrcVT = V.getValueType();
5498 unsigned NumElems = VT.getVectorNumElements();
5500 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5501 return SDValue();
5502 }
5504 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5505 return (Index == 0) ? V.getOperand(0)
5506 : DAG.getUNDEF(VT.getVectorElementType());
5508 if (V.getOpcode() == ISD::BUILD_VECTOR)
5509 return V.getOperand(Index);
5511 return SDValue();
5512 }
5514 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5515 /// shuffle operation which come from a consecutively from a zero. The
5516 /// search can start in two different directions, from left or right.
5517 /// We count undefs as zeros until PreferredNum is reached.
5518 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5519 unsigned NumElems, bool ZerosFromLeft,
5520 SelectionDAG &DAG,
5521 unsigned PreferredNum = -1U) {
5522 unsigned NumZeros = 0;
5523 for (unsigned i = 0; i != NumElems; ++i) {
5524 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5525 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5526 if (!Elt.getNode())
5527 break;
5529 if (X86::isZeroNode(Elt))
5530 ++NumZeros;
5531 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5532 NumZeros = std::min(NumZeros + 1, PreferredNum);
5533 else
5534 break;
5535 }
5537 return NumZeros;
5538 }
5540 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5541 /// correspond consecutively to elements from one of the vector operands,
5542 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5543 static
5544 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5545 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5546 unsigned NumElems, unsigned &OpNum) {
5547 bool SeenV1 = false;
5548 bool SeenV2 = false;
5550 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5551 int Idx = SVOp->getMaskElt(i);
5552 // Ignore undef indicies
5553 if (Idx < 0)
5554 continue;
5556 if (Idx < (int)NumElems)
5557 SeenV1 = true;
5558 else
5559 SeenV2 = true;
5561 // Only accept consecutive elements from the same vector
5562 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5563 return false;
5564 }
5566 OpNum = SeenV1 ? 0 : 1;
5567 return true;
5568 }
5570 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5571 /// logical left shift of a vector.
5572 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5573 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5574 unsigned NumElems =
5575 SVOp->getSimpleValueType(0).getVectorNumElements();
5576 unsigned NumZeros = getNumOfConsecutiveZeros(
5577 SVOp, NumElems, false /* check zeros from right */, DAG,
5578 SVOp->getMaskElt(0));
5579 unsigned OpSrc;
5581 if (!NumZeros)
5582 return false;
5584 // Considering the elements in the mask that are not consecutive zeros,
5585 // check if they consecutively come from only one of the source vectors.
5586 //
5587 // V1 = {X, A, B, C} 0
5588 // \ \ \ /
5589 // vector_shuffle V1, V2 <1, 2, 3, X>
5590 //
5591 if (!isShuffleMaskConsecutive(SVOp,
5592 0, // Mask Start Index
5593 NumElems-NumZeros, // Mask End Index(exclusive)
5594 NumZeros, // Where to start looking in the src vector
5595 NumElems, // Number of elements in vector
5596 OpSrc)) // Which source operand ?
5597 return false;
5599 isLeft = false;
5600 ShAmt = NumZeros;
5601 ShVal = SVOp->getOperand(OpSrc);
5602 return true;
5603 }
5605 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5606 /// logical left shift of a vector.
5607 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5608 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5609 unsigned NumElems =
5610 SVOp->getSimpleValueType(0).getVectorNumElements();
5611 unsigned NumZeros = getNumOfConsecutiveZeros(
5612 SVOp, NumElems, true /* check zeros from left */, DAG,
5613 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5614 unsigned OpSrc;
5616 if (!NumZeros)
5617 return false;
5619 // Considering the elements in the mask that are not consecutive zeros,
5620 // check if they consecutively come from only one of the source vectors.
5621 //
5622 // 0 { A, B, X, X } = V2
5623 // / \ / /
5624 // vector_shuffle V1, V2 <X, X, 4, 5>
5625 //
5626 if (!isShuffleMaskConsecutive(SVOp,
5627 NumZeros, // Mask Start Index
5628 NumElems, // Mask End Index(exclusive)
5629 0, // Where to start looking in the src vector
5630 NumElems, // Number of elements in vector
5631 OpSrc)) // Which source operand ?
5632 return false;
5634 isLeft = true;
5635 ShAmt = NumZeros;
5636 ShVal = SVOp->getOperand(OpSrc);
5637 return true;
5638 }
5640 /// isVectorShift - Returns true if the shuffle can be implemented as a
5641 /// logical left or right shift of a vector.
5642 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5643 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5644 // Although the logic below support any bitwidth size, there are no
5645 // shift instructions which handle more than 128-bit vectors.
5646 if (!SVOp->getSimpleValueType(0).is128BitVector())
5647 return false;
5649 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5650 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5651 return true;
5653 return false;
5654 }
5656 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5657 ///
5658 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5659 unsigned NumNonZero, unsigned NumZero,
5660 SelectionDAG &DAG,
5661 const X86Subtarget* Subtarget,
5662 const TargetLowering &TLI) {
5663 if (NumNonZero > 8)
5664 return SDValue();
5666 SDLoc dl(Op);
5667 SDValue V;
5668 bool First = true;
5669 for (unsigned i = 0; i < 16; ++i) {
5670 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5671 if (ThisIsNonZero && First) {
5672 if (NumZero)
5673 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5674 else
5675 V = DAG.getUNDEF(MVT::v8i16);
5676 First = false;
5677 }
5679 if ((i & 1) != 0) {
5680 SDValue ThisElt, LastElt;
5681 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5682 if (LastIsNonZero) {
5683 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5684 MVT::i16, Op.getOperand(i-1));
5685 }
5686 if (ThisIsNonZero) {
5687 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5688 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5689 ThisElt, DAG.getConstant(8, MVT::i8));
5690 if (LastIsNonZero)
5691 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5692 } else
5693 ThisElt = LastElt;
5695 if (ThisElt.getNode())
5696 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5697 DAG.getIntPtrConstant(i/2));
5698 }
5699 }
5701 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5702 }
5704 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5705 ///
5706 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5707 unsigned NumNonZero, unsigned NumZero,
5708 SelectionDAG &DAG,
5709 const X86Subtarget* Subtarget,
5710 const TargetLowering &TLI) {
5711 if (NumNonZero > 4)
5712 return SDValue();
5714 SDLoc dl(Op);
5715 SDValue V;
5716 bool First = true;
5717 for (unsigned i = 0; i < 8; ++i) {
5718 bool isNonZero = (NonZeros & (1 << i)) != 0;
5719 if (isNonZero) {
5720 if (First) {
5721 if (NumZero)
5722 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5723 else
5724 V = DAG.getUNDEF(MVT::v8i16);
5725 First = false;
5726 }
5727 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5728 MVT::v8i16, V, Op.getOperand(i),
5729 DAG.getIntPtrConstant(i));
5730 }
5731 }
5733 return V;
5734 }
5736 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5737 static SDValue LowerBuildVectorv4x32(SDValue Op, unsigned NumElems,
5738 unsigned NonZeros, unsigned NumNonZero,
5739 unsigned NumZero, SelectionDAG &DAG,
5740 const X86Subtarget *Subtarget,
5741 const TargetLowering &TLI) {
5742 // We know there's at least one non-zero element
5743 unsigned FirstNonZeroIdx = 0;
5744 SDValue FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5745 while (FirstNonZero.getOpcode() == ISD::UNDEF ||
5746 X86::isZeroNode(FirstNonZero)) {
5747 ++FirstNonZeroIdx;
5748 FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5749 }
5751 if (FirstNonZero.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5752 !isa<ConstantSDNode>(FirstNonZero.getOperand(1)))
5753 return SDValue();
5755 SDValue V = FirstNonZero.getOperand(0);
5756 MVT VVT = V.getSimpleValueType();
5757 if (!Subtarget->hasSSE41() || (VVT != MVT::v4f32 && VVT != MVT::v4i32))
5758 return SDValue();
5760 unsigned FirstNonZeroDst =
5761 cast<ConstantSDNode>(FirstNonZero.getOperand(1))->getZExtValue();
5762 unsigned CorrectIdx = FirstNonZeroDst == FirstNonZeroIdx;
5763 unsigned IncorrectIdx = CorrectIdx ? -1U : FirstNonZeroIdx;
5764 unsigned IncorrectDst = CorrectIdx ? -1U : FirstNonZeroDst;
5766 for (unsigned Idx = FirstNonZeroIdx + 1; Idx < NumElems; ++Idx) {
5767 SDValue Elem = Op.getOperand(Idx);
5768 if (Elem.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elem))
5769 continue;
5771 // TODO: What else can be here? Deal with it.
5772 if (Elem.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5773 return SDValue();
5775 // TODO: Some optimizations are still possible here
5776 // ex: Getting one element from a vector, and the rest from another.
5777 if (Elem.getOperand(0) != V)
5778 return SDValue();
5780 unsigned Dst = cast<ConstantSDNode>(Elem.getOperand(1))->getZExtValue();
5781 if (Dst == Idx)
5782 ++CorrectIdx;
5783 else if (IncorrectIdx == -1U) {
5784 IncorrectIdx = Idx;
5785 IncorrectDst = Dst;
5786 } else
5787 // There was already one element with an incorrect index.
5788 // We can't optimize this case to an insertps.
5789 return SDValue();
5790 }
5792 if (NumNonZero == CorrectIdx || NumNonZero == CorrectIdx + 1) {
5793 SDLoc dl(Op);
5794 EVT VT = Op.getSimpleValueType();
5795 unsigned ElementMoveMask = 0;
5796 if (IncorrectIdx == -1U)
5797 ElementMoveMask = FirstNonZeroIdx << 6 | FirstNonZeroIdx << 4;
5798 else
5799 ElementMoveMask = IncorrectDst << 6 | IncorrectIdx << 4;
5801 SDValue InsertpsMask =
5802 DAG.getIntPtrConstant(ElementMoveMask | (~NonZeros & 0xf));
5803 return DAG.getNode(X86ISD::INSERTPS, dl, VT, V, V, InsertpsMask);
5804 }
5806 return SDValue();
5807 }
5809 /// getVShift - Return a vector logical shift node.
5810 ///
5811 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5812 unsigned NumBits, SelectionDAG &DAG,
5813 const TargetLowering &TLI, SDLoc dl) {
5814 assert(VT.is128BitVector() && "Unknown type for VShift");
5815 EVT ShVT = MVT::v2i64;
5816 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5817 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5818 return DAG.getNode(ISD::BITCAST, dl, VT,
5819 DAG.getNode(Opc, dl, ShVT, SrcOp,
5820 DAG.getConstant(NumBits,
5821 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5822 }
5824 static SDValue
5825 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5827 // Check if the scalar load can be widened into a vector load. And if
5828 // the address is "base + cst" see if the cst can be "absorbed" into
5829 // the shuffle mask.
5830 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5831 SDValue Ptr = LD->getBasePtr();
5832 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5833 return SDValue();
5834 EVT PVT = LD->getValueType(0);
5835 if (PVT != MVT::i32 && PVT != MVT::f32)
5836 return SDValue();
5838 int FI = -1;
5839 int64_t Offset = 0;
5840 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5841 FI = FINode->getIndex();
5842 Offset = 0;
5843 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5844 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5845 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5846 Offset = Ptr.getConstantOperandVal(1);
5847 Ptr = Ptr.getOperand(0);
5848 } else {
5849 return SDValue();
5850 }
5852 // FIXME: 256-bit vector instructions don't require a strict alignment,
5853 // improve this code to support it better.
5854 unsigned RequiredAlign = VT.getSizeInBits()/8;
5855 SDValue Chain = LD->getChain();
5856 // Make sure the stack object alignment is at least 16 or 32.
5857 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5858 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5859 if (MFI->isFixedObjectIndex(FI)) {
5860 // Can't change the alignment. FIXME: It's possible to compute
5861 // the exact stack offset and reference FI + adjust offset instead.
5862 // If someone *really* cares about this. That's the way to implement it.
5863 return SDValue();
5864 } else {
5865 MFI->setObjectAlignment(FI, RequiredAlign);
5866 }
5867 }
5869 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5870 // Ptr + (Offset & ~15).
5871 if (Offset < 0)
5872 return SDValue();
5873 if ((Offset % RequiredAlign) & 3)
5874 return SDValue();
5875 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5876 if (StartOffset)
5877 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5878 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5880 int EltNo = (Offset - StartOffset) >> 2;
5881 unsigned NumElems = VT.getVectorNumElements();
5883 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5884 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5885 LD->getPointerInfo().getWithOffset(StartOffset),
5886 false, false, false, 0);
5888 SmallVector<int, 8> Mask;
5889 for (unsigned i = 0; i != NumElems; ++i)
5890 Mask.push_back(EltNo);
5892 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5893 }
5895 return SDValue();
5896 }
5898 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5899 /// vector of type 'VT', see if the elements can be replaced by a single large
5900 /// load which has the same value as a build_vector whose operands are 'elts'.
5901 ///
5902 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5903 ///
5904 /// FIXME: we'd also like to handle the case where the last elements are zero
5905 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5906 /// There's even a handy isZeroNode for that purpose.
5907 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5908 SDLoc &DL, SelectionDAG &DAG,
5909 bool isAfterLegalize) {
5910 EVT EltVT = VT.getVectorElementType();
5911 unsigned NumElems = Elts.size();
5913 LoadSDNode *LDBase = nullptr;
5914 unsigned LastLoadedElt = -1U;
5916 // For each element in the initializer, see if we've found a load or an undef.
5917 // If we don't find an initial load element, or later load elements are
5918 // non-consecutive, bail out.
5919 for (unsigned i = 0; i < NumElems; ++i) {
5920 SDValue Elt = Elts[i];
5922 if (!Elt.getNode() ||
5923 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5924 return SDValue();
5925 if (!LDBase) {
5926 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5927 return SDValue();
5928 LDBase = cast<LoadSDNode>(Elt.getNode());
5929 LastLoadedElt = i;
5930 continue;
5931 }
5932 if (Elt.getOpcode() == ISD::UNDEF)
5933 continue;
5935 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5936 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5937 return SDValue();
5938 LastLoadedElt = i;
5939 }
5941 // If we have found an entire vector of loads and undefs, then return a large
5942 // load of the entire vector width starting at the base pointer. If we found
5943 // consecutive loads for the low half, generate a vzext_load node.
5944 if (LastLoadedElt == NumElems - 1) {
5946 if (isAfterLegalize &&
5947 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5948 return SDValue();
5950 SDValue NewLd = SDValue();
5952 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5953 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5954 LDBase->getPointerInfo(),
5955 LDBase->isVolatile(), LDBase->isNonTemporal(),
5956 LDBase->isInvariant(), 0);
5957 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5958 LDBase->getPointerInfo(),
5959 LDBase->isVolatile(), LDBase->isNonTemporal(),
5960 LDBase->isInvariant(), LDBase->getAlignment());
5962 if (LDBase->hasAnyUseOfValue(1)) {
5963 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5964 SDValue(LDBase, 1),
5965 SDValue(NewLd.getNode(), 1));
5966 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5967 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5968 SDValue(NewLd.getNode(), 1));
5969 }
5971 return NewLd;
5972 }
5973 if (NumElems == 4 && LastLoadedElt == 1 &&
5974 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5975 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5976 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5977 SDValue ResNode =
5978 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5979 LDBase->getPointerInfo(),
5980 LDBase->getAlignment(),
5981 false/*isVolatile*/, true/*ReadMem*/,
5982 false/*WriteMem*/);
5984 // Make sure the newly-created LOAD is in the same position as LDBase in
5985 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5986 // update uses of LDBase's output chain to use the TokenFactor.
5987 if (LDBase->hasAnyUseOfValue(1)) {
5988 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5989 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5990 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5991 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5992 SDValue(ResNode.getNode(), 1));
5993 }
5995 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5996 }
5997 return SDValue();
5998 }
6000 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
6001 /// to generate a splat value for the following cases:
6002 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
6003 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
6004 /// a scalar load, or a constant.
6005 /// The VBROADCAST node is returned when a pattern is found,
6006 /// or SDValue() otherwise.
6007 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
6008 SelectionDAG &DAG) {
6009 // VBROADCAST requires AVX.
6010 // TODO: Splats could be generated for non-AVX CPUs using SSE
6011 // instructions, but there's less potential gain for only 128-bit vectors.
6012 if (!Subtarget->hasAVX())
6013 return SDValue();
6015 MVT VT = Op.getSimpleValueType();
6016 SDLoc dl(Op);
6018 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6019 "Unsupported vector type for broadcast.");
6021 SDValue Ld;
6022 bool ConstSplatVal;
6024 switch (Op.getOpcode()) {
6025 default:
6026 // Unknown pattern found.
6027 return SDValue();
6029 case ISD::BUILD_VECTOR: {
6030 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6031 BitVector UndefElements;
6032 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6034 // We need a splat of a single value to use broadcast, and it doesn't
6035 // make any sense if the value is only in one element of the vector.
6036 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6037 return SDValue();
6039 Ld = Splat;
6040 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6041 Ld.getOpcode() == ISD::ConstantFP);
6043 // Make sure that all of the users of a non-constant load are from the
6044 // BUILD_VECTOR node.
6045 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6046 return SDValue();
6047 break;
6048 }
6050 case ISD::VECTOR_SHUFFLE: {
6051 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6053 // Shuffles must have a splat mask where the first element is
6054 // broadcasted.
6055 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6056 return SDValue();
6058 SDValue Sc = Op.getOperand(0);
6059 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6060 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6062 if (!Subtarget->hasInt256())
6063 return SDValue();
6065 // Use the register form of the broadcast instruction available on AVX2.
6066 if (VT.getSizeInBits() >= 256)
6067 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6068 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6069 }
6071 Ld = Sc.getOperand(0);
6072 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6073 Ld.getOpcode() == ISD::ConstantFP);
6075 // The scalar_to_vector node and the suspected
6076 // load node must have exactly one user.
6077 // Constants may have multiple users.
6079 // AVX-512 has register version of the broadcast
6080 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6081 Ld.getValueType().getSizeInBits() >= 32;
6082 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6083 !hasRegVer))
6084 return SDValue();
6085 break;
6086 }
6087 }
6089 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6090 bool IsGE256 = (VT.getSizeInBits() >= 256);
6092 // When optimizing for size, generate up to 5 extra bytes for a broadcast
6093 // instruction to save 8 or more bytes of constant pool data.
6094 // TODO: If multiple splats are generated to load the same constant,
6095 // it may be detrimental to overall size. There needs to be a way to detect
6096 // that condition to know if this is truly a size win.
6097 const Function *F = DAG.getMachineFunction().getFunction();
6098 bool OptForSize = F->getAttributes().
6099 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6101 // Handle broadcasting a single constant scalar from the constant pool
6102 // into a vector.
6103 // On Sandybridge (no AVX2), it is still better to load a constant vector
6104 // from the constant pool and not to broadcast it from a scalar.
6105 // But override that restriction when optimizing for size.
6106 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
6107 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
6108 EVT CVT = Ld.getValueType();
6109 assert(!CVT.isVector() && "Must not broadcast a vector type");
6111 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
6112 // For size optimization, also splat v2f64 and v2i64, and for size opt
6113 // with AVX2, also splat i8 and i16.
6114 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
6115 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6116 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
6117 const Constant *C = nullptr;
6118 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6119 C = CI->getConstantIntValue();
6120 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6121 C = CF->getConstantFPValue();
6123 assert(C && "Invalid constant type");
6125 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6126 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6127 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6128 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6129 MachinePointerInfo::getConstantPool(),
6130 false, false, false, Alignment);
6132 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6133 }
6134 }
6136 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6138 // Handle AVX2 in-register broadcasts.
6139 if (!IsLoad && Subtarget->hasInt256() &&
6140 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6141 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6143 // The scalar source must be a normal load.
6144 if (!IsLoad)
6145 return SDValue();
6147 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
6148 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6150 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6151 // double since there is no vbroadcastsd xmm
6152 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6153 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6154 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6155 }
6157 // Unsupported broadcast.
6158 return SDValue();
6159 }
6161 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6162 /// underlying vector and index.
6163 ///
6164 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6165 /// index.
6166 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6167 SDValue ExtIdx) {
6168 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6169 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6170 return Idx;
6172 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6173 // lowered this:
6174 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6175 // to:
6176 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6177 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6178 // undef)
6179 // Constant<0>)
6180 // In this case the vector is the extract_subvector expression and the index
6181 // is 2, as specified by the shuffle.
6182 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6183 SDValue ShuffleVec = SVOp->getOperand(0);
6184 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6185 assert(ShuffleVecVT.getVectorElementType() ==
6186 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6188 int ShuffleIdx = SVOp->getMaskElt(Idx);
6189 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6190 ExtractedFromVec = ShuffleVec;
6191 return ShuffleIdx;
6192 }
6193 return Idx;
6194 }
6196 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6197 MVT VT = Op.getSimpleValueType();
6199 // Skip if insert_vec_elt is not supported.
6200 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6201 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6202 return SDValue();
6204 SDLoc DL(Op);
6205 unsigned NumElems = Op.getNumOperands();
6207 SDValue VecIn1;
6208 SDValue VecIn2;
6209 SmallVector<unsigned, 4> InsertIndices;
6210 SmallVector<int, 8> Mask(NumElems, -1);
6212 for (unsigned i = 0; i != NumElems; ++i) {
6213 unsigned Opc = Op.getOperand(i).getOpcode();
6215 if (Opc == ISD::UNDEF)
6216 continue;
6218 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6219 // Quit if more than 1 elements need inserting.
6220 if (InsertIndices.size() > 1)
6221 return SDValue();
6223 InsertIndices.push_back(i);
6224 continue;
6225 }
6227 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6228 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6229 // Quit if non-constant index.
6230 if (!isa<ConstantSDNode>(ExtIdx))
6231 return SDValue();
6232 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6234 // Quit if extracted from vector of different type.
6235 if (ExtractedFromVec.getValueType() != VT)
6236 return SDValue();
6238 if (!VecIn1.getNode())
6239 VecIn1 = ExtractedFromVec;
6240 else if (VecIn1 != ExtractedFromVec) {
6241 if (!VecIn2.getNode())
6242 VecIn2 = ExtractedFromVec;
6243 else if (VecIn2 != ExtractedFromVec)
6244 // Quit if more than 2 vectors to shuffle
6245 return SDValue();
6246 }
6248 if (ExtractedFromVec == VecIn1)
6249 Mask[i] = Idx;
6250 else if (ExtractedFromVec == VecIn2)
6251 Mask[i] = Idx + NumElems;
6252 }
6254 if (!VecIn1.getNode())
6255 return SDValue();
6257 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6258 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6259 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6260 unsigned Idx = InsertIndices[i];
6261 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6262 DAG.getIntPtrConstant(Idx));
6263 }
6265 return NV;
6266 }
6268 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6269 SDValue
6270 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6272 MVT VT = Op.getSimpleValueType();
6273 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6274 "Unexpected type in LowerBUILD_VECTORvXi1!");
6276 SDLoc dl(Op);
6277 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6278 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6279 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6280 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6281 }
6283 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6284 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6285 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6286 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6287 }
6289 bool AllContants = true;
6290 uint64_t Immediate = 0;
6291 int NonConstIdx = -1;
6292 bool IsSplat = true;
6293 unsigned NumNonConsts = 0;
6294 unsigned NumConsts = 0;
6295 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6296 SDValue In = Op.getOperand(idx);
6297 if (In.getOpcode() == ISD::UNDEF)
6298 continue;
6299 if (!isa<ConstantSDNode>(In)) {
6300 AllContants = false;
6301 NonConstIdx = idx;
6302 NumNonConsts++;
6303 }
6304 else {
6305 NumConsts++;
6306 if (cast<ConstantSDNode>(In)->getZExtValue())
6307 Immediate |= (1ULL << idx);
6308 }
6309 if (In != Op.getOperand(0))
6310 IsSplat = false;
6311 }
6313 if (AllContants) {
6314 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6315 DAG.getConstant(Immediate, MVT::i16));
6316 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6317 DAG.getIntPtrConstant(0));
6318 }
6320 if (NumNonConsts == 1 && NonConstIdx != 0) {
6321 SDValue DstVec;
6322 if (NumConsts) {
6323 SDValue VecAsImm = DAG.getConstant(Immediate,
6324 MVT::getIntegerVT(VT.getSizeInBits()));
6325 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6326 }
6327 else
6328 DstVec = DAG.getUNDEF(VT);
6329 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6330 Op.getOperand(NonConstIdx),
6331 DAG.getIntPtrConstant(NonConstIdx));
6332 }
6333 if (!IsSplat && (NonConstIdx != 0))
6334 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6335 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6336 SDValue Select;
6337 if (IsSplat)
6338 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6339 DAG.getConstant(-1, SelectVT),
6340 DAG.getConstant(0, SelectVT));
6341 else
6342 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6343 DAG.getConstant((Immediate | 1), SelectVT),
6344 DAG.getConstant(Immediate, SelectVT));
6345 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6346 }
6348 /// \brief Return true if \p N implements a horizontal binop and return the
6349 /// operands for the horizontal binop into V0 and V1.
6350 ///
6351 /// This is a helper function of PerformBUILD_VECTORCombine.
6352 /// This function checks that the build_vector \p N in input implements a
6353 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6354 /// operation to match.
6355 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6356 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6357 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6358 /// arithmetic sub.
6359 ///
6360 /// This function only analyzes elements of \p N whose indices are
6361 /// in range [BaseIdx, LastIdx).
6362 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6363 SelectionDAG &DAG,
6364 unsigned BaseIdx, unsigned LastIdx,
6365 SDValue &V0, SDValue &V1) {
6366 EVT VT = N->getValueType(0);
6368 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6369 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6370 "Invalid Vector in input!");
6372 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6373 bool CanFold = true;
6374 unsigned ExpectedVExtractIdx = BaseIdx;
6375 unsigned NumElts = LastIdx - BaseIdx;
6376 V0 = DAG.getUNDEF(VT);
6377 V1 = DAG.getUNDEF(VT);
6379 // Check if N implements a horizontal binop.
6380 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6381 SDValue Op = N->getOperand(i + BaseIdx);
6383 // Skip UNDEFs.
6384 if (Op->getOpcode() == ISD::UNDEF) {
6385 // Update the expected vector extract index.
6386 if (i * 2 == NumElts)
6387 ExpectedVExtractIdx = BaseIdx;
6388 ExpectedVExtractIdx += 2;
6389 continue;
6390 }
6392 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6394 if (!CanFold)
6395 break;
6397 SDValue Op0 = Op.getOperand(0);
6398 SDValue Op1 = Op.getOperand(1);
6400 // Try to match the following pattern:
6401 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6402 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6403 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6404 Op0.getOperand(0) == Op1.getOperand(0) &&
6405 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6406 isa<ConstantSDNode>(Op1.getOperand(1)));
6407 if (!CanFold)
6408 break;
6410 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6411 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6413 if (i * 2 < NumElts) {
6414 if (V0.getOpcode() == ISD::UNDEF)
6415 V0 = Op0.getOperand(0);
6416 } else {
6417 if (V1.getOpcode() == ISD::UNDEF)
6418 V1 = Op0.getOperand(0);
6419 if (i * 2 == NumElts)
6420 ExpectedVExtractIdx = BaseIdx;
6421 }
6423 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6424 if (I0 == ExpectedVExtractIdx)
6425 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6426 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6427 // Try to match the following dag sequence:
6428 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6429 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6430 } else
6431 CanFold = false;
6433 ExpectedVExtractIdx += 2;
6434 }
6436 return CanFold;
6437 }
6439 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6440 /// a concat_vector.
6441 ///
6442 /// This is a helper function of PerformBUILD_VECTORCombine.
6443 /// This function expects two 256-bit vectors called V0 and V1.
6444 /// At first, each vector is split into two separate 128-bit vectors.
6445 /// Then, the resulting 128-bit vectors are used to implement two
6446 /// horizontal binary operations.
6447 ///
6448 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6449 ///
6450 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6451 /// the two new horizontal binop.
6452 /// When Mode is set, the first horizontal binop dag node would take as input
6453 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6454 /// horizontal binop dag node would take as input the lower 128-bit of V1
6455 /// and the upper 128-bit of V1.
6456 /// Example:
6457 /// HADD V0_LO, V0_HI
6458 /// HADD V1_LO, V1_HI
6459 ///
6460 /// Otherwise, the first horizontal binop dag node takes as input the lower
6461 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6462 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6463 /// Example:
6464 /// HADD V0_LO, V1_LO
6465 /// HADD V0_HI, V1_HI
6466 ///
6467 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6468 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6469 /// the upper 128-bits of the result.
6470 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6471 SDLoc DL, SelectionDAG &DAG,
6472 unsigned X86Opcode, bool Mode,
6473 bool isUndefLO, bool isUndefHI) {
6474 EVT VT = V0.getValueType();
6475 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6476 "Invalid nodes in input!");
6478 unsigned NumElts = VT.getVectorNumElements();
6479 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6480 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6481 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6482 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6483 EVT NewVT = V0_LO.getValueType();
6485 SDValue LO = DAG.getUNDEF(NewVT);
6486 SDValue HI = DAG.getUNDEF(NewVT);
6488 if (Mode) {
6489 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6490 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6491 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6492 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6493 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6494 } else {
6495 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6496 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6497 V1_LO->getOpcode() != ISD::UNDEF))
6498 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6500 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6501 V1_HI->getOpcode() != ISD::UNDEF))
6502 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6503 }
6505 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6506 }
6508 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6509 /// sequence of 'vadd + vsub + blendi'.
6510 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6511 const X86Subtarget *Subtarget) {
6512 SDLoc DL(BV);
6513 EVT VT = BV->getValueType(0);
6514 unsigned NumElts = VT.getVectorNumElements();
6515 SDValue InVec0 = DAG.getUNDEF(VT);
6516 SDValue InVec1 = DAG.getUNDEF(VT);
6518 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6519 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6521 // Odd-numbered elements in the input build vector are obtained from
6522 // adding two integer/float elements.
6523 // Even-numbered elements in the input build vector are obtained from
6524 // subtracting two integer/float elements.
6525 unsigned ExpectedOpcode = ISD::FSUB;
6526 unsigned NextExpectedOpcode = ISD::FADD;
6527 bool AddFound = false;
6528 bool SubFound = false;
6530 for (unsigned i = 0, e = NumElts; i != e; i++) {
6531 SDValue Op = BV->getOperand(i);
6533 // Skip 'undef' values.
6534 unsigned Opcode = Op.getOpcode();
6535 if (Opcode == ISD::UNDEF) {
6536 std::swap(ExpectedOpcode, NextExpectedOpcode);
6537 continue;
6538 }
6540 // Early exit if we found an unexpected opcode.
6541 if (Opcode != ExpectedOpcode)
6542 return SDValue();
6544 SDValue Op0 = Op.getOperand(0);
6545 SDValue Op1 = Op.getOperand(1);
6547 // Try to match the following pattern:
6548 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6549 // Early exit if we cannot match that sequence.
6550 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6551 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6552 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6553 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6554 Op0.getOperand(1) != Op1.getOperand(1))
6555 return SDValue();
6557 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6558 if (I0 != i)
6559 return SDValue();
6561 // We found a valid add/sub node. Update the information accordingly.
6562 if (i & 1)
6563 AddFound = true;
6564 else
6565 SubFound = true;
6567 // Update InVec0 and InVec1.
6568 if (InVec0.getOpcode() == ISD::UNDEF)
6569 InVec0 = Op0.getOperand(0);
6570 if (InVec1.getOpcode() == ISD::UNDEF)
6571 InVec1 = Op1.getOperand(0);
6573 // Make sure that operands in input to each add/sub node always
6574 // come from a same pair of vectors.
6575 if (InVec0 != Op0.getOperand(0)) {
6576 if (ExpectedOpcode == ISD::FSUB)
6577 return SDValue();
6579 // FADD is commutable. Try to commute the operands
6580 // and then test again.
6581 std::swap(Op0, Op1);
6582 if (InVec0 != Op0.getOperand(0))
6583 return SDValue();
6584 }
6586 if (InVec1 != Op1.getOperand(0))
6587 return SDValue();
6589 // Update the pair of expected opcodes.
6590 std::swap(ExpectedOpcode, NextExpectedOpcode);
6591 }
6593 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6594 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6595 InVec1.getOpcode() != ISD::UNDEF)
6596 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6598 return SDValue();
6599 }
6601 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6602 const X86Subtarget *Subtarget) {
6603 SDLoc DL(N);
6604 EVT VT = N->getValueType(0);
6605 unsigned NumElts = VT.getVectorNumElements();
6606 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6607 SDValue InVec0, InVec1;
6609 // Try to match an ADDSUB.
6610 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6611 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6612 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6613 if (Value.getNode())
6614 return Value;
6615 }
6617 // Try to match horizontal ADD/SUB.
6618 unsigned NumUndefsLO = 0;
6619 unsigned NumUndefsHI = 0;
6620 unsigned Half = NumElts/2;
6622 // Count the number of UNDEF operands in the build_vector in input.
6623 for (unsigned i = 0, e = Half; i != e; ++i)
6624 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6625 NumUndefsLO++;
6627 for (unsigned i = Half, e = NumElts; i != e; ++i)
6628 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6629 NumUndefsHI++;
6631 // Early exit if this is either a build_vector of all UNDEFs or all the
6632 // operands but one are UNDEF.
6633 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6634 return SDValue();
6636 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6637 // Try to match an SSE3 float HADD/HSUB.
6638 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6639 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6641 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6642 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6643 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6644 // Try to match an SSSE3 integer HADD/HSUB.
6645 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6646 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6648 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6649 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6650 }
6652 if (!Subtarget->hasAVX())
6653 return SDValue();
6655 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6656 // Try to match an AVX horizontal add/sub of packed single/double
6657 // precision floating point values from 256-bit vectors.
6658 SDValue InVec2, InVec3;
6659 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6660 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6661 ((InVec0.getOpcode() == ISD::UNDEF ||
6662 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6663 ((InVec1.getOpcode() == ISD::UNDEF ||
6664 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6665 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6667 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6668 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6669 ((InVec0.getOpcode() == ISD::UNDEF ||
6670 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6671 ((InVec1.getOpcode() == ISD::UNDEF ||
6672 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6673 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6674 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6675 // Try to match an AVX2 horizontal add/sub of signed integers.
6676 SDValue InVec2, InVec3;
6677 unsigned X86Opcode;
6678 bool CanFold = true;
6680 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6681 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6682 ((InVec0.getOpcode() == ISD::UNDEF ||
6683 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6684 ((InVec1.getOpcode() == ISD::UNDEF ||
6685 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6686 X86Opcode = X86ISD::HADD;
6687 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6688 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6689 ((InVec0.getOpcode() == ISD::UNDEF ||
6690 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6691 ((InVec1.getOpcode() == ISD::UNDEF ||
6692 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6693 X86Opcode = X86ISD::HSUB;
6694 else
6695 CanFold = false;
6697 if (CanFold) {
6698 // Fold this build_vector into a single horizontal add/sub.
6699 // Do this only if the target has AVX2.
6700 if (Subtarget->hasAVX2())
6701 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6703 // Do not try to expand this build_vector into a pair of horizontal
6704 // add/sub if we can emit a pair of scalar add/sub.
6705 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6706 return SDValue();
6708 // Convert this build_vector into a pair of horizontal binop followed by
6709 // a concat vector.
6710 bool isUndefLO = NumUndefsLO == Half;
6711 bool isUndefHI = NumUndefsHI == Half;
6712 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6713 isUndefLO, isUndefHI);
6714 }
6715 }
6717 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6718 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6719 unsigned X86Opcode;
6720 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6721 X86Opcode = X86ISD::HADD;
6722 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6723 X86Opcode = X86ISD::HSUB;
6724 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6725 X86Opcode = X86ISD::FHADD;
6726 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6727 X86Opcode = X86ISD::FHSUB;
6728 else
6729 return SDValue();
6731 // Don't try to expand this build_vector into a pair of horizontal add/sub
6732 // if we can simply emit a pair of scalar add/sub.
6733 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6734 return SDValue();
6736 // Convert this build_vector into two horizontal add/sub followed by
6737 // a concat vector.
6738 bool isUndefLO = NumUndefsLO == Half;
6739 bool isUndefHI = NumUndefsHI == Half;
6740 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6741 isUndefLO, isUndefHI);
6742 }
6744 return SDValue();
6745 }
6747 SDValue
6748 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6749 SDLoc dl(Op);
6751 MVT VT = Op.getSimpleValueType();
6752 MVT ExtVT = VT.getVectorElementType();
6753 unsigned NumElems = Op.getNumOperands();
6755 // Generate vectors for predicate vectors.
6756 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6757 return LowerBUILD_VECTORvXi1(Op, DAG);
6759 // Vectors containing all zeros can be matched by pxor and xorps later
6760 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6761 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6762 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6763 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6764 return Op;
6766 return getZeroVector(VT, Subtarget, DAG, dl);
6767 }
6769 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6770 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6771 // vpcmpeqd on 256-bit vectors.
6772 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6773 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6774 return Op;
6776 if (!VT.is512BitVector())
6777 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6778 }
6780 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6781 if (Broadcast.getNode())
6782 return Broadcast;
6784 unsigned EVTBits = ExtVT.getSizeInBits();
6786 unsigned NumZero = 0;
6787 unsigned NumNonZero = 0;
6788 unsigned NonZeros = 0;
6789 bool IsAllConstants = true;
6790 SmallSet<SDValue, 8> Values;
6791 for (unsigned i = 0; i < NumElems; ++i) {
6792 SDValue Elt = Op.getOperand(i);
6793 if (Elt.getOpcode() == ISD::UNDEF)
6794 continue;
6795 Values.insert(Elt);
6796 if (Elt.getOpcode() != ISD::Constant &&
6797 Elt.getOpcode() != ISD::ConstantFP)
6798 IsAllConstants = false;
6799 if (X86::isZeroNode(Elt))
6800 NumZero++;
6801 else {
6802 NonZeros |= (1 << i);
6803 NumNonZero++;
6804 }
6805 }
6807 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6808 if (NumNonZero == 0)
6809 return DAG.getUNDEF(VT);
6811 // Special case for single non-zero, non-undef, element.
6812 if (NumNonZero == 1) {
6813 unsigned Idx = countTrailingZeros(NonZeros);
6814 SDValue Item = Op.getOperand(Idx);
6816 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6817 // the value are obviously zero, truncate the value to i32 and do the
6818 // insertion that way. Only do this if the value is non-constant or if the
6819 // value is a constant being inserted into element 0. It is cheaper to do
6820 // a constant pool load than it is to do a movd + shuffle.
6821 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6822 (!IsAllConstants || Idx == 0)) {
6823 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6824 // Handle SSE only.
6825 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6826 EVT VecVT = MVT::v4i32;
6827 unsigned VecElts = 4;
6829 // Truncate the value (which may itself be a constant) to i32, and
6830 // convert it to a vector with movd (S2V+shuffle to zero extend).
6831 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6832 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6834 // If using the new shuffle lowering, just directly insert this.
6835 if (ExperimentalVectorShuffleLowering)
6836 return DAG.getNode(
6837 ISD::BITCAST, dl, VT,
6838 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6840 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6842 // Now we have our 32-bit value zero extended in the low element of
6843 // a vector. If Idx != 0, swizzle it into place.
6844 if (Idx != 0) {
6845 SmallVector<int, 4> Mask;
6846 Mask.push_back(Idx);
6847 for (unsigned i = 1; i != VecElts; ++i)
6848 Mask.push_back(i);
6849 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6850 &Mask[0]);
6851 }
6852 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6853 }
6854 }
6856 // If we have a constant or non-constant insertion into the low element of
6857 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6858 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6859 // depending on what the source datatype is.
6860 if (Idx == 0) {
6861 if (NumZero == 0)
6862 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6864 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6865 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6866 if (VT.is256BitVector() || VT.is512BitVector()) {
6867 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6868 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6869 Item, DAG.getIntPtrConstant(0));
6870 }
6871 assert(VT.is128BitVector() && "Expected an SSE value type!");
6872 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6873 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6874 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6875 }
6877 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6878 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6879 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6880 if (VT.is256BitVector()) {
6881 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6882 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6883 } else {
6884 assert(VT.is128BitVector() && "Expected an SSE value type!");
6885 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6886 }
6887 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6888 }
6889 }
6891 // Is it a vector logical left shift?
6892 if (NumElems == 2 && Idx == 1 &&
6893 X86::isZeroNode(Op.getOperand(0)) &&
6894 !X86::isZeroNode(Op.getOperand(1))) {
6895 unsigned NumBits = VT.getSizeInBits();
6896 return getVShift(true, VT,
6897 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6898 VT, Op.getOperand(1)),
6899 NumBits/2, DAG, *this, dl);
6900 }
6902 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6903 return SDValue();
6905 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6906 // is a non-constant being inserted into an element other than the low one,
6907 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6908 // movd/movss) to move this into the low element, then shuffle it into
6909 // place.
6910 if (EVTBits == 32) {
6911 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6913 // If using the new shuffle lowering, just directly insert this.
6914 if (ExperimentalVectorShuffleLowering)
6915 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6917 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6918 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6919 SmallVector<int, 8> MaskVec;
6920 for (unsigned i = 0; i != NumElems; ++i)
6921 MaskVec.push_back(i == Idx ? 0 : 1);
6922 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6923 }
6924 }
6926 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6927 if (Values.size() == 1) {
6928 if (EVTBits == 32) {
6929 // Instead of a shuffle like this:
6930 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6931 // Check if it's possible to issue this instead.
6932 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6933 unsigned Idx = countTrailingZeros(NonZeros);
6934 SDValue Item = Op.getOperand(Idx);
6935 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6936 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6937 }
6938 return SDValue();
6939 }
6941 // A vector full of immediates; various special cases are already
6942 // handled, so this is best done with a single constant-pool load.
6943 if (IsAllConstants)
6944 return SDValue();
6946 // For AVX-length vectors, build the individual 128-bit pieces and use
6947 // shuffles to put them in place.
6948 if (VT.is256BitVector() || VT.is512BitVector()) {
6949 SmallVector<SDValue, 64> V;
6950 for (unsigned i = 0; i != NumElems; ++i)
6951 V.push_back(Op.getOperand(i));
6953 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6955 // Build both the lower and upper subvector.
6956 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6957 makeArrayRef(&V[0], NumElems/2));
6958 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6959 makeArrayRef(&V[NumElems / 2], NumElems/2));
6961 // Recreate the wider vector with the lower and upper part.
6962 if (VT.is256BitVector())
6963 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6964 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6965 }
6967 // Let legalizer expand 2-wide build_vectors.
6968 if (EVTBits == 64) {
6969 if (NumNonZero == 1) {
6970 // One half is zero or undef.
6971 unsigned Idx = countTrailingZeros(NonZeros);
6972 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6973 Op.getOperand(Idx));
6974 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6975 }
6976 return SDValue();
6977 }
6979 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6980 if (EVTBits == 8 && NumElems == 16) {
6981 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6982 Subtarget, *this);
6983 if (V.getNode()) return V;
6984 }
6986 if (EVTBits == 16 && NumElems == 8) {
6987 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6988 Subtarget, *this);
6989 if (V.getNode()) return V;
6990 }
6992 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6993 if (EVTBits == 32 && NumElems == 4) {
6994 SDValue V = LowerBuildVectorv4x32(Op, NumElems, NonZeros, NumNonZero,
6995 NumZero, DAG, Subtarget, *this);
6996 if (V.getNode())
6997 return V;
6998 }
7000 // If element VT is == 32 bits, turn it into a number of shuffles.
7001 SmallVector<SDValue, 8> V(NumElems);
7002 if (NumElems == 4 && NumZero > 0) {
7003 for (unsigned i = 0; i < 4; ++i) {
7004 bool isZero = !(NonZeros & (1 << i));
7005 if (isZero)
7006 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
7007 else
7008 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7009 }
7011 for (unsigned i = 0; i < 2; ++i) {
7012 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7013 default: break;
7014 case 0:
7015 V[i] = V[i*2]; // Must be a zero vector.
7016 break;
7017 case 1:
7018 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7019 break;
7020 case 2:
7021 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7022 break;
7023 case 3:
7024 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7025 break;
7026 }
7027 }
7029 bool Reverse1 = (NonZeros & 0x3) == 2;
7030 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7031 int MaskVec[] = {
7032 Reverse1 ? 1 : 0,
7033 Reverse1 ? 0 : 1,
7034 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7035 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7036 };
7037 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7038 }
7040 if (Values.size() > 1 && VT.is128BitVector()) {
7041 // Check for a build vector of consecutive loads.
7042 for (unsigned i = 0; i < NumElems; ++i)
7043 V[i] = Op.getOperand(i);
7045 // Check for elements which are consecutive loads.
7046 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7047 if (LD.getNode())
7048 return LD;
7050 // Check for a build vector from mostly shuffle plus few inserting.
7051 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7052 if (Sh.getNode())
7053 return Sh;
7055 // For SSE 4.1, use insertps to put the high elements into the low element.
7056 if (getSubtarget()->hasSSE41()) {
7057 SDValue Result;
7058 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7059 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7060 else
7061 Result = DAG.getUNDEF(VT);
7063 for (unsigned i = 1; i < NumElems; ++i) {
7064 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7065 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7066 Op.getOperand(i), DAG.getIntPtrConstant(i));
7067 }
7068 return Result;
7069 }
7071 // Otherwise, expand into a number of unpckl*, start by extending each of
7072 // our (non-undef) elements to the full vector width with the element in the
7073 // bottom slot of the vector (which generates no code for SSE).
7074 for (unsigned i = 0; i < NumElems; ++i) {
7075 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7076 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7077 else
7078 V[i] = DAG.getUNDEF(VT);
7079 }
7081 // Next, we iteratively mix elements, e.g. for v4f32:
7082 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7083 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7084 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7085 unsigned EltStride = NumElems >> 1;
7086 while (EltStride != 0) {
7087 for (unsigned i = 0; i < EltStride; ++i) {
7088 // If V[i+EltStride] is undef and this is the first round of mixing,
7089 // then it is safe to just drop this shuffle: V[i] is already in the
7090 // right place, the one element (since it's the first round) being
7091 // inserted as undef can be dropped. This isn't safe for successive
7092 // rounds because they will permute elements within both vectors.
7093 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7094 EltStride == NumElems/2)
7095 continue;
7097 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7098 }
7099 EltStride >>= 1;
7100 }
7101 return V[0];
7102 }
7103 return SDValue();
7104 }
7106 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7107 // to create 256-bit vectors from two other 128-bit ones.
7108 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7109 SDLoc dl(Op);
7110 MVT ResVT = Op.getSimpleValueType();
7112 assert((ResVT.is256BitVector() ||
7113 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7115 SDValue V1 = Op.getOperand(0);
7116 SDValue V2 = Op.getOperand(1);
7117 unsigned NumElems = ResVT.getVectorNumElements();
7118 if(ResVT.is256BitVector())
7119 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7121 if (Op.getNumOperands() == 4) {
7122 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7123 ResVT.getVectorNumElements()/2);
7124 SDValue V3 = Op.getOperand(2);
7125 SDValue V4 = Op.getOperand(3);
7126 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7127 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7128 }
7129 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7130 }
7132 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7133 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7134 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7135 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7136 Op.getNumOperands() == 4)));
7138 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7139 // from two other 128-bit ones.
7141 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7142 return LowerAVXCONCAT_VECTORS(Op, DAG);
7143 }
7146 //===----------------------------------------------------------------------===//
7147 // Vector shuffle lowering
7148 //
7149 // This is an experimental code path for lowering vector shuffles on x86. It is
7150 // designed to handle arbitrary vector shuffles and blends, gracefully
7151 // degrading performance as necessary. It works hard to recognize idiomatic
7152 // shuffles and lower them to optimal instruction patterns without leaving
7153 // a framework that allows reasonably efficient handling of all vector shuffle
7154 // patterns.
7155 //===----------------------------------------------------------------------===//
7157 /// \brief Tiny helper function to identify a no-op mask.
7158 ///
7159 /// This is a somewhat boring predicate function. It checks whether the mask
7160 /// array input, which is assumed to be a single-input shuffle mask of the kind
7161 /// used by the X86 shuffle instructions (not a fully general
7162 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7163 /// in-place shuffle are 'no-op's.
7164 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7165 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7166 if (Mask[i] != -1 && Mask[i] != i)
7167 return false;
7168 return true;
7169 }
7171 /// \brief Helper function to classify a mask as a single-input mask.
7172 ///
7173 /// This isn't a generic single-input test because in the vector shuffle
7174 /// lowering we canonicalize single inputs to be the first input operand. This
7175 /// means we can more quickly test for a single input by only checking whether
7176 /// an input from the second operand exists. We also assume that the size of
7177 /// mask corresponds to the size of the input vectors which isn't true in the
7178 /// fully general case.
7179 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7180 for (int M : Mask)
7181 if (M >= (int)Mask.size())
7182 return false;
7183 return true;
7184 }
7186 /// \brief Test whether there are elements crossing 128-bit lanes in this
7187 /// shuffle mask.
7188 ///
7189 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
7190 /// and we routinely test for these.
7191 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
7192 int LaneSize = 128 / VT.getScalarSizeInBits();
7193 int Size = Mask.size();
7194 for (int i = 0; i < Size; ++i)
7195 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
7196 return true;
7197 return false;
7198 }
7200 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
7201 ///
7202 /// This checks a shuffle mask to see if it is performing the same
7203 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
7204 /// that it is also not lane-crossing. It may however involve a blend from the
7205 /// same lane of a second vector.
7206 ///
7207 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
7208 /// non-trivial to compute in the face of undef lanes. The representation is
7209 /// *not* suitable for use with existing 128-bit shuffles as it will contain
7210 /// entries from both V1 and V2 inputs to the wider mask.
7211 static bool
7212 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
7213 SmallVectorImpl<int> &RepeatedMask) {
7214 int LaneSize = 128 / VT.getScalarSizeInBits();
7215 RepeatedMask.resize(LaneSize, -1);
7216 int Size = Mask.size();
7217 for (int i = 0; i < Size; ++i) {
7218 if (Mask[i] < 0)
7219 continue;
7220 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
7221 // This entry crosses lanes, so there is no way to model this shuffle.
7222 return false;
7224 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
7225 if (RepeatedMask[i % LaneSize] == -1)
7226 // This is the first non-undef entry in this slot of a 128-bit lane.
7227 RepeatedMask[i % LaneSize] =
7228 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
7229 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
7230 // Found a mismatch with the repeated mask.
7231 return false;
7232 }
7233 return true;
7234 }
7236 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7237 // 2013 will allow us to use it as a non-type template parameter.
7238 namespace {
7240 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7241 ///
7242 /// See its documentation for details.
7243 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7244 if (Mask.size() != Args.size())
7245 return false;
7246 for (int i = 0, e = Mask.size(); i < e; ++i) {
7247 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7248 if (Mask[i] != -1 && Mask[i] != *Args[i])
7249 return false;
7250 }
7251 return true;
7252 }
7254 } // namespace
7256 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7257 /// arguments.
7258 ///
7259 /// This is a fast way to test a shuffle mask against a fixed pattern:
7260 ///
7261 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7262 ///
7263 /// It returns true if the mask is exactly as wide as the argument list, and
7264 /// each element of the mask is either -1 (signifying undef) or the value given
7265 /// in the argument.
7266 static const VariadicFunction1<
7267 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7269 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7270 ///
7271 /// This helper function produces an 8-bit shuffle immediate corresponding to
7272 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7273 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7274 /// example.
7275 ///
7276 /// NB: We rely heavily on "undef" masks preserving the input lane.
7277 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7278 SelectionDAG &DAG) {
7279 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7280 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7281 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7282 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7283 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7285 unsigned Imm = 0;
7286 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7287 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7288 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7289 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7290 return DAG.getConstant(Imm, MVT::i8);
7291 }
7293 /// \brief Try to emit a blend instruction for a shuffle.
7294 ///
7295 /// This doesn't do any checks for the availability of instructions for blending
7296 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7297 /// be matched in the backend with the type given. What it does check for is
7298 /// that the shuffle mask is in fact a blend.
7299 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7300 SDValue V2, ArrayRef<int> Mask,
7301 const X86Subtarget *Subtarget,
7302 SelectionDAG &DAG) {
7304 unsigned BlendMask = 0;
7305 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7306 if (Mask[i] >= Size) {
7307 if (Mask[i] != i + Size)
7308 return SDValue(); // Shuffled V2 input!
7309 BlendMask |= 1u << i;
7310 continue;
7311 }
7312 if (Mask[i] >= 0 && Mask[i] != i)
7313 return SDValue(); // Shuffled V1 input!
7314 }
7315 switch (VT.SimpleTy) {
7316 case MVT::v2f64:
7317 case MVT::v4f32:
7318 case MVT::v4f64:
7319 case MVT::v8f32:
7320 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7321 DAG.getConstant(BlendMask, MVT::i8));
7323 case MVT::v4i64:
7324 case MVT::v8i32:
7325 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7326 // FALLTHROUGH
7327 case MVT::v2i64:
7328 case MVT::v4i32:
7329 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7330 // that instruction.
7331 if (Subtarget->hasAVX2()) {
7332 // Scale the blend by the number of 32-bit dwords per element.
7333 int Scale = VT.getScalarSizeInBits() / 32;
7334 BlendMask = 0;
7335 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7336 if (Mask[i] >= Size)
7337 for (int j = 0; j < Scale; ++j)
7338 BlendMask |= 1u << (i * Scale + j);
7340 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7341 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
7342 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
7343 return DAG.getNode(ISD::BITCAST, DL, VT,
7344 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7345 DAG.getConstant(BlendMask, MVT::i8)));
7346 }
7347 // FALLTHROUGH
7348 case MVT::v8i16: {
7349 // For integer shuffles we need to expand the mask and cast the inputs to
7350 // v8i16s prior to blending.
7351 int Scale = 8 / VT.getVectorNumElements();
7352 BlendMask = 0;
7353 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7354 if (Mask[i] >= Size)
7355 for (int j = 0; j < Scale; ++j)
7356 BlendMask |= 1u << (i * Scale + j);
7358 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7359 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7360 return DAG.getNode(ISD::BITCAST, DL, VT,
7361 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7362 DAG.getConstant(BlendMask, MVT::i8)));
7363 }
7365 case MVT::v16i16: {
7366 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7367 SmallVector<int, 8> RepeatedMask;
7368 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7369 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7370 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7371 BlendMask = 0;
7372 for (int i = 0; i < 8; ++i)
7373 if (RepeatedMask[i] >= 16)
7374 BlendMask |= 1u << i;
7375 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7376 DAG.getConstant(BlendMask, MVT::i8));
7377 }
7378 }
7379 // FALLTHROUGH
7380 case MVT::v32i8: {
7381 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7382 // Scale the blend by the number of bytes per element.
7383 int Scale = VT.getScalarSizeInBits() / 8;
7384 assert(Mask.size() * Scale == 32 && "Not a 256-bit vector!");
7386 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7387 // mix of LLVM's code generator and the x86 backend. We tell the code
7388 // generator that boolean values in the elements of an x86 vector register
7389 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
7390 // mapping a select to operand #1, and 'false' mapping to operand #2. The
7391 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
7392 // of the element (the remaining are ignored) and 0 in that high bit would
7393 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7394 // the LLVM model for boolean values in vector elements gets the relevant
7395 // bit set, it is set backwards and over constrained relative to x86's
7396 // actual model.
7397 SDValue VSELECTMask[32];
7398 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7399 for (int j = 0; j < Scale; ++j)
7400 VSELECTMask[Scale * i + j] =
7401 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7402 : DAG.getConstant(Mask[i] < Size ? -1 : 0, MVT::i8);
7404 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1);
7405 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V2);
7406 return DAG.getNode(
7407 ISD::BITCAST, DL, VT,
7408 DAG.getNode(ISD::VSELECT, DL, MVT::v32i8,
7409 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, VSELECTMask),
7410 V1, V2));
7411 }
7413 default:
7414 llvm_unreachable("Not a supported integer vector type!");
7415 }
7416 }
7418 /// \brief Generic routine to lower a shuffle and blend as a decomposed set of
7419 /// unblended shuffles followed by an unshuffled blend.
7420 ///
7421 /// This matches the extremely common pattern for handling combined
7422 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7423 /// operations.
7424 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7425 SDValue V1,
7426 SDValue V2,
7427 ArrayRef<int> Mask,
7428 SelectionDAG &DAG) {
7429 // Shuffle the input elements into the desired positions in V1 and V2 and
7430 // blend them together.
7431 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7432 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7433 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7434 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7435 if (Mask[i] >= 0 && Mask[i] < Size) {
7436 V1Mask[i] = Mask[i];
7437 BlendMask[i] = i;
7438 } else if (Mask[i] >= Size) {
7439 V2Mask[i] = Mask[i] - Size;
7440 BlendMask[i] = i + Size;
7441 }
7443 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7444 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7445 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7446 }
7448 /// \brief Try to lower a vector shuffle as a byte rotation.
7449 ///
7450 /// We have a generic PALIGNR instruction in x86 that will do an arbitrary
7451 /// byte-rotation of a the concatentation of two vectors. This routine will
7452 /// try to generically lower a vector shuffle through such an instruction. It
7453 /// does not check for the availability of PALIGNR-based lowerings, only the
7454 /// applicability of this strategy to the given mask. This matches shuffle
7455 /// vectors that look like:
7456 ///
7457 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7458 ///
7459 /// Essentially it concatenates V1 and V2, shifts right by some number of
7460 /// elements, and takes the low elements as the result. Note that while this is
7461 /// specified as a *right shift* because x86 is little-endian, it is a *left
7462 /// rotate* of the vector lanes.
7463 ///
7464 /// Note that this only handles 128-bit vector widths currently.
7465 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7466 SDValue V2,
7467 ArrayRef<int> Mask,
7468 SelectionDAG &DAG) {
7469 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7471 // We need to detect various ways of spelling a rotation:
7472 // [11, 12, 13, 14, 15, 0, 1, 2]
7473 // [-1, 12, 13, 14, -1, -1, 1, -1]
7474 // [-1, -1, -1, -1, -1, -1, 1, 2]
7475 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7476 // [-1, 4, 5, 6, -1, -1, 9, -1]
7477 // [-1, 4, 5, 6, -1, -1, -1, -1]
7478 int Rotation = 0;
7479 SDValue Lo, Hi;
7480 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7481 if (Mask[i] == -1)
7482 continue;
7483 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7485 // Based on the mod-Size value of this mask element determine where
7486 // a rotated vector would have started.
7487 int StartIdx = i - (Mask[i] % Size);
7488 if (StartIdx == 0)
7489 // The identity rotation isn't interesting, stop.
7490 return SDValue();
7492 // If we found the tail of a vector the rotation must be the missing
7493 // front. If we found the head of a vector, it must be how much of the head.
7494 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7496 if (Rotation == 0)
7497 Rotation = CandidateRotation;
7498 else if (Rotation != CandidateRotation)
7499 // The rotations don't match, so we can't match this mask.
7500 return SDValue();
7502 // Compute which value this mask is pointing at.
7503 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7505 // Compute which of the two target values this index should be assigned to.
7506 // This reflects whether the high elements are remaining or the low elements
7507 // are remaining.
7508 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7510 // Either set up this value if we've not encountered it before, or check
7511 // that it remains consistent.
7512 if (!TargetV)
7513 TargetV = MaskV;
7514 else if (TargetV != MaskV)
7515 // This may be a rotation, but it pulls from the inputs in some
7516 // unsupported interleaving.
7517 return SDValue();
7518 }
7520 // Check that we successfully analyzed the mask, and normalize the results.
7521 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7522 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7523 if (!Lo)
7524 Lo = Hi;
7525 else if (!Hi)
7526 Hi = Lo;
7528 // Cast the inputs to v16i8 to match PALIGNR.
7529 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7530 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7532 assert(VT.getSizeInBits() == 128 &&
7533 "Rotate-based lowering only supports 128-bit lowering!");
7534 assert(Mask.size() <= 16 &&
7535 "Can shuffle at most 16 bytes in a 128-bit vector!");
7536 // The actual rotate instruction rotates bytes, so we need to scale the
7537 // rotation based on how many bytes are in the vector.
7538 int Scale = 16 / Mask.size();
7540 return DAG.getNode(ISD::BITCAST, DL, VT,
7541 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7542 DAG.getConstant(Rotation * Scale, MVT::i8)));
7543 }
7545 /// \brief Compute whether each element of a shuffle is zeroable.
7546 ///
7547 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7548 /// Either it is an undef element in the shuffle mask, the element of the input
7549 /// referenced is undef, or the element of the input referenced is known to be
7550 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7551 /// as many lanes with this technique as possible to simplify the remaining
7552 /// shuffle.
7553 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7554 SDValue V1, SDValue V2) {
7555 SmallBitVector Zeroable(Mask.size(), false);
7557 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7558 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7560 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7561 int M = Mask[i];
7562 // Handle the easy cases.
7563 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7564 Zeroable[i] = true;
7565 continue;
7566 }
7568 // If this is an index into a build_vector node, dig out the input value and
7569 // use it.
7570 SDValue V = M < Size ? V1 : V2;
7571 if (V.getOpcode() != ISD::BUILD_VECTOR)
7572 continue;
7574 SDValue Input = V.getOperand(M % Size);
7575 // The UNDEF opcode check really should be dead code here, but not quite
7576 // worth asserting on (it isn't invalid, just unexpected).
7577 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7578 Zeroable[i] = true;
7579 }
7581 return Zeroable;
7582 }
7584 /// \brief Lower a vector shuffle as a zero or any extension.
7585 ///
7586 /// Given a specific number of elements, element bit width, and extension
7587 /// stride, produce either a zero or any extension based on the available
7588 /// features of the subtarget.
7589 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7590 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7591 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7592 assert(Scale > 1 && "Need a scale to extend.");
7593 int EltBits = VT.getSizeInBits() / NumElements;
7594 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7595 "Only 8, 16, and 32 bit elements can be extended.");
7596 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7598 // Found a valid zext mask! Try various lowering strategies based on the
7599 // input type and available ISA extensions.
7600 if (Subtarget->hasSSE41()) {
7601 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7602 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7603 NumElements / Scale);
7604 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7605 return DAG.getNode(ISD::BITCAST, DL, VT,
7606 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7607 }
7609 // For any extends we can cheat for larger element sizes and use shuffle
7610 // instructions that can fold with a load and/or copy.
7611 if (AnyExt && EltBits == 32) {
7612 int PSHUFDMask[4] = {0, -1, 1, -1};
7613 return DAG.getNode(
7614 ISD::BITCAST, DL, VT,
7615 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7616 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7617 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7618 }
7619 if (AnyExt && EltBits == 16 && Scale > 2) {
7620 int PSHUFDMask[4] = {0, -1, 0, -1};
7621 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7622 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7623 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7624 int PSHUFHWMask[4] = {1, -1, -1, -1};
7625 return DAG.getNode(
7626 ISD::BITCAST, DL, VT,
7627 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7628 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7629 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7630 }
7632 // If this would require more than 2 unpack instructions to expand, use
7633 // pshufb when available. We can only use more than 2 unpack instructions
7634 // when zero extending i8 elements which also makes it easier to use pshufb.
7635 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7636 assert(NumElements == 16 && "Unexpected byte vector width!");
7637 SDValue PSHUFBMask[16];
7638 for (int i = 0; i < 16; ++i)
7639 PSHUFBMask[i] =
7640 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7641 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7642 return DAG.getNode(ISD::BITCAST, DL, VT,
7643 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7644 DAG.getNode(ISD::BUILD_VECTOR, DL,
7645 MVT::v16i8, PSHUFBMask)));
7646 }
7648 // Otherwise emit a sequence of unpacks.
7649 do {
7650 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7651 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7652 : getZeroVector(InputVT, Subtarget, DAG, DL);
7653 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7654 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7655 Scale /= 2;
7656 EltBits *= 2;
7657 NumElements /= 2;
7658 } while (Scale > 1);
7659 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7660 }
7662 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7663 ///
7664 /// This routine will try to do everything in its power to cleverly lower
7665 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7666 /// check for the profitability of this lowering, it tries to aggressively
7667 /// match this pattern. It will use all of the micro-architectural details it
7668 /// can to emit an efficient lowering. It handles both blends with all-zero
7669 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7670 /// masking out later).
7671 ///
7672 /// The reason we have dedicated lowering for zext-style shuffles is that they
7673 /// are both incredibly common and often quite performance sensitive.
7674 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7675 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7676 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7677 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7679 int Bits = VT.getSizeInBits();
7680 int NumElements = Mask.size();
7682 // Define a helper function to check a particular ext-scale and lower to it if
7683 // valid.
7684 auto Lower = [&](int Scale) -> SDValue {
7685 SDValue InputV;
7686 bool AnyExt = true;
7687 for (int i = 0; i < NumElements; ++i) {
7688 if (Mask[i] == -1)
7689 continue; // Valid anywhere but doesn't tell us anything.
7690 if (i % Scale != 0) {
7691 // Each of the extend elements needs to be zeroable.
7692 if (!Zeroable[i])
7693 return SDValue();
7695 // We no lorger are in the anyext case.
7696 AnyExt = false;
7697 continue;
7698 }
7700 // Each of the base elements needs to be consecutive indices into the
7701 // same input vector.
7702 SDValue V = Mask[i] < NumElements ? V1 : V2;
7703 if (!InputV)
7704 InputV = V;
7705 else if (InputV != V)
7706 return SDValue(); // Flip-flopping inputs.
7708 if (Mask[i] % NumElements != i / Scale)
7709 return SDValue(); // Non-consecutive strided elemenst.
7710 }
7712 // If we fail to find an input, we have a zero-shuffle which should always
7713 // have already been handled.
7714 // FIXME: Maybe handle this here in case during blending we end up with one?
7715 if (!InputV)
7716 return SDValue();
7718 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7719 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7720 };
7722 // The widest scale possible for extending is to a 64-bit integer.
7723 assert(Bits % 64 == 0 &&
7724 "The number of bits in a vector must be divisible by 64 on x86!");
7725 int NumExtElements = Bits / 64;
7727 // Each iteration, try extending the elements half as much, but into twice as
7728 // many elements.
7729 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7730 assert(NumElements % NumExtElements == 0 &&
7731 "The input vector size must be divisble by the extended size.");
7732 if (SDValue V = Lower(NumElements / NumExtElements))
7733 return V;
7734 }
7736 // No viable ext lowering found.
7737 return SDValue();
7738 }
7740 /// \brief Try to lower insertion of a single element into a zero vector.
7741 ///
7742 /// This is a common pattern that we have especially efficient patterns to lower
7743 /// across all subtarget feature sets.
7744 static SDValue lowerVectorShuffleAsElementInsertion(
7745 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7746 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7747 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7749 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7750 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7751 Mask.begin();
7752 if (Mask.size() == 2) {
7753 if (!Zeroable[V2Index ^ 1]) {
7754 // For 2-wide masks we may be able to just invert the inputs. We use an xor
7755 // with 2 to flip from {2,3} to {0,1} and vice versa.
7756 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
7757 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
7758 if (Zeroable[V2Index])
7759 return lowerVectorShuffleAsElementInsertion(VT, DL, V2, V1, InverseMask,
7760 Subtarget, DAG);
7761 else
7762 return SDValue();
7763 }
7764 } else {
7765 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7766 if (i != V2Index && !Zeroable[i])
7767 return SDValue(); // Not inserting into a zero vector.
7768 }
7770 // Step over any bitcasts on either input so we can scan the actual
7771 // BUILD_VECTOR nodes.
7772 while (V1.getOpcode() == ISD::BITCAST)
7773 V1 = V1.getOperand(0);
7774 while (V2.getOpcode() == ISD::BITCAST)
7775 V2 = V2.getOperand(0);
7777 // Check for a single input from a SCALAR_TO_VECTOR node.
7778 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7779 // all the smarts here sunk into that routine. However, the current
7780 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7781 // vector shuffle lowering is dead.
7782 if (!((V2.getOpcode() == ISD::SCALAR_TO_VECTOR &&
7783 Mask[V2Index] == (int)Mask.size()) ||
7784 V2.getOpcode() == ISD::BUILD_VECTOR))
7785 return SDValue();
7787 SDValue V2S = V2.getOperand(Mask[V2Index] - Mask.size());
7789 // First, we need to zext the scalar if it is smaller than an i32.
7790 MVT ExtVT = VT;
7791 MVT EltVT = VT.getVectorElementType();
7792 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
7793 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7794 // Zero-extend directly to i32.
7795 ExtVT = MVT::v4i32;
7796 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7797 }
7799 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT,
7800 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S));
7801 if (ExtVT != VT)
7802 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7804 if (V2Index != 0) {
7805 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7806 // the desired position. Otherwise it is more efficient to do a vector
7807 // shift left. We know that we can do a vector shift left because all
7808 // the inputs are zero.
7809 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7810 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7811 V2Shuffle[V2Index] = 0;
7812 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7813 } else {
7814 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
7815 V2 = DAG.getNode(
7816 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7817 DAG.getConstant(
7818 V2Index * EltVT.getSizeInBits(),
7819 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
7820 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7821 }
7822 }
7823 return V2;
7824 }
7826 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7827 ///
7828 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7829 /// support for floating point shuffles but not integer shuffles. These
7830 /// instructions will incur a domain crossing penalty on some chips though so
7831 /// it is better to avoid lowering through this for integer vectors where
7832 /// possible.
7833 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7834 const X86Subtarget *Subtarget,
7835 SelectionDAG &DAG) {
7836 SDLoc DL(Op);
7837 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7838 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7839 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7840 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7841 ArrayRef<int> Mask = SVOp->getMask();
7842 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7844 if (isSingleInputShuffleMask(Mask)) {
7845 // Straight shuffle of a single input vector. Simulate this by using the
7846 // single input as both of the "inputs" to this instruction..
7847 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7849 if (Subtarget->hasAVX()) {
7850 // If we have AVX, we can use VPERMILPS which will allow folding a load
7851 // into the shuffle.
7852 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
7853 DAG.getConstant(SHUFPDMask, MVT::i8));
7854 }
7856 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
7857 DAG.getConstant(SHUFPDMask, MVT::i8));
7858 }
7859 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7860 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7862 // Use dedicated unpack instructions for masks that match their pattern.
7863 if (isShuffleEquivalent(Mask, 0, 2))
7864 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
7865 if (isShuffleEquivalent(Mask, 1, 3))
7866 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
7868 // If we have a single input, insert that into V1 if we can do so cheaply.
7869 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1)
7870 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7871 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
7872 return Insertion;
7874 if (Subtarget->hasSSE41())
7875 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
7876 Subtarget, DAG))
7877 return Blend;
7879 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
7880 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
7881 DAG.getConstant(SHUFPDMask, MVT::i8));
7882 }
7884 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
7885 ///
7886 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
7887 /// the integer unit to minimize domain crossing penalties. However, for blends
7888 /// it falls back to the floating point shuffle operation with appropriate bit
7889 /// casting.
7890 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7891 const X86Subtarget *Subtarget,
7892 SelectionDAG &DAG) {
7893 SDLoc DL(Op);
7894 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
7895 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7896 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7897 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7898 ArrayRef<int> Mask = SVOp->getMask();
7899 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7901 if (isSingleInputShuffleMask(Mask)) {
7902 // Straight shuffle of a single input vector. For everything from SSE2
7903 // onward this has a single fast instruction with no scary immediates.
7904 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7905 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
7906 int WidenedMask[4] = {
7907 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7908 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7909 return DAG.getNode(
7910 ISD::BITCAST, DL, MVT::v2i64,
7911 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
7912 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
7913 }
7915 // Use dedicated unpack instructions for masks that match their pattern.
7916 if (isShuffleEquivalent(Mask, 0, 2))
7917 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
7918 if (isShuffleEquivalent(Mask, 1, 3))
7919 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
7921 // If we have a single input from V2 insert that into V1 if we can do so
7922 // cheaply.
7923 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1)
7924 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7925 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
7926 return Insertion;
7928 if (Subtarget->hasSSE41())
7929 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
7930 Subtarget, DAG))
7931 return Blend;
7933 // Try to use rotation instructions if available.
7934 if (Subtarget->hasSSSE3())
7935 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7936 DL, MVT::v2i64, V1, V2, Mask, DAG))
7937 return Rotate;
7939 // We implement this with SHUFPD which is pretty lame because it will likely
7940 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7941 // However, all the alternatives are still more cycles and newer chips don't
7942 // have this problem. It would be really nice if x86 had better shuffles here.
7943 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
7944 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
7945 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7946 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7947 }
7949 /// \brief Lower a vector shuffle using the SHUFPS instruction.
7950 ///
7951 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
7952 /// It makes no assumptions about whether this is the *best* lowering, it simply
7953 /// uses it.
7954 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
7955 ArrayRef<int> Mask, SDValue V1,
7956 SDValue V2, SelectionDAG &DAG) {
7957 SDValue LowV = V1, HighV = V2;
7958 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
7960 int NumV2Elements =
7961 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7963 if (NumV2Elements == 1) {
7964 int V2Index =
7965 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7966 Mask.begin();
7968 // Compute the index adjacent to V2Index and in the same half by toggling
7969 // the low bit.
7970 int V2AdjIndex = V2Index ^ 1;
7972 if (Mask[V2AdjIndex] == -1) {
7973 // Handles all the cases where we have a single V2 element and an undef.
7974 // This will only ever happen in the high lanes because we commute the
7975 // vector otherwise.
7976 if (V2Index < 2)
7977 std::swap(LowV, HighV);
7978 NewMask[V2Index] -= 4;
7979 } else {
7980 // Handle the case where the V2 element ends up adjacent to a V1 element.
7981 // To make this work, blend them together as the first step.
7982 int V1Index = V2AdjIndex;
7983 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
7984 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
7985 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7987 // Now proceed to reconstruct the final blend as we have the necessary
7988 // high or low half formed.
7989 if (V2Index < 2) {
7990 LowV = V2;
7991 HighV = V1;
7992 } else {
7993 HighV = V2;
7994 }
7995 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
7996 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
7997 }
7998 } else if (NumV2Elements == 2) {
7999 if (Mask[0] < 4 && Mask[1] < 4) {
8000 // Handle the easy case where we have V1 in the low lanes and V2 in the
8001 // high lanes.
8002 NewMask[2] -= 4;
8003 NewMask[3] -= 4;
8004 } else if (Mask[2] < 4 && Mask[3] < 4) {
8005 // We also handle the reversed case because this utility may get called
8006 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8007 // arrange things in the right direction.
8008 NewMask[0] -= 4;
8009 NewMask[1] -= 4;
8010 HighV = V1;
8011 LowV = V2;
8012 } else {
8013 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8014 // trying to place elements directly, just blend them and set up the final
8015 // shuffle to place them.
8017 // The first two blend mask elements are for V1, the second two are for
8018 // V2.
8019 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8020 Mask[2] < 4 ? Mask[2] : Mask[3],
8021 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8022 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8023 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8024 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8026 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8027 // a blend.
8028 LowV = HighV = V1;
8029 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8030 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8031 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8032 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8033 }
8034 }
8035 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8036 getV4X86ShuffleImm8ForMask(NewMask, DAG));
8037 }
8039 /// \brief Lower 4-lane 32-bit floating point shuffles.
8040 ///
8041 /// Uses instructions exclusively from the floating point unit to minimize
8042 /// domain crossing penalties, as these are sufficient to implement all v4f32
8043 /// shuffles.
8044 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8045 const X86Subtarget *Subtarget,
8046 SelectionDAG &DAG) {
8047 SDLoc DL(Op);
8048 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8049 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8050 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8051 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8052 ArrayRef<int> Mask = SVOp->getMask();
8053 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8055 int NumV2Elements =
8056 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8058 if (NumV2Elements == 0) {
8059 if (Subtarget->hasAVX()) {
8060 // If we have AVX, we can use VPERMILPS which will allow folding a load
8061 // into the shuffle.
8062 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8063 getV4X86ShuffleImm8ForMask(Mask, DAG));
8064 }
8066 // Otherwise, use a straight shuffle of a single input vector. We pass the
8067 // input vector to both operands to simulate this with a SHUFPS.
8068 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8069 getV4X86ShuffleImm8ForMask(Mask, DAG));
8070 }
8072 // Use dedicated unpack instructions for masks that match their pattern.
8073 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8074 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8075 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8076 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8078 // There are special ways we can lower some single-element blends. However, we
8079 // have custom ways we can lower more complex single-element blends below that
8080 // we defer to if both this and BLENDPS fail to match, so restrict this to
8081 // when the V2 input is targeting element 0 of the mask -- that is the fast
8082 // case here.
8083 if (NumV2Elements == 1 && Mask[0] >= 4)
8084 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
8085 Mask, Subtarget, DAG))
8086 return V;
8088 if (Subtarget->hasSSE41())
8089 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8090 Subtarget, DAG))
8091 return Blend;
8093 // Check for whether we can use INSERTPS to perform the blend. We only use
8094 // INSERTPS when the V1 elements are already in the correct locations
8095 // because otherwise we can just always use two SHUFPS instructions which
8096 // are much smaller to encode than a SHUFPS and an INSERTPS.
8097 if (NumV2Elements == 1 && Subtarget->hasSSE41()) {
8098 int V2Index =
8099 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8100 Mask.begin();
8102 // When using INSERTPS we can zero any lane of the destination. Collect
8103 // the zero inputs into a mask and drop them from the lanes of V1 which
8104 // actually need to be present as inputs to the INSERTPS.
8105 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8107 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
8108 bool InsertNeedsShuffle = false;
8109 unsigned ZMask = 0;
8110 for (int i = 0; i < 4; ++i)
8111 if (i != V2Index) {
8112 if (Zeroable[i]) {
8113 ZMask |= 1 << i;
8114 } else if (Mask[i] != i) {
8115 InsertNeedsShuffle = true;
8116 break;
8117 }
8118 }
8120 // We don't want to use INSERTPS or other insertion techniques if it will
8121 // require shuffling anyways.
8122 if (!InsertNeedsShuffle) {
8123 // If all of V1 is zeroable, replace it with undef.
8124 if ((ZMask | 1 << V2Index) == 0xF)
8125 V1 = DAG.getUNDEF(MVT::v4f32);
8127 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
8128 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8130 // Insert the V2 element into the desired position.
8131 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8132 DAG.getConstant(InsertPSMask, MVT::i8));
8133 }
8134 }
8136 // Otherwise fall back to a SHUFPS lowering strategy.
8137 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8138 }
8140 /// \brief Lower 4-lane i32 vector shuffles.
8141 ///
8142 /// We try to handle these with integer-domain shuffles where we can, but for
8143 /// blends we use the floating point domain blend instructions.
8144 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8145 const X86Subtarget *Subtarget,
8146 SelectionDAG &DAG) {
8147 SDLoc DL(Op);
8148 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8149 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8150 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8151 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8152 ArrayRef<int> Mask = SVOp->getMask();
8153 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8155 int NumV2Elements =
8156 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8158 if (NumV2Elements == 0) {
8159 // Straight shuffle of a single input vector. For everything from SSE2
8160 // onward this has a single fast instruction with no scary immediates.
8161 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8162 // but we aren't actually going to use the UNPCK instruction because doing
8163 // so prevents folding a load into this instruction or making a copy.
8164 const int UnpackLoMask[] = {0, 0, 1, 1};
8165 const int UnpackHiMask[] = {2, 2, 3, 3};
8166 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
8167 Mask = UnpackLoMask;
8168 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
8169 Mask = UnpackHiMask;
8171 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8172 getV4X86ShuffleImm8ForMask(Mask, DAG));
8173 }
8175 // Whenever we can lower this as a zext, that instruction is strictly faster
8176 // than any alternative.
8177 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8178 Mask, Subtarget, DAG))
8179 return ZExt;
8181 // Use dedicated unpack instructions for masks that match their pattern.
8182 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8183 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8184 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8185 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8187 // There are special ways we can lower some single-element blends.
8188 if (NumV2Elements == 1)
8189 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
8190 Mask, Subtarget, DAG))
8191 return V;
8193 if (Subtarget->hasSSE41())
8194 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8195 Subtarget, DAG))
8196 return Blend;
8198 // Try to use rotation instructions if available.
8199 if (Subtarget->hasSSSE3())
8200 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8201 DL, MVT::v4i32, V1, V2, Mask, DAG))
8202 return Rotate;
8204 // We implement this with SHUFPS because it can blend from two vectors.
8205 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8206 // up the inputs, bypassing domain shift penalties that we would encur if we
8207 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8208 // relevant.
8209 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8210 DAG.getVectorShuffle(
8211 MVT::v4f32, DL,
8212 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
8213 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8214 }
8216 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8217 /// shuffle lowering, and the most complex part.
8218 ///
8219 /// The lowering strategy is to try to form pairs of input lanes which are
8220 /// targeted at the same half of the final vector, and then use a dword shuffle
8221 /// to place them onto the right half, and finally unpack the paired lanes into
8222 /// their final position.
8223 ///
8224 /// The exact breakdown of how to form these dword pairs and align them on the
8225 /// correct sides is really tricky. See the comments within the function for
8226 /// more of the details.
8227 static SDValue lowerV8I16SingleInputVectorShuffle(
8228 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8229 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8230 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8231 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8232 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8234 SmallVector<int, 4> LoInputs;
8235 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8236 [](int M) { return M >= 0; });
8237 std::sort(LoInputs.begin(), LoInputs.end());
8238 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8239 SmallVector<int, 4> HiInputs;
8240 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8241 [](int M) { return M >= 0; });
8242 std::sort(HiInputs.begin(), HiInputs.end());
8243 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8244 int NumLToL =
8245 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8246 int NumHToL = LoInputs.size() - NumLToL;
8247 int NumLToH =
8248 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8249 int NumHToH = HiInputs.size() - NumLToH;
8250 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8251 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8252 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8253 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8255 // Use dedicated unpack instructions for masks that match their pattern.
8256 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8257 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8258 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8259 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8261 // Try to use rotation instructions if available.
8262 if (Subtarget->hasSSSE3())
8263 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8264 DL, MVT::v8i16, V, V, Mask, DAG))
8265 return Rotate;
8267 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8268 // such inputs we can swap two of the dwords across the half mark and end up
8269 // with <=2 inputs to each half in each half. Once there, we can fall through
8270 // to the generic code below. For example:
8271 //
8272 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8273 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8274 //
8275 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8276 // and an existing 2-into-2 on the other half. In this case we may have to
8277 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8278 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8279 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8280 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8281 // half than the one we target for fixing) will be fixed when we re-enter this
8282 // path. We will also combine away any sequence of PSHUFD instructions that
8283 // result into a single instruction. Here is an example of the tricky case:
8284 //
8285 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8286 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8287 //
8288 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8289 //
8290 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8291 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8292 //
8293 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8294 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8295 //
8296 // The result is fine to be handled by the generic logic.
8297 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8298 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8299 int AOffset, int BOffset) {
8300 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8301 "Must call this with A having 3 or 1 inputs from the A half.");
8302 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8303 "Must call this with B having 1 or 3 inputs from the B half.");
8304 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8305 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8307 // Compute the index of dword with only one word among the three inputs in
8308 // a half by taking the sum of the half with three inputs and subtracting
8309 // the sum of the actual three inputs. The difference is the remaining
8310 // slot.
8311 int ADWord, BDWord;
8312 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8313 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8314 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8315 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8316 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8317 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8318 int TripleNonInputIdx =
8319 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8320 TripleDWord = TripleNonInputIdx / 2;
8322 // We use xor with one to compute the adjacent DWord to whichever one the
8323 // OneInput is in.
8324 OneInputDWord = (OneInput / 2) ^ 1;
8326 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8327 // and BToA inputs. If there is also such a problem with the BToB and AToB
8328 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8329 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8330 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8331 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8332 // Compute how many inputs will be flipped by swapping these DWords. We
8333 // need
8334 // to balance this to ensure we don't form a 3-1 shuffle in the other
8335 // half.
8336 int NumFlippedAToBInputs =
8337 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8338 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8339 int NumFlippedBToBInputs =
8340 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8341 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8342 if ((NumFlippedAToBInputs == 1 &&
8343 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8344 (NumFlippedBToBInputs == 1 &&
8345 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8346 // We choose whether to fix the A half or B half based on whether that
8347 // half has zero flipped inputs. At zero, we may not be able to fix it
8348 // with that half. We also bias towards fixing the B half because that
8349 // will more commonly be the high half, and we have to bias one way.
8350 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8351 ArrayRef<int> Inputs) {
8352 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8353 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8354 PinnedIdx ^ 1) != Inputs.end();
8355 // Determine whether the free index is in the flipped dword or the
8356 // unflipped dword based on where the pinned index is. We use this bit
8357 // in an xor to conditionally select the adjacent dword.
8358 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8359 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8360 FixFreeIdx) != Inputs.end();
8361 if (IsFixIdxInput == IsFixFreeIdxInput)
8362 FixFreeIdx += 1;
8363 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8364 FixFreeIdx) != Inputs.end();
8365 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8366 "We need to be changing the number of flipped inputs!");
8367 int PSHUFHalfMask[] = {0, 1, 2, 3};
8368 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8369 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8370 MVT::v8i16, V,
8371 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8373 for (int &M : Mask)
8374 if (M != -1 && M == FixIdx)
8375 M = FixFreeIdx;
8376 else if (M != -1 && M == FixFreeIdx)
8377 M = FixIdx;
8378 };
8379 if (NumFlippedBToBInputs != 0) {
8380 int BPinnedIdx =
8381 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8382 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8383 } else {
8384 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8385 int APinnedIdx =
8386 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8387 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8388 }
8389 }
8390 }
8392 int PSHUFDMask[] = {0, 1, 2, 3};
8393 PSHUFDMask[ADWord] = BDWord;
8394 PSHUFDMask[BDWord] = ADWord;
8395 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8396 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8397 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8398 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8400 // Adjust the mask to match the new locations of A and B.
8401 for (int &M : Mask)
8402 if (M != -1 && M/2 == ADWord)
8403 M = 2 * BDWord + M % 2;
8404 else if (M != -1 && M/2 == BDWord)
8405 M = 2 * ADWord + M % 2;
8407 // Recurse back into this routine to re-compute state now that this isn't
8408 // a 3 and 1 problem.
8409 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8410 Mask);
8411 };
8412 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8413 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8414 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8415 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8417 // At this point there are at most two inputs to the low and high halves from
8418 // each half. That means the inputs can always be grouped into dwords and
8419 // those dwords can then be moved to the correct half with a dword shuffle.
8420 // We use at most one low and one high word shuffle to collect these paired
8421 // inputs into dwords, and finally a dword shuffle to place them.
8422 int PSHUFLMask[4] = {-1, -1, -1, -1};
8423 int PSHUFHMask[4] = {-1, -1, -1, -1};
8424 int PSHUFDMask[4] = {-1, -1, -1, -1};
8426 // First fix the masks for all the inputs that are staying in their
8427 // original halves. This will then dictate the targets of the cross-half
8428 // shuffles.
8429 auto fixInPlaceInputs =
8430 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8431 MutableArrayRef<int> SourceHalfMask,
8432 MutableArrayRef<int> HalfMask, int HalfOffset) {
8433 if (InPlaceInputs.empty())
8434 return;
8435 if (InPlaceInputs.size() == 1) {
8436 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8437 InPlaceInputs[0] - HalfOffset;
8438 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8439 return;
8440 }
8441 if (IncomingInputs.empty()) {
8442 // Just fix all of the in place inputs.
8443 for (int Input : InPlaceInputs) {
8444 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8445 PSHUFDMask[Input / 2] = Input / 2;
8446 }
8447 return;
8448 }
8450 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8451 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8452 InPlaceInputs[0] - HalfOffset;
8453 // Put the second input next to the first so that they are packed into
8454 // a dword. We find the adjacent index by toggling the low bit.
8455 int AdjIndex = InPlaceInputs[0] ^ 1;
8456 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8457 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8458 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8459 };
8460 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8461 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8463 // Now gather the cross-half inputs and place them into a free dword of
8464 // their target half.
8465 // FIXME: This operation could almost certainly be simplified dramatically to
8466 // look more like the 3-1 fixing operation.
8467 auto moveInputsToRightHalf = [&PSHUFDMask](
8468 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8469 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8470 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8471 int DestOffset) {
8472 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8473 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8474 };
8475 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8476 int Word) {
8477 int LowWord = Word & ~1;
8478 int HighWord = Word | 1;
8479 return isWordClobbered(SourceHalfMask, LowWord) ||
8480 isWordClobbered(SourceHalfMask, HighWord);
8481 };
8483 if (IncomingInputs.empty())
8484 return;
8486 if (ExistingInputs.empty()) {
8487 // Map any dwords with inputs from them into the right half.
8488 for (int Input : IncomingInputs) {
8489 // If the source half mask maps over the inputs, turn those into
8490 // swaps and use the swapped lane.
8491 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8492 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8493 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8494 Input - SourceOffset;
8495 // We have to swap the uses in our half mask in one sweep.
8496 for (int &M : HalfMask)
8497 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8498 M = Input;
8499 else if (M == Input)
8500 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8501 } else {
8502 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8503 Input - SourceOffset &&
8504 "Previous placement doesn't match!");
8505 }
8506 // Note that this correctly re-maps both when we do a swap and when
8507 // we observe the other side of the swap above. We rely on that to
8508 // avoid swapping the members of the input list directly.
8509 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8510 }
8512 // Map the input's dword into the correct half.
8513 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8514 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8515 else
8516 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8517 Input / 2 &&
8518 "Previous placement doesn't match!");
8519 }
8521 // And just directly shift any other-half mask elements to be same-half
8522 // as we will have mirrored the dword containing the element into the
8523 // same position within that half.
8524 for (int &M : HalfMask)
8525 if (M >= SourceOffset && M < SourceOffset + 4) {
8526 M = M - SourceOffset + DestOffset;
8527 assert(M >= 0 && "This should never wrap below zero!");
8528 }
8529 return;
8530 }
8532 // Ensure we have the input in a viable dword of its current half. This
8533 // is particularly tricky because the original position may be clobbered
8534 // by inputs being moved and *staying* in that half.
8535 if (IncomingInputs.size() == 1) {
8536 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8537 int InputFixed = std::find(std::begin(SourceHalfMask),
8538 std::end(SourceHalfMask), -1) -
8539 std::begin(SourceHalfMask) + SourceOffset;
8540 SourceHalfMask[InputFixed - SourceOffset] =
8541 IncomingInputs[0] - SourceOffset;
8542 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8543 InputFixed);
8544 IncomingInputs[0] = InputFixed;
8545 }
8546 } else if (IncomingInputs.size() == 2) {
8547 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8548 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8549 // We have two non-adjacent or clobbered inputs we need to extract from
8550 // the source half. To do this, we need to map them into some adjacent
8551 // dword slot in the source mask.
8552 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8553 IncomingInputs[1] - SourceOffset};
8555 // If there is a free slot in the source half mask adjacent to one of
8556 // the inputs, place the other input in it. We use (Index XOR 1) to
8557 // compute an adjacent index.
8558 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8559 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8560 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8561 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8562 InputsFixed[1] = InputsFixed[0] ^ 1;
8563 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8564 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8565 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8566 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8567 InputsFixed[0] = InputsFixed[1] ^ 1;
8568 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8569 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8570 // The two inputs are in the same DWord but it is clobbered and the
8571 // adjacent DWord isn't used at all. Move both inputs to the free
8572 // slot.
8573 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8574 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8575 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8576 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8577 } else {
8578 // The only way we hit this point is if there is no clobbering
8579 // (because there are no off-half inputs to this half) and there is no
8580 // free slot adjacent to one of the inputs. In this case, we have to
8581 // swap an input with a non-input.
8582 for (int i = 0; i < 4; ++i)
8583 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8584 "We can't handle any clobbers here!");
8585 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8586 "Cannot have adjacent inputs here!");
8588 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8589 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8591 // We also have to update the final source mask in this case because
8592 // it may need to undo the above swap.
8593 for (int &M : FinalSourceHalfMask)
8594 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8595 M = InputsFixed[1] + SourceOffset;
8596 else if (M == InputsFixed[1] + SourceOffset)
8597 M = (InputsFixed[0] ^ 1) + SourceOffset;
8599 InputsFixed[1] = InputsFixed[0] ^ 1;
8600 }
8602 // Point everything at the fixed inputs.
8603 for (int &M : HalfMask)
8604 if (M == IncomingInputs[0])
8605 M = InputsFixed[0] + SourceOffset;
8606 else if (M == IncomingInputs[1])
8607 M = InputsFixed[1] + SourceOffset;
8609 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8610 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8611 }
8612 } else {
8613 llvm_unreachable("Unhandled input size!");
8614 }
8616 // Now hoist the DWord down to the right half.
8617 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8618 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8619 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8620 for (int &M : HalfMask)
8621 for (int Input : IncomingInputs)
8622 if (M == Input)
8623 M = FreeDWord * 2 + Input % 2;
8624 };
8625 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8626 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8627 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8628 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8630 // Now enact all the shuffles we've computed to move the inputs into their
8631 // target half.
8632 if (!isNoopShuffleMask(PSHUFLMask))
8633 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8634 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
8635 if (!isNoopShuffleMask(PSHUFHMask))
8636 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8637 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
8638 if (!isNoopShuffleMask(PSHUFDMask))
8639 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8640 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8641 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8642 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8644 // At this point, each half should contain all its inputs, and we can then
8645 // just shuffle them into their final position.
8646 assert(std::count_if(LoMask.begin(), LoMask.end(),
8647 [](int M) { return M >= 4; }) == 0 &&
8648 "Failed to lift all the high half inputs to the low mask!");
8649 assert(std::count_if(HiMask.begin(), HiMask.end(),
8650 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8651 "Failed to lift all the low half inputs to the high mask!");
8653 // Do a half shuffle for the low mask.
8654 if (!isNoopShuffleMask(LoMask))
8655 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8656 getV4X86ShuffleImm8ForMask(LoMask, DAG));
8658 // Do a half shuffle with the high mask after shifting its values down.
8659 for (int &M : HiMask)
8660 if (M >= 0)
8661 M -= 4;
8662 if (!isNoopShuffleMask(HiMask))
8663 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8664 getV4X86ShuffleImm8ForMask(HiMask, DAG));
8666 return V;
8667 }
8669 /// \brief Detect whether the mask pattern should be lowered through
8670 /// interleaving.
8671 ///
8672 /// This essentially tests whether viewing the mask as an interleaving of two
8673 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
8674 /// lowering it through interleaving is a significantly better strategy.
8675 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
8676 int NumEvenInputs[2] = {0, 0};
8677 int NumOddInputs[2] = {0, 0};
8678 int NumLoInputs[2] = {0, 0};
8679 int NumHiInputs[2] = {0, 0};
8680 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
8681 if (Mask[i] < 0)
8682 continue;
8684 int InputIdx = Mask[i] >= Size;
8686 if (i < Size / 2)
8687 ++NumLoInputs[InputIdx];
8688 else
8689 ++NumHiInputs[InputIdx];
8691 if ((i % 2) == 0)
8692 ++NumEvenInputs[InputIdx];
8693 else
8694 ++NumOddInputs[InputIdx];
8695 }
8697 // The minimum number of cross-input results for both the interleaved and
8698 // split cases. If interleaving results in fewer cross-input results, return
8699 // true.
8700 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
8701 NumEvenInputs[0] + NumOddInputs[1]);
8702 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
8703 NumLoInputs[0] + NumHiInputs[1]);
8704 return InterleavedCrosses < SplitCrosses;
8705 }
8707 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
8708 ///
8709 /// This strategy only works when the inputs from each vector fit into a single
8710 /// half of that vector, and generally there are not so many inputs as to leave
8711 /// the in-place shuffles required highly constrained (and thus expensive). It
8712 /// shifts all the inputs into a single side of both input vectors and then
8713 /// uses an unpack to interleave these inputs in a single vector. At that
8714 /// point, we will fall back on the generic single input shuffle lowering.
8715 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
8716 SDValue V2,
8717 MutableArrayRef<int> Mask,
8718 const X86Subtarget *Subtarget,
8719 SelectionDAG &DAG) {
8720 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8721 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8722 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
8723 for (int i = 0; i < 8; ++i)
8724 if (Mask[i] >= 0 && Mask[i] < 4)
8725 LoV1Inputs.push_back(i);
8726 else if (Mask[i] >= 4 && Mask[i] < 8)
8727 HiV1Inputs.push_back(i);
8728 else if (Mask[i] >= 8 && Mask[i] < 12)
8729 LoV2Inputs.push_back(i);
8730 else if (Mask[i] >= 12)
8731 HiV2Inputs.push_back(i);
8733 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
8734 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
8735 (void)NumV1Inputs;
8736 (void)NumV2Inputs;
8737 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
8738 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
8739 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
8741 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
8742 HiV1Inputs.size() + HiV2Inputs.size();
8744 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
8745 ArrayRef<int> HiInputs, bool MoveToLo,
8746 int MaskOffset) {
8747 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
8748 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
8749 if (BadInputs.empty())
8750 return V;
8752 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8753 int MoveOffset = MoveToLo ? 0 : 4;
8755 if (GoodInputs.empty()) {
8756 for (int BadInput : BadInputs) {
8757 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
8758 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
8759 }
8760 } else {
8761 if (GoodInputs.size() == 2) {
8762 // If the low inputs are spread across two dwords, pack them into
8763 // a single dword.
8764 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
8765 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
8766 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
8767 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
8768 } else {
8769 // Otherwise pin the good inputs.
8770 for (int GoodInput : GoodInputs)
8771 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
8772 }
8774 if (BadInputs.size() == 2) {
8775 // If we have two bad inputs then there may be either one or two good
8776 // inputs fixed in place. Find a fixed input, and then find the *other*
8777 // two adjacent indices by using modular arithmetic.
8778 int GoodMaskIdx =
8779 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
8780 [](int M) { return M >= 0; }) -
8781 std::begin(MoveMask);
8782 int MoveMaskIdx =
8783 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
8784 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
8785 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
8786 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8787 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
8788 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8789 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
8790 } else {
8791 assert(BadInputs.size() == 1 && "All sizes handled");
8792 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
8793 std::end(MoveMask), -1) -
8794 std::begin(MoveMask);
8795 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8796 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8797 }
8798 }
8800 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8801 MoveMask);
8802 };
8803 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
8804 /*MaskOffset*/ 0);
8805 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
8806 /*MaskOffset*/ 8);
8808 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
8809 // cross-half traffic in the final shuffle.
8811 // Munge the mask to be a single-input mask after the unpack merges the
8812 // results.
8813 for (int &M : Mask)
8814 if (M != -1)
8815 M = 2 * (M % 4) + (M / 8);
8817 return DAG.getVectorShuffle(
8818 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
8819 DL, MVT::v8i16, V1, V2),
8820 DAG.getUNDEF(MVT::v8i16), Mask);
8821 }
8823 /// \brief Generic lowering of 8-lane i16 shuffles.
8824 ///
8825 /// This handles both single-input shuffles and combined shuffle/blends with
8826 /// two inputs. The single input shuffles are immediately delegated to
8827 /// a dedicated lowering routine.
8828 ///
8829 /// The blends are lowered in one of three fundamental ways. If there are few
8830 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
8831 /// of the input is significantly cheaper when lowered as an interleaving of
8832 /// the two inputs, try to interleave them. Otherwise, blend the low and high
8833 /// halves of the inputs separately (making them have relatively few inputs)
8834 /// and then concatenate them.
8835 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8836 const X86Subtarget *Subtarget,
8837 SelectionDAG &DAG) {
8838 SDLoc DL(Op);
8839 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
8840 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8841 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8842 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8843 ArrayRef<int> OrigMask = SVOp->getMask();
8844 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8845 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
8846 MutableArrayRef<int> Mask(MaskStorage);
8848 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
8850 // Whenever we can lower this as a zext, that instruction is strictly faster
8851 // than any alternative.
8852 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8853 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
8854 return ZExt;
8856 auto isV1 = [](int M) { return M >= 0 && M < 8; };
8857 auto isV2 = [](int M) { return M >= 8; };
8859 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
8860 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
8862 if (NumV2Inputs == 0)
8863 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
8865 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
8866 "to be V1-input shuffles.");
8868 // There are special ways we can lower some single-element blends.
8869 if (NumV2Inputs == 1)
8870 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
8871 Mask, Subtarget, DAG))
8872 return V;
8874 if (Subtarget->hasSSE41())
8875 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
8876 Subtarget, DAG))
8877 return Blend;
8879 // Try to use rotation instructions if available.
8880 if (Subtarget->hasSSSE3())
8881 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V2, Mask, DAG))
8882 return Rotate;
8884 if (NumV1Inputs + NumV2Inputs <= 4)
8885 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
8887 // Check whether an interleaving lowering is likely to be more efficient.
8888 // This isn't perfect but it is a strong heuristic that tends to work well on
8889 // the kinds of shuffles that show up in practice.
8890 //
8891 // FIXME: Handle 1x, 2x, and 4x interleaving.
8892 if (shouldLowerAsInterleaving(Mask)) {
8893 // FIXME: Figure out whether we should pack these into the low or high
8894 // halves.
8896 int EMask[8], OMask[8];
8897 for (int i = 0; i < 4; ++i) {
8898 EMask[i] = Mask[2*i];
8899 OMask[i] = Mask[2*i + 1];
8900 EMask[i + 4] = -1;
8901 OMask[i + 4] = -1;
8902 }
8904 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
8905 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
8907 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
8908 }
8910 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8911 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8913 for (int i = 0; i < 4; ++i) {
8914 LoBlendMask[i] = Mask[i];
8915 HiBlendMask[i] = Mask[i + 4];
8916 }
8918 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
8919 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
8920 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
8921 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
8923 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8924 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
8925 }
8927 /// \brief Check whether a compaction lowering can be done by dropping even
8928 /// elements and compute how many times even elements must be dropped.
8929 ///
8930 /// This handles shuffles which take every Nth element where N is a power of
8931 /// two. Example shuffle masks:
8932 ///
8933 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
8934 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
8935 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
8936 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
8937 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
8938 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
8939 ///
8940 /// Any of these lanes can of course be undef.
8941 ///
8942 /// This routine only supports N <= 3.
8943 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
8944 /// for larger N.
8945 ///
8946 /// \returns N above, or the number of times even elements must be dropped if
8947 /// there is such a number. Otherwise returns zero.
8948 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
8949 // Figure out whether we're looping over two inputs or just one.
8950 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8952 // The modulus for the shuffle vector entries is based on whether this is
8953 // a single input or not.
8954 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
8955 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
8956 "We should only be called with masks with a power-of-2 size!");
8958 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
8960 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
8961 // and 2^3 simultaneously. This is because we may have ambiguity with
8962 // partially undef inputs.
8963 bool ViableForN[3] = {true, true, true};
8965 for (int i = 0, e = Mask.size(); i < e; ++i) {
8966 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
8967 // want.
8968 if (Mask[i] == -1)
8969 continue;
8971 bool IsAnyViable = false;
8972 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8973 if (ViableForN[j]) {
8974 uint64_t N = j + 1;
8976 // The shuffle mask must be equal to (i * 2^N) % M.
8977 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
8978 IsAnyViable = true;
8979 else
8980 ViableForN[j] = false;
8981 }
8982 // Early exit if we exhaust the possible powers of two.
8983 if (!IsAnyViable)
8984 break;
8985 }
8987 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8988 if (ViableForN[j])
8989 return j + 1;
8991 // Return 0 as there is no viable power of two.
8992 return 0;
8993 }
8995 /// \brief Generic lowering of v16i8 shuffles.
8996 ///
8997 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
8998 /// detect any complexity reducing interleaving. If that doesn't help, it uses
8999 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9000 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9001 /// back together.
9002 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9003 const X86Subtarget *Subtarget,
9004 SelectionDAG &DAG) {
9005 SDLoc DL(Op);
9006 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9007 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9008 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9009 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9010 ArrayRef<int> OrigMask = SVOp->getMask();
9011 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9013 // Try to use rotation instructions if available.
9014 if (Subtarget->hasSSSE3())
9015 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v16i8, V1, V2,
9016 OrigMask, DAG))
9017 return Rotate;
9019 // Try to use a zext lowering.
9020 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9021 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9022 return ZExt;
9024 int MaskStorage[16] = {
9025 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9026 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
9027 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
9028 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
9029 MutableArrayRef<int> Mask(MaskStorage);
9030 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
9031 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
9033 int NumV2Elements =
9034 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9036 // For single-input shuffles, there are some nicer lowering tricks we can use.
9037 if (NumV2Elements == 0) {
9038 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9039 // Notably, this handles splat and partial-splat shuffles more efficiently.
9040 // However, it only makes sense if the pre-duplication shuffle simplifies
9041 // things significantly. Currently, this means we need to be able to
9042 // express the pre-duplication shuffle as an i16 shuffle.
9043 //
9044 // FIXME: We should check for other patterns which can be widened into an
9045 // i16 shuffle as well.
9046 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9047 for (int i = 0; i < 16; i += 2)
9048 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9049 return false;
9051 return true;
9052 };
9053 auto tryToWidenViaDuplication = [&]() -> SDValue {
9054 if (!canWidenViaDuplication(Mask))
9055 return SDValue();
9056 SmallVector<int, 4> LoInputs;
9057 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9058 [](int M) { return M >= 0 && M < 8; });
9059 std::sort(LoInputs.begin(), LoInputs.end());
9060 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9061 LoInputs.end());
9062 SmallVector<int, 4> HiInputs;
9063 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9064 [](int M) { return M >= 8; });
9065 std::sort(HiInputs.begin(), HiInputs.end());
9066 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9067 HiInputs.end());
9069 bool TargetLo = LoInputs.size() >= HiInputs.size();
9070 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9071 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9073 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9074 SmallDenseMap<int, int, 8> LaneMap;
9075 for (int I : InPlaceInputs) {
9076 PreDupI16Shuffle[I/2] = I/2;
9077 LaneMap[I] = I;
9078 }
9079 int j = TargetLo ? 0 : 4, je = j + 4;
9080 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9081 // Check if j is already a shuffle of this input. This happens when
9082 // there are two adjacent bytes after we move the low one.
9083 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9084 // If we haven't yet mapped the input, search for a slot into which
9085 // we can map it.
9086 while (j < je && PreDupI16Shuffle[j] != -1)
9087 ++j;
9089 if (j == je)
9090 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9091 return SDValue();
9093 // Map this input with the i16 shuffle.
9094 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9095 }
9097 // Update the lane map based on the mapping we ended up with.
9098 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9099 }
9100 V1 = DAG.getNode(
9101 ISD::BITCAST, DL, MVT::v16i8,
9102 DAG.getVectorShuffle(MVT::v8i16, DL,
9103 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9104 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9106 // Unpack the bytes to form the i16s that will be shuffled into place.
9107 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9108 MVT::v16i8, V1, V1);
9110 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9111 for (int i = 0; i < 16; ++i)
9112 if (Mask[i] != -1) {
9113 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9114 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9115 if (PostDupI16Shuffle[i / 2] == -1)
9116 PostDupI16Shuffle[i / 2] = MappedMask;
9117 else
9118 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9119 "Conflicting entrties in the original shuffle!");
9120 }
9121 return DAG.getNode(
9122 ISD::BITCAST, DL, MVT::v16i8,
9123 DAG.getVectorShuffle(MVT::v8i16, DL,
9124 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9125 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9126 };
9127 if (SDValue V = tryToWidenViaDuplication())
9128 return V;
9129 }
9131 // Check whether an interleaving lowering is likely to be more efficient.
9132 // This isn't perfect but it is a strong heuristic that tends to work well on
9133 // the kinds of shuffles that show up in practice.
9134 //
9135 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
9136 if (shouldLowerAsInterleaving(Mask)) {
9137 // FIXME: Figure out whether we should pack these into the low or high
9138 // halves.
9140 int EMask[16], OMask[16];
9141 for (int i = 0; i < 8; ++i) {
9142 EMask[i] = Mask[2*i];
9143 OMask[i] = Mask[2*i + 1];
9144 EMask[i + 8] = -1;
9145 OMask[i + 8] = -1;
9146 }
9148 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
9149 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
9151 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, Evens, Odds);
9152 }
9154 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9155 // with PSHUFB. It is important to do this before we attempt to generate any
9156 // blends but after all of the single-input lowerings. If the single input
9157 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9158 // want to preserve that and we can DAG combine any longer sequences into
9159 // a PSHUFB in the end. But once we start blending from multiple inputs,
9160 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9161 // and there are *very* few patterns that would actually be faster than the
9162 // PSHUFB approach because of its ability to zero lanes.
9163 //
9164 // FIXME: The only exceptions to the above are blends which are exact
9165 // interleavings with direct instructions supporting them. We currently don't
9166 // handle those well here.
9167 if (Subtarget->hasSSSE3()) {
9168 SDValue V1Mask[16];
9169 SDValue V2Mask[16];
9170 for (int i = 0; i < 16; ++i)
9171 if (Mask[i] == -1) {
9172 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9173 } else {
9174 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
9175 V2Mask[i] =
9176 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
9177 }
9178 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
9179 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9180 if (isSingleInputShuffleMask(Mask))
9181 return V1; // Single inputs are easy.
9183 // Otherwise, blend the two.
9184 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
9185 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9186 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9187 }
9189 // There are special ways we can lower some single-element blends.
9190 if (NumV2Elements == 1)
9191 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
9192 Mask, Subtarget, DAG))
9193 return V;
9195 // Check whether a compaction lowering can be done. This handles shuffles
9196 // which take every Nth element for some even N. See the helper function for
9197 // details.
9198 //
9199 // We special case these as they can be particularly efficiently handled with
9200 // the PACKUSB instruction on x86 and they show up in common patterns of
9201 // rearranging bytes to truncate wide elements.
9202 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9203 // NumEvenDrops is the power of two stride of the elements. Another way of
9204 // thinking about it is that we need to drop the even elements this many
9205 // times to get the original input.
9206 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9208 // First we need to zero all the dropped bytes.
9209 assert(NumEvenDrops <= 3 &&
9210 "No support for dropping even elements more than 3 times.");
9211 // We use the mask type to pick which bytes are preserved based on how many
9212 // elements are dropped.
9213 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9214 SDValue ByteClearMask =
9215 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
9216 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
9217 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9218 if (!IsSingleInput)
9219 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9221 // Now pack things back together.
9222 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9223 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9224 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9225 for (int i = 1; i < NumEvenDrops; ++i) {
9226 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9227 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9228 }
9230 return Result;
9231 }
9233 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9234 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9235 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9236 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9238 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9239 MutableArrayRef<int> V1HalfBlendMask,
9240 MutableArrayRef<int> V2HalfBlendMask) {
9241 for (int i = 0; i < 8; ++i)
9242 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9243 V1HalfBlendMask[i] = HalfMask[i];
9244 HalfMask[i] = i;
9245 } else if (HalfMask[i] >= 16) {
9246 V2HalfBlendMask[i] = HalfMask[i] - 16;
9247 HalfMask[i] = i + 8;
9248 }
9249 };
9250 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9251 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9253 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9255 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9256 MutableArrayRef<int> HiBlendMask) {
9257 SDValue V1, V2;
9258 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9259 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9260 // i16s.
9261 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9262 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9263 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9264 [](int M) { return M >= 0 && M % 2 == 1; })) {
9265 // Use a mask to drop the high bytes.
9266 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9267 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9268 DAG.getConstant(0x00FF, MVT::v8i16));
9270 // This will be a single vector shuffle instead of a blend so nuke V2.
9271 V2 = DAG.getUNDEF(MVT::v8i16);
9273 // Squash the masks to point directly into V1.
9274 for (int &M : LoBlendMask)
9275 if (M >= 0)
9276 M /= 2;
9277 for (int &M : HiBlendMask)
9278 if (M >= 0)
9279 M /= 2;
9280 } else {
9281 // Otherwise just unpack the low half of V into V1 and the high half into
9282 // V2 so that we can blend them as i16s.
9283 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9284 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9285 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9286 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9287 }
9289 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9290 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9291 return std::make_pair(BlendedLo, BlendedHi);
9292 };
9293 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9294 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9295 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9297 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9298 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9300 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9301 }
9303 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9304 ///
9305 /// This routine breaks down the specific type of 128-bit shuffle and
9306 /// dispatches to the lowering routines accordingly.
9307 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9308 MVT VT, const X86Subtarget *Subtarget,
9309 SelectionDAG &DAG) {
9310 switch (VT.SimpleTy) {
9311 case MVT::v2i64:
9312 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9313 case MVT::v2f64:
9314 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9315 case MVT::v4i32:
9316 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9317 case MVT::v4f32:
9318 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9319 case MVT::v8i16:
9320 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9321 case MVT::v16i8:
9322 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9324 default:
9325 llvm_unreachable("Unimplemented!");
9326 }
9327 }
9329 /// \brief Generic routine to split ector shuffle into half-sized shuffles.
9330 ///
9331 /// This routine just extracts two subvectors, shuffles them independently, and
9332 /// then concatenates them back together. This should work effectively with all
9333 /// AVX vector shuffle types.
9334 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9335 SDValue V2, ArrayRef<int> Mask,
9336 SelectionDAG &DAG) {
9337 assert(VT.getSizeInBits() >= 256 &&
9338 "Only for 256-bit or wider vector shuffles!");
9339 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9340 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9342 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9343 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9345 int NumElements = VT.getVectorNumElements();
9346 int SplitNumElements = NumElements / 2;
9347 MVT ScalarVT = VT.getScalarType();
9348 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9350 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9351 DAG.getIntPtrConstant(0));
9352 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9353 DAG.getIntPtrConstant(SplitNumElements));
9354 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9355 DAG.getIntPtrConstant(0));
9356 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9357 DAG.getIntPtrConstant(SplitNumElements));
9359 // Now create two 4-way blends of these half-width vectors.
9360 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9361 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9362 for (int i = 0; i < SplitNumElements; ++i) {
9363 int M = HalfMask[i];
9364 if (M >= NumElements) {
9365 V2BlendMask.push_back(M - NumElements);
9366 V1BlendMask.push_back(-1);
9367 BlendMask.push_back(SplitNumElements + i);
9368 } else if (M >= 0) {
9369 V2BlendMask.push_back(-1);
9370 V1BlendMask.push_back(M);
9371 BlendMask.push_back(i);
9372 } else {
9373 V2BlendMask.push_back(-1);
9374 V1BlendMask.push_back(-1);
9375 BlendMask.push_back(-1);
9376 }
9377 }
9378 SDValue V1Blend =
9379 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9380 SDValue V2Blend =
9381 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9382 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9383 };
9384 SDValue Lo = HalfBlend(LoMask);
9385 SDValue Hi = HalfBlend(HiMask);
9386 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9387 }
9389 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9390 /// a permutation and blend of those lanes.
9391 ///
9392 /// This essentially blends the out-of-lane inputs to each lane into the lane
9393 /// from a permuted copy of the vector. This lowering strategy results in four
9394 /// instructions in the worst case for a single-input cross lane shuffle which
9395 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9396 /// of. Special cases for each particular shuffle pattern should be handled
9397 /// prior to trying this lowering.
9398 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9399 SDValue V1, SDValue V2,
9400 ArrayRef<int> Mask,
9401 SelectionDAG &DAG) {
9402 // FIXME: This should probably be generalized for 512-bit vectors as well.
9403 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9404 int LaneSize = Mask.size() / 2;
9406 // If there are only inputs from one 128-bit lane, splitting will in fact be
9407 // less expensive. The flags track wether the given lane contains an element
9408 // that crosses to another lane.
9409 bool LaneCrossing[2] = {false, false};
9410 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9411 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9412 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9413 if (!LaneCrossing[0] || !LaneCrossing[1])
9414 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9416 if (isSingleInputShuffleMask(Mask)) {
9417 SmallVector<int, 32> FlippedBlendMask;
9418 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9419 FlippedBlendMask.push_back(
9420 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9421 ? Mask[i]
9422 : Mask[i] % LaneSize +
9423 (i / LaneSize) * LaneSize + Size));
9425 // Flip the vector, and blend the results which should now be in-lane. The
9426 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9427 // 5 for the high source. The value 3 selects the high half of source 2 and
9428 // the value 2 selects the low half of source 2. We only use source 2 to
9429 // allow folding it into a memory operand.
9430 unsigned PERMMask = 3 | 2 << 4;
9431 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9432 V1, DAG.getConstant(PERMMask, MVT::i8));
9433 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9434 }
9436 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9437 // will be handled by the above logic and a blend of the results, much like
9438 // other patterns in AVX.
9439 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9440 }
9442 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9443 ///
9444 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9445 /// isn't available.
9446 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9447 const X86Subtarget *Subtarget,
9448 SelectionDAG &DAG) {
9449 SDLoc DL(Op);
9450 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9451 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9452 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9453 ArrayRef<int> Mask = SVOp->getMask();
9454 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9456 if (isSingleInputShuffleMask(Mask)) {
9457 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
9458 // Non-half-crossing single input shuffles can be lowerid with an
9459 // interleaved permutation.
9460 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
9461 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
9462 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
9463 DAG.getConstant(VPERMILPMask, MVT::i8));
9464 }
9466 // With AVX2 we have direct support for this permutation.
9467 if (Subtarget->hasAVX2())
9468 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
9469 getV4X86ShuffleImm8ForMask(Mask, DAG));
9471 // Otherwise, fall back.
9472 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
9473 DAG);
9474 }
9476 // X86 has dedicated unpack instructions that can handle specific blend
9477 // operations: UNPCKH and UNPCKL.
9478 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
9479 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
9480 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
9481 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
9483 // If we have a single input to the zero element, insert that into V1 if we
9484 // can do so cheaply.
9485 int NumV2Elements =
9486 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
9487 if (NumV2Elements == 1 && Mask[0] >= 4)
9488 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
9489 MVT::v4f64, DL, V1, V2, Mask, Subtarget, DAG))
9490 return Insertion;
9492 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
9493 Subtarget, DAG))
9494 return Blend;
9496 // Check if the blend happens to exactly fit that of SHUFPD.
9497 if ((Mask[0] == -1 || Mask[0] < 2) &&
9498 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
9499 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
9500 (Mask[3] == -1 || Mask[3] >= 6)) {
9501 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
9502 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
9503 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
9504 DAG.getConstant(SHUFPDMask, MVT::i8));
9505 }
9506 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
9507 (Mask[1] == -1 || Mask[1] < 2) &&
9508 (Mask[2] == -1 || Mask[2] >= 6) &&
9509 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
9510 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
9511 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
9512 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
9513 DAG.getConstant(SHUFPDMask, MVT::i8));
9514 }
9516 // Otherwise fall back on generic blend lowering.
9517 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
9518 Mask, DAG);
9519 }
9521 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
9522 ///
9523 /// This routine is only called when we have AVX2 and thus a reasonable
9524 /// instruction set for v4i64 shuffling..
9525 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9526 const X86Subtarget *Subtarget,
9527 SelectionDAG &DAG) {
9528 SDLoc DL(Op);
9529 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9530 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9531 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9532 ArrayRef<int> Mask = SVOp->getMask();
9533 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9534 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
9536 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
9537 Subtarget, DAG))
9538 return Blend;
9540 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
9541 // use lower latency instructions that will operate on both 128-bit lanes.
9542 SmallVector<int, 2> RepeatedMask;
9543 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
9544 if (isSingleInputShuffleMask(Mask)) {
9545 int PSHUFDMask[] = {-1, -1, -1, -1};
9546 for (int i = 0; i < 2; ++i)
9547 if (RepeatedMask[i] >= 0) {
9548 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
9549 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
9550 }
9551 return DAG.getNode(
9552 ISD::BITCAST, DL, MVT::v4i64,
9553 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
9554 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
9555 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
9556 }
9558 // Use dedicated unpack instructions for masks that match their pattern.
9559 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
9560 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
9561 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
9562 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
9563 }
9565 // AVX2 provides a direct instruction for permuting a single input across
9566 // lanes.
9567 if (isSingleInputShuffleMask(Mask))
9568 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
9569 getV4X86ShuffleImm8ForMask(Mask, DAG));
9571 // Otherwise fall back on generic blend lowering.
9572 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
9573 Mask, DAG);
9574 }
9576 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
9577 ///
9578 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
9579 /// isn't available.
9580 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9581 const X86Subtarget *Subtarget,
9582 SelectionDAG &DAG) {
9583 SDLoc DL(Op);
9584 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9585 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9586 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9587 ArrayRef<int> Mask = SVOp->getMask();
9588 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9590 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
9591 Subtarget, DAG))
9592 return Blend;
9594 // If the shuffle mask is repeated in each 128-bit lane, we have many more
9595 // options to efficiently lower the shuffle.
9596 SmallVector<int, 4> RepeatedMask;
9597 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
9598 assert(RepeatedMask.size() == 4 &&
9599 "Repeated masks must be half the mask width!");
9600 if (isSingleInputShuffleMask(Mask))
9601 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
9602 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
9604 // Use dedicated unpack instructions for masks that match their pattern.
9605 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
9606 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
9607 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
9608 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
9610 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
9611 // have already handled any direct blends. We also need to squash the
9612 // repeated mask into a simulated v4f32 mask.
9613 for (int i = 0; i < 4; ++i)
9614 if (RepeatedMask[i] >= 8)
9615 RepeatedMask[i] -= 4;
9616 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
9617 }
9619 // If we have a single input shuffle with different shuffle patterns in the
9620 // two 128-bit lanes use the variable mask to VPERMILPS.
9621 if (isSingleInputShuffleMask(Mask)) {
9622 SDValue VPermMask[8];
9623 for (int i = 0; i < 8; ++i)
9624 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9625 : DAG.getConstant(Mask[i], MVT::i32);
9626 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
9627 return DAG.getNode(
9628 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
9629 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
9631 if (Subtarget->hasAVX2())
9632 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
9633 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
9634 DAG.getNode(ISD::BUILD_VECTOR, DL,
9635 MVT::v8i32, VPermMask)),
9636 V1);
9638 // Otherwise, fall back.
9639 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
9640 DAG);
9641 }
9643 // Otherwise fall back on generic blend lowering.
9644 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
9645 Mask, DAG);
9646 }
9648 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
9649 ///
9650 /// This routine is only called when we have AVX2 and thus a reasonable
9651 /// instruction set for v8i32 shuffling..
9652 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9653 const X86Subtarget *Subtarget,
9654 SelectionDAG &DAG) {
9655 SDLoc DL(Op);
9656 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9657 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9658 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9659 ArrayRef<int> Mask = SVOp->getMask();
9660 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9661 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
9663 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
9664 Subtarget, DAG))
9665 return Blend;
9667 // If the shuffle mask is repeated in each 128-bit lane we can use more
9668 // efficient instructions that mirror the shuffles across the two 128-bit
9669 // lanes.
9670 SmallVector<int, 4> RepeatedMask;
9671 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
9672 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
9673 if (isSingleInputShuffleMask(Mask))
9674 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
9675 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
9677 // Use dedicated unpack instructions for masks that match their pattern.
9678 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
9679 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
9680 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
9681 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
9682 }
9684 // If the shuffle patterns aren't repeated but it is a single input, directly
9685 // generate a cross-lane VPERMD instruction.
9686 if (isSingleInputShuffleMask(Mask)) {
9687 SDValue VPermMask[8];
9688 for (int i = 0; i < 8; ++i)
9689 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9690 : DAG.getConstant(Mask[i], MVT::i32);
9691 return DAG.getNode(
9692 X86ISD::VPERMV, DL, MVT::v8i32,
9693 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
9694 }
9696 // Otherwise fall back on generic blend lowering.
9697 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
9698 Mask, DAG);
9699 }
9701 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
9702 ///
9703 /// This routine is only called when we have AVX2 and thus a reasonable
9704 /// instruction set for v16i16 shuffling..
9705 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9706 const X86Subtarget *Subtarget,
9707 SelectionDAG &DAG) {
9708 SDLoc DL(Op);
9709 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9710 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9711 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9712 ArrayRef<int> Mask = SVOp->getMask();
9713 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9714 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
9716 // There are no generalized cross-lane shuffle operations available on i16
9717 // element types.
9718 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
9719 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
9720 Mask, DAG);
9722 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
9723 Subtarget, DAG))
9724 return Blend;
9726 // Use dedicated unpack instructions for masks that match their pattern.
9727 if (isShuffleEquivalent(Mask,
9728 // First 128-bit lane:
9729 0, 16, 1, 17, 2, 18, 3, 19,
9730 // Second 128-bit lane:
9731 8, 24, 9, 25, 10, 26, 11, 27))
9732 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
9733 if (isShuffleEquivalent(Mask,
9734 // First 128-bit lane:
9735 4, 20, 5, 21, 6, 22, 7, 23,
9736 // Second 128-bit lane:
9737 12, 28, 13, 29, 14, 30, 15, 31))
9738 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
9740 if (isSingleInputShuffleMask(Mask)) {
9741 SDValue PSHUFBMask[32];
9742 for (int i = 0; i < 16; ++i) {
9743 if (Mask[i] == -1) {
9744 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
9745 continue;
9746 }
9748 int M = i < 8 ? Mask[i] : Mask[i] - 8;
9749 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
9750 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, MVT::i8);
9751 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, MVT::i8);
9752 }
9753 return DAG.getNode(
9754 ISD::BITCAST, DL, MVT::v16i16,
9755 DAG.getNode(
9756 X86ISD::PSHUFB, DL, MVT::v32i8,
9757 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
9758 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
9759 }
9761 // Otherwise fall back on generic blend lowering.
9762 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i16, V1, V2,
9763 Mask, DAG);
9764 }
9766 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
9767 ///
9768 /// This routine is only called when we have AVX2 and thus a reasonable
9769 /// instruction set for v32i8 shuffling..
9770 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9771 const X86Subtarget *Subtarget,
9772 SelectionDAG &DAG) {
9773 SDLoc DL(Op);
9774 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9775 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9776 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9777 ArrayRef<int> Mask = SVOp->getMask();
9778 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
9779 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
9781 // There are no generalized cross-lane shuffle operations available on i8
9782 // element types.
9783 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
9784 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
9785 Mask, DAG);
9787 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
9788 Subtarget, DAG))
9789 return Blend;
9791 // Use dedicated unpack instructions for masks that match their pattern.
9792 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
9793 // 256-bit lanes.
9794 if (isShuffleEquivalent(
9795 Mask,
9796 // First 128-bit lane:
9797 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
9798 // Second 128-bit lane:
9799 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55))
9800 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
9801 if (isShuffleEquivalent(
9802 Mask,
9803 // First 128-bit lane:
9804 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
9805 // Second 128-bit lane:
9806 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63))
9807 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
9809 if (isSingleInputShuffleMask(Mask)) {
9810 SDValue PSHUFBMask[32];
9811 for (int i = 0; i < 32; ++i)
9812 PSHUFBMask[i] =
9813 Mask[i] < 0
9814 ? DAG.getUNDEF(MVT::i8)
9815 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, MVT::i8);
9817 return DAG.getNode(
9818 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
9819 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
9820 }
9822 // Otherwise fall back on generic blend lowering.
9823 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v32i8, V1, V2,
9824 Mask, DAG);
9825 }
9827 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
9828 ///
9829 /// This routine either breaks down the specific type of a 256-bit x86 vector
9830 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
9831 /// together based on the available instructions.
9832 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9833 MVT VT, const X86Subtarget *Subtarget,
9834 SelectionDAG &DAG) {
9835 SDLoc DL(Op);
9836 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9837 ArrayRef<int> Mask = SVOp->getMask();
9839 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
9840 // check for those subtargets here and avoid much of the subtarget querying in
9841 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
9842 // ability to manipulate a 256-bit vector with integer types. Since we'll use
9843 // floating point types there eventually, just immediately cast everything to
9844 // a float and operate entirely in that domain.
9845 if (VT.isInteger() && !Subtarget->hasAVX2()) {
9846 int ElementBits = VT.getScalarSizeInBits();
9847 if (ElementBits < 32)
9848 // No floating point type available, decompose into 128-bit vectors.
9849 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9851 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
9852 VT.getVectorNumElements());
9853 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
9854 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
9855 return DAG.getNode(ISD::BITCAST, DL, VT,
9856 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
9857 }
9859 switch (VT.SimpleTy) {
9860 case MVT::v4f64:
9861 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9862 case MVT::v4i64:
9863 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9864 case MVT::v8f32:
9865 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9866 case MVT::v8i32:
9867 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9868 case MVT::v16i16:
9869 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9870 case MVT::v32i8:
9871 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9873 default:
9874 llvm_unreachable("Not a valid 256-bit x86 vector type!");
9875 }
9876 }
9878 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
9879 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9880 const X86Subtarget *Subtarget,
9881 SelectionDAG &DAG) {
9882 SDLoc DL(Op);
9883 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
9884 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
9885 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9886 ArrayRef<int> Mask = SVOp->getMask();
9887 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9889 // FIXME: Implement direct support for this type!
9890 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
9891 }
9893 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
9894 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9895 const X86Subtarget *Subtarget,
9896 SelectionDAG &DAG) {
9897 SDLoc DL(Op);
9898 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
9899 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
9900 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9901 ArrayRef<int> Mask = SVOp->getMask();
9902 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9904 // FIXME: Implement direct support for this type!
9905 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
9906 }
9908 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
9909 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9910 const X86Subtarget *Subtarget,
9911 SelectionDAG &DAG) {
9912 SDLoc DL(Op);
9913 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
9914 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
9915 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9916 ArrayRef<int> Mask = SVOp->getMask();
9917 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9918 assert(Subtarget->hasDQI() && "We can only lower v8i64 with AVX-512-DQI");
9920 // FIXME: Implement direct support for this type!
9921 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
9922 }
9924 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
9925 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9926 const X86Subtarget *Subtarget,
9927 SelectionDAG &DAG) {
9928 SDLoc DL(Op);
9929 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
9930 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
9931 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9932 ArrayRef<int> Mask = SVOp->getMask();
9933 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9934 assert(Subtarget->hasDQI() && "We can only lower v16i32 with AVX-512-DQI!");
9936 // FIXME: Implement direct support for this type!
9937 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
9938 }
9940 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
9941 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9942 const X86Subtarget *Subtarget,
9943 SelectionDAG &DAG) {
9944 SDLoc DL(Op);
9945 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
9946 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
9947 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9948 ArrayRef<int> Mask = SVOp->getMask();
9949 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
9950 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
9952 // FIXME: Implement direct support for this type!
9953 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
9954 }
9956 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
9957 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9958 const X86Subtarget *Subtarget,
9959 SelectionDAG &DAG) {
9960 SDLoc DL(Op);
9961 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
9962 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
9963 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9964 ArrayRef<int> Mask = SVOp->getMask();
9965 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
9966 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
9968 // FIXME: Implement direct support for this type!
9969 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
9970 }
9972 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
9973 ///
9974 /// This routine either breaks down the specific type of a 512-bit x86 vector
9975 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
9976 /// together based on the available instructions.
9977 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9978 MVT VT, const X86Subtarget *Subtarget,
9979 SelectionDAG &DAG) {
9980 SDLoc DL(Op);
9981 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9982 ArrayRef<int> Mask = SVOp->getMask();
9983 assert(Subtarget->hasAVX512() &&
9984 "Cannot lower 512-bit vectors w/ basic ISA!");
9986 // Dispatch to each element type for lowering. If we don't have supprot for
9987 // specific element type shuffles at 512 bits, immediately split them and
9988 // lower them. Each lowering routine of a given type is allowed to assume that
9989 // the requisite ISA extensions for that element type are available.
9990 switch (VT.SimpleTy) {
9991 case MVT::v8f64:
9992 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9993 case MVT::v16f32:
9994 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9995 case MVT::v8i64:
9996 if (Subtarget->hasDQI())
9997 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9998 break;
9999 case MVT::v16i32:
10000 if (Subtarget->hasDQI())
10001 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10002 break;
10003 case MVT::v32i16:
10004 if (Subtarget->hasBWI())
10005 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10006 break;
10007 case MVT::v64i8:
10008 if (Subtarget->hasBWI())
10009 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10010 break;
10012 default:
10013 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10014 }
10016 // Otherwise fall back on splitting.
10017 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10018 }
10020 /// \brief Helper function to test whether a shuffle mask could be
10021 /// simplified by widening the elements being shuffled.
10022 ///
10023 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
10024 /// leaves it in an unspecified state.
10025 ///
10026 /// NOTE: This must handle normal vector shuffle masks and *target* vector
10027 /// shuffle masks. The latter have the special property of a '-2' representing
10028 /// a zero-ed lane of a vector.
10029 static bool canWidenShuffleElements(ArrayRef<int> Mask,
10030 SmallVectorImpl<int> &WidenedMask) {
10031 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
10032 // If both elements are undef, its trivial.
10033 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
10034 WidenedMask.push_back(SM_SentinelUndef);
10035 continue;
10036 }
10038 // Check for an undef mask and a mask value properly aligned to fit with
10039 // a pair of values. If we find such a case, use the non-undef mask's value.
10040 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
10041 WidenedMask.push_back(Mask[i + 1] / 2);
10042 continue;
10043 }
10044 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
10045 WidenedMask.push_back(Mask[i] / 2);
10046 continue;
10047 }
10049 // When zeroing, we need to spread the zeroing across both lanes to widen.
10050 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
10051 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
10052 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
10053 WidenedMask.push_back(SM_SentinelZero);
10054 continue;
10055 }
10056 return false;
10057 }
10059 // Finally check if the two mask values are adjacent and aligned with
10060 // a pair.
10061 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
10062 WidenedMask.push_back(Mask[i] / 2);
10063 continue;
10064 }
10066 // Otherwise we can't safely widen the elements used in this shuffle.
10067 return false;
10068 }
10069 assert(WidenedMask.size() == Mask.size() / 2 &&
10070 "Incorrect size of mask after widening the elements!");
10072 return true;
10073 }
10075 /// \brief Top-level lowering for x86 vector shuffles.
10076 ///
10077 /// This handles decomposition, canonicalization, and lowering of all x86
10078 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10079 /// above in helper routines. The canonicalization attempts to widen shuffles
10080 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10081 /// s.t. only one of the two inputs needs to be tested, etc.
10082 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10083 SelectionDAG &DAG) {
10084 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10085 ArrayRef<int> Mask = SVOp->getMask();
10086 SDValue V1 = Op.getOperand(0);
10087 SDValue V2 = Op.getOperand(1);
10088 MVT VT = Op.getSimpleValueType();
10089 int NumElements = VT.getVectorNumElements();
10090 SDLoc dl(Op);
10092 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10094 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10095 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10096 if (V1IsUndef && V2IsUndef)
10097 return DAG.getUNDEF(VT);
10099 // When we create a shuffle node we put the UNDEF node to second operand,
10100 // but in some cases the first operand may be transformed to UNDEF.
10101 // In this case we should just commute the node.
10102 if (V1IsUndef)
10103 return DAG.getCommutedVectorShuffle(*SVOp);
10105 // Check for non-undef masks pointing at an undef vector and make the masks
10106 // undef as well. This makes it easier to match the shuffle based solely on
10107 // the mask.
10108 if (V2IsUndef)
10109 for (int M : Mask)
10110 if (M >= NumElements) {
10111 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10112 for (int &M : NewMask)
10113 if (M >= NumElements)
10114 M = -1;
10115 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10116 }
10118 // For integer vector shuffles, try to collapse them into a shuffle of fewer
10119 // lanes but wider integers. We cap this to not form integers larger than i64
10120 // but it might be interesting to form i128 integers to handle flipping the
10121 // low and high halves of AVX 256-bit vectors.
10122 SmallVector<int, 16> WidenedMask;
10123 if (VT.isInteger() && VT.getScalarSizeInBits() < 64 &&
10124 canWidenShuffleElements(Mask, WidenedMask)) {
10125 MVT NewVT =
10126 MVT::getVectorVT(MVT::getIntegerVT(VT.getScalarSizeInBits() * 2),
10127 VT.getVectorNumElements() / 2);
10128 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
10129 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
10130 return DAG.getNode(ISD::BITCAST, dl, VT,
10131 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10132 }
10134 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10135 for (int M : SVOp->getMask())
10136 if (M < 0)
10137 ++NumUndefElements;
10138 else if (M < NumElements)
10139 ++NumV1Elements;
10140 else
10141 ++NumV2Elements;
10143 // Commute the shuffle as needed such that more elements come from V1 than
10144 // V2. This allows us to match the shuffle pattern strictly on how many
10145 // elements come from V1 without handling the symmetric cases.
10146 if (NumV2Elements > NumV1Elements)
10147 return DAG.getCommutedVectorShuffle(*SVOp);
10149 // When the number of V1 and V2 elements are the same, try to minimize the
10150 // number of uses of V2 in the low half of the vector. When that is tied,
10151 // ensure that the sum of indices for V1 is equal to or lower than the sum
10152 // indices for V2.
10153 if (NumV1Elements == NumV2Elements) {
10154 int LowV1Elements = 0, LowV2Elements = 0;
10155 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10156 if (M >= NumElements)
10157 ++LowV2Elements;
10158 else if (M >= 0)
10159 ++LowV1Elements;
10160 if (LowV2Elements > LowV1Elements) {
10161 return DAG.getCommutedVectorShuffle(*SVOp);
10162 } else if (LowV2Elements == LowV1Elements) {
10163 int SumV1Indices = 0, SumV2Indices = 0;
10164 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10165 if (SVOp->getMask()[i] >= NumElements)
10166 SumV2Indices += i;
10167 else if (SVOp->getMask()[i] >= 0)
10168 SumV1Indices += i;
10169 if (SumV2Indices < SumV1Indices)
10170 return DAG.getCommutedVectorShuffle(*SVOp);
10171 }
10172 }
10174 // For each vector width, delegate to a specialized lowering routine.
10175 if (VT.getSizeInBits() == 128)
10176 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10178 if (VT.getSizeInBits() == 256)
10179 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10181 // Force AVX-512 vectors to be scalarized for now.
10182 // FIXME: Implement AVX-512 support!
10183 if (VT.getSizeInBits() == 512)
10184 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10186 llvm_unreachable("Unimplemented!");
10187 }
10190 //===----------------------------------------------------------------------===//
10191 // Legacy vector shuffle lowering
10192 //
10193 // This code is the legacy code handling vector shuffles until the above
10194 // replaces its functionality and performance.
10195 //===----------------------------------------------------------------------===//
10197 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
10198 bool hasInt256, unsigned *MaskOut = nullptr) {
10199 MVT EltVT = VT.getVectorElementType();
10201 // There is no blend with immediate in AVX-512.
10202 if (VT.is512BitVector())
10203 return false;
10205 if (!hasSSE41 || EltVT == MVT::i8)
10206 return false;
10207 if (!hasInt256 && VT == MVT::v16i16)
10208 return false;
10210 unsigned MaskValue = 0;
10211 unsigned NumElems = VT.getVectorNumElements();
10212 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10213 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10214 unsigned NumElemsInLane = NumElems / NumLanes;
10216 // Blend for v16i16 should be symetric for the both lanes.
10217 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10219 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
10220 int EltIdx = MaskVals[i];
10222 if ((EltIdx < 0 || EltIdx == (int)i) &&
10223 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
10224 continue;
10226 if (((unsigned)EltIdx == (i + NumElems)) &&
10227 (SndLaneEltIdx < 0 ||
10228 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
10229 MaskValue |= (1 << i);
10230 else
10231 return false;
10232 }
10234 if (MaskOut)
10235 *MaskOut = MaskValue;
10236 return true;
10237 }
10239 // Try to lower a shuffle node into a simple blend instruction.
10240 // This function assumes isBlendMask returns true for this
10241 // SuffleVectorSDNode
10242 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
10243 unsigned MaskValue,
10244 const X86Subtarget *Subtarget,
10245 SelectionDAG &DAG) {
10246 MVT VT = SVOp->getSimpleValueType(0);
10247 MVT EltVT = VT.getVectorElementType();
10248 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
10249 Subtarget->hasInt256() && "Trying to lower a "
10250 "VECTOR_SHUFFLE to a Blend but "
10251 "with the wrong mask"));
10252 SDValue V1 = SVOp->getOperand(0);
10253 SDValue V2 = SVOp->getOperand(1);
10254 SDLoc dl(SVOp);
10255 unsigned NumElems = VT.getVectorNumElements();
10257 // Convert i32 vectors to floating point if it is not AVX2.
10258 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
10259 MVT BlendVT = VT;
10260 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
10261 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
10262 NumElems);
10263 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
10264 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
10265 }
10267 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
10268 DAG.getConstant(MaskValue, MVT::i32));
10269 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
10270 }
10272 /// In vector type \p VT, return true if the element at index \p InputIdx
10273 /// falls on a different 128-bit lane than \p OutputIdx.
10274 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
10275 unsigned OutputIdx) {
10276 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
10277 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
10278 }
10280 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
10281 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
10282 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
10283 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
10284 /// zero.
10285 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
10286 SelectionDAG &DAG) {
10287 MVT VT = V1.getSimpleValueType();
10288 assert(VT.is128BitVector() || VT.is256BitVector());
10290 MVT EltVT = VT.getVectorElementType();
10291 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
10292 unsigned NumElts = VT.getVectorNumElements();
10294 SmallVector<SDValue, 32> PshufbMask;
10295 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
10296 int InputIdx = MaskVals[OutputIdx];
10297 unsigned InputByteIdx;
10299 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
10300 InputByteIdx = 0x80;
10301 else {
10302 // Cross lane is not allowed.
10303 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
10304 return SDValue();
10305 InputByteIdx = InputIdx * EltSizeInBytes;
10306 // Index is an byte offset within the 128-bit lane.
10307 InputByteIdx &= 0xf;
10308 }
10310 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
10311 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
10312 if (InputByteIdx != 0x80)
10313 ++InputByteIdx;
10314 }
10315 }
10317 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
10318 if (ShufVT != VT)
10319 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
10320 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
10321 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
10322 }
10324 // v8i16 shuffles - Prefer shuffles in the following order:
10325 // 1. [all] pshuflw, pshufhw, optional move
10326 // 2. [ssse3] 1 x pshufb
10327 // 3. [ssse3] 2 x pshufb + 1 x por
10328 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
10329 static SDValue
10330 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
10331 SelectionDAG &DAG) {
10332 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10333 SDValue V1 = SVOp->getOperand(0);
10334 SDValue V2 = SVOp->getOperand(1);
10335 SDLoc dl(SVOp);
10336 SmallVector<int, 8> MaskVals;
10338 // Determine if more than 1 of the words in each of the low and high quadwords
10339 // of the result come from the same quadword of one of the two inputs. Undef
10340 // mask values count as coming from any quadword, for better codegen.
10341 //
10342 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
10343 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
10344 unsigned LoQuad[] = { 0, 0, 0, 0 };
10345 unsigned HiQuad[] = { 0, 0, 0, 0 };
10346 // Indices of quads used.
10347 std::bitset<4> InputQuads;
10348 for (unsigned i = 0; i < 8; ++i) {
10349 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
10350 int EltIdx = SVOp->getMaskElt(i);
10351 MaskVals.push_back(EltIdx);
10352 if (EltIdx < 0) {
10353 ++Quad[0];
10354 ++Quad[1];
10355 ++Quad[2];
10356 ++Quad[3];
10357 continue;
10358 }
10359 ++Quad[EltIdx / 4];
10360 InputQuads.set(EltIdx / 4);
10361 }
10363 int BestLoQuad = -1;
10364 unsigned MaxQuad = 1;
10365 for (unsigned i = 0; i < 4; ++i) {
10366 if (LoQuad[i] > MaxQuad) {
10367 BestLoQuad = i;
10368 MaxQuad = LoQuad[i];
10369 }
10370 }
10372 int BestHiQuad = -1;
10373 MaxQuad = 1;
10374 for (unsigned i = 0; i < 4; ++i) {
10375 if (HiQuad[i] > MaxQuad) {
10376 BestHiQuad = i;
10377 MaxQuad = HiQuad[i];
10378 }
10379 }
10381 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
10382 // of the two input vectors, shuffle them into one input vector so only a
10383 // single pshufb instruction is necessary. If there are more than 2 input
10384 // quads, disable the next transformation since it does not help SSSE3.
10385 bool V1Used = InputQuads[0] || InputQuads[1];
10386 bool V2Used = InputQuads[2] || InputQuads[3];
10387 if (Subtarget->hasSSSE3()) {
10388 if (InputQuads.count() == 2 && V1Used && V2Used) {
10389 BestLoQuad = InputQuads[0] ? 0 : 1;
10390 BestHiQuad = InputQuads[2] ? 2 : 3;
10391 }
10392 if (InputQuads.count() > 2) {
10393 BestLoQuad = -1;
10394 BestHiQuad = -1;
10395 }
10396 }
10398 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
10399 // the shuffle mask. If a quad is scored as -1, that means that it contains
10400 // words from all 4 input quadwords.
10401 SDValue NewV;
10402 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
10403 int MaskV[] = {
10404 BestLoQuad < 0 ? 0 : BestLoQuad,
10405 BestHiQuad < 0 ? 1 : BestHiQuad
10406 };
10407 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
10408 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
10409 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
10410 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
10412 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
10413 // source words for the shuffle, to aid later transformations.
10414 bool AllWordsInNewV = true;
10415 bool InOrder[2] = { true, true };
10416 for (unsigned i = 0; i != 8; ++i) {
10417 int idx = MaskVals[i];
10418 if (idx != (int)i)
10419 InOrder[i/4] = false;
10420 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
10421 continue;
10422 AllWordsInNewV = false;
10423 break;
10424 }
10426 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
10427 if (AllWordsInNewV) {
10428 for (int i = 0; i != 8; ++i) {
10429 int idx = MaskVals[i];
10430 if (idx < 0)
10431 continue;
10432 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
10433 if ((idx != i) && idx < 4)
10434 pshufhw = false;
10435 if ((idx != i) && idx > 3)
10436 pshuflw = false;
10437 }
10438 V1 = NewV;
10439 V2Used = false;
10440 BestLoQuad = 0;
10441 BestHiQuad = 1;
10442 }
10444 // If we've eliminated the use of V2, and the new mask is a pshuflw or
10445 // pshufhw, that's as cheap as it gets. Return the new shuffle.
10446 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
10447 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
10448 unsigned TargetMask = 0;
10449 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
10450 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
10451 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10452 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
10453 getShufflePSHUFLWImmediate(SVOp);
10454 V1 = NewV.getOperand(0);
10455 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
10456 }
10457 }
10459 // Promote splats to a larger type which usually leads to more efficient code.
10460 // FIXME: Is this true if pshufb is available?
10461 if (SVOp->isSplat())
10462 return PromoteSplat(SVOp, DAG);
10464 // If we have SSSE3, and all words of the result are from 1 input vector,
10465 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
10466 // is present, fall back to case 4.
10467 if (Subtarget->hasSSSE3()) {
10468 SmallVector<SDValue,16> pshufbMask;
10470 // If we have elements from both input vectors, set the high bit of the
10471 // shuffle mask element to zero out elements that come from V2 in the V1
10472 // mask, and elements that come from V1 in the V2 mask, so that the two
10473 // results can be OR'd together.
10474 bool TwoInputs = V1Used && V2Used;
10475 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
10476 if (!TwoInputs)
10477 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10479 // Calculate the shuffle mask for the second input, shuffle it, and
10480 // OR it with the first shuffled input.
10481 CommuteVectorShuffleMask(MaskVals, 8);
10482 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
10483 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
10484 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10485 }
10487 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
10488 // and update MaskVals with new element order.
10489 std::bitset<8> InOrder;
10490 if (BestLoQuad >= 0) {
10491 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
10492 for (int i = 0; i != 4; ++i) {
10493 int idx = MaskVals[i];
10494 if (idx < 0) {
10495 InOrder.set(i);
10496 } else if ((idx / 4) == BestLoQuad) {
10497 MaskV[i] = idx & 3;
10498 InOrder.set(i);
10499 }
10500 }
10501 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
10502 &MaskV[0]);
10504 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
10505 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10506 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
10507 NewV.getOperand(0),
10508 getShufflePSHUFLWImmediate(SVOp), DAG);
10509 }
10510 }
10512 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
10513 // and update MaskVals with the new element order.
10514 if (BestHiQuad >= 0) {
10515 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
10516 for (unsigned i = 4; i != 8; ++i) {
10517 int idx = MaskVals[i];
10518 if (idx < 0) {
10519 InOrder.set(i);
10520 } else if ((idx / 4) == BestHiQuad) {
10521 MaskV[i] = (idx & 3) + 4;
10522 InOrder.set(i);
10523 }
10524 }
10525 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
10526 &MaskV[0]);
10528 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
10529 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10530 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
10531 NewV.getOperand(0),
10532 getShufflePSHUFHWImmediate(SVOp), DAG);
10533 }
10534 }
10536 // In case BestHi & BestLo were both -1, which means each quadword has a word
10537 // from each of the four input quadwords, calculate the InOrder bitvector now
10538 // before falling through to the insert/extract cleanup.
10539 if (BestLoQuad == -1 && BestHiQuad == -1) {
10540 NewV = V1;
10541 for (int i = 0; i != 8; ++i)
10542 if (MaskVals[i] < 0 || MaskVals[i] == i)
10543 InOrder.set(i);
10544 }
10546 // The other elements are put in the right place using pextrw and pinsrw.
10547 for (unsigned i = 0; i != 8; ++i) {
10548 if (InOrder[i])
10549 continue;
10550 int EltIdx = MaskVals[i];
10551 if (EltIdx < 0)
10552 continue;
10553 SDValue ExtOp = (EltIdx < 8) ?
10554 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
10555 DAG.getIntPtrConstant(EltIdx)) :
10556 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
10557 DAG.getIntPtrConstant(EltIdx - 8));
10558 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
10559 DAG.getIntPtrConstant(i));
10560 }
10561 return NewV;
10562 }
10564 /// \brief v16i16 shuffles
10565 ///
10566 /// FIXME: We only support generation of a single pshufb currently. We can
10567 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
10568 /// well (e.g 2 x pshufb + 1 x por).
10569 static SDValue
10570 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
10571 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10572 SDValue V1 = SVOp->getOperand(0);
10573 SDValue V2 = SVOp->getOperand(1);
10574 SDLoc dl(SVOp);
10576 if (V2.getOpcode() != ISD::UNDEF)
10577 return SDValue();
10579 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
10580 return getPSHUFB(MaskVals, V1, dl, DAG);
10581 }
10583 // v16i8 shuffles - Prefer shuffles in the following order:
10584 // 1. [ssse3] 1 x pshufb
10585 // 2. [ssse3] 2 x pshufb + 1 x por
10586 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
10587 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
10588 const X86Subtarget* Subtarget,
10589 SelectionDAG &DAG) {
10590 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10591 SDValue V1 = SVOp->getOperand(0);
10592 SDValue V2 = SVOp->getOperand(1);
10593 SDLoc dl(SVOp);
10594 ArrayRef<int> MaskVals = SVOp->getMask();
10596 // Promote splats to a larger type which usually leads to more efficient code.
10597 // FIXME: Is this true if pshufb is available?
10598 if (SVOp->isSplat())
10599 return PromoteSplat(SVOp, DAG);
10601 // If we have SSSE3, case 1 is generated when all result bytes come from
10602 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
10603 // present, fall back to case 3.
10605 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
10606 if (Subtarget->hasSSSE3()) {
10607 SmallVector<SDValue,16> pshufbMask;
10609 // If all result elements are from one input vector, then only translate
10610 // undef mask values to 0x80 (zero out result) in the pshufb mask.
10611 //
10612 // Otherwise, we have elements from both input vectors, and must zero out
10613 // elements that come from V2 in the first mask, and V1 in the second mask
10614 // so that we can OR them together.
10615 for (unsigned i = 0; i != 16; ++i) {
10616 int EltIdx = MaskVals[i];
10617 if (EltIdx < 0 || EltIdx >= 16)
10618 EltIdx = 0x80;
10619 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
10620 }
10621 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
10622 DAG.getNode(ISD::BUILD_VECTOR, dl,
10623 MVT::v16i8, pshufbMask));
10625 // As PSHUFB will zero elements with negative indices, it's safe to ignore
10626 // the 2nd operand if it's undefined or zero.
10627 if (V2.getOpcode() == ISD::UNDEF ||
10628 ISD::isBuildVectorAllZeros(V2.getNode()))
10629 return V1;
10631 // Calculate the shuffle mask for the second input, shuffle it, and
10632 // OR it with the first shuffled input.
10633 pshufbMask.clear();
10634 for (unsigned i = 0; i != 16; ++i) {
10635 int EltIdx = MaskVals[i];
10636 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
10637 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
10638 }
10639 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
10640 DAG.getNode(ISD::BUILD_VECTOR, dl,
10641 MVT::v16i8, pshufbMask));
10642 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
10643 }
10645 // No SSSE3 - Calculate in place words and then fix all out of place words
10646 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
10647 // the 16 different words that comprise the two doublequadword input vectors.
10648 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10649 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
10650 SDValue NewV = V1;
10651 for (int i = 0; i != 8; ++i) {
10652 int Elt0 = MaskVals[i*2];
10653 int Elt1 = MaskVals[i*2+1];
10655 // This word of the result is all undef, skip it.
10656 if (Elt0 < 0 && Elt1 < 0)
10657 continue;
10659 // This word of the result is already in the correct place, skip it.
10660 if ((Elt0 == i*2) && (Elt1 == i*2+1))
10661 continue;
10663 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
10664 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
10665 SDValue InsElt;
10667 // If Elt0 and Elt1 are defined, are consecutive, and can be load
10668 // using a single extract together, load it and store it.
10669 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
10670 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
10671 DAG.getIntPtrConstant(Elt1 / 2));
10672 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
10673 DAG.getIntPtrConstant(i));
10674 continue;
10675 }
10677 // If Elt1 is defined, extract it from the appropriate source. If the
10678 // source byte is not also odd, shift the extracted word left 8 bits
10679 // otherwise clear the bottom 8 bits if we need to do an or.
10680 if (Elt1 >= 0) {
10681 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
10682 DAG.getIntPtrConstant(Elt1 / 2));
10683 if ((Elt1 & 1) == 0)
10684 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
10685 DAG.getConstant(8,
10686 TLI.getShiftAmountTy(InsElt.getValueType())));
10687 else if (Elt0 >= 0)
10688 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
10689 DAG.getConstant(0xFF00, MVT::i16));
10690 }
10691 // If Elt0 is defined, extract it from the appropriate source. If the
10692 // source byte is not also even, shift the extracted word right 8 bits. If
10693 // Elt1 was also defined, OR the extracted values together before
10694 // inserting them in the result.
10695 if (Elt0 >= 0) {
10696 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
10697 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
10698 if ((Elt0 & 1) != 0)
10699 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
10700 DAG.getConstant(8,
10701 TLI.getShiftAmountTy(InsElt0.getValueType())));
10702 else if (Elt1 >= 0)
10703 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
10704 DAG.getConstant(0x00FF, MVT::i16));
10705 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
10706 : InsElt0;
10707 }
10708 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
10709 DAG.getIntPtrConstant(i));
10710 }
10711 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
10712 }
10714 // v32i8 shuffles - Translate to VPSHUFB if possible.
10715 static
10716 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
10717 const X86Subtarget *Subtarget,
10718 SelectionDAG &DAG) {
10719 MVT VT = SVOp->getSimpleValueType(0);
10720 SDValue V1 = SVOp->getOperand(0);
10721 SDValue V2 = SVOp->getOperand(1);
10722 SDLoc dl(SVOp);
10723 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
10725 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10726 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
10727 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
10729 // VPSHUFB may be generated if
10730 // (1) one of input vector is undefined or zeroinitializer.
10731 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
10732 // And (2) the mask indexes don't cross the 128-bit lane.
10733 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
10734 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
10735 return SDValue();
10737 if (V1IsAllZero && !V2IsAllZero) {
10738 CommuteVectorShuffleMask(MaskVals, 32);
10739 V1 = V2;
10740 }
10741 return getPSHUFB(MaskVals, V1, dl, DAG);
10742 }
10744 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
10745 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
10746 /// done when every pair / quad of shuffle mask elements point to elements in
10747 /// the right sequence. e.g.
10748 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
10749 static
10750 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
10751 SelectionDAG &DAG) {
10752 MVT VT = SVOp->getSimpleValueType(0);
10753 SDLoc dl(SVOp);
10754 unsigned NumElems = VT.getVectorNumElements();
10755 MVT NewVT;
10756 unsigned Scale;
10757 switch (VT.SimpleTy) {
10758 default: llvm_unreachable("Unexpected!");
10759 case MVT::v2i64:
10760 case MVT::v2f64:
10761 return SDValue(SVOp, 0);
10762 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
10763 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
10764 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
10765 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
10766 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
10767 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
10768 }
10770 SmallVector<int, 8> MaskVec;
10771 for (unsigned i = 0; i != NumElems; i += Scale) {
10772 int StartIdx = -1;
10773 for (unsigned j = 0; j != Scale; ++j) {
10774 int EltIdx = SVOp->getMaskElt(i+j);
10775 if (EltIdx < 0)
10776 continue;
10777 if (StartIdx < 0)
10778 StartIdx = (EltIdx / Scale);
10779 if (EltIdx != (int)(StartIdx*Scale + j))
10780 return SDValue();
10781 }
10782 MaskVec.push_back(StartIdx);
10783 }
10785 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
10786 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
10787 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
10788 }
10790 /// getVZextMovL - Return a zero-extending vector move low node.
10791 ///
10792 static SDValue getVZextMovL(MVT VT, MVT OpVT,
10793 SDValue SrcOp, SelectionDAG &DAG,
10794 const X86Subtarget *Subtarget, SDLoc dl) {
10795 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
10796 LoadSDNode *LD = nullptr;
10797 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
10798 LD = dyn_cast<LoadSDNode>(SrcOp);
10799 if (!LD) {
10800 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
10801 // instead.
10802 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
10803 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
10804 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
10805 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
10806 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
10807 // PR2108
10808 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
10809 return DAG.getNode(ISD::BITCAST, dl, VT,
10810 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
10811 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
10812 OpVT,
10813 SrcOp.getOperand(0)
10814 .getOperand(0))));
10815 }
10816 }
10817 }
10819 return DAG.getNode(ISD::BITCAST, dl, VT,
10820 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
10821 DAG.getNode(ISD::BITCAST, dl,
10822 OpVT, SrcOp)));
10823 }
10825 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
10826 /// which could not be matched by any known target speficic shuffle
10827 static SDValue
10828 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
10830 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
10831 if (NewOp.getNode())
10832 return NewOp;
10834 MVT VT = SVOp->getSimpleValueType(0);
10836 unsigned NumElems = VT.getVectorNumElements();
10837 unsigned NumLaneElems = NumElems / 2;
10839 SDLoc dl(SVOp);
10840 MVT EltVT = VT.getVectorElementType();
10841 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
10842 SDValue Output[2];
10844 SmallVector<int, 16> Mask;
10845 for (unsigned l = 0; l < 2; ++l) {
10846 // Build a shuffle mask for the output, discovering on the fly which
10847 // input vectors to use as shuffle operands (recorded in InputUsed).
10848 // If building a suitable shuffle vector proves too hard, then bail
10849 // out with UseBuildVector set.
10850 bool UseBuildVector = false;
10851 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
10852 unsigned LaneStart = l * NumLaneElems;
10853 for (unsigned i = 0; i != NumLaneElems; ++i) {
10854 // The mask element. This indexes into the input.
10855 int Idx = SVOp->getMaskElt(i+LaneStart);
10856 if (Idx < 0) {
10857 // the mask element does not index into any input vector.
10858 Mask.push_back(-1);
10859 continue;
10860 }
10862 // The input vector this mask element indexes into.
10863 int Input = Idx / NumLaneElems;
10865 // Turn the index into an offset from the start of the input vector.
10866 Idx -= Input * NumLaneElems;
10868 // Find or create a shuffle vector operand to hold this input.
10869 unsigned OpNo;
10870 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
10871 if (InputUsed[OpNo] == Input)
10872 // This input vector is already an operand.
10873 break;
10874 if (InputUsed[OpNo] < 0) {
10875 // Create a new operand for this input vector.
10876 InputUsed[OpNo] = Input;
10877 break;
10878 }
10879 }
10881 if (OpNo >= array_lengthof(InputUsed)) {
10882 // More than two input vectors used! Give up on trying to create a
10883 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
10884 UseBuildVector = true;
10885 break;
10886 }
10888 // Add the mask index for the new shuffle vector.
10889 Mask.push_back(Idx + OpNo * NumLaneElems);
10890 }
10892 if (UseBuildVector) {
10893 SmallVector<SDValue, 16> SVOps;
10894 for (unsigned i = 0; i != NumLaneElems; ++i) {
10895 // The mask element. This indexes into the input.
10896 int Idx = SVOp->getMaskElt(i+LaneStart);
10897 if (Idx < 0) {
10898 SVOps.push_back(DAG.getUNDEF(EltVT));
10899 continue;
10900 }
10902 // The input vector this mask element indexes into.
10903 int Input = Idx / NumElems;
10905 // Turn the index into an offset from the start of the input vector.
10906 Idx -= Input * NumElems;
10908 // Extract the vector element by hand.
10909 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
10910 SVOp->getOperand(Input),
10911 DAG.getIntPtrConstant(Idx)));
10912 }
10914 // Construct the output using a BUILD_VECTOR.
10915 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
10916 } else if (InputUsed[0] < 0) {
10917 // No input vectors were used! The result is undefined.
10918 Output[l] = DAG.getUNDEF(NVT);
10919 } else {
10920 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
10921 (InputUsed[0] % 2) * NumLaneElems,
10922 DAG, dl);
10923 // If only one input was used, use an undefined vector for the other.
10924 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
10925 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
10926 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
10927 // At least one input vector was used. Create a new shuffle vector.
10928 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
10929 }
10931 Mask.clear();
10932 }
10934 // Concatenate the result back
10935 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
10936 }
10938 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
10939 /// 4 elements, and match them with several different shuffle types.
10940 static SDValue
10941 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
10942 SDValue V1 = SVOp->getOperand(0);
10943 SDValue V2 = SVOp->getOperand(1);
10944 SDLoc dl(SVOp);
10945 MVT VT = SVOp->getSimpleValueType(0);
10947 assert(VT.is128BitVector() && "Unsupported vector size");
10949 std::pair<int, int> Locs[4];
10950 int Mask1[] = { -1, -1, -1, -1 };
10951 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
10953 unsigned NumHi = 0;
10954 unsigned NumLo = 0;
10955 for (unsigned i = 0; i != 4; ++i) {
10956 int Idx = PermMask[i];
10957 if (Idx < 0) {
10958 Locs[i] = std::make_pair(-1, -1);
10959 } else {
10960 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
10961 if (Idx < 4) {
10962 Locs[i] = std::make_pair(0, NumLo);
10963 Mask1[NumLo] = Idx;
10964 NumLo++;
10965 } else {
10966 Locs[i] = std::make_pair(1, NumHi);
10967 if (2+NumHi < 4)
10968 Mask1[2+NumHi] = Idx;
10969 NumHi++;
10970 }
10971 }
10972 }
10974 if (NumLo <= 2 && NumHi <= 2) {
10975 // If no more than two elements come from either vector. This can be
10976 // implemented with two shuffles. First shuffle gather the elements.
10977 // The second shuffle, which takes the first shuffle as both of its
10978 // vector operands, put the elements into the right order.
10979 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
10981 int Mask2[] = { -1, -1, -1, -1 };
10983 for (unsigned i = 0; i != 4; ++i)
10984 if (Locs[i].first != -1) {
10985 unsigned Idx = (i < 2) ? 0 : 4;
10986 Idx += Locs[i].first * 2 + Locs[i].second;
10987 Mask2[i] = Idx;
10988 }
10990 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
10991 }
10993 if (NumLo == 3 || NumHi == 3) {
10994 // Otherwise, we must have three elements from one vector, call it X, and
10995 // one element from the other, call it Y. First, use a shufps to build an
10996 // intermediate vector with the one element from Y and the element from X
10997 // that will be in the same half in the final destination (the indexes don't
10998 // matter). Then, use a shufps to build the final vector, taking the half
10999 // containing the element from Y from the intermediate, and the other half
11000 // from X.
11001 if (NumHi == 3) {
11002 // Normalize it so the 3 elements come from V1.
11003 CommuteVectorShuffleMask(PermMask, 4);
11004 std::swap(V1, V2);
11005 }
11007 // Find the element from V2.
11008 unsigned HiIndex;
11009 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
11010 int Val = PermMask[HiIndex];
11011 if (Val < 0)
11012 continue;
11013 if (Val >= 4)
11014 break;
11015 }
11017 Mask1[0] = PermMask[HiIndex];
11018 Mask1[1] = -1;
11019 Mask1[2] = PermMask[HiIndex^1];
11020 Mask1[3] = -1;
11021 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11023 if (HiIndex >= 2) {
11024 Mask1[0] = PermMask[0];
11025 Mask1[1] = PermMask[1];
11026 Mask1[2] = HiIndex & 1 ? 6 : 4;
11027 Mask1[3] = HiIndex & 1 ? 4 : 6;
11028 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11029 }
11031 Mask1[0] = HiIndex & 1 ? 2 : 0;
11032 Mask1[1] = HiIndex & 1 ? 0 : 2;
11033 Mask1[2] = PermMask[2];
11034 Mask1[3] = PermMask[3];
11035 if (Mask1[2] >= 0)
11036 Mask1[2] += 4;
11037 if (Mask1[3] >= 0)
11038 Mask1[3] += 4;
11039 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
11040 }
11042 // Break it into (shuffle shuffle_hi, shuffle_lo).
11043 int LoMask[] = { -1, -1, -1, -1 };
11044 int HiMask[] = { -1, -1, -1, -1 };
11046 int *MaskPtr = LoMask;
11047 unsigned MaskIdx = 0;
11048 unsigned LoIdx = 0;
11049 unsigned HiIdx = 2;
11050 for (unsigned i = 0; i != 4; ++i) {
11051 if (i == 2) {
11052 MaskPtr = HiMask;
11053 MaskIdx = 1;
11054 LoIdx = 0;
11055 HiIdx = 2;
11056 }
11057 int Idx = PermMask[i];
11058 if (Idx < 0) {
11059 Locs[i] = std::make_pair(-1, -1);
11060 } else if (Idx < 4) {
11061 Locs[i] = std::make_pair(MaskIdx, LoIdx);
11062 MaskPtr[LoIdx] = Idx;
11063 LoIdx++;
11064 } else {
11065 Locs[i] = std::make_pair(MaskIdx, HiIdx);
11066 MaskPtr[HiIdx] = Idx;
11067 HiIdx++;
11068 }
11069 }
11071 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
11072 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
11073 int MaskOps[] = { -1, -1, -1, -1 };
11074 for (unsigned i = 0; i != 4; ++i)
11075 if (Locs[i].first != -1)
11076 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
11077 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
11078 }
11080 static bool MayFoldVectorLoad(SDValue V) {
11081 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
11082 V = V.getOperand(0);
11084 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
11085 V = V.getOperand(0);
11086 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
11087 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
11088 // BUILD_VECTOR (load), undef
11089 V = V.getOperand(0);
11091 return MayFoldLoad(V);
11092 }
11094 static
11095 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
11096 MVT VT = Op.getSimpleValueType();
11098 // Canonizalize to v2f64.
11099 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
11100 return DAG.getNode(ISD::BITCAST, dl, VT,
11101 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
11102 V1, DAG));
11103 }
11105 static
11106 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
11107 bool HasSSE2) {
11108 SDValue V1 = Op.getOperand(0);
11109 SDValue V2 = Op.getOperand(1);
11110 MVT VT = Op.getSimpleValueType();
11112 assert(VT != MVT::v2i64 && "unsupported shuffle type");
11114 if (HasSSE2 && VT == MVT::v2f64)
11115 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
11117 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
11118 return DAG.getNode(ISD::BITCAST, dl, VT,
11119 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
11120 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
11121 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
11122 }
11124 static
11125 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
11126 SDValue V1 = Op.getOperand(0);
11127 SDValue V2 = Op.getOperand(1);
11128 MVT VT = Op.getSimpleValueType();
11130 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
11131 "unsupported shuffle type");
11133 if (V2.getOpcode() == ISD::UNDEF)
11134 V2 = V1;
11136 // v4i32 or v4f32
11137 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
11138 }
11140 static
11141 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
11142 SDValue V1 = Op.getOperand(0);
11143 SDValue V2 = Op.getOperand(1);
11144 MVT VT = Op.getSimpleValueType();
11145 unsigned NumElems = VT.getVectorNumElements();
11147 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
11148 // operand of these instructions is only memory, so check if there's a
11149 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
11150 // same masks.
11151 bool CanFoldLoad = false;
11153 // Trivial case, when V2 comes from a load.
11154 if (MayFoldVectorLoad(V2))
11155 CanFoldLoad = true;
11157 // When V1 is a load, it can be folded later into a store in isel, example:
11158 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
11159 // turns into:
11160 // (MOVLPSmr addr:$src1, VR128:$src2)
11161 // So, recognize this potential and also use MOVLPS or MOVLPD
11162 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
11163 CanFoldLoad = true;
11165 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11166 if (CanFoldLoad) {
11167 if (HasSSE2 && NumElems == 2)
11168 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
11170 if (NumElems == 4)
11171 // If we don't care about the second element, proceed to use movss.
11172 if (SVOp->getMaskElt(1) != -1)
11173 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
11174 }
11176 // movl and movlp will both match v2i64, but v2i64 is never matched by
11177 // movl earlier because we make it strict to avoid messing with the movlp load
11178 // folding logic (see the code above getMOVLP call). Match it here then,
11179 // this is horrible, but will stay like this until we move all shuffle
11180 // matching to x86 specific nodes. Note that for the 1st condition all
11181 // types are matched with movsd.
11182 if (HasSSE2) {
11183 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
11184 // as to remove this logic from here, as much as possible
11185 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
11186 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11187 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11188 }
11190 assert(VT != MVT::v4i32 && "unsupported shuffle type");
11192 // Invert the operand order and use SHUFPS to match it.
11193 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
11194 getShuffleSHUFImmediate(SVOp), DAG);
11195 }
11197 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
11198 SelectionDAG &DAG) {
11199 SDLoc dl(Load);
11200 MVT VT = Load->getSimpleValueType(0);
11201 MVT EVT = VT.getVectorElementType();
11202 SDValue Addr = Load->getOperand(1);
11203 SDValue NewAddr = DAG.getNode(
11204 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
11205 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
11207 SDValue NewLoad =
11208 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
11209 DAG.getMachineFunction().getMachineMemOperand(
11210 Load->getMemOperand(), 0, EVT.getStoreSize()));
11211 return NewLoad;
11212 }
11214 // It is only safe to call this function if isINSERTPSMask is true for
11215 // this shufflevector mask.
11216 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
11217 SelectionDAG &DAG) {
11218 // Generate an insertps instruction when inserting an f32 from memory onto a
11219 // v4f32 or when copying a member from one v4f32 to another.
11220 // We also use it for transferring i32 from one register to another,
11221 // since it simply copies the same bits.
11222 // If we're transferring an i32 from memory to a specific element in a
11223 // register, we output a generic DAG that will match the PINSRD
11224 // instruction.
11225 MVT VT = SVOp->getSimpleValueType(0);
11226 MVT EVT = VT.getVectorElementType();
11227 SDValue V1 = SVOp->getOperand(0);
11228 SDValue V2 = SVOp->getOperand(1);
11229 auto Mask = SVOp->getMask();
11230 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
11231 "unsupported vector type for insertps/pinsrd");
11233 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
11234 auto FromV2Predicate = [](const int &i) { return i >= 4; };
11235 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
11237 SDValue From;
11238 SDValue To;
11239 unsigned DestIndex;
11240 if (FromV1 == 1) {
11241 From = V1;
11242 To = V2;
11243 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
11244 Mask.begin();
11246 // If we have 1 element from each vector, we have to check if we're
11247 // changing V1's element's place. If so, we're done. Otherwise, we
11248 // should assume we're changing V2's element's place and behave
11249 // accordingly.
11250 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
11251 assert(DestIndex <= INT32_MAX && "truncated destination index");
11252 if (FromV1 == FromV2 &&
11253 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
11254 From = V2;
11255 To = V1;
11256 DestIndex =
11257 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11258 }
11259 } else {
11260 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
11261 "More than one element from V1 and from V2, or no elements from one "
11262 "of the vectors. This case should not have returned true from "
11263 "isINSERTPSMask");
11264 From = V2;
11265 To = V1;
11266 DestIndex =
11267 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11268 }
11270 // Get an index into the source vector in the range [0,4) (the mask is
11271 // in the range [0,8) because it can address V1 and V2)
11272 unsigned SrcIndex = Mask[DestIndex] % 4;
11273 if (MayFoldLoad(From)) {
11274 // Trivial case, when From comes from a load and is only used by the
11275 // shuffle. Make it use insertps from the vector that we need from that
11276 // load.
11277 SDValue NewLoad =
11278 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
11279 if (!NewLoad.getNode())
11280 return SDValue();
11282 if (EVT == MVT::f32) {
11283 // Create this as a scalar to vector to match the instruction pattern.
11284 SDValue LoadScalarToVector =
11285 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
11286 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
11287 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
11288 InsertpsMask);
11289 } else { // EVT == MVT::i32
11290 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
11291 // instruction, to match the PINSRD instruction, which loads an i32 to a
11292 // certain vector element.
11293 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
11294 DAG.getConstant(DestIndex, MVT::i32));
11295 }
11296 }
11298 // Vector-element-to-vector
11299 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
11300 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
11301 }
11303 // Reduce a vector shuffle to zext.
11304 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
11305 SelectionDAG &DAG) {
11306 // PMOVZX is only available from SSE41.
11307 if (!Subtarget->hasSSE41())
11308 return SDValue();
11310 MVT VT = Op.getSimpleValueType();
11312 // Only AVX2 support 256-bit vector integer extending.
11313 if (!Subtarget->hasInt256() && VT.is256BitVector())
11314 return SDValue();
11316 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11317 SDLoc DL(Op);
11318 SDValue V1 = Op.getOperand(0);
11319 SDValue V2 = Op.getOperand(1);
11320 unsigned NumElems = VT.getVectorNumElements();
11322 // Extending is an unary operation and the element type of the source vector
11323 // won't be equal to or larger than i64.
11324 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
11325 VT.getVectorElementType() == MVT::i64)
11326 return SDValue();
11328 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
11329 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
11330 while ((1U << Shift) < NumElems) {
11331 if (SVOp->getMaskElt(1U << Shift) == 1)
11332 break;
11333 Shift += 1;
11334 // The maximal ratio is 8, i.e. from i8 to i64.
11335 if (Shift > 3)
11336 return SDValue();
11337 }
11339 // Check the shuffle mask.
11340 unsigned Mask = (1U << Shift) - 1;
11341 for (unsigned i = 0; i != NumElems; ++i) {
11342 int EltIdx = SVOp->getMaskElt(i);
11343 if ((i & Mask) != 0 && EltIdx != -1)
11344 return SDValue();
11345 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
11346 return SDValue();
11347 }
11349 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
11350 MVT NeVT = MVT::getIntegerVT(NBits);
11351 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
11353 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
11354 return SDValue();
11356 // Simplify the operand as it's prepared to be fed into shuffle.
11357 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
11358 if (V1.getOpcode() == ISD::BITCAST &&
11359 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
11360 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
11361 V1.getOperand(0).getOperand(0)
11362 .getSimpleValueType().getSizeInBits() == SignificantBits) {
11363 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
11364 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
11365 ConstantSDNode *CIdx =
11366 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
11367 // If it's foldable, i.e. normal load with single use, we will let code
11368 // selection to fold it. Otherwise, we will short the conversion sequence.
11369 if (CIdx && CIdx->getZExtValue() == 0 &&
11370 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
11371 MVT FullVT = V.getSimpleValueType();
11372 MVT V1VT = V1.getSimpleValueType();
11373 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
11374 // The "ext_vec_elt" node is wider than the result node.
11375 // In this case we should extract subvector from V.
11376 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
11377 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
11378 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
11379 FullVT.getVectorNumElements()/Ratio);
11380 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
11381 DAG.getIntPtrConstant(0));
11382 }
11383 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
11384 }
11385 }
11387 return DAG.getNode(ISD::BITCAST, DL, VT,
11388 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
11389 }
11391 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
11392 SelectionDAG &DAG) {
11393 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11394 MVT VT = Op.getSimpleValueType();
11395 SDLoc dl(Op);
11396 SDValue V1 = Op.getOperand(0);
11397 SDValue V2 = Op.getOperand(1);
11399 if (isZeroShuffle(SVOp))
11400 return getZeroVector(VT, Subtarget, DAG, dl);
11402 // Handle splat operations
11403 if (SVOp->isSplat()) {
11404 // Use vbroadcast whenever the splat comes from a foldable load
11405 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
11406 if (Broadcast.getNode())
11407 return Broadcast;
11408 }
11410 // Check integer expanding shuffles.
11411 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
11412 if (NewOp.getNode())
11413 return NewOp;
11415 // If the shuffle can be profitably rewritten as a narrower shuffle, then
11416 // do it!
11417 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
11418 VT == MVT::v32i8) {
11419 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11420 if (NewOp.getNode())
11421 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
11422 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
11423 // FIXME: Figure out a cleaner way to do this.
11424 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
11425 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11426 if (NewOp.getNode()) {
11427 MVT NewVT = NewOp.getSimpleValueType();
11428 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
11429 NewVT, true, false))
11430 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
11431 dl);
11432 }
11433 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
11434 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11435 if (NewOp.getNode()) {
11436 MVT NewVT = NewOp.getSimpleValueType();
11437 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
11438 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
11439 dl);
11440 }
11441 }
11442 }
11443 return SDValue();
11444 }
11446 SDValue
11447 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
11448 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11449 SDValue V1 = Op.getOperand(0);
11450 SDValue V2 = Op.getOperand(1);
11451 MVT VT = Op.getSimpleValueType();
11452 SDLoc dl(Op);
11453 unsigned NumElems = VT.getVectorNumElements();
11454 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
11455 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11456 bool V1IsSplat = false;
11457 bool V2IsSplat = false;
11458 bool HasSSE2 = Subtarget->hasSSE2();
11459 bool HasFp256 = Subtarget->hasFp256();
11460 bool HasInt256 = Subtarget->hasInt256();
11461 MachineFunction &MF = DAG.getMachineFunction();
11462 bool OptForSize = MF.getFunction()->getAttributes().
11463 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
11465 // Check if we should use the experimental vector shuffle lowering. If so,
11466 // delegate completely to that code path.
11467 if (ExperimentalVectorShuffleLowering)
11468 return lowerVectorShuffle(Op, Subtarget, DAG);
11470 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
11472 if (V1IsUndef && V2IsUndef)
11473 return DAG.getUNDEF(VT);
11475 // When we create a shuffle node we put the UNDEF node to second operand,
11476 // but in some cases the first operand may be transformed to UNDEF.
11477 // In this case we should just commute the node.
11478 if (V1IsUndef)
11479 return DAG.getCommutedVectorShuffle(*SVOp);
11481 // Vector shuffle lowering takes 3 steps:
11482 //
11483 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
11484 // narrowing and commutation of operands should be handled.
11485 // 2) Matching of shuffles with known shuffle masks to x86 target specific
11486 // shuffle nodes.
11487 // 3) Rewriting of unmatched masks into new generic shuffle operations,
11488 // so the shuffle can be broken into other shuffles and the legalizer can
11489 // try the lowering again.
11490 //
11491 // The general idea is that no vector_shuffle operation should be left to
11492 // be matched during isel, all of them must be converted to a target specific
11493 // node here.
11495 // Normalize the input vectors. Here splats, zeroed vectors, profitable
11496 // narrowing and commutation of operands should be handled. The actual code
11497 // doesn't include all of those, work in progress...
11498 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
11499 if (NewOp.getNode())
11500 return NewOp;
11502 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
11504 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
11505 // unpckh_undef). Only use pshufd if speed is more important than size.
11506 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
11507 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11508 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
11509 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11511 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
11512 V2IsUndef && MayFoldVectorLoad(V1))
11513 return getMOVDDup(Op, dl, V1, DAG);
11515 if (isMOVHLPS_v_undef_Mask(M, VT))
11516 return getMOVHighToLow(Op, dl, DAG);
11518 // Use to match splats
11519 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
11520 (VT == MVT::v2f64 || VT == MVT::v2i64))
11521 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11523 if (isPSHUFDMask(M, VT)) {
11524 // The actual implementation will match the mask in the if above and then
11525 // during isel it can match several different instructions, not only pshufd
11526 // as its name says, sad but true, emulate the behavior for now...
11527 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
11528 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
11530 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
11532 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
11533 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
11535 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
11536 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1, TargetMask,
11537 DAG);
11539 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
11540 TargetMask, DAG);
11541 }
11543 if (isPALIGNRMask(M, VT, Subtarget))
11544 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
11545 getShufflePALIGNRImmediate(SVOp),
11546 DAG);
11548 if (isVALIGNMask(M, VT, Subtarget))
11549 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
11550 getShuffleVALIGNImmediate(SVOp),
11551 DAG);
11553 // Check if this can be converted into a logical shift.
11554 bool isLeft = false;
11555 unsigned ShAmt = 0;
11556 SDValue ShVal;
11557 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
11558 if (isShift && ShVal.hasOneUse()) {
11559 // If the shifted value has multiple uses, it may be cheaper to use
11560 // v_set0 + movlhps or movhlps, etc.
11561 MVT EltVT = VT.getVectorElementType();
11562 ShAmt *= EltVT.getSizeInBits();
11563 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
11564 }
11566 if (isMOVLMask(M, VT)) {
11567 if (ISD::isBuildVectorAllZeros(V1.getNode()))
11568 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
11569 if (!isMOVLPMask(M, VT)) {
11570 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
11571 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11573 if (VT == MVT::v4i32 || VT == MVT::v4f32)
11574 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11575 }
11576 }
11578 // FIXME: fold these into legal mask.
11579 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
11580 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
11582 if (isMOVHLPSMask(M, VT))
11583 return getMOVHighToLow(Op, dl, DAG);
11585 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
11586 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
11588 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
11589 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
11591 if (isMOVLPMask(M, VT))
11592 return getMOVLP(Op, dl, DAG, HasSSE2);
11594 if (ShouldXformToMOVHLPS(M, VT) ||
11595 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
11596 return DAG.getCommutedVectorShuffle(*SVOp);
11598 if (isShift) {
11599 // No better options. Use a vshldq / vsrldq.
11600 MVT EltVT = VT.getVectorElementType();
11601 ShAmt *= EltVT.getSizeInBits();
11602 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
11603 }
11605 bool Commuted = false;
11606 // FIXME: This should also accept a bitcast of a splat? Be careful, not
11607 // 1,1,1,1 -> v8i16 though.
11608 BitVector UndefElements;
11609 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
11610 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
11611 V1IsSplat = true;
11612 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
11613 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
11614 V2IsSplat = true;
11616 // Canonicalize the splat or undef, if present, to be on the RHS.
11617 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
11618 CommuteVectorShuffleMask(M, NumElems);
11619 std::swap(V1, V2);
11620 std::swap(V1IsSplat, V2IsSplat);
11621 Commuted = true;
11622 }
11624 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
11625 // Shuffling low element of v1 into undef, just return v1.
11626 if (V2IsUndef)
11627 return V1;
11628 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
11629 // the instruction selector will not match, so get a canonical MOVL with
11630 // swapped operands to undo the commute.
11631 return getMOVL(DAG, dl, VT, V2, V1);
11632 }
11634 if (isUNPCKLMask(M, VT, HasInt256))
11635 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11637 if (isUNPCKHMask(M, VT, HasInt256))
11638 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11640 if (V2IsSplat) {
11641 // Normalize mask so all entries that point to V2 points to its first
11642 // element then try to match unpck{h|l} again. If match, return a
11643 // new vector_shuffle with the corrected mask.p
11644 SmallVector<int, 8> NewMask(M.begin(), M.end());
11645 NormalizeMask(NewMask, NumElems);
11646 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
11647 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11648 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
11649 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11650 }
11652 if (Commuted) {
11653 // Commute is back and try unpck* again.
11654 // FIXME: this seems wrong.
11655 CommuteVectorShuffleMask(M, NumElems);
11656 std::swap(V1, V2);
11657 std::swap(V1IsSplat, V2IsSplat);
11659 if (isUNPCKLMask(M, VT, HasInt256))
11660 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11662 if (isUNPCKHMask(M, VT, HasInt256))
11663 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11664 }
11666 // Normalize the node to match x86 shuffle ops if needed
11667 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
11668 return DAG.getCommutedVectorShuffle(*SVOp);
11670 // The checks below are all present in isShuffleMaskLegal, but they are
11671 // inlined here right now to enable us to directly emit target specific
11672 // nodes, and remove one by one until they don't return Op anymore.
11674 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
11675 SVOp->getSplatIndex() == 0 && V2IsUndef) {
11676 if (VT == MVT::v2f64 || VT == MVT::v2i64)
11677 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11678 }
11680 if (isPSHUFHWMask(M, VT, HasInt256))
11681 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
11682 getShufflePSHUFHWImmediate(SVOp),
11683 DAG);
11685 if (isPSHUFLWMask(M, VT, HasInt256))
11686 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
11687 getShufflePSHUFLWImmediate(SVOp),
11688 DAG);
11690 unsigned MaskValue;
11691 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
11692 &MaskValue))
11693 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
11695 if (isSHUFPMask(M, VT))
11696 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
11697 getShuffleSHUFImmediate(SVOp), DAG);
11699 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
11700 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11701 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
11702 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11704 //===--------------------------------------------------------------------===//
11705 // Generate target specific nodes for 128 or 256-bit shuffles only
11706 // supported in the AVX instruction set.
11707 //
11709 // Handle VMOVDDUPY permutations
11710 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
11711 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
11713 // Handle VPERMILPS/D* permutations
11714 if (isVPERMILPMask(M, VT)) {
11715 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
11716 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
11717 getShuffleSHUFImmediate(SVOp), DAG);
11718 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1,
11719 getShuffleSHUFImmediate(SVOp), DAG);
11720 }
11722 unsigned Idx;
11723 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
11724 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
11725 Idx*(NumElems/2), DAG, dl);
11727 // Handle VPERM2F128/VPERM2I128 permutations
11728 if (isVPERM2X128Mask(M, VT, HasFp256))
11729 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
11730 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
11732 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
11733 return getINSERTPS(SVOp, dl, DAG);
11735 unsigned Imm8;
11736 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
11737 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
11739 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
11740 VT.is512BitVector()) {
11741 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
11742 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
11743 SmallVector<SDValue, 16> permclMask;
11744 for (unsigned i = 0; i != NumElems; ++i) {
11745 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
11746 }
11748 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
11749 if (V2IsUndef)
11750 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
11751 return DAG.getNode(X86ISD::VPERMV, dl, VT,
11752 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
11753 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
11754 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
11755 }
11757 //===--------------------------------------------------------------------===//
11758 // Since no target specific shuffle was selected for this generic one,
11759 // lower it into other known shuffles. FIXME: this isn't true yet, but
11760 // this is the plan.
11761 //
11763 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
11764 if (VT == MVT::v8i16) {
11765 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
11766 if (NewOp.getNode())
11767 return NewOp;
11768 }
11770 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
11771 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
11772 if (NewOp.getNode())
11773 return NewOp;
11774 }
11776 if (VT == MVT::v16i8) {
11777 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
11778 if (NewOp.getNode())
11779 return NewOp;
11780 }
11782 if (VT == MVT::v32i8) {
11783 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
11784 if (NewOp.getNode())
11785 return NewOp;
11786 }
11788 // Handle all 128-bit wide vectors with 4 elements, and match them with
11789 // several different shuffle types.
11790 if (NumElems == 4 && VT.is128BitVector())
11791 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
11793 // Handle general 256-bit shuffles
11794 if (VT.is256BitVector())
11795 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
11797 return SDValue();
11798 }
11800 // This function assumes its argument is a BUILD_VECTOR of constants or
11801 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
11802 // true.
11803 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
11804 unsigned &MaskValue) {
11805 MaskValue = 0;
11806 unsigned NumElems = BuildVector->getNumOperands();
11807 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
11808 unsigned NumLanes = (NumElems - 1) / 8 + 1;
11809 unsigned NumElemsInLane = NumElems / NumLanes;
11811 // Blend for v16i16 should be symetric for the both lanes.
11812 for (unsigned i = 0; i < NumElemsInLane; ++i) {
11813 SDValue EltCond = BuildVector->getOperand(i);
11814 SDValue SndLaneEltCond =
11815 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
11817 int Lane1Cond = -1, Lane2Cond = -1;
11818 if (isa<ConstantSDNode>(EltCond))
11819 Lane1Cond = !isZero(EltCond);
11820 if (isa<ConstantSDNode>(SndLaneEltCond))
11821 Lane2Cond = !isZero(SndLaneEltCond);
11823 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
11824 // Lane1Cond != 0, means we want the first argument.
11825 // Lane1Cond == 0, means we want the second argument.
11826 // The encoding of this argument is 0 for the first argument, 1
11827 // for the second. Therefore, invert the condition.
11828 MaskValue |= !Lane1Cond << i;
11829 else if (Lane1Cond < 0)
11830 MaskValue |= !Lane2Cond << i;
11831 else
11832 return false;
11833 }
11834 return true;
11835 }
11837 /// \brief Try to lower a VSELECT instruction to an immediate-controlled blend
11838 /// instruction.
11839 static SDValue lowerVSELECTtoBLENDI(SDValue Op, const X86Subtarget *Subtarget,
11840 SelectionDAG &DAG) {
11841 SDValue Cond = Op.getOperand(0);
11842 SDValue LHS = Op.getOperand(1);
11843 SDValue RHS = Op.getOperand(2);
11844 SDLoc dl(Op);
11845 MVT VT = Op.getSimpleValueType();
11846 MVT EltVT = VT.getVectorElementType();
11847 unsigned NumElems = VT.getVectorNumElements();
11849 // There is no blend with immediate in AVX-512.
11850 if (VT.is512BitVector())
11851 return SDValue();
11853 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
11854 return SDValue();
11855 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
11856 return SDValue();
11858 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
11859 return SDValue();
11861 // Check the mask for BLEND and build the value.
11862 unsigned MaskValue = 0;
11863 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
11864 return SDValue();
11866 // Convert i32 vectors to floating point if it is not AVX2.
11867 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
11868 MVT BlendVT = VT;
11869 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
11870 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
11871 NumElems);
11872 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
11873 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
11874 }
11876 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
11877 DAG.getConstant(MaskValue, MVT::i32));
11878 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
11879 }
11881 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
11882 // A vselect where all conditions and data are constants can be optimized into
11883 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
11884 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
11885 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
11886 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
11887 return SDValue();
11889 SDValue BlendOp = lowerVSELECTtoBLENDI(Op, Subtarget, DAG);
11890 if (BlendOp.getNode())
11891 return BlendOp;
11893 // Some types for vselect were previously set to Expand, not Legal or
11894 // Custom. Return an empty SDValue so we fall-through to Expand, after
11895 // the Custom lowering phase.
11896 MVT VT = Op.getSimpleValueType();
11897 switch (VT.SimpleTy) {
11898 default:
11899 break;
11900 case MVT::v8i16:
11901 case MVT::v16i16:
11902 if (Subtarget->hasBWI() && Subtarget->hasVLX())
11903 break;
11904 return SDValue();
11905 }
11907 // We couldn't create a "Blend with immediate" node.
11908 // This node should still be legal, but we'll have to emit a blendv*
11909 // instruction.
11910 return Op;
11911 }
11913 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
11914 MVT VT = Op.getSimpleValueType();
11915 SDLoc dl(Op);
11917 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
11918 return SDValue();
11920 if (VT.getSizeInBits() == 8) {
11921 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
11922 Op.getOperand(0), Op.getOperand(1));
11923 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11924 DAG.getValueType(VT));
11925 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11926 }
11928 if (VT.getSizeInBits() == 16) {
11929 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11930 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
11931 if (Idx == 0)
11932 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11933 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11934 DAG.getNode(ISD::BITCAST, dl,
11935 MVT::v4i32,
11936 Op.getOperand(0)),
11937 Op.getOperand(1)));
11938 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
11939 Op.getOperand(0), Op.getOperand(1));
11940 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11941 DAG.getValueType(VT));
11942 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11943 }
11945 if (VT == MVT::f32) {
11946 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
11947 // the result back to FR32 register. It's only worth matching if the
11948 // result has a single use which is a store or a bitcast to i32. And in
11949 // the case of a store, it's not worth it if the index is a constant 0,
11950 // because a MOVSSmr can be used instead, which is smaller and faster.
11951 if (!Op.hasOneUse())
11952 return SDValue();
11953 SDNode *User = *Op.getNode()->use_begin();
11954 if ((User->getOpcode() != ISD::STORE ||
11955 (isa<ConstantSDNode>(Op.getOperand(1)) &&
11956 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
11957 (User->getOpcode() != ISD::BITCAST ||
11958 User->getValueType(0) != MVT::i32))
11959 return SDValue();
11960 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11961 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
11962 Op.getOperand(0)),
11963 Op.getOperand(1));
11964 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
11965 }
11967 if (VT == MVT::i32 || VT == MVT::i64) {
11968 // ExtractPS/pextrq works with constant index.
11969 if (isa<ConstantSDNode>(Op.getOperand(1)))
11970 return Op;
11971 }
11972 return SDValue();
11973 }
11975 /// Extract one bit from mask vector, like v16i1 or v8i1.
11976 /// AVX-512 feature.
11977 SDValue
11978 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
11979 SDValue Vec = Op.getOperand(0);
11980 SDLoc dl(Vec);
11981 MVT VecVT = Vec.getSimpleValueType();
11982 SDValue Idx = Op.getOperand(1);
11983 MVT EltVT = Op.getSimpleValueType();
11985 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
11987 // variable index can't be handled in mask registers,
11988 // extend vector to VR512
11989 if (!isa<ConstantSDNode>(Idx)) {
11990 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11991 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
11992 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
11993 ExtVT.getVectorElementType(), Ext, Idx);
11994 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
11995 }
11997 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11998 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11999 unsigned MaxSift = rc->getSize()*8 - 1;
12000 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
12001 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12002 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
12003 DAG.getConstant(MaxSift, MVT::i8));
12004 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
12005 DAG.getIntPtrConstant(0));
12006 }
12008 SDValue
12009 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
12010 SelectionDAG &DAG) const {
12011 SDLoc dl(Op);
12012 SDValue Vec = Op.getOperand(0);
12013 MVT VecVT = Vec.getSimpleValueType();
12014 SDValue Idx = Op.getOperand(1);
12016 if (Op.getSimpleValueType() == MVT::i1)
12017 return ExtractBitFromMaskVector(Op, DAG);
12019 if (!isa<ConstantSDNode>(Idx)) {
12020 if (VecVT.is512BitVector() ||
12021 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
12022 VecVT.getVectorElementType().getSizeInBits() == 32)) {
12024 MVT MaskEltVT =
12025 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
12026 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
12027 MaskEltVT.getSizeInBits());
12029 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
12030 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
12031 getZeroVector(MaskVT, Subtarget, DAG, dl),
12032 Idx, DAG.getConstant(0, getPointerTy()));
12033 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
12034 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
12035 Perm, DAG.getConstant(0, getPointerTy()));
12036 }
12037 return SDValue();
12038 }
12040 // If this is a 256-bit vector result, first extract the 128-bit vector and
12041 // then extract the element from the 128-bit vector.
12042 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
12044 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12045 // Get the 128-bit vector.
12046 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
12047 MVT EltVT = VecVT.getVectorElementType();
12049 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
12051 //if (IdxVal >= NumElems/2)
12052 // IdxVal -= NumElems/2;
12053 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
12054 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
12055 DAG.getConstant(IdxVal, MVT::i32));
12056 }
12058 assert(VecVT.is128BitVector() && "Unexpected vector length");
12060 if (Subtarget->hasSSE41()) {
12061 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
12062 if (Res.getNode())
12063 return Res;
12064 }
12066 MVT VT = Op.getSimpleValueType();
12067 // TODO: handle v16i8.
12068 if (VT.getSizeInBits() == 16) {
12069 SDValue Vec = Op.getOperand(0);
12070 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12071 if (Idx == 0)
12072 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12073 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12074 DAG.getNode(ISD::BITCAST, dl,
12075 MVT::v4i32, Vec),
12076 Op.getOperand(1)));
12077 // Transform it so it match pextrw which produces a 32-bit result.
12078 MVT EltVT = MVT::i32;
12079 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
12080 Op.getOperand(0), Op.getOperand(1));
12081 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
12082 DAG.getValueType(VT));
12083 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12084 }
12086 if (VT.getSizeInBits() == 32) {
12087 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12088 if (Idx == 0)
12089 return Op;
12091 // SHUFPS the element to the lowest double word, then movss.
12092 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
12093 MVT VVT = Op.getOperand(0).getSimpleValueType();
12094 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12095 DAG.getUNDEF(VVT), Mask);
12096 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12097 DAG.getIntPtrConstant(0));
12098 }
12100 if (VT.getSizeInBits() == 64) {
12101 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
12102 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
12103 // to match extract_elt for f64.
12104 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12105 if (Idx == 0)
12106 return Op;
12108 // UNPCKHPD the element to the lowest double word, then movsd.
12109 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
12110 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
12111 int Mask[2] = { 1, -1 };
12112 MVT VVT = Op.getOperand(0).getSimpleValueType();
12113 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12114 DAG.getUNDEF(VVT), Mask);
12115 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12116 DAG.getIntPtrConstant(0));
12117 }
12119 return SDValue();
12120 }
12122 /// Insert one bit to mask vector, like v16i1 or v8i1.
12123 /// AVX-512 feature.
12124 SDValue
12125 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
12126 SDLoc dl(Op);
12127 SDValue Vec = Op.getOperand(0);
12128 SDValue Elt = Op.getOperand(1);
12129 SDValue Idx = Op.getOperand(2);
12130 MVT VecVT = Vec.getSimpleValueType();
12132 if (!isa<ConstantSDNode>(Idx)) {
12133 // Non constant index. Extend source and destination,
12134 // insert element and then truncate the result.
12135 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12136 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
12137 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
12138 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
12139 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
12140 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
12141 }
12143 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12144 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
12145 if (Vec.getOpcode() == ISD::UNDEF)
12146 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12147 DAG.getConstant(IdxVal, MVT::i8));
12148 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12149 unsigned MaxSift = rc->getSize()*8 - 1;
12150 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12151 DAG.getConstant(MaxSift, MVT::i8));
12152 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
12153 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12154 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
12155 }
12157 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
12158 SelectionDAG &DAG) const {
12159 MVT VT = Op.getSimpleValueType();
12160 MVT EltVT = VT.getVectorElementType();
12162 if (EltVT == MVT::i1)
12163 return InsertBitToMaskVector(Op, DAG);
12165 SDLoc dl(Op);
12166 SDValue N0 = Op.getOperand(0);
12167 SDValue N1 = Op.getOperand(1);
12168 SDValue N2 = Op.getOperand(2);
12169 if (!isa<ConstantSDNode>(N2))
12170 return SDValue();
12171 auto *N2C = cast<ConstantSDNode>(N2);
12172 unsigned IdxVal = N2C->getZExtValue();
12174 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
12175 // into that, and then insert the subvector back into the result.
12176 if (VT.is256BitVector() || VT.is512BitVector()) {
12177 // Get the desired 128-bit vector half.
12178 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
12180 // Insert the element into the desired half.
12181 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
12182 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
12184 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
12185 DAG.getConstant(IdxIn128, MVT::i32));
12187 // Insert the changed part back to the 256-bit vector
12188 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
12189 }
12190 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
12192 if (Subtarget->hasSSE41()) {
12193 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
12194 unsigned Opc;
12195 if (VT == MVT::v8i16) {
12196 Opc = X86ISD::PINSRW;
12197 } else {
12198 assert(VT == MVT::v16i8);
12199 Opc = X86ISD::PINSRB;
12200 }
12202 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
12203 // argument.
12204 if (N1.getValueType() != MVT::i32)
12205 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12206 if (N2.getValueType() != MVT::i32)
12207 N2 = DAG.getIntPtrConstant(IdxVal);
12208 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
12209 }
12211 if (EltVT == MVT::f32) {
12212 // Bits [7:6] of the constant are the source select. This will always be
12213 // zero here. The DAG Combiner may combine an extract_elt index into
12214 // these
12215 // bits. For example (insert (extract, 3), 2) could be matched by
12216 // putting
12217 // the '3' into bits [7:6] of X86ISD::INSERTPS.
12218 // Bits [5:4] of the constant are the destination select. This is the
12219 // value of the incoming immediate.
12220 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
12221 // combine either bitwise AND or insert of float 0.0 to set these bits.
12222 N2 = DAG.getIntPtrConstant(IdxVal << 4);
12223 // Create this as a scalar to vector..
12224 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
12225 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
12226 }
12228 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
12229 // PINSR* works with constant index.
12230 return Op;
12231 }
12232 }
12234 if (EltVT == MVT::i8)
12235 return SDValue();
12237 if (EltVT.getSizeInBits() == 16) {
12238 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
12239 // as its second argument.
12240 if (N1.getValueType() != MVT::i32)
12241 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12242 if (N2.getValueType() != MVT::i32)
12243 N2 = DAG.getIntPtrConstant(IdxVal);
12244 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
12245 }
12246 return SDValue();
12247 }
12249 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
12250 SDLoc dl(Op);
12251 MVT OpVT = Op.getSimpleValueType();
12253 // If this is a 256-bit vector result, first insert into a 128-bit
12254 // vector and then insert into the 256-bit vector.
12255 if (!OpVT.is128BitVector()) {
12256 // Insert into a 128-bit vector.
12257 unsigned SizeFactor = OpVT.getSizeInBits()/128;
12258 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
12259 OpVT.getVectorNumElements() / SizeFactor);
12261 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
12263 // Insert the 128-bit vector.
12264 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
12265 }
12267 if (OpVT == MVT::v1i64 &&
12268 Op.getOperand(0).getValueType() == MVT::i64)
12269 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
12271 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
12272 assert(OpVT.is128BitVector() && "Expected an SSE type!");
12273 return DAG.getNode(ISD::BITCAST, dl, OpVT,
12274 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
12275 }
12277 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
12278 // a simple subregister reference or explicit instructions to grab
12279 // upper bits of a vector.
12280 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12281 SelectionDAG &DAG) {
12282 SDLoc dl(Op);
12283 SDValue In = Op.getOperand(0);
12284 SDValue Idx = Op.getOperand(1);
12285 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12286 MVT ResVT = Op.getSimpleValueType();
12287 MVT InVT = In.getSimpleValueType();
12289 if (Subtarget->hasFp256()) {
12290 if (ResVT.is128BitVector() &&
12291 (InVT.is256BitVector() || InVT.is512BitVector()) &&
12292 isa<ConstantSDNode>(Idx)) {
12293 return Extract128BitVector(In, IdxVal, DAG, dl);
12294 }
12295 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
12296 isa<ConstantSDNode>(Idx)) {
12297 return Extract256BitVector(In, IdxVal, DAG, dl);
12298 }
12299 }
12300 return SDValue();
12301 }
12303 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
12304 // simple superregister reference or explicit instructions to insert
12305 // the upper bits of a vector.
12306 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12307 SelectionDAG &DAG) {
12308 if (Subtarget->hasFp256()) {
12309 SDLoc dl(Op.getNode());
12310 SDValue Vec = Op.getNode()->getOperand(0);
12311 SDValue SubVec = Op.getNode()->getOperand(1);
12312 SDValue Idx = Op.getNode()->getOperand(2);
12314 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
12315 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
12316 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
12317 isa<ConstantSDNode>(Idx)) {
12318 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12319 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
12320 }
12322 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
12323 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
12324 isa<ConstantSDNode>(Idx)) {
12325 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12326 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
12327 }
12328 }
12329 return SDValue();
12330 }
12332 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
12333 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
12334 // one of the above mentioned nodes. It has to be wrapped because otherwise
12335 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
12336 // be used to form addressing mode. These wrapped nodes will be selected
12337 // into MOV32ri.
12338 SDValue
12339 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
12340 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
12342 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12343 // global base reg.
12344 unsigned char OpFlag = 0;
12345 unsigned WrapperKind = X86ISD::Wrapper;
12346 CodeModel::Model M = DAG.getTarget().getCodeModel();
12348 if (Subtarget->isPICStyleRIPRel() &&
12349 (M == CodeModel::Small || M == CodeModel::Kernel))
12350 WrapperKind = X86ISD::WrapperRIP;
12351 else if (Subtarget->isPICStyleGOT())
12352 OpFlag = X86II::MO_GOTOFF;
12353 else if (Subtarget->isPICStyleStubPIC())
12354 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12356 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
12357 CP->getAlignment(),
12358 CP->getOffset(), OpFlag);
12359 SDLoc DL(CP);
12360 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12361 // With PIC, the address is actually $g + Offset.
12362 if (OpFlag) {
12363 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12364 DAG.getNode(X86ISD::GlobalBaseReg,
12365 SDLoc(), getPointerTy()),
12366 Result);
12367 }
12369 return Result;
12370 }
12372 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
12373 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
12375 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12376 // global base reg.
12377 unsigned char OpFlag = 0;
12378 unsigned WrapperKind = X86ISD::Wrapper;
12379 CodeModel::Model M = DAG.getTarget().getCodeModel();
12381 if (Subtarget->isPICStyleRIPRel() &&
12382 (M == CodeModel::Small || M == CodeModel::Kernel))
12383 WrapperKind = X86ISD::WrapperRIP;
12384 else if (Subtarget->isPICStyleGOT())
12385 OpFlag = X86II::MO_GOTOFF;
12386 else if (Subtarget->isPICStyleStubPIC())
12387 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12389 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
12390 OpFlag);
12391 SDLoc DL(JT);
12392 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12394 // With PIC, the address is actually $g + Offset.
12395 if (OpFlag)
12396 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12397 DAG.getNode(X86ISD::GlobalBaseReg,
12398 SDLoc(), getPointerTy()),
12399 Result);
12401 return Result;
12402 }
12404 SDValue
12405 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
12406 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
12408 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12409 // global base reg.
12410 unsigned char OpFlag = 0;
12411 unsigned WrapperKind = X86ISD::Wrapper;
12412 CodeModel::Model M = DAG.getTarget().getCodeModel();
12414 if (Subtarget->isPICStyleRIPRel() &&
12415 (M == CodeModel::Small || M == CodeModel::Kernel)) {
12416 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
12417 OpFlag = X86II::MO_GOTPCREL;
12418 WrapperKind = X86ISD::WrapperRIP;
12419 } else if (Subtarget->isPICStyleGOT()) {
12420 OpFlag = X86II::MO_GOT;
12421 } else if (Subtarget->isPICStyleStubPIC()) {
12422 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
12423 } else if (Subtarget->isPICStyleStubNoDynamic()) {
12424 OpFlag = X86II::MO_DARWIN_NONLAZY;
12425 }
12427 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
12429 SDLoc DL(Op);
12430 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12432 // With PIC, the address is actually $g + Offset.
12433 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
12434 !Subtarget->is64Bit()) {
12435 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12436 DAG.getNode(X86ISD::GlobalBaseReg,
12437 SDLoc(), getPointerTy()),
12438 Result);
12439 }
12441 // For symbols that require a load from a stub to get the address, emit the
12442 // load.
12443 if (isGlobalStubReference(OpFlag))
12444 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
12445 MachinePointerInfo::getGOT(), false, false, false, 0);
12447 return Result;
12448 }
12450 SDValue
12451 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
12452 // Create the TargetBlockAddressAddress node.
12453 unsigned char OpFlags =
12454 Subtarget->ClassifyBlockAddressReference();
12455 CodeModel::Model M = DAG.getTarget().getCodeModel();
12456 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
12457 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
12458 SDLoc dl(Op);
12459 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
12460 OpFlags);
12462 if (Subtarget->isPICStyleRIPRel() &&
12463 (M == CodeModel::Small || M == CodeModel::Kernel))
12464 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
12465 else
12466 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
12468 // With PIC, the address is actually $g + Offset.
12469 if (isGlobalRelativeToPICBase(OpFlags)) {
12470 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
12471 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
12472 Result);
12473 }
12475 return Result;
12476 }
12478 SDValue
12479 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
12480 int64_t Offset, SelectionDAG &DAG) const {
12481 // Create the TargetGlobalAddress node, folding in the constant
12482 // offset if it is legal.
12483 unsigned char OpFlags =
12484 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
12485 CodeModel::Model M = DAG.getTarget().getCodeModel();
12486 SDValue Result;
12487 if (OpFlags == X86II::MO_NO_FLAG &&
12488 X86::isOffsetSuitableForCodeModel(Offset, M)) {
12489 // A direct static reference to a global.
12490 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
12491 Offset = 0;
12492 } else {
12493 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
12494 }
12496 if (Subtarget->isPICStyleRIPRel() &&
12497 (M == CodeModel::Small || M == CodeModel::Kernel))
12498 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
12499 else
12500 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
12502 // With PIC, the address is actually $g + Offset.
12503 if (isGlobalRelativeToPICBase(OpFlags)) {
12504 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
12505 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
12506 Result);
12507 }
12509 // For globals that require a load from a stub to get the address, emit the
12510 // load.
12511 if (isGlobalStubReference(OpFlags))
12512 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
12513 MachinePointerInfo::getGOT(), false, false, false, 0);
12515 // If there was a non-zero offset that we didn't fold, create an explicit
12516 // addition for it.
12517 if (Offset != 0)
12518 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
12519 DAG.getConstant(Offset, getPointerTy()));
12521 return Result;
12522 }
12524 SDValue
12525 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
12526 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
12527 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
12528 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
12529 }
12531 static SDValue
12532 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
12533 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
12534 unsigned char OperandFlags, bool LocalDynamic = false) {
12535 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12536 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12537 SDLoc dl(GA);
12538 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12539 GA->getValueType(0),
12540 GA->getOffset(),
12541 OperandFlags);
12543 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
12544 : X86ISD::TLSADDR;
12546 if (InFlag) {
12547 SDValue Ops[] = { Chain, TGA, *InFlag };
12548 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12549 } else {
12550 SDValue Ops[] = { Chain, TGA };
12551 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12552 }
12554 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
12555 MFI->setAdjustsStack(true);
12557 SDValue Flag = Chain.getValue(1);
12558 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
12559 }
12561 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
12562 static SDValue
12563 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12564 const EVT PtrVT) {
12565 SDValue InFlag;
12566 SDLoc dl(GA); // ? function entry point might be better
12567 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12568 DAG.getNode(X86ISD::GlobalBaseReg,
12569 SDLoc(), PtrVT), InFlag);
12570 InFlag = Chain.getValue(1);
12572 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
12573 }
12575 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
12576 static SDValue
12577 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12578 const EVT PtrVT) {
12579 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
12580 X86::RAX, X86II::MO_TLSGD);
12581 }
12583 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
12584 SelectionDAG &DAG,
12585 const EVT PtrVT,
12586 bool is64Bit) {
12587 SDLoc dl(GA);
12589 // Get the start address of the TLS block for this module.
12590 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
12591 .getInfo<X86MachineFunctionInfo>();
12592 MFI->incNumLocalDynamicTLSAccesses();
12594 SDValue Base;
12595 if (is64Bit) {
12596 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
12597 X86II::MO_TLSLD, /*LocalDynamic=*/true);
12598 } else {
12599 SDValue InFlag;
12600 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12601 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
12602 InFlag = Chain.getValue(1);
12603 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
12604 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
12605 }
12607 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
12608 // of Base.
12610 // Build x@dtpoff.
12611 unsigned char OperandFlags = X86II::MO_DTPOFF;
12612 unsigned WrapperKind = X86ISD::Wrapper;
12613 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12614 GA->getValueType(0),
12615 GA->getOffset(), OperandFlags);
12616 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12618 // Add x@dtpoff with the base.
12619 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
12620 }
12622 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
12623 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12624 const EVT PtrVT, TLSModel::Model model,
12625 bool is64Bit, bool isPIC) {
12626 SDLoc dl(GA);
12628 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
12629 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
12630 is64Bit ? 257 : 256));
12632 SDValue ThreadPointer =
12633 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
12634 MachinePointerInfo(Ptr), false, false, false, 0);
12636 unsigned char OperandFlags = 0;
12637 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
12638 // initialexec.
12639 unsigned WrapperKind = X86ISD::Wrapper;
12640 if (model == TLSModel::LocalExec) {
12641 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
12642 } else if (model == TLSModel::InitialExec) {
12643 if (is64Bit) {
12644 OperandFlags = X86II::MO_GOTTPOFF;
12645 WrapperKind = X86ISD::WrapperRIP;
12646 } else {
12647 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
12648 }
12649 } else {
12650 llvm_unreachable("Unexpected model");
12651 }
12653 // emit "addl x@ntpoff,%eax" (local exec)
12654 // or "addl x@indntpoff,%eax" (initial exec)
12655 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
12656 SDValue TGA =
12657 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
12658 GA->getOffset(), OperandFlags);
12659 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12661 if (model == TLSModel::InitialExec) {
12662 if (isPIC && !is64Bit) {
12663 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
12664 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12665 Offset);
12666 }
12668 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
12669 MachinePointerInfo::getGOT(), false, false, false, 0);
12670 }
12672 // The address of the thread local variable is the add of the thread
12673 // pointer with the offset of the variable.
12674 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
12675 }
12677 SDValue
12678 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
12680 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
12681 const GlobalValue *GV = GA->getGlobal();
12683 if (Subtarget->isTargetELF()) {
12684 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
12686 switch (model) {
12687 case TLSModel::GeneralDynamic:
12688 if (Subtarget->is64Bit())
12689 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
12690 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
12691 case TLSModel::LocalDynamic:
12692 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
12693 Subtarget->is64Bit());
12694 case TLSModel::InitialExec:
12695 case TLSModel::LocalExec:
12696 return LowerToTLSExecModel(
12697 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
12698 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
12699 }
12700 llvm_unreachable("Unknown TLS model.");
12701 }
12703 if (Subtarget->isTargetDarwin()) {
12704 // Darwin only has one model of TLS. Lower to that.
12705 unsigned char OpFlag = 0;
12706 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
12707 X86ISD::WrapperRIP : X86ISD::Wrapper;
12709 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12710 // global base reg.
12711 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
12712 !Subtarget->is64Bit();
12713 if (PIC32)
12714 OpFlag = X86II::MO_TLVP_PIC_BASE;
12715 else
12716 OpFlag = X86II::MO_TLVP;
12717 SDLoc DL(Op);
12718 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
12719 GA->getValueType(0),
12720 GA->getOffset(), OpFlag);
12721 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12723 // With PIC32, the address is actually $g + Offset.
12724 if (PIC32)
12725 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12726 DAG.getNode(X86ISD::GlobalBaseReg,
12727 SDLoc(), getPointerTy()),
12728 Offset);
12730 // Lowering the machine isd will make sure everything is in the right
12731 // location.
12732 SDValue Chain = DAG.getEntryNode();
12733 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12734 SDValue Args[] = { Chain, Offset };
12735 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
12737 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
12738 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12739 MFI->setAdjustsStack(true);
12741 // And our return value (tls address) is in the standard call return value
12742 // location.
12743 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12744 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
12745 Chain.getValue(1));
12746 }
12748 if (Subtarget->isTargetKnownWindowsMSVC() ||
12749 Subtarget->isTargetWindowsGNU()) {
12750 // Just use the implicit TLS architecture
12751 // Need to generate someting similar to:
12752 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
12753 // ; from TEB
12754 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
12755 // mov rcx, qword [rdx+rcx*8]
12756 // mov eax, .tls$:tlsvar
12757 // [rax+rcx] contains the address
12758 // Windows 64bit: gs:0x58
12759 // Windows 32bit: fs:__tls_array
12761 SDLoc dl(GA);
12762 SDValue Chain = DAG.getEntryNode();
12764 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
12765 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
12766 // use its literal value of 0x2C.
12767 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
12768 ? Type::getInt8PtrTy(*DAG.getContext(),
12769 256)
12770 : Type::getInt32PtrTy(*DAG.getContext(),
12771 257));
12773 SDValue TlsArray =
12774 Subtarget->is64Bit()
12775 ? DAG.getIntPtrConstant(0x58)
12776 : (Subtarget->isTargetWindowsGNU()
12777 ? DAG.getIntPtrConstant(0x2C)
12778 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
12780 SDValue ThreadPointer =
12781 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
12782 MachinePointerInfo(Ptr), false, false, false, 0);
12784 // Load the _tls_index variable
12785 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
12786 if (Subtarget->is64Bit())
12787 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
12788 IDX, MachinePointerInfo(), MVT::i32,
12789 false, false, false, 0);
12790 else
12791 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
12792 false, false, false, 0);
12794 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
12795 getPointerTy());
12796 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
12798 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
12799 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
12800 false, false, false, 0);
12802 // Get the offset of start of .tls section
12803 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12804 GA->getValueType(0),
12805 GA->getOffset(), X86II::MO_SECREL);
12806 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
12808 // The address of the thread local variable is the add of the thread
12809 // pointer with the offset of the variable.
12810 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
12811 }
12813 llvm_unreachable("TLS not implemented for this target.");
12814 }
12816 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
12817 /// and take a 2 x i32 value to shift plus a shift amount.
12818 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
12819 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
12820 MVT VT = Op.getSimpleValueType();
12821 unsigned VTBits = VT.getSizeInBits();
12822 SDLoc dl(Op);
12823 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
12824 SDValue ShOpLo = Op.getOperand(0);
12825 SDValue ShOpHi = Op.getOperand(1);
12826 SDValue ShAmt = Op.getOperand(2);
12827 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
12828 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
12829 // during isel.
12830 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12831 DAG.getConstant(VTBits - 1, MVT::i8));
12832 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
12833 DAG.getConstant(VTBits - 1, MVT::i8))
12834 : DAG.getConstant(0, VT);
12836 SDValue Tmp2, Tmp3;
12837 if (Op.getOpcode() == ISD::SHL_PARTS) {
12838 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
12839 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
12840 } else {
12841 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
12842 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
12843 }
12845 // If the shift amount is larger or equal than the width of a part we can't
12846 // rely on the results of shld/shrd. Insert a test and select the appropriate
12847 // values for large shift amounts.
12848 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12849 DAG.getConstant(VTBits, MVT::i8));
12850 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
12851 AndNode, DAG.getConstant(0, MVT::i8));
12853 SDValue Hi, Lo;
12854 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
12855 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
12856 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
12858 if (Op.getOpcode() == ISD::SHL_PARTS) {
12859 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12860 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12861 } else {
12862 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12863 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12864 }
12866 SDValue Ops[2] = { Lo, Hi };
12867 return DAG.getMergeValues(Ops, dl);
12868 }
12870 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
12871 SelectionDAG &DAG) const {
12872 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
12874 if (SrcVT.isVector())
12875 return SDValue();
12877 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
12878 "Unknown SINT_TO_FP to lower!");
12880 // These are really Legal; return the operand so the caller accepts it as
12881 // Legal.
12882 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
12883 return Op;
12884 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
12885 Subtarget->is64Bit()) {
12886 return Op;
12887 }
12889 SDLoc dl(Op);
12890 unsigned Size = SrcVT.getSizeInBits()/8;
12891 MachineFunction &MF = DAG.getMachineFunction();
12892 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
12893 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12894 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12895 StackSlot,
12896 MachinePointerInfo::getFixedStack(SSFI),
12897 false, false, 0);
12898 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
12899 }
12901 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
12902 SDValue StackSlot,
12903 SelectionDAG &DAG) const {
12904 // Build the FILD
12905 SDLoc DL(Op);
12906 SDVTList Tys;
12907 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
12908 if (useSSE)
12909 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
12910 else
12911 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
12913 unsigned ByteSize = SrcVT.getSizeInBits()/8;
12915 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
12916 MachineMemOperand *MMO;
12917 if (FI) {
12918 int SSFI = FI->getIndex();
12919 MMO =
12920 DAG.getMachineFunction()
12921 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12922 MachineMemOperand::MOLoad, ByteSize, ByteSize);
12923 } else {
12924 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
12925 StackSlot = StackSlot.getOperand(1);
12926 }
12927 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
12928 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
12929 X86ISD::FILD, DL,
12930 Tys, Ops, SrcVT, MMO);
12932 if (useSSE) {
12933 Chain = Result.getValue(1);
12934 SDValue InFlag = Result.getValue(2);
12936 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
12937 // shouldn't be necessary except that RFP cannot be live across
12938 // multiple blocks. When stackifier is fixed, they can be uncoupled.
12939 MachineFunction &MF = DAG.getMachineFunction();
12940 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
12941 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
12942 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12943 Tys = DAG.getVTList(MVT::Other);
12944 SDValue Ops[] = {
12945 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
12946 };
12947 MachineMemOperand *MMO =
12948 DAG.getMachineFunction()
12949 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12950 MachineMemOperand::MOStore, SSFISize, SSFISize);
12952 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
12953 Ops, Op.getValueType(), MMO);
12954 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
12955 MachinePointerInfo::getFixedStack(SSFI),
12956 false, false, false, 0);
12957 }
12959 return Result;
12960 }
12962 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
12963 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
12964 SelectionDAG &DAG) const {
12965 // This algorithm is not obvious. Here it is what we're trying to output:
12966 /*
12967 movq %rax, %xmm0
12968 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
12969 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
12970 #ifdef __SSE3__
12971 haddpd %xmm0, %xmm0
12972 #else
12973 pshufd $0x4e, %xmm0, %xmm1
12974 addpd %xmm1, %xmm0
12975 #endif
12976 */
12978 SDLoc dl(Op);
12979 LLVMContext *Context = DAG.getContext();
12981 // Build some magic constants.
12982 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
12983 Constant *C0 = ConstantDataVector::get(*Context, CV0);
12984 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
12986 SmallVector<Constant*,2> CV1;
12987 CV1.push_back(
12988 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12989 APInt(64, 0x4330000000000000ULL))));
12990 CV1.push_back(
12991 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12992 APInt(64, 0x4530000000000000ULL))));
12993 Constant *C1 = ConstantVector::get(CV1);
12994 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
12996 // Load the 64-bit value into an XMM register.
12997 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
12998 Op.getOperand(0));
12999 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
13000 MachinePointerInfo::getConstantPool(),
13001 false, false, false, 16);
13002 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
13003 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
13004 CLod0);
13006 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
13007 MachinePointerInfo::getConstantPool(),
13008 false, false, false, 16);
13009 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
13010 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
13011 SDValue Result;
13013 if (Subtarget->hasSSE3()) {
13014 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
13015 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
13016 } else {
13017 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
13018 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
13019 S2F, 0x4E, DAG);
13020 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
13021 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
13022 Sub);
13023 }
13025 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
13026 DAG.getIntPtrConstant(0));
13027 }
13029 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
13030 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
13031 SelectionDAG &DAG) const {
13032 SDLoc dl(Op);
13033 // FP constant to bias correct the final result.
13034 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13035 MVT::f64);
13037 // Load the 32-bit value into an XMM register.
13038 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
13039 Op.getOperand(0));
13041 // Zero out the upper parts of the register.
13042 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
13044 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13045 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
13046 DAG.getIntPtrConstant(0));
13048 // Or the load with the bias.
13049 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
13050 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13051 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13052 MVT::v2f64, Load)),
13053 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13054 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13055 MVT::v2f64, Bias)));
13056 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13057 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
13058 DAG.getIntPtrConstant(0));
13060 // Subtract the bias.
13061 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
13063 // Handle final rounding.
13064 EVT DestVT = Op.getValueType();
13066 if (DestVT.bitsLT(MVT::f64))
13067 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
13068 DAG.getIntPtrConstant(0));
13069 if (DestVT.bitsGT(MVT::f64))
13070 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
13072 // Handle final rounding.
13073 return Sub;
13074 }
13076 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
13077 SelectionDAG &DAG) const {
13078 SDValue N0 = Op.getOperand(0);
13079 MVT SVT = N0.getSimpleValueType();
13080 SDLoc dl(Op);
13082 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
13083 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
13084 "Custom UINT_TO_FP is not supported!");
13086 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
13087 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13088 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
13089 }
13091 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
13092 SelectionDAG &DAG) const {
13093 SDValue N0 = Op.getOperand(0);
13094 SDLoc dl(Op);
13096 if (Op.getValueType().isVector())
13097 return lowerUINT_TO_FP_vec(Op, DAG);
13099 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
13100 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
13101 // the optimization here.
13102 if (DAG.SignBitIsZero(N0))
13103 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
13105 MVT SrcVT = N0.getSimpleValueType();
13106 MVT DstVT = Op.getSimpleValueType();
13107 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
13108 return LowerUINT_TO_FP_i64(Op, DAG);
13109 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
13110 return LowerUINT_TO_FP_i32(Op, DAG);
13111 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
13112 return SDValue();
13114 // Make a 64-bit buffer, and use it to build an FILD.
13115 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
13116 if (SrcVT == MVT::i32) {
13117 SDValue WordOff = DAG.getConstant(4, getPointerTy());
13118 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
13119 getPointerTy(), StackSlot, WordOff);
13120 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13121 StackSlot, MachinePointerInfo(),
13122 false, false, 0);
13123 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
13124 OffsetSlot, MachinePointerInfo(),
13125 false, false, 0);
13126 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
13127 return Fild;
13128 }
13130 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
13131 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13132 StackSlot, MachinePointerInfo(),
13133 false, false, 0);
13134 // For i64 source, we need to add the appropriate power of 2 if the input
13135 // was negative. This is the same as the optimization in
13136 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
13137 // we must be careful to do the computation in x87 extended precision, not
13138 // in SSE. (The generic code can't know it's OK to do this, or how to.)
13139 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
13140 MachineMemOperand *MMO =
13141 DAG.getMachineFunction()
13142 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13143 MachineMemOperand::MOLoad, 8, 8);
13145 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
13146 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
13147 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
13148 MVT::i64, MMO);
13150 APInt FF(32, 0x5F800000ULL);
13152 // Check whether the sign bit is set.
13153 SDValue SignSet = DAG.getSetCC(dl,
13154 getSetCCResultType(*DAG.getContext(), MVT::i64),
13155 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
13156 ISD::SETLT);
13158 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
13159 SDValue FudgePtr = DAG.getConstantPool(
13160 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
13161 getPointerTy());
13163 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
13164 SDValue Zero = DAG.getIntPtrConstant(0);
13165 SDValue Four = DAG.getIntPtrConstant(4);
13166 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
13167 Zero, Four);
13168 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
13170 // Load the value out, extending it from f32 to f80.
13171 // FIXME: Avoid the extend by constructing the right constant pool?
13172 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
13173 FudgePtr, MachinePointerInfo::getConstantPool(),
13174 MVT::f32, false, false, false, 4);
13175 // Extend everything to 80 bits to force it to be done on x87.
13176 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
13177 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
13178 }
13180 std::pair<SDValue,SDValue>
13181 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
13182 bool IsSigned, bool IsReplace) const {
13183 SDLoc DL(Op);
13185 EVT DstTy = Op.getValueType();
13187 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
13188 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
13189 DstTy = MVT::i64;
13190 }
13192 assert(DstTy.getSimpleVT() <= MVT::i64 &&
13193 DstTy.getSimpleVT() >= MVT::i16 &&
13194 "Unknown FP_TO_INT to lower!");
13196 // These are really Legal.
13197 if (DstTy == MVT::i32 &&
13198 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13199 return std::make_pair(SDValue(), SDValue());
13200 if (Subtarget->is64Bit() &&
13201 DstTy == MVT::i64 &&
13202 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13203 return std::make_pair(SDValue(), SDValue());
13205 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
13206 // stack slot, or into the FTOL runtime function.
13207 MachineFunction &MF = DAG.getMachineFunction();
13208 unsigned MemSize = DstTy.getSizeInBits()/8;
13209 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13210 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13212 unsigned Opc;
13213 if (!IsSigned && isIntegerTypeFTOL(DstTy))
13214 Opc = X86ISD::WIN_FTOL;
13215 else
13216 switch (DstTy.getSimpleVT().SimpleTy) {
13217 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
13218 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
13219 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
13220 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
13221 }
13223 SDValue Chain = DAG.getEntryNode();
13224 SDValue Value = Op.getOperand(0);
13225 EVT TheVT = Op.getOperand(0).getValueType();
13226 // FIXME This causes a redundant load/store if the SSE-class value is already
13227 // in memory, such as if it is on the callstack.
13228 if (isScalarFPTypeInSSEReg(TheVT)) {
13229 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
13230 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
13231 MachinePointerInfo::getFixedStack(SSFI),
13232 false, false, 0);
13233 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
13234 SDValue Ops[] = {
13235 Chain, StackSlot, DAG.getValueType(TheVT)
13236 };
13238 MachineMemOperand *MMO =
13239 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13240 MachineMemOperand::MOLoad, MemSize, MemSize);
13241 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
13242 Chain = Value.getValue(1);
13243 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13244 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13245 }
13247 MachineMemOperand *MMO =
13248 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13249 MachineMemOperand::MOStore, MemSize, MemSize);
13251 if (Opc != X86ISD::WIN_FTOL) {
13252 // Build the FP_TO_INT*_IN_MEM
13253 SDValue Ops[] = { Chain, Value, StackSlot };
13254 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
13255 Ops, DstTy, MMO);
13256 return std::make_pair(FIST, StackSlot);
13257 } else {
13258 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
13259 DAG.getVTList(MVT::Other, MVT::Glue),
13260 Chain, Value);
13261 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
13262 MVT::i32, ftol.getValue(1));
13263 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
13264 MVT::i32, eax.getValue(2));
13265 SDValue Ops[] = { eax, edx };
13266 SDValue pair = IsReplace
13267 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
13268 : DAG.getMergeValues(Ops, DL);
13269 return std::make_pair(pair, SDValue());
13270 }
13271 }
13273 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
13274 const X86Subtarget *Subtarget) {
13275 MVT VT = Op->getSimpleValueType(0);
13276 SDValue In = Op->getOperand(0);
13277 MVT InVT = In.getSimpleValueType();
13278 SDLoc dl(Op);
13280 // Optimize vectors in AVX mode:
13281 //
13282 // v8i16 -> v8i32
13283 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
13284 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
13285 // Concat upper and lower parts.
13286 //
13287 // v4i32 -> v4i64
13288 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
13289 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
13290 // Concat upper and lower parts.
13291 //
13293 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
13294 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
13295 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
13296 return SDValue();
13298 if (Subtarget->hasInt256())
13299 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
13301 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
13302 SDValue Undef = DAG.getUNDEF(InVT);
13303 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
13304 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13305 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13307 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
13308 VT.getVectorNumElements()/2);
13310 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
13311 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
13313 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13314 }
13316 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
13317 SelectionDAG &DAG) {
13318 MVT VT = Op->getSimpleValueType(0);
13319 SDValue In = Op->getOperand(0);
13320 MVT InVT = In.getSimpleValueType();
13321 SDLoc DL(Op);
13322 unsigned int NumElts = VT.getVectorNumElements();
13323 if (NumElts != 8 && NumElts != 16)
13324 return SDValue();
13326 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
13327 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
13329 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
13330 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13331 // Now we have only mask extension
13332 assert(InVT.getVectorElementType() == MVT::i1);
13333 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
13334 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
13335 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
13336 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13337 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
13338 MachinePointerInfo::getConstantPool(),
13339 false, false, false, Alignment);
13341 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
13342 if (VT.is512BitVector())
13343 return Brcst;
13344 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
13345 }
13347 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13348 SelectionDAG &DAG) {
13349 if (Subtarget->hasFp256()) {
13350 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
13351 if (Res.getNode())
13352 return Res;
13353 }
13355 return SDValue();
13356 }
13358 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13359 SelectionDAG &DAG) {
13360 SDLoc DL(Op);
13361 MVT VT = Op.getSimpleValueType();
13362 SDValue In = Op.getOperand(0);
13363 MVT SVT = In.getSimpleValueType();
13365 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
13366 return LowerZERO_EXTEND_AVX512(Op, DAG);
13368 if (Subtarget->hasFp256()) {
13369 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
13370 if (Res.getNode())
13371 return Res;
13372 }
13374 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
13375 VT.getVectorNumElements() != SVT.getVectorNumElements());
13376 return SDValue();
13377 }
13379 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
13380 SDLoc DL(Op);
13381 MVT VT = Op.getSimpleValueType();
13382 SDValue In = Op.getOperand(0);
13383 MVT InVT = In.getSimpleValueType();
13385 if (VT == MVT::i1) {
13386 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
13387 "Invalid scalar TRUNCATE operation");
13388 if (InVT.getSizeInBits() >= 32)
13389 return SDValue();
13390 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
13391 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
13392 }
13393 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
13394 "Invalid TRUNCATE operation");
13396 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
13397 if (VT.getVectorElementType().getSizeInBits() >=8)
13398 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
13400 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13401 unsigned NumElts = InVT.getVectorNumElements();
13402 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
13403 if (InVT.getSizeInBits() < 512) {
13404 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
13405 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
13406 InVT = ExtVT;
13407 }
13409 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
13410 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
13411 SDValue CP = DAG.getConstantPool(C, getPointerTy());
13412 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13413 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
13414 MachinePointerInfo::getConstantPool(),
13415 false, false, false, Alignment);
13416 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
13417 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
13418 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
13419 }
13421 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
13422 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
13423 if (Subtarget->hasInt256()) {
13424 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13425 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
13426 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
13427 ShufMask);
13428 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
13429 DAG.getIntPtrConstant(0));
13430 }
13432 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13433 DAG.getIntPtrConstant(0));
13434 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13435 DAG.getIntPtrConstant(2));
13436 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
13437 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
13438 static const int ShufMask[] = {0, 2, 4, 6};
13439 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
13440 }
13442 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
13443 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
13444 if (Subtarget->hasInt256()) {
13445 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
13447 SmallVector<SDValue,32> pshufbMask;
13448 for (unsigned i = 0; i < 2; ++i) {
13449 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
13450 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
13451 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
13452 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
13453 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
13454 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
13455 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
13456 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
13457 for (unsigned j = 0; j < 8; ++j)
13458 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
13459 }
13460 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
13461 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
13462 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
13464 static const int ShufMask[] = {0, 2, -1, -1};
13465 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
13466 &ShufMask[0]);
13467 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13468 DAG.getIntPtrConstant(0));
13469 return DAG.getNode(ISD::BITCAST, DL, VT, In);
13470 }
13472 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13473 DAG.getIntPtrConstant(0));
13475 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13476 DAG.getIntPtrConstant(4));
13478 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
13479 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
13481 // The PSHUFB mask:
13482 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13483 -1, -1, -1, -1, -1, -1, -1, -1};
13485 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
13486 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
13487 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
13489 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
13490 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
13492 // The MOVLHPS Mask:
13493 static const int ShufMask2[] = {0, 1, 4, 5};
13494 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
13495 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
13496 }
13498 // Handle truncation of V256 to V128 using shuffles.
13499 if (!VT.is128BitVector() || !InVT.is256BitVector())
13500 return SDValue();
13502 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
13504 unsigned NumElems = VT.getVectorNumElements();
13505 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
13507 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
13508 // Prepare truncation shuffle mask
13509 for (unsigned i = 0; i != NumElems; ++i)
13510 MaskVec[i] = i * 2;
13511 SDValue V = DAG.getVectorShuffle(NVT, DL,
13512 DAG.getNode(ISD::BITCAST, DL, NVT, In),
13513 DAG.getUNDEF(NVT), &MaskVec[0]);
13514 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
13515 DAG.getIntPtrConstant(0));
13516 }
13518 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
13519 SelectionDAG &DAG) const {
13520 assert(!Op.getSimpleValueType().isVector());
13522 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13523 /*IsSigned=*/ true, /*IsReplace=*/ false);
13524 SDValue FIST = Vals.first, StackSlot = Vals.second;
13525 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13526 if (!FIST.getNode()) return Op;
13528 if (StackSlot.getNode())
13529 // Load the result.
13530 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13531 FIST, StackSlot, MachinePointerInfo(),
13532 false, false, false, 0);
13534 // The node is the result.
13535 return FIST;
13536 }
13538 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
13539 SelectionDAG &DAG) const {
13540 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13541 /*IsSigned=*/ false, /*IsReplace=*/ false);
13542 SDValue FIST = Vals.first, StackSlot = Vals.second;
13543 assert(FIST.getNode() && "Unexpected failure");
13545 if (StackSlot.getNode())
13546 // Load the result.
13547 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13548 FIST, StackSlot, MachinePointerInfo(),
13549 false, false, false, 0);
13551 // The node is the result.
13552 return FIST;
13553 }
13555 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
13556 SDLoc DL(Op);
13557 MVT VT = Op.getSimpleValueType();
13558 SDValue In = Op.getOperand(0);
13559 MVT SVT = In.getSimpleValueType();
13561 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
13563 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
13564 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
13565 In, DAG.getUNDEF(SVT)));
13566 }
13568 // The only differences between FABS and FNEG are the mask and the logic op.
13569 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
13570 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
13571 "Wrong opcode for lowering FABS or FNEG.");
13573 bool IsFABS = (Op.getOpcode() == ISD::FABS);
13574 SDLoc dl(Op);
13575 MVT VT = Op.getSimpleValueType();
13576 // Assume scalar op for initialization; update for vector if needed.
13577 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
13578 // generate a 16-byte vector constant and logic op even for the scalar case.
13579 // Using a 16-byte mask allows folding the load of the mask with
13580 // the logic op, so it can save (~4 bytes) on code size.
13581 MVT EltVT = VT;
13582 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
13583 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
13584 // decide if we should generate a 16-byte constant mask when we only need 4 or
13585 // 8 bytes for the scalar case.
13586 if (VT.isVector()) {
13587 EltVT = VT.getVectorElementType();
13588 NumElts = VT.getVectorNumElements();
13589 }
13591 unsigned EltBits = EltVT.getSizeInBits();
13592 LLVMContext *Context = DAG.getContext();
13593 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
13594 APInt MaskElt =
13595 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
13596 Constant *C = ConstantInt::get(*Context, MaskElt);
13597 C = ConstantVector::getSplat(NumElts, C);
13598 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13599 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
13600 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13601 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
13602 MachinePointerInfo::getConstantPool(),
13603 false, false, false, Alignment);
13605 if (VT.isVector()) {
13606 // For a vector, cast operands to a vector type, perform the logic op,
13607 // and cast the result back to the original value type.
13608 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
13609 SDValue Op0Casted = DAG.getNode(ISD::BITCAST, dl, VecVT, Op.getOperand(0));
13610 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
13611 unsigned LogicOp = IsFABS ? ISD::AND : ISD::XOR;
13612 return DAG.getNode(ISD::BITCAST, dl, VT,
13613 DAG.getNode(LogicOp, dl, VecVT, Op0Casted, MaskCasted));
13614 }
13615 // If not vector, then scalar.
13616 unsigned LogicOp = IsFABS ? X86ISD::FAND : X86ISD::FXOR;
13617 return DAG.getNode(LogicOp, dl, VT, Op.getOperand(0), Mask);
13618 }
13620 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
13621 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13622 LLVMContext *Context = DAG.getContext();
13623 SDValue Op0 = Op.getOperand(0);
13624 SDValue Op1 = Op.getOperand(1);
13625 SDLoc dl(Op);
13626 MVT VT = Op.getSimpleValueType();
13627 MVT SrcVT = Op1.getSimpleValueType();
13629 // If second operand is smaller, extend it first.
13630 if (SrcVT.bitsLT(VT)) {
13631 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
13632 SrcVT = VT;
13633 }
13634 // And if it is bigger, shrink it first.
13635 if (SrcVT.bitsGT(VT)) {
13636 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
13637 SrcVT = VT;
13638 }
13640 // At this point the operands and the result should have the same
13641 // type, and that won't be f80 since that is not custom lowered.
13643 // First get the sign bit of second operand.
13644 SmallVector<Constant*,4> CV;
13645 if (SrcVT == MVT::f64) {
13646 const fltSemantics &Sem = APFloat::IEEEdouble;
13647 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
13648 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
13649 } else {
13650 const fltSemantics &Sem = APFloat::IEEEsingle;
13651 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
13652 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13653 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13654 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13655 }
13656 Constant *C = ConstantVector::get(CV);
13657 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
13658 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
13659 MachinePointerInfo::getConstantPool(),
13660 false, false, false, 16);
13661 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
13663 // Shift sign bit right or left if the two operands have different types.
13664 if (SrcVT.bitsGT(VT)) {
13665 // Op0 is MVT::f32, Op1 is MVT::f64.
13666 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
13667 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
13668 DAG.getConstant(32, MVT::i32));
13669 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
13670 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
13671 DAG.getIntPtrConstant(0));
13672 }
13674 // Clear first operand sign bit.
13675 CV.clear();
13676 if (VT == MVT::f64) {
13677 const fltSemantics &Sem = APFloat::IEEEdouble;
13678 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
13679 APInt(64, ~(1ULL << 63)))));
13680 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
13681 } else {
13682 const fltSemantics &Sem = APFloat::IEEEsingle;
13683 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
13684 APInt(32, ~(1U << 31)))));
13685 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13686 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13687 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13688 }
13689 C = ConstantVector::get(CV);
13690 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
13691 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
13692 MachinePointerInfo::getConstantPool(),
13693 false, false, false, 16);
13694 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
13696 // Or the value with the sign bit.
13697 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
13698 }
13700 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
13701 SDValue N0 = Op.getOperand(0);
13702 SDLoc dl(Op);
13703 MVT VT = Op.getSimpleValueType();
13705 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
13706 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
13707 DAG.getConstant(1, VT));
13708 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
13709 }
13711 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
13712 //
13713 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
13714 SelectionDAG &DAG) {
13715 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
13717 if (!Subtarget->hasSSE41())
13718 return SDValue();
13720 if (!Op->hasOneUse())
13721 return SDValue();
13723 SDNode *N = Op.getNode();
13724 SDLoc DL(N);
13726 SmallVector<SDValue, 8> Opnds;
13727 DenseMap<SDValue, unsigned> VecInMap;
13728 SmallVector<SDValue, 8> VecIns;
13729 EVT VT = MVT::Other;
13731 // Recognize a special case where a vector is casted into wide integer to
13732 // test all 0s.
13733 Opnds.push_back(N->getOperand(0));
13734 Opnds.push_back(N->getOperand(1));
13736 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
13737 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
13738 // BFS traverse all OR'd operands.
13739 if (I->getOpcode() == ISD::OR) {
13740 Opnds.push_back(I->getOperand(0));
13741 Opnds.push_back(I->getOperand(1));
13742 // Re-evaluate the number of nodes to be traversed.
13743 e += 2; // 2 more nodes (LHS and RHS) are pushed.
13744 continue;
13745 }
13747 // Quit if a non-EXTRACT_VECTOR_ELT
13748 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13749 return SDValue();
13751 // Quit if without a constant index.
13752 SDValue Idx = I->getOperand(1);
13753 if (!isa<ConstantSDNode>(Idx))
13754 return SDValue();
13756 SDValue ExtractedFromVec = I->getOperand(0);
13757 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
13758 if (M == VecInMap.end()) {
13759 VT = ExtractedFromVec.getValueType();
13760 // Quit if not 128/256-bit vector.
13761 if (!VT.is128BitVector() && !VT.is256BitVector())
13762 return SDValue();
13763 // Quit if not the same type.
13764 if (VecInMap.begin() != VecInMap.end() &&
13765 VT != VecInMap.begin()->first.getValueType())
13766 return SDValue();
13767 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
13768 VecIns.push_back(ExtractedFromVec);
13769 }
13770 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
13771 }
13773 assert((VT.is128BitVector() || VT.is256BitVector()) &&
13774 "Not extracted from 128-/256-bit vector.");
13776 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
13778 for (DenseMap<SDValue, unsigned>::const_iterator
13779 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
13780 // Quit if not all elements are used.
13781 if (I->second != FullMask)
13782 return SDValue();
13783 }
13785 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
13787 // Cast all vectors into TestVT for PTEST.
13788 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
13789 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
13791 // If more than one full vectors are evaluated, OR them first before PTEST.
13792 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
13793 // Each iteration will OR 2 nodes and append the result until there is only
13794 // 1 node left, i.e. the final OR'd value of all vectors.
13795 SDValue LHS = VecIns[Slot];
13796 SDValue RHS = VecIns[Slot + 1];
13797 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
13798 }
13800 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
13801 VecIns.back(), VecIns.back());
13802 }
13804 /// \brief return true if \c Op has a use that doesn't just read flags.
13805 static bool hasNonFlagsUse(SDValue Op) {
13806 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
13807 ++UI) {
13808 SDNode *User = *UI;
13809 unsigned UOpNo = UI.getOperandNo();
13810 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
13811 // Look pass truncate.
13812 UOpNo = User->use_begin().getOperandNo();
13813 User = *User->use_begin();
13814 }
13816 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
13817 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
13818 return true;
13819 }
13820 return false;
13821 }
13823 /// Emit nodes that will be selected as "test Op0,Op0", or something
13824 /// equivalent.
13825 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
13826 SelectionDAG &DAG) const {
13827 if (Op.getValueType() == MVT::i1)
13828 // KORTEST instruction should be selected
13829 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13830 DAG.getConstant(0, Op.getValueType()));
13832 // CF and OF aren't always set the way we want. Determine which
13833 // of these we need.
13834 bool NeedCF = false;
13835 bool NeedOF = false;
13836 switch (X86CC) {
13837 default: break;
13838 case X86::COND_A: case X86::COND_AE:
13839 case X86::COND_B: case X86::COND_BE:
13840 NeedCF = true;
13841 break;
13842 case X86::COND_G: case X86::COND_GE:
13843 case X86::COND_L: case X86::COND_LE:
13844 case X86::COND_O: case X86::COND_NO: {
13845 // Check if we really need to set the
13846 // Overflow flag. If NoSignedWrap is present
13847 // that is not actually needed.
13848 switch (Op->getOpcode()) {
13849 case ISD::ADD:
13850 case ISD::SUB:
13851 case ISD::MUL:
13852 case ISD::SHL: {
13853 const BinaryWithFlagsSDNode *BinNode =
13854 cast<BinaryWithFlagsSDNode>(Op.getNode());
13855 if (BinNode->hasNoSignedWrap())
13856 break;
13857 }
13858 default:
13859 NeedOF = true;
13860 break;
13861 }
13862 break;
13863 }
13864 }
13865 // See if we can use the EFLAGS value from the operand instead of
13866 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
13867 // we prove that the arithmetic won't overflow, we can't use OF or CF.
13868 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
13869 // Emit a CMP with 0, which is the TEST pattern.
13870 //if (Op.getValueType() == MVT::i1)
13871 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
13872 // DAG.getConstant(0, MVT::i1));
13873 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13874 DAG.getConstant(0, Op.getValueType()));
13875 }
13876 unsigned Opcode = 0;
13877 unsigned NumOperands = 0;
13879 // Truncate operations may prevent the merge of the SETCC instruction
13880 // and the arithmetic instruction before it. Attempt to truncate the operands
13881 // of the arithmetic instruction and use a reduced bit-width instruction.
13882 bool NeedTruncation = false;
13883 SDValue ArithOp = Op;
13884 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
13885 SDValue Arith = Op->getOperand(0);
13886 // Both the trunc and the arithmetic op need to have one user each.
13887 if (Arith->hasOneUse())
13888 switch (Arith.getOpcode()) {
13889 default: break;
13890 case ISD::ADD:
13891 case ISD::SUB:
13892 case ISD::AND:
13893 case ISD::OR:
13894 case ISD::XOR: {
13895 NeedTruncation = true;
13896 ArithOp = Arith;
13897 }
13898 }
13899 }
13901 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
13902 // which may be the result of a CAST. We use the variable 'Op', which is the
13903 // non-casted variable when we check for possible users.
13904 switch (ArithOp.getOpcode()) {
13905 case ISD::ADD:
13906 // Due to an isel shortcoming, be conservative if this add is likely to be
13907 // selected as part of a load-modify-store instruction. When the root node
13908 // in a match is a store, isel doesn't know how to remap non-chain non-flag
13909 // uses of other nodes in the match, such as the ADD in this case. This
13910 // leads to the ADD being left around and reselected, with the result being
13911 // two adds in the output. Alas, even if none our users are stores, that
13912 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
13913 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
13914 // climbing the DAG back to the root, and it doesn't seem to be worth the
13915 // effort.
13916 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13917 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13918 if (UI->getOpcode() != ISD::CopyToReg &&
13919 UI->getOpcode() != ISD::SETCC &&
13920 UI->getOpcode() != ISD::STORE)
13921 goto default_case;
13923 if (ConstantSDNode *C =
13924 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
13925 // An add of one will be selected as an INC.
13926 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
13927 Opcode = X86ISD::INC;
13928 NumOperands = 1;
13929 break;
13930 }
13932 // An add of negative one (subtract of one) will be selected as a DEC.
13933 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
13934 Opcode = X86ISD::DEC;
13935 NumOperands = 1;
13936 break;
13937 }
13938 }
13940 // Otherwise use a regular EFLAGS-setting add.
13941 Opcode = X86ISD::ADD;
13942 NumOperands = 2;
13943 break;
13944 case ISD::SHL:
13945 case ISD::SRL:
13946 // If we have a constant logical shift that's only used in a comparison
13947 // against zero turn it into an equivalent AND. This allows turning it into
13948 // a TEST instruction later.
13949 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
13950 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
13951 EVT VT = Op.getValueType();
13952 unsigned BitWidth = VT.getSizeInBits();
13953 unsigned ShAmt = Op->getConstantOperandVal(1);
13954 if (ShAmt >= BitWidth) // Avoid undefined shifts.
13955 break;
13956 APInt Mask = ArithOp.getOpcode() == ISD::SRL
13957 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
13958 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
13959 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
13960 break;
13961 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
13962 DAG.getConstant(Mask, VT));
13963 DAG.ReplaceAllUsesWith(Op, New);
13964 Op = New;
13965 }
13966 break;
13968 case ISD::AND:
13969 // If the primary and result isn't used, don't bother using X86ISD::AND,
13970 // because a TEST instruction will be better.
13971 if (!hasNonFlagsUse(Op))
13972 break;
13973 // FALL THROUGH
13974 case ISD::SUB:
13975 case ISD::OR:
13976 case ISD::XOR:
13977 // Due to the ISEL shortcoming noted above, be conservative if this op is
13978 // likely to be selected as part of a load-modify-store instruction.
13979 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13980 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13981 if (UI->getOpcode() == ISD::STORE)
13982 goto default_case;
13984 // Otherwise use a regular EFLAGS-setting instruction.
13985 switch (ArithOp.getOpcode()) {
13986 default: llvm_unreachable("unexpected operator!");
13987 case ISD::SUB: Opcode = X86ISD::SUB; break;
13988 case ISD::XOR: Opcode = X86ISD::XOR; break;
13989 case ISD::AND: Opcode = X86ISD::AND; break;
13990 case ISD::OR: {
13991 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
13992 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
13993 if (EFLAGS.getNode())
13994 return EFLAGS;
13995 }
13996 Opcode = X86ISD::OR;
13997 break;
13998 }
13999 }
14001 NumOperands = 2;
14002 break;
14003 case X86ISD::ADD:
14004 case X86ISD::SUB:
14005 case X86ISD::INC:
14006 case X86ISD::DEC:
14007 case X86ISD::OR:
14008 case X86ISD::XOR:
14009 case X86ISD::AND:
14010 return SDValue(Op.getNode(), 1);
14011 default:
14012 default_case:
14013 break;
14014 }
14016 // If we found that truncation is beneficial, perform the truncation and
14017 // update 'Op'.
14018 if (NeedTruncation) {
14019 EVT VT = Op.getValueType();
14020 SDValue WideVal = Op->getOperand(0);
14021 EVT WideVT = WideVal.getValueType();
14022 unsigned ConvertedOp = 0;
14023 // Use a target machine opcode to prevent further DAGCombine
14024 // optimizations that may separate the arithmetic operations
14025 // from the setcc node.
14026 switch (WideVal.getOpcode()) {
14027 default: break;
14028 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
14029 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
14030 case ISD::AND: ConvertedOp = X86ISD::AND; break;
14031 case ISD::OR: ConvertedOp = X86ISD::OR; break;
14032 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
14033 }
14035 if (ConvertedOp) {
14036 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14037 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
14038 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
14039 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
14040 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
14041 }
14042 }
14043 }
14045 if (Opcode == 0)
14046 // Emit a CMP with 0, which is the TEST pattern.
14047 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14048 DAG.getConstant(0, Op.getValueType()));
14050 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14051 SmallVector<SDValue, 4> Ops;
14052 for (unsigned i = 0; i != NumOperands; ++i)
14053 Ops.push_back(Op.getOperand(i));
14055 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
14056 DAG.ReplaceAllUsesWith(Op, New);
14057 return SDValue(New.getNode(), 1);
14058 }
14060 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
14061 /// equivalent.
14062 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
14063 SDLoc dl, SelectionDAG &DAG) const {
14064 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
14065 if (C->getAPIntValue() == 0)
14066 return EmitTest(Op0, X86CC, dl, DAG);
14068 if (Op0.getValueType() == MVT::i1)
14069 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
14070 }
14072 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
14073 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
14074 // Do the comparison at i32 if it's smaller, besides the Atom case.
14075 // This avoids subregister aliasing issues. Keep the smaller reference
14076 // if we're optimizing for size, however, as that'll allow better folding
14077 // of memory operations.
14078 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
14079 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
14080 AttributeSet::FunctionIndex, Attribute::MinSize) &&
14081 !Subtarget->isAtom()) {
14082 unsigned ExtendOp =
14083 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
14084 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
14085 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
14086 }
14087 // Use SUB instead of CMP to enable CSE between SUB and CMP.
14088 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
14089 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
14090 Op0, Op1);
14091 return SDValue(Sub.getNode(), 1);
14092 }
14093 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
14094 }
14096 /// Convert a comparison if required by the subtarget.
14097 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
14098 SelectionDAG &DAG) const {
14099 // If the subtarget does not support the FUCOMI instruction, floating-point
14100 // comparisons have to be converted.
14101 if (Subtarget->hasCMov() ||
14102 Cmp.getOpcode() != X86ISD::CMP ||
14103 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
14104 !Cmp.getOperand(1).getValueType().isFloatingPoint())
14105 return Cmp;
14107 // The instruction selector will select an FUCOM instruction instead of
14108 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
14109 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
14110 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
14111 SDLoc dl(Cmp);
14112 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
14113 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
14114 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
14115 DAG.getConstant(8, MVT::i8));
14116 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
14117 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
14118 }
14120 static bool isAllOnes(SDValue V) {
14121 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
14122 return C && C->isAllOnesValue();
14123 }
14125 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
14126 /// if it's possible.
14127 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
14128 SDLoc dl, SelectionDAG &DAG) const {
14129 SDValue Op0 = And.getOperand(0);
14130 SDValue Op1 = And.getOperand(1);
14131 if (Op0.getOpcode() == ISD::TRUNCATE)
14132 Op0 = Op0.getOperand(0);
14133 if (Op1.getOpcode() == ISD::TRUNCATE)
14134 Op1 = Op1.getOperand(0);
14136 SDValue LHS, RHS;
14137 if (Op1.getOpcode() == ISD::SHL)
14138 std::swap(Op0, Op1);
14139 if (Op0.getOpcode() == ISD::SHL) {
14140 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
14141 if (And00C->getZExtValue() == 1) {
14142 // If we looked past a truncate, check that it's only truncating away
14143 // known zeros.
14144 unsigned BitWidth = Op0.getValueSizeInBits();
14145 unsigned AndBitWidth = And.getValueSizeInBits();
14146 if (BitWidth > AndBitWidth) {
14147 APInt Zeros, Ones;
14148 DAG.computeKnownBits(Op0, Zeros, Ones);
14149 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
14150 return SDValue();
14151 }
14152 LHS = Op1;
14153 RHS = Op0.getOperand(1);
14154 }
14155 } else if (Op1.getOpcode() == ISD::Constant) {
14156 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
14157 uint64_t AndRHSVal = AndRHS->getZExtValue();
14158 SDValue AndLHS = Op0;
14160 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
14161 LHS = AndLHS.getOperand(0);
14162 RHS = AndLHS.getOperand(1);
14163 }
14165 // Use BT if the immediate can't be encoded in a TEST instruction.
14166 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
14167 LHS = AndLHS;
14168 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
14169 }
14170 }
14172 if (LHS.getNode()) {
14173 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
14174 // instruction. Since the shift amount is in-range-or-undefined, we know
14175 // that doing a bittest on the i32 value is ok. We extend to i32 because
14176 // the encoding for the i16 version is larger than the i32 version.
14177 // Also promote i16 to i32 for performance / code size reason.
14178 if (LHS.getValueType() == MVT::i8 ||
14179 LHS.getValueType() == MVT::i16)
14180 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
14182 // If the operand types disagree, extend the shift amount to match. Since
14183 // BT ignores high bits (like shifts) we can use anyextend.
14184 if (LHS.getValueType() != RHS.getValueType())
14185 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
14187 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
14188 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
14189 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14190 DAG.getConstant(Cond, MVT::i8), BT);
14191 }
14193 return SDValue();
14194 }
14196 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
14197 /// mask CMPs.
14198 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
14199 SDValue &Op1) {
14200 unsigned SSECC;
14201 bool Swap = false;
14203 // SSE Condition code mapping:
14204 // 0 - EQ
14205 // 1 - LT
14206 // 2 - LE
14207 // 3 - UNORD
14208 // 4 - NEQ
14209 // 5 - NLT
14210 // 6 - NLE
14211 // 7 - ORD
14212 switch (SetCCOpcode) {
14213 default: llvm_unreachable("Unexpected SETCC condition");
14214 case ISD::SETOEQ:
14215 case ISD::SETEQ: SSECC = 0; break;
14216 case ISD::SETOGT:
14217 case ISD::SETGT: Swap = true; // Fallthrough
14218 case ISD::SETLT:
14219 case ISD::SETOLT: SSECC = 1; break;
14220 case ISD::SETOGE:
14221 case ISD::SETGE: Swap = true; // Fallthrough
14222 case ISD::SETLE:
14223 case ISD::SETOLE: SSECC = 2; break;
14224 case ISD::SETUO: SSECC = 3; break;
14225 case ISD::SETUNE:
14226 case ISD::SETNE: SSECC = 4; break;
14227 case ISD::SETULE: Swap = true; // Fallthrough
14228 case ISD::SETUGE: SSECC = 5; break;
14229 case ISD::SETULT: Swap = true; // Fallthrough
14230 case ISD::SETUGT: SSECC = 6; break;
14231 case ISD::SETO: SSECC = 7; break;
14232 case ISD::SETUEQ:
14233 case ISD::SETONE: SSECC = 8; break;
14234 }
14235 if (Swap)
14236 std::swap(Op0, Op1);
14238 return SSECC;
14239 }
14241 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
14242 // ones, and then concatenate the result back.
14243 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
14244 MVT VT = Op.getSimpleValueType();
14246 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
14247 "Unsupported value type for operation");
14249 unsigned NumElems = VT.getVectorNumElements();
14250 SDLoc dl(Op);
14251 SDValue CC = Op.getOperand(2);
14253 // Extract the LHS vectors
14254 SDValue LHS = Op.getOperand(0);
14255 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
14256 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
14258 // Extract the RHS vectors
14259 SDValue RHS = Op.getOperand(1);
14260 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
14261 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
14263 // Issue the operation on the smaller types and concatenate the result back
14264 MVT EltVT = VT.getVectorElementType();
14265 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
14266 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
14267 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
14268 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
14269 }
14271 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
14272 const X86Subtarget *Subtarget) {
14273 SDValue Op0 = Op.getOperand(0);
14274 SDValue Op1 = Op.getOperand(1);
14275 SDValue CC = Op.getOperand(2);
14276 MVT VT = Op.getSimpleValueType();
14277 SDLoc dl(Op);
14279 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
14280 Op.getValueType().getScalarType() == MVT::i1 &&
14281 "Cannot set masked compare for this operation");
14283 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14284 unsigned Opc = 0;
14285 bool Unsigned = false;
14286 bool Swap = false;
14287 unsigned SSECC;
14288 switch (SetCCOpcode) {
14289 default: llvm_unreachable("Unexpected SETCC condition");
14290 case ISD::SETNE: SSECC = 4; break;
14291 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
14292 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
14293 case ISD::SETLT: Swap = true; //fall-through
14294 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
14295 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
14296 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
14297 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
14298 case ISD::SETULE: Unsigned = true; //fall-through
14299 case ISD::SETLE: SSECC = 2; break;
14300 }
14302 if (Swap)
14303 std::swap(Op0, Op1);
14304 if (Opc)
14305 return DAG.getNode(Opc, dl, VT, Op0, Op1);
14306 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
14307 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14308 DAG.getConstant(SSECC, MVT::i8));
14309 }
14311 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
14312 /// operand \p Op1. If non-trivial (for example because it's not constant)
14313 /// return an empty value.
14314 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
14315 {
14316 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
14317 if (!BV)
14318 return SDValue();
14320 MVT VT = Op1.getSimpleValueType();
14321 MVT EVT = VT.getVectorElementType();
14322 unsigned n = VT.getVectorNumElements();
14323 SmallVector<SDValue, 8> ULTOp1;
14325 for (unsigned i = 0; i < n; ++i) {
14326 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
14327 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
14328 return SDValue();
14330 // Avoid underflow.
14331 APInt Val = Elt->getAPIntValue();
14332 if (Val == 0)
14333 return SDValue();
14335 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
14336 }
14338 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
14339 }
14341 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
14342 SelectionDAG &DAG) {
14343 SDValue Op0 = Op.getOperand(0);
14344 SDValue Op1 = Op.getOperand(1);
14345 SDValue CC = Op.getOperand(2);
14346 MVT VT = Op.getSimpleValueType();
14347 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14348 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
14349 SDLoc dl(Op);
14351 if (isFP) {
14352 #ifndef NDEBUG
14353 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
14354 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
14355 #endif
14357 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
14358 unsigned Opc = X86ISD::CMPP;
14359 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
14360 assert(VT.getVectorNumElements() <= 16);
14361 Opc = X86ISD::CMPM;
14362 }
14363 // In the two special cases we can't handle, emit two comparisons.
14364 if (SSECC == 8) {
14365 unsigned CC0, CC1;
14366 unsigned CombineOpc;
14367 if (SetCCOpcode == ISD::SETUEQ) {
14368 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
14369 } else {
14370 assert(SetCCOpcode == ISD::SETONE);
14371 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
14372 }
14374 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14375 DAG.getConstant(CC0, MVT::i8));
14376 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14377 DAG.getConstant(CC1, MVT::i8));
14378 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
14379 }
14380 // Handle all other FP comparisons here.
14381 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14382 DAG.getConstant(SSECC, MVT::i8));
14383 }
14385 // Break 256-bit integer vector compare into smaller ones.
14386 if (VT.is256BitVector() && !Subtarget->hasInt256())
14387 return Lower256IntVSETCC(Op, DAG);
14389 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
14390 EVT OpVT = Op1.getValueType();
14391 if (Subtarget->hasAVX512()) {
14392 if (Op1.getValueType().is512BitVector() ||
14393 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
14394 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
14395 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
14397 // In AVX-512 architecture setcc returns mask with i1 elements,
14398 // But there is no compare instruction for i8 and i16 elements in KNL.
14399 // We are not talking about 512-bit operands in this case, these
14400 // types are illegal.
14401 if (MaskResult &&
14402 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
14403 OpVT.getVectorElementType().getSizeInBits() >= 8))
14404 return DAG.getNode(ISD::TRUNCATE, dl, VT,
14405 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
14406 }
14408 // We are handling one of the integer comparisons here. Since SSE only has
14409 // GT and EQ comparisons for integer, swapping operands and multiple
14410 // operations may be required for some comparisons.
14411 unsigned Opc;
14412 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
14413 bool Subus = false;
14415 switch (SetCCOpcode) {
14416 default: llvm_unreachable("Unexpected SETCC condition");
14417 case ISD::SETNE: Invert = true;
14418 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
14419 case ISD::SETLT: Swap = true;
14420 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
14421 case ISD::SETGE: Swap = true;
14422 case ISD::SETLE: Opc = X86ISD::PCMPGT;
14423 Invert = true; break;
14424 case ISD::SETULT: Swap = true;
14425 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
14426 FlipSigns = true; break;
14427 case ISD::SETUGE: Swap = true;
14428 case ISD::SETULE: Opc = X86ISD::PCMPGT;
14429 FlipSigns = true; Invert = true; break;
14430 }
14432 // Special case: Use min/max operations for SETULE/SETUGE
14433 MVT VET = VT.getVectorElementType();
14434 bool hasMinMax =
14435 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
14436 || (Subtarget->hasSSE2() && (VET == MVT::i8));
14438 if (hasMinMax) {
14439 switch (SetCCOpcode) {
14440 default: break;
14441 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
14442 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
14443 }
14445 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
14446 }
14448 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
14449 if (!MinMax && hasSubus) {
14450 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
14451 // Op0 u<= Op1:
14452 // t = psubus Op0, Op1
14453 // pcmpeq t, <0..0>
14454 switch (SetCCOpcode) {
14455 default: break;
14456 case ISD::SETULT: {
14457 // If the comparison is against a constant we can turn this into a
14458 // setule. With psubus, setule does not require a swap. This is
14459 // beneficial because the constant in the register is no longer
14460 // destructed as the destination so it can be hoisted out of a loop.
14461 // Only do this pre-AVX since vpcmp* is no longer destructive.
14462 if (Subtarget->hasAVX())
14463 break;
14464 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
14465 if (ULEOp1.getNode()) {
14466 Op1 = ULEOp1;
14467 Subus = true; Invert = false; Swap = false;
14468 }
14469 break;
14470 }
14471 // Psubus is better than flip-sign because it requires no inversion.
14472 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
14473 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
14474 }
14476 if (Subus) {
14477 Opc = X86ISD::SUBUS;
14478 FlipSigns = false;
14479 }
14480 }
14482 if (Swap)
14483 std::swap(Op0, Op1);
14485 // Check that the operation in question is available (most are plain SSE2,
14486 // but PCMPGTQ and PCMPEQQ have different requirements).
14487 if (VT == MVT::v2i64) {
14488 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
14489 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
14491 // First cast everything to the right type.
14492 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
14493 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
14495 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14496 // bits of the inputs before performing those operations. The lower
14497 // compare is always unsigned.
14498 SDValue SB;
14499 if (FlipSigns) {
14500 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
14501 } else {
14502 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
14503 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
14504 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
14505 Sign, Zero, Sign, Zero);
14506 }
14507 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
14508 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
14510 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
14511 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
14512 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
14514 // Create masks for only the low parts/high parts of the 64 bit integers.
14515 static const int MaskHi[] = { 1, 1, 3, 3 };
14516 static const int MaskLo[] = { 0, 0, 2, 2 };
14517 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
14518 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
14519 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
14521 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
14522 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
14524 if (Invert)
14525 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14527 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
14528 }
14530 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
14531 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
14532 // pcmpeqd + pshufd + pand.
14533 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
14535 // First cast everything to the right type.
14536 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
14537 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
14539 // Do the compare.
14540 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
14542 // Make sure the lower and upper halves are both all-ones.
14543 static const int Mask[] = { 1, 0, 3, 2 };
14544 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
14545 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
14547 if (Invert)
14548 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14550 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
14551 }
14552 }
14554 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14555 // bits of the inputs before performing those operations.
14556 if (FlipSigns) {
14557 EVT EltVT = VT.getVectorElementType();
14558 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
14559 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
14560 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
14561 }
14563 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
14565 // If the logical-not of the result is required, perform that now.
14566 if (Invert)
14567 Result = DAG.getNOT(dl, Result, VT);
14569 if (MinMax)
14570 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
14572 if (Subus)
14573 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
14574 getZeroVector(VT, Subtarget, DAG, dl));
14576 return Result;
14577 }
14579 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
14581 MVT VT = Op.getSimpleValueType();
14583 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
14585 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
14586 && "SetCC type must be 8-bit or 1-bit integer");
14587 SDValue Op0 = Op.getOperand(0);
14588 SDValue Op1 = Op.getOperand(1);
14589 SDLoc dl(Op);
14590 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
14592 // Optimize to BT if possible.
14593 // Lower (X & (1 << N)) == 0 to BT(X, N).
14594 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
14595 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
14596 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
14597 Op1.getOpcode() == ISD::Constant &&
14598 cast<ConstantSDNode>(Op1)->isNullValue() &&
14599 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14600 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
14601 if (NewSetCC.getNode())
14602 return NewSetCC;
14603 }
14605 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
14606 // these.
14607 if (Op1.getOpcode() == ISD::Constant &&
14608 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
14609 cast<ConstantSDNode>(Op1)->isNullValue()) &&
14610 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14612 // If the input is a setcc, then reuse the input setcc or use a new one with
14613 // the inverted condition.
14614 if (Op0.getOpcode() == X86ISD::SETCC) {
14615 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
14616 bool Invert = (CC == ISD::SETNE) ^
14617 cast<ConstantSDNode>(Op1)->isNullValue();
14618 if (!Invert)
14619 return Op0;
14621 CCode = X86::GetOppositeBranchCondition(CCode);
14622 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14623 DAG.getConstant(CCode, MVT::i8),
14624 Op0.getOperand(1));
14625 if (VT == MVT::i1)
14626 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14627 return SetCC;
14628 }
14629 }
14630 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
14631 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
14632 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14634 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
14635 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
14636 }
14638 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
14639 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
14640 if (X86CC == X86::COND_INVALID)
14641 return SDValue();
14643 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
14644 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
14645 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14646 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
14647 if (VT == MVT::i1)
14648 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14649 return SetCC;
14650 }
14652 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
14653 static bool isX86LogicalCmp(SDValue Op) {
14654 unsigned Opc = Op.getNode()->getOpcode();
14655 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
14656 Opc == X86ISD::SAHF)
14657 return true;
14658 if (Op.getResNo() == 1 &&
14659 (Opc == X86ISD::ADD ||
14660 Opc == X86ISD::SUB ||
14661 Opc == X86ISD::ADC ||
14662 Opc == X86ISD::SBB ||
14663 Opc == X86ISD::SMUL ||
14664 Opc == X86ISD::UMUL ||
14665 Opc == X86ISD::INC ||
14666 Opc == X86ISD::DEC ||
14667 Opc == X86ISD::OR ||
14668 Opc == X86ISD::XOR ||
14669 Opc == X86ISD::AND))
14670 return true;
14672 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
14673 return true;
14675 return false;
14676 }
14678 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
14679 if (V.getOpcode() != ISD::TRUNCATE)
14680 return false;
14682 SDValue VOp0 = V.getOperand(0);
14683 unsigned InBits = VOp0.getValueSizeInBits();
14684 unsigned Bits = V.getValueSizeInBits();
14685 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
14686 }
14688 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
14689 bool addTest = true;
14690 SDValue Cond = Op.getOperand(0);
14691 SDValue Op1 = Op.getOperand(1);
14692 SDValue Op2 = Op.getOperand(2);
14693 SDLoc DL(Op);
14694 EVT VT = Op1.getValueType();
14695 SDValue CC;
14697 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
14698 // are available. Otherwise fp cmovs get lowered into a less efficient branch
14699 // sequence later on.
14700 if (Cond.getOpcode() == ISD::SETCC &&
14701 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
14702 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
14703 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
14704 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
14705 int SSECC = translateX86FSETCC(
14706 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
14708 if (SSECC != 8) {
14709 if (Subtarget->hasAVX512()) {
14710 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
14711 DAG.getConstant(SSECC, MVT::i8));
14712 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
14713 }
14714 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
14715 DAG.getConstant(SSECC, MVT::i8));
14716 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
14717 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
14718 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
14719 }
14720 }
14722 if (Cond.getOpcode() == ISD::SETCC) {
14723 SDValue NewCond = LowerSETCC(Cond, DAG);
14724 if (NewCond.getNode())
14725 Cond = NewCond;
14726 }
14728 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
14729 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
14730 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
14731 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
14732 if (Cond.getOpcode() == X86ISD::SETCC &&
14733 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
14734 isZero(Cond.getOperand(1).getOperand(1))) {
14735 SDValue Cmp = Cond.getOperand(1);
14737 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
14739 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
14740 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
14741 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
14743 SDValue CmpOp0 = Cmp.getOperand(0);
14744 // Apply further optimizations for special cases
14745 // (select (x != 0), -1, 0) -> neg & sbb
14746 // (select (x == 0), 0, -1) -> neg & sbb
14747 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
14748 if (YC->isNullValue() &&
14749 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
14750 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
14751 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
14752 DAG.getConstant(0, CmpOp0.getValueType()),
14753 CmpOp0);
14754 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14755 DAG.getConstant(X86::COND_B, MVT::i8),
14756 SDValue(Neg.getNode(), 1));
14757 return Res;
14758 }
14760 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
14761 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
14762 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14764 SDValue Res = // Res = 0 or -1.
14765 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14766 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
14768 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
14769 Res = DAG.getNOT(DL, Res, Res.getValueType());
14771 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
14772 if (!N2C || !N2C->isNullValue())
14773 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
14774 return Res;
14775 }
14776 }
14778 // Look past (and (setcc_carry (cmp ...)), 1).
14779 if (Cond.getOpcode() == ISD::AND &&
14780 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14781 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14782 if (C && C->getAPIntValue() == 1)
14783 Cond = Cond.getOperand(0);
14784 }
14786 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14787 // setting operand in place of the X86ISD::SETCC.
14788 unsigned CondOpcode = Cond.getOpcode();
14789 if (CondOpcode == X86ISD::SETCC ||
14790 CondOpcode == X86ISD::SETCC_CARRY) {
14791 CC = Cond.getOperand(0);
14793 SDValue Cmp = Cond.getOperand(1);
14794 unsigned Opc = Cmp.getOpcode();
14795 MVT VT = Op.getSimpleValueType();
14797 bool IllegalFPCMov = false;
14798 if (VT.isFloatingPoint() && !VT.isVector() &&
14799 !isScalarFPTypeInSSEReg(VT)) // FPStack?
14800 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
14802 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
14803 Opc == X86ISD::BT) { // FIXME
14804 Cond = Cmp;
14805 addTest = false;
14806 }
14807 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14808 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14809 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14810 Cond.getOperand(0).getValueType() != MVT::i8)) {
14811 SDValue LHS = Cond.getOperand(0);
14812 SDValue RHS = Cond.getOperand(1);
14813 unsigned X86Opcode;
14814 unsigned X86Cond;
14815 SDVTList VTs;
14816 switch (CondOpcode) {
14817 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14818 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14819 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14820 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14821 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14822 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14823 default: llvm_unreachable("unexpected overflowing operator");
14824 }
14825 if (CondOpcode == ISD::UMULO)
14826 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14827 MVT::i32);
14828 else
14829 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14831 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
14833 if (CondOpcode == ISD::UMULO)
14834 Cond = X86Op.getValue(2);
14835 else
14836 Cond = X86Op.getValue(1);
14838 CC = DAG.getConstant(X86Cond, MVT::i8);
14839 addTest = false;
14840 }
14842 if (addTest) {
14843 // Look pass the truncate if the high bits are known zero.
14844 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14845 Cond = Cond.getOperand(0);
14847 // We know the result of AND is compared against zero. Try to match
14848 // it to BT.
14849 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14850 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
14851 if (NewSetCC.getNode()) {
14852 CC = NewSetCC.getOperand(0);
14853 Cond = NewSetCC.getOperand(1);
14854 addTest = false;
14855 }
14856 }
14857 }
14859 if (addTest) {
14860 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
14861 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
14862 }
14864 // a < b ? -1 : 0 -> RES = ~setcc_carry
14865 // a < b ? 0 : -1 -> RES = setcc_carry
14866 // a >= b ? -1 : 0 -> RES = setcc_carry
14867 // a >= b ? 0 : -1 -> RES = ~setcc_carry
14868 if (Cond.getOpcode() == X86ISD::SUB) {
14869 Cond = ConvertCmpIfNecessary(Cond, DAG);
14870 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
14872 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
14873 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
14874 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14875 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
14876 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
14877 return DAG.getNOT(DL, Res, Res.getValueType());
14878 return Res;
14879 }
14880 }
14882 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
14883 // widen the cmov and push the truncate through. This avoids introducing a new
14884 // branch during isel and doesn't add any extensions.
14885 if (Op.getValueType() == MVT::i8 &&
14886 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
14887 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
14888 if (T1.getValueType() == T2.getValueType() &&
14889 // Blacklist CopyFromReg to avoid partial register stalls.
14890 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
14891 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
14892 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
14893 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
14894 }
14895 }
14897 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
14898 // condition is true.
14899 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
14900 SDValue Ops[] = { Op2, Op1, CC, Cond };
14901 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
14902 }
14904 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
14905 MVT VT = Op->getSimpleValueType(0);
14906 SDValue In = Op->getOperand(0);
14907 MVT InVT = In.getSimpleValueType();
14908 SDLoc dl(Op);
14910 unsigned int NumElts = VT.getVectorNumElements();
14911 if (NumElts != 8 && NumElts != 16)
14912 return SDValue();
14914 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
14915 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14917 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14918 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14920 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
14921 Constant *C = ConstantInt::get(*DAG.getContext(),
14922 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
14924 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
14925 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14926 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
14927 MachinePointerInfo::getConstantPool(),
14928 false, false, false, Alignment);
14929 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
14930 if (VT.is512BitVector())
14931 return Brcst;
14932 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
14933 }
14935 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14936 SelectionDAG &DAG) {
14937 MVT VT = Op->getSimpleValueType(0);
14938 SDValue In = Op->getOperand(0);
14939 MVT InVT = In.getSimpleValueType();
14940 SDLoc dl(Op);
14942 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
14943 return LowerSIGN_EXTEND_AVX512(Op, DAG);
14945 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
14946 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
14947 (VT != MVT::v16i16 || InVT != MVT::v16i8))
14948 return SDValue();
14950 if (Subtarget->hasInt256())
14951 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14953 // Optimize vectors in AVX mode
14954 // Sign extend v8i16 to v8i32 and
14955 // v4i32 to v4i64
14956 //
14957 // Divide input vector into two parts
14958 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14959 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14960 // concat the vectors to original VT
14962 unsigned NumElems = InVT.getVectorNumElements();
14963 SDValue Undef = DAG.getUNDEF(InVT);
14965 SmallVector<int,8> ShufMask1(NumElems, -1);
14966 for (unsigned i = 0; i != NumElems/2; ++i)
14967 ShufMask1[i] = i;
14969 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
14971 SmallVector<int,8> ShufMask2(NumElems, -1);
14972 for (unsigned i = 0; i != NumElems/2; ++i)
14973 ShufMask2[i] = i + NumElems/2;
14975 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
14977 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
14978 VT.getVectorNumElements()/2);
14980 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
14981 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
14983 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14984 }
14986 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
14987 // may emit an illegal shuffle but the expansion is still better than scalar
14988 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
14989 // we'll emit a shuffle and a arithmetic shift.
14990 // TODO: It is possible to support ZExt by zeroing the undef values during
14991 // the shuffle phase or after the shuffle.
14992 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
14993 SelectionDAG &DAG) {
14994 MVT RegVT = Op.getSimpleValueType();
14995 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
14996 assert(RegVT.isInteger() &&
14997 "We only custom lower integer vector sext loads.");
14999 // Nothing useful we can do without SSE2 shuffles.
15000 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15002 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15003 SDLoc dl(Ld);
15004 EVT MemVT = Ld->getMemoryVT();
15005 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15006 unsigned RegSz = RegVT.getSizeInBits();
15008 ISD::LoadExtType Ext = Ld->getExtensionType();
15010 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15011 && "Only anyext and sext are currently implemented.");
15012 assert(MemVT != RegVT && "Cannot extend to the same type");
15013 assert(MemVT.isVector() && "Must load a vector from memory");
15015 unsigned NumElems = RegVT.getVectorNumElements();
15016 unsigned MemSz = MemVT.getSizeInBits();
15017 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15019 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15020 // The only way in which we have a legal 256-bit vector result but not the
15021 // integer 256-bit operations needed to directly lower a sextload is if we
15022 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15023 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15024 // correctly legalized. We do this late to allow the canonical form of
15025 // sextload to persist throughout the rest of the DAG combiner -- it wants
15026 // to fold together any extensions it can, and so will fuse a sign_extend
15027 // of an sextload into a sextload targeting a wider value.
15028 SDValue Load;
15029 if (MemSz == 128) {
15030 // Just switch this to a normal load.
15031 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15032 "it must be a legal 128-bit vector "
15033 "type!");
15034 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15035 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15036 Ld->isInvariant(), Ld->getAlignment());
15037 } else {
15038 assert(MemSz < 128 &&
15039 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15040 // Do an sext load to a 128-bit vector type. We want to use the same
15041 // number of elements, but elements half as wide. This will end up being
15042 // recursively lowered by this routine, but will succeed as we definitely
15043 // have all the necessary features if we're using AVX1.
15044 EVT HalfEltVT =
15045 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15046 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15047 Load =
15048 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15049 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15050 Ld->isNonTemporal(), Ld->isInvariant(),
15051 Ld->getAlignment());
15052 }
15054 // Replace chain users with the new chain.
15055 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15056 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15058 // Finally, do a normal sign-extend to the desired register.
15059 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15060 }
15062 // All sizes must be a power of two.
15063 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15064 "Non-power-of-two elements are not custom lowered!");
15066 // Attempt to load the original value using scalar loads.
15067 // Find the largest scalar type that divides the total loaded size.
15068 MVT SclrLoadTy = MVT::i8;
15069 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
15070 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
15071 MVT Tp = (MVT::SimpleValueType)tp;
15072 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15073 SclrLoadTy = Tp;
15074 }
15075 }
15077 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15078 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15079 (64 <= MemSz))
15080 SclrLoadTy = MVT::f64;
15082 // Calculate the number of scalar loads that we need to perform
15083 // in order to load our vector from memory.
15084 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15086 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
15087 "Can only lower sext loads with a single scalar load!");
15089 unsigned loadRegZize = RegSz;
15090 if (Ext == ISD::SEXTLOAD && RegSz == 256)
15091 loadRegZize /= 2;
15093 // Represent our vector as a sequence of elements which are the
15094 // largest scalar that we can load.
15095 EVT LoadUnitVecVT = EVT::getVectorVT(
15096 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15098 // Represent the data using the same element type that is stored in
15099 // memory. In practice, we ''widen'' MemVT.
15100 EVT WideVecVT =
15101 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15102 loadRegZize / MemVT.getScalarType().getSizeInBits());
15104 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15105 "Invalid vector type");
15107 // We can't shuffle using an illegal type.
15108 assert(TLI.isTypeLegal(WideVecVT) &&
15109 "We only lower types that form legal widened vector types");
15111 SmallVector<SDValue, 8> Chains;
15112 SDValue Ptr = Ld->getBasePtr();
15113 SDValue Increment =
15114 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
15115 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
15117 for (unsigned i = 0; i < NumLoads; ++i) {
15118 // Perform a single load.
15119 SDValue ScalarLoad =
15120 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
15121 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
15122 Ld->getAlignment());
15123 Chains.push_back(ScalarLoad.getValue(1));
15124 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
15125 // another round of DAGCombining.
15126 if (i == 0)
15127 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
15128 else
15129 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
15130 ScalarLoad, DAG.getIntPtrConstant(i));
15132 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
15133 }
15135 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
15137 // Bitcast the loaded value to a vector of the original element type, in
15138 // the size of the target vector type.
15139 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
15140 unsigned SizeRatio = RegSz / MemSz;
15142 if (Ext == ISD::SEXTLOAD) {
15143 // If we have SSE4.1, we can directly emit a VSEXT node.
15144 if (Subtarget->hasSSE41()) {
15145 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
15146 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15147 return Sext;
15148 }
15150 // Otherwise we'll shuffle the small elements in the high bits of the
15151 // larger type and perform an arithmetic shift. If the shift is not legal
15152 // it's better to scalarize.
15153 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
15154 "We can't implement a sext load without an arithmetic right shift!");
15156 // Redistribute the loaded elements into the different locations.
15157 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15158 for (unsigned i = 0; i != NumElems; ++i)
15159 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
15161 SDValue Shuff = DAG.getVectorShuffle(
15162 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15164 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
15166 // Build the arithmetic shift.
15167 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
15168 MemVT.getVectorElementType().getSizeInBits();
15169 Shuff =
15170 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
15172 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15173 return Shuff;
15174 }
15176 // Redistribute the loaded elements into the different locations.
15177 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15178 for (unsigned i = 0; i != NumElems; ++i)
15179 ShuffleVec[i * SizeRatio] = i;
15181 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
15182 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15184 // Bitcast to the requested type.
15185 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
15186 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15187 return Shuff;
15188 }
15190 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
15191 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
15192 // from the AND / OR.
15193 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
15194 Opc = Op.getOpcode();
15195 if (Opc != ISD::OR && Opc != ISD::AND)
15196 return false;
15197 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15198 Op.getOperand(0).hasOneUse() &&
15199 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
15200 Op.getOperand(1).hasOneUse());
15201 }
15203 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
15204 // 1 and that the SETCC node has a single use.
15205 static bool isXor1OfSetCC(SDValue Op) {
15206 if (Op.getOpcode() != ISD::XOR)
15207 return false;
15208 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
15209 if (N1C && N1C->getAPIntValue() == 1) {
15210 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15211 Op.getOperand(0).hasOneUse();
15212 }
15213 return false;
15214 }
15216 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
15217 bool addTest = true;
15218 SDValue Chain = Op.getOperand(0);
15219 SDValue Cond = Op.getOperand(1);
15220 SDValue Dest = Op.getOperand(2);
15221 SDLoc dl(Op);
15222 SDValue CC;
15223 bool Inverted = false;
15225 if (Cond.getOpcode() == ISD::SETCC) {
15226 // Check for setcc([su]{add,sub,mul}o == 0).
15227 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
15228 isa<ConstantSDNode>(Cond.getOperand(1)) &&
15229 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
15230 Cond.getOperand(0).getResNo() == 1 &&
15231 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
15232 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
15233 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
15234 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
15235 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
15236 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
15237 Inverted = true;
15238 Cond = Cond.getOperand(0);
15239 } else {
15240 SDValue NewCond = LowerSETCC(Cond, DAG);
15241 if (NewCond.getNode())
15242 Cond = NewCond;
15243 }
15244 }
15245 #if 0
15246 // FIXME: LowerXALUO doesn't handle these!!
15247 else if (Cond.getOpcode() == X86ISD::ADD ||
15248 Cond.getOpcode() == X86ISD::SUB ||
15249 Cond.getOpcode() == X86ISD::SMUL ||
15250 Cond.getOpcode() == X86ISD::UMUL)
15251 Cond = LowerXALUO(Cond, DAG);
15252 #endif
15254 // Look pass (and (setcc_carry (cmp ...)), 1).
15255 if (Cond.getOpcode() == ISD::AND &&
15256 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15257 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15258 if (C && C->getAPIntValue() == 1)
15259 Cond = Cond.getOperand(0);
15260 }
15262 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15263 // setting operand in place of the X86ISD::SETCC.
15264 unsigned CondOpcode = Cond.getOpcode();
15265 if (CondOpcode == X86ISD::SETCC ||
15266 CondOpcode == X86ISD::SETCC_CARRY) {
15267 CC = Cond.getOperand(0);
15269 SDValue Cmp = Cond.getOperand(1);
15270 unsigned Opc = Cmp.getOpcode();
15271 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
15272 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
15273 Cond = Cmp;
15274 addTest = false;
15275 } else {
15276 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
15277 default: break;
15278 case X86::COND_O:
15279 case X86::COND_B:
15280 // These can only come from an arithmetic instruction with overflow,
15281 // e.g. SADDO, UADDO.
15282 Cond = Cond.getNode()->getOperand(1);
15283 addTest = false;
15284 break;
15285 }
15286 }
15287 }
15288 CondOpcode = Cond.getOpcode();
15289 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15290 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15291 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15292 Cond.getOperand(0).getValueType() != MVT::i8)) {
15293 SDValue LHS = Cond.getOperand(0);
15294 SDValue RHS = Cond.getOperand(1);
15295 unsigned X86Opcode;
15296 unsigned X86Cond;
15297 SDVTList VTs;
15298 // Keep this in sync with LowerXALUO, otherwise we might create redundant
15299 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
15300 // X86ISD::INC).
15301 switch (CondOpcode) {
15302 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15303 case ISD::SADDO:
15304 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15305 if (C->isOne()) {
15306 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
15307 break;
15308 }
15309 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15310 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15311 case ISD::SSUBO:
15312 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15313 if (C->isOne()) {
15314 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
15315 break;
15316 }
15317 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15318 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15319 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15320 default: llvm_unreachable("unexpected overflowing operator");
15321 }
15322 if (Inverted)
15323 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
15324 if (CondOpcode == ISD::UMULO)
15325 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15326 MVT::i32);
15327 else
15328 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15330 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
15332 if (CondOpcode == ISD::UMULO)
15333 Cond = X86Op.getValue(2);
15334 else
15335 Cond = X86Op.getValue(1);
15337 CC = DAG.getConstant(X86Cond, MVT::i8);
15338 addTest = false;
15339 } else {
15340 unsigned CondOpc;
15341 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
15342 SDValue Cmp = Cond.getOperand(0).getOperand(1);
15343 if (CondOpc == ISD::OR) {
15344 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
15345 // two branches instead of an explicit OR instruction with a
15346 // separate test.
15347 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15348 isX86LogicalCmp(Cmp)) {
15349 CC = Cond.getOperand(0).getOperand(0);
15350 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15351 Chain, Dest, CC, Cmp);
15352 CC = Cond.getOperand(1).getOperand(0);
15353 Cond = Cmp;
15354 addTest = false;
15355 }
15356 } else { // ISD::AND
15357 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
15358 // two branches instead of an explicit AND instruction with a
15359 // separate test. However, we only do this if this block doesn't
15360 // have a fall-through edge, because this requires an explicit
15361 // jmp when the condition is false.
15362 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15363 isX86LogicalCmp(Cmp) &&
15364 Op.getNode()->hasOneUse()) {
15365 X86::CondCode CCode =
15366 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15367 CCode = X86::GetOppositeBranchCondition(CCode);
15368 CC = DAG.getConstant(CCode, MVT::i8);
15369 SDNode *User = *Op.getNode()->use_begin();
15370 // Look for an unconditional branch following this conditional branch.
15371 // We need this because we need to reverse the successors in order
15372 // to implement FCMP_OEQ.
15373 if (User->getOpcode() == ISD::BR) {
15374 SDValue FalseBB = User->getOperand(1);
15375 SDNode *NewBR =
15376 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15377 assert(NewBR == User);
15378 (void)NewBR;
15379 Dest = FalseBB;
15381 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15382 Chain, Dest, CC, Cmp);
15383 X86::CondCode CCode =
15384 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
15385 CCode = X86::GetOppositeBranchCondition(CCode);
15386 CC = DAG.getConstant(CCode, MVT::i8);
15387 Cond = Cmp;
15388 addTest = false;
15389 }
15390 }
15391 }
15392 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
15393 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
15394 // It should be transformed during dag combiner except when the condition
15395 // is set by a arithmetics with overflow node.
15396 X86::CondCode CCode =
15397 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15398 CCode = X86::GetOppositeBranchCondition(CCode);
15399 CC = DAG.getConstant(CCode, MVT::i8);
15400 Cond = Cond.getOperand(0).getOperand(1);
15401 addTest = false;
15402 } else if (Cond.getOpcode() == ISD::SETCC &&
15403 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
15404 // For FCMP_OEQ, we can emit
15405 // two branches instead of an explicit AND instruction with a
15406 // separate test. However, we only do this if this block doesn't
15407 // have a fall-through edge, because this requires an explicit
15408 // jmp when the condition is false.
15409 if (Op.getNode()->hasOneUse()) {
15410 SDNode *User = *Op.getNode()->use_begin();
15411 // Look for an unconditional branch following this conditional branch.
15412 // We need this because we need to reverse the successors in order
15413 // to implement FCMP_OEQ.
15414 if (User->getOpcode() == ISD::BR) {
15415 SDValue FalseBB = User->getOperand(1);
15416 SDNode *NewBR =
15417 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15418 assert(NewBR == User);
15419 (void)NewBR;
15420 Dest = FalseBB;
15422 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15423 Cond.getOperand(0), Cond.getOperand(1));
15424 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15425 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15426 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15427 Chain, Dest, CC, Cmp);
15428 CC = DAG.getConstant(X86::COND_P, MVT::i8);
15429 Cond = Cmp;
15430 addTest = false;
15431 }
15432 }
15433 } else if (Cond.getOpcode() == ISD::SETCC &&
15434 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
15435 // For FCMP_UNE, we can emit
15436 // two branches instead of an explicit AND instruction with a
15437 // separate test. However, we only do this if this block doesn't
15438 // have a fall-through edge, because this requires an explicit
15439 // jmp when the condition is false.
15440 if (Op.getNode()->hasOneUse()) {
15441 SDNode *User = *Op.getNode()->use_begin();
15442 // Look for an unconditional branch following this conditional branch.
15443 // We need this because we need to reverse the successors in order
15444 // to implement FCMP_UNE.
15445 if (User->getOpcode() == ISD::BR) {
15446 SDValue FalseBB = User->getOperand(1);
15447 SDNode *NewBR =
15448 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15449 assert(NewBR == User);
15450 (void)NewBR;
15452 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15453 Cond.getOperand(0), Cond.getOperand(1));
15454 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15455 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15456 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15457 Chain, Dest, CC, Cmp);
15458 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
15459 Cond = Cmp;
15460 addTest = false;
15461 Dest = FalseBB;
15462 }
15463 }
15464 }
15465 }
15467 if (addTest) {
15468 // Look pass the truncate if the high bits are known zero.
15469 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15470 Cond = Cond.getOperand(0);
15472 // We know the result of AND is compared against zero. Try to match
15473 // it to BT.
15474 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15475 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
15476 if (NewSetCC.getNode()) {
15477 CC = NewSetCC.getOperand(0);
15478 Cond = NewSetCC.getOperand(1);
15479 addTest = false;
15480 }
15481 }
15482 }
15484 if (addTest) {
15485 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
15486 CC = DAG.getConstant(X86Cond, MVT::i8);
15487 Cond = EmitTest(Cond, X86Cond, dl, DAG);
15488 }
15489 Cond = ConvertCmpIfNecessary(Cond, DAG);
15490 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15491 Chain, Dest, CC, Cond);
15492 }
15494 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
15495 // Calls to _alloca are needed to probe the stack when allocating more than 4k
15496 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
15497 // that the guard pages used by the OS virtual memory manager are allocated in
15498 // correct sequence.
15499 SDValue
15500 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
15501 SelectionDAG &DAG) const {
15502 MachineFunction &MF = DAG.getMachineFunction();
15503 bool SplitStack = MF.shouldSplitStack();
15504 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
15505 SplitStack;
15506 SDLoc dl(Op);
15508 if (!Lower) {
15509 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15510 SDNode* Node = Op.getNode();
15512 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
15513 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
15514 " not tell us which reg is the stack pointer!");
15515 EVT VT = Node->getValueType(0);
15516 SDValue Tmp1 = SDValue(Node, 0);
15517 SDValue Tmp2 = SDValue(Node, 1);
15518 SDValue Tmp3 = Node->getOperand(2);
15519 SDValue Chain = Tmp1.getOperand(0);
15521 // Chain the dynamic stack allocation so that it doesn't modify the stack
15522 // pointer when other instructions are using the stack.
15523 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
15524 SDLoc(Node));
15526 SDValue Size = Tmp2.getOperand(1);
15527 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
15528 Chain = SP.getValue(1);
15529 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
15530 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
15531 unsigned StackAlign = TFI.getStackAlignment();
15532 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
15533 if (Align > StackAlign)
15534 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
15535 DAG.getConstant(-(uint64_t)Align, VT));
15536 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
15538 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
15539 DAG.getIntPtrConstant(0, true), SDValue(),
15540 SDLoc(Node));
15542 SDValue Ops[2] = { Tmp1, Tmp2 };
15543 return DAG.getMergeValues(Ops, dl);
15544 }
15546 // Get the inputs.
15547 SDValue Chain = Op.getOperand(0);
15548 SDValue Size = Op.getOperand(1);
15549 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
15550 EVT VT = Op.getNode()->getValueType(0);
15552 bool Is64Bit = Subtarget->is64Bit();
15553 EVT SPTy = getPointerTy();
15555 if (SplitStack) {
15556 MachineRegisterInfo &MRI = MF.getRegInfo();
15558 if (Is64Bit) {
15559 // The 64 bit implementation of segmented stacks needs to clobber both r10
15560 // r11. This makes it impossible to use it along with nested parameters.
15561 const Function *F = MF.getFunction();
15563 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
15564 I != E; ++I)
15565 if (I->hasNestAttr())
15566 report_fatal_error("Cannot use segmented stacks with functions that "
15567 "have nested arguments.");
15568 }
15570 const TargetRegisterClass *AddrRegClass =
15571 getRegClassFor(getPointerTy());
15572 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
15573 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
15574 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
15575 DAG.getRegister(Vreg, SPTy));
15576 SDValue Ops1[2] = { Value, Chain };
15577 return DAG.getMergeValues(Ops1, dl);
15578 } else {
15579 SDValue Flag;
15580 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
15582 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
15583 Flag = Chain.getValue(1);
15584 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
15586 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
15588 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15589 DAG.getSubtarget().getRegisterInfo());
15590 unsigned SPReg = RegInfo->getStackRegister();
15591 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
15592 Chain = SP.getValue(1);
15594 if (Align) {
15595 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
15596 DAG.getConstant(-(uint64_t)Align, VT));
15597 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
15598 }
15600 SDValue Ops1[2] = { SP, Chain };
15601 return DAG.getMergeValues(Ops1, dl);
15602 }
15603 }
15605 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
15606 MachineFunction &MF = DAG.getMachineFunction();
15607 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15609 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15610 SDLoc DL(Op);
15612 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
15613 // vastart just stores the address of the VarArgsFrameIndex slot into the
15614 // memory location argument.
15615 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
15616 getPointerTy());
15617 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
15618 MachinePointerInfo(SV), false, false, 0);
15619 }
15621 // __va_list_tag:
15622 // gp_offset (0 - 6 * 8)
15623 // fp_offset (48 - 48 + 8 * 16)
15624 // overflow_arg_area (point to parameters coming in memory).
15625 // reg_save_area
15626 SmallVector<SDValue, 8> MemOps;
15627 SDValue FIN = Op.getOperand(1);
15628 // Store gp_offset
15629 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
15630 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
15631 MVT::i32),
15632 FIN, MachinePointerInfo(SV), false, false, 0);
15633 MemOps.push_back(Store);
15635 // Store fp_offset
15636 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15637 FIN, DAG.getIntPtrConstant(4));
15638 Store = DAG.getStore(Op.getOperand(0), DL,
15639 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
15640 MVT::i32),
15641 FIN, MachinePointerInfo(SV, 4), false, false, 0);
15642 MemOps.push_back(Store);
15644 // Store ptr to overflow_arg_area
15645 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15646 FIN, DAG.getIntPtrConstant(4));
15647 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
15648 getPointerTy());
15649 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
15650 MachinePointerInfo(SV, 8),
15651 false, false, 0);
15652 MemOps.push_back(Store);
15654 // Store ptr to reg_save_area.
15655 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15656 FIN, DAG.getIntPtrConstant(8));
15657 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
15658 getPointerTy());
15659 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
15660 MachinePointerInfo(SV, 16), false, false, 0);
15661 MemOps.push_back(Store);
15662 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
15663 }
15665 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
15666 assert(Subtarget->is64Bit() &&
15667 "LowerVAARG only handles 64-bit va_arg!");
15668 assert((Subtarget->isTargetLinux() ||
15669 Subtarget->isTargetDarwin()) &&
15670 "Unhandled target in LowerVAARG");
15671 assert(Op.getNode()->getNumOperands() == 4);
15672 SDValue Chain = Op.getOperand(0);
15673 SDValue SrcPtr = Op.getOperand(1);
15674 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15675 unsigned Align = Op.getConstantOperandVal(3);
15676 SDLoc dl(Op);
15678 EVT ArgVT = Op.getNode()->getValueType(0);
15679 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15680 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
15681 uint8_t ArgMode;
15683 // Decide which area this value should be read from.
15684 // TODO: Implement the AMD64 ABI in its entirety. This simple
15685 // selection mechanism works only for the basic types.
15686 if (ArgVT == MVT::f80) {
15687 llvm_unreachable("va_arg for f80 not yet implemented");
15688 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
15689 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
15690 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
15691 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
15692 } else {
15693 llvm_unreachable("Unhandled argument type in LowerVAARG");
15694 }
15696 if (ArgMode == 2) {
15697 // Sanity Check: Make sure using fp_offset makes sense.
15698 assert(!DAG.getTarget().Options.UseSoftFloat &&
15699 !(DAG.getMachineFunction()
15700 .getFunction()->getAttributes()
15701 .hasAttribute(AttributeSet::FunctionIndex,
15702 Attribute::NoImplicitFloat)) &&
15703 Subtarget->hasSSE1());
15704 }
15706 // Insert VAARG_64 node into the DAG
15707 // VAARG_64 returns two values: Variable Argument Address, Chain
15708 SmallVector<SDValue, 11> InstOps;
15709 InstOps.push_back(Chain);
15710 InstOps.push_back(SrcPtr);
15711 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
15712 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
15713 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
15714 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
15715 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
15716 VTs, InstOps, MVT::i64,
15717 MachinePointerInfo(SV),
15718 /*Align=*/0,
15719 /*Volatile=*/false,
15720 /*ReadMem=*/true,
15721 /*WriteMem=*/true);
15722 Chain = VAARG.getValue(1);
15724 // Load the next argument and return it
15725 return DAG.getLoad(ArgVT, dl,
15726 Chain,
15727 VAARG,
15728 MachinePointerInfo(),
15729 false, false, false, 0);
15730 }
15732 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
15733 SelectionDAG &DAG) {
15734 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
15735 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
15736 SDValue Chain = Op.getOperand(0);
15737 SDValue DstPtr = Op.getOperand(1);
15738 SDValue SrcPtr = Op.getOperand(2);
15739 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
15740 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15741 SDLoc DL(Op);
15743 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
15744 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
15745 false,
15746 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
15747 }
15749 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
15750 // amount is a constant. Takes immediate version of shift as input.
15751 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
15752 SDValue SrcOp, uint64_t ShiftAmt,
15753 SelectionDAG &DAG) {
15754 MVT ElementType = VT.getVectorElementType();
15756 // Fold this packed shift into its first operand if ShiftAmt is 0.
15757 if (ShiftAmt == 0)
15758 return SrcOp;
15760 // Check for ShiftAmt >= element width
15761 if (ShiftAmt >= ElementType.getSizeInBits()) {
15762 if (Opc == X86ISD::VSRAI)
15763 ShiftAmt = ElementType.getSizeInBits() - 1;
15764 else
15765 return DAG.getConstant(0, VT);
15766 }
15768 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
15769 && "Unknown target vector shift-by-constant node");
15771 // Fold this packed vector shift into a build vector if SrcOp is a
15772 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
15773 if (VT == SrcOp.getSimpleValueType() &&
15774 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
15775 SmallVector<SDValue, 8> Elts;
15776 unsigned NumElts = SrcOp->getNumOperands();
15777 ConstantSDNode *ND;
15779 switch(Opc) {
15780 default: llvm_unreachable(nullptr);
15781 case X86ISD::VSHLI:
15782 for (unsigned i=0; i!=NumElts; ++i) {
15783 SDValue CurrentOp = SrcOp->getOperand(i);
15784 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15785 Elts.push_back(CurrentOp);
15786 continue;
15787 }
15788 ND = cast<ConstantSDNode>(CurrentOp);
15789 const APInt &C = ND->getAPIntValue();
15790 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
15791 }
15792 break;
15793 case X86ISD::VSRLI:
15794 for (unsigned i=0; i!=NumElts; ++i) {
15795 SDValue CurrentOp = SrcOp->getOperand(i);
15796 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15797 Elts.push_back(CurrentOp);
15798 continue;
15799 }
15800 ND = cast<ConstantSDNode>(CurrentOp);
15801 const APInt &C = ND->getAPIntValue();
15802 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
15803 }
15804 break;
15805 case X86ISD::VSRAI:
15806 for (unsigned i=0; i!=NumElts; ++i) {
15807 SDValue CurrentOp = SrcOp->getOperand(i);
15808 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15809 Elts.push_back(CurrentOp);
15810 continue;
15811 }
15812 ND = cast<ConstantSDNode>(CurrentOp);
15813 const APInt &C = ND->getAPIntValue();
15814 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
15815 }
15816 break;
15817 }
15819 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15820 }
15822 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
15823 }
15825 // getTargetVShiftNode - Handle vector element shifts where the shift amount
15826 // may or may not be a constant. Takes immediate version of shift as input.
15827 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
15828 SDValue SrcOp, SDValue ShAmt,
15829 SelectionDAG &DAG) {
15830 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
15832 // Catch shift-by-constant.
15833 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
15834 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
15835 CShAmt->getZExtValue(), DAG);
15837 // Change opcode to non-immediate version
15838 switch (Opc) {
15839 default: llvm_unreachable("Unknown target vector shift node");
15840 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
15841 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
15842 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
15843 }
15845 // Need to build a vector containing shift amount
15846 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
15847 SDValue ShOps[4];
15848 ShOps[0] = ShAmt;
15849 ShOps[1] = DAG.getConstant(0, MVT::i32);
15850 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
15851 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
15853 // The return type has to be a 128-bit type with the same element
15854 // type as the input type.
15855 MVT EltVT = VT.getVectorElementType();
15856 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
15858 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
15859 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
15860 }
15862 /// \brief Return (and \p Op, \p Mask) for compare instructions or
15863 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
15864 /// necessary casting for \p Mask when lowering masking intrinsics.
15865 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
15866 SDValue PreservedSrc, SelectionDAG &DAG) {
15867 EVT VT = Op.getValueType();
15868 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
15869 MVT::i1, VT.getVectorNumElements());
15870 SDLoc dl(Op);
15872 assert(MaskVT.isSimple() && "invalid mask type");
15874 if (isAllOnes(Mask))
15875 return Op;
15877 switch (Op.getOpcode()) {
15878 default: break;
15879 case X86ISD::PCMPEQM:
15880 case X86ISD::PCMPGTM:
15881 case X86ISD::CMPM:
15882 case X86ISD::CMPMU:
15883 return DAG.getNode(ISD::AND, dl, VT, Op,
15884 DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask));
15885 }
15887 return DAG.getNode(ISD::VSELECT, dl, VT,
15888 DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask),
15889 Op, PreservedSrc);
15890 }
15892 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
15893 switch (IntNo) {
15894 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15895 case Intrinsic::x86_fma_vfmadd_ps:
15896 case Intrinsic::x86_fma_vfmadd_pd:
15897 case Intrinsic::x86_fma_vfmadd_ps_256:
15898 case Intrinsic::x86_fma_vfmadd_pd_256:
15899 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
15900 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
15901 return X86ISD::FMADD;
15902 case Intrinsic::x86_fma_vfmsub_ps:
15903 case Intrinsic::x86_fma_vfmsub_pd:
15904 case Intrinsic::x86_fma_vfmsub_ps_256:
15905 case Intrinsic::x86_fma_vfmsub_pd_256:
15906 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
15907 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
15908 return X86ISD::FMSUB;
15909 case Intrinsic::x86_fma_vfnmadd_ps:
15910 case Intrinsic::x86_fma_vfnmadd_pd:
15911 case Intrinsic::x86_fma_vfnmadd_ps_256:
15912 case Intrinsic::x86_fma_vfnmadd_pd_256:
15913 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
15914 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
15915 return X86ISD::FNMADD;
15916 case Intrinsic::x86_fma_vfnmsub_ps:
15917 case Intrinsic::x86_fma_vfnmsub_pd:
15918 case Intrinsic::x86_fma_vfnmsub_ps_256:
15919 case Intrinsic::x86_fma_vfnmsub_pd_256:
15920 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
15921 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
15922 return X86ISD::FNMSUB;
15923 case Intrinsic::x86_fma_vfmaddsub_ps:
15924 case Intrinsic::x86_fma_vfmaddsub_pd:
15925 case Intrinsic::x86_fma_vfmaddsub_ps_256:
15926 case Intrinsic::x86_fma_vfmaddsub_pd_256:
15927 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
15928 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
15929 return X86ISD::FMADDSUB;
15930 case Intrinsic::x86_fma_vfmsubadd_ps:
15931 case Intrinsic::x86_fma_vfmsubadd_pd:
15932 case Intrinsic::x86_fma_vfmsubadd_ps_256:
15933 case Intrinsic::x86_fma_vfmsubadd_pd_256:
15934 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
15935 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
15936 return X86ISD::FMSUBADD;
15937 }
15938 }
15940 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
15941 SDLoc dl(Op);
15942 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15944 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
15945 if (IntrData) {
15946 switch(IntrData->Type) {
15947 case INTR_TYPE_1OP:
15948 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
15949 case INTR_TYPE_2OP:
15950 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15951 Op.getOperand(2));
15952 case INTR_TYPE_3OP:
15953 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15954 Op.getOperand(2), Op.getOperand(3));
15955 case CMP_MASK: {
15956 EVT VT = Op.getOperand(1).getValueType();
15957 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15958 VT.getVectorNumElements());
15959 SDValue Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT,
15960 Op.getOperand(1), Op.getOperand(2));
15961 SDValue Res = getVectorMaskingNode(Cmp, Op.getOperand(3),
15962 DAG.getTargetConstant(0, MaskVT), DAG);
15963 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
15964 }
15965 case COMI: { // Comparison intrinsics
15966 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
15967 SDValue LHS = Op.getOperand(1);
15968 SDValue RHS = Op.getOperand(2);
15969 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
15970 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
15971 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
15972 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15973 DAG.getConstant(X86CC, MVT::i8), Cond);
15974 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15975 }
15976 case VSHIFT:
15977 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
15978 Op.getOperand(1), Op.getOperand(2), DAG);
15979 default:
15980 break;
15981 }
15982 }
15984 switch (IntNo) {
15985 default: return SDValue(); // Don't custom lower most intrinsics.
15987 // Arithmetic intrinsics.
15988 case Intrinsic::x86_sse2_pmulu_dq:
15989 case Intrinsic::x86_avx2_pmulu_dq:
15990 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
15991 Op.getOperand(1), Op.getOperand(2));
15993 case Intrinsic::x86_sse41_pmuldq:
15994 case Intrinsic::x86_avx2_pmul_dq:
15995 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
15996 Op.getOperand(1), Op.getOperand(2));
15998 case Intrinsic::x86_sse2_pmulhu_w:
15999 case Intrinsic::x86_avx2_pmulhu_w:
16000 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
16001 Op.getOperand(1), Op.getOperand(2));
16003 case Intrinsic::x86_sse2_pmulh_w:
16004 case Intrinsic::x86_avx2_pmulh_w:
16005 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
16006 Op.getOperand(1), Op.getOperand(2));
16008 // SSE/SSE2/AVX floating point max/min intrinsics.
16009 case Intrinsic::x86_sse_max_ps:
16010 case Intrinsic::x86_sse2_max_pd:
16011 case Intrinsic::x86_avx_max_ps_256:
16012 case Intrinsic::x86_avx_max_pd_256:
16013 case Intrinsic::x86_sse_min_ps:
16014 case Intrinsic::x86_sse2_min_pd:
16015 case Intrinsic::x86_avx_min_ps_256:
16016 case Intrinsic::x86_avx_min_pd_256: {
16017 unsigned Opcode;
16018 switch (IntNo) {
16019 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16020 case Intrinsic::x86_sse_max_ps:
16021 case Intrinsic::x86_sse2_max_pd:
16022 case Intrinsic::x86_avx_max_ps_256:
16023 case Intrinsic::x86_avx_max_pd_256:
16024 Opcode = X86ISD::FMAX;
16025 break;
16026 case Intrinsic::x86_sse_min_ps:
16027 case Intrinsic::x86_sse2_min_pd:
16028 case Intrinsic::x86_avx_min_ps_256:
16029 case Intrinsic::x86_avx_min_pd_256:
16030 Opcode = X86ISD::FMIN;
16031 break;
16032 }
16033 return DAG.getNode(Opcode, dl, Op.getValueType(),
16034 Op.getOperand(1), Op.getOperand(2));
16035 }
16037 // AVX2 variable shift intrinsics
16038 case Intrinsic::x86_avx2_psllv_d:
16039 case Intrinsic::x86_avx2_psllv_q:
16040 case Intrinsic::x86_avx2_psllv_d_256:
16041 case Intrinsic::x86_avx2_psllv_q_256:
16042 case Intrinsic::x86_avx2_psrlv_d:
16043 case Intrinsic::x86_avx2_psrlv_q:
16044 case Intrinsic::x86_avx2_psrlv_d_256:
16045 case Intrinsic::x86_avx2_psrlv_q_256:
16046 case Intrinsic::x86_avx2_psrav_d:
16047 case Intrinsic::x86_avx2_psrav_d_256: {
16048 unsigned Opcode;
16049 switch (IntNo) {
16050 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16051 case Intrinsic::x86_avx2_psllv_d:
16052 case Intrinsic::x86_avx2_psllv_q:
16053 case Intrinsic::x86_avx2_psllv_d_256:
16054 case Intrinsic::x86_avx2_psllv_q_256:
16055 Opcode = ISD::SHL;
16056 break;
16057 case Intrinsic::x86_avx2_psrlv_d:
16058 case Intrinsic::x86_avx2_psrlv_q:
16059 case Intrinsic::x86_avx2_psrlv_d_256:
16060 case Intrinsic::x86_avx2_psrlv_q_256:
16061 Opcode = ISD::SRL;
16062 break;
16063 case Intrinsic::x86_avx2_psrav_d:
16064 case Intrinsic::x86_avx2_psrav_d_256:
16065 Opcode = ISD::SRA;
16066 break;
16067 }
16068 return DAG.getNode(Opcode, dl, Op.getValueType(),
16069 Op.getOperand(1), Op.getOperand(2));
16070 }
16072 case Intrinsic::x86_sse2_packssdw_128:
16073 case Intrinsic::x86_sse2_packsswb_128:
16074 case Intrinsic::x86_avx2_packssdw:
16075 case Intrinsic::x86_avx2_packsswb:
16076 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
16077 Op.getOperand(1), Op.getOperand(2));
16079 case Intrinsic::x86_sse2_packuswb_128:
16080 case Intrinsic::x86_sse41_packusdw:
16081 case Intrinsic::x86_avx2_packuswb:
16082 case Intrinsic::x86_avx2_packusdw:
16083 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
16084 Op.getOperand(1), Op.getOperand(2));
16086 case Intrinsic::x86_ssse3_pshuf_b_128:
16087 case Intrinsic::x86_avx2_pshuf_b:
16088 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
16089 Op.getOperand(1), Op.getOperand(2));
16091 case Intrinsic::x86_sse2_pshuf_d:
16092 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
16093 Op.getOperand(1), Op.getOperand(2));
16095 case Intrinsic::x86_sse2_pshufl_w:
16096 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
16097 Op.getOperand(1), Op.getOperand(2));
16099 case Intrinsic::x86_sse2_pshufh_w:
16100 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
16101 Op.getOperand(1), Op.getOperand(2));
16103 case Intrinsic::x86_ssse3_psign_b_128:
16104 case Intrinsic::x86_ssse3_psign_w_128:
16105 case Intrinsic::x86_ssse3_psign_d_128:
16106 case Intrinsic::x86_avx2_psign_b:
16107 case Intrinsic::x86_avx2_psign_w:
16108 case Intrinsic::x86_avx2_psign_d:
16109 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
16110 Op.getOperand(1), Op.getOperand(2));
16112 case Intrinsic::x86_avx2_permd:
16113 case Intrinsic::x86_avx2_permps:
16114 // Operands intentionally swapped. Mask is last operand to intrinsic,
16115 // but second operand for node/instruction.
16116 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
16117 Op.getOperand(2), Op.getOperand(1));
16119 case Intrinsic::x86_avx512_mask_valign_q_512:
16120 case Intrinsic::x86_avx512_mask_valign_d_512:
16121 // Vector source operands are swapped.
16122 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
16123 Op.getValueType(), Op.getOperand(2),
16124 Op.getOperand(1),
16125 Op.getOperand(3)),
16126 Op.getOperand(5), Op.getOperand(4), DAG);
16128 // ptest and testp intrinsics. The intrinsic these come from are designed to
16129 // return an integer value, not just an instruction so lower it to the ptest
16130 // or testp pattern and a setcc for the result.
16131 case Intrinsic::x86_sse41_ptestz:
16132 case Intrinsic::x86_sse41_ptestc:
16133 case Intrinsic::x86_sse41_ptestnzc:
16134 case Intrinsic::x86_avx_ptestz_256:
16135 case Intrinsic::x86_avx_ptestc_256:
16136 case Intrinsic::x86_avx_ptestnzc_256:
16137 case Intrinsic::x86_avx_vtestz_ps:
16138 case Intrinsic::x86_avx_vtestc_ps:
16139 case Intrinsic::x86_avx_vtestnzc_ps:
16140 case Intrinsic::x86_avx_vtestz_pd:
16141 case Intrinsic::x86_avx_vtestc_pd:
16142 case Intrinsic::x86_avx_vtestnzc_pd:
16143 case Intrinsic::x86_avx_vtestz_ps_256:
16144 case Intrinsic::x86_avx_vtestc_ps_256:
16145 case Intrinsic::x86_avx_vtestnzc_ps_256:
16146 case Intrinsic::x86_avx_vtestz_pd_256:
16147 case Intrinsic::x86_avx_vtestc_pd_256:
16148 case Intrinsic::x86_avx_vtestnzc_pd_256: {
16149 bool IsTestPacked = false;
16150 unsigned X86CC;
16151 switch (IntNo) {
16152 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
16153 case Intrinsic::x86_avx_vtestz_ps:
16154 case Intrinsic::x86_avx_vtestz_pd:
16155 case Intrinsic::x86_avx_vtestz_ps_256:
16156 case Intrinsic::x86_avx_vtestz_pd_256:
16157 IsTestPacked = true; // Fallthrough
16158 case Intrinsic::x86_sse41_ptestz:
16159 case Intrinsic::x86_avx_ptestz_256:
16160 // ZF = 1
16161 X86CC = X86::COND_E;
16162 break;
16163 case Intrinsic::x86_avx_vtestc_ps:
16164 case Intrinsic::x86_avx_vtestc_pd:
16165 case Intrinsic::x86_avx_vtestc_ps_256:
16166 case Intrinsic::x86_avx_vtestc_pd_256:
16167 IsTestPacked = true; // Fallthrough
16168 case Intrinsic::x86_sse41_ptestc:
16169 case Intrinsic::x86_avx_ptestc_256:
16170 // CF = 1
16171 X86CC = X86::COND_B;
16172 break;
16173 case Intrinsic::x86_avx_vtestnzc_ps:
16174 case Intrinsic::x86_avx_vtestnzc_pd:
16175 case Intrinsic::x86_avx_vtestnzc_ps_256:
16176 case Intrinsic::x86_avx_vtestnzc_pd_256:
16177 IsTestPacked = true; // Fallthrough
16178 case Intrinsic::x86_sse41_ptestnzc:
16179 case Intrinsic::x86_avx_ptestnzc_256:
16180 // ZF and CF = 0
16181 X86CC = X86::COND_A;
16182 break;
16183 }
16185 SDValue LHS = Op.getOperand(1);
16186 SDValue RHS = Op.getOperand(2);
16187 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
16188 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
16189 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
16190 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
16191 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16192 }
16193 case Intrinsic::x86_avx512_kortestz_w:
16194 case Intrinsic::x86_avx512_kortestc_w: {
16195 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
16196 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
16197 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
16198 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
16199 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
16200 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
16201 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16202 }
16204 case Intrinsic::x86_sse42_pcmpistria128:
16205 case Intrinsic::x86_sse42_pcmpestria128:
16206 case Intrinsic::x86_sse42_pcmpistric128:
16207 case Intrinsic::x86_sse42_pcmpestric128:
16208 case Intrinsic::x86_sse42_pcmpistrio128:
16209 case Intrinsic::x86_sse42_pcmpestrio128:
16210 case Intrinsic::x86_sse42_pcmpistris128:
16211 case Intrinsic::x86_sse42_pcmpestris128:
16212 case Intrinsic::x86_sse42_pcmpistriz128:
16213 case Intrinsic::x86_sse42_pcmpestriz128: {
16214 unsigned Opcode;
16215 unsigned X86CC;
16216 switch (IntNo) {
16217 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16218 case Intrinsic::x86_sse42_pcmpistria128:
16219 Opcode = X86ISD::PCMPISTRI;
16220 X86CC = X86::COND_A;
16221 break;
16222 case Intrinsic::x86_sse42_pcmpestria128:
16223 Opcode = X86ISD::PCMPESTRI;
16224 X86CC = X86::COND_A;
16225 break;
16226 case Intrinsic::x86_sse42_pcmpistric128:
16227 Opcode = X86ISD::PCMPISTRI;
16228 X86CC = X86::COND_B;
16229 break;
16230 case Intrinsic::x86_sse42_pcmpestric128:
16231 Opcode = X86ISD::PCMPESTRI;
16232 X86CC = X86::COND_B;
16233 break;
16234 case Intrinsic::x86_sse42_pcmpistrio128:
16235 Opcode = X86ISD::PCMPISTRI;
16236 X86CC = X86::COND_O;
16237 break;
16238 case Intrinsic::x86_sse42_pcmpestrio128:
16239 Opcode = X86ISD::PCMPESTRI;
16240 X86CC = X86::COND_O;
16241 break;
16242 case Intrinsic::x86_sse42_pcmpistris128:
16243 Opcode = X86ISD::PCMPISTRI;
16244 X86CC = X86::COND_S;
16245 break;
16246 case Intrinsic::x86_sse42_pcmpestris128:
16247 Opcode = X86ISD::PCMPESTRI;
16248 X86CC = X86::COND_S;
16249 break;
16250 case Intrinsic::x86_sse42_pcmpistriz128:
16251 Opcode = X86ISD::PCMPISTRI;
16252 X86CC = X86::COND_E;
16253 break;
16254 case Intrinsic::x86_sse42_pcmpestriz128:
16255 Opcode = X86ISD::PCMPESTRI;
16256 X86CC = X86::COND_E;
16257 break;
16258 }
16259 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16260 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16261 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
16262 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16263 DAG.getConstant(X86CC, MVT::i8),
16264 SDValue(PCMP.getNode(), 1));
16265 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16266 }
16268 case Intrinsic::x86_sse42_pcmpistri128:
16269 case Intrinsic::x86_sse42_pcmpestri128: {
16270 unsigned Opcode;
16271 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
16272 Opcode = X86ISD::PCMPISTRI;
16273 else
16274 Opcode = X86ISD::PCMPESTRI;
16276 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16277 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16278 return DAG.getNode(Opcode, dl, VTs, NewOps);
16279 }
16281 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16282 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16283 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16284 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16285 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16286 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16287 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16288 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16289 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16290 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16291 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16292 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
16293 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
16294 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
16295 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
16296 dl, Op.getValueType(),
16297 Op.getOperand(1),
16298 Op.getOperand(2),
16299 Op.getOperand(3)),
16300 Op.getOperand(4), Op.getOperand(1), DAG);
16301 else
16302 return SDValue();
16303 }
16305 case Intrinsic::x86_fma_vfmadd_ps:
16306 case Intrinsic::x86_fma_vfmadd_pd:
16307 case Intrinsic::x86_fma_vfmsub_ps:
16308 case Intrinsic::x86_fma_vfmsub_pd:
16309 case Intrinsic::x86_fma_vfnmadd_ps:
16310 case Intrinsic::x86_fma_vfnmadd_pd:
16311 case Intrinsic::x86_fma_vfnmsub_ps:
16312 case Intrinsic::x86_fma_vfnmsub_pd:
16313 case Intrinsic::x86_fma_vfmaddsub_ps:
16314 case Intrinsic::x86_fma_vfmaddsub_pd:
16315 case Intrinsic::x86_fma_vfmsubadd_ps:
16316 case Intrinsic::x86_fma_vfmsubadd_pd:
16317 case Intrinsic::x86_fma_vfmadd_ps_256:
16318 case Intrinsic::x86_fma_vfmadd_pd_256:
16319 case Intrinsic::x86_fma_vfmsub_ps_256:
16320 case Intrinsic::x86_fma_vfmsub_pd_256:
16321 case Intrinsic::x86_fma_vfnmadd_ps_256:
16322 case Intrinsic::x86_fma_vfnmadd_pd_256:
16323 case Intrinsic::x86_fma_vfnmsub_ps_256:
16324 case Intrinsic::x86_fma_vfnmsub_pd_256:
16325 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16326 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16327 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16328 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16329 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
16330 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
16331 }
16332 }
16334 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16335 SDValue Src, SDValue Mask, SDValue Base,
16336 SDValue Index, SDValue ScaleOp, SDValue Chain,
16337 const X86Subtarget * Subtarget) {
16338 SDLoc dl(Op);
16339 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16340 assert(C && "Invalid scale type");
16341 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16342 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16343 Index.getSimpleValueType().getVectorNumElements());
16344 SDValue MaskInReg;
16345 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16346 if (MaskC)
16347 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16348 else
16349 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16350 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
16351 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16352 SDValue Segment = DAG.getRegister(0, MVT::i32);
16353 if (Src.getOpcode() == ISD::UNDEF)
16354 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
16355 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16356 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16357 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
16358 return DAG.getMergeValues(RetOps, dl);
16359 }
16361 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16362 SDValue Src, SDValue Mask, SDValue Base,
16363 SDValue Index, SDValue ScaleOp, SDValue Chain) {
16364 SDLoc dl(Op);
16365 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16366 assert(C && "Invalid scale type");
16367 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16368 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16369 SDValue Segment = DAG.getRegister(0, MVT::i32);
16370 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16371 Index.getSimpleValueType().getVectorNumElements());
16372 SDValue MaskInReg;
16373 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16374 if (MaskC)
16375 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16376 else
16377 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16378 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
16379 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
16380 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16381 return SDValue(Res, 1);
16382 }
16384 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16385 SDValue Mask, SDValue Base, SDValue Index,
16386 SDValue ScaleOp, SDValue Chain) {
16387 SDLoc dl(Op);
16388 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16389 assert(C && "Invalid scale type");
16390 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16391 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16392 SDValue Segment = DAG.getRegister(0, MVT::i32);
16393 EVT MaskVT =
16394 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
16395 SDValue MaskInReg;
16396 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16397 if (MaskC)
16398 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16399 else
16400 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16401 //SDVTList VTs = DAG.getVTList(MVT::Other);
16402 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16403 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
16404 return SDValue(Res, 0);
16405 }
16407 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
16408 // read performance monitor counters (x86_rdpmc).
16409 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
16410 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16411 SmallVectorImpl<SDValue> &Results) {
16412 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16413 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16414 SDValue LO, HI;
16416 // The ECX register is used to select the index of the performance counter
16417 // to read.
16418 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
16419 N->getOperand(2));
16420 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
16422 // Reads the content of a 64-bit performance counter and returns it in the
16423 // registers EDX:EAX.
16424 if (Subtarget->is64Bit()) {
16425 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16426 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16427 LO.getValue(2));
16428 } else {
16429 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16430 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16431 LO.getValue(2));
16432 }
16433 Chain = HI.getValue(1);
16435 if (Subtarget->is64Bit()) {
16436 // The EAX register is loaded with the low-order 32 bits. The EDX register
16437 // is loaded with the supported high-order bits of the counter.
16438 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16439 DAG.getConstant(32, MVT::i8));
16440 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16441 Results.push_back(Chain);
16442 return;
16443 }
16445 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16446 SDValue Ops[] = { LO, HI };
16447 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16448 Results.push_back(Pair);
16449 Results.push_back(Chain);
16450 }
16452 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
16453 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
16454 // also used to custom lower READCYCLECOUNTER nodes.
16455 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
16456 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16457 SmallVectorImpl<SDValue> &Results) {
16458 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16459 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
16460 SDValue LO, HI;
16462 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
16463 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
16464 // and the EAX register is loaded with the low-order 32 bits.
16465 if (Subtarget->is64Bit()) {
16466 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16467 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16468 LO.getValue(2));
16469 } else {
16470 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16471 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16472 LO.getValue(2));
16473 }
16474 SDValue Chain = HI.getValue(1);
16476 if (Opcode == X86ISD::RDTSCP_DAG) {
16477 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16479 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
16480 // the ECX register. Add 'ecx' explicitly to the chain.
16481 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
16482 HI.getValue(2));
16483 // Explicitly store the content of ECX at the location passed in input
16484 // to the 'rdtscp' intrinsic.
16485 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
16486 MachinePointerInfo(), false, false, 0);
16487 }
16489 if (Subtarget->is64Bit()) {
16490 // The EDX register is loaded with the high-order 32 bits of the MSR, and
16491 // the EAX register is loaded with the low-order 32 bits.
16492 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16493 DAG.getConstant(32, MVT::i8));
16494 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16495 Results.push_back(Chain);
16496 return;
16497 }
16499 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16500 SDValue Ops[] = { LO, HI };
16501 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16502 Results.push_back(Pair);
16503 Results.push_back(Chain);
16504 }
16506 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
16507 SelectionDAG &DAG) {
16508 SmallVector<SDValue, 2> Results;
16509 SDLoc DL(Op);
16510 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
16511 Results);
16512 return DAG.getMergeValues(Results, DL);
16513 }
16516 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16517 SelectionDAG &DAG) {
16518 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
16520 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
16521 if (!IntrData)
16522 return SDValue();
16524 SDLoc dl(Op);
16525 switch(IntrData->Type) {
16526 default:
16527 llvm_unreachable("Unknown Intrinsic Type");
16528 break;
16529 case RDSEED:
16530 case RDRAND: {
16531 // Emit the node with the right value type.
16532 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
16533 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16535 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
16536 // Otherwise return the value from Rand, which is always 0, casted to i32.
16537 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
16538 DAG.getConstant(1, Op->getValueType(1)),
16539 DAG.getConstant(X86::COND_B, MVT::i32),
16540 SDValue(Result.getNode(), 1) };
16541 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
16542 DAG.getVTList(Op->getValueType(1), MVT::Glue),
16543 Ops);
16545 // Return { result, isValid, chain }.
16546 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
16547 SDValue(Result.getNode(), 2));
16548 }
16549 case GATHER: {
16550 //gather(v1, mask, index, base, scale);
16551 SDValue Chain = Op.getOperand(0);
16552 SDValue Src = Op.getOperand(2);
16553 SDValue Base = Op.getOperand(3);
16554 SDValue Index = Op.getOperand(4);
16555 SDValue Mask = Op.getOperand(5);
16556 SDValue Scale = Op.getOperand(6);
16557 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
16558 Subtarget);
16559 }
16560 case SCATTER: {
16561 //scatter(base, mask, index, v1, scale);
16562 SDValue Chain = Op.getOperand(0);
16563 SDValue Base = Op.getOperand(2);
16564 SDValue Mask = Op.getOperand(3);
16565 SDValue Index = Op.getOperand(4);
16566 SDValue Src = Op.getOperand(5);
16567 SDValue Scale = Op.getOperand(6);
16568 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
16569 }
16570 case PREFETCH: {
16571 SDValue Hint = Op.getOperand(6);
16572 unsigned HintVal;
16573 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
16574 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
16575 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
16576 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
16577 SDValue Chain = Op.getOperand(0);
16578 SDValue Mask = Op.getOperand(2);
16579 SDValue Index = Op.getOperand(3);
16580 SDValue Base = Op.getOperand(4);
16581 SDValue Scale = Op.getOperand(5);
16582 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
16583 }
16584 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
16585 case RDTSC: {
16586 SmallVector<SDValue, 2> Results;
16587 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
16588 return DAG.getMergeValues(Results, dl);
16589 }
16590 // Read Performance Monitoring Counters.
16591 case RDPMC: {
16592 SmallVector<SDValue, 2> Results;
16593 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
16594 return DAG.getMergeValues(Results, dl);
16595 }
16596 // XTEST intrinsics.
16597 case XTEST: {
16598 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16599 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16600 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16601 DAG.getConstant(X86::COND_NE, MVT::i8),
16602 InTrans);
16603 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
16604 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
16605 Ret, SDValue(InTrans.getNode(), 1));
16606 }
16607 // ADC/ADCX/SBB
16608 case ADX: {
16609 SmallVector<SDValue, 2> Results;
16610 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16611 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
16612 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
16613 DAG.getConstant(-1, MVT::i8));
16614 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
16615 Op.getOperand(4), GenCF.getValue(1));
16616 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
16617 Op.getOperand(5), MachinePointerInfo(),
16618 false, false, 0);
16619 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16620 DAG.getConstant(X86::COND_B, MVT::i8),
16621 Res.getValue(1));
16622 Results.push_back(SetCC);
16623 Results.push_back(Store);
16624 return DAG.getMergeValues(Results, dl);
16625 }
16626 }
16627 }
16629 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
16630 SelectionDAG &DAG) const {
16631 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16632 MFI->setReturnAddressIsTaken(true);
16634 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
16635 return SDValue();
16637 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16638 SDLoc dl(Op);
16639 EVT PtrVT = getPointerTy();
16641 if (Depth > 0) {
16642 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
16643 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16644 DAG.getSubtarget().getRegisterInfo());
16645 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
16646 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16647 DAG.getNode(ISD::ADD, dl, PtrVT,
16648 FrameAddr, Offset),
16649 MachinePointerInfo(), false, false, false, 0);
16650 }
16652 // Just load the return address.
16653 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
16654 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16655 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
16656 }
16658 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
16659 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16660 MFI->setFrameAddressIsTaken(true);
16662 EVT VT = Op.getValueType();
16663 SDLoc dl(Op); // FIXME probably not meaningful
16664 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16665 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16666 DAG.getSubtarget().getRegisterInfo());
16667 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
16668 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
16669 (FrameReg == X86::EBP && VT == MVT::i32)) &&
16670 "Invalid Frame Register!");
16671 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
16672 while (Depth--)
16673 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
16674 MachinePointerInfo(),
16675 false, false, false, 0);
16676 return FrameAddr;
16677 }
16679 // FIXME? Maybe this could be a TableGen attribute on some registers and
16680 // this table could be generated automatically from RegInfo.
16681 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
16682 EVT VT) const {
16683 unsigned Reg = StringSwitch<unsigned>(RegName)
16684 .Case("esp", X86::ESP)
16685 .Case("rsp", X86::RSP)
16686 .Default(0);
16687 if (Reg)
16688 return Reg;
16689 report_fatal_error("Invalid register name global variable");
16690 }
16692 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
16693 SelectionDAG &DAG) const {
16694 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16695 DAG.getSubtarget().getRegisterInfo());
16696 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
16697 }
16699 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
16700 SDValue Chain = Op.getOperand(0);
16701 SDValue Offset = Op.getOperand(1);
16702 SDValue Handler = Op.getOperand(2);
16703 SDLoc dl (Op);
16705 EVT PtrVT = getPointerTy();
16706 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16707 DAG.getSubtarget().getRegisterInfo());
16708 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
16709 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
16710 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
16711 "Invalid Frame Register!");
16712 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
16713 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
16715 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
16716 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
16717 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
16718 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
16719 false, false, 0);
16720 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
16722 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
16723 DAG.getRegister(StoreAddrReg, PtrVT));
16724 }
16726 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
16727 SelectionDAG &DAG) const {
16728 SDLoc DL(Op);
16729 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
16730 DAG.getVTList(MVT::i32, MVT::Other),
16731 Op.getOperand(0), Op.getOperand(1));
16732 }
16734 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
16735 SelectionDAG &DAG) const {
16736 SDLoc DL(Op);
16737 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
16738 Op.getOperand(0), Op.getOperand(1));
16739 }
16741 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
16742 return Op.getOperand(0);
16743 }
16745 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
16746 SelectionDAG &DAG) const {
16747 SDValue Root = Op.getOperand(0);
16748 SDValue Trmp = Op.getOperand(1); // trampoline
16749 SDValue FPtr = Op.getOperand(2); // nested function
16750 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
16751 SDLoc dl (Op);
16753 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16754 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
16756 if (Subtarget->is64Bit()) {
16757 SDValue OutChains[6];
16759 // Large code-model.
16760 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
16761 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
16763 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
16764 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
16766 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
16768 // Load the pointer to the nested function into R11.
16769 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
16770 SDValue Addr = Trmp;
16771 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16772 Addr, MachinePointerInfo(TrmpAddr),
16773 false, false, 0);
16775 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16776 DAG.getConstant(2, MVT::i64));
16777 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
16778 MachinePointerInfo(TrmpAddr, 2),
16779 false, false, 2);
16781 // Load the 'nest' parameter value into R10.
16782 // R10 is specified in X86CallingConv.td
16783 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
16784 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16785 DAG.getConstant(10, MVT::i64));
16786 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16787 Addr, MachinePointerInfo(TrmpAddr, 10),
16788 false, false, 0);
16790 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16791 DAG.getConstant(12, MVT::i64));
16792 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
16793 MachinePointerInfo(TrmpAddr, 12),
16794 false, false, 2);
16796 // Jump to the nested function.
16797 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
16798 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16799 DAG.getConstant(20, MVT::i64));
16800 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16801 Addr, MachinePointerInfo(TrmpAddr, 20),
16802 false, false, 0);
16804 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
16805 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16806 DAG.getConstant(22, MVT::i64));
16807 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
16808 MachinePointerInfo(TrmpAddr, 22),
16809 false, false, 0);
16811 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16812 } else {
16813 const Function *Func =
16814 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
16815 CallingConv::ID CC = Func->getCallingConv();
16816 unsigned NestReg;
16818 switch (CC) {
16819 default:
16820 llvm_unreachable("Unsupported calling convention");
16821 case CallingConv::C:
16822 case CallingConv::X86_StdCall: {
16823 // Pass 'nest' parameter in ECX.
16824 // Must be kept in sync with X86CallingConv.td
16825 NestReg = X86::ECX;
16827 // Check that ECX wasn't needed by an 'inreg' parameter.
16828 FunctionType *FTy = Func->getFunctionType();
16829 const AttributeSet &Attrs = Func->getAttributes();
16831 if (!Attrs.isEmpty() && !Func->isVarArg()) {
16832 unsigned InRegCount = 0;
16833 unsigned Idx = 1;
16835 for (FunctionType::param_iterator I = FTy->param_begin(),
16836 E = FTy->param_end(); I != E; ++I, ++Idx)
16837 if (Attrs.hasAttribute(Idx, Attribute::InReg))
16838 // FIXME: should only count parameters that are lowered to integers.
16839 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
16841 if (InRegCount > 2) {
16842 report_fatal_error("Nest register in use - reduce number of inreg"
16843 " parameters!");
16844 }
16845 }
16846 break;
16847 }
16848 case CallingConv::X86_FastCall:
16849 case CallingConv::X86_ThisCall:
16850 case CallingConv::Fast:
16851 // Pass 'nest' parameter in EAX.
16852 // Must be kept in sync with X86CallingConv.td
16853 NestReg = X86::EAX;
16854 break;
16855 }
16857 SDValue OutChains[4];
16858 SDValue Addr, Disp;
16860 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16861 DAG.getConstant(10, MVT::i32));
16862 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
16864 // This is storing the opcode for MOV32ri.
16865 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
16866 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
16867 OutChains[0] = DAG.getStore(Root, dl,
16868 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
16869 Trmp, MachinePointerInfo(TrmpAddr),
16870 false, false, 0);
16872 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16873 DAG.getConstant(1, MVT::i32));
16874 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
16875 MachinePointerInfo(TrmpAddr, 1),
16876 false, false, 1);
16878 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
16879 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16880 DAG.getConstant(5, MVT::i32));
16881 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
16882 MachinePointerInfo(TrmpAddr, 5),
16883 false, false, 1);
16885 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16886 DAG.getConstant(6, MVT::i32));
16887 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
16888 MachinePointerInfo(TrmpAddr, 6),
16889 false, false, 1);
16891 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16892 }
16893 }
16895 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
16896 SelectionDAG &DAG) const {
16897 /*
16898 The rounding mode is in bits 11:10 of FPSR, and has the following
16899 settings:
16900 00 Round to nearest
16901 01 Round to -inf
16902 10 Round to +inf
16903 11 Round to 0
16905 FLT_ROUNDS, on the other hand, expects the following:
16906 -1 Undefined
16907 0 Round to 0
16908 1 Round to nearest
16909 2 Round to +inf
16910 3 Round to -inf
16912 To perform the conversion, we do:
16913 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
16914 */
16916 MachineFunction &MF = DAG.getMachineFunction();
16917 const TargetMachine &TM = MF.getTarget();
16918 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
16919 unsigned StackAlignment = TFI.getStackAlignment();
16920 MVT VT = Op.getSimpleValueType();
16921 SDLoc DL(Op);
16923 // Save FP Control Word to stack slot
16924 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
16925 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
16927 MachineMemOperand *MMO =
16928 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
16929 MachineMemOperand::MOStore, 2, 2);
16931 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
16932 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
16933 DAG.getVTList(MVT::Other),
16934 Ops, MVT::i16, MMO);
16936 // Load FP Control Word from stack slot
16937 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
16938 MachinePointerInfo(), false, false, false, 0);
16940 // Transform as necessary
16941 SDValue CWD1 =
16942 DAG.getNode(ISD::SRL, DL, MVT::i16,
16943 DAG.getNode(ISD::AND, DL, MVT::i16,
16944 CWD, DAG.getConstant(0x800, MVT::i16)),
16945 DAG.getConstant(11, MVT::i8));
16946 SDValue CWD2 =
16947 DAG.getNode(ISD::SRL, DL, MVT::i16,
16948 DAG.getNode(ISD::AND, DL, MVT::i16,
16949 CWD, DAG.getConstant(0x400, MVT::i16)),
16950 DAG.getConstant(9, MVT::i8));
16952 SDValue RetVal =
16953 DAG.getNode(ISD::AND, DL, MVT::i16,
16954 DAG.getNode(ISD::ADD, DL, MVT::i16,
16955 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
16956 DAG.getConstant(1, MVT::i16)),
16957 DAG.getConstant(3, MVT::i16));
16959 return DAG.getNode((VT.getSizeInBits() < 16 ?
16960 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
16961 }
16963 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
16964 MVT VT = Op.getSimpleValueType();
16965 EVT OpVT = VT;
16966 unsigned NumBits = VT.getSizeInBits();
16967 SDLoc dl(Op);
16969 Op = Op.getOperand(0);
16970 if (VT == MVT::i8) {
16971 // Zero extend to i32 since there is not an i8 bsr.
16972 OpVT = MVT::i32;
16973 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16974 }
16976 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
16977 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16978 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16980 // If src is zero (i.e. bsr sets ZF), returns NumBits.
16981 SDValue Ops[] = {
16982 Op,
16983 DAG.getConstant(NumBits+NumBits-1, OpVT),
16984 DAG.getConstant(X86::COND_E, MVT::i8),
16985 Op.getValue(1)
16986 };
16987 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
16989 // Finally xor with NumBits-1.
16990 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
16992 if (VT == MVT::i8)
16993 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16994 return Op;
16995 }
16997 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
16998 MVT VT = Op.getSimpleValueType();
16999 EVT OpVT = VT;
17000 unsigned NumBits = VT.getSizeInBits();
17001 SDLoc dl(Op);
17003 Op = Op.getOperand(0);
17004 if (VT == MVT::i8) {
17005 // Zero extend to i32 since there is not an i8 bsr.
17006 OpVT = MVT::i32;
17007 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17008 }
17010 // Issue a bsr (scan bits in reverse).
17011 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17012 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17014 // And xor with NumBits-1.
17015 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17017 if (VT == MVT::i8)
17018 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17019 return Op;
17020 }
17022 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17023 MVT VT = Op.getSimpleValueType();
17024 unsigned NumBits = VT.getSizeInBits();
17025 SDLoc dl(Op);
17026 Op = Op.getOperand(0);
17028 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17029 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17030 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
17032 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17033 SDValue Ops[] = {
17034 Op,
17035 DAG.getConstant(NumBits, VT),
17036 DAG.getConstant(X86::COND_E, MVT::i8),
17037 Op.getValue(1)
17038 };
17039 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
17040 }
17042 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
17043 // ones, and then concatenate the result back.
17044 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
17045 MVT VT = Op.getSimpleValueType();
17047 assert(VT.is256BitVector() && VT.isInteger() &&
17048 "Unsupported value type for operation");
17050 unsigned NumElems = VT.getVectorNumElements();
17051 SDLoc dl(Op);
17053 // Extract the LHS vectors
17054 SDValue LHS = Op.getOperand(0);
17055 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17056 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17058 // Extract the RHS vectors
17059 SDValue RHS = Op.getOperand(1);
17060 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
17061 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
17063 MVT EltVT = VT.getVectorElementType();
17064 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17066 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17067 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
17068 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
17069 }
17071 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
17072 assert(Op.getSimpleValueType().is256BitVector() &&
17073 Op.getSimpleValueType().isInteger() &&
17074 "Only handle AVX 256-bit vector integer operation");
17075 return Lower256IntArith(Op, DAG);
17076 }
17078 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
17079 assert(Op.getSimpleValueType().is256BitVector() &&
17080 Op.getSimpleValueType().isInteger() &&
17081 "Only handle AVX 256-bit vector integer operation");
17082 return Lower256IntArith(Op, DAG);
17083 }
17085 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
17086 SelectionDAG &DAG) {
17087 SDLoc dl(Op);
17088 MVT VT = Op.getSimpleValueType();
17090 // Decompose 256-bit ops into smaller 128-bit ops.
17091 if (VT.is256BitVector() && !Subtarget->hasInt256())
17092 return Lower256IntArith(Op, DAG);
17094 SDValue A = Op.getOperand(0);
17095 SDValue B = Op.getOperand(1);
17097 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
17098 if (VT == MVT::v4i32) {
17099 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
17100 "Should not custom lower when pmuldq is available!");
17102 // Extract the odd parts.
17103 static const int UnpackMask[] = { 1, -1, 3, -1 };
17104 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
17105 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
17107 // Multiply the even parts.
17108 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
17109 // Now multiply odd parts.
17110 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
17112 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
17113 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
17115 // Merge the two vectors back together with a shuffle. This expands into 2
17116 // shuffles.
17117 static const int ShufMask[] = { 0, 4, 2, 6 };
17118 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
17119 }
17121 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
17122 "Only know how to lower V2I64/V4I64/V8I64 multiply");
17124 // Ahi = psrlqi(a, 32);
17125 // Bhi = psrlqi(b, 32);
17126 //
17127 // AloBlo = pmuludq(a, b);
17128 // AloBhi = pmuludq(a, Bhi);
17129 // AhiBlo = pmuludq(Ahi, b);
17131 // AloBhi = psllqi(AloBhi, 32);
17132 // AhiBlo = psllqi(AhiBlo, 32);
17133 // return AloBlo + AloBhi + AhiBlo;
17135 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
17136 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
17138 // Bit cast to 32-bit vectors for MULUDQ
17139 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
17140 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
17141 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
17142 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
17143 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
17144 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
17146 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
17147 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
17148 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
17150 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
17151 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
17153 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
17154 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
17155 }
17157 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
17158 assert(Subtarget->isTargetWin64() && "Unexpected target");
17159 EVT VT = Op.getValueType();
17160 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
17161 "Unexpected return type for lowering");
17163 RTLIB::Libcall LC;
17164 bool isSigned;
17165 switch (Op->getOpcode()) {
17166 default: llvm_unreachable("Unexpected request for libcall!");
17167 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
17168 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
17169 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
17170 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
17171 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
17172 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
17173 }
17175 SDLoc dl(Op);
17176 SDValue InChain = DAG.getEntryNode();
17178 TargetLowering::ArgListTy Args;
17179 TargetLowering::ArgListEntry Entry;
17180 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
17181 EVT ArgVT = Op->getOperand(i).getValueType();
17182 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
17183 "Unexpected argument type for lowering");
17184 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
17185 Entry.Node = StackPtr;
17186 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
17187 false, false, 16);
17188 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17189 Entry.Ty = PointerType::get(ArgTy,0);
17190 Entry.isSExt = false;
17191 Entry.isZExt = false;
17192 Args.push_back(Entry);
17193 }
17195 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
17196 getPointerTy());
17198 TargetLowering::CallLoweringInfo CLI(DAG);
17199 CLI.setDebugLoc(dl).setChain(InChain)
17200 .setCallee(getLibcallCallingConv(LC),
17201 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
17202 Callee, std::move(Args), 0)
17203 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
17205 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
17206 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
17207 }
17209 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
17210 SelectionDAG &DAG) {
17211 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
17212 EVT VT = Op0.getValueType();
17213 SDLoc dl(Op);
17215 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
17216 (VT == MVT::v8i32 && Subtarget->hasInt256()));
17218 // PMULxD operations multiply each even value (starting at 0) of LHS with
17219 // the related value of RHS and produce a widen result.
17220 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17221 // => <2 x i64> <ae|cg>
17222 //
17223 // In other word, to have all the results, we need to perform two PMULxD:
17224 // 1. one with the even values.
17225 // 2. one with the odd values.
17226 // To achieve #2, with need to place the odd values at an even position.
17227 //
17228 // Place the odd value at an even position (basically, shift all values 1
17229 // step to the left):
17230 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
17231 // <a|b|c|d> => <b|undef|d|undef>
17232 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
17233 // <e|f|g|h> => <f|undef|h|undef>
17234 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
17236 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
17237 // ints.
17238 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
17239 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
17240 unsigned Opcode =
17241 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
17242 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17243 // => <2 x i64> <ae|cg>
17244 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
17245 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
17246 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
17247 // => <2 x i64> <bf|dh>
17248 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
17249 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
17251 // Shuffle it back into the right order.
17252 SDValue Highs, Lows;
17253 if (VT == MVT::v8i32) {
17254 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
17255 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17256 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
17257 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17258 } else {
17259 const int HighMask[] = {1, 5, 3, 7};
17260 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17261 const int LowMask[] = {0, 4, 2, 6};
17262 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17263 }
17265 // If we have a signed multiply but no PMULDQ fix up the high parts of a
17266 // unsigned multiply.
17267 if (IsSigned && !Subtarget->hasSSE41()) {
17268 SDValue ShAmt =
17269 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
17270 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
17271 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
17272 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
17273 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
17275 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
17276 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
17277 }
17279 // The first result of MUL_LOHI is actually the low value, followed by the
17280 // high value.
17281 SDValue Ops[] = {Lows, Highs};
17282 return DAG.getMergeValues(Ops, dl);
17283 }
17285 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
17286 const X86Subtarget *Subtarget) {
17287 MVT VT = Op.getSimpleValueType();
17288 SDLoc dl(Op);
17289 SDValue R = Op.getOperand(0);
17290 SDValue Amt = Op.getOperand(1);
17292 // Optimize shl/srl/sra with constant shift amount.
17293 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
17294 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
17295 uint64_t ShiftAmt = ShiftConst->getZExtValue();
17297 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
17298 (Subtarget->hasInt256() &&
17299 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
17300 (Subtarget->hasAVX512() &&
17301 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
17302 if (Op.getOpcode() == ISD::SHL)
17303 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
17304 DAG);
17305 if (Op.getOpcode() == ISD::SRL)
17306 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
17307 DAG);
17308 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
17309 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
17310 DAG);
17311 }
17313 if (VT == MVT::v16i8) {
17314 if (Op.getOpcode() == ISD::SHL) {
17315 // Make a large shift.
17316 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
17317 MVT::v8i16, R, ShiftAmt,
17318 DAG);
17319 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
17320 // Zero out the rightmost bits.
17321 SmallVector<SDValue, 16> V(16,
17322 DAG.getConstant(uint8_t(-1U << ShiftAmt),
17323 MVT::i8));
17324 return DAG.getNode(ISD::AND, dl, VT, SHL,
17325 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17326 }
17327 if (Op.getOpcode() == ISD::SRL) {
17328 // Make a large shift.
17329 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
17330 MVT::v8i16, R, ShiftAmt,
17331 DAG);
17332 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
17333 // Zero out the leftmost bits.
17334 SmallVector<SDValue, 16> V(16,
17335 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
17336 MVT::i8));
17337 return DAG.getNode(ISD::AND, dl, VT, SRL,
17338 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17339 }
17340 if (Op.getOpcode() == ISD::SRA) {
17341 if (ShiftAmt == 7) {
17342 // R s>> 7 === R s< 0
17343 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
17344 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
17345 }
17347 // R s>> a === ((R u>> a) ^ m) - m
17348 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
17349 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
17350 MVT::i8));
17351 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
17352 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
17353 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
17354 return Res;
17355 }
17356 llvm_unreachable("Unknown shift opcode.");
17357 }
17359 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
17360 if (Op.getOpcode() == ISD::SHL) {
17361 // Make a large shift.
17362 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
17363 MVT::v16i16, R, ShiftAmt,
17364 DAG);
17365 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
17366 // Zero out the rightmost bits.
17367 SmallVector<SDValue, 32> V(32,
17368 DAG.getConstant(uint8_t(-1U << ShiftAmt),
17369 MVT::i8));
17370 return DAG.getNode(ISD::AND, dl, VT, SHL,
17371 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17372 }
17373 if (Op.getOpcode() == ISD::SRL) {
17374 // Make a large shift.
17375 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
17376 MVT::v16i16, R, ShiftAmt,
17377 DAG);
17378 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
17379 // Zero out the leftmost bits.
17380 SmallVector<SDValue, 32> V(32,
17381 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
17382 MVT::i8));
17383 return DAG.getNode(ISD::AND, dl, VT, SRL,
17384 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17385 }
17386 if (Op.getOpcode() == ISD::SRA) {
17387 if (ShiftAmt == 7) {
17388 // R s>> 7 === R s< 0
17389 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
17390 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
17391 }
17393 // R s>> a === ((R u>> a) ^ m) - m
17394 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
17395 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
17396 MVT::i8));
17397 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
17398 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
17399 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
17400 return Res;
17401 }
17402 llvm_unreachable("Unknown shift opcode.");
17403 }
17404 }
17405 }
17407 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17408 if (!Subtarget->is64Bit() &&
17409 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
17410 Amt.getOpcode() == ISD::BITCAST &&
17411 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
17412 Amt = Amt.getOperand(0);
17413 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17414 VT.getVectorNumElements();
17415 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
17416 uint64_t ShiftAmt = 0;
17417 for (unsigned i = 0; i != Ratio; ++i) {
17418 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
17419 if (!C)
17420 return SDValue();
17421 // 6 == Log2(64)
17422 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
17423 }
17424 // Check remaining shift amounts.
17425 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17426 uint64_t ShAmt = 0;
17427 for (unsigned j = 0; j != Ratio; ++j) {
17428 ConstantSDNode *C =
17429 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
17430 if (!C)
17431 return SDValue();
17432 // 6 == Log2(64)
17433 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
17434 }
17435 if (ShAmt != ShiftAmt)
17436 return SDValue();
17437 }
17438 switch (Op.getOpcode()) {
17439 default:
17440 llvm_unreachable("Unknown shift opcode!");
17441 case ISD::SHL:
17442 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
17443 DAG);
17444 case ISD::SRL:
17445 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
17446 DAG);
17447 case ISD::SRA:
17448 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
17449 DAG);
17450 }
17451 }
17453 return SDValue();
17454 }
17456 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
17457 const X86Subtarget* Subtarget) {
17458 MVT VT = Op.getSimpleValueType();
17459 SDLoc dl(Op);
17460 SDValue R = Op.getOperand(0);
17461 SDValue Amt = Op.getOperand(1);
17463 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
17464 VT == MVT::v4i32 || VT == MVT::v8i16 ||
17465 (Subtarget->hasInt256() &&
17466 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
17467 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
17468 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
17469 SDValue BaseShAmt;
17470 EVT EltVT = VT.getVectorElementType();
17472 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
17473 unsigned NumElts = VT.getVectorNumElements();
17474 unsigned i, j;
17475 for (i = 0; i != NumElts; ++i) {
17476 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
17477 continue;
17478 break;
17479 }
17480 for (j = i; j != NumElts; ++j) {
17481 SDValue Arg = Amt.getOperand(j);
17482 if (Arg.getOpcode() == ISD::UNDEF) continue;
17483 if (Arg != Amt.getOperand(i))
17484 break;
17485 }
17486 if (i != NumElts && j == NumElts)
17487 BaseShAmt = Amt.getOperand(i);
17488 } else {
17489 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
17490 Amt = Amt.getOperand(0);
17491 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
17492 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
17493 SDValue InVec = Amt.getOperand(0);
17494 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
17495 unsigned NumElts = InVec.getValueType().getVectorNumElements();
17496 unsigned i = 0;
17497 for (; i != NumElts; ++i) {
17498 SDValue Arg = InVec.getOperand(i);
17499 if (Arg.getOpcode() == ISD::UNDEF) continue;
17500 BaseShAmt = Arg;
17501 break;
17502 }
17503 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
17504 if (ConstantSDNode *C =
17505 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
17506 unsigned SplatIdx =
17507 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
17508 if (C->getZExtValue() == SplatIdx)
17509 BaseShAmt = InVec.getOperand(1);
17510 }
17511 }
17512 if (!BaseShAmt.getNode())
17513 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
17514 DAG.getIntPtrConstant(0));
17515 }
17516 }
17518 if (BaseShAmt.getNode()) {
17519 if (EltVT.bitsGT(MVT::i32))
17520 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
17521 else if (EltVT.bitsLT(MVT::i32))
17522 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
17524 switch (Op.getOpcode()) {
17525 default:
17526 llvm_unreachable("Unknown shift opcode!");
17527 case ISD::SHL:
17528 switch (VT.SimpleTy) {
17529 default: return SDValue();
17530 case MVT::v2i64:
17531 case MVT::v4i32:
17532 case MVT::v8i16:
17533 case MVT::v4i64:
17534 case MVT::v8i32:
17535 case MVT::v16i16:
17536 case MVT::v16i32:
17537 case MVT::v8i64:
17538 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
17539 }
17540 case ISD::SRA:
17541 switch (VT.SimpleTy) {
17542 default: return SDValue();
17543 case MVT::v4i32:
17544 case MVT::v8i16:
17545 case MVT::v8i32:
17546 case MVT::v16i16:
17547 case MVT::v16i32:
17548 case MVT::v8i64:
17549 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
17550 }
17551 case ISD::SRL:
17552 switch (VT.SimpleTy) {
17553 default: return SDValue();
17554 case MVT::v2i64:
17555 case MVT::v4i32:
17556 case MVT::v8i16:
17557 case MVT::v4i64:
17558 case MVT::v8i32:
17559 case MVT::v16i16:
17560 case MVT::v16i32:
17561 case MVT::v8i64:
17562 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
17563 }
17564 }
17565 }
17566 }
17568 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17569 if (!Subtarget->is64Bit() &&
17570 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
17571 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
17572 Amt.getOpcode() == ISD::BITCAST &&
17573 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
17574 Amt = Amt.getOperand(0);
17575 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17576 VT.getVectorNumElements();
17577 std::vector<SDValue> Vals(Ratio);
17578 for (unsigned i = 0; i != Ratio; ++i)
17579 Vals[i] = Amt.getOperand(i);
17580 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17581 for (unsigned j = 0; j != Ratio; ++j)
17582 if (Vals[j] != Amt.getOperand(i + j))
17583 return SDValue();
17584 }
17585 switch (Op.getOpcode()) {
17586 default:
17587 llvm_unreachable("Unknown shift opcode!");
17588 case ISD::SHL:
17589 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
17590 case ISD::SRL:
17591 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
17592 case ISD::SRA:
17593 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
17594 }
17595 }
17597 return SDValue();
17598 }
17600 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
17601 SelectionDAG &DAG) {
17602 MVT VT = Op.getSimpleValueType();
17603 SDLoc dl(Op);
17604 SDValue R = Op.getOperand(0);
17605 SDValue Amt = Op.getOperand(1);
17606 SDValue V;
17608 assert(VT.isVector() && "Custom lowering only for vector shifts!");
17609 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
17611 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
17612 if (V.getNode())
17613 return V;
17615 V = LowerScalarVariableShift(Op, DAG, Subtarget);
17616 if (V.getNode())
17617 return V;
17619 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
17620 return Op;
17621 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
17622 if (Subtarget->hasInt256()) {
17623 if (Op.getOpcode() == ISD::SRL &&
17624 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
17625 VT == MVT::v4i64 || VT == MVT::v8i32))
17626 return Op;
17627 if (Op.getOpcode() == ISD::SHL &&
17628 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
17629 VT == MVT::v4i64 || VT == MVT::v8i32))
17630 return Op;
17631 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
17632 return Op;
17633 }
17635 // If possible, lower this packed shift into a vector multiply instead of
17636 // expanding it into a sequence of scalar shifts.
17637 // Do this only if the vector shift count is a constant build_vector.
17638 if (Op.getOpcode() == ISD::SHL &&
17639 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
17640 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
17641 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17642 SmallVector<SDValue, 8> Elts;
17643 EVT SVT = VT.getScalarType();
17644 unsigned SVTBits = SVT.getSizeInBits();
17645 const APInt &One = APInt(SVTBits, 1);
17646 unsigned NumElems = VT.getVectorNumElements();
17648 for (unsigned i=0; i !=NumElems; ++i) {
17649 SDValue Op = Amt->getOperand(i);
17650 if (Op->getOpcode() == ISD::UNDEF) {
17651 Elts.push_back(Op);
17652 continue;
17653 }
17655 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
17656 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
17657 uint64_t ShAmt = C.getZExtValue();
17658 if (ShAmt >= SVTBits) {
17659 Elts.push_back(DAG.getUNDEF(SVT));
17660 continue;
17661 }
17662 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
17663 }
17664 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
17665 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
17666 }
17668 // Lower SHL with variable shift amount.
17669 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
17670 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
17672 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
17673 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
17674 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
17675 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
17676 }
17678 // If possible, lower this shift as a sequence of two shifts by
17679 // constant plus a MOVSS/MOVSD instead of scalarizing it.
17680 // Example:
17681 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
17682 //
17683 // Could be rewritten as:
17684 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
17685 //
17686 // The advantage is that the two shifts from the example would be
17687 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
17688 // the vector shift into four scalar shifts plus four pairs of vector
17689 // insert/extract.
17690 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
17691 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17692 unsigned TargetOpcode = X86ISD::MOVSS;
17693 bool CanBeSimplified;
17694 // The splat value for the first packed shift (the 'X' from the example).
17695 SDValue Amt1 = Amt->getOperand(0);
17696 // The splat value for the second packed shift (the 'Y' from the example).
17697 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
17698 Amt->getOperand(2);
17700 // See if it is possible to replace this node with a sequence of
17701 // two shifts followed by a MOVSS/MOVSD
17702 if (VT == MVT::v4i32) {
17703 // Check if it is legal to use a MOVSS.
17704 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
17705 Amt2 == Amt->getOperand(3);
17706 if (!CanBeSimplified) {
17707 // Otherwise, check if we can still simplify this node using a MOVSD.
17708 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
17709 Amt->getOperand(2) == Amt->getOperand(3);
17710 TargetOpcode = X86ISD::MOVSD;
17711 Amt2 = Amt->getOperand(2);
17712 }
17713 } else {
17714 // Do similar checks for the case where the machine value type
17715 // is MVT::v8i16.
17716 CanBeSimplified = Amt1 == Amt->getOperand(1);
17717 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
17718 CanBeSimplified = Amt2 == Amt->getOperand(i);
17720 if (!CanBeSimplified) {
17721 TargetOpcode = X86ISD::MOVSD;
17722 CanBeSimplified = true;
17723 Amt2 = Amt->getOperand(4);
17724 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
17725 CanBeSimplified = Amt1 == Amt->getOperand(i);
17726 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
17727 CanBeSimplified = Amt2 == Amt->getOperand(j);
17728 }
17729 }
17731 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
17732 isa<ConstantSDNode>(Amt2)) {
17733 // Replace this node with two shifts followed by a MOVSS/MOVSD.
17734 EVT CastVT = MVT::v4i32;
17735 SDValue Splat1 =
17736 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
17737 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
17738 SDValue Splat2 =
17739 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
17740 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
17741 if (TargetOpcode == X86ISD::MOVSD)
17742 CastVT = MVT::v2i64;
17743 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
17744 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
17745 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
17746 BitCast1, DAG);
17747 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
17748 }
17749 }
17751 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
17752 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
17754 // a = a << 5;
17755 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
17756 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
17758 // Turn 'a' into a mask suitable for VSELECT
17759 SDValue VSelM = DAG.getConstant(0x80, VT);
17760 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17761 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17763 SDValue CM1 = DAG.getConstant(0x0f, VT);
17764 SDValue CM2 = DAG.getConstant(0x3f, VT);
17766 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
17767 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
17768 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
17769 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
17770 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
17772 // a += a
17773 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
17774 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17775 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17777 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
17778 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
17779 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
17780 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
17781 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
17783 // a += a
17784 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
17785 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17786 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17788 // return VSELECT(r, r+r, a);
17789 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
17790 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
17791 return R;
17792 }
17794 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
17795 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
17796 // solution better.
17797 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
17798 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
17799 unsigned ExtOpc =
17800 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
17801 R = DAG.getNode(ExtOpc, dl, NewVT, R);
17802 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
17803 return DAG.getNode(ISD::TRUNCATE, dl, VT,
17804 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
17805 }
17807 // Decompose 256-bit shifts into smaller 128-bit shifts.
17808 if (VT.is256BitVector()) {
17809 unsigned NumElems = VT.getVectorNumElements();
17810 MVT EltVT = VT.getVectorElementType();
17811 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17813 // Extract the two vectors
17814 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
17815 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
17817 // Recreate the shift amount vectors
17818 SDValue Amt1, Amt2;
17819 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
17820 // Constant shift amount
17821 SmallVector<SDValue, 4> Amt1Csts;
17822 SmallVector<SDValue, 4> Amt2Csts;
17823 for (unsigned i = 0; i != NumElems/2; ++i)
17824 Amt1Csts.push_back(Amt->getOperand(i));
17825 for (unsigned i = NumElems/2; i != NumElems; ++i)
17826 Amt2Csts.push_back(Amt->getOperand(i));
17828 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
17829 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
17830 } else {
17831 // Variable shift amount
17832 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
17833 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
17834 }
17836 // Issue new vector shifts for the smaller types
17837 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
17838 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
17840 // Concatenate the result back
17841 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
17842 }
17844 return SDValue();
17845 }
17847 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
17848 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
17849 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
17850 // looks for this combo and may remove the "setcc" instruction if the "setcc"
17851 // has only one use.
17852 SDNode *N = Op.getNode();
17853 SDValue LHS = N->getOperand(0);
17854 SDValue RHS = N->getOperand(1);
17855 unsigned BaseOp = 0;
17856 unsigned Cond = 0;
17857 SDLoc DL(Op);
17858 switch (Op.getOpcode()) {
17859 default: llvm_unreachable("Unknown ovf instruction!");
17860 case ISD::SADDO:
17861 // A subtract of one will be selected as a INC. Note that INC doesn't
17862 // set CF, so we can't do this for UADDO.
17863 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17864 if (C->isOne()) {
17865 BaseOp = X86ISD::INC;
17866 Cond = X86::COND_O;
17867 break;
17868 }
17869 BaseOp = X86ISD::ADD;
17870 Cond = X86::COND_O;
17871 break;
17872 case ISD::UADDO:
17873 BaseOp = X86ISD::ADD;
17874 Cond = X86::COND_B;
17875 break;
17876 case ISD::SSUBO:
17877 // A subtract of one will be selected as a DEC. Note that DEC doesn't
17878 // set CF, so we can't do this for USUBO.
17879 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17880 if (C->isOne()) {
17881 BaseOp = X86ISD::DEC;
17882 Cond = X86::COND_O;
17883 break;
17884 }
17885 BaseOp = X86ISD::SUB;
17886 Cond = X86::COND_O;
17887 break;
17888 case ISD::USUBO:
17889 BaseOp = X86ISD::SUB;
17890 Cond = X86::COND_B;
17891 break;
17892 case ISD::SMULO:
17893 BaseOp = X86ISD::SMUL;
17894 Cond = X86::COND_O;
17895 break;
17896 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
17897 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
17898 MVT::i32);
17899 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
17901 SDValue SetCC =
17902 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17903 DAG.getConstant(X86::COND_O, MVT::i32),
17904 SDValue(Sum.getNode(), 2));
17906 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17907 }
17908 }
17910 // Also sets EFLAGS.
17911 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
17912 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
17914 SDValue SetCC =
17915 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
17916 DAG.getConstant(Cond, MVT::i32),
17917 SDValue(Sum.getNode(), 1));
17919 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17920 }
17922 // Sign extension of the low part of vector elements. This may be used either
17923 // when sign extend instructions are not available or if the vector element
17924 // sizes already match the sign-extended size. If the vector elements are in
17925 // their pre-extended size and sign extend instructions are available, that will
17926 // be handled by LowerSIGN_EXTEND.
17927 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
17928 SelectionDAG &DAG) const {
17929 SDLoc dl(Op);
17930 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
17931 MVT VT = Op.getSimpleValueType();
17933 if (!Subtarget->hasSSE2() || !VT.isVector())
17934 return SDValue();
17936 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
17937 ExtraVT.getScalarType().getSizeInBits();
17939 switch (VT.SimpleTy) {
17940 default: return SDValue();
17941 case MVT::v8i32:
17942 case MVT::v16i16:
17943 if (!Subtarget->hasFp256())
17944 return SDValue();
17945 if (!Subtarget->hasInt256()) {
17946 // needs to be split
17947 unsigned NumElems = VT.getVectorNumElements();
17949 // Extract the LHS vectors
17950 SDValue LHS = Op.getOperand(0);
17951 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17952 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17954 MVT EltVT = VT.getVectorElementType();
17955 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17957 EVT ExtraEltVT = ExtraVT.getVectorElementType();
17958 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
17959 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
17960 ExtraNumElems/2);
17961 SDValue Extra = DAG.getValueType(ExtraVT);
17963 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
17964 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
17966 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
17967 }
17968 // fall through
17969 case MVT::v4i32:
17970 case MVT::v8i16: {
17971 SDValue Op0 = Op.getOperand(0);
17973 // This is a sign extension of some low part of vector elements without
17974 // changing the size of the vector elements themselves:
17975 // Shift-Left + Shift-Right-Algebraic.
17976 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
17977 BitsDiff, DAG);
17978 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
17979 DAG);
17980 }
17981 }
17982 }
17984 /// Returns true if the operand type is exactly twice the native width, and
17985 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
17986 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
17987 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
17988 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
17989 const X86Subtarget &Subtarget =
17990 getTargetMachine().getSubtarget<X86Subtarget>();
17991 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
17993 if (OpWidth == 64)
17994 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
17995 else if (OpWidth == 128)
17996 return Subtarget.hasCmpxchg16b();
17997 else
17998 return false;
17999 }
18001 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18002 return needsCmpXchgNb(SI->getValueOperand()->getType());
18003 }
18005 // Note: this turns large loads into lock cmpxchg8b/16b.
18006 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18007 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18008 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18009 return needsCmpXchgNb(PTy->getElementType());
18010 }
18012 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
18013 const X86Subtarget &Subtarget =
18014 getTargetMachine().getSubtarget<X86Subtarget>();
18015 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18016 const Type *MemType = AI->getType();
18018 // If the operand is too big, we must see if cmpxchg8/16b is available
18019 // and default to library calls otherwise.
18020 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18021 return needsCmpXchgNb(MemType);
18023 AtomicRMWInst::BinOp Op = AI->getOperation();
18024 switch (Op) {
18025 default:
18026 llvm_unreachable("Unknown atomic operation");
18027 case AtomicRMWInst::Xchg:
18028 case AtomicRMWInst::Add:
18029 case AtomicRMWInst::Sub:
18030 // It's better to use xadd, xsub or xchg for these in all cases.
18031 return false;
18032 case AtomicRMWInst::Or:
18033 case AtomicRMWInst::And:
18034 case AtomicRMWInst::Xor:
18035 // If the atomicrmw's result isn't actually used, we can just add a "lock"
18036 // prefix to a normal instruction for these operations.
18037 return !AI->use_empty();
18038 case AtomicRMWInst::Nand:
18039 case AtomicRMWInst::Max:
18040 case AtomicRMWInst::Min:
18041 case AtomicRMWInst::UMax:
18042 case AtomicRMWInst::UMin:
18043 // These always require a non-trivial set of data operations on x86. We must
18044 // use a cmpxchg loop.
18045 return true;
18046 }
18047 }
18049 static bool hasMFENCE(const X86Subtarget& Subtarget) {
18050 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
18051 // no-sse2). There isn't any reason to disable it if the target processor
18052 // supports it.
18053 return Subtarget.hasSSE2() || Subtarget.is64Bit();
18054 }
18056 LoadInst *
18057 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
18058 const X86Subtarget &Subtarget =
18059 getTargetMachine().getSubtarget<X86Subtarget>();
18060 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18061 const Type *MemType = AI->getType();
18062 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
18063 // there is no benefit in turning such RMWs into loads, and it is actually
18064 // harmful as it introduces a mfence.
18065 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18066 return nullptr;
18068 auto Builder = IRBuilder<>(AI);
18069 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
18070 auto SynchScope = AI->getSynchScope();
18071 // We must restrict the ordering to avoid generating loads with Release or
18072 // ReleaseAcquire orderings.
18073 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
18074 auto Ptr = AI->getPointerOperand();
18076 // Before the load we need a fence. Here is an example lifted from
18077 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
18078 // is required:
18079 // Thread 0:
18080 // x.store(1, relaxed);
18081 // r1 = y.fetch_add(0, release);
18082 // Thread 1:
18083 // y.fetch_add(42, acquire);
18084 // r2 = x.load(relaxed);
18085 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
18086 // lowered to just a load without a fence. A mfence flushes the store buffer,
18087 // making the optimization clearly correct.
18088 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
18089 // otherwise, we might be able to be more agressive on relaxed idempotent
18090 // rmw. In practice, they do not look useful, so we don't try to be
18091 // especially clever.
18092 if (SynchScope == SingleThread) {
18093 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
18094 // the IR level, so we must wrap it in an intrinsic.
18095 return nullptr;
18096 } else if (hasMFENCE(Subtarget)) {
18097 Function *MFence = llvm::Intrinsic::getDeclaration(M,
18098 Intrinsic::x86_sse2_mfence);
18099 Builder.CreateCall(MFence);
18100 } else {
18101 // FIXME: it might make sense to use a locked operation here but on a
18102 // different cache-line to prevent cache-line bouncing. In practice it
18103 // is probably a small win, and x86 processors without mfence are rare
18104 // enough that we do not bother.
18105 return nullptr;
18106 }
18108 // Finally we can emit the atomic load.
18109 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
18110 AI->getType()->getPrimitiveSizeInBits());
18111 Loaded->setAtomic(Order, SynchScope);
18112 AI->replaceAllUsesWith(Loaded);
18113 AI->eraseFromParent();
18114 return Loaded;
18115 }
18117 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
18118 SelectionDAG &DAG) {
18119 SDLoc dl(Op);
18120 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
18121 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
18122 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
18123 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
18125 // The only fence that needs an instruction is a sequentially-consistent
18126 // cross-thread fence.
18127 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
18128 if (hasMFENCE(*Subtarget))
18129 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
18131 SDValue Chain = Op.getOperand(0);
18132 SDValue Zero = DAG.getConstant(0, MVT::i32);
18133 SDValue Ops[] = {
18134 DAG.getRegister(X86::ESP, MVT::i32), // Base
18135 DAG.getTargetConstant(1, MVT::i8), // Scale
18136 DAG.getRegister(0, MVT::i32), // Index
18137 DAG.getTargetConstant(0, MVT::i32), // Disp
18138 DAG.getRegister(0, MVT::i32), // Segment.
18139 Zero,
18140 Chain
18141 };
18142 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
18143 return SDValue(Res, 0);
18144 }
18146 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
18147 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
18148 }
18150 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
18151 SelectionDAG &DAG) {
18152 MVT T = Op.getSimpleValueType();
18153 SDLoc DL(Op);
18154 unsigned Reg = 0;
18155 unsigned size = 0;
18156 switch(T.SimpleTy) {
18157 default: llvm_unreachable("Invalid value type!");
18158 case MVT::i8: Reg = X86::AL; size = 1; break;
18159 case MVT::i16: Reg = X86::AX; size = 2; break;
18160 case MVT::i32: Reg = X86::EAX; size = 4; break;
18161 case MVT::i64:
18162 assert(Subtarget->is64Bit() && "Node not type legal!");
18163 Reg = X86::RAX; size = 8;
18164 break;
18165 }
18166 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
18167 Op.getOperand(2), SDValue());
18168 SDValue Ops[] = { cpIn.getValue(0),
18169 Op.getOperand(1),
18170 Op.getOperand(3),
18171 DAG.getTargetConstant(size, MVT::i8),
18172 cpIn.getValue(1) };
18173 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18174 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
18175 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
18176 Ops, T, MMO);
18178 SDValue cpOut =
18179 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
18180 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
18181 MVT::i32, cpOut.getValue(2));
18182 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
18183 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
18185 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
18186 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
18187 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
18188 return SDValue();
18189 }
18191 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
18192 SelectionDAG &DAG) {
18193 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
18194 MVT DstVT = Op.getSimpleValueType();
18196 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
18197 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18198 if (DstVT != MVT::f64)
18199 // This conversion needs to be expanded.
18200 return SDValue();
18202 SDValue InVec = Op->getOperand(0);
18203 SDLoc dl(Op);
18204 unsigned NumElts = SrcVT.getVectorNumElements();
18205 EVT SVT = SrcVT.getVectorElementType();
18207 // Widen the vector in input in the case of MVT::v2i32.
18208 // Example: from MVT::v2i32 to MVT::v4i32.
18209 SmallVector<SDValue, 16> Elts;
18210 for (unsigned i = 0, e = NumElts; i != e; ++i)
18211 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
18212 DAG.getIntPtrConstant(i)));
18214 // Explicitly mark the extra elements as Undef.
18215 SDValue Undef = DAG.getUNDEF(SVT);
18216 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
18217 Elts.push_back(Undef);
18219 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18220 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
18221 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
18222 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
18223 DAG.getIntPtrConstant(0));
18224 }
18226 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
18227 Subtarget->hasMMX() && "Unexpected custom BITCAST");
18228 assert((DstVT == MVT::i64 ||
18229 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
18230 "Unexpected custom BITCAST");
18231 // i64 <=> MMX conversions are Legal.
18232 if (SrcVT==MVT::i64 && DstVT.isVector())
18233 return Op;
18234 if (DstVT==MVT::i64 && SrcVT.isVector())
18235 return Op;
18236 // MMX <=> MMX conversions are Legal.
18237 if (SrcVT.isVector() && DstVT.isVector())
18238 return Op;
18239 // All other conversions need to be expanded.
18240 return SDValue();
18241 }
18243 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
18244 SDNode *Node = Op.getNode();
18245 SDLoc dl(Node);
18246 EVT T = Node->getValueType(0);
18247 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
18248 DAG.getConstant(0, T), Node->getOperand(2));
18249 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
18250 cast<AtomicSDNode>(Node)->getMemoryVT(),
18251 Node->getOperand(0),
18252 Node->getOperand(1), negOp,
18253 cast<AtomicSDNode>(Node)->getMemOperand(),
18254 cast<AtomicSDNode>(Node)->getOrdering(),
18255 cast<AtomicSDNode>(Node)->getSynchScope());
18256 }
18258 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
18259 SDNode *Node = Op.getNode();
18260 SDLoc dl(Node);
18261 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
18263 // Convert seq_cst store -> xchg
18264 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
18265 // FIXME: On 32-bit, store -> fist or movq would be more efficient
18266 // (The only way to get a 16-byte store is cmpxchg16b)
18267 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
18268 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
18269 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
18270 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
18271 cast<AtomicSDNode>(Node)->getMemoryVT(),
18272 Node->getOperand(0),
18273 Node->getOperand(1), Node->getOperand(2),
18274 cast<AtomicSDNode>(Node)->getMemOperand(),
18275 cast<AtomicSDNode>(Node)->getOrdering(),
18276 cast<AtomicSDNode>(Node)->getSynchScope());
18277 return Swap.getValue(1);
18278 }
18279 // Other atomic stores have a simple pattern.
18280 return Op;
18281 }
18283 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
18284 EVT VT = Op.getNode()->getSimpleValueType(0);
18286 // Let legalize expand this if it isn't a legal type yet.
18287 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
18288 return SDValue();
18290 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
18292 unsigned Opc;
18293 bool ExtraOp = false;
18294 switch (Op.getOpcode()) {
18295 default: llvm_unreachable("Invalid code");
18296 case ISD::ADDC: Opc = X86ISD::ADD; break;
18297 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
18298 case ISD::SUBC: Opc = X86ISD::SUB; break;
18299 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
18300 }
18302 if (!ExtraOp)
18303 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
18304 Op.getOperand(1));
18305 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
18306 Op.getOperand(1), Op.getOperand(2));
18307 }
18309 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
18310 SelectionDAG &DAG) {
18311 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
18313 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
18314 // which returns the values as { float, float } (in XMM0) or
18315 // { double, double } (which is returned in XMM0, XMM1).
18316 SDLoc dl(Op);
18317 SDValue Arg = Op.getOperand(0);
18318 EVT ArgVT = Arg.getValueType();
18319 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18321 TargetLowering::ArgListTy Args;
18322 TargetLowering::ArgListEntry Entry;
18324 Entry.Node = Arg;
18325 Entry.Ty = ArgTy;
18326 Entry.isSExt = false;
18327 Entry.isZExt = false;
18328 Args.push_back(Entry);
18330 bool isF64 = ArgVT == MVT::f64;
18331 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
18332 // the small struct {f32, f32} is returned in (eax, edx). For f64,
18333 // the results are returned via SRet in memory.
18334 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
18335 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18336 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
18338 Type *RetTy = isF64
18339 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
18340 : (Type*)VectorType::get(ArgTy, 4);
18342 TargetLowering::CallLoweringInfo CLI(DAG);
18343 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
18344 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
18346 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
18348 if (isF64)
18349 // Returned in xmm0 and xmm1.
18350 return CallResult.first;
18352 // Returned in bits 0:31 and 32:64 xmm0.
18353 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
18354 CallResult.first, DAG.getIntPtrConstant(0));
18355 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
18356 CallResult.first, DAG.getIntPtrConstant(1));
18357 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
18358 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
18359 }
18361 /// LowerOperation - Provide custom lowering hooks for some operations.
18362 ///
18363 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
18364 switch (Op.getOpcode()) {
18365 default: llvm_unreachable("Should not custom lower this!");
18366 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
18367 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
18368 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
18369 return LowerCMP_SWAP(Op, Subtarget, DAG);
18370 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
18371 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
18372 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
18373 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
18374 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
18375 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
18376 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
18377 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
18378 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
18379 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
18380 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
18381 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
18382 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
18383 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
18384 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
18385 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
18386 case ISD::SHL_PARTS:
18387 case ISD::SRA_PARTS:
18388 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
18389 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
18390 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
18391 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
18392 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
18393 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
18394 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
18395 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
18396 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
18397 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
18398 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
18399 case ISD::FABS:
18400 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
18401 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
18402 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
18403 case ISD::SETCC: return LowerSETCC(Op, DAG);
18404 case ISD::SELECT: return LowerSELECT(Op, DAG);
18405 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
18406 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
18407 case ISD::VASTART: return LowerVASTART(Op, DAG);
18408 case ISD::VAARG: return LowerVAARG(Op, DAG);
18409 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
18410 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
18411 case ISD::INTRINSIC_VOID:
18412 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
18413 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
18414 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
18415 case ISD::FRAME_TO_ARGS_OFFSET:
18416 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
18417 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
18418 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
18419 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
18420 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
18421 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
18422 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
18423 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
18424 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
18425 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
18426 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
18427 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
18428 case ISD::UMUL_LOHI:
18429 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
18430 case ISD::SRA:
18431 case ISD::SRL:
18432 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
18433 case ISD::SADDO:
18434 case ISD::UADDO:
18435 case ISD::SSUBO:
18436 case ISD::USUBO:
18437 case ISD::SMULO:
18438 case ISD::UMULO: return LowerXALUO(Op, DAG);
18439 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
18440 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
18441 case ISD::ADDC:
18442 case ISD::ADDE:
18443 case ISD::SUBC:
18444 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
18445 case ISD::ADD: return LowerADD(Op, DAG);
18446 case ISD::SUB: return LowerSUB(Op, DAG);
18447 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
18448 }
18449 }
18451 /// ReplaceNodeResults - Replace a node with an illegal result type
18452 /// with a new node built out of custom code.
18453 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
18454 SmallVectorImpl<SDValue>&Results,
18455 SelectionDAG &DAG) const {
18456 SDLoc dl(N);
18457 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18458 switch (N->getOpcode()) {
18459 default:
18460 llvm_unreachable("Do not know how to custom type legalize this operation!");
18461 case ISD::SIGN_EXTEND_INREG:
18462 case ISD::ADDC:
18463 case ISD::ADDE:
18464 case ISD::SUBC:
18465 case ISD::SUBE:
18466 // We don't want to expand or promote these.
18467 return;
18468 case ISD::SDIV:
18469 case ISD::UDIV:
18470 case ISD::SREM:
18471 case ISD::UREM:
18472 case ISD::SDIVREM:
18473 case ISD::UDIVREM: {
18474 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
18475 Results.push_back(V);
18476 return;
18477 }
18478 case ISD::FP_TO_SINT:
18479 case ISD::FP_TO_UINT: {
18480 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
18482 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
18483 return;
18485 std::pair<SDValue,SDValue> Vals =
18486 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
18487 SDValue FIST = Vals.first, StackSlot = Vals.second;
18488 if (FIST.getNode()) {
18489 EVT VT = N->getValueType(0);
18490 // Return a load from the stack slot.
18491 if (StackSlot.getNode())
18492 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
18493 MachinePointerInfo(),
18494 false, false, false, 0));
18495 else
18496 Results.push_back(FIST);
18497 }
18498 return;
18499 }
18500 case ISD::UINT_TO_FP: {
18501 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18502 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
18503 N->getValueType(0) != MVT::v2f32)
18504 return;
18505 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
18506 N->getOperand(0));
18507 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
18508 MVT::f64);
18509 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
18510 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
18511 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
18512 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
18513 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
18514 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
18515 return;
18516 }
18517 case ISD::FP_ROUND: {
18518 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
18519 return;
18520 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
18521 Results.push_back(V);
18522 return;
18523 }
18524 case ISD::INTRINSIC_W_CHAIN: {
18525 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
18526 switch (IntNo) {
18527 default : llvm_unreachable("Do not know how to custom type "
18528 "legalize this intrinsic operation!");
18529 case Intrinsic::x86_rdtsc:
18530 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18531 Results);
18532 case Intrinsic::x86_rdtscp:
18533 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
18534 Results);
18535 case Intrinsic::x86_rdpmc:
18536 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
18537 }
18538 }
18539 case ISD::READCYCLECOUNTER: {
18540 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18541 Results);
18542 }
18543 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
18544 EVT T = N->getValueType(0);
18545 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
18546 bool Regs64bit = T == MVT::i128;
18547 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
18548 SDValue cpInL, cpInH;
18549 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18550 DAG.getConstant(0, HalfT));
18551 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18552 DAG.getConstant(1, HalfT));
18553 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
18554 Regs64bit ? X86::RAX : X86::EAX,
18555 cpInL, SDValue());
18556 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
18557 Regs64bit ? X86::RDX : X86::EDX,
18558 cpInH, cpInL.getValue(1));
18559 SDValue swapInL, swapInH;
18560 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18561 DAG.getConstant(0, HalfT));
18562 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18563 DAG.getConstant(1, HalfT));
18564 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
18565 Regs64bit ? X86::RBX : X86::EBX,
18566 swapInL, cpInH.getValue(1));
18567 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
18568 Regs64bit ? X86::RCX : X86::ECX,
18569 swapInH, swapInL.getValue(1));
18570 SDValue Ops[] = { swapInH.getValue(0),
18571 N->getOperand(1),
18572 swapInH.getValue(1) };
18573 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18574 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
18575 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
18576 X86ISD::LCMPXCHG8_DAG;
18577 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
18578 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
18579 Regs64bit ? X86::RAX : X86::EAX,
18580 HalfT, Result.getValue(1));
18581 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
18582 Regs64bit ? X86::RDX : X86::EDX,
18583 HalfT, cpOutL.getValue(2));
18584 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
18586 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
18587 MVT::i32, cpOutH.getValue(2));
18588 SDValue Success =
18589 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
18590 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
18591 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
18593 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
18594 Results.push_back(Success);
18595 Results.push_back(EFLAGS.getValue(1));
18596 return;
18597 }
18598 case ISD::ATOMIC_SWAP:
18599 case ISD::ATOMIC_LOAD_ADD:
18600 case ISD::ATOMIC_LOAD_SUB:
18601 case ISD::ATOMIC_LOAD_AND:
18602 case ISD::ATOMIC_LOAD_OR:
18603 case ISD::ATOMIC_LOAD_XOR:
18604 case ISD::ATOMIC_LOAD_NAND:
18605 case ISD::ATOMIC_LOAD_MIN:
18606 case ISD::ATOMIC_LOAD_MAX:
18607 case ISD::ATOMIC_LOAD_UMIN:
18608 case ISD::ATOMIC_LOAD_UMAX:
18609 case ISD::ATOMIC_LOAD: {
18610 // Delegate to generic TypeLegalization. Situations we can really handle
18611 // should have already been dealt with by AtomicExpandPass.cpp.
18612 break;
18613 }
18614 case ISD::BITCAST: {
18615 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18616 EVT DstVT = N->getValueType(0);
18617 EVT SrcVT = N->getOperand(0)->getValueType(0);
18619 if (SrcVT != MVT::f64 ||
18620 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
18621 return;
18623 unsigned NumElts = DstVT.getVectorNumElements();
18624 EVT SVT = DstVT.getVectorElementType();
18625 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18626 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
18627 MVT::v2f64, N->getOperand(0));
18628 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
18630 if (ExperimentalVectorWideningLegalization) {
18631 // If we are legalizing vectors by widening, we already have the desired
18632 // legal vector type, just return it.
18633 Results.push_back(ToVecInt);
18634 return;
18635 }
18637 SmallVector<SDValue, 8> Elts;
18638 for (unsigned i = 0, e = NumElts; i != e; ++i)
18639 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
18640 ToVecInt, DAG.getIntPtrConstant(i)));
18642 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
18643 }
18644 }
18645 }
18647 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
18648 switch (Opcode) {
18649 default: return nullptr;
18650 case X86ISD::BSF: return "X86ISD::BSF";
18651 case X86ISD::BSR: return "X86ISD::BSR";
18652 case X86ISD::SHLD: return "X86ISD::SHLD";
18653 case X86ISD::SHRD: return "X86ISD::SHRD";
18654 case X86ISD::FAND: return "X86ISD::FAND";
18655 case X86ISD::FANDN: return "X86ISD::FANDN";
18656 case X86ISD::FOR: return "X86ISD::FOR";
18657 case X86ISD::FXOR: return "X86ISD::FXOR";
18658 case X86ISD::FSRL: return "X86ISD::FSRL";
18659 case X86ISD::FILD: return "X86ISD::FILD";
18660 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
18661 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
18662 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
18663 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
18664 case X86ISD::FLD: return "X86ISD::FLD";
18665 case X86ISD::FST: return "X86ISD::FST";
18666 case X86ISD::CALL: return "X86ISD::CALL";
18667 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
18668 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
18669 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
18670 case X86ISD::BT: return "X86ISD::BT";
18671 case X86ISD::CMP: return "X86ISD::CMP";
18672 case X86ISD::COMI: return "X86ISD::COMI";
18673 case X86ISD::UCOMI: return "X86ISD::UCOMI";
18674 case X86ISD::CMPM: return "X86ISD::CMPM";
18675 case X86ISD::CMPMU: return "X86ISD::CMPMU";
18676 case X86ISD::SETCC: return "X86ISD::SETCC";
18677 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
18678 case X86ISD::FSETCC: return "X86ISD::FSETCC";
18679 case X86ISD::CMOV: return "X86ISD::CMOV";
18680 case X86ISD::BRCOND: return "X86ISD::BRCOND";
18681 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
18682 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
18683 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
18684 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
18685 case X86ISD::Wrapper: return "X86ISD::Wrapper";
18686 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
18687 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
18688 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
18689 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
18690 case X86ISD::PINSRB: return "X86ISD::PINSRB";
18691 case X86ISD::PINSRW: return "X86ISD::PINSRW";
18692 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
18693 case X86ISD::ANDNP: return "X86ISD::ANDNP";
18694 case X86ISD::PSIGN: return "X86ISD::PSIGN";
18695 case X86ISD::BLENDI: return "X86ISD::BLENDI";
18696 case X86ISD::SUBUS: return "X86ISD::SUBUS";
18697 case X86ISD::HADD: return "X86ISD::HADD";
18698 case X86ISD::HSUB: return "X86ISD::HSUB";
18699 case X86ISD::FHADD: return "X86ISD::FHADD";
18700 case X86ISD::FHSUB: return "X86ISD::FHSUB";
18701 case X86ISD::UMAX: return "X86ISD::UMAX";
18702 case X86ISD::UMIN: return "X86ISD::UMIN";
18703 case X86ISD::SMAX: return "X86ISD::SMAX";
18704 case X86ISD::SMIN: return "X86ISD::SMIN";
18705 case X86ISD::FMAX: return "X86ISD::FMAX";
18706 case X86ISD::FMIN: return "X86ISD::FMIN";
18707 case X86ISD::FMAXC: return "X86ISD::FMAXC";
18708 case X86ISD::FMINC: return "X86ISD::FMINC";
18709 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
18710 case X86ISD::FRCP: return "X86ISD::FRCP";
18711 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
18712 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
18713 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
18714 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
18715 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
18716 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
18717 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
18718 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
18719 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
18720 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
18721 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
18722 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
18723 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
18724 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
18725 case X86ISD::VZEXT: return "X86ISD::VZEXT";
18726 case X86ISD::VSEXT: return "X86ISD::VSEXT";
18727 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
18728 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
18729 case X86ISD::VINSERT: return "X86ISD::VINSERT";
18730 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
18731 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
18732 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
18733 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
18734 case X86ISD::VSHL: return "X86ISD::VSHL";
18735 case X86ISD::VSRL: return "X86ISD::VSRL";
18736 case X86ISD::VSRA: return "X86ISD::VSRA";
18737 case X86ISD::VSHLI: return "X86ISD::VSHLI";
18738 case X86ISD::VSRLI: return "X86ISD::VSRLI";
18739 case X86ISD::VSRAI: return "X86ISD::VSRAI";
18740 case X86ISD::CMPP: return "X86ISD::CMPP";
18741 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
18742 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
18743 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
18744 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
18745 case X86ISD::ADD: return "X86ISD::ADD";
18746 case X86ISD::SUB: return "X86ISD::SUB";
18747 case X86ISD::ADC: return "X86ISD::ADC";
18748 case X86ISD::SBB: return "X86ISD::SBB";
18749 case X86ISD::SMUL: return "X86ISD::SMUL";
18750 case X86ISD::UMUL: return "X86ISD::UMUL";
18751 case X86ISD::INC: return "X86ISD::INC";
18752 case X86ISD::DEC: return "X86ISD::DEC";
18753 case X86ISD::OR: return "X86ISD::OR";
18754 case X86ISD::XOR: return "X86ISD::XOR";
18755 case X86ISD::AND: return "X86ISD::AND";
18756 case X86ISD::BEXTR: return "X86ISD::BEXTR";
18757 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
18758 case X86ISD::PTEST: return "X86ISD::PTEST";
18759 case X86ISD::TESTP: return "X86ISD::TESTP";
18760 case X86ISD::TESTM: return "X86ISD::TESTM";
18761 case X86ISD::TESTNM: return "X86ISD::TESTNM";
18762 case X86ISD::KORTEST: return "X86ISD::KORTEST";
18763 case X86ISD::PACKSS: return "X86ISD::PACKSS";
18764 case X86ISD::PACKUS: return "X86ISD::PACKUS";
18765 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
18766 case X86ISD::VALIGN: return "X86ISD::VALIGN";
18767 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
18768 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
18769 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
18770 case X86ISD::SHUFP: return "X86ISD::SHUFP";
18771 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
18772 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
18773 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
18774 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
18775 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
18776 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
18777 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
18778 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
18779 case X86ISD::MOVSD: return "X86ISD::MOVSD";
18780 case X86ISD::MOVSS: return "X86ISD::MOVSS";
18781 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
18782 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
18783 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
18784 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
18785 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
18786 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
18787 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
18788 case X86ISD::VPERMV: return "X86ISD::VPERMV";
18789 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
18790 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
18791 case X86ISD::VPERMI: return "X86ISD::VPERMI";
18792 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
18793 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
18794 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
18795 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
18796 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
18797 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
18798 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
18799 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
18800 case X86ISD::SAHF: return "X86ISD::SAHF";
18801 case X86ISD::RDRAND: return "X86ISD::RDRAND";
18802 case X86ISD::RDSEED: return "X86ISD::RDSEED";
18803 case X86ISD::FMADD: return "X86ISD::FMADD";
18804 case X86ISD::FMSUB: return "X86ISD::FMSUB";
18805 case X86ISD::FNMADD: return "X86ISD::FNMADD";
18806 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
18807 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
18808 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
18809 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
18810 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
18811 case X86ISD::XTEST: return "X86ISD::XTEST";
18812 }
18813 }
18815 // isLegalAddressingMode - Return true if the addressing mode represented
18816 // by AM is legal for this target, for a load/store of the specified type.
18817 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
18818 Type *Ty) const {
18819 // X86 supports extremely general addressing modes.
18820 CodeModel::Model M = getTargetMachine().getCodeModel();
18821 Reloc::Model R = getTargetMachine().getRelocationModel();
18823 // X86 allows a sign-extended 32-bit immediate field as a displacement.
18824 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
18825 return false;
18827 if (AM.BaseGV) {
18828 unsigned GVFlags =
18829 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
18831 // If a reference to this global requires an extra load, we can't fold it.
18832 if (isGlobalStubReference(GVFlags))
18833 return false;
18835 // If BaseGV requires a register for the PIC base, we cannot also have a
18836 // BaseReg specified.
18837 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
18838 return false;
18840 // If lower 4G is not available, then we must use rip-relative addressing.
18841 if ((M != CodeModel::Small || R != Reloc::Static) &&
18842 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
18843 return false;
18844 }
18846 switch (AM.Scale) {
18847 case 0:
18848 case 1:
18849 case 2:
18850 case 4:
18851 case 8:
18852 // These scales always work.
18853 break;
18854 case 3:
18855 case 5:
18856 case 9:
18857 // These scales are formed with basereg+scalereg. Only accept if there is
18858 // no basereg yet.
18859 if (AM.HasBaseReg)
18860 return false;
18861 break;
18862 default: // Other stuff never works.
18863 return false;
18864 }
18866 return true;
18867 }
18869 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
18870 unsigned Bits = Ty->getScalarSizeInBits();
18872 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
18873 // particularly cheaper than those without.
18874 if (Bits == 8)
18875 return false;
18877 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
18878 // variable shifts just as cheap as scalar ones.
18879 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
18880 return false;
18882 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
18883 // fully general vector.
18884 return true;
18885 }
18887 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
18888 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18889 return false;
18890 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
18891 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
18892 return NumBits1 > NumBits2;
18893 }
18895 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
18896 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18897 return false;
18899 if (!isTypeLegal(EVT::getEVT(Ty1)))
18900 return false;
18902 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
18904 // Assuming the caller doesn't have a zeroext or signext return parameter,
18905 // truncation all the way down to i1 is valid.
18906 return true;
18907 }
18909 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
18910 return isInt<32>(Imm);
18911 }
18913 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
18914 // Can also use sub to handle negated immediates.
18915 return isInt<32>(Imm);
18916 }
18918 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
18919 if (!VT1.isInteger() || !VT2.isInteger())
18920 return false;
18921 unsigned NumBits1 = VT1.getSizeInBits();
18922 unsigned NumBits2 = VT2.getSizeInBits();
18923 return NumBits1 > NumBits2;
18924 }
18926 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
18927 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18928 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
18929 }
18931 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
18932 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18933 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
18934 }
18936 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
18937 EVT VT1 = Val.getValueType();
18938 if (isZExtFree(VT1, VT2))
18939 return true;
18941 if (Val.getOpcode() != ISD::LOAD)
18942 return false;
18944 if (!VT1.isSimple() || !VT1.isInteger() ||
18945 !VT2.isSimple() || !VT2.isInteger())
18946 return false;
18948 switch (VT1.getSimpleVT().SimpleTy) {
18949 default: break;
18950 case MVT::i8:
18951 case MVT::i16:
18952 case MVT::i32:
18953 // X86 has 8, 16, and 32-bit zero-extending loads.
18954 return true;
18955 }
18957 return false;
18958 }
18960 bool
18961 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
18962 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
18963 return false;
18965 VT = VT.getScalarType();
18967 if (!VT.isSimple())
18968 return false;
18970 switch (VT.getSimpleVT().SimpleTy) {
18971 case MVT::f32:
18972 case MVT::f64:
18973 return true;
18974 default:
18975 break;
18976 }
18978 return false;
18979 }
18981 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
18982 // i16 instructions are longer (0x66 prefix) and potentially slower.
18983 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
18984 }
18986 /// isShuffleMaskLegal - Targets can use this to indicate that they only
18987 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
18988 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
18989 /// are assumed to be legal.
18990 bool
18991 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
18992 EVT VT) const {
18993 if (!VT.isSimple())
18994 return false;
18996 MVT SVT = VT.getSimpleVT();
18998 // Very little shuffling can be done for 64-bit vectors right now.
18999 if (VT.getSizeInBits() == 64)
19000 return false;
19002 // If this is a single-input shuffle with no 128 bit lane crossings we can
19003 // lower it into pshufb.
19004 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
19005 (SVT.is256BitVector() && Subtarget->hasInt256())) {
19006 bool isLegal = true;
19007 for (unsigned I = 0, E = M.size(); I != E; ++I) {
19008 if (M[I] >= (int)SVT.getVectorNumElements() ||
19009 ShuffleCrosses128bitLane(SVT, I, M[I])) {
19010 isLegal = false;
19011 break;
19012 }
19013 }
19014 if (isLegal)
19015 return true;
19016 }
19018 // FIXME: blends, shifts.
19019 return (SVT.getVectorNumElements() == 2 ||
19020 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
19021 isMOVLMask(M, SVT) ||
19022 isMOVHLPSMask(M, SVT) ||
19023 isSHUFPMask(M, SVT) ||
19024 isPSHUFDMask(M, SVT) ||
19025 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
19026 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
19027 isPALIGNRMask(M, SVT, Subtarget) ||
19028 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
19029 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
19030 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
19031 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
19032 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()));
19033 }
19035 bool
19036 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
19037 EVT VT) const {
19038 if (!VT.isSimple())
19039 return false;
19041 MVT SVT = VT.getSimpleVT();
19042 unsigned NumElts = SVT.getVectorNumElements();
19043 // FIXME: This collection of masks seems suspect.
19044 if (NumElts == 2)
19045 return true;
19046 if (NumElts == 4 && SVT.is128BitVector()) {
19047 return (isMOVLMask(Mask, SVT) ||
19048 isCommutedMOVLMask(Mask, SVT, true) ||
19049 isSHUFPMask(Mask, SVT) ||
19050 isSHUFPMask(Mask, SVT, /* Commuted */ true));
19051 }
19052 return false;
19053 }
19055 //===----------------------------------------------------------------------===//
19056 // X86 Scheduler Hooks
19057 //===----------------------------------------------------------------------===//
19059 /// Utility function to emit xbegin specifying the start of an RTM region.
19060 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
19061 const TargetInstrInfo *TII) {
19062 DebugLoc DL = MI->getDebugLoc();
19064 const BasicBlock *BB = MBB->getBasicBlock();
19065 MachineFunction::iterator I = MBB;
19066 ++I;
19068 // For the v = xbegin(), we generate
19069 //
19070 // thisMBB:
19071 // xbegin sinkMBB
19072 //
19073 // mainMBB:
19074 // eax = -1
19075 //
19076 // sinkMBB:
19077 // v = eax
19079 MachineBasicBlock *thisMBB = MBB;
19080 MachineFunction *MF = MBB->getParent();
19081 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19082 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19083 MF->insert(I, mainMBB);
19084 MF->insert(I, sinkMBB);
19086 // Transfer the remainder of BB and its successor edges to sinkMBB.
19087 sinkMBB->splice(sinkMBB->begin(), MBB,
19088 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19089 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19091 // thisMBB:
19092 // xbegin sinkMBB
19093 // # fallthrough to mainMBB
19094 // # abortion to sinkMBB
19095 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
19096 thisMBB->addSuccessor(mainMBB);
19097 thisMBB->addSuccessor(sinkMBB);
19099 // mainMBB:
19100 // EAX = -1
19101 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
19102 mainMBB->addSuccessor(sinkMBB);
19104 // sinkMBB:
19105 // EAX is live into the sinkMBB
19106 sinkMBB->addLiveIn(X86::EAX);
19107 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19108 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19109 .addReg(X86::EAX);
19111 MI->eraseFromParent();
19112 return sinkMBB;
19113 }
19115 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
19116 // or XMM0_V32I8 in AVX all of this code can be replaced with that
19117 // in the .td file.
19118 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
19119 const TargetInstrInfo *TII) {
19120 unsigned Opc;
19121 switch (MI->getOpcode()) {
19122 default: llvm_unreachable("illegal opcode!");
19123 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
19124 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
19125 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
19126 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
19127 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
19128 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
19129 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
19130 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
19131 }
19133 DebugLoc dl = MI->getDebugLoc();
19134 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
19136 unsigned NumArgs = MI->getNumOperands();
19137 for (unsigned i = 1; i < NumArgs; ++i) {
19138 MachineOperand &Op = MI->getOperand(i);
19139 if (!(Op.isReg() && Op.isImplicit()))
19140 MIB.addOperand(Op);
19141 }
19142 if (MI->hasOneMemOperand())
19143 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
19145 BuildMI(*BB, MI, dl,
19146 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19147 .addReg(X86::XMM0);
19149 MI->eraseFromParent();
19150 return BB;
19151 }
19153 // FIXME: Custom handling because TableGen doesn't support multiple implicit
19154 // defs in an instruction pattern
19155 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
19156 const TargetInstrInfo *TII) {
19157 unsigned Opc;
19158 switch (MI->getOpcode()) {
19159 default: llvm_unreachable("illegal opcode!");
19160 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
19161 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
19162 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
19163 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
19164 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
19165 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
19166 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
19167 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
19168 }
19170 DebugLoc dl = MI->getDebugLoc();
19171 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
19173 unsigned NumArgs = MI->getNumOperands(); // remove the results
19174 for (unsigned i = 1; i < NumArgs; ++i) {
19175 MachineOperand &Op = MI->getOperand(i);
19176 if (!(Op.isReg() && Op.isImplicit()))
19177 MIB.addOperand(Op);
19178 }
19179 if (MI->hasOneMemOperand())
19180 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
19182 BuildMI(*BB, MI, dl,
19183 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19184 .addReg(X86::ECX);
19186 MI->eraseFromParent();
19187 return BB;
19188 }
19190 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
19191 const TargetInstrInfo *TII,
19192 const X86Subtarget* Subtarget) {
19193 DebugLoc dl = MI->getDebugLoc();
19195 // Address into RAX/EAX, other two args into ECX, EDX.
19196 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
19197 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
19198 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
19199 for (int i = 0; i < X86::AddrNumOperands; ++i)
19200 MIB.addOperand(MI->getOperand(i));
19202 unsigned ValOps = X86::AddrNumOperands;
19203 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
19204 .addReg(MI->getOperand(ValOps).getReg());
19205 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
19206 .addReg(MI->getOperand(ValOps+1).getReg());
19208 // The instruction doesn't actually take any operands though.
19209 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
19211 MI->eraseFromParent(); // The pseudo is gone now.
19212 return BB;
19213 }
19215 MachineBasicBlock *
19216 X86TargetLowering::EmitVAARG64WithCustomInserter(
19217 MachineInstr *MI,
19218 MachineBasicBlock *MBB) const {
19219 // Emit va_arg instruction on X86-64.
19221 // Operands to this pseudo-instruction:
19222 // 0 ) Output : destination address (reg)
19223 // 1-5) Input : va_list address (addr, i64mem)
19224 // 6 ) ArgSize : Size (in bytes) of vararg type
19225 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
19226 // 8 ) Align : Alignment of type
19227 // 9 ) EFLAGS (implicit-def)
19229 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
19230 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
19232 unsigned DestReg = MI->getOperand(0).getReg();
19233 MachineOperand &Base = MI->getOperand(1);
19234 MachineOperand &Scale = MI->getOperand(2);
19235 MachineOperand &Index = MI->getOperand(3);
19236 MachineOperand &Disp = MI->getOperand(4);
19237 MachineOperand &Segment = MI->getOperand(5);
19238 unsigned ArgSize = MI->getOperand(6).getImm();
19239 unsigned ArgMode = MI->getOperand(7).getImm();
19240 unsigned Align = MI->getOperand(8).getImm();
19242 // Memory Reference
19243 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
19244 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19245 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19247 // Machine Information
19248 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
19249 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
19250 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
19251 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
19252 DebugLoc DL = MI->getDebugLoc();
19254 // struct va_list {
19255 // i32 gp_offset
19256 // i32 fp_offset
19257 // i64 overflow_area (address)
19258 // i64 reg_save_area (address)
19259 // }
19260 // sizeof(va_list) = 24
19261 // alignment(va_list) = 8
19263 unsigned TotalNumIntRegs = 6;
19264 unsigned TotalNumXMMRegs = 8;
19265 bool UseGPOffset = (ArgMode == 1);
19266 bool UseFPOffset = (ArgMode == 2);
19267 unsigned MaxOffset = TotalNumIntRegs * 8 +
19268 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
19270 /* Align ArgSize to a multiple of 8 */
19271 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
19272 bool NeedsAlign = (Align > 8);
19274 MachineBasicBlock *thisMBB = MBB;
19275 MachineBasicBlock *overflowMBB;
19276 MachineBasicBlock *offsetMBB;
19277 MachineBasicBlock *endMBB;
19279 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
19280 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
19281 unsigned OffsetReg = 0;
19283 if (!UseGPOffset && !UseFPOffset) {
19284 // If we only pull from the overflow region, we don't create a branch.
19285 // We don't need to alter control flow.
19286 OffsetDestReg = 0; // unused
19287 OverflowDestReg = DestReg;
19289 offsetMBB = nullptr;
19290 overflowMBB = thisMBB;
19291 endMBB = thisMBB;
19292 } else {
19293 // First emit code to check if gp_offset (or fp_offset) is below the bound.
19294 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
19295 // If not, pull from overflow_area. (branch to overflowMBB)
19296 //
19297 // thisMBB
19298 // | .
19299 // | .
19300 // offsetMBB overflowMBB
19301 // | .
19302 // | .
19303 // endMBB
19305 // Registers for the PHI in endMBB
19306 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
19307 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
19309 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
19310 MachineFunction *MF = MBB->getParent();
19311 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19312 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19313 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19315 MachineFunction::iterator MBBIter = MBB;
19316 ++MBBIter;
19318 // Insert the new basic blocks
19319 MF->insert(MBBIter, offsetMBB);
19320 MF->insert(MBBIter, overflowMBB);
19321 MF->insert(MBBIter, endMBB);
19323 // Transfer the remainder of MBB and its successor edges to endMBB.
19324 endMBB->splice(endMBB->begin(), thisMBB,
19325 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
19326 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
19328 // Make offsetMBB and overflowMBB successors of thisMBB
19329 thisMBB->addSuccessor(offsetMBB);
19330 thisMBB->addSuccessor(overflowMBB);
19332 // endMBB is a successor of both offsetMBB and overflowMBB
19333 offsetMBB->addSuccessor(endMBB);
19334 overflowMBB->addSuccessor(endMBB);
19336 // Load the offset value into a register
19337 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
19338 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
19339 .addOperand(Base)
19340 .addOperand(Scale)
19341 .addOperand(Index)
19342 .addDisp(Disp, UseFPOffset ? 4 : 0)
19343 .addOperand(Segment)
19344 .setMemRefs(MMOBegin, MMOEnd);
19346 // Check if there is enough room left to pull this argument.
19347 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
19348 .addReg(OffsetReg)
19349 .addImm(MaxOffset + 8 - ArgSizeA8);
19351 // Branch to "overflowMBB" if offset >= max
19352 // Fall through to "offsetMBB" otherwise
19353 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
19354 .addMBB(overflowMBB);
19355 }
19357 // In offsetMBB, emit code to use the reg_save_area.
19358 if (offsetMBB) {
19359 assert(OffsetReg != 0);
19361 // Read the reg_save_area address.
19362 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
19363 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
19364 .addOperand(Base)
19365 .addOperand(Scale)
19366 .addOperand(Index)
19367 .addDisp(Disp, 16)
19368 .addOperand(Segment)
19369 .setMemRefs(MMOBegin, MMOEnd);
19371 // Zero-extend the offset
19372 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
19373 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
19374 .addImm(0)
19375 .addReg(OffsetReg)
19376 .addImm(X86::sub_32bit);
19378 // Add the offset to the reg_save_area to get the final address.
19379 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
19380 .addReg(OffsetReg64)
19381 .addReg(RegSaveReg);
19383 // Compute the offset for the next argument
19384 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
19385 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
19386 .addReg(OffsetReg)
19387 .addImm(UseFPOffset ? 16 : 8);
19389 // Store it back into the va_list.
19390 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
19391 .addOperand(Base)
19392 .addOperand(Scale)
19393 .addOperand(Index)
19394 .addDisp(Disp, UseFPOffset ? 4 : 0)
19395 .addOperand(Segment)
19396 .addReg(NextOffsetReg)
19397 .setMemRefs(MMOBegin, MMOEnd);
19399 // Jump to endMBB
19400 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
19401 .addMBB(endMBB);
19402 }
19404 //
19405 // Emit code to use overflow area
19406 //
19408 // Load the overflow_area address into a register.
19409 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
19410 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
19411 .addOperand(Base)
19412 .addOperand(Scale)
19413 .addOperand(Index)
19414 .addDisp(Disp, 8)
19415 .addOperand(Segment)
19416 .setMemRefs(MMOBegin, MMOEnd);
19418 // If we need to align it, do so. Otherwise, just copy the address
19419 // to OverflowDestReg.
19420 if (NeedsAlign) {
19421 // Align the overflow address
19422 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
19423 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
19425 // aligned_addr = (addr + (align-1)) & ~(align-1)
19426 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
19427 .addReg(OverflowAddrReg)
19428 .addImm(Align-1);
19430 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
19431 .addReg(TmpReg)
19432 .addImm(~(uint64_t)(Align-1));
19433 } else {
19434 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
19435 .addReg(OverflowAddrReg);
19436 }
19438 // Compute the next overflow address after this argument.
19439 // (the overflow address should be kept 8-byte aligned)
19440 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
19441 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
19442 .addReg(OverflowDestReg)
19443 .addImm(ArgSizeA8);
19445 // Store the new overflow address.
19446 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
19447 .addOperand(Base)
19448 .addOperand(Scale)
19449 .addOperand(Index)
19450 .addDisp(Disp, 8)
19451 .addOperand(Segment)
19452 .addReg(NextAddrReg)
19453 .setMemRefs(MMOBegin, MMOEnd);
19455 // If we branched, emit the PHI to the front of endMBB.
19456 if (offsetMBB) {
19457 BuildMI(*endMBB, endMBB->begin(), DL,
19458 TII->get(X86::PHI), DestReg)
19459 .addReg(OffsetDestReg).addMBB(offsetMBB)
19460 .addReg(OverflowDestReg).addMBB(overflowMBB);
19461 }
19463 // Erase the pseudo instruction
19464 MI->eraseFromParent();
19466 return endMBB;
19467 }
19469 MachineBasicBlock *
19470 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
19471 MachineInstr *MI,
19472 MachineBasicBlock *MBB) const {
19473 // Emit code to save XMM registers to the stack. The ABI says that the
19474 // number of registers to save is given in %al, so it's theoretically
19475 // possible to do an indirect jump trick to avoid saving all of them,
19476 // however this code takes a simpler approach and just executes all
19477 // of the stores if %al is non-zero. It's less code, and it's probably
19478 // easier on the hardware branch predictor, and stores aren't all that
19479 // expensive anyway.
19481 // Create the new basic blocks. One block contains all the XMM stores,
19482 // and one block is the final destination regardless of whether any
19483 // stores were performed.
19484 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
19485 MachineFunction *F = MBB->getParent();
19486 MachineFunction::iterator MBBIter = MBB;
19487 ++MBBIter;
19488 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
19489 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
19490 F->insert(MBBIter, XMMSaveMBB);
19491 F->insert(MBBIter, EndMBB);
19493 // Transfer the remainder of MBB and its successor edges to EndMBB.
19494 EndMBB->splice(EndMBB->begin(), MBB,
19495 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19496 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
19498 // The original block will now fall through to the XMM save block.
19499 MBB->addSuccessor(XMMSaveMBB);
19500 // The XMMSaveMBB will fall through to the end block.
19501 XMMSaveMBB->addSuccessor(EndMBB);
19503 // Now add the instructions.
19504 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
19505 DebugLoc DL = MI->getDebugLoc();
19507 unsigned CountReg = MI->getOperand(0).getReg();
19508 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
19509 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
19511 if (!Subtarget->isTargetWin64()) {
19512 // If %al is 0, branch around the XMM save block.
19513 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
19514 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
19515 MBB->addSuccessor(EndMBB);
19516 }
19518 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
19519 // that was just emitted, but clearly shouldn't be "saved".
19520 assert((MI->getNumOperands() <= 3 ||
19521 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
19522 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
19523 && "Expected last argument to be EFLAGS");
19524 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
19525 // In the XMM save block, save all the XMM argument registers.
19526 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
19527 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
19528 MachineMemOperand *MMO =
19529 F->getMachineMemOperand(
19530 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
19531 MachineMemOperand::MOStore,
19532 /*Size=*/16, /*Align=*/16);
19533 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
19534 .addFrameIndex(RegSaveFrameIndex)
19535 .addImm(/*Scale=*/1)
19536 .addReg(/*IndexReg=*/0)
19537 .addImm(/*Disp=*/Offset)
19538 .addReg(/*Segment=*/0)
19539 .addReg(MI->getOperand(i).getReg())
19540 .addMemOperand(MMO);
19541 }
19543 MI->eraseFromParent(); // The pseudo instruction is gone now.
19545 return EndMBB;
19546 }
19548 // The EFLAGS operand of SelectItr might be missing a kill marker
19549 // because there were multiple uses of EFLAGS, and ISel didn't know
19550 // which to mark. Figure out whether SelectItr should have had a
19551 // kill marker, and set it if it should. Returns the correct kill
19552 // marker value.
19553 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
19554 MachineBasicBlock* BB,
19555 const TargetRegisterInfo* TRI) {
19556 // Scan forward through BB for a use/def of EFLAGS.
19557 MachineBasicBlock::iterator miI(std::next(SelectItr));
19558 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
19559 const MachineInstr& mi = *miI;
19560 if (mi.readsRegister(X86::EFLAGS))
19561 return false;
19562 if (mi.definesRegister(X86::EFLAGS))
19563 break; // Should have kill-flag - update below.
19564 }
19566 // If we hit the end of the block, check whether EFLAGS is live into a
19567 // successor.
19568 if (miI == BB->end()) {
19569 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
19570 sEnd = BB->succ_end();
19571 sItr != sEnd; ++sItr) {
19572 MachineBasicBlock* succ = *sItr;
19573 if (succ->isLiveIn(X86::EFLAGS))
19574 return false;
19575 }
19576 }
19578 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
19579 // out. SelectMI should have a kill flag on EFLAGS.
19580 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
19581 return true;
19582 }
19584 MachineBasicBlock *
19585 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
19586 MachineBasicBlock *BB) const {
19587 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
19588 DebugLoc DL = MI->getDebugLoc();
19590 // To "insert" a SELECT_CC instruction, we actually have to insert the
19591 // diamond control-flow pattern. The incoming instruction knows the
19592 // destination vreg to set, the condition code register to branch on, the
19593 // true/false values to select between, and a branch opcode to use.
19594 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19595 MachineFunction::iterator It = BB;
19596 ++It;
19598 // thisMBB:
19599 // ...
19600 // TrueVal = ...
19601 // cmpTY ccX, r1, r2
19602 // bCC copy1MBB
19603 // fallthrough --> copy0MBB
19604 MachineBasicBlock *thisMBB = BB;
19605 MachineFunction *F = BB->getParent();
19606 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
19607 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
19608 F->insert(It, copy0MBB);
19609 F->insert(It, sinkMBB);
19611 // If the EFLAGS register isn't dead in the terminator, then claim that it's
19612 // live into the sink and copy blocks.
19613 const TargetRegisterInfo *TRI =
19614 BB->getParent()->getSubtarget().getRegisterInfo();
19615 if (!MI->killsRegister(X86::EFLAGS) &&
19616 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
19617 copy0MBB->addLiveIn(X86::EFLAGS);
19618 sinkMBB->addLiveIn(X86::EFLAGS);
19619 }
19621 // Transfer the remainder of BB and its successor edges to sinkMBB.
19622 sinkMBB->splice(sinkMBB->begin(), BB,
19623 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19624 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
19626 // Add the true and fallthrough blocks as its successors.
19627 BB->addSuccessor(copy0MBB);
19628 BB->addSuccessor(sinkMBB);
19630 // Create the conditional branch instruction.
19631 unsigned Opc =
19632 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
19633 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
19635 // copy0MBB:
19636 // %FalseValue = ...
19637 // # fallthrough to sinkMBB
19638 copy0MBB->addSuccessor(sinkMBB);
19640 // sinkMBB:
19641 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
19642 // ...
19643 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19644 TII->get(X86::PHI), MI->getOperand(0).getReg())
19645 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
19646 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
19648 MI->eraseFromParent(); // The pseudo instruction is gone now.
19649 return sinkMBB;
19650 }
19652 MachineBasicBlock *
19653 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
19654 MachineBasicBlock *BB) const {
19655 MachineFunction *MF = BB->getParent();
19656 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
19657 DebugLoc DL = MI->getDebugLoc();
19658 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19660 assert(MF->shouldSplitStack());
19662 const bool Is64Bit = Subtarget->is64Bit();
19663 const bool IsLP64 = Subtarget->isTarget64BitLP64();
19665 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
19666 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
19668 // BB:
19669 // ... [Till the alloca]
19670 // If stacklet is not large enough, jump to mallocMBB
19671 //
19672 // bumpMBB:
19673 // Allocate by subtracting from RSP
19674 // Jump to continueMBB
19675 //
19676 // mallocMBB:
19677 // Allocate by call to runtime
19678 //
19679 // continueMBB:
19680 // ...
19681 // [rest of original BB]
19682 //
19684 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19685 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19686 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19688 MachineRegisterInfo &MRI = MF->getRegInfo();
19689 const TargetRegisterClass *AddrRegClass =
19690 getRegClassFor(getPointerTy());
19692 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19693 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19694 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
19695 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
19696 sizeVReg = MI->getOperand(1).getReg(),
19697 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
19699 MachineFunction::iterator MBBIter = BB;
19700 ++MBBIter;
19702 MF->insert(MBBIter, bumpMBB);
19703 MF->insert(MBBIter, mallocMBB);
19704 MF->insert(MBBIter, continueMBB);
19706 continueMBB->splice(continueMBB->begin(), BB,
19707 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19708 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
19710 // Add code to the main basic block to check if the stack limit has been hit,
19711 // and if so, jump to mallocMBB otherwise to bumpMBB.
19712 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
19713 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
19714 .addReg(tmpSPVReg).addReg(sizeVReg);
19715 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
19716 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
19717 .addReg(SPLimitVReg);
19718 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
19720 // bumpMBB simply decreases the stack pointer, since we know the current
19721 // stacklet has enough space.
19722 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
19723 .addReg(SPLimitVReg);
19724 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
19725 .addReg(SPLimitVReg);
19726 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
19728 // Calls into a routine in libgcc to allocate more space from the heap.
19729 const uint32_t *RegMask = MF->getTarget()
19730 .getSubtargetImpl()
19731 ->getRegisterInfo()
19732 ->getCallPreservedMask(CallingConv::C);
19733 if (IsLP64) {
19734 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
19735 .addReg(sizeVReg);
19736 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19737 .addExternalSymbol("__morestack_allocate_stack_space")
19738 .addRegMask(RegMask)
19739 .addReg(X86::RDI, RegState::Implicit)
19740 .addReg(X86::RAX, RegState::ImplicitDefine);
19741 } else if (Is64Bit) {
19742 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
19743 .addReg(sizeVReg);
19744 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19745 .addExternalSymbol("__morestack_allocate_stack_space")
19746 .addRegMask(RegMask)
19747 .addReg(X86::EDI, RegState::Implicit)
19748 .addReg(X86::EAX, RegState::ImplicitDefine);
19749 } else {
19750 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
19751 .addImm(12);
19752 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
19753 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
19754 .addExternalSymbol("__morestack_allocate_stack_space")
19755 .addRegMask(RegMask)
19756 .addReg(X86::EAX, RegState::ImplicitDefine);
19757 }
19759 if (!Is64Bit)
19760 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
19761 .addImm(16);
19763 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
19764 .addReg(IsLP64 ? X86::RAX : X86::EAX);
19765 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
19767 // Set up the CFG correctly.
19768 BB->addSuccessor(bumpMBB);
19769 BB->addSuccessor(mallocMBB);
19770 mallocMBB->addSuccessor(continueMBB);
19771 bumpMBB->addSuccessor(continueMBB);
19773 // Take care of the PHI nodes.
19774 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
19775 MI->getOperand(0).getReg())
19776 .addReg(mallocPtrVReg).addMBB(mallocMBB)
19777 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
19779 // Delete the original pseudo instruction.
19780 MI->eraseFromParent();
19782 // And we're done.
19783 return continueMBB;
19784 }
19786 MachineBasicBlock *
19787 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
19788 MachineBasicBlock *BB) const {
19789 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
19790 DebugLoc DL = MI->getDebugLoc();
19792 assert(!Subtarget->isTargetMacho());
19794 // The lowering is pretty easy: we're just emitting the call to _alloca. The
19795 // non-trivial part is impdef of ESP.
19797 if (Subtarget->isTargetWin64()) {
19798 if (Subtarget->isTargetCygMing()) {
19799 // ___chkstk(Mingw64):
19800 // Clobbers R10, R11, RAX and EFLAGS.
19801 // Updates RSP.
19802 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
19803 .addExternalSymbol("___chkstk")
19804 .addReg(X86::RAX, RegState::Implicit)
19805 .addReg(X86::RSP, RegState::Implicit)
19806 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
19807 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
19808 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19809 } else {
19810 // __chkstk(MSVCRT): does not update stack pointer.
19811 // Clobbers R10, R11 and EFLAGS.
19812 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
19813 .addExternalSymbol("__chkstk")
19814 .addReg(X86::RAX, RegState::Implicit)
19815 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19816 // RAX has the offset to be subtracted from RSP.
19817 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
19818 .addReg(X86::RSP)
19819 .addReg(X86::RAX);
19820 }
19821 } else {
19822 const char *StackProbeSymbol =
19823 Subtarget->isTargetKnownWindowsMSVC() ? "_chkstk" : "_alloca";
19825 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
19826 .addExternalSymbol(StackProbeSymbol)
19827 .addReg(X86::EAX, RegState::Implicit)
19828 .addReg(X86::ESP, RegState::Implicit)
19829 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
19830 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
19831 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19832 }
19834 MI->eraseFromParent(); // The pseudo instruction is gone now.
19835 return BB;
19836 }
19838 MachineBasicBlock *
19839 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
19840 MachineBasicBlock *BB) const {
19841 // This is pretty easy. We're taking the value that we received from
19842 // our load from the relocation, sticking it in either RDI (x86-64)
19843 // or EAX and doing an indirect call. The return value will then
19844 // be in the normal return register.
19845 MachineFunction *F = BB->getParent();
19846 const X86InstrInfo *TII =
19847 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
19848 DebugLoc DL = MI->getDebugLoc();
19850 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
19851 assert(MI->getOperand(3).isGlobal() && "This should be a global");
19853 // Get a register mask for the lowered call.
19854 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
19855 // proper register mask.
19856 const uint32_t *RegMask = F->getTarget()
19857 .getSubtargetImpl()
19858 ->getRegisterInfo()
19859 ->getCallPreservedMask(CallingConv::C);
19860 if (Subtarget->is64Bit()) {
19861 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19862 TII->get(X86::MOV64rm), X86::RDI)
19863 .addReg(X86::RIP)
19864 .addImm(0).addReg(0)
19865 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19866 MI->getOperand(3).getTargetFlags())
19867 .addReg(0);
19868 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
19869 addDirectMem(MIB, X86::RDI);
19870 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
19871 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
19872 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19873 TII->get(X86::MOV32rm), X86::EAX)
19874 .addReg(0)
19875 .addImm(0).addReg(0)
19876 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19877 MI->getOperand(3).getTargetFlags())
19878 .addReg(0);
19879 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19880 addDirectMem(MIB, X86::EAX);
19881 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19882 } else {
19883 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19884 TII->get(X86::MOV32rm), X86::EAX)
19885 .addReg(TII->getGlobalBaseReg(F))
19886 .addImm(0).addReg(0)
19887 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19888 MI->getOperand(3).getTargetFlags())
19889 .addReg(0);
19890 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19891 addDirectMem(MIB, X86::EAX);
19892 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19893 }
19895 MI->eraseFromParent(); // The pseudo instruction is gone now.
19896 return BB;
19897 }
19899 MachineBasicBlock *
19900 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
19901 MachineBasicBlock *MBB) const {
19902 DebugLoc DL = MI->getDebugLoc();
19903 MachineFunction *MF = MBB->getParent();
19904 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
19905 MachineRegisterInfo &MRI = MF->getRegInfo();
19907 const BasicBlock *BB = MBB->getBasicBlock();
19908 MachineFunction::iterator I = MBB;
19909 ++I;
19911 // Memory Reference
19912 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19913 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19915 unsigned DstReg;
19916 unsigned MemOpndSlot = 0;
19918 unsigned CurOp = 0;
19920 DstReg = MI->getOperand(CurOp++).getReg();
19921 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
19922 assert(RC->hasType(MVT::i32) && "Invalid destination!");
19923 unsigned mainDstReg = MRI.createVirtualRegister(RC);
19924 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
19926 MemOpndSlot = CurOp;
19928 MVT PVT = getPointerTy();
19929 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19930 "Invalid Pointer Size!");
19932 // For v = setjmp(buf), we generate
19933 //
19934 // thisMBB:
19935 // buf[LabelOffset] = restoreMBB
19936 // SjLjSetup restoreMBB
19937 //
19938 // mainMBB:
19939 // v_main = 0
19940 //
19941 // sinkMBB:
19942 // v = phi(main, restore)
19943 //
19944 // restoreMBB:
19945 // v_restore = 1
19947 MachineBasicBlock *thisMBB = MBB;
19948 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19949 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19950 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
19951 MF->insert(I, mainMBB);
19952 MF->insert(I, sinkMBB);
19953 MF->push_back(restoreMBB);
19955 MachineInstrBuilder MIB;
19957 // Transfer the remainder of BB and its successor edges to sinkMBB.
19958 sinkMBB->splice(sinkMBB->begin(), MBB,
19959 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19960 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19962 // thisMBB:
19963 unsigned PtrStoreOpc = 0;
19964 unsigned LabelReg = 0;
19965 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19966 Reloc::Model RM = MF->getTarget().getRelocationModel();
19967 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
19968 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
19970 // Prepare IP either in reg or imm.
19971 if (!UseImmLabel) {
19972 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
19973 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
19974 LabelReg = MRI.createVirtualRegister(PtrRC);
19975 if (Subtarget->is64Bit()) {
19976 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
19977 .addReg(X86::RIP)
19978 .addImm(0)
19979 .addReg(0)
19980 .addMBB(restoreMBB)
19981 .addReg(0);
19982 } else {
19983 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
19984 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
19985 .addReg(XII->getGlobalBaseReg(MF))
19986 .addImm(0)
19987 .addReg(0)
19988 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
19989 .addReg(0);
19990 }
19991 } else
19992 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
19993 // Store IP
19994 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
19995 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19996 if (i == X86::AddrDisp)
19997 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
19998 else
19999 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
20000 }
20001 if (!UseImmLabel)
20002 MIB.addReg(LabelReg);
20003 else
20004 MIB.addMBB(restoreMBB);
20005 MIB.setMemRefs(MMOBegin, MMOEnd);
20006 // Setup
20007 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
20008 .addMBB(restoreMBB);
20010 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
20011 MF->getSubtarget().getRegisterInfo());
20012 MIB.addRegMask(RegInfo->getNoPreservedMask());
20013 thisMBB->addSuccessor(mainMBB);
20014 thisMBB->addSuccessor(restoreMBB);
20016 // mainMBB:
20017 // EAX = 0
20018 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
20019 mainMBB->addSuccessor(sinkMBB);
20021 // sinkMBB:
20022 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20023 TII->get(X86::PHI), DstReg)
20024 .addReg(mainDstReg).addMBB(mainMBB)
20025 .addReg(restoreDstReg).addMBB(restoreMBB);
20027 // restoreMBB:
20028 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
20029 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
20030 restoreMBB->addSuccessor(sinkMBB);
20032 MI->eraseFromParent();
20033 return sinkMBB;
20034 }
20036 MachineBasicBlock *
20037 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
20038 MachineBasicBlock *MBB) const {
20039 DebugLoc DL = MI->getDebugLoc();
20040 MachineFunction *MF = MBB->getParent();
20041 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20042 MachineRegisterInfo &MRI = MF->getRegInfo();
20044 // Memory Reference
20045 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20046 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20048 MVT PVT = getPointerTy();
20049 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20050 "Invalid Pointer Size!");
20052 const TargetRegisterClass *RC =
20053 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
20054 unsigned Tmp = MRI.createVirtualRegister(RC);
20055 // Since FP is only updated here but NOT referenced, it's treated as GPR.
20056 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
20057 MF->getSubtarget().getRegisterInfo());
20058 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
20059 unsigned SP = RegInfo->getStackRegister();
20061 MachineInstrBuilder MIB;
20063 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20064 const int64_t SPOffset = 2 * PVT.getStoreSize();
20066 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
20067 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
20069 // Reload FP
20070 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
20071 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
20072 MIB.addOperand(MI->getOperand(i));
20073 MIB.setMemRefs(MMOBegin, MMOEnd);
20074 // Reload IP
20075 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
20076 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20077 if (i == X86::AddrDisp)
20078 MIB.addDisp(MI->getOperand(i), LabelOffset);
20079 else
20080 MIB.addOperand(MI->getOperand(i));
20081 }
20082 MIB.setMemRefs(MMOBegin, MMOEnd);
20083 // Reload SP
20084 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
20085 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20086 if (i == X86::AddrDisp)
20087 MIB.addDisp(MI->getOperand(i), SPOffset);
20088 else
20089 MIB.addOperand(MI->getOperand(i));
20090 }
20091 MIB.setMemRefs(MMOBegin, MMOEnd);
20092 // Jump
20093 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
20095 MI->eraseFromParent();
20096 return MBB;
20097 }
20099 // Replace 213-type (isel default) FMA3 instructions with 231-type for
20100 // accumulator loops. Writing back to the accumulator allows the coalescer
20101 // to remove extra copies in the loop.
20102 MachineBasicBlock *
20103 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
20104 MachineBasicBlock *MBB) const {
20105 MachineOperand &AddendOp = MI->getOperand(3);
20107 // Bail out early if the addend isn't a register - we can't switch these.
20108 if (!AddendOp.isReg())
20109 return MBB;
20111 MachineFunction &MF = *MBB->getParent();
20112 MachineRegisterInfo &MRI = MF.getRegInfo();
20114 // Check whether the addend is defined by a PHI:
20115 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
20116 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
20117 if (!AddendDef.isPHI())
20118 return MBB;
20120 // Look for the following pattern:
20121 // loop:
20122 // %addend = phi [%entry, 0], [%loop, %result]
20123 // ...
20124 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
20126 // Replace with:
20127 // loop:
20128 // %addend = phi [%entry, 0], [%loop, %result]
20129 // ...
20130 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
20132 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
20133 assert(AddendDef.getOperand(i).isReg());
20134 MachineOperand PHISrcOp = AddendDef.getOperand(i);
20135 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
20136 if (&PHISrcInst == MI) {
20137 // Found a matching instruction.
20138 unsigned NewFMAOpc = 0;
20139 switch (MI->getOpcode()) {
20140 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
20141 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
20142 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
20143 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
20144 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
20145 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
20146 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
20147 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
20148 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
20149 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
20150 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
20151 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
20152 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
20153 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
20154 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
20155 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
20156 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
20157 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
20158 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
20159 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
20160 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
20161 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
20162 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
20163 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
20164 default: llvm_unreachable("Unrecognized FMA variant.");
20165 }
20167 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
20168 MachineInstrBuilder MIB =
20169 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
20170 .addOperand(MI->getOperand(0))
20171 .addOperand(MI->getOperand(3))
20172 .addOperand(MI->getOperand(2))
20173 .addOperand(MI->getOperand(1));
20174 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
20175 MI->eraseFromParent();
20176 }
20177 }
20179 return MBB;
20180 }
20182 MachineBasicBlock *
20183 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
20184 MachineBasicBlock *BB) const {
20185 switch (MI->getOpcode()) {
20186 default: llvm_unreachable("Unexpected instr type to insert");
20187 case X86::TAILJMPd64:
20188 case X86::TAILJMPr64:
20189 case X86::TAILJMPm64:
20190 llvm_unreachable("TAILJMP64 would not be touched here.");
20191 case X86::TCRETURNdi64:
20192 case X86::TCRETURNri64:
20193 case X86::TCRETURNmi64:
20194 return BB;
20195 case X86::WIN_ALLOCA:
20196 return EmitLoweredWinAlloca(MI, BB);
20197 case X86::SEG_ALLOCA_32:
20198 case X86::SEG_ALLOCA_64:
20199 return EmitLoweredSegAlloca(MI, BB);
20200 case X86::TLSCall_32:
20201 case X86::TLSCall_64:
20202 return EmitLoweredTLSCall(MI, BB);
20203 case X86::CMOV_GR8:
20204 case X86::CMOV_FR32:
20205 case X86::CMOV_FR64:
20206 case X86::CMOV_V4F32:
20207 case X86::CMOV_V2F64:
20208 case X86::CMOV_V2I64:
20209 case X86::CMOV_V8F32:
20210 case X86::CMOV_V4F64:
20211 case X86::CMOV_V4I64:
20212 case X86::CMOV_V16F32:
20213 case X86::CMOV_V8F64:
20214 case X86::CMOV_V8I64:
20215 case X86::CMOV_GR16:
20216 case X86::CMOV_GR32:
20217 case X86::CMOV_RFP32:
20218 case X86::CMOV_RFP64:
20219 case X86::CMOV_RFP80:
20220 return EmitLoweredSelect(MI, BB);
20222 case X86::FP32_TO_INT16_IN_MEM:
20223 case X86::FP32_TO_INT32_IN_MEM:
20224 case X86::FP32_TO_INT64_IN_MEM:
20225 case X86::FP64_TO_INT16_IN_MEM:
20226 case X86::FP64_TO_INT32_IN_MEM:
20227 case X86::FP64_TO_INT64_IN_MEM:
20228 case X86::FP80_TO_INT16_IN_MEM:
20229 case X86::FP80_TO_INT32_IN_MEM:
20230 case X86::FP80_TO_INT64_IN_MEM: {
20231 MachineFunction *F = BB->getParent();
20232 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
20233 DebugLoc DL = MI->getDebugLoc();
20235 // Change the floating point control register to use "round towards zero"
20236 // mode when truncating to an integer value.
20237 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
20238 addFrameReference(BuildMI(*BB, MI, DL,
20239 TII->get(X86::FNSTCW16m)), CWFrameIdx);
20241 // Load the old value of the high byte of the control word...
20242 unsigned OldCW =
20243 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
20244 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
20245 CWFrameIdx);
20247 // Set the high part to be round to zero...
20248 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
20249 .addImm(0xC7F);
20251 // Reload the modified control word now...
20252 addFrameReference(BuildMI(*BB, MI, DL,
20253 TII->get(X86::FLDCW16m)), CWFrameIdx);
20255 // Restore the memory image of control word to original value
20256 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
20257 .addReg(OldCW);
20259 // Get the X86 opcode to use.
20260 unsigned Opc;
20261 switch (MI->getOpcode()) {
20262 default: llvm_unreachable("illegal opcode!");
20263 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
20264 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
20265 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
20266 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
20267 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
20268 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
20269 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
20270 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
20271 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
20272 }
20274 X86AddressMode AM;
20275 MachineOperand &Op = MI->getOperand(0);
20276 if (Op.isReg()) {
20277 AM.BaseType = X86AddressMode::RegBase;
20278 AM.Base.Reg = Op.getReg();
20279 } else {
20280 AM.BaseType = X86AddressMode::FrameIndexBase;
20281 AM.Base.FrameIndex = Op.getIndex();
20282 }
20283 Op = MI->getOperand(1);
20284 if (Op.isImm())
20285 AM.Scale = Op.getImm();
20286 Op = MI->getOperand(2);
20287 if (Op.isImm())
20288 AM.IndexReg = Op.getImm();
20289 Op = MI->getOperand(3);
20290 if (Op.isGlobal()) {
20291 AM.GV = Op.getGlobal();
20292 } else {
20293 AM.Disp = Op.getImm();
20294 }
20295 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
20296 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
20298 // Reload the original control word now.
20299 addFrameReference(BuildMI(*BB, MI, DL,
20300 TII->get(X86::FLDCW16m)), CWFrameIdx);
20302 MI->eraseFromParent(); // The pseudo instruction is gone now.
20303 return BB;
20304 }
20305 // String/text processing lowering.
20306 case X86::PCMPISTRM128REG:
20307 case X86::VPCMPISTRM128REG:
20308 case X86::PCMPISTRM128MEM:
20309 case X86::VPCMPISTRM128MEM:
20310 case X86::PCMPESTRM128REG:
20311 case X86::VPCMPESTRM128REG:
20312 case X86::PCMPESTRM128MEM:
20313 case X86::VPCMPESTRM128MEM:
20314 assert(Subtarget->hasSSE42() &&
20315 "Target must have SSE4.2 or AVX features enabled");
20316 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
20318 // String/text processing lowering.
20319 case X86::PCMPISTRIREG:
20320 case X86::VPCMPISTRIREG:
20321 case X86::PCMPISTRIMEM:
20322 case X86::VPCMPISTRIMEM:
20323 case X86::PCMPESTRIREG:
20324 case X86::VPCMPESTRIREG:
20325 case X86::PCMPESTRIMEM:
20326 case X86::VPCMPESTRIMEM:
20327 assert(Subtarget->hasSSE42() &&
20328 "Target must have SSE4.2 or AVX features enabled");
20329 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
20331 // Thread synchronization.
20332 case X86::MONITOR:
20333 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
20334 Subtarget);
20336 // xbegin
20337 case X86::XBEGIN:
20338 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
20340 case X86::VASTART_SAVE_XMM_REGS:
20341 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
20343 case X86::VAARG_64:
20344 return EmitVAARG64WithCustomInserter(MI, BB);
20346 case X86::EH_SjLj_SetJmp32:
20347 case X86::EH_SjLj_SetJmp64:
20348 return emitEHSjLjSetJmp(MI, BB);
20350 case X86::EH_SjLj_LongJmp32:
20351 case X86::EH_SjLj_LongJmp64:
20352 return emitEHSjLjLongJmp(MI, BB);
20354 case TargetOpcode::STACKMAP:
20355 case TargetOpcode::PATCHPOINT:
20356 return emitPatchPoint(MI, BB);
20358 case X86::VFMADDPDr213r:
20359 case X86::VFMADDPSr213r:
20360 case X86::VFMADDSDr213r:
20361 case X86::VFMADDSSr213r:
20362 case X86::VFMSUBPDr213r:
20363 case X86::VFMSUBPSr213r:
20364 case X86::VFMSUBSDr213r:
20365 case X86::VFMSUBSSr213r:
20366 case X86::VFNMADDPDr213r:
20367 case X86::VFNMADDPSr213r:
20368 case X86::VFNMADDSDr213r:
20369 case X86::VFNMADDSSr213r:
20370 case X86::VFNMSUBPDr213r:
20371 case X86::VFNMSUBPSr213r:
20372 case X86::VFNMSUBSDr213r:
20373 case X86::VFNMSUBSSr213r:
20374 case X86::VFMADDPDr213rY:
20375 case X86::VFMADDPSr213rY:
20376 case X86::VFMSUBPDr213rY:
20377 case X86::VFMSUBPSr213rY:
20378 case X86::VFNMADDPDr213rY:
20379 case X86::VFNMADDPSr213rY:
20380 case X86::VFNMSUBPDr213rY:
20381 case X86::VFNMSUBPSr213rY:
20382 return emitFMA3Instr(MI, BB);
20383 }
20384 }
20386 //===----------------------------------------------------------------------===//
20387 // X86 Optimization Hooks
20388 //===----------------------------------------------------------------------===//
20390 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
20391 APInt &KnownZero,
20392 APInt &KnownOne,
20393 const SelectionDAG &DAG,
20394 unsigned Depth) const {
20395 unsigned BitWidth = KnownZero.getBitWidth();
20396 unsigned Opc = Op.getOpcode();
20397 assert((Opc >= ISD::BUILTIN_OP_END ||
20398 Opc == ISD::INTRINSIC_WO_CHAIN ||
20399 Opc == ISD::INTRINSIC_W_CHAIN ||
20400 Opc == ISD::INTRINSIC_VOID) &&
20401 "Should use MaskedValueIsZero if you don't know whether Op"
20402 " is a target node!");
20404 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
20405 switch (Opc) {
20406 default: break;
20407 case X86ISD::ADD:
20408 case X86ISD::SUB:
20409 case X86ISD::ADC:
20410 case X86ISD::SBB:
20411 case X86ISD::SMUL:
20412 case X86ISD::UMUL:
20413 case X86ISD::INC:
20414 case X86ISD::DEC:
20415 case X86ISD::OR:
20416 case X86ISD::XOR:
20417 case X86ISD::AND:
20418 // These nodes' second result is a boolean.
20419 if (Op.getResNo() == 0)
20420 break;
20421 // Fallthrough
20422 case X86ISD::SETCC:
20423 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
20424 break;
20425 case ISD::INTRINSIC_WO_CHAIN: {
20426 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
20427 unsigned NumLoBits = 0;
20428 switch (IntId) {
20429 default: break;
20430 case Intrinsic::x86_sse_movmsk_ps:
20431 case Intrinsic::x86_avx_movmsk_ps_256:
20432 case Intrinsic::x86_sse2_movmsk_pd:
20433 case Intrinsic::x86_avx_movmsk_pd_256:
20434 case Intrinsic::x86_mmx_pmovmskb:
20435 case Intrinsic::x86_sse2_pmovmskb_128:
20436 case Intrinsic::x86_avx2_pmovmskb: {
20437 // High bits of movmskp{s|d}, pmovmskb are known zero.
20438 switch (IntId) {
20439 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
20440 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
20441 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
20442 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
20443 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
20444 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
20445 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
20446 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
20447 }
20448 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
20449 break;
20450 }
20451 }
20452 break;
20453 }
20454 }
20455 }
20457 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
20458 SDValue Op,
20459 const SelectionDAG &,
20460 unsigned Depth) const {
20461 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
20462 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
20463 return Op.getValueType().getScalarType().getSizeInBits();
20465 // Fallback case.
20466 return 1;
20467 }
20469 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
20470 /// node is a GlobalAddress + offset.
20471 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
20472 const GlobalValue* &GA,
20473 int64_t &Offset) const {
20474 if (N->getOpcode() == X86ISD::Wrapper) {
20475 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
20476 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
20477 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
20478 return true;
20479 }
20480 }
20481 return TargetLowering::isGAPlusOffset(N, GA, Offset);
20482 }
20484 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
20485 /// same as extracting the high 128-bit part of 256-bit vector and then
20486 /// inserting the result into the low part of a new 256-bit vector
20487 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
20488 EVT VT = SVOp->getValueType(0);
20489 unsigned NumElems = VT.getVectorNumElements();
20491 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20492 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
20493 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
20494 SVOp->getMaskElt(j) >= 0)
20495 return false;
20497 return true;
20498 }
20500 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
20501 /// same as extracting the low 128-bit part of 256-bit vector and then
20502 /// inserting the result into the high part of a new 256-bit vector
20503 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
20504 EVT VT = SVOp->getValueType(0);
20505 unsigned NumElems = VT.getVectorNumElements();
20507 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20508 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
20509 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
20510 SVOp->getMaskElt(j) >= 0)
20511 return false;
20513 return true;
20514 }
20516 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
20517 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
20518 TargetLowering::DAGCombinerInfo &DCI,
20519 const X86Subtarget* Subtarget) {
20520 SDLoc dl(N);
20521 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
20522 SDValue V1 = SVOp->getOperand(0);
20523 SDValue V2 = SVOp->getOperand(1);
20524 EVT VT = SVOp->getValueType(0);
20525 unsigned NumElems = VT.getVectorNumElements();
20527 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
20528 V2.getOpcode() == ISD::CONCAT_VECTORS) {
20529 //
20530 // 0,0,0,...
20531 // |
20532 // V UNDEF BUILD_VECTOR UNDEF
20533 // \ / \ /
20534 // CONCAT_VECTOR CONCAT_VECTOR
20535 // \ /
20536 // \ /
20537 // RESULT: V + zero extended
20538 //
20539 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
20540 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
20541 V1.getOperand(1).getOpcode() != ISD::UNDEF)
20542 return SDValue();
20544 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
20545 return SDValue();
20547 // To match the shuffle mask, the first half of the mask should
20548 // be exactly the first vector, and all the rest a splat with the
20549 // first element of the second one.
20550 for (unsigned i = 0; i != NumElems/2; ++i)
20551 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
20552 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
20553 return SDValue();
20555 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
20556 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
20557 if (Ld->hasNUsesOfValue(1, 0)) {
20558 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
20559 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
20560 SDValue ResNode =
20561 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
20562 Ld->getMemoryVT(),
20563 Ld->getPointerInfo(),
20564 Ld->getAlignment(),
20565 false/*isVolatile*/, true/*ReadMem*/,
20566 false/*WriteMem*/);
20568 // Make sure the newly-created LOAD is in the same position as Ld in
20569 // terms of dependency. We create a TokenFactor for Ld and ResNode,
20570 // and update uses of Ld's output chain to use the TokenFactor.
20571 if (Ld->hasAnyUseOfValue(1)) {
20572 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
20573 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
20574 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
20575 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
20576 SDValue(ResNode.getNode(), 1));
20577 }
20579 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
20580 }
20581 }
20583 // Emit a zeroed vector and insert the desired subvector on its
20584 // first half.
20585 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
20586 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
20587 return DCI.CombineTo(N, InsV);
20588 }
20590 //===--------------------------------------------------------------------===//
20591 // Combine some shuffles into subvector extracts and inserts:
20592 //
20594 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20595 if (isShuffleHigh128VectorInsertLow(SVOp)) {
20596 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
20597 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
20598 return DCI.CombineTo(N, InsV);
20599 }
20601 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20602 if (isShuffleLow128VectorInsertHigh(SVOp)) {
20603 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
20604 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
20605 return DCI.CombineTo(N, InsV);
20606 }
20608 return SDValue();
20609 }
20611 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
20612 /// possible.
20613 ///
20614 /// This is the leaf of the recursive combinine below. When we have found some
20615 /// chain of single-use x86 shuffle instructions and accumulated the combined
20616 /// shuffle mask represented by them, this will try to pattern match that mask
20617 /// into either a single instruction if there is a special purpose instruction
20618 /// for this operation, or into a PSHUFB instruction which is a fully general
20619 /// instruction but should only be used to replace chains over a certain depth.
20620 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
20621 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
20622 TargetLowering::DAGCombinerInfo &DCI,
20623 const X86Subtarget *Subtarget) {
20624 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
20626 // Find the operand that enters the chain. Note that multiple uses are OK
20627 // here, we're not going to remove the operand we find.
20628 SDValue Input = Op.getOperand(0);
20629 while (Input.getOpcode() == ISD::BITCAST)
20630 Input = Input.getOperand(0);
20632 MVT VT = Input.getSimpleValueType();
20633 MVT RootVT = Root.getSimpleValueType();
20634 SDLoc DL(Root);
20636 // Just remove no-op shuffle masks.
20637 if (Mask.size() == 1) {
20638 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
20639 /*AddTo*/ true);
20640 return true;
20641 }
20643 // Use the float domain if the operand type is a floating point type.
20644 bool FloatDomain = VT.isFloatingPoint();
20646 // For floating point shuffles, we don't have free copies in the shuffle
20647 // instructions or the ability to load as part of the instruction, so
20648 // canonicalize their shuffles to UNPCK or MOV variants.
20649 //
20650 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
20651 // vectors because it can have a load folded into it that UNPCK cannot. This
20652 // doesn't preclude something switching to the shorter encoding post-RA.
20653 if (FloatDomain) {
20654 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
20655 bool Lo = Mask.equals(0, 0);
20656 unsigned Shuffle;
20657 MVT ShuffleVT;
20658 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
20659 // is no slower than UNPCKLPD but has the option to fold the input operand
20660 // into even an unaligned memory load.
20661 if (Lo && Subtarget->hasSSE3()) {
20662 Shuffle = X86ISD::MOVDDUP;
20663 ShuffleVT = MVT::v2f64;
20664 } else {
20665 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
20666 // than the UNPCK variants.
20667 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
20668 ShuffleVT = MVT::v4f32;
20669 }
20670 if (Depth == 1 && Root->getOpcode() == Shuffle)
20671 return false; // Nothing to do!
20672 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20673 DCI.AddToWorklist(Op.getNode());
20674 if (Shuffle == X86ISD::MOVDDUP)
20675 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20676 else
20677 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20678 DCI.AddToWorklist(Op.getNode());
20679 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20680 /*AddTo*/ true);
20681 return true;
20682 }
20683 if (Subtarget->hasSSE3() &&
20684 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
20685 bool Lo = Mask.equals(0, 0, 2, 2);
20686 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
20687 MVT ShuffleVT = MVT::v4f32;
20688 if (Depth == 1 && Root->getOpcode() == Shuffle)
20689 return false; // Nothing to do!
20690 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20691 DCI.AddToWorklist(Op.getNode());
20692 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20693 DCI.AddToWorklist(Op.getNode());
20694 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20695 /*AddTo*/ true);
20696 return true;
20697 }
20698 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
20699 bool Lo = Mask.equals(0, 0, 1, 1);
20700 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20701 MVT ShuffleVT = MVT::v4f32;
20702 if (Depth == 1 && Root->getOpcode() == Shuffle)
20703 return false; // Nothing to do!
20704 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20705 DCI.AddToWorklist(Op.getNode());
20706 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20707 DCI.AddToWorklist(Op.getNode());
20708 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20709 /*AddTo*/ true);
20710 return true;
20711 }
20712 }
20714 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
20715 // variants as none of these have single-instruction variants that are
20716 // superior to the UNPCK formulation.
20717 if (!FloatDomain &&
20718 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
20719 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
20720 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
20721 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
20722 15))) {
20723 bool Lo = Mask[0] == 0;
20724 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20725 if (Depth == 1 && Root->getOpcode() == Shuffle)
20726 return false; // Nothing to do!
20727 MVT ShuffleVT;
20728 switch (Mask.size()) {
20729 case 8:
20730 ShuffleVT = MVT::v8i16;
20731 break;
20732 case 16:
20733 ShuffleVT = MVT::v16i8;
20734 break;
20735 default:
20736 llvm_unreachable("Impossible mask size!");
20737 };
20738 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20739 DCI.AddToWorklist(Op.getNode());
20740 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20741 DCI.AddToWorklist(Op.getNode());
20742 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20743 /*AddTo*/ true);
20744 return true;
20745 }
20747 // Don't try to re-form single instruction chains under any circumstances now
20748 // that we've done encoding canonicalization for them.
20749 if (Depth < 2)
20750 return false;
20752 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
20753 // can replace them with a single PSHUFB instruction profitably. Intel's
20754 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
20755 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
20756 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
20757 SmallVector<SDValue, 16> PSHUFBMask;
20758 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
20759 int Ratio = 16 / Mask.size();
20760 for (unsigned i = 0; i < 16; ++i) {
20761 if (Mask[i / Ratio] == SM_SentinelUndef) {
20762 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
20763 continue;
20764 }
20765 int M = Mask[i / Ratio] != SM_SentinelZero
20766 ? Ratio * Mask[i / Ratio] + i % Ratio
20767 : 255;
20768 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
20769 }
20770 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
20771 DCI.AddToWorklist(Op.getNode());
20772 SDValue PSHUFBMaskOp =
20773 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
20774 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
20775 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
20776 DCI.AddToWorklist(Op.getNode());
20777 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20778 /*AddTo*/ true);
20779 return true;
20780 }
20782 // Failed to find any combines.
20783 return false;
20784 }
20786 /// \brief Fully generic combining of x86 shuffle instructions.
20787 ///
20788 /// This should be the last combine run over the x86 shuffle instructions. Once
20789 /// they have been fully optimized, this will recursively consider all chains
20790 /// of single-use shuffle instructions, build a generic model of the cumulative
20791 /// shuffle operation, and check for simpler instructions which implement this
20792 /// operation. We use this primarily for two purposes:
20793 ///
20794 /// 1) Collapse generic shuffles to specialized single instructions when
20795 /// equivalent. In most cases, this is just an encoding size win, but
20796 /// sometimes we will collapse multiple generic shuffles into a single
20797 /// special-purpose shuffle.
20798 /// 2) Look for sequences of shuffle instructions with 3 or more total
20799 /// instructions, and replace them with the slightly more expensive SSSE3
20800 /// PSHUFB instruction if available. We do this as the last combining step
20801 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
20802 /// a suitable short sequence of other instructions. The PHUFB will either
20803 /// use a register or have to read from memory and so is slightly (but only
20804 /// slightly) more expensive than the other shuffle instructions.
20805 ///
20806 /// Because this is inherently a quadratic operation (for each shuffle in
20807 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
20808 /// This should never be an issue in practice as the shuffle lowering doesn't
20809 /// produce sequences of more than 8 instructions.
20810 ///
20811 /// FIXME: We will currently miss some cases where the redundant shuffling
20812 /// would simplify under the threshold for PSHUFB formation because of
20813 /// combine-ordering. To fix this, we should do the redundant instruction
20814 /// combining in this recursive walk.
20815 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
20816 ArrayRef<int> RootMask,
20817 int Depth, bool HasPSHUFB,
20818 SelectionDAG &DAG,
20819 TargetLowering::DAGCombinerInfo &DCI,
20820 const X86Subtarget *Subtarget) {
20821 // Bound the depth of our recursive combine because this is ultimately
20822 // quadratic in nature.
20823 if (Depth > 8)
20824 return false;
20826 // Directly rip through bitcasts to find the underlying operand.
20827 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
20828 Op = Op.getOperand(0);
20830 MVT VT = Op.getSimpleValueType();
20831 if (!VT.isVector())
20832 return false; // Bail if we hit a non-vector.
20833 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
20834 // version should be added.
20835 if (VT.getSizeInBits() != 128)
20836 return false;
20838 assert(Root.getSimpleValueType().isVector() &&
20839 "Shuffles operate on vector types!");
20840 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
20841 "Can only combine shuffles of the same vector register size.");
20843 if (!isTargetShuffle(Op.getOpcode()))
20844 return false;
20845 SmallVector<int, 16> OpMask;
20846 bool IsUnary;
20847 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
20848 // We only can combine unary shuffles which we can decode the mask for.
20849 if (!HaveMask || !IsUnary)
20850 return false;
20852 assert(VT.getVectorNumElements() == OpMask.size() &&
20853 "Different mask size from vector size!");
20854 assert(((RootMask.size() > OpMask.size() &&
20855 RootMask.size() % OpMask.size() == 0) ||
20856 (OpMask.size() > RootMask.size() &&
20857 OpMask.size() % RootMask.size() == 0) ||
20858 OpMask.size() == RootMask.size()) &&
20859 "The smaller number of elements must divide the larger.");
20860 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
20861 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
20862 assert(((RootRatio == 1 && OpRatio == 1) ||
20863 (RootRatio == 1) != (OpRatio == 1)) &&
20864 "Must not have a ratio for both incoming and op masks!");
20866 SmallVector<int, 16> Mask;
20867 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
20869 // Merge this shuffle operation's mask into our accumulated mask. Note that
20870 // this shuffle's mask will be the first applied to the input, followed by the
20871 // root mask to get us all the way to the root value arrangement. The reason
20872 // for this order is that we are recursing up the operation chain.
20873 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
20874 int RootIdx = i / RootRatio;
20875 if (RootMask[RootIdx] < 0) {
20876 // This is a zero or undef lane, we're done.
20877 Mask.push_back(RootMask[RootIdx]);
20878 continue;
20879 }
20881 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
20882 int OpIdx = RootMaskedIdx / OpRatio;
20883 if (OpMask[OpIdx] < 0) {
20884 // The incoming lanes are zero or undef, it doesn't matter which ones we
20885 // are using.
20886 Mask.push_back(OpMask[OpIdx]);
20887 continue;
20888 }
20890 // Ok, we have non-zero lanes, map them through.
20891 Mask.push_back(OpMask[OpIdx] * OpRatio +
20892 RootMaskedIdx % OpRatio);
20893 }
20895 // See if we can recurse into the operand to combine more things.
20896 switch (Op.getOpcode()) {
20897 case X86ISD::PSHUFB:
20898 HasPSHUFB = true;
20899 case X86ISD::PSHUFD:
20900 case X86ISD::PSHUFHW:
20901 case X86ISD::PSHUFLW:
20902 if (Op.getOperand(0).hasOneUse() &&
20903 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20904 HasPSHUFB, DAG, DCI, Subtarget))
20905 return true;
20906 break;
20908 case X86ISD::UNPCKL:
20909 case X86ISD::UNPCKH:
20910 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
20911 // We can't check for single use, we have to check that this shuffle is the only user.
20912 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
20913 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20914 HasPSHUFB, DAG, DCI, Subtarget))
20915 return true;
20916 break;
20917 }
20919 // Minor canonicalization of the accumulated shuffle mask to make it easier
20920 // to match below. All this does is detect masks with squential pairs of
20921 // elements, and shrink them to the half-width mask. It does this in a loop
20922 // so it will reduce the size of the mask to the minimal width mask which
20923 // performs an equivalent shuffle.
20924 SmallVector<int, 16> WidenedMask;
20925 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
20926 Mask = std::move(WidenedMask);
20927 WidenedMask.clear();
20928 }
20930 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
20931 Subtarget);
20932 }
20934 /// \brief Get the PSHUF-style mask from PSHUF node.
20935 ///
20936 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
20937 /// PSHUF-style masks that can be reused with such instructions.
20938 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
20939 SmallVector<int, 4> Mask;
20940 bool IsUnary;
20941 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
20942 (void)HaveMask;
20943 assert(HaveMask);
20945 switch (N.getOpcode()) {
20946 case X86ISD::PSHUFD:
20947 return Mask;
20948 case X86ISD::PSHUFLW:
20949 Mask.resize(4);
20950 return Mask;
20951 case X86ISD::PSHUFHW:
20952 Mask.erase(Mask.begin(), Mask.begin() + 4);
20953 for (int &M : Mask)
20954 M -= 4;
20955 return Mask;
20956 default:
20957 llvm_unreachable("No valid shuffle instruction found!");
20958 }
20959 }
20961 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
20962 ///
20963 /// We walk up the chain and look for a combinable shuffle, skipping over
20964 /// shuffles that we could hoist this shuffle's transformation past without
20965 /// altering anything.
20966 static SDValue
20967 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
20968 SelectionDAG &DAG,
20969 TargetLowering::DAGCombinerInfo &DCI) {
20970 assert(N.getOpcode() == X86ISD::PSHUFD &&
20971 "Called with something other than an x86 128-bit half shuffle!");
20972 SDLoc DL(N);
20974 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
20975 // of the shuffles in the chain so that we can form a fresh chain to replace
20976 // this one.
20977 SmallVector<SDValue, 8> Chain;
20978 SDValue V = N.getOperand(0);
20979 for (; V.hasOneUse(); V = V.getOperand(0)) {
20980 switch (V.getOpcode()) {
20981 default:
20982 return SDValue(); // Nothing combined!
20984 case ISD::BITCAST:
20985 // Skip bitcasts as we always know the type for the target specific
20986 // instructions.
20987 continue;
20989 case X86ISD::PSHUFD:
20990 // Found another dword shuffle.
20991 break;
20993 case X86ISD::PSHUFLW:
20994 // Check that the low words (being shuffled) are the identity in the
20995 // dword shuffle, and the high words are self-contained.
20996 if (Mask[0] != 0 || Mask[1] != 1 ||
20997 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
20998 return SDValue();
21000 Chain.push_back(V);
21001 continue;
21003 case X86ISD::PSHUFHW:
21004 // Check that the high words (being shuffled) are the identity in the
21005 // dword shuffle, and the low words are self-contained.
21006 if (Mask[2] != 2 || Mask[3] != 3 ||
21007 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
21008 return SDValue();
21010 Chain.push_back(V);
21011 continue;
21013 case X86ISD::UNPCKL:
21014 case X86ISD::UNPCKH:
21015 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
21016 // shuffle into a preceding word shuffle.
21017 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
21018 return SDValue();
21020 // Search for a half-shuffle which we can combine with.
21021 unsigned CombineOp =
21022 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
21023 if (V.getOperand(0) != V.getOperand(1) ||
21024 !V->isOnlyUserOf(V.getOperand(0).getNode()))
21025 return SDValue();
21026 Chain.push_back(V);
21027 V = V.getOperand(0);
21028 do {
21029 switch (V.getOpcode()) {
21030 default:
21031 return SDValue(); // Nothing to combine.
21033 case X86ISD::PSHUFLW:
21034 case X86ISD::PSHUFHW:
21035 if (V.getOpcode() == CombineOp)
21036 break;
21038 Chain.push_back(V);
21040 // Fallthrough!
21041 case ISD::BITCAST:
21042 V = V.getOperand(0);
21043 continue;
21044 }
21045 break;
21046 } while (V.hasOneUse());
21047 break;
21048 }
21049 // Break out of the loop if we break out of the switch.
21050 break;
21051 }
21053 if (!V.hasOneUse())
21054 // We fell out of the loop without finding a viable combining instruction.
21055 return SDValue();
21057 // Merge this node's mask and our incoming mask.
21058 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21059 for (int &M : Mask)
21060 M = VMask[M];
21061 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
21062 getV4X86ShuffleImm8ForMask(Mask, DAG));
21064 // Rebuild the chain around this new shuffle.
21065 while (!Chain.empty()) {
21066 SDValue W = Chain.pop_back_val();
21068 if (V.getValueType() != W.getOperand(0).getValueType())
21069 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
21071 switch (W.getOpcode()) {
21072 default:
21073 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
21075 case X86ISD::UNPCKL:
21076 case X86ISD::UNPCKH:
21077 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
21078 break;
21080 case X86ISD::PSHUFD:
21081 case X86ISD::PSHUFLW:
21082 case X86ISD::PSHUFHW:
21083 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
21084 break;
21085 }
21086 }
21087 if (V.getValueType() != N.getValueType())
21088 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
21090 // Return the new chain to replace N.
21091 return V;
21092 }
21094 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
21095 ///
21096 /// We walk up the chain, skipping shuffles of the other half and looking
21097 /// through shuffles which switch halves trying to find a shuffle of the same
21098 /// pair of dwords.
21099 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
21100 SelectionDAG &DAG,
21101 TargetLowering::DAGCombinerInfo &DCI) {
21102 assert(
21103 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
21104 "Called with something other than an x86 128-bit half shuffle!");
21105 SDLoc DL(N);
21106 unsigned CombineOpcode = N.getOpcode();
21108 // Walk up a single-use chain looking for a combinable shuffle.
21109 SDValue V = N.getOperand(0);
21110 for (; V.hasOneUse(); V = V.getOperand(0)) {
21111 switch (V.getOpcode()) {
21112 default:
21113 return false; // Nothing combined!
21115 case ISD::BITCAST:
21116 // Skip bitcasts as we always know the type for the target specific
21117 // instructions.
21118 continue;
21120 case X86ISD::PSHUFLW:
21121 case X86ISD::PSHUFHW:
21122 if (V.getOpcode() == CombineOpcode)
21123 break;
21125 // Other-half shuffles are no-ops.
21126 continue;
21127 }
21128 // Break out of the loop if we break out of the switch.
21129 break;
21130 }
21132 if (!V.hasOneUse())
21133 // We fell out of the loop without finding a viable combining instruction.
21134 return false;
21136 // Combine away the bottom node as its shuffle will be accumulated into
21137 // a preceding shuffle.
21138 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
21140 // Record the old value.
21141 SDValue Old = V;
21143 // Merge this node's mask and our incoming mask (adjusted to account for all
21144 // the pshufd instructions encountered).
21145 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21146 for (int &M : Mask)
21147 M = VMask[M];
21148 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
21149 getV4X86ShuffleImm8ForMask(Mask, DAG));
21151 // Check that the shuffles didn't cancel each other out. If not, we need to
21152 // combine to the new one.
21153 if (Old != V)
21154 // Replace the combinable shuffle with the combined one, updating all users
21155 // so that we re-evaluate the chain here.
21156 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
21158 return true;
21159 }
21161 /// \brief Try to combine x86 target specific shuffles.
21162 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
21163 TargetLowering::DAGCombinerInfo &DCI,
21164 const X86Subtarget *Subtarget) {
21165 SDLoc DL(N);
21166 MVT VT = N.getSimpleValueType();
21167 SmallVector<int, 4> Mask;
21169 switch (N.getOpcode()) {
21170 case X86ISD::PSHUFD:
21171 case X86ISD::PSHUFLW:
21172 case X86ISD::PSHUFHW:
21173 Mask = getPSHUFShuffleMask(N);
21174 assert(Mask.size() == 4);
21175 break;
21176 default:
21177 return SDValue();
21178 }
21180 // Nuke no-op shuffles that show up after combining.
21181 if (isNoopShuffleMask(Mask))
21182 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
21184 // Look for simplifications involving one or two shuffle instructions.
21185 SDValue V = N.getOperand(0);
21186 switch (N.getOpcode()) {
21187 default:
21188 break;
21189 case X86ISD::PSHUFLW:
21190 case X86ISD::PSHUFHW:
21191 assert(VT == MVT::v8i16);
21192 (void)VT;
21194 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
21195 return SDValue(); // We combined away this shuffle, so we're done.
21197 // See if this reduces to a PSHUFD which is no more expensive and can
21198 // combine with more operations. Note that it has to at least flip the
21199 // dwords as otherwise it would have been removed as a no-op.
21200 if (Mask[0] == 2 && Mask[1] == 3 && Mask[2] == 0 && Mask[3] == 1) {
21201 int DMask[] = {0, 1, 2, 3};
21202 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
21203 DMask[DOffset + 0] = DOffset + 1;
21204 DMask[DOffset + 1] = DOffset + 0;
21205 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
21206 DCI.AddToWorklist(V.getNode());
21207 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
21208 getV4X86ShuffleImm8ForMask(DMask, DAG));
21209 DCI.AddToWorklist(V.getNode());
21210 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
21211 }
21213 // Look for shuffle patterns which can be implemented as a single unpack.
21214 // FIXME: This doesn't handle the location of the PSHUFD generically, and
21215 // only works when we have a PSHUFD followed by two half-shuffles.
21216 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
21217 (V.getOpcode() == X86ISD::PSHUFLW ||
21218 V.getOpcode() == X86ISD::PSHUFHW) &&
21219 V.getOpcode() != N.getOpcode() &&
21220 V.hasOneUse()) {
21221 SDValue D = V.getOperand(0);
21222 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
21223 D = D.getOperand(0);
21224 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
21225 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21226 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
21227 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
21228 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
21229 int WordMask[8];
21230 for (int i = 0; i < 4; ++i) {
21231 WordMask[i + NOffset] = Mask[i] + NOffset;
21232 WordMask[i + VOffset] = VMask[i] + VOffset;
21233 }
21234 // Map the word mask through the DWord mask.
21235 int MappedMask[8];
21236 for (int i = 0; i < 8; ++i)
21237 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
21238 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
21239 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
21240 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
21241 std::begin(UnpackLoMask)) ||
21242 std::equal(std::begin(MappedMask), std::end(MappedMask),
21243 std::begin(UnpackHiMask))) {
21244 // We can replace all three shuffles with an unpack.
21245 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
21246 DCI.AddToWorklist(V.getNode());
21247 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
21248 : X86ISD::UNPCKH,
21249 DL, MVT::v8i16, V, V);
21250 }
21251 }
21252 }
21254 break;
21256 case X86ISD::PSHUFD:
21257 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
21258 return NewN;
21260 break;
21261 }
21263 return SDValue();
21264 }
21266 /// \brief Try to combine a shuffle into a target-specific add-sub node.
21267 ///
21268 /// We combine this directly on the abstract vector shuffle nodes so it is
21269 /// easier to generically match. We also insert dummy vector shuffle nodes for
21270 /// the operands which explicitly discard the lanes which are unused by this
21271 /// operation to try to flow through the rest of the combiner the fact that
21272 /// they're unused.
21273 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
21274 SDLoc DL(N);
21275 EVT VT = N->getValueType(0);
21277 // We only handle target-independent shuffles.
21278 // FIXME: It would be easy and harmless to use the target shuffle mask
21279 // extraction tool to support more.
21280 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
21281 return SDValue();
21283 auto *SVN = cast<ShuffleVectorSDNode>(N);
21284 ArrayRef<int> Mask = SVN->getMask();
21285 SDValue V1 = N->getOperand(0);
21286 SDValue V2 = N->getOperand(1);
21288 // We require the first shuffle operand to be the SUB node, and the second to
21289 // be the ADD node.
21290 // FIXME: We should support the commuted patterns.
21291 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
21292 return SDValue();
21294 // If there are other uses of these operations we can't fold them.
21295 if (!V1->hasOneUse() || !V2->hasOneUse())
21296 return SDValue();
21298 // Ensure that both operations have the same operands. Note that we can
21299 // commute the FADD operands.
21300 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
21301 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
21302 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
21303 return SDValue();
21305 // We're looking for blends between FADD and FSUB nodes. We insist on these
21306 // nodes being lined up in a specific expected pattern.
21307 if (!(isShuffleEquivalent(Mask, 0, 3) ||
21308 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
21309 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
21310 return SDValue();
21312 // Only specific types are legal at this point, assert so we notice if and
21313 // when these change.
21314 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
21315 VT == MVT::v4f64) &&
21316 "Unknown vector type encountered!");
21318 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
21319 }
21321 /// PerformShuffleCombine - Performs several different shuffle combines.
21322 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
21323 TargetLowering::DAGCombinerInfo &DCI,
21324 const X86Subtarget *Subtarget) {
21325 SDLoc dl(N);
21326 SDValue N0 = N->getOperand(0);
21327 SDValue N1 = N->getOperand(1);
21328 EVT VT = N->getValueType(0);
21330 // Don't create instructions with illegal types after legalize types has run.
21331 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21332 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
21333 return SDValue();
21335 // If we have legalized the vector types, look for blends of FADD and FSUB
21336 // nodes that we can fuse into an ADDSUB node.
21337 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
21338 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
21339 return AddSub;
21341 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
21342 if (Subtarget->hasFp256() && VT.is256BitVector() &&
21343 N->getOpcode() == ISD::VECTOR_SHUFFLE)
21344 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
21346 // During Type Legalization, when promoting illegal vector types,
21347 // the backend might introduce new shuffle dag nodes and bitcasts.
21348 //
21349 // This code performs the following transformation:
21350 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
21351 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
21352 //
21353 // We do this only if both the bitcast and the BINOP dag nodes have
21354 // one use. Also, perform this transformation only if the new binary
21355 // operation is legal. This is to avoid introducing dag nodes that
21356 // potentially need to be further expanded (or custom lowered) into a
21357 // less optimal sequence of dag nodes.
21358 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
21359 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
21360 N0.getOpcode() == ISD::BITCAST) {
21361 SDValue BC0 = N0.getOperand(0);
21362 EVT SVT = BC0.getValueType();
21363 unsigned Opcode = BC0.getOpcode();
21364 unsigned NumElts = VT.getVectorNumElements();
21366 if (BC0.hasOneUse() && SVT.isVector() &&
21367 SVT.getVectorNumElements() * 2 == NumElts &&
21368 TLI.isOperationLegal(Opcode, VT)) {
21369 bool CanFold = false;
21370 switch (Opcode) {
21371 default : break;
21372 case ISD::ADD :
21373 case ISD::FADD :
21374 case ISD::SUB :
21375 case ISD::FSUB :
21376 case ISD::MUL :
21377 case ISD::FMUL :
21378 CanFold = true;
21379 }
21381 unsigned SVTNumElts = SVT.getVectorNumElements();
21382 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21383 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
21384 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
21385 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
21386 CanFold = SVOp->getMaskElt(i) < 0;
21388 if (CanFold) {
21389 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
21390 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
21391 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
21392 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
21393 }
21394 }
21395 }
21397 // Only handle 128 wide vector from here on.
21398 if (!VT.is128BitVector())
21399 return SDValue();
21401 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
21402 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
21403 // consecutive, non-overlapping, and in the right order.
21404 SmallVector<SDValue, 16> Elts;
21405 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
21406 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
21408 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
21409 if (LD.getNode())
21410 return LD;
21412 if (isTargetShuffle(N->getOpcode())) {
21413 SDValue Shuffle =
21414 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
21415 if (Shuffle.getNode())
21416 return Shuffle;
21418 // Try recursively combining arbitrary sequences of x86 shuffle
21419 // instructions into higher-order shuffles. We do this after combining
21420 // specific PSHUF instruction sequences into their minimal form so that we
21421 // can evaluate how many specialized shuffle instructions are involved in
21422 // a particular chain.
21423 SmallVector<int, 1> NonceMask; // Just a placeholder.
21424 NonceMask.push_back(0);
21425 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
21426 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
21427 DCI, Subtarget))
21428 return SDValue(); // This routine will use CombineTo to replace N.
21429 }
21431 return SDValue();
21432 }
21434 /// PerformTruncateCombine - Converts truncate operation to
21435 /// a sequence of vector shuffle operations.
21436 /// It is possible when we truncate 256-bit vector to 128-bit vector
21437 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
21438 TargetLowering::DAGCombinerInfo &DCI,
21439 const X86Subtarget *Subtarget) {
21440 return SDValue();
21441 }
21443 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
21444 /// specific shuffle of a load can be folded into a single element load.
21445 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
21446 /// shuffles have been customed lowered so we need to handle those here.
21447 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
21448 TargetLowering::DAGCombinerInfo &DCI) {
21449 if (DCI.isBeforeLegalizeOps())
21450 return SDValue();
21452 SDValue InVec = N->getOperand(0);
21453 SDValue EltNo = N->getOperand(1);
21455 if (!isa<ConstantSDNode>(EltNo))
21456 return SDValue();
21458 EVT VT = InVec.getValueType();
21460 if (InVec.getOpcode() == ISD::BITCAST) {
21461 // Don't duplicate a load with other uses.
21462 if (!InVec.hasOneUse())
21463 return SDValue();
21464 EVT BCVT = InVec.getOperand(0).getValueType();
21465 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
21466 return SDValue();
21467 InVec = InVec.getOperand(0);
21468 }
21470 if (!isTargetShuffle(InVec.getOpcode()))
21471 return SDValue();
21473 // Don't duplicate a load with other uses.
21474 if (!InVec.hasOneUse())
21475 return SDValue();
21477 SmallVector<int, 16> ShuffleMask;
21478 bool UnaryShuffle;
21479 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
21480 UnaryShuffle))
21481 return SDValue();
21483 // Select the input vector, guarding against out of range extract vector.
21484 unsigned NumElems = VT.getVectorNumElements();
21485 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
21486 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
21487 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
21488 : InVec.getOperand(1);
21490 // If inputs to shuffle are the same for both ops, then allow 2 uses
21491 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
21493 if (LdNode.getOpcode() == ISD::BITCAST) {
21494 // Don't duplicate a load with other uses.
21495 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
21496 return SDValue();
21498 AllowedUses = 1; // only allow 1 load use if we have a bitcast
21499 LdNode = LdNode.getOperand(0);
21500 }
21502 if (!ISD::isNormalLoad(LdNode.getNode()))
21503 return SDValue();
21505 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
21507 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
21508 return SDValue();
21510 EVT EltVT = N->getValueType(0);
21511 // If there's a bitcast before the shuffle, check if the load type and
21512 // alignment is valid.
21513 unsigned Align = LN0->getAlignment();
21514 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21515 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
21516 EltVT.getTypeForEVT(*DAG.getContext()));
21518 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
21519 return SDValue();
21521 // All checks match so transform back to vector_shuffle so that DAG combiner
21522 // can finish the job
21523 SDLoc dl(N);
21525 // Create shuffle node taking into account the case that its a unary shuffle
21526 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
21527 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
21528 InVec.getOperand(0), Shuffle,
21529 &ShuffleMask[0]);
21530 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
21531 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
21532 EltNo);
21533 }
21535 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
21536 /// generation and convert it from being a bunch of shuffles and extracts
21537 /// to a simple store and scalar loads to extract the elements.
21538 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
21539 TargetLowering::DAGCombinerInfo &DCI) {
21540 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
21541 if (NewOp.getNode())
21542 return NewOp;
21544 SDValue InputVector = N->getOperand(0);
21546 // Detect whether we are trying to convert from mmx to i32 and the bitcast
21547 // from mmx to v2i32 has a single usage.
21548 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
21549 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
21550 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
21551 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
21552 N->getValueType(0),
21553 InputVector.getNode()->getOperand(0));
21555 // Only operate on vectors of 4 elements, where the alternative shuffling
21556 // gets to be more expensive.
21557 if (InputVector.getValueType() != MVT::v4i32)
21558 return SDValue();
21560 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
21561 // single use which is a sign-extend or zero-extend, and all elements are
21562 // used.
21563 SmallVector<SDNode *, 4> Uses;
21564 unsigned ExtractedElements = 0;
21565 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
21566 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
21567 if (UI.getUse().getResNo() != InputVector.getResNo())
21568 return SDValue();
21570 SDNode *Extract = *UI;
21571 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
21572 return SDValue();
21574 if (Extract->getValueType(0) != MVT::i32)
21575 return SDValue();
21576 if (!Extract->hasOneUse())
21577 return SDValue();
21578 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
21579 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
21580 return SDValue();
21581 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
21582 return SDValue();
21584 // Record which element was extracted.
21585 ExtractedElements |=
21586 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
21588 Uses.push_back(Extract);
21589 }
21591 // If not all the elements were used, this may not be worthwhile.
21592 if (ExtractedElements != 15)
21593 return SDValue();
21595 // Ok, we've now decided to do the transformation.
21596 SDLoc dl(InputVector);
21598 // Store the value to a temporary stack slot.
21599 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
21600 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
21601 MachinePointerInfo(), false, false, 0);
21603 // Replace each use (extract) with a load of the appropriate element.
21604 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
21605 UE = Uses.end(); UI != UE; ++UI) {
21606 SDNode *Extract = *UI;
21608 // cOMpute the element's address.
21609 SDValue Idx = Extract->getOperand(1);
21610 unsigned EltSize =
21611 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
21612 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
21613 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21614 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
21616 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
21617 StackPtr, OffsetVal);
21619 // Load the scalar.
21620 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
21621 ScalarAddr, MachinePointerInfo(),
21622 false, false, false, 0);
21624 // Replace the exact with the load.
21625 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
21626 }
21628 // The replacement was made in place; don't return anything.
21629 return SDValue();
21630 }
21632 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
21633 static std::pair<unsigned, bool>
21634 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
21635 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
21636 if (!VT.isVector())
21637 return std::make_pair(0, false);
21639 bool NeedSplit = false;
21640 switch (VT.getSimpleVT().SimpleTy) {
21641 default: return std::make_pair(0, false);
21642 case MVT::v32i8:
21643 case MVT::v16i16:
21644 case MVT::v8i32:
21645 if (!Subtarget->hasAVX2())
21646 NeedSplit = true;
21647 if (!Subtarget->hasAVX())
21648 return std::make_pair(0, false);
21649 break;
21650 case MVT::v16i8:
21651 case MVT::v8i16:
21652 case MVT::v4i32:
21653 if (!Subtarget->hasSSE2())
21654 return std::make_pair(0, false);
21655 }
21657 // SSE2 has only a small subset of the operations.
21658 bool hasUnsigned = Subtarget->hasSSE41() ||
21659 (Subtarget->hasSSE2() && VT == MVT::v16i8);
21660 bool hasSigned = Subtarget->hasSSE41() ||
21661 (Subtarget->hasSSE2() && VT == MVT::v8i16);
21663 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21665 unsigned Opc = 0;
21666 // Check for x CC y ? x : y.
21667 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21668 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21669 switch (CC) {
21670 default: break;
21671 case ISD::SETULT:
21672 case ISD::SETULE:
21673 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
21674 case ISD::SETUGT:
21675 case ISD::SETUGE:
21676 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
21677 case ISD::SETLT:
21678 case ISD::SETLE:
21679 Opc = hasSigned ? X86ISD::SMIN : 0; break;
21680 case ISD::SETGT:
21681 case ISD::SETGE:
21682 Opc = hasSigned ? X86ISD::SMAX : 0; break;
21683 }
21684 // Check for x CC y ? y : x -- a min/max with reversed arms.
21685 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21686 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21687 switch (CC) {
21688 default: break;
21689 case ISD::SETULT:
21690 case ISD::SETULE:
21691 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
21692 case ISD::SETUGT:
21693 case ISD::SETUGE:
21694 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
21695 case ISD::SETLT:
21696 case ISD::SETLE:
21697 Opc = hasSigned ? X86ISD::SMAX : 0; break;
21698 case ISD::SETGT:
21699 case ISD::SETGE:
21700 Opc = hasSigned ? X86ISD::SMIN : 0; break;
21701 }
21702 }
21704 return std::make_pair(Opc, NeedSplit);
21705 }
21707 static SDValue
21708 TransformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
21709 const X86Subtarget *Subtarget) {
21710 SDLoc dl(N);
21711 SDValue Cond = N->getOperand(0);
21712 SDValue LHS = N->getOperand(1);
21713 SDValue RHS = N->getOperand(2);
21715 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
21716 SDValue CondSrc = Cond->getOperand(0);
21717 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
21718 Cond = CondSrc->getOperand(0);
21719 }
21721 MVT VT = N->getSimpleValueType(0);
21722 MVT EltVT = VT.getVectorElementType();
21723 unsigned NumElems = VT.getVectorNumElements();
21724 // There is no blend with immediate in AVX-512.
21725 if (VT.is512BitVector())
21726 return SDValue();
21728 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
21729 return SDValue();
21730 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
21731 return SDValue();
21733 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
21734 return SDValue();
21736 // A vselect where all conditions and data are constants can be optimized into
21737 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
21738 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
21739 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
21740 return SDValue();
21742 unsigned MaskValue = 0;
21743 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
21744 return SDValue();
21746 SmallVector<int, 8> ShuffleMask(NumElems, -1);
21747 for (unsigned i = 0; i < NumElems; ++i) {
21748 // Be sure we emit undef where we can.
21749 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
21750 ShuffleMask[i] = -1;
21751 else
21752 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
21753 }
21755 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
21756 }
21758 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
21759 /// nodes.
21760 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
21761 TargetLowering::DAGCombinerInfo &DCI,
21762 const X86Subtarget *Subtarget) {
21763 SDLoc DL(N);
21764 SDValue Cond = N->getOperand(0);
21765 // Get the LHS/RHS of the select.
21766 SDValue LHS = N->getOperand(1);
21767 SDValue RHS = N->getOperand(2);
21768 EVT VT = LHS.getValueType();
21769 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21771 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
21772 // instructions match the semantics of the common C idiom x<y?x:y but not
21773 // x<=y?x:y, because of how they handle negative zero (which can be
21774 // ignored in unsafe-math mode).
21775 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
21776 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
21777 (Subtarget->hasSSE2() ||
21778 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
21779 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21781 unsigned Opcode = 0;
21782 // Check for x CC y ? x : y.
21783 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21784 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21785 switch (CC) {
21786 default: break;
21787 case ISD::SETULT:
21788 // Converting this to a min would handle NaNs incorrectly, and swapping
21789 // the operands would cause it to handle comparisons between positive
21790 // and negative zero incorrectly.
21791 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21792 if (!DAG.getTarget().Options.UnsafeFPMath &&
21793 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21794 break;
21795 std::swap(LHS, RHS);
21796 }
21797 Opcode = X86ISD::FMIN;
21798 break;
21799 case ISD::SETOLE:
21800 // Converting this to a min would handle comparisons between positive
21801 // and negative zero incorrectly.
21802 if (!DAG.getTarget().Options.UnsafeFPMath &&
21803 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21804 break;
21805 Opcode = X86ISD::FMIN;
21806 break;
21807 case ISD::SETULE:
21808 // Converting this to a min would handle both negative zeros and NaNs
21809 // incorrectly, but we can swap the operands to fix both.
21810 std::swap(LHS, RHS);
21811 case ISD::SETOLT:
21812 case ISD::SETLT:
21813 case ISD::SETLE:
21814 Opcode = X86ISD::FMIN;
21815 break;
21817 case ISD::SETOGE:
21818 // Converting this to a max would handle comparisons between positive
21819 // and negative zero incorrectly.
21820 if (!DAG.getTarget().Options.UnsafeFPMath &&
21821 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21822 break;
21823 Opcode = X86ISD::FMAX;
21824 break;
21825 case ISD::SETUGT:
21826 // Converting this to a max would handle NaNs incorrectly, and swapping
21827 // the operands would cause it to handle comparisons between positive
21828 // and negative zero incorrectly.
21829 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21830 if (!DAG.getTarget().Options.UnsafeFPMath &&
21831 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21832 break;
21833 std::swap(LHS, RHS);
21834 }
21835 Opcode = X86ISD::FMAX;
21836 break;
21837 case ISD::SETUGE:
21838 // Converting this to a max would handle both negative zeros and NaNs
21839 // incorrectly, but we can swap the operands to fix both.
21840 std::swap(LHS, RHS);
21841 case ISD::SETOGT:
21842 case ISD::SETGT:
21843 case ISD::SETGE:
21844 Opcode = X86ISD::FMAX;
21845 break;
21846 }
21847 // Check for x CC y ? y : x -- a min/max with reversed arms.
21848 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21849 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21850 switch (CC) {
21851 default: break;
21852 case ISD::SETOGE:
21853 // Converting this to a min would handle comparisons between positive
21854 // and negative zero incorrectly, and swapping the operands would
21855 // cause it to handle NaNs incorrectly.
21856 if (!DAG.getTarget().Options.UnsafeFPMath &&
21857 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
21858 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21859 break;
21860 std::swap(LHS, RHS);
21861 }
21862 Opcode = X86ISD::FMIN;
21863 break;
21864 case ISD::SETUGT:
21865 // Converting this to a min would handle NaNs incorrectly.
21866 if (!DAG.getTarget().Options.UnsafeFPMath &&
21867 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
21868 break;
21869 Opcode = X86ISD::FMIN;
21870 break;
21871 case ISD::SETUGE:
21872 // Converting this to a min would handle both negative zeros and NaNs
21873 // incorrectly, but we can swap the operands to fix both.
21874 std::swap(LHS, RHS);
21875 case ISD::SETOGT:
21876 case ISD::SETGT:
21877 case ISD::SETGE:
21878 Opcode = X86ISD::FMIN;
21879 break;
21881 case ISD::SETULT:
21882 // Converting this to a max would handle NaNs incorrectly.
21883 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21884 break;
21885 Opcode = X86ISD::FMAX;
21886 break;
21887 case ISD::SETOLE:
21888 // Converting this to a max would handle comparisons between positive
21889 // and negative zero incorrectly, and swapping the operands would
21890 // cause it to handle NaNs incorrectly.
21891 if (!DAG.getTarget().Options.UnsafeFPMath &&
21892 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
21893 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21894 break;
21895 std::swap(LHS, RHS);
21896 }
21897 Opcode = X86ISD::FMAX;
21898 break;
21899 case ISD::SETULE:
21900 // Converting this to a max would handle both negative zeros and NaNs
21901 // incorrectly, but we can swap the operands to fix both.
21902 std::swap(LHS, RHS);
21903 case ISD::SETOLT:
21904 case ISD::SETLT:
21905 case ISD::SETLE:
21906 Opcode = X86ISD::FMAX;
21907 break;
21908 }
21909 }
21911 if (Opcode)
21912 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
21913 }
21915 EVT CondVT = Cond.getValueType();
21916 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
21917 CondVT.getVectorElementType() == MVT::i1) {
21918 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
21919 // lowering on KNL. In this case we convert it to
21920 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
21921 // The same situation for all 128 and 256-bit vectors of i8 and i16.
21922 // Since SKX these selects have a proper lowering.
21923 EVT OpVT = LHS.getValueType();
21924 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
21925 (OpVT.getVectorElementType() == MVT::i8 ||
21926 OpVT.getVectorElementType() == MVT::i16) &&
21927 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
21928 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
21929 DCI.AddToWorklist(Cond.getNode());
21930 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
21931 }
21932 }
21933 // If this is a select between two integer constants, try to do some
21934 // optimizations.
21935 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
21936 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
21937 // Don't do this for crazy integer types.
21938 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
21939 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
21940 // so that TrueC (the true value) is larger than FalseC.
21941 bool NeedsCondInvert = false;
21943 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
21944 // Efficiently invertible.
21945 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
21946 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
21947 isa<ConstantSDNode>(Cond.getOperand(1))))) {
21948 NeedsCondInvert = true;
21949 std::swap(TrueC, FalseC);
21950 }
21952 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
21953 if (FalseC->getAPIntValue() == 0 &&
21954 TrueC->getAPIntValue().isPowerOf2()) {
21955 if (NeedsCondInvert) // Invert the condition if needed.
21956 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21957 DAG.getConstant(1, Cond.getValueType()));
21959 // Zero extend the condition if needed.
21960 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
21962 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
21963 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
21964 DAG.getConstant(ShAmt, MVT::i8));
21965 }
21967 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
21968 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
21969 if (NeedsCondInvert) // Invert the condition if needed.
21970 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21971 DAG.getConstant(1, Cond.getValueType()));
21973 // Zero extend the condition if needed.
21974 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
21975 FalseC->getValueType(0), Cond);
21976 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21977 SDValue(FalseC, 0));
21978 }
21980 // Optimize cases that will turn into an LEA instruction. This requires
21981 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
21982 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
21983 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
21984 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
21986 bool isFastMultiplier = false;
21987 if (Diff < 10) {
21988 switch ((unsigned char)Diff) {
21989 default: break;
21990 case 1: // result = add base, cond
21991 case 2: // result = lea base( , cond*2)
21992 case 3: // result = lea base(cond, cond*2)
21993 case 4: // result = lea base( , cond*4)
21994 case 5: // result = lea base(cond, cond*4)
21995 case 8: // result = lea base( , cond*8)
21996 case 9: // result = lea base(cond, cond*8)
21997 isFastMultiplier = true;
21998 break;
21999 }
22000 }
22002 if (isFastMultiplier) {
22003 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22004 if (NeedsCondInvert) // Invert the condition if needed.
22005 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22006 DAG.getConstant(1, Cond.getValueType()));
22008 // Zero extend the condition if needed.
22009 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22010 Cond);
22011 // Scale the condition by the difference.
22012 if (Diff != 1)
22013 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22014 DAG.getConstant(Diff, Cond.getValueType()));
22016 // Add the base if non-zero.
22017 if (FalseC->getAPIntValue() != 0)
22018 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22019 SDValue(FalseC, 0));
22020 return Cond;
22021 }
22022 }
22023 }
22024 }
22026 // Canonicalize max and min:
22027 // (x > y) ? x : y -> (x >= y) ? x : y
22028 // (x < y) ? x : y -> (x <= y) ? x : y
22029 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
22030 // the need for an extra compare
22031 // against zero. e.g.
22032 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
22033 // subl %esi, %edi
22034 // testl %edi, %edi
22035 // movl $0, %eax
22036 // cmovgl %edi, %eax
22037 // =>
22038 // xorl %eax, %eax
22039 // subl %esi, $edi
22040 // cmovsl %eax, %edi
22041 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
22042 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22043 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22044 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22045 switch (CC) {
22046 default: break;
22047 case ISD::SETLT:
22048 case ISD::SETGT: {
22049 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
22050 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
22051 Cond.getOperand(0), Cond.getOperand(1), NewCC);
22052 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
22053 }
22054 }
22055 }
22057 // Early exit check
22058 if (!TLI.isTypeLegal(VT))
22059 return SDValue();
22061 // Match VSELECTs into subs with unsigned saturation.
22062 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
22063 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
22064 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
22065 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
22066 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22068 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
22069 // left side invert the predicate to simplify logic below.
22070 SDValue Other;
22071 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
22072 Other = RHS;
22073 CC = ISD::getSetCCInverse(CC, true);
22074 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
22075 Other = LHS;
22076 }
22078 if (Other.getNode() && Other->getNumOperands() == 2 &&
22079 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
22080 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
22081 SDValue CondRHS = Cond->getOperand(1);
22083 // Look for a general sub with unsigned saturation first.
22084 // x >= y ? x-y : 0 --> subus x, y
22085 // x > y ? x-y : 0 --> subus x, y
22086 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
22087 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
22088 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
22090 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
22091 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
22092 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
22093 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
22094 // If the RHS is a constant we have to reverse the const
22095 // canonicalization.
22096 // x > C-1 ? x+-C : 0 --> subus x, C
22097 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
22098 CondRHSConst->getAPIntValue() ==
22099 (-OpRHSConst->getAPIntValue() - 1))
22100 return DAG.getNode(
22101 X86ISD::SUBUS, DL, VT, OpLHS,
22102 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
22104 // Another special case: If C was a sign bit, the sub has been
22105 // canonicalized into a xor.
22106 // FIXME: Would it be better to use computeKnownBits to determine
22107 // whether it's safe to decanonicalize the xor?
22108 // x s< 0 ? x^C : 0 --> subus x, C
22109 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
22110 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
22111 OpRHSConst->getAPIntValue().isSignBit())
22112 // Note that we have to rebuild the RHS constant here to ensure we
22113 // don't rely on particular values of undef lanes.
22114 return DAG.getNode(
22115 X86ISD::SUBUS, DL, VT, OpLHS,
22116 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
22117 }
22118 }
22119 }
22121 // Try to match a min/max vector operation.
22122 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
22123 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
22124 unsigned Opc = ret.first;
22125 bool NeedSplit = ret.second;
22127 if (Opc && NeedSplit) {
22128 unsigned NumElems = VT.getVectorNumElements();
22129 // Extract the LHS vectors
22130 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
22131 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
22133 // Extract the RHS vectors
22134 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
22135 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
22137 // Create min/max for each subvector
22138 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
22139 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
22141 // Merge the result
22142 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
22143 } else if (Opc)
22144 return DAG.getNode(Opc, DL, VT, LHS, RHS);
22145 }
22147 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
22148 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
22149 // Check if SETCC has already been promoted
22150 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT &&
22151 // Check that condition value type matches vselect operand type
22152 CondVT == VT) {
22154 assert(Cond.getValueType().isVector() &&
22155 "vector select expects a vector selector!");
22157 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
22158 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
22160 if (!TValIsAllOnes && !FValIsAllZeros) {
22161 // Try invert the condition if true value is not all 1s and false value
22162 // is not all 0s.
22163 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
22164 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
22166 if (TValIsAllZeros || FValIsAllOnes) {
22167 SDValue CC = Cond.getOperand(2);
22168 ISD::CondCode NewCC =
22169 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
22170 Cond.getOperand(0).getValueType().isInteger());
22171 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
22172 std::swap(LHS, RHS);
22173 TValIsAllOnes = FValIsAllOnes;
22174 FValIsAllZeros = TValIsAllZeros;
22175 }
22176 }
22178 if (TValIsAllOnes || FValIsAllZeros) {
22179 SDValue Ret;
22181 if (TValIsAllOnes && FValIsAllZeros)
22182 Ret = Cond;
22183 else if (TValIsAllOnes)
22184 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
22185 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
22186 else if (FValIsAllZeros)
22187 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
22188 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
22190 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
22191 }
22192 }
22194 // Try to fold this VSELECT into a MOVSS/MOVSD
22195 if (N->getOpcode() == ISD::VSELECT &&
22196 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
22197 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
22198 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
22199 bool CanFold = false;
22200 unsigned NumElems = Cond.getNumOperands();
22201 SDValue A = LHS;
22202 SDValue B = RHS;
22204 if (isZero(Cond.getOperand(0))) {
22205 CanFold = true;
22207 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
22208 // fold (vselect <0,-1> -> (movsd A, B)
22209 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
22210 CanFold = isAllOnes(Cond.getOperand(i));
22211 } else if (isAllOnes(Cond.getOperand(0))) {
22212 CanFold = true;
22213 std::swap(A, B);
22215 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
22216 // fold (vselect <-1,0> -> (movsd B, A)
22217 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
22218 CanFold = isZero(Cond.getOperand(i));
22219 }
22221 if (CanFold) {
22222 if (VT == MVT::v4i32 || VT == MVT::v4f32)
22223 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
22224 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
22225 }
22227 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
22228 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
22229 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
22230 // (v2i64 (bitcast B)))))
22231 //
22232 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
22233 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
22234 // (v2f64 (bitcast B)))))
22235 //
22236 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
22237 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
22238 // (v2i64 (bitcast A)))))
22239 //
22240 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
22241 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
22242 // (v2f64 (bitcast A)))))
22244 CanFold = (isZero(Cond.getOperand(0)) &&
22245 isZero(Cond.getOperand(1)) &&
22246 isAllOnes(Cond.getOperand(2)) &&
22247 isAllOnes(Cond.getOperand(3)));
22249 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
22250 isAllOnes(Cond.getOperand(1)) &&
22251 isZero(Cond.getOperand(2)) &&
22252 isZero(Cond.getOperand(3))) {
22253 CanFold = true;
22254 std::swap(LHS, RHS);
22255 }
22257 if (CanFold) {
22258 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
22259 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
22260 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
22261 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
22262 NewB, DAG);
22263 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
22264 }
22265 }
22266 }
22267 }
22269 // If we know that this node is legal then we know that it is going to be
22270 // matched by one of the SSE/AVX BLEND instructions. These instructions only
22271 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
22272 // to simplify previous instructions.
22273 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
22274 !DCI.isBeforeLegalize() &&
22275 // We explicitly check against v8i16 and v16i16 because, although
22276 // they're marked as Custom, they might only be legal when Cond is a
22277 // build_vector of constants. This will be taken care in a later
22278 // condition.
22279 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
22280 VT != MVT::v8i16)) {
22281 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
22283 // Don't optimize vector selects that map to mask-registers.
22284 if (BitWidth == 1)
22285 return SDValue();
22287 // Check all uses of that condition operand to check whether it will be
22288 // consumed by non-BLEND instructions, which may depend on all bits are set
22289 // properly.
22290 for (SDNode::use_iterator I = Cond->use_begin(),
22291 E = Cond->use_end(); I != E; ++I)
22292 if (I->getOpcode() != ISD::VSELECT)
22293 // TODO: Add other opcodes eventually lowered into BLEND.
22294 return SDValue();
22296 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
22297 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
22299 APInt KnownZero, KnownOne;
22300 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
22301 DCI.isBeforeLegalizeOps());
22302 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
22303 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
22304 DCI.CommitTargetLoweringOpt(TLO);
22305 }
22307 // We should generate an X86ISD::BLENDI from a vselect if its argument
22308 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
22309 // constants. This specific pattern gets generated when we split a
22310 // selector for a 512 bit vector in a machine without AVX512 (but with
22311 // 256-bit vectors), during legalization:
22312 //
22313 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
22314 //
22315 // Iff we find this pattern and the build_vectors are built from
22316 // constants, we translate the vselect into a shuffle_vector that we
22317 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
22318 if (N->getOpcode() == ISD::VSELECT && !DCI.isBeforeLegalize()) {
22319 SDValue Shuffle = TransformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
22320 if (Shuffle.getNode())
22321 return Shuffle;
22322 }
22324 return SDValue();
22325 }
22327 // Check whether a boolean test is testing a boolean value generated by
22328 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
22329 // code.
22330 //
22331 // Simplify the following patterns:
22332 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
22333 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
22334 // to (Op EFLAGS Cond)
22335 //
22336 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
22337 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
22338 // to (Op EFLAGS !Cond)
22339 //
22340 // where Op could be BRCOND or CMOV.
22341 //
22342 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
22343 // Quit if not CMP and SUB with its value result used.
22344 if (Cmp.getOpcode() != X86ISD::CMP &&
22345 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
22346 return SDValue();
22348 // Quit if not used as a boolean value.
22349 if (CC != X86::COND_E && CC != X86::COND_NE)
22350 return SDValue();
22352 // Check CMP operands. One of them should be 0 or 1 and the other should be
22353 // an SetCC or extended from it.
22354 SDValue Op1 = Cmp.getOperand(0);
22355 SDValue Op2 = Cmp.getOperand(1);
22357 SDValue SetCC;
22358 const ConstantSDNode* C = nullptr;
22359 bool needOppositeCond = (CC == X86::COND_E);
22360 bool checkAgainstTrue = false; // Is it a comparison against 1?
22362 if ((C = dyn_cast<ConstantSDNode>(Op1)))
22363 SetCC = Op2;
22364 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
22365 SetCC = Op1;
22366 else // Quit if all operands are not constants.
22367 return SDValue();
22369 if (C->getZExtValue() == 1) {
22370 needOppositeCond = !needOppositeCond;
22371 checkAgainstTrue = true;
22372 } else if (C->getZExtValue() != 0)
22373 // Quit if the constant is neither 0 or 1.
22374 return SDValue();
22376 bool truncatedToBoolWithAnd = false;
22377 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
22378 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
22379 SetCC.getOpcode() == ISD::TRUNCATE ||
22380 SetCC.getOpcode() == ISD::AND) {
22381 if (SetCC.getOpcode() == ISD::AND) {
22382 int OpIdx = -1;
22383 ConstantSDNode *CS;
22384 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
22385 CS->getZExtValue() == 1)
22386 OpIdx = 1;
22387 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
22388 CS->getZExtValue() == 1)
22389 OpIdx = 0;
22390 if (OpIdx == -1)
22391 break;
22392 SetCC = SetCC.getOperand(OpIdx);
22393 truncatedToBoolWithAnd = true;
22394 } else
22395 SetCC = SetCC.getOperand(0);
22396 }
22398 switch (SetCC.getOpcode()) {
22399 case X86ISD::SETCC_CARRY:
22400 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
22401 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
22402 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
22403 // truncated to i1 using 'and'.
22404 if (checkAgainstTrue && !truncatedToBoolWithAnd)
22405 break;
22406 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
22407 "Invalid use of SETCC_CARRY!");
22408 // FALL THROUGH
22409 case X86ISD::SETCC:
22410 // Set the condition code or opposite one if necessary.
22411 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
22412 if (needOppositeCond)
22413 CC = X86::GetOppositeBranchCondition(CC);
22414 return SetCC.getOperand(1);
22415 case X86ISD::CMOV: {
22416 // Check whether false/true value has canonical one, i.e. 0 or 1.
22417 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
22418 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
22419 // Quit if true value is not a constant.
22420 if (!TVal)
22421 return SDValue();
22422 // Quit if false value is not a constant.
22423 if (!FVal) {
22424 SDValue Op = SetCC.getOperand(0);
22425 // Skip 'zext' or 'trunc' node.
22426 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
22427 Op.getOpcode() == ISD::TRUNCATE)
22428 Op = Op.getOperand(0);
22429 // A special case for rdrand/rdseed, where 0 is set if false cond is
22430 // found.
22431 if ((Op.getOpcode() != X86ISD::RDRAND &&
22432 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
22433 return SDValue();
22434 }
22435 // Quit if false value is not the constant 0 or 1.
22436 bool FValIsFalse = true;
22437 if (FVal && FVal->getZExtValue() != 0) {
22438 if (FVal->getZExtValue() != 1)
22439 return SDValue();
22440 // If FVal is 1, opposite cond is needed.
22441 needOppositeCond = !needOppositeCond;
22442 FValIsFalse = false;
22443 }
22444 // Quit if TVal is not the constant opposite of FVal.
22445 if (FValIsFalse && TVal->getZExtValue() != 1)
22446 return SDValue();
22447 if (!FValIsFalse && TVal->getZExtValue() != 0)
22448 return SDValue();
22449 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
22450 if (needOppositeCond)
22451 CC = X86::GetOppositeBranchCondition(CC);
22452 return SetCC.getOperand(3);
22453 }
22454 }
22456 return SDValue();
22457 }
22459 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
22460 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
22461 TargetLowering::DAGCombinerInfo &DCI,
22462 const X86Subtarget *Subtarget) {
22463 SDLoc DL(N);
22465 // If the flag operand isn't dead, don't touch this CMOV.
22466 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
22467 return SDValue();
22469 SDValue FalseOp = N->getOperand(0);
22470 SDValue TrueOp = N->getOperand(1);
22471 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
22472 SDValue Cond = N->getOperand(3);
22474 if (CC == X86::COND_E || CC == X86::COND_NE) {
22475 switch (Cond.getOpcode()) {
22476 default: break;
22477 case X86ISD::BSR:
22478 case X86ISD::BSF:
22479 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
22480 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
22481 return (CC == X86::COND_E) ? FalseOp : TrueOp;
22482 }
22483 }
22485 SDValue Flags;
22487 Flags = checkBoolTestSetCCCombine(Cond, CC);
22488 if (Flags.getNode() &&
22489 // Extra check as FCMOV only supports a subset of X86 cond.
22490 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
22491 SDValue Ops[] = { FalseOp, TrueOp,
22492 DAG.getConstant(CC, MVT::i8), Flags };
22493 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
22494 }
22496 // If this is a select between two integer constants, try to do some
22497 // optimizations. Note that the operands are ordered the opposite of SELECT
22498 // operands.
22499 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
22500 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
22501 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
22502 // larger than FalseC (the false value).
22503 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
22504 CC = X86::GetOppositeBranchCondition(CC);
22505 std::swap(TrueC, FalseC);
22506 std::swap(TrueOp, FalseOp);
22507 }
22509 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
22510 // This is efficient for any integer data type (including i8/i16) and
22511 // shift amount.
22512 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
22513 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22514 DAG.getConstant(CC, MVT::i8), Cond);
22516 // Zero extend the condition if needed.
22517 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
22519 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22520 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
22521 DAG.getConstant(ShAmt, MVT::i8));
22522 if (N->getNumValues() == 2) // Dead flag value?
22523 return DCI.CombineTo(N, Cond, SDValue());
22524 return Cond;
22525 }
22527 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
22528 // for any integer data type, including i8/i16.
22529 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22530 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22531 DAG.getConstant(CC, MVT::i8), Cond);
22533 // Zero extend the condition if needed.
22534 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22535 FalseC->getValueType(0), Cond);
22536 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22537 SDValue(FalseC, 0));
22539 if (N->getNumValues() == 2) // Dead flag value?
22540 return DCI.CombineTo(N, Cond, SDValue());
22541 return Cond;
22542 }
22544 // Optimize cases that will turn into an LEA instruction. This requires
22545 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22546 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22547 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22548 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22550 bool isFastMultiplier = false;
22551 if (Diff < 10) {
22552 switch ((unsigned char)Diff) {
22553 default: break;
22554 case 1: // result = add base, cond
22555 case 2: // result = lea base( , cond*2)
22556 case 3: // result = lea base(cond, cond*2)
22557 case 4: // result = lea base( , cond*4)
22558 case 5: // result = lea base(cond, cond*4)
22559 case 8: // result = lea base( , cond*8)
22560 case 9: // result = lea base(cond, cond*8)
22561 isFastMultiplier = true;
22562 break;
22563 }
22564 }
22566 if (isFastMultiplier) {
22567 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22568 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22569 DAG.getConstant(CC, MVT::i8), Cond);
22570 // Zero extend the condition if needed.
22571 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22572 Cond);
22573 // Scale the condition by the difference.
22574 if (Diff != 1)
22575 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22576 DAG.getConstant(Diff, Cond.getValueType()));
22578 // Add the base if non-zero.
22579 if (FalseC->getAPIntValue() != 0)
22580 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22581 SDValue(FalseC, 0));
22582 if (N->getNumValues() == 2) // Dead flag value?
22583 return DCI.CombineTo(N, Cond, SDValue());
22584 return Cond;
22585 }
22586 }
22587 }
22588 }
22590 // Handle these cases:
22591 // (select (x != c), e, c) -> select (x != c), e, x),
22592 // (select (x == c), c, e) -> select (x == c), x, e)
22593 // where the c is an integer constant, and the "select" is the combination
22594 // of CMOV and CMP.
22595 //
22596 // The rationale for this change is that the conditional-move from a constant
22597 // needs two instructions, however, conditional-move from a register needs
22598 // only one instruction.
22599 //
22600 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
22601 // some instruction-combining opportunities. This opt needs to be
22602 // postponed as late as possible.
22603 //
22604 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
22605 // the DCI.xxxx conditions are provided to postpone the optimization as
22606 // late as possible.
22608 ConstantSDNode *CmpAgainst = nullptr;
22609 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
22610 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
22611 !isa<ConstantSDNode>(Cond.getOperand(0))) {
22613 if (CC == X86::COND_NE &&
22614 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
22615 CC = X86::GetOppositeBranchCondition(CC);
22616 std::swap(TrueOp, FalseOp);
22617 }
22619 if (CC == X86::COND_E &&
22620 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
22621 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
22622 DAG.getConstant(CC, MVT::i8), Cond };
22623 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
22624 }
22625 }
22626 }
22628 return SDValue();
22629 }
22631 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
22632 const X86Subtarget *Subtarget) {
22633 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
22634 switch (IntNo) {
22635 default: return SDValue();
22636 // SSE/AVX/AVX2 blend intrinsics.
22637 case Intrinsic::x86_avx2_pblendvb:
22638 case Intrinsic::x86_avx2_pblendw:
22639 case Intrinsic::x86_avx2_pblendd_128:
22640 case Intrinsic::x86_avx2_pblendd_256:
22641 // Don't try to simplify this intrinsic if we don't have AVX2.
22642 if (!Subtarget->hasAVX2())
22643 return SDValue();
22644 // FALL-THROUGH
22645 case Intrinsic::x86_avx_blend_pd_256:
22646 case Intrinsic::x86_avx_blend_ps_256:
22647 case Intrinsic::x86_avx_blendv_pd_256:
22648 case Intrinsic::x86_avx_blendv_ps_256:
22649 // Don't try to simplify this intrinsic if we don't have AVX.
22650 if (!Subtarget->hasAVX())
22651 return SDValue();
22652 // FALL-THROUGH
22653 case Intrinsic::x86_sse41_pblendw:
22654 case Intrinsic::x86_sse41_blendpd:
22655 case Intrinsic::x86_sse41_blendps:
22656 case Intrinsic::x86_sse41_blendvps:
22657 case Intrinsic::x86_sse41_blendvpd:
22658 case Intrinsic::x86_sse41_pblendvb: {
22659 SDValue Op0 = N->getOperand(1);
22660 SDValue Op1 = N->getOperand(2);
22661 SDValue Mask = N->getOperand(3);
22663 // Don't try to simplify this intrinsic if we don't have SSE4.1.
22664 if (!Subtarget->hasSSE41())
22665 return SDValue();
22667 // fold (blend A, A, Mask) -> A
22668 if (Op0 == Op1)
22669 return Op0;
22670 // fold (blend A, B, allZeros) -> A
22671 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
22672 return Op0;
22673 // fold (blend A, B, allOnes) -> B
22674 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
22675 return Op1;
22677 // Simplify the case where the mask is a constant i32 value.
22678 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
22679 if (C->isNullValue())
22680 return Op0;
22681 if (C->isAllOnesValue())
22682 return Op1;
22683 }
22685 return SDValue();
22686 }
22688 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
22689 case Intrinsic::x86_sse2_psrai_w:
22690 case Intrinsic::x86_sse2_psrai_d:
22691 case Intrinsic::x86_avx2_psrai_w:
22692 case Intrinsic::x86_avx2_psrai_d:
22693 case Intrinsic::x86_sse2_psra_w:
22694 case Intrinsic::x86_sse2_psra_d:
22695 case Intrinsic::x86_avx2_psra_w:
22696 case Intrinsic::x86_avx2_psra_d: {
22697 SDValue Op0 = N->getOperand(1);
22698 SDValue Op1 = N->getOperand(2);
22699 EVT VT = Op0.getValueType();
22700 assert(VT.isVector() && "Expected a vector type!");
22702 if (isa<BuildVectorSDNode>(Op1))
22703 Op1 = Op1.getOperand(0);
22705 if (!isa<ConstantSDNode>(Op1))
22706 return SDValue();
22708 EVT SVT = VT.getVectorElementType();
22709 unsigned SVTBits = SVT.getSizeInBits();
22711 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
22712 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
22713 uint64_t ShAmt = C.getZExtValue();
22715 // Don't try to convert this shift into a ISD::SRA if the shift
22716 // count is bigger than or equal to the element size.
22717 if (ShAmt >= SVTBits)
22718 return SDValue();
22720 // Trivial case: if the shift count is zero, then fold this
22721 // into the first operand.
22722 if (ShAmt == 0)
22723 return Op0;
22725 // Replace this packed shift intrinsic with a target independent
22726 // shift dag node.
22727 SDValue Splat = DAG.getConstant(C, VT);
22728 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
22729 }
22730 }
22731 }
22733 /// PerformMulCombine - Optimize a single multiply with constant into two
22734 /// in order to implement it with two cheaper instructions, e.g.
22735 /// LEA + SHL, LEA + LEA.
22736 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
22737 TargetLowering::DAGCombinerInfo &DCI) {
22738 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
22739 return SDValue();
22741 EVT VT = N->getValueType(0);
22742 if (VT != MVT::i64)
22743 return SDValue();
22745 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
22746 if (!C)
22747 return SDValue();
22748 uint64_t MulAmt = C->getZExtValue();
22749 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
22750 return SDValue();
22752 uint64_t MulAmt1 = 0;
22753 uint64_t MulAmt2 = 0;
22754 if ((MulAmt % 9) == 0) {
22755 MulAmt1 = 9;
22756 MulAmt2 = MulAmt / 9;
22757 } else if ((MulAmt % 5) == 0) {
22758 MulAmt1 = 5;
22759 MulAmt2 = MulAmt / 5;
22760 } else if ((MulAmt % 3) == 0) {
22761 MulAmt1 = 3;
22762 MulAmt2 = MulAmt / 3;
22763 }
22764 if (MulAmt2 &&
22765 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
22766 SDLoc DL(N);
22768 if (isPowerOf2_64(MulAmt2) &&
22769 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
22770 // If second multiplifer is pow2, issue it first. We want the multiply by
22771 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
22772 // is an add.
22773 std::swap(MulAmt1, MulAmt2);
22775 SDValue NewMul;
22776 if (isPowerOf2_64(MulAmt1))
22777 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
22778 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
22779 else
22780 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
22781 DAG.getConstant(MulAmt1, VT));
22783 if (isPowerOf2_64(MulAmt2))
22784 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
22785 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
22786 else
22787 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
22788 DAG.getConstant(MulAmt2, VT));
22790 // Do not add new nodes to DAG combiner worklist.
22791 DCI.CombineTo(N, NewMul, false);
22792 }
22793 return SDValue();
22794 }
22796 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
22797 SDValue N0 = N->getOperand(0);
22798 SDValue N1 = N->getOperand(1);
22799 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
22800 EVT VT = N0.getValueType();
22802 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
22803 // since the result of setcc_c is all zero's or all ones.
22804 if (VT.isInteger() && !VT.isVector() &&
22805 N1C && N0.getOpcode() == ISD::AND &&
22806 N0.getOperand(1).getOpcode() == ISD::Constant) {
22807 SDValue N00 = N0.getOperand(0);
22808 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
22809 ((N00.getOpcode() == ISD::ANY_EXTEND ||
22810 N00.getOpcode() == ISD::ZERO_EXTEND) &&
22811 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
22812 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
22813 APInt ShAmt = N1C->getAPIntValue();
22814 Mask = Mask.shl(ShAmt);
22815 if (Mask != 0)
22816 return DAG.getNode(ISD::AND, SDLoc(N), VT,
22817 N00, DAG.getConstant(Mask, VT));
22818 }
22819 }
22821 // Hardware support for vector shifts is sparse which makes us scalarize the
22822 // vector operations in many cases. Also, on sandybridge ADD is faster than
22823 // shl.
22824 // (shl V, 1) -> add V,V
22825 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
22826 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
22827 assert(N0.getValueType().isVector() && "Invalid vector shift type");
22828 // We shift all of the values by one. In many cases we do not have
22829 // hardware support for this operation. This is better expressed as an ADD
22830 // of two values.
22831 if (N1SplatC->getZExtValue() == 1)
22832 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
22833 }
22835 return SDValue();
22836 }
22838 /// \brief Returns a vector of 0s if the node in input is a vector logical
22839 /// shift by a constant amount which is known to be bigger than or equal
22840 /// to the vector element size in bits.
22841 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
22842 const X86Subtarget *Subtarget) {
22843 EVT VT = N->getValueType(0);
22845 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
22846 (!Subtarget->hasInt256() ||
22847 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
22848 return SDValue();
22850 SDValue Amt = N->getOperand(1);
22851 SDLoc DL(N);
22852 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
22853 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
22854 APInt ShiftAmt = AmtSplat->getAPIntValue();
22855 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
22857 // SSE2/AVX2 logical shifts always return a vector of 0s
22858 // if the shift amount is bigger than or equal to
22859 // the element size. The constant shift amount will be
22860 // encoded as a 8-bit immediate.
22861 if (ShiftAmt.trunc(8).uge(MaxAmount))
22862 return getZeroVector(VT, Subtarget, DAG, DL);
22863 }
22865 return SDValue();
22866 }
22868 /// PerformShiftCombine - Combine shifts.
22869 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
22870 TargetLowering::DAGCombinerInfo &DCI,
22871 const X86Subtarget *Subtarget) {
22872 if (N->getOpcode() == ISD::SHL) {
22873 SDValue V = PerformSHLCombine(N, DAG);
22874 if (V.getNode()) return V;
22875 }
22877 if (N->getOpcode() != ISD::SRA) {
22878 // Try to fold this logical shift into a zero vector.
22879 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
22880 if (V.getNode()) return V;
22881 }
22883 return SDValue();
22884 }
22886 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
22887 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
22888 // and friends. Likewise for OR -> CMPNEQSS.
22889 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
22890 TargetLowering::DAGCombinerInfo &DCI,
22891 const X86Subtarget *Subtarget) {
22892 unsigned opcode;
22894 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
22895 // we're requiring SSE2 for both.
22896 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
22897 SDValue N0 = N->getOperand(0);
22898 SDValue N1 = N->getOperand(1);
22899 SDValue CMP0 = N0->getOperand(1);
22900 SDValue CMP1 = N1->getOperand(1);
22901 SDLoc DL(N);
22903 // The SETCCs should both refer to the same CMP.
22904 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
22905 return SDValue();
22907 SDValue CMP00 = CMP0->getOperand(0);
22908 SDValue CMP01 = CMP0->getOperand(1);
22909 EVT VT = CMP00.getValueType();
22911 if (VT == MVT::f32 || VT == MVT::f64) {
22912 bool ExpectingFlags = false;
22913 // Check for any users that want flags:
22914 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
22915 !ExpectingFlags && UI != UE; ++UI)
22916 switch (UI->getOpcode()) {
22917 default:
22918 case ISD::BR_CC:
22919 case ISD::BRCOND:
22920 case ISD::SELECT:
22921 ExpectingFlags = true;
22922 break;
22923 case ISD::CopyToReg:
22924 case ISD::SIGN_EXTEND:
22925 case ISD::ZERO_EXTEND:
22926 case ISD::ANY_EXTEND:
22927 break;
22928 }
22930 if (!ExpectingFlags) {
22931 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
22932 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
22934 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
22935 X86::CondCode tmp = cc0;
22936 cc0 = cc1;
22937 cc1 = tmp;
22938 }
22940 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
22941 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
22942 // FIXME: need symbolic constants for these magic numbers.
22943 // See X86ATTInstPrinter.cpp:printSSECC().
22944 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
22945 if (Subtarget->hasAVX512()) {
22946 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
22947 CMP01, DAG.getConstant(x86cc, MVT::i8));
22948 if (N->getValueType(0) != MVT::i1)
22949 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
22950 FSetCC);
22951 return FSetCC;
22952 }
22953 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
22954 CMP00.getValueType(), CMP00, CMP01,
22955 DAG.getConstant(x86cc, MVT::i8));
22957 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
22958 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
22960 if (is64BitFP && !Subtarget->is64Bit()) {
22961 // On a 32-bit target, we cannot bitcast the 64-bit float to a
22962 // 64-bit integer, since that's not a legal type. Since
22963 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
22964 // bits, but can do this little dance to extract the lowest 32 bits
22965 // and work with those going forward.
22966 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
22967 OnesOrZeroesF);
22968 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
22969 Vector64);
22970 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
22971 Vector32, DAG.getIntPtrConstant(0));
22972 IntVT = MVT::i32;
22973 }
22975 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
22976 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
22977 DAG.getConstant(1, IntVT));
22978 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
22979 return OneBitOfTruth;
22980 }
22981 }
22982 }
22983 }
22984 return SDValue();
22985 }
22987 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
22988 /// so it can be folded inside ANDNP.
22989 static bool CanFoldXORWithAllOnes(const SDNode *N) {
22990 EVT VT = N->getValueType(0);
22992 // Match direct AllOnes for 128 and 256-bit vectors
22993 if (ISD::isBuildVectorAllOnes(N))
22994 return true;
22996 // Look through a bit convert.
22997 if (N->getOpcode() == ISD::BITCAST)
22998 N = N->getOperand(0).getNode();
23000 // Sometimes the operand may come from a insert_subvector building a 256-bit
23001 // allones vector
23002 if (VT.is256BitVector() &&
23003 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
23004 SDValue V1 = N->getOperand(0);
23005 SDValue V2 = N->getOperand(1);
23007 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
23008 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
23009 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
23010 ISD::isBuildVectorAllOnes(V2.getNode()))
23011 return true;
23012 }
23014 return false;
23015 }
23017 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
23018 // register. In most cases we actually compare or select YMM-sized registers
23019 // and mixing the two types creates horrible code. This method optimizes
23020 // some of the transition sequences.
23021 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
23022 TargetLowering::DAGCombinerInfo &DCI,
23023 const X86Subtarget *Subtarget) {
23024 EVT VT = N->getValueType(0);
23025 if (!VT.is256BitVector())
23026 return SDValue();
23028 assert((N->getOpcode() == ISD::ANY_EXTEND ||
23029 N->getOpcode() == ISD::ZERO_EXTEND ||
23030 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
23032 SDValue Narrow = N->getOperand(0);
23033 EVT NarrowVT = Narrow->getValueType(0);
23034 if (!NarrowVT.is128BitVector())
23035 return SDValue();
23037 if (Narrow->getOpcode() != ISD::XOR &&
23038 Narrow->getOpcode() != ISD::AND &&
23039 Narrow->getOpcode() != ISD::OR)
23040 return SDValue();
23042 SDValue N0 = Narrow->getOperand(0);
23043 SDValue N1 = Narrow->getOperand(1);
23044 SDLoc DL(Narrow);
23046 // The Left side has to be a trunc.
23047 if (N0.getOpcode() != ISD::TRUNCATE)
23048 return SDValue();
23050 // The type of the truncated inputs.
23051 EVT WideVT = N0->getOperand(0)->getValueType(0);
23052 if (WideVT != VT)
23053 return SDValue();
23055 // The right side has to be a 'trunc' or a constant vector.
23056 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
23057 ConstantSDNode *RHSConstSplat = nullptr;
23058 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
23059 RHSConstSplat = RHSBV->getConstantSplatNode();
23060 if (!RHSTrunc && !RHSConstSplat)
23061 return SDValue();
23063 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23065 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
23066 return SDValue();
23068 // Set N0 and N1 to hold the inputs to the new wide operation.
23069 N0 = N0->getOperand(0);
23070 if (RHSConstSplat) {
23071 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
23072 SDValue(RHSConstSplat, 0));
23073 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
23074 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
23075 } else if (RHSTrunc) {
23076 N1 = N1->getOperand(0);
23077 }
23079 // Generate the wide operation.
23080 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
23081 unsigned Opcode = N->getOpcode();
23082 switch (Opcode) {
23083 case ISD::ANY_EXTEND:
23084 return Op;
23085 case ISD::ZERO_EXTEND: {
23086 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
23087 APInt Mask = APInt::getAllOnesValue(InBits);
23088 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
23089 return DAG.getNode(ISD::AND, DL, VT,
23090 Op, DAG.getConstant(Mask, VT));
23091 }
23092 case ISD::SIGN_EXTEND:
23093 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
23094 Op, DAG.getValueType(NarrowVT));
23095 default:
23096 llvm_unreachable("Unexpected opcode");
23097 }
23098 }
23100 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
23101 TargetLowering::DAGCombinerInfo &DCI,
23102 const X86Subtarget *Subtarget) {
23103 EVT VT = N->getValueType(0);
23104 if (DCI.isBeforeLegalizeOps())
23105 return SDValue();
23107 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
23108 if (R.getNode())
23109 return R;
23111 // Create BEXTR instructions
23112 // BEXTR is ((X >> imm) & (2**size-1))
23113 if (VT == MVT::i32 || VT == MVT::i64) {
23114 SDValue N0 = N->getOperand(0);
23115 SDValue N1 = N->getOperand(1);
23116 SDLoc DL(N);
23118 // Check for BEXTR.
23119 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
23120 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
23121 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
23122 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
23123 if (MaskNode && ShiftNode) {
23124 uint64_t Mask = MaskNode->getZExtValue();
23125 uint64_t Shift = ShiftNode->getZExtValue();
23126 if (isMask_64(Mask)) {
23127 uint64_t MaskSize = CountPopulation_64(Mask);
23128 if (Shift + MaskSize <= VT.getSizeInBits())
23129 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
23130 DAG.getConstant(Shift | (MaskSize << 8), VT));
23131 }
23132 }
23133 } // BEXTR
23135 return SDValue();
23136 }
23138 // Want to form ANDNP nodes:
23139 // 1) In the hopes of then easily combining them with OR and AND nodes
23140 // to form PBLEND/PSIGN.
23141 // 2) To match ANDN packed intrinsics
23142 if (VT != MVT::v2i64 && VT != MVT::v4i64)
23143 return SDValue();
23145 SDValue N0 = N->getOperand(0);
23146 SDValue N1 = N->getOperand(1);
23147 SDLoc DL(N);
23149 // Check LHS for vnot
23150 if (N0.getOpcode() == ISD::XOR &&
23151 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
23152 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
23153 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
23155 // Check RHS for vnot
23156 if (N1.getOpcode() == ISD::XOR &&
23157 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
23158 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
23159 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
23161 return SDValue();
23162 }
23164 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
23165 TargetLowering::DAGCombinerInfo &DCI,
23166 const X86Subtarget *Subtarget) {
23167 if (DCI.isBeforeLegalizeOps())
23168 return SDValue();
23170 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
23171 if (R.getNode())
23172 return R;
23174 SDValue N0 = N->getOperand(0);
23175 SDValue N1 = N->getOperand(1);
23176 EVT VT = N->getValueType(0);
23178 // look for psign/blend
23179 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
23180 if (!Subtarget->hasSSSE3() ||
23181 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
23182 return SDValue();
23184 // Canonicalize pandn to RHS
23185 if (N0.getOpcode() == X86ISD::ANDNP)
23186 std::swap(N0, N1);
23187 // or (and (m, y), (pandn m, x))
23188 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
23189 SDValue Mask = N1.getOperand(0);
23190 SDValue X = N1.getOperand(1);
23191 SDValue Y;
23192 if (N0.getOperand(0) == Mask)
23193 Y = N0.getOperand(1);
23194 if (N0.getOperand(1) == Mask)
23195 Y = N0.getOperand(0);
23197 // Check to see if the mask appeared in both the AND and ANDNP and
23198 if (!Y.getNode())
23199 return SDValue();
23201 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
23202 // Look through mask bitcast.
23203 if (Mask.getOpcode() == ISD::BITCAST)
23204 Mask = Mask.getOperand(0);
23205 if (X.getOpcode() == ISD::BITCAST)
23206 X = X.getOperand(0);
23207 if (Y.getOpcode() == ISD::BITCAST)
23208 Y = Y.getOperand(0);
23210 EVT MaskVT = Mask.getValueType();
23212 // Validate that the Mask operand is a vector sra node.
23213 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
23214 // there is no psrai.b
23215 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
23216 unsigned SraAmt = ~0;
23217 if (Mask.getOpcode() == ISD::SRA) {
23218 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
23219 if (auto *AmtConst = AmtBV->getConstantSplatNode())
23220 SraAmt = AmtConst->getZExtValue();
23221 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
23222 SDValue SraC = Mask.getOperand(1);
23223 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
23224 }
23225 if ((SraAmt + 1) != EltBits)
23226 return SDValue();
23228 SDLoc DL(N);
23230 // Now we know we at least have a plendvb with the mask val. See if
23231 // we can form a psignb/w/d.
23232 // psign = x.type == y.type == mask.type && y = sub(0, x);
23233 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
23234 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
23235 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
23236 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
23237 "Unsupported VT for PSIGN");
23238 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
23239 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
23240 }
23241 // PBLENDVB only available on SSE 4.1
23242 if (!Subtarget->hasSSE41())
23243 return SDValue();
23245 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
23247 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
23248 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
23249 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
23250 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
23251 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
23252 }
23253 }
23255 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
23256 return SDValue();
23258 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
23259 MachineFunction &MF = DAG.getMachineFunction();
23260 bool OptForSize = MF.getFunction()->getAttributes().
23261 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
23263 // SHLD/SHRD instructions have lower register pressure, but on some
23264 // platforms they have higher latency than the equivalent
23265 // series of shifts/or that would otherwise be generated.
23266 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
23267 // have higher latencies and we are not optimizing for size.
23268 if (!OptForSize && Subtarget->isSHLDSlow())
23269 return SDValue();
23271 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
23272 std::swap(N0, N1);
23273 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
23274 return SDValue();
23275 if (!N0.hasOneUse() || !N1.hasOneUse())
23276 return SDValue();
23278 SDValue ShAmt0 = N0.getOperand(1);
23279 if (ShAmt0.getValueType() != MVT::i8)
23280 return SDValue();
23281 SDValue ShAmt1 = N1.getOperand(1);
23282 if (ShAmt1.getValueType() != MVT::i8)
23283 return SDValue();
23284 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
23285 ShAmt0 = ShAmt0.getOperand(0);
23286 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
23287 ShAmt1 = ShAmt1.getOperand(0);
23289 SDLoc DL(N);
23290 unsigned Opc = X86ISD::SHLD;
23291 SDValue Op0 = N0.getOperand(0);
23292 SDValue Op1 = N1.getOperand(0);
23293 if (ShAmt0.getOpcode() == ISD::SUB) {
23294 Opc = X86ISD::SHRD;
23295 std::swap(Op0, Op1);
23296 std::swap(ShAmt0, ShAmt1);
23297 }
23299 unsigned Bits = VT.getSizeInBits();
23300 if (ShAmt1.getOpcode() == ISD::SUB) {
23301 SDValue Sum = ShAmt1.getOperand(0);
23302 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
23303 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
23304 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
23305 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
23306 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
23307 return DAG.getNode(Opc, DL, VT,
23308 Op0, Op1,
23309 DAG.getNode(ISD::TRUNCATE, DL,
23310 MVT::i8, ShAmt0));
23311 }
23312 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
23313 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
23314 if (ShAmt0C &&
23315 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
23316 return DAG.getNode(Opc, DL, VT,
23317 N0.getOperand(0), N1.getOperand(0),
23318 DAG.getNode(ISD::TRUNCATE, DL,
23319 MVT::i8, ShAmt0));
23320 }
23322 return SDValue();
23323 }
23325 // Generate NEG and CMOV for integer abs.
23326 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
23327 EVT VT = N->getValueType(0);
23329 // Since X86 does not have CMOV for 8-bit integer, we don't convert
23330 // 8-bit integer abs to NEG and CMOV.
23331 if (VT.isInteger() && VT.getSizeInBits() == 8)
23332 return SDValue();
23334 SDValue N0 = N->getOperand(0);
23335 SDValue N1 = N->getOperand(1);
23336 SDLoc DL(N);
23338 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
23339 // and change it to SUB and CMOV.
23340 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
23341 N0.getOpcode() == ISD::ADD &&
23342 N0.getOperand(1) == N1 &&
23343 N1.getOpcode() == ISD::SRA &&
23344 N1.getOperand(0) == N0.getOperand(0))
23345 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
23346 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
23347 // Generate SUB & CMOV.
23348 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
23349 DAG.getConstant(0, VT), N0.getOperand(0));
23351 SDValue Ops[] = { N0.getOperand(0), Neg,
23352 DAG.getConstant(X86::COND_GE, MVT::i8),
23353 SDValue(Neg.getNode(), 1) };
23354 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
23355 }
23356 return SDValue();
23357 }
23359 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
23360 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
23361 TargetLowering::DAGCombinerInfo &DCI,
23362 const X86Subtarget *Subtarget) {
23363 if (DCI.isBeforeLegalizeOps())
23364 return SDValue();
23366 if (Subtarget->hasCMov()) {
23367 SDValue RV = performIntegerAbsCombine(N, DAG);
23368 if (RV.getNode())
23369 return RV;
23370 }
23372 return SDValue();
23373 }
23375 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
23376 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
23377 TargetLowering::DAGCombinerInfo &DCI,
23378 const X86Subtarget *Subtarget) {
23379 LoadSDNode *Ld = cast<LoadSDNode>(N);
23380 EVT RegVT = Ld->getValueType(0);
23381 EVT MemVT = Ld->getMemoryVT();
23382 SDLoc dl(Ld);
23383 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23385 // On Sandybridge unaligned 256bit loads are inefficient.
23386 ISD::LoadExtType Ext = Ld->getExtensionType();
23387 unsigned Alignment = Ld->getAlignment();
23388 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
23389 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
23390 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
23391 unsigned NumElems = RegVT.getVectorNumElements();
23392 if (NumElems < 2)
23393 return SDValue();
23395 SDValue Ptr = Ld->getBasePtr();
23396 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
23398 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
23399 NumElems/2);
23400 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23401 Ld->getPointerInfo(), Ld->isVolatile(),
23402 Ld->isNonTemporal(), Ld->isInvariant(),
23403 Alignment);
23404 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23405 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23406 Ld->getPointerInfo(), Ld->isVolatile(),
23407 Ld->isNonTemporal(), Ld->isInvariant(),
23408 std::min(16U, Alignment));
23409 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
23410 Load1.getValue(1),
23411 Load2.getValue(1));
23413 SDValue NewVec = DAG.getUNDEF(RegVT);
23414 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
23415 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
23416 return DCI.CombineTo(N, NewVec, TF, true);
23417 }
23419 return SDValue();
23420 }
23422 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
23423 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
23424 const X86Subtarget *Subtarget) {
23425 StoreSDNode *St = cast<StoreSDNode>(N);
23426 EVT VT = St->getValue().getValueType();
23427 EVT StVT = St->getMemoryVT();
23428 SDLoc dl(St);
23429 SDValue StoredVal = St->getOperand(1);
23430 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23432 // If we are saving a concatenation of two XMM registers, perform two stores.
23433 // On Sandy Bridge, 256-bit memory operations are executed by two
23434 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
23435 // memory operation.
23436 unsigned Alignment = St->getAlignment();
23437 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
23438 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
23439 StVT == VT && !IsAligned) {
23440 unsigned NumElems = VT.getVectorNumElements();
23441 if (NumElems < 2)
23442 return SDValue();
23444 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
23445 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
23447 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
23448 SDValue Ptr0 = St->getBasePtr();
23449 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
23451 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
23452 St->getPointerInfo(), St->isVolatile(),
23453 St->isNonTemporal(), Alignment);
23454 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
23455 St->getPointerInfo(), St->isVolatile(),
23456 St->isNonTemporal(),
23457 std::min(16U, Alignment));
23458 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
23459 }
23461 // Optimize trunc store (of multiple scalars) to shuffle and store.
23462 // First, pack all of the elements in one place. Next, store to memory
23463 // in fewer chunks.
23464 if (St->isTruncatingStore() && VT.isVector()) {
23465 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23466 unsigned NumElems = VT.getVectorNumElements();
23467 assert(StVT != VT && "Cannot truncate to the same type");
23468 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
23469 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
23471 // From, To sizes and ElemCount must be pow of two
23472 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
23473 // We are going to use the original vector elt for storing.
23474 // Accumulated smaller vector elements must be a multiple of the store size.
23475 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
23477 unsigned SizeRatio = FromSz / ToSz;
23479 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
23481 // Create a type on which we perform the shuffle
23482 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23483 StVT.getScalarType(), NumElems*SizeRatio);
23485 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23487 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
23488 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
23489 for (unsigned i = 0; i != NumElems; ++i)
23490 ShuffleVec[i] = i * SizeRatio;
23492 // Can't shuffle using an illegal type.
23493 if (!TLI.isTypeLegal(WideVecVT))
23494 return SDValue();
23496 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
23497 DAG.getUNDEF(WideVecVT),
23498 &ShuffleVec[0]);
23499 // At this point all of the data is stored at the bottom of the
23500 // register. We now need to save it to mem.
23502 // Find the largest store unit
23503 MVT StoreType = MVT::i8;
23504 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
23505 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
23506 MVT Tp = (MVT::SimpleValueType)tp;
23507 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
23508 StoreType = Tp;
23509 }
23511 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
23512 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
23513 (64 <= NumElems * ToSz))
23514 StoreType = MVT::f64;
23516 // Bitcast the original vector into a vector of store-size units
23517 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
23518 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
23519 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
23520 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
23521 SmallVector<SDValue, 8> Chains;
23522 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
23523 TLI.getPointerTy());
23524 SDValue Ptr = St->getBasePtr();
23526 // Perform one or more big stores into memory.
23527 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
23528 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
23529 StoreType, ShuffWide,
23530 DAG.getIntPtrConstant(i));
23531 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
23532 St->getPointerInfo(), St->isVolatile(),
23533 St->isNonTemporal(), St->getAlignment());
23534 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23535 Chains.push_back(Ch);
23536 }
23538 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
23539 }
23541 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
23542 // the FP state in cases where an emms may be missing.
23543 // A preferable solution to the general problem is to figure out the right
23544 // places to insert EMMS. This qualifies as a quick hack.
23546 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
23547 if (VT.getSizeInBits() != 64)
23548 return SDValue();
23550 const Function *F = DAG.getMachineFunction().getFunction();
23551 bool NoImplicitFloatOps = F->getAttributes().
23552 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
23553 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
23554 && Subtarget->hasSSE2();
23555 if ((VT.isVector() ||
23556 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
23557 isa<LoadSDNode>(St->getValue()) &&
23558 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
23559 St->getChain().hasOneUse() && !St->isVolatile()) {
23560 SDNode* LdVal = St->getValue().getNode();
23561 LoadSDNode *Ld = nullptr;
23562 int TokenFactorIndex = -1;
23563 SmallVector<SDValue, 8> Ops;
23564 SDNode* ChainVal = St->getChain().getNode();
23565 // Must be a store of a load. We currently handle two cases: the load
23566 // is a direct child, and it's under an intervening TokenFactor. It is
23567 // possible to dig deeper under nested TokenFactors.
23568 if (ChainVal == LdVal)
23569 Ld = cast<LoadSDNode>(St->getChain());
23570 else if (St->getValue().hasOneUse() &&
23571 ChainVal->getOpcode() == ISD::TokenFactor) {
23572 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
23573 if (ChainVal->getOperand(i).getNode() == LdVal) {
23574 TokenFactorIndex = i;
23575 Ld = cast<LoadSDNode>(St->getValue());
23576 } else
23577 Ops.push_back(ChainVal->getOperand(i));
23578 }
23579 }
23581 if (!Ld || !ISD::isNormalLoad(Ld))
23582 return SDValue();
23584 // If this is not the MMX case, i.e. we are just turning i64 load/store
23585 // into f64 load/store, avoid the transformation if there are multiple
23586 // uses of the loaded value.
23587 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
23588 return SDValue();
23590 SDLoc LdDL(Ld);
23591 SDLoc StDL(N);
23592 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
23593 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
23594 // pair instead.
23595 if (Subtarget->is64Bit() || F64IsLegal) {
23596 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
23597 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
23598 Ld->getPointerInfo(), Ld->isVolatile(),
23599 Ld->isNonTemporal(), Ld->isInvariant(),
23600 Ld->getAlignment());
23601 SDValue NewChain = NewLd.getValue(1);
23602 if (TokenFactorIndex != -1) {
23603 Ops.push_back(NewChain);
23604 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23605 }
23606 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
23607 St->getPointerInfo(),
23608 St->isVolatile(), St->isNonTemporal(),
23609 St->getAlignment());
23610 }
23612 // Otherwise, lower to two pairs of 32-bit loads / stores.
23613 SDValue LoAddr = Ld->getBasePtr();
23614 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
23615 DAG.getConstant(4, MVT::i32));
23617 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
23618 Ld->getPointerInfo(),
23619 Ld->isVolatile(), Ld->isNonTemporal(),
23620 Ld->isInvariant(), Ld->getAlignment());
23621 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
23622 Ld->getPointerInfo().getWithOffset(4),
23623 Ld->isVolatile(), Ld->isNonTemporal(),
23624 Ld->isInvariant(),
23625 MinAlign(Ld->getAlignment(), 4));
23627 SDValue NewChain = LoLd.getValue(1);
23628 if (TokenFactorIndex != -1) {
23629 Ops.push_back(LoLd);
23630 Ops.push_back(HiLd);
23631 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23632 }
23634 LoAddr = St->getBasePtr();
23635 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
23636 DAG.getConstant(4, MVT::i32));
23638 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
23639 St->getPointerInfo(),
23640 St->isVolatile(), St->isNonTemporal(),
23641 St->getAlignment());
23642 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
23643 St->getPointerInfo().getWithOffset(4),
23644 St->isVolatile(),
23645 St->isNonTemporal(),
23646 MinAlign(St->getAlignment(), 4));
23647 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
23648 }
23649 return SDValue();
23650 }
23652 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
23653 /// and return the operands for the horizontal operation in LHS and RHS. A
23654 /// horizontal operation performs the binary operation on successive elements
23655 /// of its first operand, then on successive elements of its second operand,
23656 /// returning the resulting values in a vector. For example, if
23657 /// A = < float a0, float a1, float a2, float a3 >
23658 /// and
23659 /// B = < float b0, float b1, float b2, float b3 >
23660 /// then the result of doing a horizontal operation on A and B is
23661 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
23662 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
23663 /// A horizontal-op B, for some already available A and B, and if so then LHS is
23664 /// set to A, RHS to B, and the routine returns 'true'.
23665 /// Note that the binary operation should have the property that if one of the
23666 /// operands is UNDEF then the result is UNDEF.
23667 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
23668 // Look for the following pattern: if
23669 // A = < float a0, float a1, float a2, float a3 >
23670 // B = < float b0, float b1, float b2, float b3 >
23671 // and
23672 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
23673 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
23674 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
23675 // which is A horizontal-op B.
23677 // At least one of the operands should be a vector shuffle.
23678 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
23679 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
23680 return false;
23682 MVT VT = LHS.getSimpleValueType();
23684 assert((VT.is128BitVector() || VT.is256BitVector()) &&
23685 "Unsupported vector type for horizontal add/sub");
23687 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
23688 // operate independently on 128-bit lanes.
23689 unsigned NumElts = VT.getVectorNumElements();
23690 unsigned NumLanes = VT.getSizeInBits()/128;
23691 unsigned NumLaneElts = NumElts / NumLanes;
23692 assert((NumLaneElts % 2 == 0) &&
23693 "Vector type should have an even number of elements in each lane");
23694 unsigned HalfLaneElts = NumLaneElts/2;
23696 // View LHS in the form
23697 // LHS = VECTOR_SHUFFLE A, B, LMask
23698 // If LHS is not a shuffle then pretend it is the shuffle
23699 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
23700 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
23701 // type VT.
23702 SDValue A, B;
23703 SmallVector<int, 16> LMask(NumElts);
23704 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23705 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
23706 A = LHS.getOperand(0);
23707 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
23708 B = LHS.getOperand(1);
23709 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
23710 std::copy(Mask.begin(), Mask.end(), LMask.begin());
23711 } else {
23712 if (LHS.getOpcode() != ISD::UNDEF)
23713 A = LHS;
23714 for (unsigned i = 0; i != NumElts; ++i)
23715 LMask[i] = i;
23716 }
23718 // Likewise, view RHS in the form
23719 // RHS = VECTOR_SHUFFLE C, D, RMask
23720 SDValue C, D;
23721 SmallVector<int, 16> RMask(NumElts);
23722 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23723 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
23724 C = RHS.getOperand(0);
23725 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
23726 D = RHS.getOperand(1);
23727 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
23728 std::copy(Mask.begin(), Mask.end(), RMask.begin());
23729 } else {
23730 if (RHS.getOpcode() != ISD::UNDEF)
23731 C = RHS;
23732 for (unsigned i = 0; i != NumElts; ++i)
23733 RMask[i] = i;
23734 }
23736 // Check that the shuffles are both shuffling the same vectors.
23737 if (!(A == C && B == D) && !(A == D && B == C))
23738 return false;
23740 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
23741 if (!A.getNode() && !B.getNode())
23742 return false;
23744 // If A and B occur in reverse order in RHS, then "swap" them (which means
23745 // rewriting the mask).
23746 if (A != C)
23747 CommuteVectorShuffleMask(RMask, NumElts);
23749 // At this point LHS and RHS are equivalent to
23750 // LHS = VECTOR_SHUFFLE A, B, LMask
23751 // RHS = VECTOR_SHUFFLE A, B, RMask
23752 // Check that the masks correspond to performing a horizontal operation.
23753 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
23754 for (unsigned i = 0; i != NumLaneElts; ++i) {
23755 int LIdx = LMask[i+l], RIdx = RMask[i+l];
23757 // Ignore any UNDEF components.
23758 if (LIdx < 0 || RIdx < 0 ||
23759 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
23760 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
23761 continue;
23763 // Check that successive elements are being operated on. If not, this is
23764 // not a horizontal operation.
23765 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
23766 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
23767 if (!(LIdx == Index && RIdx == Index + 1) &&
23768 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
23769 return false;
23770 }
23771 }
23773 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
23774 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
23775 return true;
23776 }
23778 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
23779 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
23780 const X86Subtarget *Subtarget) {
23781 EVT VT = N->getValueType(0);
23782 SDValue LHS = N->getOperand(0);
23783 SDValue RHS = N->getOperand(1);
23785 // Try to synthesize horizontal adds from adds of shuffles.
23786 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23787 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23788 isHorizontalBinOp(LHS, RHS, true))
23789 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
23790 return SDValue();
23791 }
23793 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
23794 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
23795 const X86Subtarget *Subtarget) {
23796 EVT VT = N->getValueType(0);
23797 SDValue LHS = N->getOperand(0);
23798 SDValue RHS = N->getOperand(1);
23800 // Try to synthesize horizontal subs from subs of shuffles.
23801 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23802 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23803 isHorizontalBinOp(LHS, RHS, false))
23804 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
23805 return SDValue();
23806 }
23808 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
23809 /// X86ISD::FXOR nodes.
23810 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
23811 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
23812 // F[X]OR(0.0, x) -> x
23813 // F[X]OR(x, 0.0) -> x
23814 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23815 if (C->getValueAPF().isPosZero())
23816 return N->getOperand(1);
23817 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23818 if (C->getValueAPF().isPosZero())
23819 return N->getOperand(0);
23820 return SDValue();
23821 }
23823 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
23824 /// X86ISD::FMAX nodes.
23825 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
23826 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
23828 // Only perform optimizations if UnsafeMath is used.
23829 if (!DAG.getTarget().Options.UnsafeFPMath)
23830 return SDValue();
23832 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
23833 // into FMINC and FMAXC, which are Commutative operations.
23834 unsigned NewOp = 0;
23835 switch (N->getOpcode()) {
23836 default: llvm_unreachable("unknown opcode");
23837 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
23838 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
23839 }
23841 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
23842 N->getOperand(0), N->getOperand(1));
23843 }
23845 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
23846 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
23847 // FAND(0.0, x) -> 0.0
23848 // FAND(x, 0.0) -> 0.0
23849 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23850 if (C->getValueAPF().isPosZero())
23851 return N->getOperand(0);
23852 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23853 if (C->getValueAPF().isPosZero())
23854 return N->getOperand(1);
23855 return SDValue();
23856 }
23858 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
23859 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
23860 // FANDN(x, 0.0) -> 0.0
23861 // FANDN(0.0, x) -> x
23862 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23863 if (C->getValueAPF().isPosZero())
23864 return N->getOperand(1);
23865 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23866 if (C->getValueAPF().isPosZero())
23867 return N->getOperand(1);
23868 return SDValue();
23869 }
23871 static SDValue PerformBTCombine(SDNode *N,
23872 SelectionDAG &DAG,
23873 TargetLowering::DAGCombinerInfo &DCI) {
23874 // BT ignores high bits in the bit index operand.
23875 SDValue Op1 = N->getOperand(1);
23876 if (Op1.hasOneUse()) {
23877 unsigned BitWidth = Op1.getValueSizeInBits();
23878 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
23879 APInt KnownZero, KnownOne;
23880 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
23881 !DCI.isBeforeLegalizeOps());
23882 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23883 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
23884 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
23885 DCI.CommitTargetLoweringOpt(TLO);
23886 }
23887 return SDValue();
23888 }
23890 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
23891 SDValue Op = N->getOperand(0);
23892 if (Op.getOpcode() == ISD::BITCAST)
23893 Op = Op.getOperand(0);
23894 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
23895 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
23896 VT.getVectorElementType().getSizeInBits() ==
23897 OpVT.getVectorElementType().getSizeInBits()) {
23898 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
23899 }
23900 return SDValue();
23901 }
23903 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
23904 const X86Subtarget *Subtarget) {
23905 EVT VT = N->getValueType(0);
23906 if (!VT.isVector())
23907 return SDValue();
23909 SDValue N0 = N->getOperand(0);
23910 SDValue N1 = N->getOperand(1);
23911 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
23912 SDLoc dl(N);
23914 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
23915 // both SSE and AVX2 since there is no sign-extended shift right
23916 // operation on a vector with 64-bit elements.
23917 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
23918 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
23919 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
23920 N0.getOpcode() == ISD::SIGN_EXTEND)) {
23921 SDValue N00 = N0.getOperand(0);
23923 // EXTLOAD has a better solution on AVX2,
23924 // it may be replaced with X86ISD::VSEXT node.
23925 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
23926 if (!ISD::isNormalLoad(N00.getNode()))
23927 return SDValue();
23929 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
23930 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
23931 N00, N1);
23932 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
23933 }
23934 }
23935 return SDValue();
23936 }
23938 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
23939 TargetLowering::DAGCombinerInfo &DCI,
23940 const X86Subtarget *Subtarget) {
23941 if (!DCI.isBeforeLegalizeOps())
23942 return SDValue();
23944 if (!Subtarget->hasFp256())
23945 return SDValue();
23947 EVT VT = N->getValueType(0);
23948 if (VT.isVector() && VT.getSizeInBits() == 256) {
23949 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
23950 if (R.getNode())
23951 return R;
23952 }
23954 return SDValue();
23955 }
23957 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
23958 const X86Subtarget* Subtarget) {
23959 SDLoc dl(N);
23960 EVT VT = N->getValueType(0);
23962 // Let legalize expand this if it isn't a legal type yet.
23963 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
23964 return SDValue();
23966 EVT ScalarVT = VT.getScalarType();
23967 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
23968 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
23969 return SDValue();
23971 SDValue A = N->getOperand(0);
23972 SDValue B = N->getOperand(1);
23973 SDValue C = N->getOperand(2);
23975 bool NegA = (A.getOpcode() == ISD::FNEG);
23976 bool NegB = (B.getOpcode() == ISD::FNEG);
23977 bool NegC = (C.getOpcode() == ISD::FNEG);
23979 // Negative multiplication when NegA xor NegB
23980 bool NegMul = (NegA != NegB);
23981 if (NegA)
23982 A = A.getOperand(0);
23983 if (NegB)
23984 B = B.getOperand(0);
23985 if (NegC)
23986 C = C.getOperand(0);
23988 unsigned Opcode;
23989 if (!NegMul)
23990 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
23991 else
23992 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
23994 return DAG.getNode(Opcode, dl, VT, A, B, C);
23995 }
23997 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
23998 TargetLowering::DAGCombinerInfo &DCI,
23999 const X86Subtarget *Subtarget) {
24000 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
24001 // (and (i32 x86isd::setcc_carry), 1)
24002 // This eliminates the zext. This transformation is necessary because
24003 // ISD::SETCC is always legalized to i8.
24004 SDLoc dl(N);
24005 SDValue N0 = N->getOperand(0);
24006 EVT VT = N->getValueType(0);
24008 if (N0.getOpcode() == ISD::AND &&
24009 N0.hasOneUse() &&
24010 N0.getOperand(0).hasOneUse()) {
24011 SDValue N00 = N0.getOperand(0);
24012 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24013 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24014 if (!C || C->getZExtValue() != 1)
24015 return SDValue();
24016 return DAG.getNode(ISD::AND, dl, VT,
24017 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24018 N00.getOperand(0), N00.getOperand(1)),
24019 DAG.getConstant(1, VT));
24020 }
24021 }
24023 if (N0.getOpcode() == ISD::TRUNCATE &&
24024 N0.hasOneUse() &&
24025 N0.getOperand(0).hasOneUse()) {
24026 SDValue N00 = N0.getOperand(0);
24027 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24028 return DAG.getNode(ISD::AND, dl, VT,
24029 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24030 N00.getOperand(0), N00.getOperand(1)),
24031 DAG.getConstant(1, VT));
24032 }
24033 }
24034 if (VT.is256BitVector()) {
24035 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24036 if (R.getNode())
24037 return R;
24038 }
24040 return SDValue();
24041 }
24043 // Optimize x == -y --> x+y == 0
24044 // x != -y --> x+y != 0
24045 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
24046 const X86Subtarget* Subtarget) {
24047 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
24048 SDValue LHS = N->getOperand(0);
24049 SDValue RHS = N->getOperand(1);
24050 EVT VT = N->getValueType(0);
24051 SDLoc DL(N);
24053 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
24054 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
24055 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
24056 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
24057 LHS.getValueType(), RHS, LHS.getOperand(1));
24058 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
24059 addV, DAG.getConstant(0, addV.getValueType()), CC);
24060 }
24061 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
24062 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
24063 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
24064 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
24065 RHS.getValueType(), LHS, RHS.getOperand(1));
24066 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
24067 addV, DAG.getConstant(0, addV.getValueType()), CC);
24068 }
24070 if (VT.getScalarType() == MVT::i1) {
24071 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
24072 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24073 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
24074 if (!IsSEXT0 && !IsVZero0)
24075 return SDValue();
24076 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
24077 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24078 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
24080 if (!IsSEXT1 && !IsVZero1)
24081 return SDValue();
24083 if (IsSEXT0 && IsVZero1) {
24084 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
24085 if (CC == ISD::SETEQ)
24086 return DAG.getNOT(DL, LHS.getOperand(0), VT);
24087 return LHS.getOperand(0);
24088 }
24089 if (IsSEXT1 && IsVZero0) {
24090 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
24091 if (CC == ISD::SETEQ)
24092 return DAG.getNOT(DL, RHS.getOperand(0), VT);
24093 return RHS.getOperand(0);
24094 }
24095 }
24097 return SDValue();
24098 }
24100 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
24101 const X86Subtarget *Subtarget) {
24102 SDLoc dl(N);
24103 MVT VT = N->getOperand(1)->getSimpleValueType(0);
24104 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
24105 "X86insertps is only defined for v4x32");
24107 SDValue Ld = N->getOperand(1);
24108 if (MayFoldLoad(Ld)) {
24109 // Extract the countS bits from the immediate so we can get the proper
24110 // address when narrowing the vector load to a specific element.
24111 // When the second source op is a memory address, interps doesn't use
24112 // countS and just gets an f32 from that address.
24113 unsigned DestIndex =
24114 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
24115 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
24116 } else
24117 return SDValue();
24119 // Create this as a scalar to vector to match the instruction pattern.
24120 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
24121 // countS bits are ignored when loading from memory on insertps, which
24122 // means we don't need to explicitly set them to 0.
24123 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
24124 LoadScalarToVector, N->getOperand(2));
24125 }
24127 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
24128 // as "sbb reg,reg", since it can be extended without zext and produces
24129 // an all-ones bit which is more useful than 0/1 in some cases.
24130 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
24131 MVT VT) {
24132 if (VT == MVT::i8)
24133 return DAG.getNode(ISD::AND, DL, VT,
24134 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24135 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
24136 DAG.getConstant(1, VT));
24137 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
24138 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
24139 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24140 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
24141 }
24143 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
24144 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
24145 TargetLowering::DAGCombinerInfo &DCI,
24146 const X86Subtarget *Subtarget) {
24147 SDLoc DL(N);
24148 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
24149 SDValue EFLAGS = N->getOperand(1);
24151 if (CC == X86::COND_A) {
24152 // Try to convert COND_A into COND_B in an attempt to facilitate
24153 // materializing "setb reg".
24154 //
24155 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
24156 // cannot take an immediate as its first operand.
24157 //
24158 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
24159 EFLAGS.getValueType().isInteger() &&
24160 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
24161 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
24162 EFLAGS.getNode()->getVTList(),
24163 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
24164 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
24165 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
24166 }
24167 }
24169 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
24170 // a zext and produces an all-ones bit which is more useful than 0/1 in some
24171 // cases.
24172 if (CC == X86::COND_B)
24173 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
24175 SDValue Flags;
24177 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
24178 if (Flags.getNode()) {
24179 SDValue Cond = DAG.getConstant(CC, MVT::i8);
24180 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
24181 }
24183 return SDValue();
24184 }
24186 // Optimize branch condition evaluation.
24187 //
24188 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
24189 TargetLowering::DAGCombinerInfo &DCI,
24190 const X86Subtarget *Subtarget) {
24191 SDLoc DL(N);
24192 SDValue Chain = N->getOperand(0);
24193 SDValue Dest = N->getOperand(1);
24194 SDValue EFLAGS = N->getOperand(3);
24195 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
24197 SDValue Flags;
24199 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
24200 if (Flags.getNode()) {
24201 SDValue Cond = DAG.getConstant(CC, MVT::i8);
24202 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
24203 Flags);
24204 }
24206 return SDValue();
24207 }
24209 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
24210 SelectionDAG &DAG) {
24211 // Take advantage of vector comparisons producing 0 or -1 in each lane to
24212 // optimize away operation when it's from a constant.
24213 //
24214 // The general transformation is:
24215 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
24216 // AND(VECTOR_CMP(x,y), constant2)
24217 // constant2 = UNARYOP(constant)
24219 // Early exit if this isn't a vector operation, the operand of the
24220 // unary operation isn't a bitwise AND, or if the sizes of the operations
24221 // aren't the same.
24222 EVT VT = N->getValueType(0);
24223 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
24224 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
24225 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
24226 return SDValue();
24228 // Now check that the other operand of the AND is a constant. We could
24229 // make the transformation for non-constant splats as well, but it's unclear
24230 // that would be a benefit as it would not eliminate any operations, just
24231 // perform one more step in scalar code before moving to the vector unit.
24232 if (BuildVectorSDNode *BV =
24233 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
24234 // Bail out if the vector isn't a constant.
24235 if (!BV->isConstant())
24236 return SDValue();
24238 // Everything checks out. Build up the new and improved node.
24239 SDLoc DL(N);
24240 EVT IntVT = BV->getValueType(0);
24241 // Create a new constant of the appropriate type for the transformed
24242 // DAG.
24243 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
24244 // The AND node needs bitcasts to/from an integer vector type around it.
24245 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
24246 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
24247 N->getOperand(0)->getOperand(0), MaskConst);
24248 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
24249 return Res;
24250 }
24252 return SDValue();
24253 }
24255 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
24256 const X86TargetLowering *XTLI) {
24257 // First try to optimize away the conversion entirely when it's
24258 // conditionally from a constant. Vectors only.
24259 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
24260 if (Res != SDValue())
24261 return Res;
24263 // Now move on to more general possibilities.
24264 SDValue Op0 = N->getOperand(0);
24265 EVT InVT = Op0->getValueType(0);
24267 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
24268 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
24269 SDLoc dl(N);
24270 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
24271 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
24272 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
24273 }
24275 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
24276 // a 32-bit target where SSE doesn't support i64->FP operations.
24277 if (Op0.getOpcode() == ISD::LOAD) {
24278 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
24279 EVT VT = Ld->getValueType(0);
24280 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
24281 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
24282 !XTLI->getSubtarget()->is64Bit() &&
24283 VT == MVT::i64) {
24284 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
24285 Ld->getChain(), Op0, DAG);
24286 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
24287 return FILDChain;
24288 }
24289 }
24290 return SDValue();
24291 }
24293 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
24294 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
24295 X86TargetLowering::DAGCombinerInfo &DCI) {
24296 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
24297 // the result is either zero or one (depending on the input carry bit).
24298 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
24299 if (X86::isZeroNode(N->getOperand(0)) &&
24300 X86::isZeroNode(N->getOperand(1)) &&
24301 // We don't have a good way to replace an EFLAGS use, so only do this when
24302 // dead right now.
24303 SDValue(N, 1).use_empty()) {
24304 SDLoc DL(N);
24305 EVT VT = N->getValueType(0);
24306 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
24307 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
24308 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
24309 DAG.getConstant(X86::COND_B,MVT::i8),
24310 N->getOperand(2)),
24311 DAG.getConstant(1, VT));
24312 return DCI.CombineTo(N, Res1, CarryOut);
24313 }
24315 return SDValue();
24316 }
24318 // fold (add Y, (sete X, 0)) -> adc 0, Y
24319 // (add Y, (setne X, 0)) -> sbb -1, Y
24320 // (sub (sete X, 0), Y) -> sbb 0, Y
24321 // (sub (setne X, 0), Y) -> adc -1, Y
24322 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
24323 SDLoc DL(N);
24325 // Look through ZExts.
24326 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
24327 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
24328 return SDValue();
24330 SDValue SetCC = Ext.getOperand(0);
24331 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
24332 return SDValue();
24334 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
24335 if (CC != X86::COND_E && CC != X86::COND_NE)
24336 return SDValue();
24338 SDValue Cmp = SetCC.getOperand(1);
24339 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
24340 !X86::isZeroNode(Cmp.getOperand(1)) ||
24341 !Cmp.getOperand(0).getValueType().isInteger())
24342 return SDValue();
24344 SDValue CmpOp0 = Cmp.getOperand(0);
24345 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
24346 DAG.getConstant(1, CmpOp0.getValueType()));
24348 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
24349 if (CC == X86::COND_NE)
24350 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
24351 DL, OtherVal.getValueType(), OtherVal,
24352 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
24353 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
24354 DL, OtherVal.getValueType(), OtherVal,
24355 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
24356 }
24358 /// PerformADDCombine - Do target-specific dag combines on integer adds.
24359 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
24360 const X86Subtarget *Subtarget) {
24361 EVT VT = N->getValueType(0);
24362 SDValue Op0 = N->getOperand(0);
24363 SDValue Op1 = N->getOperand(1);
24365 // Try to synthesize horizontal adds from adds of shuffles.
24366 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24367 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24368 isHorizontalBinOp(Op0, Op1, true))
24369 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
24371 return OptimizeConditionalInDecrement(N, DAG);
24372 }
24374 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
24375 const X86Subtarget *Subtarget) {
24376 SDValue Op0 = N->getOperand(0);
24377 SDValue Op1 = N->getOperand(1);
24379 // X86 can't encode an immediate LHS of a sub. See if we can push the
24380 // negation into a preceding instruction.
24381 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
24382 // If the RHS of the sub is a XOR with one use and a constant, invert the
24383 // immediate. Then add one to the LHS of the sub so we can turn
24384 // X-Y -> X+~Y+1, saving one register.
24385 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
24386 isa<ConstantSDNode>(Op1.getOperand(1))) {
24387 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
24388 EVT VT = Op0.getValueType();
24389 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
24390 Op1.getOperand(0),
24391 DAG.getConstant(~XorC, VT));
24392 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
24393 DAG.getConstant(C->getAPIntValue()+1, VT));
24394 }
24395 }
24397 // Try to synthesize horizontal adds from adds of shuffles.
24398 EVT VT = N->getValueType(0);
24399 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24400 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24401 isHorizontalBinOp(Op0, Op1, true))
24402 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
24404 return OptimizeConditionalInDecrement(N, DAG);
24405 }
24407 /// performVZEXTCombine - Performs build vector combines
24408 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
24409 TargetLowering::DAGCombinerInfo &DCI,
24410 const X86Subtarget *Subtarget) {
24411 // (vzext (bitcast (vzext (x)) -> (vzext x)
24412 SDValue In = N->getOperand(0);
24413 while (In.getOpcode() == ISD::BITCAST)
24414 In = In.getOperand(0);
24416 if (In.getOpcode() != X86ISD::VZEXT)
24417 return SDValue();
24419 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
24420 In.getOperand(0));
24421 }
24423 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
24424 DAGCombinerInfo &DCI) const {
24425 SelectionDAG &DAG = DCI.DAG;
24426 switch (N->getOpcode()) {
24427 default: break;
24428 case ISD::EXTRACT_VECTOR_ELT:
24429 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
24430 case ISD::VSELECT:
24431 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
24432 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
24433 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
24434 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
24435 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
24436 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
24437 case ISD::SHL:
24438 case ISD::SRA:
24439 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
24440 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
24441 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
24442 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
24443 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
24444 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
24445 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
24446 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
24447 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
24448 case X86ISD::FXOR:
24449 case X86ISD::FOR: return PerformFORCombine(N, DAG);
24450 case X86ISD::FMIN:
24451 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
24452 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
24453 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
24454 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
24455 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
24456 case ISD::ANY_EXTEND:
24457 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
24458 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
24459 case ISD::SIGN_EXTEND_INREG:
24460 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
24461 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
24462 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
24463 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
24464 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
24465 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
24466 case X86ISD::SHUFP: // Handle all target specific shuffles
24467 case X86ISD::PALIGNR:
24468 case X86ISD::UNPCKH:
24469 case X86ISD::UNPCKL:
24470 case X86ISD::MOVHLPS:
24471 case X86ISD::MOVLHPS:
24472 case X86ISD::PSHUFB:
24473 case X86ISD::PSHUFD:
24474 case X86ISD::PSHUFHW:
24475 case X86ISD::PSHUFLW:
24476 case X86ISD::MOVSS:
24477 case X86ISD::MOVSD:
24478 case X86ISD::VPERMILPI:
24479 case X86ISD::VPERM2X128:
24480 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
24481 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
24482 case ISD::INTRINSIC_WO_CHAIN:
24483 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
24484 case X86ISD::INSERTPS:
24485 return PerformINSERTPSCombine(N, DAG, Subtarget);
24486 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
24487 }
24489 return SDValue();
24490 }
24492 /// isTypeDesirableForOp - Return true if the target has native support for
24493 /// the specified value type and it is 'desirable' to use the type for the
24494 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
24495 /// instruction encodings are longer and some i16 instructions are slow.
24496 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
24497 if (!isTypeLegal(VT))
24498 return false;
24499 if (VT != MVT::i16)
24500 return true;
24502 switch (Opc) {
24503 default:
24504 return true;
24505 case ISD::LOAD:
24506 case ISD::SIGN_EXTEND:
24507 case ISD::ZERO_EXTEND:
24508 case ISD::ANY_EXTEND:
24509 case ISD::SHL:
24510 case ISD::SRL:
24511 case ISD::SUB:
24512 case ISD::ADD:
24513 case ISD::MUL:
24514 case ISD::AND:
24515 case ISD::OR:
24516 case ISD::XOR:
24517 return false;
24518 }
24519 }
24521 /// IsDesirableToPromoteOp - This method query the target whether it is
24522 /// beneficial for dag combiner to promote the specified node. If true, it
24523 /// should return the desired promotion type by reference.
24524 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
24525 EVT VT = Op.getValueType();
24526 if (VT != MVT::i16)
24527 return false;
24529 bool Promote = false;
24530 bool Commute = false;
24531 switch (Op.getOpcode()) {
24532 default: break;
24533 case ISD::LOAD: {
24534 LoadSDNode *LD = cast<LoadSDNode>(Op);
24535 // If the non-extending load has a single use and it's not live out, then it
24536 // might be folded.
24537 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
24538 Op.hasOneUse()*/) {
24539 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
24540 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
24541 // The only case where we'd want to promote LOAD (rather then it being
24542 // promoted as an operand is when it's only use is liveout.
24543 if (UI->getOpcode() != ISD::CopyToReg)
24544 return false;
24545 }
24546 }
24547 Promote = true;
24548 break;
24549 }
24550 case ISD::SIGN_EXTEND:
24551 case ISD::ZERO_EXTEND:
24552 case ISD::ANY_EXTEND:
24553 Promote = true;
24554 break;
24555 case ISD::SHL:
24556 case ISD::SRL: {
24557 SDValue N0 = Op.getOperand(0);
24558 // Look out for (store (shl (load), x)).
24559 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
24560 return false;
24561 Promote = true;
24562 break;
24563 }
24564 case ISD::ADD:
24565 case ISD::MUL:
24566 case ISD::AND:
24567 case ISD::OR:
24568 case ISD::XOR:
24569 Commute = true;
24570 // fallthrough
24571 case ISD::SUB: {
24572 SDValue N0 = Op.getOperand(0);
24573 SDValue N1 = Op.getOperand(1);
24574 if (!Commute && MayFoldLoad(N1))
24575 return false;
24576 // Avoid disabling potential load folding opportunities.
24577 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
24578 return false;
24579 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
24580 return false;
24581 Promote = true;
24582 }
24583 }
24585 PVT = MVT::i32;
24586 return Promote;
24587 }
24589 //===----------------------------------------------------------------------===//
24590 // X86 Inline Assembly Support
24591 //===----------------------------------------------------------------------===//
24593 namespace {
24594 // Helper to match a string separated by whitespace.
24595 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
24596 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
24598 for (unsigned i = 0, e = args.size(); i != e; ++i) {
24599 StringRef piece(*args[i]);
24600 if (!s.startswith(piece)) // Check if the piece matches.
24601 return false;
24603 s = s.substr(piece.size());
24604 StringRef::size_type pos = s.find_first_not_of(" \t");
24605 if (pos == 0) // We matched a prefix.
24606 return false;
24608 s = s.substr(pos);
24609 }
24611 return s.empty();
24612 }
24613 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
24614 }
24616 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
24618 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
24619 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
24620 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
24621 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
24623 if (AsmPieces.size() == 3)
24624 return true;
24625 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
24626 return true;
24627 }
24628 }
24629 return false;
24630 }
24632 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
24633 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
24635 std::string AsmStr = IA->getAsmString();
24637 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
24638 if (!Ty || Ty->getBitWidth() % 16 != 0)
24639 return false;
24641 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
24642 SmallVector<StringRef, 4> AsmPieces;
24643 SplitString(AsmStr, AsmPieces, ";\n");
24645 switch (AsmPieces.size()) {
24646 default: return false;
24647 case 1:
24648 // FIXME: this should verify that we are targeting a 486 or better. If not,
24649 // we will turn this bswap into something that will be lowered to logical
24650 // ops instead of emitting the bswap asm. For now, we don't support 486 or
24651 // lower so don't worry about this.
24652 // bswap $0
24653 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
24654 matchAsm(AsmPieces[0], "bswapl", "$0") ||
24655 matchAsm(AsmPieces[0], "bswapq", "$0") ||
24656 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
24657 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
24658 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
24659 // No need to check constraints, nothing other than the equivalent of
24660 // "=r,0" would be valid here.
24661 return IntrinsicLowering::LowerToByteSwap(CI);
24662 }
24664 // rorw $$8, ${0:w} --> llvm.bswap.i16
24665 if (CI->getType()->isIntegerTy(16) &&
24666 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24667 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
24668 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
24669 AsmPieces.clear();
24670 const std::string &ConstraintsStr = IA->getConstraintString();
24671 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24672 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24673 if (clobbersFlagRegisters(AsmPieces))
24674 return IntrinsicLowering::LowerToByteSwap(CI);
24675 }
24676 break;
24677 case 3:
24678 if (CI->getType()->isIntegerTy(32) &&
24679 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24680 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
24681 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
24682 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
24683 AsmPieces.clear();
24684 const std::string &ConstraintsStr = IA->getConstraintString();
24685 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24686 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24687 if (clobbersFlagRegisters(AsmPieces))
24688 return IntrinsicLowering::LowerToByteSwap(CI);
24689 }
24691 if (CI->getType()->isIntegerTy(64)) {
24692 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
24693 if (Constraints.size() >= 2 &&
24694 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
24695 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
24696 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
24697 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
24698 matchAsm(AsmPieces[1], "bswap", "%edx") &&
24699 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
24700 return IntrinsicLowering::LowerToByteSwap(CI);
24701 }
24702 }
24703 break;
24704 }
24705 return false;
24706 }
24708 /// getConstraintType - Given a constraint letter, return the type of
24709 /// constraint it is for this target.
24710 X86TargetLowering::ConstraintType
24711 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
24712 if (Constraint.size() == 1) {
24713 switch (Constraint[0]) {
24714 case 'R':
24715 case 'q':
24716 case 'Q':
24717 case 'f':
24718 case 't':
24719 case 'u':
24720 case 'y':
24721 case 'x':
24722 case 'Y':
24723 case 'l':
24724 return C_RegisterClass;
24725 case 'a':
24726 case 'b':
24727 case 'c':
24728 case 'd':
24729 case 'S':
24730 case 'D':
24731 case 'A':
24732 return C_Register;
24733 case 'I':
24734 case 'J':
24735 case 'K':
24736 case 'L':
24737 case 'M':
24738 case 'N':
24739 case 'G':
24740 case 'C':
24741 case 'e':
24742 case 'Z':
24743 return C_Other;
24744 default:
24745 break;
24746 }
24747 }
24748 return TargetLowering::getConstraintType(Constraint);
24749 }
24751 /// Examine constraint type and operand type and determine a weight value.
24752 /// This object must already have been set up with the operand type
24753 /// and the current alternative constraint selected.
24754 TargetLowering::ConstraintWeight
24755 X86TargetLowering::getSingleConstraintMatchWeight(
24756 AsmOperandInfo &info, const char *constraint) const {
24757 ConstraintWeight weight = CW_Invalid;
24758 Value *CallOperandVal = info.CallOperandVal;
24759 // If we don't have a value, we can't do a match,
24760 // but allow it at the lowest weight.
24761 if (!CallOperandVal)
24762 return CW_Default;
24763 Type *type = CallOperandVal->getType();
24764 // Look at the constraint type.
24765 switch (*constraint) {
24766 default:
24767 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
24768 case 'R':
24769 case 'q':
24770 case 'Q':
24771 case 'a':
24772 case 'b':
24773 case 'c':
24774 case 'd':
24775 case 'S':
24776 case 'D':
24777 case 'A':
24778 if (CallOperandVal->getType()->isIntegerTy())
24779 weight = CW_SpecificReg;
24780 break;
24781 case 'f':
24782 case 't':
24783 case 'u':
24784 if (type->isFloatingPointTy())
24785 weight = CW_SpecificReg;
24786 break;
24787 case 'y':
24788 if (type->isX86_MMXTy() && Subtarget->hasMMX())
24789 weight = CW_SpecificReg;
24790 break;
24791 case 'x':
24792 case 'Y':
24793 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
24794 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
24795 weight = CW_Register;
24796 break;
24797 case 'I':
24798 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
24799 if (C->getZExtValue() <= 31)
24800 weight = CW_Constant;
24801 }
24802 break;
24803 case 'J':
24804 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24805 if (C->getZExtValue() <= 63)
24806 weight = CW_Constant;
24807 }
24808 break;
24809 case 'K':
24810 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24811 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
24812 weight = CW_Constant;
24813 }
24814 break;
24815 case 'L':
24816 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24817 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
24818 weight = CW_Constant;
24819 }
24820 break;
24821 case 'M':
24822 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24823 if (C->getZExtValue() <= 3)
24824 weight = CW_Constant;
24825 }
24826 break;
24827 case 'N':
24828 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24829 if (C->getZExtValue() <= 0xff)
24830 weight = CW_Constant;
24831 }
24832 break;
24833 case 'G':
24834 case 'C':
24835 if (dyn_cast<ConstantFP>(CallOperandVal)) {
24836 weight = CW_Constant;
24837 }
24838 break;
24839 case 'e':
24840 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24841 if ((C->getSExtValue() >= -0x80000000LL) &&
24842 (C->getSExtValue() <= 0x7fffffffLL))
24843 weight = CW_Constant;
24844 }
24845 break;
24846 case 'Z':
24847 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24848 if (C->getZExtValue() <= 0xffffffff)
24849 weight = CW_Constant;
24850 }
24851 break;
24852 }
24853 return weight;
24854 }
24856 /// LowerXConstraint - try to replace an X constraint, which matches anything,
24857 /// with another that has more specific requirements based on the type of the
24858 /// corresponding operand.
24859 const char *X86TargetLowering::
24860 LowerXConstraint(EVT ConstraintVT) const {
24861 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
24862 // 'f' like normal targets.
24863 if (ConstraintVT.isFloatingPoint()) {
24864 if (Subtarget->hasSSE2())
24865 return "Y";
24866 if (Subtarget->hasSSE1())
24867 return "x";
24868 }
24870 return TargetLowering::LowerXConstraint(ConstraintVT);
24871 }
24873 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
24874 /// vector. If it is invalid, don't add anything to Ops.
24875 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
24876 std::string &Constraint,
24877 std::vector<SDValue>&Ops,
24878 SelectionDAG &DAG) const {
24879 SDValue Result;
24881 // Only support length 1 constraints for now.
24882 if (Constraint.length() > 1) return;
24884 char ConstraintLetter = Constraint[0];
24885 switch (ConstraintLetter) {
24886 default: break;
24887 case 'I':
24888 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24889 if (C->getZExtValue() <= 31) {
24890 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24891 break;
24892 }
24893 }
24894 return;
24895 case 'J':
24896 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24897 if (C->getZExtValue() <= 63) {
24898 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24899 break;
24900 }
24901 }
24902 return;
24903 case 'K':
24904 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24905 if (isInt<8>(C->getSExtValue())) {
24906 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24907 break;
24908 }
24909 }
24910 return;
24911 case 'N':
24912 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24913 if (C->getZExtValue() <= 255) {
24914 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24915 break;
24916 }
24917 }
24918 return;
24919 case 'e': {
24920 // 32-bit signed value
24921 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24922 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
24923 C->getSExtValue())) {
24924 // Widen to 64 bits here to get it sign extended.
24925 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
24926 break;
24927 }
24928 // FIXME gcc accepts some relocatable values here too, but only in certain
24929 // memory models; it's complicated.
24930 }
24931 return;
24932 }
24933 case 'Z': {
24934 // 32-bit unsigned value
24935 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24936 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
24937 C->getZExtValue())) {
24938 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24939 break;
24940 }
24941 }
24942 // FIXME gcc accepts some relocatable values here too, but only in certain
24943 // memory models; it's complicated.
24944 return;
24945 }
24946 case 'i': {
24947 // Literal immediates are always ok.
24948 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
24949 // Widen to 64 bits here to get it sign extended.
24950 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
24951 break;
24952 }
24954 // In any sort of PIC mode addresses need to be computed at runtime by
24955 // adding in a register or some sort of table lookup. These can't
24956 // be used as immediates.
24957 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
24958 return;
24960 // If we are in non-pic codegen mode, we allow the address of a global (with
24961 // an optional displacement) to be used with 'i'.
24962 GlobalAddressSDNode *GA = nullptr;
24963 int64_t Offset = 0;
24965 // Match either (GA), (GA+C), (GA+C1+C2), etc.
24966 while (1) {
24967 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
24968 Offset += GA->getOffset();
24969 break;
24970 } else if (Op.getOpcode() == ISD::ADD) {
24971 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
24972 Offset += C->getZExtValue();
24973 Op = Op.getOperand(0);
24974 continue;
24975 }
24976 } else if (Op.getOpcode() == ISD::SUB) {
24977 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
24978 Offset += -C->getZExtValue();
24979 Op = Op.getOperand(0);
24980 continue;
24981 }
24982 }
24984 // Otherwise, this isn't something we can handle, reject it.
24985 return;
24986 }
24988 const GlobalValue *GV = GA->getGlobal();
24989 // If we require an extra load to get this address, as in PIC mode, we
24990 // can't accept it.
24991 if (isGlobalStubReference(
24992 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
24993 return;
24995 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
24996 GA->getValueType(0), Offset);
24997 break;
24998 }
24999 }
25001 if (Result.getNode()) {
25002 Ops.push_back(Result);
25003 return;
25004 }
25005 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
25006 }
25008 std::pair<unsigned, const TargetRegisterClass*>
25009 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
25010 MVT VT) const {
25011 // First, see if this is a constraint that directly corresponds to an LLVM
25012 // register class.
25013 if (Constraint.size() == 1) {
25014 // GCC Constraint Letters
25015 switch (Constraint[0]) {
25016 default: break;
25017 // TODO: Slight differences here in allocation order and leaving
25018 // RIP in the class. Do they matter any more here than they do
25019 // in the normal allocation?
25020 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
25021 if (Subtarget->is64Bit()) {
25022 if (VT == MVT::i32 || VT == MVT::f32)
25023 return std::make_pair(0U, &X86::GR32RegClass);
25024 if (VT == MVT::i16)
25025 return std::make_pair(0U, &X86::GR16RegClass);
25026 if (VT == MVT::i8 || VT == MVT::i1)
25027 return std::make_pair(0U, &X86::GR8RegClass);
25028 if (VT == MVT::i64 || VT == MVT::f64)
25029 return std::make_pair(0U, &X86::GR64RegClass);
25030 break;
25031 }
25032 // 32-bit fallthrough
25033 case 'Q': // Q_REGS
25034 if (VT == MVT::i32 || VT == MVT::f32)
25035 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
25036 if (VT == MVT::i16)
25037 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
25038 if (VT == MVT::i8 || VT == MVT::i1)
25039 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
25040 if (VT == MVT::i64)
25041 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
25042 break;
25043 case 'r': // GENERAL_REGS
25044 case 'l': // INDEX_REGS
25045 if (VT == MVT::i8 || VT == MVT::i1)
25046 return std::make_pair(0U, &X86::GR8RegClass);
25047 if (VT == MVT::i16)
25048 return std::make_pair(0U, &X86::GR16RegClass);
25049 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
25050 return std::make_pair(0U, &X86::GR32RegClass);
25051 return std::make_pair(0U, &X86::GR64RegClass);
25052 case 'R': // LEGACY_REGS
25053 if (VT == MVT::i8 || VT == MVT::i1)
25054 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
25055 if (VT == MVT::i16)
25056 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
25057 if (VT == MVT::i32 || !Subtarget->is64Bit())
25058 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
25059 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
25060 case 'f': // FP Stack registers.
25061 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
25062 // value to the correct fpstack register class.
25063 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
25064 return std::make_pair(0U, &X86::RFP32RegClass);
25065 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
25066 return std::make_pair(0U, &X86::RFP64RegClass);
25067 return std::make_pair(0U, &X86::RFP80RegClass);
25068 case 'y': // MMX_REGS if MMX allowed.
25069 if (!Subtarget->hasMMX()) break;
25070 return std::make_pair(0U, &X86::VR64RegClass);
25071 case 'Y': // SSE_REGS if SSE2 allowed
25072 if (!Subtarget->hasSSE2()) break;
25073 // FALL THROUGH.
25074 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
25075 if (!Subtarget->hasSSE1()) break;
25077 switch (VT.SimpleTy) {
25078 default: break;
25079 // Scalar SSE types.
25080 case MVT::f32:
25081 case MVT::i32:
25082 return std::make_pair(0U, &X86::FR32RegClass);
25083 case MVT::f64:
25084 case MVT::i64:
25085 return std::make_pair(0U, &X86::FR64RegClass);
25086 // Vector types.
25087 case MVT::v16i8:
25088 case MVT::v8i16:
25089 case MVT::v4i32:
25090 case MVT::v2i64:
25091 case MVT::v4f32:
25092 case MVT::v2f64:
25093 return std::make_pair(0U, &X86::VR128RegClass);
25094 // AVX types.
25095 case MVT::v32i8:
25096 case MVT::v16i16:
25097 case MVT::v8i32:
25098 case MVT::v4i64:
25099 case MVT::v8f32:
25100 case MVT::v4f64:
25101 return std::make_pair(0U, &X86::VR256RegClass);
25102 case MVT::v8f64:
25103 case MVT::v16f32:
25104 case MVT::v16i32:
25105 case MVT::v8i64:
25106 return std::make_pair(0U, &X86::VR512RegClass);
25107 }
25108 break;
25109 }
25110 }
25112 // Use the default implementation in TargetLowering to convert the register
25113 // constraint into a member of a register class.
25114 std::pair<unsigned, const TargetRegisterClass*> Res;
25115 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
25117 // Not found as a standard register?
25118 if (!Res.second) {
25119 // Map st(0) -> st(7) -> ST0
25120 if (Constraint.size() == 7 && Constraint[0] == '{' &&
25121 tolower(Constraint[1]) == 's' &&
25122 tolower(Constraint[2]) == 't' &&
25123 Constraint[3] == '(' &&
25124 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
25125 Constraint[5] == ')' &&
25126 Constraint[6] == '}') {
25128 Res.first = X86::FP0+Constraint[4]-'0';
25129 Res.second = &X86::RFP80RegClass;
25130 return Res;
25131 }
25133 // GCC allows "st(0)" to be called just plain "st".
25134 if (StringRef("{st}").equals_lower(Constraint)) {
25135 Res.first = X86::FP0;
25136 Res.second = &X86::RFP80RegClass;
25137 return Res;
25138 }
25140 // flags -> EFLAGS
25141 if (StringRef("{flags}").equals_lower(Constraint)) {
25142 Res.first = X86::EFLAGS;
25143 Res.second = &X86::CCRRegClass;
25144 return Res;
25145 }
25147 // 'A' means EAX + EDX.
25148 if (Constraint == "A") {
25149 Res.first = X86::EAX;
25150 Res.second = &X86::GR32_ADRegClass;
25151 return Res;
25152 }
25153 return Res;
25154 }
25156 // Otherwise, check to see if this is a register class of the wrong value
25157 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
25158 // turn into {ax},{dx}.
25159 if (Res.second->hasType(VT))
25160 return Res; // Correct type already, nothing to do.
25162 // All of the single-register GCC register classes map their values onto
25163 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
25164 // really want an 8-bit or 32-bit register, map to the appropriate register
25165 // class and return the appropriate register.
25166 if (Res.second == &X86::GR16RegClass) {
25167 if (VT == MVT::i8 || VT == MVT::i1) {
25168 unsigned DestReg = 0;
25169 switch (Res.first) {
25170 default: break;
25171 case X86::AX: DestReg = X86::AL; break;
25172 case X86::DX: DestReg = X86::DL; break;
25173 case X86::CX: DestReg = X86::CL; break;
25174 case X86::BX: DestReg = X86::BL; break;
25175 }
25176 if (DestReg) {
25177 Res.first = DestReg;
25178 Res.second = &X86::GR8RegClass;
25179 }
25180 } else if (VT == MVT::i32 || VT == MVT::f32) {
25181 unsigned DestReg = 0;
25182 switch (Res.first) {
25183 default: break;
25184 case X86::AX: DestReg = X86::EAX; break;
25185 case X86::DX: DestReg = X86::EDX; break;
25186 case X86::CX: DestReg = X86::ECX; break;
25187 case X86::BX: DestReg = X86::EBX; break;
25188 case X86::SI: DestReg = X86::ESI; break;
25189 case X86::DI: DestReg = X86::EDI; break;
25190 case X86::BP: DestReg = X86::EBP; break;
25191 case X86::SP: DestReg = X86::ESP; break;
25192 }
25193 if (DestReg) {
25194 Res.first = DestReg;
25195 Res.second = &X86::GR32RegClass;
25196 }
25197 } else if (VT == MVT::i64 || VT == MVT::f64) {
25198 unsigned DestReg = 0;
25199 switch (Res.first) {
25200 default: break;
25201 case X86::AX: DestReg = X86::RAX; break;
25202 case X86::DX: DestReg = X86::RDX; break;
25203 case X86::CX: DestReg = X86::RCX; break;
25204 case X86::BX: DestReg = X86::RBX; break;
25205 case X86::SI: DestReg = X86::RSI; break;
25206 case X86::DI: DestReg = X86::RDI; break;
25207 case X86::BP: DestReg = X86::RBP; break;
25208 case X86::SP: DestReg = X86::RSP; break;
25209 }
25210 if (DestReg) {
25211 Res.first = DestReg;
25212 Res.second = &X86::GR64RegClass;
25213 }
25214 }
25215 } else if (Res.second == &X86::FR32RegClass ||
25216 Res.second == &X86::FR64RegClass ||
25217 Res.second == &X86::VR128RegClass ||
25218 Res.second == &X86::VR256RegClass ||
25219 Res.second == &X86::FR32XRegClass ||
25220 Res.second == &X86::FR64XRegClass ||
25221 Res.second == &X86::VR128XRegClass ||
25222 Res.second == &X86::VR256XRegClass ||
25223 Res.second == &X86::VR512RegClass) {
25224 // Handle references to XMM physical registers that got mapped into the
25225 // wrong class. This can happen with constraints like {xmm0} where the
25226 // target independent register mapper will just pick the first match it can
25227 // find, ignoring the required type.
25229 if (VT == MVT::f32 || VT == MVT::i32)
25230 Res.second = &X86::FR32RegClass;
25231 else if (VT == MVT::f64 || VT == MVT::i64)
25232 Res.second = &X86::FR64RegClass;
25233 else if (X86::VR128RegClass.hasType(VT))
25234 Res.second = &X86::VR128RegClass;
25235 else if (X86::VR256RegClass.hasType(VT))
25236 Res.second = &X86::VR256RegClass;
25237 else if (X86::VR512RegClass.hasType(VT))
25238 Res.second = &X86::VR512RegClass;
25239 }
25241 return Res;
25242 }
25244 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
25245 Type *Ty) const {
25246 // Scaling factors are not free at all.
25247 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
25248 // will take 2 allocations in the out of order engine instead of 1
25249 // for plain addressing mode, i.e. inst (reg1).
25250 // E.g.,
25251 // vaddps (%rsi,%drx), %ymm0, %ymm1
25252 // Requires two allocations (one for the load, one for the computation)
25253 // whereas:
25254 // vaddps (%rsi), %ymm0, %ymm1
25255 // Requires just 1 allocation, i.e., freeing allocations for other operations
25256 // and having less micro operations to execute.
25257 //
25258 // For some X86 architectures, this is even worse because for instance for
25259 // stores, the complex addressing mode forces the instruction to use the
25260 // "load" ports instead of the dedicated "store" port.
25261 // E.g., on Haswell:
25262 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
25263 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
25264 if (isLegalAddressingMode(AM, Ty))
25265 // Scale represents reg2 * scale, thus account for 1
25266 // as soon as we use a second register.
25267 return AM.Scale != 0;
25268 return -1;
25269 }
25271 bool X86TargetLowering::isTargetFTOL() const {
25272 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();
25273 }