1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
54 #include <bitset>
55 #include <numeric>
56 #include <cctype>
57 using namespace llvm;
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
67 cl::Hidden);
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(false),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
72 cl::Hidden);
74 // Forward declarations.
75 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
76 SDValue V2);
78 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
79 SelectionDAG &DAG, SDLoc dl,
80 unsigned vectorWidth) {
81 assert((vectorWidth == 128 || vectorWidth == 256) &&
82 "Unsupported vector width");
83 EVT VT = Vec.getValueType();
84 EVT ElVT = VT.getVectorElementType();
85 unsigned Factor = VT.getSizeInBits()/vectorWidth;
86 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
87 VT.getVectorNumElements()/Factor);
89 // Extract from UNDEF is UNDEF.
90 if (Vec.getOpcode() == ISD::UNDEF)
91 return DAG.getUNDEF(ResultVT);
93 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
94 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
96 // This is the index of the first element of the vectorWidth-bit chunk
97 // we want.
98 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
99 * ElemsPerChunk);
101 // If the input is a buildvector just emit a smaller one.
102 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
103 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
104 makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
105 ElemsPerChunk));
107 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
108 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
109 VecIdx);
111 return Result;
113 }
114 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
115 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
116 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
117 /// instructions or a simple subregister reference. Idx is an index in the
118 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
119 /// lowering EXTRACT_VECTOR_ELT operations easier.
120 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
121 SelectionDAG &DAG, SDLoc dl) {
122 assert((Vec.getValueType().is256BitVector() ||
123 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
124 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
125 }
127 /// Generate a DAG to grab 256-bits from a 512-bit vector.
128 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
129 SelectionDAG &DAG, SDLoc dl) {
130 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
131 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
132 }
134 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
135 unsigned IdxVal, SelectionDAG &DAG,
136 SDLoc dl, unsigned vectorWidth) {
137 assert((vectorWidth == 128 || vectorWidth == 256) &&
138 "Unsupported vector width");
139 // Inserting UNDEF is Result
140 if (Vec.getOpcode() == ISD::UNDEF)
141 return Result;
142 EVT VT = Vec.getValueType();
143 EVT ElVT = VT.getVectorElementType();
144 EVT ResultVT = Result.getValueType();
146 // Insert the relevant vectorWidth bits.
147 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
149 // This is the index of the first element of the vectorWidth-bit chunk
150 // we want.
151 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
152 * ElemsPerChunk);
154 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
155 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
156 VecIdx);
157 }
158 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
159 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
160 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
161 /// simple superregister reference. Idx is an index in the 128 bits
162 /// we want. It need not be aligned to a 128-bit bounday. That makes
163 /// lowering INSERT_VECTOR_ELT operations easier.
164 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
165 unsigned IdxVal, SelectionDAG &DAG,
166 SDLoc dl) {
167 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
168 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
169 }
171 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
172 unsigned IdxVal, SelectionDAG &DAG,
173 SDLoc dl) {
174 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
175 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
176 }
178 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
179 /// instructions. This is used because creating CONCAT_VECTOR nodes of
180 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
181 /// large BUILD_VECTORS.
182 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
183 unsigned NumElems, SelectionDAG &DAG,
184 SDLoc dl) {
185 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
186 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
187 }
189 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
190 unsigned NumElems, SelectionDAG &DAG,
191 SDLoc dl) {
192 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
193 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
194 }
196 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
197 if (TT.isOSBinFormatMachO()) {
198 if (TT.getArch() == Triple::x86_64)
199 return new X86_64MachoTargetObjectFile();
200 return new TargetLoweringObjectFileMachO();
201 }
203 if (TT.isOSLinux())
204 return new X86LinuxTargetObjectFile();
205 if (TT.isOSBinFormatELF())
206 return new TargetLoweringObjectFileELF();
207 if (TT.isKnownWindowsMSVCEnvironment())
208 return new X86WindowsTargetObjectFile();
209 if (TT.isOSBinFormatCOFF())
210 return new TargetLoweringObjectFileCOFF();
211 llvm_unreachable("unknown subtarget type");
212 }
214 // FIXME: This should stop caching the target machine as soon as
215 // we can remove resetOperationActions et al.
216 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
217 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
218 Subtarget = &TM.getSubtarget<X86Subtarget>();
219 X86ScalarSSEf64 = Subtarget->hasSSE2();
220 X86ScalarSSEf32 = Subtarget->hasSSE1();
221 TD = getDataLayout();
223 resetOperationActions();
224 }
226 void X86TargetLowering::resetOperationActions() {
227 const TargetMachine &TM = getTargetMachine();
228 static bool FirstTimeThrough = true;
230 // If none of the target options have changed, then we don't need to reset the
231 // operation actions.
232 if (!FirstTimeThrough && TO == TM.Options) return;
234 if (!FirstTimeThrough) {
235 // Reinitialize the actions.
236 initActions();
237 FirstTimeThrough = false;
238 }
240 TO = TM.Options;
242 // Set up the TargetLowering object.
243 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
245 // X86 is weird, it always uses i8 for shift amounts and setcc results.
246 setBooleanContents(ZeroOrOneBooleanContent);
247 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
248 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
250 // For 64-bit since we have so many registers use the ILP scheduler, for
251 // 32-bit code use the register pressure specific scheduling.
252 // For Atom, always use ILP scheduling.
253 if (Subtarget->isAtom())
254 setSchedulingPreference(Sched::ILP);
255 else if (Subtarget->is64Bit())
256 setSchedulingPreference(Sched::ILP);
257 else
258 setSchedulingPreference(Sched::RegPressure);
259 const X86RegisterInfo *RegInfo =
260 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
261 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
263 // Bypass expensive divides on Atom when compiling with O2
264 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
265 addBypassSlowDiv(32, 8);
266 if (Subtarget->is64Bit())
267 addBypassSlowDiv(64, 16);
268 }
270 if (Subtarget->isTargetKnownWindowsMSVC()) {
271 // Setup Windows compiler runtime calls.
272 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
273 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
274 setLibcallName(RTLIB::SREM_I64, "_allrem");
275 setLibcallName(RTLIB::UREM_I64, "_aullrem");
276 setLibcallName(RTLIB::MUL_I64, "_allmul");
277 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
278 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
279 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
280 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
281 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
283 // The _ftol2 runtime function has an unusual calling conv, which
284 // is modeled by a special pseudo-instruction.
285 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
286 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
287 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
288 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
289 }
291 if (Subtarget->isTargetDarwin()) {
292 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
293 setUseUnderscoreSetJmp(false);
294 setUseUnderscoreLongJmp(false);
295 } else if (Subtarget->isTargetWindowsGNU()) {
296 // MS runtime is weird: it exports _setjmp, but longjmp!
297 setUseUnderscoreSetJmp(true);
298 setUseUnderscoreLongJmp(false);
299 } else {
300 setUseUnderscoreSetJmp(true);
301 setUseUnderscoreLongJmp(true);
302 }
304 // Set up the register classes.
305 addRegisterClass(MVT::i8, &X86::GR8RegClass);
306 addRegisterClass(MVT::i16, &X86::GR16RegClass);
307 addRegisterClass(MVT::i32, &X86::GR32RegClass);
308 if (Subtarget->is64Bit())
309 addRegisterClass(MVT::i64, &X86::GR64RegClass);
311 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
313 // We don't accept any truncstore of integer registers.
314 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
315 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
316 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
317 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
318 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
319 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
321 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
323 // SETOEQ and SETUNE require checking two conditions.
324 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
325 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
326 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
327 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
328 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
329 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
331 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
332 // operation.
333 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
334 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
335 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
337 if (Subtarget->is64Bit()) {
338 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
339 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
340 } else if (!TM.Options.UseSoftFloat) {
341 // We have an algorithm for SSE2->double, and we turn this into a
342 // 64-bit FILD followed by conditional FADD for other targets.
343 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
344 // We have an algorithm for SSE2, and we turn this into a 64-bit
345 // FILD for other targets.
346 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
347 }
349 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
350 // this operation.
351 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
352 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
354 if (!TM.Options.UseSoftFloat) {
355 // SSE has no i16 to fp conversion, only i32
356 if (X86ScalarSSEf32) {
357 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
358 // f32 and f64 cases are Legal, f80 case is not
359 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
360 } else {
361 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
362 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
363 }
364 } else {
365 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
366 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
367 }
369 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
370 // are Legal, f80 is custom lowered.
371 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
372 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
374 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
375 // this operation.
376 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
377 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
379 if (X86ScalarSSEf32) {
380 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
381 // f32 and f64 cases are Legal, f80 case is not
382 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
383 } else {
384 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
385 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
386 }
388 // Handle FP_TO_UINT by promoting the destination to a larger signed
389 // conversion.
390 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
391 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
392 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
394 if (Subtarget->is64Bit()) {
395 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
396 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
397 } else if (!TM.Options.UseSoftFloat) {
398 // Since AVX is a superset of SSE3, only check for SSE here.
399 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
400 // Expand FP_TO_UINT into a select.
401 // FIXME: We would like to use a Custom expander here eventually to do
402 // the optimal thing for SSE vs. the default expansion in the legalizer.
403 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
404 else
405 // With SSE3 we can use fisttpll to convert to a signed i64; without
406 // SSE, we're stuck with a fistpll.
407 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
408 }
410 if (isTargetFTOL()) {
411 // Use the _ftol2 runtime function, which has a pseudo-instruction
412 // to handle its weird calling convention.
413 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
414 }
416 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
417 if (!X86ScalarSSEf64) {
418 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
419 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
420 if (Subtarget->is64Bit()) {
421 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
422 // Without SSE, i64->f64 goes through memory.
423 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
424 }
425 }
427 // Scalar integer divide and remainder are lowered to use operations that
428 // produce two results, to match the available instructions. This exposes
429 // the two-result form to trivial CSE, which is able to combine x/y and x%y
430 // into a single instruction.
431 //
432 // Scalar integer multiply-high is also lowered to use two-result
433 // operations, to match the available instructions. However, plain multiply
434 // (low) operations are left as Legal, as there are single-result
435 // instructions for this in x86. Using the two-result multiply instructions
436 // when both high and low results are needed must be arranged by dagcombine.
437 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
438 MVT VT = IntVTs[i];
439 setOperationAction(ISD::MULHS, VT, Expand);
440 setOperationAction(ISD::MULHU, VT, Expand);
441 setOperationAction(ISD::SDIV, VT, Expand);
442 setOperationAction(ISD::UDIV, VT, Expand);
443 setOperationAction(ISD::SREM, VT, Expand);
444 setOperationAction(ISD::UREM, VT, Expand);
446 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
447 setOperationAction(ISD::ADDC, VT, Custom);
448 setOperationAction(ISD::ADDE, VT, Custom);
449 setOperationAction(ISD::SUBC, VT, Custom);
450 setOperationAction(ISD::SUBE, VT, Custom);
451 }
453 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
454 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
455 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
456 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
457 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
458 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
459 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
460 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
461 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
462 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
463 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
464 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
465 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
466 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
467 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
468 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
469 if (Subtarget->is64Bit())
470 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
471 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
472 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
473 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
474 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
475 setOperationAction(ISD::FREM , MVT::f32 , Expand);
476 setOperationAction(ISD::FREM , MVT::f64 , Expand);
477 setOperationAction(ISD::FREM , MVT::f80 , Expand);
478 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
480 // Promote the i8 variants and force them on up to i32 which has a shorter
481 // encoding.
482 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
483 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
484 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
485 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
486 if (Subtarget->hasBMI()) {
487 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
488 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
489 if (Subtarget->is64Bit())
490 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
491 } else {
492 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
493 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
494 if (Subtarget->is64Bit())
495 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
496 }
498 if (Subtarget->hasLZCNT()) {
499 // When promoting the i8 variants, force them to i32 for a shorter
500 // encoding.
501 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
502 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
503 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
504 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
505 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
506 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
507 if (Subtarget->is64Bit())
508 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
509 } else {
510 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
511 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
512 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
513 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
514 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
515 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
516 if (Subtarget->is64Bit()) {
517 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
518 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
519 }
520 }
522 // Special handling for half-precision floating point conversions.
523 // If we don't have F16C support, then lower half float conversions
524 // into library calls.
525 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
526 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
527 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
528 }
530 // There's never any support for operations beyond MVT::f32.
531 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
532 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
533 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
534 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
536 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
537 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
538 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
539 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
541 if (Subtarget->hasPOPCNT()) {
542 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
543 } else {
544 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
545 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
546 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
547 if (Subtarget->is64Bit())
548 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
549 }
551 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
553 if (!Subtarget->hasMOVBE())
554 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
556 // These should be promoted to a larger select which is supported.
557 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
558 // X86 wants to expand cmov itself.
559 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
560 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
561 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
562 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
563 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
564 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
565 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
566 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
567 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
568 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
569 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
570 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
571 if (Subtarget->is64Bit()) {
572 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
573 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
574 }
575 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
576 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
577 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
578 // support continuation, user-level threading, and etc.. As a result, no
579 // other SjLj exception interfaces are implemented and please don't build
580 // your own exception handling based on them.
581 // LLVM/Clang supports zero-cost DWARF exception handling.
582 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
583 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
585 // Darwin ABI issue.
586 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
587 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
588 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
589 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
590 if (Subtarget->is64Bit())
591 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
592 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
593 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
594 if (Subtarget->is64Bit()) {
595 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
596 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
597 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
598 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
599 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
600 }
601 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
602 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
603 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
604 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
605 if (Subtarget->is64Bit()) {
606 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
607 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
608 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
609 }
611 if (Subtarget->hasSSE1())
612 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
614 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
616 // Expand certain atomics
617 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
618 MVT VT = IntVTs[i];
619 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
620 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
621 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
622 }
624 if (Subtarget->hasCmpxchg16b()) {
625 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
626 }
628 // FIXME - use subtarget debug flags
629 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
630 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
631 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
632 }
634 if (Subtarget->is64Bit()) {
635 setExceptionPointerRegister(X86::RAX);
636 setExceptionSelectorRegister(X86::RDX);
637 } else {
638 setExceptionPointerRegister(X86::EAX);
639 setExceptionSelectorRegister(X86::EDX);
640 }
641 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
642 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
644 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
645 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
647 setOperationAction(ISD::TRAP, MVT::Other, Legal);
648 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
650 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
651 setOperationAction(ISD::VASTART , MVT::Other, Custom);
652 setOperationAction(ISD::VAEND , MVT::Other, Expand);
653 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
654 // TargetInfo::X86_64ABIBuiltinVaList
655 setOperationAction(ISD::VAARG , MVT::Other, Custom);
656 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
657 } else {
658 // TargetInfo::CharPtrBuiltinVaList
659 setOperationAction(ISD::VAARG , MVT::Other, Expand);
660 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
661 }
663 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
664 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
666 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
668 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
669 // f32 and f64 use SSE.
670 // Set up the FP register classes.
671 addRegisterClass(MVT::f32, &X86::FR32RegClass);
672 addRegisterClass(MVT::f64, &X86::FR64RegClass);
674 // Use ANDPD to simulate FABS.
675 setOperationAction(ISD::FABS , MVT::f64, Custom);
676 setOperationAction(ISD::FABS , MVT::f32, Custom);
678 // Use XORP to simulate FNEG.
679 setOperationAction(ISD::FNEG , MVT::f64, Custom);
680 setOperationAction(ISD::FNEG , MVT::f32, Custom);
682 // Use ANDPD and ORPD to simulate FCOPYSIGN.
683 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
684 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
686 // Lower this to FGETSIGNx86 plus an AND.
687 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
688 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
690 // We don't support sin/cos/fmod
691 setOperationAction(ISD::FSIN , MVT::f64, Expand);
692 setOperationAction(ISD::FCOS , MVT::f64, Expand);
693 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
694 setOperationAction(ISD::FSIN , MVT::f32, Expand);
695 setOperationAction(ISD::FCOS , MVT::f32, Expand);
696 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
698 // Expand FP immediates into loads from the stack, except for the special
699 // cases we handle.
700 addLegalFPImmediate(APFloat(+0.0)); // xorpd
701 addLegalFPImmediate(APFloat(+0.0f)); // xorps
702 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
703 // Use SSE for f32, x87 for f64.
704 // Set up the FP register classes.
705 addRegisterClass(MVT::f32, &X86::FR32RegClass);
706 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
708 // Use ANDPS to simulate FABS.
709 setOperationAction(ISD::FABS , MVT::f32, Custom);
711 // Use XORP to simulate FNEG.
712 setOperationAction(ISD::FNEG , MVT::f32, Custom);
714 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
716 // Use ANDPS and ORPS to simulate FCOPYSIGN.
717 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
718 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
720 // We don't support sin/cos/fmod
721 setOperationAction(ISD::FSIN , MVT::f32, Expand);
722 setOperationAction(ISD::FCOS , MVT::f32, Expand);
723 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
725 // Special cases we handle for FP constants.
726 addLegalFPImmediate(APFloat(+0.0f)); // xorps
727 addLegalFPImmediate(APFloat(+0.0)); // FLD0
728 addLegalFPImmediate(APFloat(+1.0)); // FLD1
729 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
730 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
732 if (!TM.Options.UnsafeFPMath) {
733 setOperationAction(ISD::FSIN , MVT::f64, Expand);
734 setOperationAction(ISD::FCOS , MVT::f64, Expand);
735 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
736 }
737 } else if (!TM.Options.UseSoftFloat) {
738 // f32 and f64 in x87.
739 // Set up the FP register classes.
740 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
741 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
743 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
744 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
745 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
746 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
748 if (!TM.Options.UnsafeFPMath) {
749 setOperationAction(ISD::FSIN , MVT::f64, Expand);
750 setOperationAction(ISD::FSIN , MVT::f32, Expand);
751 setOperationAction(ISD::FCOS , MVT::f64, Expand);
752 setOperationAction(ISD::FCOS , MVT::f32, Expand);
753 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
754 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
755 }
756 addLegalFPImmediate(APFloat(+0.0)); // FLD0
757 addLegalFPImmediate(APFloat(+1.0)); // FLD1
758 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
759 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
760 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
761 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
762 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
763 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
764 }
766 // We don't support FMA.
767 setOperationAction(ISD::FMA, MVT::f64, Expand);
768 setOperationAction(ISD::FMA, MVT::f32, Expand);
770 // Long double always uses X87.
771 if (!TM.Options.UseSoftFloat) {
772 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
773 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
774 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
775 {
776 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
777 addLegalFPImmediate(TmpFlt); // FLD0
778 TmpFlt.changeSign();
779 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
781 bool ignored;
782 APFloat TmpFlt2(+1.0);
783 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
784 &ignored);
785 addLegalFPImmediate(TmpFlt2); // FLD1
786 TmpFlt2.changeSign();
787 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
788 }
790 if (!TM.Options.UnsafeFPMath) {
791 setOperationAction(ISD::FSIN , MVT::f80, Expand);
792 setOperationAction(ISD::FCOS , MVT::f80, Expand);
793 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
794 }
796 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
797 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
798 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
799 setOperationAction(ISD::FRINT, MVT::f80, Expand);
800 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
801 setOperationAction(ISD::FMA, MVT::f80, Expand);
802 }
804 // Always use a library call for pow.
805 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
806 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
807 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
809 setOperationAction(ISD::FLOG, MVT::f80, Expand);
810 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
811 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
812 setOperationAction(ISD::FEXP, MVT::f80, Expand);
813 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
815 // First set operation action for all vector types to either promote
816 // (for widening) or expand (for scalarization). Then we will selectively
817 // turn on ones that can be effectively codegen'd.
818 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
819 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
820 MVT VT = (MVT::SimpleValueType)i;
821 setOperationAction(ISD::ADD , VT, Expand);
822 setOperationAction(ISD::SUB , VT, Expand);
823 setOperationAction(ISD::FADD, VT, Expand);
824 setOperationAction(ISD::FNEG, VT, Expand);
825 setOperationAction(ISD::FSUB, VT, Expand);
826 setOperationAction(ISD::MUL , VT, Expand);
827 setOperationAction(ISD::FMUL, VT, Expand);
828 setOperationAction(ISD::SDIV, VT, Expand);
829 setOperationAction(ISD::UDIV, VT, Expand);
830 setOperationAction(ISD::FDIV, VT, Expand);
831 setOperationAction(ISD::SREM, VT, Expand);
832 setOperationAction(ISD::UREM, VT, Expand);
833 setOperationAction(ISD::LOAD, VT, Expand);
834 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
835 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
836 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
837 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
838 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
839 setOperationAction(ISD::FABS, VT, Expand);
840 setOperationAction(ISD::FSIN, VT, Expand);
841 setOperationAction(ISD::FSINCOS, VT, Expand);
842 setOperationAction(ISD::FCOS, VT, Expand);
843 setOperationAction(ISD::FSINCOS, VT, Expand);
844 setOperationAction(ISD::FREM, VT, Expand);
845 setOperationAction(ISD::FMA, VT, Expand);
846 setOperationAction(ISD::FPOWI, VT, Expand);
847 setOperationAction(ISD::FSQRT, VT, Expand);
848 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
849 setOperationAction(ISD::FFLOOR, VT, Expand);
850 setOperationAction(ISD::FCEIL, VT, Expand);
851 setOperationAction(ISD::FTRUNC, VT, Expand);
852 setOperationAction(ISD::FRINT, VT, Expand);
853 setOperationAction(ISD::FNEARBYINT, VT, Expand);
854 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
855 setOperationAction(ISD::MULHS, VT, Expand);
856 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
857 setOperationAction(ISD::MULHU, VT, Expand);
858 setOperationAction(ISD::SDIVREM, VT, Expand);
859 setOperationAction(ISD::UDIVREM, VT, Expand);
860 setOperationAction(ISD::FPOW, VT, Expand);
861 setOperationAction(ISD::CTPOP, VT, Expand);
862 setOperationAction(ISD::CTTZ, VT, Expand);
863 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
864 setOperationAction(ISD::CTLZ, VT, Expand);
865 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
866 setOperationAction(ISD::SHL, VT, Expand);
867 setOperationAction(ISD::SRA, VT, Expand);
868 setOperationAction(ISD::SRL, VT, Expand);
869 setOperationAction(ISD::ROTL, VT, Expand);
870 setOperationAction(ISD::ROTR, VT, Expand);
871 setOperationAction(ISD::BSWAP, VT, Expand);
872 setOperationAction(ISD::SETCC, VT, Expand);
873 setOperationAction(ISD::FLOG, VT, Expand);
874 setOperationAction(ISD::FLOG2, VT, Expand);
875 setOperationAction(ISD::FLOG10, VT, Expand);
876 setOperationAction(ISD::FEXP, VT, Expand);
877 setOperationAction(ISD::FEXP2, VT, Expand);
878 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
879 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
880 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
881 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
882 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
883 setOperationAction(ISD::TRUNCATE, VT, Expand);
884 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
885 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
886 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
887 setOperationAction(ISD::VSELECT, VT, Expand);
888 setOperationAction(ISD::SELECT_CC, VT, Expand);
889 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
890 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
891 setTruncStoreAction(VT,
892 (MVT::SimpleValueType)InnerVT, Expand);
893 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
894 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
896 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
897 // we have to deal with them whether we ask for Expansion or not. Setting
898 // Expand causes its own optimisation problems though, so leave them legal.
899 if (VT.getVectorElementType() == MVT::i1)
900 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
901 }
903 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
904 // with -msoft-float, disable use of MMX as well.
905 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
906 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
907 // No operations on x86mmx supported, everything uses intrinsics.
908 }
910 // MMX-sized vectors (other than x86mmx) are expected to be expanded
911 // into smaller operations.
912 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
913 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
914 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
915 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
916 setOperationAction(ISD::AND, MVT::v8i8, Expand);
917 setOperationAction(ISD::AND, MVT::v4i16, Expand);
918 setOperationAction(ISD::AND, MVT::v2i32, Expand);
919 setOperationAction(ISD::AND, MVT::v1i64, Expand);
920 setOperationAction(ISD::OR, MVT::v8i8, Expand);
921 setOperationAction(ISD::OR, MVT::v4i16, Expand);
922 setOperationAction(ISD::OR, MVT::v2i32, Expand);
923 setOperationAction(ISD::OR, MVT::v1i64, Expand);
924 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
925 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
926 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
927 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
928 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
929 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
930 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
931 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
932 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
933 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
934 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
935 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
936 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
937 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
938 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
939 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
940 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
942 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
943 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
945 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
946 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
947 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
948 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
949 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
950 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
951 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
952 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
953 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
954 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
955 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
956 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
957 }
959 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
960 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
962 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
963 // registers cannot be used even for integer operations.
964 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
965 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
966 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
967 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
969 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
970 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
971 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
972 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
973 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
974 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
975 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
976 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
977 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
978 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
979 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
980 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
981 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
982 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
983 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
984 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
985 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
986 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
987 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
988 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
989 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
990 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
992 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
993 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
994 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
995 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
997 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
998 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
999 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1000 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1001 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1003 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
1004 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1005 MVT VT = (MVT::SimpleValueType)i;
1006 // Do not attempt to custom lower non-power-of-2 vectors
1007 if (!isPowerOf2_32(VT.getVectorNumElements()))
1008 continue;
1009 // Do not attempt to custom lower non-128-bit vectors
1010 if (!VT.is128BitVector())
1011 continue;
1012 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1013 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1014 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1015 }
1017 // We support custom legalizing of sext and anyext loads for specific
1018 // memory vector types which we can load as a scalar (or sequence of
1019 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1020 // loads these must work with a single scalar load.
1021 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1022 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1023 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1024 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1025 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1026 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1027 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1028 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1029 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1031 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1032 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1033 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1034 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1035 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1036 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1038 if (Subtarget->is64Bit()) {
1039 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1040 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1041 }
1043 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1044 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1045 MVT VT = (MVT::SimpleValueType)i;
1047 // Do not attempt to promote non-128-bit vectors
1048 if (!VT.is128BitVector())
1049 continue;
1051 setOperationAction(ISD::AND, VT, Promote);
1052 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1053 setOperationAction(ISD::OR, VT, Promote);
1054 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1055 setOperationAction(ISD::XOR, VT, Promote);
1056 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1057 setOperationAction(ISD::LOAD, VT, Promote);
1058 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1059 setOperationAction(ISD::SELECT, VT, Promote);
1060 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1061 }
1063 // Custom lower v2i64 and v2f64 selects.
1064 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1065 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1066 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1067 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1069 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1070 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1072 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1073 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1074 // As there is no 64-bit GPR available, we need build a special custom
1075 // sequence to convert from v2i32 to v2f32.
1076 if (!Subtarget->is64Bit())
1077 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1079 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1080 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1082 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1084 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1085 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1086 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1087 }
1089 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1090 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1091 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1092 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1093 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1094 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1095 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1096 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1097 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1098 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1099 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1101 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1102 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1103 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1104 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1105 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1106 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1107 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1108 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1109 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1110 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1112 // FIXME: Do we need to handle scalar-to-vector here?
1113 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1115 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1116 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1117 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1118 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1119 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1120 // There is no BLENDI for byte vectors. We don't need to custom lower
1121 // some vselects for now.
1122 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1124 // SSE41 brings specific instructions for doing vector sign extend even in
1125 // cases where we don't have SRA.
1126 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1127 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1128 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1130 // i8 and i16 vectors are custom because the source register and source
1131 // source memory operand types are not the same width. f32 vectors are
1132 // custom since the immediate controlling the insert encodes additional
1133 // information.
1134 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1135 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1136 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1137 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1139 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1140 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1141 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1142 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1144 // FIXME: these should be Legal, but that's only for the case where
1145 // the index is constant. For now custom expand to deal with that.
1146 if (Subtarget->is64Bit()) {
1147 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1148 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1149 }
1150 }
1152 if (Subtarget->hasSSE2()) {
1153 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1154 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1156 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1157 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1159 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1160 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1162 // In the customized shift lowering, the legal cases in AVX2 will be
1163 // recognized.
1164 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1165 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1167 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1168 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1170 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1171 }
1173 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1174 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1175 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1176 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1177 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1178 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1179 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1181 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1182 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1183 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1185 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1186 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1187 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1188 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1189 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1190 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1191 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1192 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1193 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1194 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1195 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1196 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1198 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1199 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1200 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1201 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1202 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1203 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1204 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1205 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1206 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1207 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1208 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1209 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1211 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1212 // even though v8i16 is a legal type.
1213 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1214 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1215 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1217 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1218 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1219 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1221 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1222 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1224 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1226 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1227 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1229 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1230 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1232 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1233 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1235 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1236 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1237 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1238 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1240 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1241 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1242 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1244 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1245 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1246 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1247 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1249 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1250 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1251 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1252 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1253 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1254 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1255 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1256 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1257 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1258 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1259 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1260 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1262 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1263 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1264 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1265 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1266 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1267 setOperationAction(ISD::FMA, MVT::f32, Legal);
1268 setOperationAction(ISD::FMA, MVT::f64, Legal);
1269 }
1271 if (Subtarget->hasInt256()) {
1272 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1273 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1274 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1275 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1277 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1278 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1279 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1280 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1282 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1283 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1284 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1285 // Don't lower v32i8 because there is no 128-bit byte mul
1287 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1288 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1289 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1290 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1292 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1293 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1294 } else {
1295 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1296 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1297 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1298 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1300 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1301 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1302 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1303 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1305 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1306 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1307 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1308 // Don't lower v32i8 because there is no 128-bit byte mul
1309 }
1311 // In the customized shift lowering, the legal cases in AVX2 will be
1312 // recognized.
1313 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1314 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1316 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1317 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1319 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1321 // Custom lower several nodes for 256-bit types.
1322 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1323 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1324 MVT VT = (MVT::SimpleValueType)i;
1326 // Extract subvector is special because the value type
1327 // (result) is 128-bit but the source is 256-bit wide.
1328 if (VT.is128BitVector())
1329 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1331 // Do not attempt to custom lower other non-256-bit vectors
1332 if (!VT.is256BitVector())
1333 continue;
1335 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1336 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1337 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1338 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1339 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1340 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1341 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1342 }
1344 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1345 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1346 MVT VT = (MVT::SimpleValueType)i;
1348 // Do not attempt to promote non-256-bit vectors
1349 if (!VT.is256BitVector())
1350 continue;
1352 setOperationAction(ISD::AND, VT, Promote);
1353 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1354 setOperationAction(ISD::OR, VT, Promote);
1355 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1356 setOperationAction(ISD::XOR, VT, Promote);
1357 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1358 setOperationAction(ISD::LOAD, VT, Promote);
1359 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1360 setOperationAction(ISD::SELECT, VT, Promote);
1361 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1362 }
1363 }
1365 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1366 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1367 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1368 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1369 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1371 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1372 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1373 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1375 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1376 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1377 setOperationAction(ISD::XOR, MVT::i1, Legal);
1378 setOperationAction(ISD::OR, MVT::i1, Legal);
1379 setOperationAction(ISD::AND, MVT::i1, Legal);
1380 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1381 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1382 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1383 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1384 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1385 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1387 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1388 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1389 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1390 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1391 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1392 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1394 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1395 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1396 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1397 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1398 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1399 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1400 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1401 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1403 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1404 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1405 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1406 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1407 if (Subtarget->is64Bit()) {
1408 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1409 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1410 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1411 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1412 }
1413 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1414 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1415 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1416 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1417 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1418 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1419 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1420 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1421 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1422 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1424 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1425 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1426 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1427 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1428 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1429 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1430 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1431 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1432 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1433 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1434 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1438 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1439 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1440 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1441 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1442 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1443 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1445 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1446 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1448 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1450 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1451 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1452 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1453 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1454 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1455 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1456 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1457 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1458 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1460 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1461 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1463 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1464 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1466 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1468 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1469 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1471 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1472 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1474 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1475 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1477 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1478 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1479 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1480 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1481 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1482 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1484 if (Subtarget->hasCDI()) {
1485 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1486 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1487 }
1489 // Custom lower several nodes.
1490 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1491 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1492 MVT VT = (MVT::SimpleValueType)i;
1494 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1495 // Extract subvector is special because the value type
1496 // (result) is 256/128-bit but the source is 512-bit wide.
1497 if (VT.is128BitVector() || VT.is256BitVector())
1498 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1500 if (VT.getVectorElementType() == MVT::i1)
1501 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1503 // Do not attempt to custom lower other non-512-bit vectors
1504 if (!VT.is512BitVector())
1505 continue;
1507 if ( EltSize >= 32) {
1508 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1509 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1510 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1511 setOperationAction(ISD::VSELECT, VT, Legal);
1512 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1513 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1514 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1515 }
1516 }
1517 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1518 MVT VT = (MVT::SimpleValueType)i;
1520 // Do not attempt to promote non-256-bit vectors
1521 if (!VT.is512BitVector())
1522 continue;
1524 setOperationAction(ISD::SELECT, VT, Promote);
1525 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1526 }
1527 }// has AVX-512
1529 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1530 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1531 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1533 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1534 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1536 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1537 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1538 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1539 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1541 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1542 const MVT VT = (MVT::SimpleValueType)i;
1544 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1546 // Do not attempt to promote non-256-bit vectors
1547 if (!VT.is512BitVector())
1548 continue;
1550 if ( EltSize < 32) {
1551 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1552 setOperationAction(ISD::VSELECT, VT, Legal);
1553 }
1554 }
1555 }
1557 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1558 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1559 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1561 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1562 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1563 }
1565 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1566 // of this type with custom code.
1567 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1568 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1569 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1570 Custom);
1571 }
1573 // We want to custom lower some of our intrinsics.
1574 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1575 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1576 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1577 if (!Subtarget->is64Bit())
1578 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1580 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1581 // handle type legalization for these operations here.
1582 //
1583 // FIXME: We really should do custom legalization for addition and
1584 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1585 // than generic legalization for 64-bit multiplication-with-overflow, though.
1586 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1587 // Add/Sub/Mul with overflow operations are custom lowered.
1588 MVT VT = IntVTs[i];
1589 setOperationAction(ISD::SADDO, VT, Custom);
1590 setOperationAction(ISD::UADDO, VT, Custom);
1591 setOperationAction(ISD::SSUBO, VT, Custom);
1592 setOperationAction(ISD::USUBO, VT, Custom);
1593 setOperationAction(ISD::SMULO, VT, Custom);
1594 setOperationAction(ISD::UMULO, VT, Custom);
1595 }
1597 // There are no 8-bit 3-address imul/mul instructions
1598 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1599 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1601 if (!Subtarget->is64Bit()) {
1602 // These libcalls are not available in 32-bit.
1603 setLibcallName(RTLIB::SHL_I128, nullptr);
1604 setLibcallName(RTLIB::SRL_I128, nullptr);
1605 setLibcallName(RTLIB::SRA_I128, nullptr);
1606 }
1608 // Combine sin / cos into one node or libcall if possible.
1609 if (Subtarget->hasSinCos()) {
1610 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1611 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1612 if (Subtarget->isTargetDarwin()) {
1613 // For MacOSX, we don't want to the normal expansion of a libcall to
1614 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1615 // traffic.
1616 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1617 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1618 }
1619 }
1621 if (Subtarget->isTargetWin64()) {
1622 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1623 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1624 setOperationAction(ISD::SREM, MVT::i128, Custom);
1625 setOperationAction(ISD::UREM, MVT::i128, Custom);
1626 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1627 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1628 }
1630 // We have target-specific dag combine patterns for the following nodes:
1631 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1632 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1633 setTargetDAGCombine(ISD::VSELECT);
1634 setTargetDAGCombine(ISD::SELECT);
1635 setTargetDAGCombine(ISD::SHL);
1636 setTargetDAGCombine(ISD::SRA);
1637 setTargetDAGCombine(ISD::SRL);
1638 setTargetDAGCombine(ISD::OR);
1639 setTargetDAGCombine(ISD::AND);
1640 setTargetDAGCombine(ISD::ADD);
1641 setTargetDAGCombine(ISD::FADD);
1642 setTargetDAGCombine(ISD::FSUB);
1643 setTargetDAGCombine(ISD::FMA);
1644 setTargetDAGCombine(ISD::SUB);
1645 setTargetDAGCombine(ISD::LOAD);
1646 setTargetDAGCombine(ISD::STORE);
1647 setTargetDAGCombine(ISD::ZERO_EXTEND);
1648 setTargetDAGCombine(ISD::ANY_EXTEND);
1649 setTargetDAGCombine(ISD::SIGN_EXTEND);
1650 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1651 setTargetDAGCombine(ISD::TRUNCATE);
1652 setTargetDAGCombine(ISD::SINT_TO_FP);
1653 setTargetDAGCombine(ISD::SETCC);
1654 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1655 setTargetDAGCombine(ISD::BUILD_VECTOR);
1656 if (Subtarget->is64Bit())
1657 setTargetDAGCombine(ISD::MUL);
1658 setTargetDAGCombine(ISD::XOR);
1660 computeRegisterProperties();
1662 // On Darwin, -Os means optimize for size without hurting performance,
1663 // do not reduce the limit.
1664 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1665 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1666 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1667 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1668 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1669 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1670 setPrefLoopAlignment(4); // 2^4 bytes.
1672 // Predictable cmov don't hurt on atom because it's in-order.
1673 PredictableSelectIsExpensive = !Subtarget->isAtom();
1675 setPrefFunctionAlignment(4); // 2^4 bytes.
1677 verifyIntrinsicTables();
1678 }
1680 // This has so far only been implemented for 64-bit MachO.
1681 bool X86TargetLowering::useLoadStackGuardNode() const {
1682 return Subtarget->getTargetTriple().getObjectFormat() == Triple::MachO &&
1683 Subtarget->is64Bit();
1684 }
1686 TargetLoweringBase::LegalizeTypeAction
1687 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1688 if (ExperimentalVectorWideningLegalization &&
1689 VT.getVectorNumElements() != 1 &&
1690 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1691 return TypeWidenVector;
1693 return TargetLoweringBase::getPreferredVectorAction(VT);
1694 }
1696 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1697 if (!VT.isVector())
1698 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1700 const unsigned NumElts = VT.getVectorNumElements();
1701 const EVT EltVT = VT.getVectorElementType();
1702 if (VT.is512BitVector()) {
1703 if (Subtarget->hasAVX512())
1704 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1705 EltVT == MVT::f32 || EltVT == MVT::f64)
1706 switch(NumElts) {
1707 case 8: return MVT::v8i1;
1708 case 16: return MVT::v16i1;
1709 }
1710 if (Subtarget->hasBWI())
1711 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1712 switch(NumElts) {
1713 case 32: return MVT::v32i1;
1714 case 64: return MVT::v64i1;
1715 }
1716 }
1718 if (VT.is256BitVector() || VT.is128BitVector()) {
1719 if (Subtarget->hasVLX())
1720 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1721 EltVT == MVT::f32 || EltVT == MVT::f64)
1722 switch(NumElts) {
1723 case 2: return MVT::v2i1;
1724 case 4: return MVT::v4i1;
1725 case 8: return MVT::v8i1;
1726 }
1727 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1728 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1729 switch(NumElts) {
1730 case 8: return MVT::v8i1;
1731 case 16: return MVT::v16i1;
1732 case 32: return MVT::v32i1;
1733 }
1734 }
1736 return VT.changeVectorElementTypeToInteger();
1737 }
1739 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1740 /// the desired ByVal argument alignment.
1741 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1742 if (MaxAlign == 16)
1743 return;
1744 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1745 if (VTy->getBitWidth() == 128)
1746 MaxAlign = 16;
1747 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1748 unsigned EltAlign = 0;
1749 getMaxByValAlign(ATy->getElementType(), EltAlign);
1750 if (EltAlign > MaxAlign)
1751 MaxAlign = EltAlign;
1752 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1753 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1754 unsigned EltAlign = 0;
1755 getMaxByValAlign(STy->getElementType(i), EltAlign);
1756 if (EltAlign > MaxAlign)
1757 MaxAlign = EltAlign;
1758 if (MaxAlign == 16)
1759 break;
1760 }
1761 }
1762 }
1764 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1765 /// function arguments in the caller parameter area. For X86, aggregates
1766 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1767 /// are at 4-byte boundaries.
1768 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1769 if (Subtarget->is64Bit()) {
1770 // Max of 8 and alignment of type.
1771 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1772 if (TyAlign > 8)
1773 return TyAlign;
1774 return 8;
1775 }
1777 unsigned Align = 4;
1778 if (Subtarget->hasSSE1())
1779 getMaxByValAlign(Ty, Align);
1780 return Align;
1781 }
1783 /// getOptimalMemOpType - Returns the target specific optimal type for load
1784 /// and store operations as a result of memset, memcpy, and memmove
1785 /// lowering. If DstAlign is zero that means it's safe to destination
1786 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1787 /// means there isn't a need to check it against alignment requirement,
1788 /// probably because the source does not need to be loaded. If 'IsMemset' is
1789 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1790 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1791 /// source is constant so it does not need to be loaded.
1792 /// It returns EVT::Other if the type should be determined using generic
1793 /// target-independent logic.
1794 EVT
1795 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1796 unsigned DstAlign, unsigned SrcAlign,
1797 bool IsMemset, bool ZeroMemset,
1798 bool MemcpyStrSrc,
1799 MachineFunction &MF) const {
1800 const Function *F = MF.getFunction();
1801 if ((!IsMemset || ZeroMemset) &&
1802 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1803 Attribute::NoImplicitFloat)) {
1804 if (Size >= 16 &&
1805 (Subtarget->isUnalignedMemAccessFast() ||
1806 ((DstAlign == 0 || DstAlign >= 16) &&
1807 (SrcAlign == 0 || SrcAlign >= 16)))) {
1808 if (Size >= 32) {
1809 if (Subtarget->hasInt256())
1810 return MVT::v8i32;
1811 if (Subtarget->hasFp256())
1812 return MVT::v8f32;
1813 }
1814 if (Subtarget->hasSSE2())
1815 return MVT::v4i32;
1816 if (Subtarget->hasSSE1())
1817 return MVT::v4f32;
1818 } else if (!MemcpyStrSrc && Size >= 8 &&
1819 !Subtarget->is64Bit() &&
1820 Subtarget->hasSSE2()) {
1821 // Do not use f64 to lower memcpy if source is string constant. It's
1822 // better to use i32 to avoid the loads.
1823 return MVT::f64;
1824 }
1825 }
1826 if (Subtarget->is64Bit() && Size >= 8)
1827 return MVT::i64;
1828 return MVT::i32;
1829 }
1831 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1832 if (VT == MVT::f32)
1833 return X86ScalarSSEf32;
1834 else if (VT == MVT::f64)
1835 return X86ScalarSSEf64;
1836 return true;
1837 }
1839 bool
1840 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1841 unsigned,
1842 unsigned,
1843 bool *Fast) const {
1844 if (Fast)
1845 *Fast = Subtarget->isUnalignedMemAccessFast();
1846 return true;
1847 }
1849 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1850 /// current function. The returned value is a member of the
1851 /// MachineJumpTableInfo::JTEntryKind enum.
1852 unsigned X86TargetLowering::getJumpTableEncoding() const {
1853 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1854 // symbol.
1855 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1856 Subtarget->isPICStyleGOT())
1857 return MachineJumpTableInfo::EK_Custom32;
1859 // Otherwise, use the normal jump table encoding heuristics.
1860 return TargetLowering::getJumpTableEncoding();
1861 }
1863 const MCExpr *
1864 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1865 const MachineBasicBlock *MBB,
1866 unsigned uid,MCContext &Ctx) const{
1867 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1868 Subtarget->isPICStyleGOT());
1869 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1870 // entries.
1871 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1872 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1873 }
1875 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1876 /// jumptable.
1877 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1878 SelectionDAG &DAG) const {
1879 if (!Subtarget->is64Bit())
1880 // This doesn't have SDLoc associated with it, but is not really the
1881 // same as a Register.
1882 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1883 return Table;
1884 }
1886 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1887 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1888 /// MCExpr.
1889 const MCExpr *X86TargetLowering::
1890 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1891 MCContext &Ctx) const {
1892 // X86-64 uses RIP relative addressing based on the jump table label.
1893 if (Subtarget->isPICStyleRIPRel())
1894 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1896 // Otherwise, the reference is relative to the PIC base.
1897 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1898 }
1900 // FIXME: Why this routine is here? Move to RegInfo!
1901 std::pair<const TargetRegisterClass*, uint8_t>
1902 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1903 const TargetRegisterClass *RRC = nullptr;
1904 uint8_t Cost = 1;
1905 switch (VT.SimpleTy) {
1906 default:
1907 return TargetLowering::findRepresentativeClass(VT);
1908 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1909 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1910 break;
1911 case MVT::x86mmx:
1912 RRC = &X86::VR64RegClass;
1913 break;
1914 case MVT::f32: case MVT::f64:
1915 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1916 case MVT::v4f32: case MVT::v2f64:
1917 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1918 case MVT::v4f64:
1919 RRC = &X86::VR128RegClass;
1920 break;
1921 }
1922 return std::make_pair(RRC, Cost);
1923 }
1925 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1926 unsigned &Offset) const {
1927 if (!Subtarget->isTargetLinux())
1928 return false;
1930 if (Subtarget->is64Bit()) {
1931 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1932 Offset = 0x28;
1933 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1934 AddressSpace = 256;
1935 else
1936 AddressSpace = 257;
1937 } else {
1938 // %gs:0x14 on i386
1939 Offset = 0x14;
1940 AddressSpace = 256;
1941 }
1942 return true;
1943 }
1945 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1946 unsigned DestAS) const {
1947 assert(SrcAS != DestAS && "Expected different address spaces!");
1949 return SrcAS < 256 && DestAS < 256;
1950 }
1952 //===----------------------------------------------------------------------===//
1953 // Return Value Calling Convention Implementation
1954 //===----------------------------------------------------------------------===//
1956 #include "X86GenCallingConv.inc"
1958 bool
1959 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1960 MachineFunction &MF, bool isVarArg,
1961 const SmallVectorImpl<ISD::OutputArg> &Outs,
1962 LLVMContext &Context) const {
1963 SmallVector<CCValAssign, 16> RVLocs;
1964 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1965 return CCInfo.CheckReturn(Outs, RetCC_X86);
1966 }
1968 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1969 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1970 return ScratchRegs;
1971 }
1973 SDValue
1974 X86TargetLowering::LowerReturn(SDValue Chain,
1975 CallingConv::ID CallConv, bool isVarArg,
1976 const SmallVectorImpl<ISD::OutputArg> &Outs,
1977 const SmallVectorImpl<SDValue> &OutVals,
1978 SDLoc dl, SelectionDAG &DAG) const {
1979 MachineFunction &MF = DAG.getMachineFunction();
1980 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1982 SmallVector<CCValAssign, 16> RVLocs;
1983 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1984 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1986 SDValue Flag;
1987 SmallVector<SDValue, 6> RetOps;
1988 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1989 // Operand #1 = Bytes To Pop
1990 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1991 MVT::i16));
1993 // Copy the result values into the output registers.
1994 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1995 CCValAssign &VA = RVLocs[i];
1996 assert(VA.isRegLoc() && "Can only return in registers!");
1997 SDValue ValToCopy = OutVals[i];
1998 EVT ValVT = ValToCopy.getValueType();
2000 // Promote values to the appropriate types
2001 if (VA.getLocInfo() == CCValAssign::SExt)
2002 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2003 else if (VA.getLocInfo() == CCValAssign::ZExt)
2004 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2005 else if (VA.getLocInfo() == CCValAssign::AExt)
2006 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2007 else if (VA.getLocInfo() == CCValAssign::BCvt)
2008 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2010 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2011 "Unexpected FP-extend for return value.");
2013 // If this is x86-64, and we disabled SSE, we can't return FP values,
2014 // or SSE or MMX vectors.
2015 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2016 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2017 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2018 report_fatal_error("SSE register return with SSE disabled");
2019 }
2020 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2021 // llvm-gcc has never done it right and no one has noticed, so this
2022 // should be OK for now.
2023 if (ValVT == MVT::f64 &&
2024 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2025 report_fatal_error("SSE2 register return with SSE2 disabled");
2027 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2028 // the RET instruction and handled by the FP Stackifier.
2029 if (VA.getLocReg() == X86::FP0 ||
2030 VA.getLocReg() == X86::FP1) {
2031 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2032 // change the value to the FP stack register class.
2033 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2034 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2035 RetOps.push_back(ValToCopy);
2036 // Don't emit a copytoreg.
2037 continue;
2038 }
2040 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2041 // which is returned in RAX / RDX.
2042 if (Subtarget->is64Bit()) {
2043 if (ValVT == MVT::x86mmx) {
2044 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2045 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2046 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2047 ValToCopy);
2048 // If we don't have SSE2 available, convert to v4f32 so the generated
2049 // register is legal.
2050 if (!Subtarget->hasSSE2())
2051 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2052 }
2053 }
2054 }
2056 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2057 Flag = Chain.getValue(1);
2058 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2059 }
2061 // The x86-64 ABIs require that for returning structs by value we copy
2062 // the sret argument into %rax/%eax (depending on ABI) for the return.
2063 // Win32 requires us to put the sret argument to %eax as well.
2064 // We saved the argument into a virtual register in the entry block,
2065 // so now we copy the value out and into %rax/%eax.
2066 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2067 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2068 MachineFunction &MF = DAG.getMachineFunction();
2069 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2070 unsigned Reg = FuncInfo->getSRetReturnReg();
2071 assert(Reg &&
2072 "SRetReturnReg should have been set in LowerFormalArguments().");
2073 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2075 unsigned RetValReg
2076 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2077 X86::RAX : X86::EAX;
2078 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2079 Flag = Chain.getValue(1);
2081 // RAX/EAX now acts like a return value.
2082 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2083 }
2085 RetOps[0] = Chain; // Update chain.
2087 // Add the flag if we have it.
2088 if (Flag.getNode())
2089 RetOps.push_back(Flag);
2091 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2092 }
2094 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2095 if (N->getNumValues() != 1)
2096 return false;
2097 if (!N->hasNUsesOfValue(1, 0))
2098 return false;
2100 SDValue TCChain = Chain;
2101 SDNode *Copy = *N->use_begin();
2102 if (Copy->getOpcode() == ISD::CopyToReg) {
2103 // If the copy has a glue operand, we conservatively assume it isn't safe to
2104 // perform a tail call.
2105 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2106 return false;
2107 TCChain = Copy->getOperand(0);
2108 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2109 return false;
2111 bool HasRet = false;
2112 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2113 UI != UE; ++UI) {
2114 if (UI->getOpcode() != X86ISD::RET_FLAG)
2115 return false;
2116 // If we are returning more than one value, we can definitely
2117 // not make a tail call see PR19530
2118 if (UI->getNumOperands() > 4)
2119 return false;
2120 if (UI->getNumOperands() == 4 &&
2121 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2122 return false;
2123 HasRet = true;
2124 }
2126 if (!HasRet)
2127 return false;
2129 Chain = TCChain;
2130 return true;
2131 }
2133 EVT
2134 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2135 ISD::NodeType ExtendKind) const {
2136 MVT ReturnMVT;
2137 // TODO: Is this also valid on 32-bit?
2138 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2139 ReturnMVT = MVT::i8;
2140 else
2141 ReturnMVT = MVT::i32;
2143 EVT MinVT = getRegisterType(Context, ReturnMVT);
2144 return VT.bitsLT(MinVT) ? MinVT : VT;
2145 }
2147 /// LowerCallResult - Lower the result values of a call into the
2148 /// appropriate copies out of appropriate physical registers.
2149 ///
2150 SDValue
2151 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2152 CallingConv::ID CallConv, bool isVarArg,
2153 const SmallVectorImpl<ISD::InputArg> &Ins,
2154 SDLoc dl, SelectionDAG &DAG,
2155 SmallVectorImpl<SDValue> &InVals) const {
2157 // Assign locations to each value returned by this call.
2158 SmallVector<CCValAssign, 16> RVLocs;
2159 bool Is64Bit = Subtarget->is64Bit();
2160 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2161 *DAG.getContext());
2162 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2164 // Copy all of the result registers out of their specified physreg.
2165 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2166 CCValAssign &VA = RVLocs[i];
2167 EVT CopyVT = VA.getValVT();
2169 // If this is x86-64, and we disabled SSE, we can't return FP values
2170 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2171 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2172 report_fatal_error("SSE register return with SSE disabled");
2173 }
2175 // If we prefer to use the value in xmm registers, copy it out as f80 and
2176 // use a truncate to move it from fp stack reg to xmm reg.
2177 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2178 isScalarFPTypeInSSEReg(VA.getValVT()))
2179 CopyVT = MVT::f80;
2181 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2182 CopyVT, InFlag).getValue(1);
2183 SDValue Val = Chain.getValue(0);
2185 if (CopyVT != VA.getValVT())
2186 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2187 // This truncation won't change the value.
2188 DAG.getIntPtrConstant(1));
2190 InFlag = Chain.getValue(2);
2191 InVals.push_back(Val);
2192 }
2194 return Chain;
2195 }
2197 //===----------------------------------------------------------------------===//
2198 // C & StdCall & Fast Calling Convention implementation
2199 //===----------------------------------------------------------------------===//
2200 // StdCall calling convention seems to be standard for many Windows' API
2201 // routines and around. It differs from C calling convention just a little:
2202 // callee should clean up the stack, not caller. Symbols should be also
2203 // decorated in some fancy way :) It doesn't support any vector arguments.
2204 // For info on fast calling convention see Fast Calling Convention (tail call)
2205 // implementation LowerX86_32FastCCCallTo.
2207 /// CallIsStructReturn - Determines whether a call uses struct return
2208 /// semantics.
2209 enum StructReturnType {
2210 NotStructReturn,
2211 RegStructReturn,
2212 StackStructReturn
2213 };
2214 static StructReturnType
2215 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2216 if (Outs.empty())
2217 return NotStructReturn;
2219 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2220 if (!Flags.isSRet())
2221 return NotStructReturn;
2222 if (Flags.isInReg())
2223 return RegStructReturn;
2224 return StackStructReturn;
2225 }
2227 /// ArgsAreStructReturn - Determines whether a function uses struct
2228 /// return semantics.
2229 static StructReturnType
2230 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2231 if (Ins.empty())
2232 return NotStructReturn;
2234 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2235 if (!Flags.isSRet())
2236 return NotStructReturn;
2237 if (Flags.isInReg())
2238 return RegStructReturn;
2239 return StackStructReturn;
2240 }
2242 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2243 /// by "Src" to address "Dst" with size and alignment information specified by
2244 /// the specific parameter attribute. The copy will be passed as a byval
2245 /// function parameter.
2246 static SDValue
2247 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2248 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2249 SDLoc dl) {
2250 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2252 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2253 /*isVolatile*/false, /*AlwaysInline=*/true,
2254 MachinePointerInfo(), MachinePointerInfo());
2255 }
2257 /// IsTailCallConvention - Return true if the calling convention is one that
2258 /// supports tail call optimization.
2259 static bool IsTailCallConvention(CallingConv::ID CC) {
2260 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2261 CC == CallingConv::HiPE);
2262 }
2264 /// \brief Return true if the calling convention is a C calling convention.
2265 static bool IsCCallConvention(CallingConv::ID CC) {
2266 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2267 CC == CallingConv::X86_64_SysV);
2268 }
2270 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2271 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2272 return false;
2274 CallSite CS(CI);
2275 CallingConv::ID CalleeCC = CS.getCallingConv();
2276 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2277 return false;
2279 return true;
2280 }
2282 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2283 /// a tailcall target by changing its ABI.
2284 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2285 bool GuaranteedTailCallOpt) {
2286 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2287 }
2289 SDValue
2290 X86TargetLowering::LowerMemArgument(SDValue Chain,
2291 CallingConv::ID CallConv,
2292 const SmallVectorImpl<ISD::InputArg> &Ins,
2293 SDLoc dl, SelectionDAG &DAG,
2294 const CCValAssign &VA,
2295 MachineFrameInfo *MFI,
2296 unsigned i) const {
2297 // Create the nodes corresponding to a load from this parameter slot.
2298 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2299 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2300 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2301 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2302 EVT ValVT;
2304 // If value is passed by pointer we have address passed instead of the value
2305 // itself.
2306 if (VA.getLocInfo() == CCValAssign::Indirect)
2307 ValVT = VA.getLocVT();
2308 else
2309 ValVT = VA.getValVT();
2311 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2312 // changed with more analysis.
2313 // In case of tail call optimization mark all arguments mutable. Since they
2314 // could be overwritten by lowering of arguments in case of a tail call.
2315 if (Flags.isByVal()) {
2316 unsigned Bytes = Flags.getByValSize();
2317 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2318 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2319 return DAG.getFrameIndex(FI, getPointerTy());
2320 } else {
2321 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2322 VA.getLocMemOffset(), isImmutable);
2323 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2324 return DAG.getLoad(ValVT, dl, Chain, FIN,
2325 MachinePointerInfo::getFixedStack(FI),
2326 false, false, false, 0);
2327 }
2328 }
2330 // FIXME: Get this from tablegen.
2331 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2332 const X86Subtarget *Subtarget) {
2333 assert(Subtarget->is64Bit());
2335 if (Subtarget->isCallingConvWin64(CallConv)) {
2336 static const MCPhysReg GPR64ArgRegsWin64[] = {
2337 X86::RCX, X86::RDX, X86::R8, X86::R9
2338 };
2339 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2340 }
2342 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2343 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2344 };
2345 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2346 }
2348 // FIXME: Get this from tablegen.
2349 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2350 CallingConv::ID CallConv,
2351 const X86Subtarget *Subtarget) {
2352 assert(Subtarget->is64Bit());
2353 if (Subtarget->isCallingConvWin64(CallConv)) {
2354 // The XMM registers which might contain var arg parameters are shadowed
2355 // in their paired GPR. So we only need to save the GPR to their home
2356 // slots.
2357 // TODO: __vectorcall will change this.
2358 return None;
2359 }
2361 const Function *Fn = MF.getFunction();
2362 bool NoImplicitFloatOps = Fn->getAttributes().
2363 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2364 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2365 "SSE register cannot be used when SSE is disabled!");
2366 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2367 !Subtarget->hasSSE1())
2368 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2369 // registers.
2370 return None;
2372 static const MCPhysReg XMMArgRegs64Bit[] = {
2373 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2374 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2375 };
2376 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2377 }
2379 SDValue
2380 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2381 CallingConv::ID CallConv,
2382 bool isVarArg,
2383 const SmallVectorImpl<ISD::InputArg> &Ins,
2384 SDLoc dl,
2385 SelectionDAG &DAG,
2386 SmallVectorImpl<SDValue> &InVals)
2387 const {
2388 MachineFunction &MF = DAG.getMachineFunction();
2389 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2391 const Function* Fn = MF.getFunction();
2392 if (Fn->hasExternalLinkage() &&
2393 Subtarget->isTargetCygMing() &&
2394 Fn->getName() == "main")
2395 FuncInfo->setForceFramePointer(true);
2397 MachineFrameInfo *MFI = MF.getFrameInfo();
2398 bool Is64Bit = Subtarget->is64Bit();
2399 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2401 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2402 "Var args not supported with calling convention fastcc, ghc or hipe");
2404 // Assign locations to all of the incoming arguments.
2405 SmallVector<CCValAssign, 16> ArgLocs;
2406 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2408 // Allocate shadow area for Win64
2409 if (IsWin64)
2410 CCInfo.AllocateStack(32, 8);
2412 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2414 unsigned LastVal = ~0U;
2415 SDValue ArgValue;
2416 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2417 CCValAssign &VA = ArgLocs[i];
2418 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2419 // places.
2420 assert(VA.getValNo() != LastVal &&
2421 "Don't support value assigned to multiple locs yet");
2422 (void)LastVal;
2423 LastVal = VA.getValNo();
2425 if (VA.isRegLoc()) {
2426 EVT RegVT = VA.getLocVT();
2427 const TargetRegisterClass *RC;
2428 if (RegVT == MVT::i32)
2429 RC = &X86::GR32RegClass;
2430 else if (Is64Bit && RegVT == MVT::i64)
2431 RC = &X86::GR64RegClass;
2432 else if (RegVT == MVT::f32)
2433 RC = &X86::FR32RegClass;
2434 else if (RegVT == MVT::f64)
2435 RC = &X86::FR64RegClass;
2436 else if (RegVT.is512BitVector())
2437 RC = &X86::VR512RegClass;
2438 else if (RegVT.is256BitVector())
2439 RC = &X86::VR256RegClass;
2440 else if (RegVT.is128BitVector())
2441 RC = &X86::VR128RegClass;
2442 else if (RegVT == MVT::x86mmx)
2443 RC = &X86::VR64RegClass;
2444 else if (RegVT == MVT::i1)
2445 RC = &X86::VK1RegClass;
2446 else if (RegVT == MVT::v8i1)
2447 RC = &X86::VK8RegClass;
2448 else if (RegVT == MVT::v16i1)
2449 RC = &X86::VK16RegClass;
2450 else if (RegVT == MVT::v32i1)
2451 RC = &X86::VK32RegClass;
2452 else if (RegVT == MVT::v64i1)
2453 RC = &X86::VK64RegClass;
2454 else
2455 llvm_unreachable("Unknown argument type!");
2457 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2458 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2460 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2461 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2462 // right size.
2463 if (VA.getLocInfo() == CCValAssign::SExt)
2464 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2465 DAG.getValueType(VA.getValVT()));
2466 else if (VA.getLocInfo() == CCValAssign::ZExt)
2467 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2468 DAG.getValueType(VA.getValVT()));
2469 else if (VA.getLocInfo() == CCValAssign::BCvt)
2470 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2472 if (VA.isExtInLoc()) {
2473 // Handle MMX values passed in XMM regs.
2474 if (RegVT.isVector())
2475 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2476 else
2477 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2478 }
2479 } else {
2480 assert(VA.isMemLoc());
2481 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2482 }
2484 // If value is passed via pointer - do a load.
2485 if (VA.getLocInfo() == CCValAssign::Indirect)
2486 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2487 MachinePointerInfo(), false, false, false, 0);
2489 InVals.push_back(ArgValue);
2490 }
2492 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2493 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2494 // The x86-64 ABIs require that for returning structs by value we copy
2495 // the sret argument into %rax/%eax (depending on ABI) for the return.
2496 // Win32 requires us to put the sret argument to %eax as well.
2497 // Save the argument into a virtual register so that we can access it
2498 // from the return points.
2499 if (Ins[i].Flags.isSRet()) {
2500 unsigned Reg = FuncInfo->getSRetReturnReg();
2501 if (!Reg) {
2502 MVT PtrTy = getPointerTy();
2503 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2504 FuncInfo->setSRetReturnReg(Reg);
2505 }
2506 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2507 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2508 break;
2509 }
2510 }
2511 }
2513 unsigned StackSize = CCInfo.getNextStackOffset();
2514 // Align stack specially for tail calls.
2515 if (FuncIsMadeTailCallSafe(CallConv,
2516 MF.getTarget().Options.GuaranteedTailCallOpt))
2517 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2519 // If the function takes variable number of arguments, make a frame index for
2520 // the start of the first vararg value... for expansion of llvm.va_start. We
2521 // can skip this if there are no va_start calls.
2522 if (MFI->hasVAStart() &&
2523 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2524 CallConv != CallingConv::X86_ThisCall))) {
2525 FuncInfo->setVarArgsFrameIndex(
2526 MFI->CreateFixedObject(1, StackSize, true));
2527 }
2529 // 64-bit calling conventions support varargs and register parameters, so we
2530 // have to do extra work to spill them in the prologue or forward them to
2531 // musttail calls.
2532 if (Is64Bit && isVarArg &&
2533 (MFI->hasVAStart() || MFI->hasMustTailInVarArgFunc())) {
2534 // Find the first unallocated argument registers.
2535 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2536 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2537 unsigned NumIntRegs =
2538 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2539 unsigned NumXMMRegs =
2540 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2541 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2542 "SSE register cannot be used when SSE is disabled!");
2544 // Gather all the live in physical registers.
2545 SmallVector<SDValue, 6> LiveGPRs;
2546 SmallVector<SDValue, 8> LiveXMMRegs;
2547 SDValue ALVal;
2548 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2549 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2550 LiveGPRs.push_back(
2551 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2552 }
2553 if (!ArgXMMs.empty()) {
2554 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2555 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2556 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2557 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2558 LiveXMMRegs.push_back(
2559 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2560 }
2561 }
2563 // Store them to the va_list returned by va_start.
2564 if (MFI->hasVAStart()) {
2565 if (IsWin64) {
2566 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2567 // Get to the caller-allocated home save location. Add 8 to account
2568 // for the return address.
2569 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2570 FuncInfo->setRegSaveFrameIndex(
2571 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2572 // Fixup to set vararg frame on shadow area (4 x i64).
2573 if (NumIntRegs < 4)
2574 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2575 } else {
2576 // For X86-64, if there are vararg parameters that are passed via
2577 // registers, then we must store them to their spots on the stack so
2578 // they may be loaded by deferencing the result of va_next.
2579 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2580 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2581 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2582 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2583 }
2585 // Store the integer parameter registers.
2586 SmallVector<SDValue, 8> MemOps;
2587 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2588 getPointerTy());
2589 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2590 for (SDValue Val : LiveGPRs) {
2591 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2592 DAG.getIntPtrConstant(Offset));
2593 SDValue Store =
2594 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2595 MachinePointerInfo::getFixedStack(
2596 FuncInfo->getRegSaveFrameIndex(), Offset),
2597 false, false, 0);
2598 MemOps.push_back(Store);
2599 Offset += 8;
2600 }
2602 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2603 // Now store the XMM (fp + vector) parameter registers.
2604 SmallVector<SDValue, 12> SaveXMMOps;
2605 SaveXMMOps.push_back(Chain);
2606 SaveXMMOps.push_back(ALVal);
2607 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2608 FuncInfo->getRegSaveFrameIndex()));
2609 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2610 FuncInfo->getVarArgsFPOffset()));
2611 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2612 LiveXMMRegs.end());
2613 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2614 MVT::Other, SaveXMMOps));
2615 }
2617 if (!MemOps.empty())
2618 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2619 } else {
2620 // Add all GPRs, al, and XMMs to the list of forwards. We will add then
2621 // to the liveout set on a musttail call.
2622 assert(MFI->hasMustTailInVarArgFunc());
2623 auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
2624 typedef X86MachineFunctionInfo::Forward Forward;
2626 for (unsigned I = 0, E = LiveGPRs.size(); I != E; ++I) {
2627 unsigned VReg =
2628 MF.getRegInfo().createVirtualRegister(&X86::GR64RegClass);
2629 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveGPRs[I]);
2630 Forwards.push_back(Forward(VReg, ArgGPRs[NumIntRegs + I], MVT::i64));
2631 }
2633 if (!ArgXMMs.empty()) {
2634 unsigned ALVReg =
2635 MF.getRegInfo().createVirtualRegister(&X86::GR8RegClass);
2636 Chain = DAG.getCopyToReg(Chain, dl, ALVReg, ALVal);
2637 Forwards.push_back(Forward(ALVReg, X86::AL, MVT::i8));
2639 for (unsigned I = 0, E = LiveXMMRegs.size(); I != E; ++I) {
2640 unsigned VReg =
2641 MF.getRegInfo().createVirtualRegister(&X86::VR128RegClass);
2642 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveXMMRegs[I]);
2643 Forwards.push_back(
2644 Forward(VReg, ArgXMMs[NumXMMRegs + I], MVT::v4f32));
2645 }
2646 }
2647 }
2648 }
2650 // Some CCs need callee pop.
2651 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2652 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2653 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2654 } else {
2655 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2656 // If this is an sret function, the return should pop the hidden pointer.
2657 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2658 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2659 argsAreStructReturn(Ins) == StackStructReturn)
2660 FuncInfo->setBytesToPopOnReturn(4);
2661 }
2663 if (!Is64Bit) {
2664 // RegSaveFrameIndex is X86-64 only.
2665 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2666 if (CallConv == CallingConv::X86_FastCall ||
2667 CallConv == CallingConv::X86_ThisCall)
2668 // fastcc functions can't have varargs.
2669 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2670 }
2672 FuncInfo->setArgumentStackSize(StackSize);
2674 return Chain;
2675 }
2677 SDValue
2678 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2679 SDValue StackPtr, SDValue Arg,
2680 SDLoc dl, SelectionDAG &DAG,
2681 const CCValAssign &VA,
2682 ISD::ArgFlagsTy Flags) const {
2683 unsigned LocMemOffset = VA.getLocMemOffset();
2684 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2685 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2686 if (Flags.isByVal())
2687 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2689 return DAG.getStore(Chain, dl, Arg, PtrOff,
2690 MachinePointerInfo::getStack(LocMemOffset),
2691 false, false, 0);
2692 }
2694 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2695 /// optimization is performed and it is required.
2696 SDValue
2697 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2698 SDValue &OutRetAddr, SDValue Chain,
2699 bool IsTailCall, bool Is64Bit,
2700 int FPDiff, SDLoc dl) const {
2701 // Adjust the Return address stack slot.
2702 EVT VT = getPointerTy();
2703 OutRetAddr = getReturnAddressFrameIndex(DAG);
2705 // Load the "old" Return address.
2706 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2707 false, false, false, 0);
2708 return SDValue(OutRetAddr.getNode(), 1);
2709 }
2711 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2712 /// optimization is performed and it is required (FPDiff!=0).
2713 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2714 SDValue Chain, SDValue RetAddrFrIdx,
2715 EVT PtrVT, unsigned SlotSize,
2716 int FPDiff, SDLoc dl) {
2717 // Store the return address to the appropriate stack slot.
2718 if (!FPDiff) return Chain;
2719 // Calculate the new stack slot for the return address.
2720 int NewReturnAddrFI =
2721 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2722 false);
2723 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2724 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2725 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2726 false, false, 0);
2727 return Chain;
2728 }
2730 SDValue
2731 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2732 SmallVectorImpl<SDValue> &InVals) const {
2733 SelectionDAG &DAG = CLI.DAG;
2734 SDLoc &dl = CLI.DL;
2735 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2736 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2737 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2738 SDValue Chain = CLI.Chain;
2739 SDValue Callee = CLI.Callee;
2740 CallingConv::ID CallConv = CLI.CallConv;
2741 bool &isTailCall = CLI.IsTailCall;
2742 bool isVarArg = CLI.IsVarArg;
2744 MachineFunction &MF = DAG.getMachineFunction();
2745 bool Is64Bit = Subtarget->is64Bit();
2746 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2747 StructReturnType SR = callIsStructReturn(Outs);
2748 bool IsSibcall = false;
2749 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2751 if (MF.getTarget().Options.DisableTailCalls)
2752 isTailCall = false;
2754 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2755 if (IsMustTail) {
2756 // Force this to be a tail call. The verifier rules are enough to ensure
2757 // that we can lower this successfully without moving the return address
2758 // around.
2759 isTailCall = true;
2760 } else if (isTailCall) {
2761 // Check if it's really possible to do a tail call.
2762 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2763 isVarArg, SR != NotStructReturn,
2764 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2765 Outs, OutVals, Ins, DAG);
2767 // Sibcalls are automatically detected tailcalls which do not require
2768 // ABI changes.
2769 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2770 IsSibcall = true;
2772 if (isTailCall)
2773 ++NumTailCalls;
2774 }
2776 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2777 "Var args not supported with calling convention fastcc, ghc or hipe");
2779 // Analyze operands of the call, assigning locations to each operand.
2780 SmallVector<CCValAssign, 16> ArgLocs;
2781 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2783 // Allocate shadow area for Win64
2784 if (IsWin64)
2785 CCInfo.AllocateStack(32, 8);
2787 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2789 // Get a count of how many bytes are to be pushed on the stack.
2790 unsigned NumBytes = CCInfo.getNextStackOffset();
2791 if (IsSibcall)
2792 // This is a sibcall. The memory operands are available in caller's
2793 // own caller's stack.
2794 NumBytes = 0;
2795 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2796 IsTailCallConvention(CallConv))
2797 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2799 int FPDiff = 0;
2800 if (isTailCall && !IsSibcall && !IsMustTail) {
2801 // Lower arguments at fp - stackoffset + fpdiff.
2802 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2804 FPDiff = NumBytesCallerPushed - NumBytes;
2806 // Set the delta of movement of the returnaddr stackslot.
2807 // But only set if delta is greater than previous delta.
2808 if (FPDiff < X86Info->getTCReturnAddrDelta())
2809 X86Info->setTCReturnAddrDelta(FPDiff);
2810 }
2812 unsigned NumBytesToPush = NumBytes;
2813 unsigned NumBytesToPop = NumBytes;
2815 // If we have an inalloca argument, all stack space has already been allocated
2816 // for us and be right at the top of the stack. We don't support multiple
2817 // arguments passed in memory when using inalloca.
2818 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2819 NumBytesToPush = 0;
2820 if (!ArgLocs.back().isMemLoc())
2821 report_fatal_error("cannot use inalloca attribute on a register "
2822 "parameter");
2823 if (ArgLocs.back().getLocMemOffset() != 0)
2824 report_fatal_error("any parameter with the inalloca attribute must be "
2825 "the only memory argument");
2826 }
2828 if (!IsSibcall)
2829 Chain = DAG.getCALLSEQ_START(
2830 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2832 SDValue RetAddrFrIdx;
2833 // Load return address for tail calls.
2834 if (isTailCall && FPDiff)
2835 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2836 Is64Bit, FPDiff, dl);
2838 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2839 SmallVector<SDValue, 8> MemOpChains;
2840 SDValue StackPtr;
2842 // Walk the register/memloc assignments, inserting copies/loads. In the case
2843 // of tail call optimization arguments are handle later.
2844 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2845 DAG.getSubtarget().getRegisterInfo());
2846 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2847 // Skip inalloca arguments, they have already been written.
2848 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2849 if (Flags.isInAlloca())
2850 continue;
2852 CCValAssign &VA = ArgLocs[i];
2853 EVT RegVT = VA.getLocVT();
2854 SDValue Arg = OutVals[i];
2855 bool isByVal = Flags.isByVal();
2857 // Promote the value if needed.
2858 switch (VA.getLocInfo()) {
2859 default: llvm_unreachable("Unknown loc info!");
2860 case CCValAssign::Full: break;
2861 case CCValAssign::SExt:
2862 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2863 break;
2864 case CCValAssign::ZExt:
2865 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2866 break;
2867 case CCValAssign::AExt:
2868 if (RegVT.is128BitVector()) {
2869 // Special case: passing MMX values in XMM registers.
2870 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2871 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2872 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2873 } else
2874 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2875 break;
2876 case CCValAssign::BCvt:
2877 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2878 break;
2879 case CCValAssign::Indirect: {
2880 // Store the argument.
2881 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2882 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2883 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2884 MachinePointerInfo::getFixedStack(FI),
2885 false, false, 0);
2886 Arg = SpillSlot;
2887 break;
2888 }
2889 }
2891 if (VA.isRegLoc()) {
2892 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2893 if (isVarArg && IsWin64) {
2894 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2895 // shadow reg if callee is a varargs function.
2896 unsigned ShadowReg = 0;
2897 switch (VA.getLocReg()) {
2898 case X86::XMM0: ShadowReg = X86::RCX; break;
2899 case X86::XMM1: ShadowReg = X86::RDX; break;
2900 case X86::XMM2: ShadowReg = X86::R8; break;
2901 case X86::XMM3: ShadowReg = X86::R9; break;
2902 }
2903 if (ShadowReg)
2904 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2905 }
2906 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2907 assert(VA.isMemLoc());
2908 if (!StackPtr.getNode())
2909 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2910 getPointerTy());
2911 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2912 dl, DAG, VA, Flags));
2913 }
2914 }
2916 if (!MemOpChains.empty())
2917 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2919 if (Subtarget->isPICStyleGOT()) {
2920 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2921 // GOT pointer.
2922 if (!isTailCall) {
2923 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2924 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2925 } else {
2926 // If we are tail calling and generating PIC/GOT style code load the
2927 // address of the callee into ECX. The value in ecx is used as target of
2928 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2929 // for tail calls on PIC/GOT architectures. Normally we would just put the
2930 // address of GOT into ebx and then call target@PLT. But for tail calls
2931 // ebx would be restored (since ebx is callee saved) before jumping to the
2932 // target@PLT.
2934 // Note: The actual moving to ECX is done further down.
2935 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2936 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2937 !G->getGlobal()->hasProtectedVisibility())
2938 Callee = LowerGlobalAddress(Callee, DAG);
2939 else if (isa<ExternalSymbolSDNode>(Callee))
2940 Callee = LowerExternalSymbol(Callee, DAG);
2941 }
2942 }
2944 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2945 // From AMD64 ABI document:
2946 // For calls that may call functions that use varargs or stdargs
2947 // (prototype-less calls or calls to functions containing ellipsis (...) in
2948 // the declaration) %al is used as hidden argument to specify the number
2949 // of SSE registers used. The contents of %al do not need to match exactly
2950 // the number of registers, but must be an ubound on the number of SSE
2951 // registers used and is in the range 0 - 8 inclusive.
2953 // Count the number of XMM registers allocated.
2954 static const MCPhysReg XMMArgRegs[] = {
2955 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2956 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2957 };
2958 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2959 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2960 && "SSE registers cannot be used when SSE is disabled");
2962 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2963 DAG.getConstant(NumXMMRegs, MVT::i8)));
2964 }
2966 if (Is64Bit && isVarArg && IsMustTail) {
2967 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2968 for (const auto &F : Forwards) {
2969 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2970 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
2971 }
2972 }
2974 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2975 // don't need this because the eligibility check rejects calls that require
2976 // shuffling arguments passed in memory.
2977 if (!IsSibcall && isTailCall) {
2978 // Force all the incoming stack arguments to be loaded from the stack
2979 // before any new outgoing arguments are stored to the stack, because the
2980 // outgoing stack slots may alias the incoming argument stack slots, and
2981 // the alias isn't otherwise explicit. This is slightly more conservative
2982 // than necessary, because it means that each store effectively depends
2983 // on every argument instead of just those arguments it would clobber.
2984 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2986 SmallVector<SDValue, 8> MemOpChains2;
2987 SDValue FIN;
2988 int FI = 0;
2989 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2990 CCValAssign &VA = ArgLocs[i];
2991 if (VA.isRegLoc())
2992 continue;
2993 assert(VA.isMemLoc());
2994 SDValue Arg = OutVals[i];
2995 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2996 // Skip inalloca arguments. They don't require any work.
2997 if (Flags.isInAlloca())
2998 continue;
2999 // Create frame index.
3000 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3001 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3002 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3003 FIN = DAG.getFrameIndex(FI, getPointerTy());
3005 if (Flags.isByVal()) {
3006 // Copy relative to framepointer.
3007 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3008 if (!StackPtr.getNode())
3009 StackPtr = DAG.getCopyFromReg(Chain, dl,
3010 RegInfo->getStackRegister(),
3011 getPointerTy());
3012 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3014 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3015 ArgChain,
3016 Flags, DAG, dl));
3017 } else {
3018 // Store relative to framepointer.
3019 MemOpChains2.push_back(
3020 DAG.getStore(ArgChain, dl, Arg, FIN,
3021 MachinePointerInfo::getFixedStack(FI),
3022 false, false, 0));
3023 }
3024 }
3026 if (!MemOpChains2.empty())
3027 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3029 // Store the return address to the appropriate stack slot.
3030 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3031 getPointerTy(), RegInfo->getSlotSize(),
3032 FPDiff, dl);
3033 }
3035 // Build a sequence of copy-to-reg nodes chained together with token chain
3036 // and flag operands which copy the outgoing args into registers.
3037 SDValue InFlag;
3038 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3039 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3040 RegsToPass[i].second, InFlag);
3041 InFlag = Chain.getValue(1);
3042 }
3044 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3045 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3046 // In the 64-bit large code model, we have to make all calls
3047 // through a register, since the call instruction's 32-bit
3048 // pc-relative offset may not be large enough to hold the whole
3049 // address.
3050 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3051 // If the callee is a GlobalAddress node (quite common, every direct call
3052 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3053 // it.
3055 // We should use extra load for direct calls to dllimported functions in
3056 // non-JIT mode.
3057 const GlobalValue *GV = G->getGlobal();
3058 if (!GV->hasDLLImportStorageClass()) {
3059 unsigned char OpFlags = 0;
3060 bool ExtraLoad = false;
3061 unsigned WrapperKind = ISD::DELETED_NODE;
3063 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3064 // external symbols most go through the PLT in PIC mode. If the symbol
3065 // has hidden or protected visibility, or if it is static or local, then
3066 // we don't need to use the PLT - we can directly call it.
3067 if (Subtarget->isTargetELF() &&
3068 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3069 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3070 OpFlags = X86II::MO_PLT;
3071 } else if (Subtarget->isPICStyleStubAny() &&
3072 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3073 (!Subtarget->getTargetTriple().isMacOSX() ||
3074 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3075 // PC-relative references to external symbols should go through $stub,
3076 // unless we're building with the leopard linker or later, which
3077 // automatically synthesizes these stubs.
3078 OpFlags = X86II::MO_DARWIN_STUB;
3079 } else if (Subtarget->isPICStyleRIPRel() &&
3080 isa<Function>(GV) &&
3081 cast<Function>(GV)->getAttributes().
3082 hasAttribute(AttributeSet::FunctionIndex,
3083 Attribute::NonLazyBind)) {
3084 // If the function is marked as non-lazy, generate an indirect call
3085 // which loads from the GOT directly. This avoids runtime overhead
3086 // at the cost of eager binding (and one extra byte of encoding).
3087 OpFlags = X86II::MO_GOTPCREL;
3088 WrapperKind = X86ISD::WrapperRIP;
3089 ExtraLoad = true;
3090 }
3092 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3093 G->getOffset(), OpFlags);
3095 // Add a wrapper if needed.
3096 if (WrapperKind != ISD::DELETED_NODE)
3097 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3098 // Add extra indirection if needed.
3099 if (ExtraLoad)
3100 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3101 MachinePointerInfo::getGOT(),
3102 false, false, false, 0);
3103 }
3104 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3105 unsigned char OpFlags = 0;
3107 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3108 // external symbols should go through the PLT.
3109 if (Subtarget->isTargetELF() &&
3110 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3111 OpFlags = X86II::MO_PLT;
3112 } else if (Subtarget->isPICStyleStubAny() &&
3113 (!Subtarget->getTargetTriple().isMacOSX() ||
3114 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3115 // PC-relative references to external symbols should go through $stub,
3116 // unless we're building with the leopard linker or later, which
3117 // automatically synthesizes these stubs.
3118 OpFlags = X86II::MO_DARWIN_STUB;
3119 }
3121 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3122 OpFlags);
3123 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3124 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3125 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3126 }
3128 // Returns a chain & a flag for retval copy to use.
3129 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3130 SmallVector<SDValue, 8> Ops;
3132 if (!IsSibcall && isTailCall) {
3133 Chain = DAG.getCALLSEQ_END(Chain,
3134 DAG.getIntPtrConstant(NumBytesToPop, true),
3135 DAG.getIntPtrConstant(0, true), InFlag, dl);
3136 InFlag = Chain.getValue(1);
3137 }
3139 Ops.push_back(Chain);
3140 Ops.push_back(Callee);
3142 if (isTailCall)
3143 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3145 // Add argument registers to the end of the list so that they are known live
3146 // into the call.
3147 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3148 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3149 RegsToPass[i].second.getValueType()));
3151 // Add a register mask operand representing the call-preserved registers.
3152 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3153 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3154 assert(Mask && "Missing call preserved mask for calling convention");
3155 Ops.push_back(DAG.getRegisterMask(Mask));
3157 if (InFlag.getNode())
3158 Ops.push_back(InFlag);
3160 if (isTailCall) {
3161 // We used to do:
3162 //// If this is the first return lowered for this function, add the regs
3163 //// to the liveout set for the function.
3164 // This isn't right, although it's probably harmless on x86; liveouts
3165 // should be computed from returns not tail calls. Consider a void
3166 // function making a tail call to a function returning int.
3167 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3168 }
3170 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3171 InFlag = Chain.getValue(1);
3173 // Create the CALLSEQ_END node.
3174 unsigned NumBytesForCalleeToPop;
3175 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3176 DAG.getTarget().Options.GuaranteedTailCallOpt))
3177 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3178 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3179 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3180 SR == StackStructReturn)
3181 // If this is a call to a struct-return function, the callee
3182 // pops the hidden struct pointer, so we have to push it back.
3183 // This is common for Darwin/X86, Linux & Mingw32 targets.
3184 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3185 NumBytesForCalleeToPop = 4;
3186 else
3187 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3189 // Returns a flag for retval copy to use.
3190 if (!IsSibcall) {
3191 Chain = DAG.getCALLSEQ_END(Chain,
3192 DAG.getIntPtrConstant(NumBytesToPop, true),
3193 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3194 true),
3195 InFlag, dl);
3196 InFlag = Chain.getValue(1);
3197 }
3199 // Handle result values, copying them out of physregs into vregs that we
3200 // return.
3201 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3202 Ins, dl, DAG, InVals);
3203 }
3205 //===----------------------------------------------------------------------===//
3206 // Fast Calling Convention (tail call) implementation
3207 //===----------------------------------------------------------------------===//
3209 // Like std call, callee cleans arguments, convention except that ECX is
3210 // reserved for storing the tail called function address. Only 2 registers are
3211 // free for argument passing (inreg). Tail call optimization is performed
3212 // provided:
3213 // * tailcallopt is enabled
3214 // * caller/callee are fastcc
3215 // On X86_64 architecture with GOT-style position independent code only local
3216 // (within module) calls are supported at the moment.
3217 // To keep the stack aligned according to platform abi the function
3218 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3219 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3220 // If a tail called function callee has more arguments than the caller the
3221 // caller needs to make sure that there is room to move the RETADDR to. This is
3222 // achieved by reserving an area the size of the argument delta right after the
3223 // original RETADDR, but before the saved framepointer or the spilled registers
3224 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3225 // stack layout:
3226 // arg1
3227 // arg2
3228 // RETADDR
3229 // [ new RETADDR
3230 // move area ]
3231 // (possible EBP)
3232 // ESI
3233 // EDI
3234 // local1 ..
3236 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3237 /// for a 16 byte align requirement.
3238 unsigned
3239 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3240 SelectionDAG& DAG) const {
3241 MachineFunction &MF = DAG.getMachineFunction();
3242 const TargetMachine &TM = MF.getTarget();
3243 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3244 TM.getSubtargetImpl()->getRegisterInfo());
3245 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3246 unsigned StackAlignment = TFI.getStackAlignment();
3247 uint64_t AlignMask = StackAlignment - 1;
3248 int64_t Offset = StackSize;
3249 unsigned SlotSize = RegInfo->getSlotSize();
3250 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3251 // Number smaller than 12 so just add the difference.
3252 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3253 } else {
3254 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3255 Offset = ((~AlignMask) & Offset) + StackAlignment +
3256 (StackAlignment-SlotSize);
3257 }
3258 return Offset;
3259 }
3261 /// MatchingStackOffset - Return true if the given stack call argument is
3262 /// already available in the same position (relatively) of the caller's
3263 /// incoming argument stack.
3264 static
3265 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3266 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3267 const X86InstrInfo *TII) {
3268 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3269 int FI = INT_MAX;
3270 if (Arg.getOpcode() == ISD::CopyFromReg) {
3271 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3272 if (!TargetRegisterInfo::isVirtualRegister(VR))
3273 return false;
3274 MachineInstr *Def = MRI->getVRegDef(VR);
3275 if (!Def)
3276 return false;
3277 if (!Flags.isByVal()) {
3278 if (!TII->isLoadFromStackSlot(Def, FI))
3279 return false;
3280 } else {
3281 unsigned Opcode = Def->getOpcode();
3282 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3283 Def->getOperand(1).isFI()) {
3284 FI = Def->getOperand(1).getIndex();
3285 Bytes = Flags.getByValSize();
3286 } else
3287 return false;
3288 }
3289 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3290 if (Flags.isByVal())
3291 // ByVal argument is passed in as a pointer but it's now being
3292 // dereferenced. e.g.
3293 // define @foo(%struct.X* %A) {
3294 // tail call @bar(%struct.X* byval %A)
3295 // }
3296 return false;
3297 SDValue Ptr = Ld->getBasePtr();
3298 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3299 if (!FINode)
3300 return false;
3301 FI = FINode->getIndex();
3302 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3303 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3304 FI = FINode->getIndex();
3305 Bytes = Flags.getByValSize();
3306 } else
3307 return false;
3309 assert(FI != INT_MAX);
3310 if (!MFI->isFixedObjectIndex(FI))
3311 return false;
3312 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3313 }
3315 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3316 /// for tail call optimization. Targets which want to do tail call
3317 /// optimization should implement this function.
3318 bool
3319 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3320 CallingConv::ID CalleeCC,
3321 bool isVarArg,
3322 bool isCalleeStructRet,
3323 bool isCallerStructRet,
3324 Type *RetTy,
3325 const SmallVectorImpl<ISD::OutputArg> &Outs,
3326 const SmallVectorImpl<SDValue> &OutVals,
3327 const SmallVectorImpl<ISD::InputArg> &Ins,
3328 SelectionDAG &DAG) const {
3329 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3330 return false;
3332 // If -tailcallopt is specified, make fastcc functions tail-callable.
3333 const MachineFunction &MF = DAG.getMachineFunction();
3334 const Function *CallerF = MF.getFunction();
3336 // If the function return type is x86_fp80 and the callee return type is not,
3337 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3338 // perform a tailcall optimization here.
3339 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3340 return false;
3342 CallingConv::ID CallerCC = CallerF->getCallingConv();
3343 bool CCMatch = CallerCC == CalleeCC;
3344 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3345 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3347 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3348 if (IsTailCallConvention(CalleeCC) && CCMatch)
3349 return true;
3350 return false;
3351 }
3353 // Look for obvious safe cases to perform tail call optimization that do not
3354 // require ABI changes. This is what gcc calls sibcall.
3356 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3357 // emit a special epilogue.
3358 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3359 DAG.getSubtarget().getRegisterInfo());
3360 if (RegInfo->needsStackRealignment(MF))
3361 return false;
3363 // Also avoid sibcall optimization if either caller or callee uses struct
3364 // return semantics.
3365 if (isCalleeStructRet || isCallerStructRet)
3366 return false;
3368 // An stdcall/thiscall caller is expected to clean up its arguments; the
3369 // callee isn't going to do that.
3370 // FIXME: this is more restrictive than needed. We could produce a tailcall
3371 // when the stack adjustment matches. For example, with a thiscall that takes
3372 // only one argument.
3373 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3374 CallerCC == CallingConv::X86_ThisCall))
3375 return false;
3377 // Do not sibcall optimize vararg calls unless all arguments are passed via
3378 // registers.
3379 if (isVarArg && !Outs.empty()) {
3381 // Optimizing for varargs on Win64 is unlikely to be safe without
3382 // additional testing.
3383 if (IsCalleeWin64 || IsCallerWin64)
3384 return false;
3386 SmallVector<CCValAssign, 16> ArgLocs;
3387 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3388 *DAG.getContext());
3390 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3391 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3392 if (!ArgLocs[i].isRegLoc())
3393 return false;
3394 }
3396 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3397 // stack. Therefore, if it's not used by the call it is not safe to optimize
3398 // this into a sibcall.
3399 bool Unused = false;
3400 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3401 if (!Ins[i].Used) {
3402 Unused = true;
3403 break;
3404 }
3405 }
3406 if (Unused) {
3407 SmallVector<CCValAssign, 16> RVLocs;
3408 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3409 *DAG.getContext());
3410 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3411 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3412 CCValAssign &VA = RVLocs[i];
3413 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3414 return false;
3415 }
3416 }
3418 // If the calling conventions do not match, then we'd better make sure the
3419 // results are returned in the same way as what the caller expects.
3420 if (!CCMatch) {
3421 SmallVector<CCValAssign, 16> RVLocs1;
3422 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3423 *DAG.getContext());
3424 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3426 SmallVector<CCValAssign, 16> RVLocs2;
3427 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3428 *DAG.getContext());
3429 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3431 if (RVLocs1.size() != RVLocs2.size())
3432 return false;
3433 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3434 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3435 return false;
3436 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3437 return false;
3438 if (RVLocs1[i].isRegLoc()) {
3439 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3440 return false;
3441 } else {
3442 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3443 return false;
3444 }
3445 }
3446 }
3448 // If the callee takes no arguments then go on to check the results of the
3449 // call.
3450 if (!Outs.empty()) {
3451 // Check if stack adjustment is needed. For now, do not do this if any
3452 // argument is passed on the stack.
3453 SmallVector<CCValAssign, 16> ArgLocs;
3454 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3455 *DAG.getContext());
3457 // Allocate shadow area for Win64
3458 if (IsCalleeWin64)
3459 CCInfo.AllocateStack(32, 8);
3461 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3462 if (CCInfo.getNextStackOffset()) {
3463 MachineFunction &MF = DAG.getMachineFunction();
3464 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3465 return false;
3467 // Check if the arguments are already laid out in the right way as
3468 // the caller's fixed stack objects.
3469 MachineFrameInfo *MFI = MF.getFrameInfo();
3470 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3471 const X86InstrInfo *TII =
3472 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3473 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3474 CCValAssign &VA = ArgLocs[i];
3475 SDValue Arg = OutVals[i];
3476 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3477 if (VA.getLocInfo() == CCValAssign::Indirect)
3478 return false;
3479 if (!VA.isRegLoc()) {
3480 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3481 MFI, MRI, TII))
3482 return false;
3483 }
3484 }
3485 }
3487 // If the tailcall address may be in a register, then make sure it's
3488 // possible to register allocate for it. In 32-bit, the call address can
3489 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3490 // callee-saved registers are restored. These happen to be the same
3491 // registers used to pass 'inreg' arguments so watch out for those.
3492 if (!Subtarget->is64Bit() &&
3493 ((!isa<GlobalAddressSDNode>(Callee) &&
3494 !isa<ExternalSymbolSDNode>(Callee)) ||
3495 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3496 unsigned NumInRegs = 0;
3497 // In PIC we need an extra register to formulate the address computation
3498 // for the callee.
3499 unsigned MaxInRegs =
3500 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3502 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3503 CCValAssign &VA = ArgLocs[i];
3504 if (!VA.isRegLoc())
3505 continue;
3506 unsigned Reg = VA.getLocReg();
3507 switch (Reg) {
3508 default: break;
3509 case X86::EAX: case X86::EDX: case X86::ECX:
3510 if (++NumInRegs == MaxInRegs)
3511 return false;
3512 break;
3513 }
3514 }
3515 }
3516 }
3518 return true;
3519 }
3521 FastISel *
3522 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3523 const TargetLibraryInfo *libInfo) const {
3524 return X86::createFastISel(funcInfo, libInfo);
3525 }
3527 //===----------------------------------------------------------------------===//
3528 // Other Lowering Hooks
3529 //===----------------------------------------------------------------------===//
3531 static bool MayFoldLoad(SDValue Op) {
3532 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3533 }
3535 static bool MayFoldIntoStore(SDValue Op) {
3536 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3537 }
3539 static bool isTargetShuffle(unsigned Opcode) {
3540 switch(Opcode) {
3541 default: return false;
3542 case X86ISD::BLENDI:
3543 case X86ISD::PSHUFB:
3544 case X86ISD::PSHUFD:
3545 case X86ISD::PSHUFHW:
3546 case X86ISD::PSHUFLW:
3547 case X86ISD::SHUFP:
3548 case X86ISD::PALIGNR:
3549 case X86ISD::MOVLHPS:
3550 case X86ISD::MOVLHPD:
3551 case X86ISD::MOVHLPS:
3552 case X86ISD::MOVLPS:
3553 case X86ISD::MOVLPD:
3554 case X86ISD::MOVSHDUP:
3555 case X86ISD::MOVSLDUP:
3556 case X86ISD::MOVDDUP:
3557 case X86ISD::MOVSS:
3558 case X86ISD::MOVSD:
3559 case X86ISD::UNPCKL:
3560 case X86ISD::UNPCKH:
3561 case X86ISD::VPERMILPI:
3562 case X86ISD::VPERM2X128:
3563 case X86ISD::VPERMI:
3564 return true;
3565 }
3566 }
3568 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3569 SDValue V1, SelectionDAG &DAG) {
3570 switch(Opc) {
3571 default: llvm_unreachable("Unknown x86 shuffle node");
3572 case X86ISD::MOVSHDUP:
3573 case X86ISD::MOVSLDUP:
3574 case X86ISD::MOVDDUP:
3575 return DAG.getNode(Opc, dl, VT, V1);
3576 }
3577 }
3579 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3580 SDValue V1, unsigned TargetMask,
3581 SelectionDAG &DAG) {
3582 switch(Opc) {
3583 default: llvm_unreachable("Unknown x86 shuffle node");
3584 case X86ISD::PSHUFD:
3585 case X86ISD::PSHUFHW:
3586 case X86ISD::PSHUFLW:
3587 case X86ISD::VPERMILPI:
3588 case X86ISD::VPERMI:
3589 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3590 }
3591 }
3593 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3594 SDValue V1, SDValue V2, unsigned TargetMask,
3595 SelectionDAG &DAG) {
3596 switch(Opc) {
3597 default: llvm_unreachable("Unknown x86 shuffle node");
3598 case X86ISD::PALIGNR:
3599 case X86ISD::VALIGN:
3600 case X86ISD::SHUFP:
3601 case X86ISD::VPERM2X128:
3602 return DAG.getNode(Opc, dl, VT, V1, V2,
3603 DAG.getConstant(TargetMask, MVT::i8));
3604 }
3605 }
3607 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3608 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3609 switch(Opc) {
3610 default: llvm_unreachable("Unknown x86 shuffle node");
3611 case X86ISD::MOVLHPS:
3612 case X86ISD::MOVLHPD:
3613 case X86ISD::MOVHLPS:
3614 case X86ISD::MOVLPS:
3615 case X86ISD::MOVLPD:
3616 case X86ISD::MOVSS:
3617 case X86ISD::MOVSD:
3618 case X86ISD::UNPCKL:
3619 case X86ISD::UNPCKH:
3620 return DAG.getNode(Opc, dl, VT, V1, V2);
3621 }
3622 }
3624 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3625 MachineFunction &MF = DAG.getMachineFunction();
3626 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3627 DAG.getSubtarget().getRegisterInfo());
3628 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3629 int ReturnAddrIndex = FuncInfo->getRAIndex();
3631 if (ReturnAddrIndex == 0) {
3632 // Set up a frame object for the return address.
3633 unsigned SlotSize = RegInfo->getSlotSize();
3634 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3635 -(int64_t)SlotSize,
3636 false);
3637 FuncInfo->setRAIndex(ReturnAddrIndex);
3638 }
3640 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3641 }
3643 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3644 bool hasSymbolicDisplacement) {
3645 // Offset should fit into 32 bit immediate field.
3646 if (!isInt<32>(Offset))
3647 return false;
3649 // If we don't have a symbolic displacement - we don't have any extra
3650 // restrictions.
3651 if (!hasSymbolicDisplacement)
3652 return true;
3654 // FIXME: Some tweaks might be needed for medium code model.
3655 if (M != CodeModel::Small && M != CodeModel::Kernel)
3656 return false;
3658 // For small code model we assume that latest object is 16MB before end of 31
3659 // bits boundary. We may also accept pretty large negative constants knowing
3660 // that all objects are in the positive half of address space.
3661 if (M == CodeModel::Small && Offset < 16*1024*1024)
3662 return true;
3664 // For kernel code model we know that all object resist in the negative half
3665 // of 32bits address space. We may not accept negative offsets, since they may
3666 // be just off and we may accept pretty large positive ones.
3667 if (M == CodeModel::Kernel && Offset > 0)
3668 return true;
3670 return false;
3671 }
3673 /// isCalleePop - Determines whether the callee is required to pop its
3674 /// own arguments. Callee pop is necessary to support tail calls.
3675 bool X86::isCalleePop(CallingConv::ID CallingConv,
3676 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3677 switch (CallingConv) {
3678 default:
3679 return false;
3680 case CallingConv::X86_StdCall:
3681 case CallingConv::X86_FastCall:
3682 case CallingConv::X86_ThisCall:
3683 return !is64Bit;
3684 case CallingConv::Fast:
3685 case CallingConv::GHC:
3686 case CallingConv::HiPE:
3687 if (IsVarArg)
3688 return false;
3689 return TailCallOpt;
3690 }
3691 }
3693 /// \brief Return true if the condition is an unsigned comparison operation.
3694 static bool isX86CCUnsigned(unsigned X86CC) {
3695 switch (X86CC) {
3696 default: llvm_unreachable("Invalid integer condition!");
3697 case X86::COND_E: return true;
3698 case X86::COND_G: return false;
3699 case X86::COND_GE: return false;
3700 case X86::COND_L: return false;
3701 case X86::COND_LE: return false;
3702 case X86::COND_NE: return true;
3703 case X86::COND_B: return true;
3704 case X86::COND_A: return true;
3705 case X86::COND_BE: return true;
3706 case X86::COND_AE: return true;
3707 }
3708 llvm_unreachable("covered switch fell through?!");
3709 }
3711 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3712 /// specific condition code, returning the condition code and the LHS/RHS of the
3713 /// comparison to make.
3714 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3715 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3716 if (!isFP) {
3717 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3718 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3719 // X > -1 -> X == 0, jump !sign.
3720 RHS = DAG.getConstant(0, RHS.getValueType());
3721 return X86::COND_NS;
3722 }
3723 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3724 // X < 0 -> X == 0, jump on sign.
3725 return X86::COND_S;
3726 }
3727 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3728 // X < 1 -> X <= 0
3729 RHS = DAG.getConstant(0, RHS.getValueType());
3730 return X86::COND_LE;
3731 }
3732 }
3734 switch (SetCCOpcode) {
3735 default: llvm_unreachable("Invalid integer condition!");
3736 case ISD::SETEQ: return X86::COND_E;
3737 case ISD::SETGT: return X86::COND_G;
3738 case ISD::SETGE: return X86::COND_GE;
3739 case ISD::SETLT: return X86::COND_L;
3740 case ISD::SETLE: return X86::COND_LE;
3741 case ISD::SETNE: return X86::COND_NE;
3742 case ISD::SETULT: return X86::COND_B;
3743 case ISD::SETUGT: return X86::COND_A;
3744 case ISD::SETULE: return X86::COND_BE;
3745 case ISD::SETUGE: return X86::COND_AE;
3746 }
3747 }
3749 // First determine if it is required or is profitable to flip the operands.
3751 // If LHS is a foldable load, but RHS is not, flip the condition.
3752 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3753 !ISD::isNON_EXTLoad(RHS.getNode())) {
3754 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3755 std::swap(LHS, RHS);
3756 }
3758 switch (SetCCOpcode) {
3759 default: break;
3760 case ISD::SETOLT:
3761 case ISD::SETOLE:
3762 case ISD::SETUGT:
3763 case ISD::SETUGE:
3764 std::swap(LHS, RHS);
3765 break;
3766 }
3768 // On a floating point condition, the flags are set as follows:
3769 // ZF PF CF op
3770 // 0 | 0 | 0 | X > Y
3771 // 0 | 0 | 1 | X < Y
3772 // 1 | 0 | 0 | X == Y
3773 // 1 | 1 | 1 | unordered
3774 switch (SetCCOpcode) {
3775 default: llvm_unreachable("Condcode should be pre-legalized away");
3776 case ISD::SETUEQ:
3777 case ISD::SETEQ: return X86::COND_E;
3778 case ISD::SETOLT: // flipped
3779 case ISD::SETOGT:
3780 case ISD::SETGT: return X86::COND_A;
3781 case ISD::SETOLE: // flipped
3782 case ISD::SETOGE:
3783 case ISD::SETGE: return X86::COND_AE;
3784 case ISD::SETUGT: // flipped
3785 case ISD::SETULT:
3786 case ISD::SETLT: return X86::COND_B;
3787 case ISD::SETUGE: // flipped
3788 case ISD::SETULE:
3789 case ISD::SETLE: return X86::COND_BE;
3790 case ISD::SETONE:
3791 case ISD::SETNE: return X86::COND_NE;
3792 case ISD::SETUO: return X86::COND_P;
3793 case ISD::SETO: return X86::COND_NP;
3794 case ISD::SETOEQ:
3795 case ISD::SETUNE: return X86::COND_INVALID;
3796 }
3797 }
3799 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3800 /// code. Current x86 isa includes the following FP cmov instructions:
3801 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3802 static bool hasFPCMov(unsigned X86CC) {
3803 switch (X86CC) {
3804 default:
3805 return false;
3806 case X86::COND_B:
3807 case X86::COND_BE:
3808 case X86::COND_E:
3809 case X86::COND_P:
3810 case X86::COND_A:
3811 case X86::COND_AE:
3812 case X86::COND_NE:
3813 case X86::COND_NP:
3814 return true;
3815 }
3816 }
3818 /// isFPImmLegal - Returns true if the target can instruction select the
3819 /// specified FP immediate natively. If false, the legalizer will
3820 /// materialize the FP immediate as a load from a constant pool.
3821 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3822 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3823 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3824 return true;
3825 }
3826 return false;
3827 }
3829 /// \brief Returns true if it is beneficial to convert a load of a constant
3830 /// to just the constant itself.
3831 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3832 Type *Ty) const {
3833 assert(Ty->isIntegerTy());
3835 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3836 if (BitSize == 0 || BitSize > 64)
3837 return false;
3838 return true;
3839 }
3841 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3842 /// the specified range (L, H].
3843 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3844 return (Val < 0) || (Val >= Low && Val < Hi);
3845 }
3847 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3848 /// specified value.
3849 static bool isUndefOrEqual(int Val, int CmpVal) {
3850 return (Val < 0 || Val == CmpVal);
3851 }
3853 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3854 /// from position Pos and ending in Pos+Size, falls within the specified
3855 /// sequential range (L, L+Pos]. or is undef.
3856 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3857 unsigned Pos, unsigned Size, int Low) {
3858 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3859 if (!isUndefOrEqual(Mask[i], Low))
3860 return false;
3861 return true;
3862 }
3864 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3865 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3866 /// the second operand.
3867 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3868 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3869 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3870 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3871 return (Mask[0] < 2 && Mask[1] < 2);
3872 return false;
3873 }
3875 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3876 /// is suitable for input to PSHUFHW.
3877 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3878 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3879 return false;
3881 // Lower quadword copied in order or undef.
3882 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3883 return false;
3885 // Upper quadword shuffled.
3886 for (unsigned i = 4; i != 8; ++i)
3887 if (!isUndefOrInRange(Mask[i], 4, 8))
3888 return false;
3890 if (VT == MVT::v16i16) {
3891 // Lower quadword copied in order or undef.
3892 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3893 return false;
3895 // Upper quadword shuffled.
3896 for (unsigned i = 12; i != 16; ++i)
3897 if (!isUndefOrInRange(Mask[i], 12, 16))
3898 return false;
3899 }
3901 return true;
3902 }
3904 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3905 /// is suitable for input to PSHUFLW.
3906 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3907 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3908 return false;
3910 // Upper quadword copied in order.
3911 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3912 return false;
3914 // Lower quadword shuffled.
3915 for (unsigned i = 0; i != 4; ++i)
3916 if (!isUndefOrInRange(Mask[i], 0, 4))
3917 return false;
3919 if (VT == MVT::v16i16) {
3920 // Upper quadword copied in order.
3921 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3922 return false;
3924 // Lower quadword shuffled.
3925 for (unsigned i = 8; i != 12; ++i)
3926 if (!isUndefOrInRange(Mask[i], 8, 12))
3927 return false;
3928 }
3930 return true;
3931 }
3933 /// \brief Return true if the mask specifies a shuffle of elements that is
3934 /// suitable for input to intralane (palignr) or interlane (valign) vector
3935 /// right-shift.
3936 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3937 unsigned NumElts = VT.getVectorNumElements();
3938 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3939 unsigned NumLaneElts = NumElts/NumLanes;
3941 // Do not handle 64-bit element shuffles with palignr.
3942 if (NumLaneElts == 2)
3943 return false;
3945 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3946 unsigned i;
3947 for (i = 0; i != NumLaneElts; ++i) {
3948 if (Mask[i+l] >= 0)
3949 break;
3950 }
3952 // Lane is all undef, go to next lane
3953 if (i == NumLaneElts)
3954 continue;
3956 int Start = Mask[i+l];
3958 // Make sure its in this lane in one of the sources
3959 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3960 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3961 return false;
3963 // If not lane 0, then we must match lane 0
3964 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3965 return false;
3967 // Correct second source to be contiguous with first source
3968 if (Start >= (int)NumElts)
3969 Start -= NumElts - NumLaneElts;
3971 // Make sure we're shifting in the right direction.
3972 if (Start <= (int)(i+l))
3973 return false;
3975 Start -= i;
3977 // Check the rest of the elements to see if they are consecutive.
3978 for (++i; i != NumLaneElts; ++i) {
3979 int Idx = Mask[i+l];
3981 // Make sure its in this lane
3982 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3983 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3984 return false;
3986 // If not lane 0, then we must match lane 0
3987 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3988 return false;
3990 if (Idx >= (int)NumElts)
3991 Idx -= NumElts - NumLaneElts;
3993 if (!isUndefOrEqual(Idx, Start+i))
3994 return false;
3996 }
3997 }
3999 return true;
4000 }
4002 /// \brief Return true if the node specifies a shuffle of elements that is
4003 /// suitable for input to PALIGNR.
4004 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4005 const X86Subtarget *Subtarget) {
4006 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4007 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4008 VT.is512BitVector())
4009 // FIXME: Add AVX512BW.
4010 return false;
4012 return isAlignrMask(Mask, VT, false);
4013 }
4015 /// \brief Return true if the node specifies a shuffle of elements that is
4016 /// suitable for input to VALIGN.
4017 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4018 const X86Subtarget *Subtarget) {
4019 // FIXME: Add AVX512VL.
4020 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4021 return false;
4022 return isAlignrMask(Mask, VT, true);
4023 }
4025 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4026 /// the two vector operands have swapped position.
4027 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4028 unsigned NumElems) {
4029 for (unsigned i = 0; i != NumElems; ++i) {
4030 int idx = Mask[i];
4031 if (idx < 0)
4032 continue;
4033 else if (idx < (int)NumElems)
4034 Mask[i] = idx + NumElems;
4035 else
4036 Mask[i] = idx - NumElems;
4037 }
4038 }
4040 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4041 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4042 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4043 /// reverse of what x86 shuffles want.
4044 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4046 unsigned NumElems = VT.getVectorNumElements();
4047 unsigned NumLanes = VT.getSizeInBits()/128;
4048 unsigned NumLaneElems = NumElems/NumLanes;
4050 if (NumLaneElems != 2 && NumLaneElems != 4)
4051 return false;
4053 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4054 bool symetricMaskRequired =
4055 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4057 // VSHUFPSY divides the resulting vector into 4 chunks.
4058 // The sources are also splitted into 4 chunks, and each destination
4059 // chunk must come from a different source chunk.
4060 //
4061 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4062 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4063 //
4064 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4065 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4066 //
4067 // VSHUFPDY divides the resulting vector into 4 chunks.
4068 // The sources are also splitted into 4 chunks, and each destination
4069 // chunk must come from a different source chunk.
4070 //
4071 // SRC1 => X3 X2 X1 X0
4072 // SRC2 => Y3 Y2 Y1 Y0
4073 //
4074 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4075 //
4076 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4077 unsigned HalfLaneElems = NumLaneElems/2;
4078 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4079 for (unsigned i = 0; i != NumLaneElems; ++i) {
4080 int Idx = Mask[i+l];
4081 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4082 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4083 return false;
4084 // For VSHUFPSY, the mask of the second half must be the same as the
4085 // first but with the appropriate offsets. This works in the same way as
4086 // VPERMILPS works with masks.
4087 if (!symetricMaskRequired || Idx < 0)
4088 continue;
4089 if (MaskVal[i] < 0) {
4090 MaskVal[i] = Idx - l;
4091 continue;
4092 }
4093 if ((signed)(Idx - l) != MaskVal[i])
4094 return false;
4095 }
4096 }
4098 return true;
4099 }
4101 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4102 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4103 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4104 if (!VT.is128BitVector())
4105 return false;
4107 unsigned NumElems = VT.getVectorNumElements();
4109 if (NumElems != 4)
4110 return false;
4112 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4113 return isUndefOrEqual(Mask[0], 6) &&
4114 isUndefOrEqual(Mask[1], 7) &&
4115 isUndefOrEqual(Mask[2], 2) &&
4116 isUndefOrEqual(Mask[3], 3);
4117 }
4119 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4120 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4121 /// <2, 3, 2, 3>
4122 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4123 if (!VT.is128BitVector())
4124 return false;
4126 unsigned NumElems = VT.getVectorNumElements();
4128 if (NumElems != 4)
4129 return false;
4131 return isUndefOrEqual(Mask[0], 2) &&
4132 isUndefOrEqual(Mask[1], 3) &&
4133 isUndefOrEqual(Mask[2], 2) &&
4134 isUndefOrEqual(Mask[3], 3);
4135 }
4137 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4138 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4139 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4140 if (!VT.is128BitVector())
4141 return false;
4143 unsigned NumElems = VT.getVectorNumElements();
4145 if (NumElems != 2 && NumElems != 4)
4146 return false;
4148 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4149 if (!isUndefOrEqual(Mask[i], i + NumElems))
4150 return false;
4152 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4153 if (!isUndefOrEqual(Mask[i], i))
4154 return false;
4156 return true;
4157 }
4159 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4160 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4161 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4162 if (!VT.is128BitVector())
4163 return false;
4165 unsigned NumElems = VT.getVectorNumElements();
4167 if (NumElems != 2 && NumElems != 4)
4168 return false;
4170 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4171 if (!isUndefOrEqual(Mask[i], i))
4172 return false;
4174 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4175 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4176 return false;
4178 return true;
4179 }
4181 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4182 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4183 /// i. e: If all but one element come from the same vector.
4184 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4185 // TODO: Deal with AVX's VINSERTPS
4186 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4187 return false;
4189 unsigned CorrectPosV1 = 0;
4190 unsigned CorrectPosV2 = 0;
4191 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4192 if (Mask[i] == -1) {
4193 ++CorrectPosV1;
4194 ++CorrectPosV2;
4195 continue;
4196 }
4198 if (Mask[i] == i)
4199 ++CorrectPosV1;
4200 else if (Mask[i] == i + 4)
4201 ++CorrectPosV2;
4202 }
4204 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4205 // We have 3 elements (undefs count as elements from any vector) from one
4206 // vector, and one from another.
4207 return true;
4209 return false;
4210 }
4212 //
4213 // Some special combinations that can be optimized.
4214 //
4215 static
4216 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4217 SelectionDAG &DAG) {
4218 MVT VT = SVOp->getSimpleValueType(0);
4219 SDLoc dl(SVOp);
4221 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4222 return SDValue();
4224 ArrayRef<int> Mask = SVOp->getMask();
4226 // These are the special masks that may be optimized.
4227 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4228 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4229 bool MatchEvenMask = true;
4230 bool MatchOddMask = true;
4231 for (int i=0; i<8; ++i) {
4232 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4233 MatchEvenMask = false;
4234 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4235 MatchOddMask = false;
4236 }
4238 if (!MatchEvenMask && !MatchOddMask)
4239 return SDValue();
4241 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4243 SDValue Op0 = SVOp->getOperand(0);
4244 SDValue Op1 = SVOp->getOperand(1);
4246 if (MatchEvenMask) {
4247 // Shift the second operand right to 32 bits.
4248 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4249 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4250 } else {
4251 // Shift the first operand left to 32 bits.
4252 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4253 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4254 }
4255 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4256 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4257 }
4259 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4260 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4261 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4262 bool HasInt256, bool V2IsSplat = false) {
4264 assert(VT.getSizeInBits() >= 128 &&
4265 "Unsupported vector type for unpckl");
4267 unsigned NumElts = VT.getVectorNumElements();
4268 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4269 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4270 return false;
4272 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4273 "Unsupported vector type for unpckh");
4275 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4276 unsigned NumLanes = VT.getSizeInBits()/128;
4277 unsigned NumLaneElts = NumElts/NumLanes;
4279 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4280 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4281 int BitI = Mask[l+i];
4282 int BitI1 = Mask[l+i+1];
4283 if (!isUndefOrEqual(BitI, j))
4284 return false;
4285 if (V2IsSplat) {
4286 if (!isUndefOrEqual(BitI1, NumElts))
4287 return false;
4288 } else {
4289 if (!isUndefOrEqual(BitI1, j + NumElts))
4290 return false;
4291 }
4292 }
4293 }
4295 return true;
4296 }
4298 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4299 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4300 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4301 bool HasInt256, bool V2IsSplat = false) {
4302 assert(VT.getSizeInBits() >= 128 &&
4303 "Unsupported vector type for unpckh");
4305 unsigned NumElts = VT.getVectorNumElements();
4306 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4307 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4308 return false;
4310 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4311 "Unsupported vector type for unpckh");
4313 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4314 unsigned NumLanes = VT.getSizeInBits()/128;
4315 unsigned NumLaneElts = NumElts/NumLanes;
4317 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4318 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4319 int BitI = Mask[l+i];
4320 int BitI1 = Mask[l+i+1];
4321 if (!isUndefOrEqual(BitI, j))
4322 return false;
4323 if (V2IsSplat) {
4324 if (isUndefOrEqual(BitI1, NumElts))
4325 return false;
4326 } else {
4327 if (!isUndefOrEqual(BitI1, j+NumElts))
4328 return false;
4329 }
4330 }
4331 }
4332 return true;
4333 }
4335 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4336 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4337 /// <0, 0, 1, 1>
4338 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4339 unsigned NumElts = VT.getVectorNumElements();
4340 bool Is256BitVec = VT.is256BitVector();
4342 if (VT.is512BitVector())
4343 return false;
4344 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4345 "Unsupported vector type for unpckh");
4347 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4348 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4349 return false;
4351 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4352 // FIXME: Need a better way to get rid of this, there's no latency difference
4353 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4354 // the former later. We should also remove the "_undef" special mask.
4355 if (NumElts == 4 && Is256BitVec)
4356 return false;
4358 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4359 // independently on 128-bit lanes.
4360 unsigned NumLanes = VT.getSizeInBits()/128;
4361 unsigned NumLaneElts = NumElts/NumLanes;
4363 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4364 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4365 int BitI = Mask[l+i];
4366 int BitI1 = Mask[l+i+1];
4368 if (!isUndefOrEqual(BitI, j))
4369 return false;
4370 if (!isUndefOrEqual(BitI1, j))
4371 return false;
4372 }
4373 }
4375 return true;
4376 }
4378 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4379 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4380 /// <2, 2, 3, 3>
4381 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4382 unsigned NumElts = VT.getVectorNumElements();
4384 if (VT.is512BitVector())
4385 return false;
4387 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4388 "Unsupported vector type for unpckh");
4390 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4391 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4392 return false;
4394 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4395 // independently on 128-bit lanes.
4396 unsigned NumLanes = VT.getSizeInBits()/128;
4397 unsigned NumLaneElts = NumElts/NumLanes;
4399 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4400 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4401 int BitI = Mask[l+i];
4402 int BitI1 = Mask[l+i+1];
4403 if (!isUndefOrEqual(BitI, j))
4404 return false;
4405 if (!isUndefOrEqual(BitI1, j))
4406 return false;
4407 }
4408 }
4409 return true;
4410 }
4412 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4413 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4414 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4415 if (!VT.is512BitVector())
4416 return false;
4418 unsigned NumElts = VT.getVectorNumElements();
4419 unsigned HalfSize = NumElts/2;
4420 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4421 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4422 *Imm = 1;
4423 return true;
4424 }
4425 }
4426 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4427 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4428 *Imm = 0;
4429 return true;
4430 }
4431 }
4432 return false;
4433 }
4435 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4436 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4437 /// MOVSD, and MOVD, i.e. setting the lowest element.
4438 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4439 if (VT.getVectorElementType().getSizeInBits() < 32)
4440 return false;
4441 if (!VT.is128BitVector())
4442 return false;
4444 unsigned NumElts = VT.getVectorNumElements();
4446 if (!isUndefOrEqual(Mask[0], NumElts))
4447 return false;
4449 for (unsigned i = 1; i != NumElts; ++i)
4450 if (!isUndefOrEqual(Mask[i], i))
4451 return false;
4453 return true;
4454 }
4456 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4457 /// as permutations between 128-bit chunks or halves. As an example: this
4458 /// shuffle bellow:
4459 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4460 /// The first half comes from the second half of V1 and the second half from the
4461 /// the second half of V2.
4462 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4463 if (!HasFp256 || !VT.is256BitVector())
4464 return false;
4466 // The shuffle result is divided into half A and half B. In total the two
4467 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4468 // B must come from C, D, E or F.
4469 unsigned HalfSize = VT.getVectorNumElements()/2;
4470 bool MatchA = false, MatchB = false;
4472 // Check if A comes from one of C, D, E, F.
4473 for (unsigned Half = 0; Half != 4; ++Half) {
4474 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4475 MatchA = true;
4476 break;
4477 }
4478 }
4480 // Check if B comes from one of C, D, E, F.
4481 for (unsigned Half = 0; Half != 4; ++Half) {
4482 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4483 MatchB = true;
4484 break;
4485 }
4486 }
4488 return MatchA && MatchB;
4489 }
4491 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4492 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4493 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4494 MVT VT = SVOp->getSimpleValueType(0);
4496 unsigned HalfSize = VT.getVectorNumElements()/2;
4498 unsigned FstHalf = 0, SndHalf = 0;
4499 for (unsigned i = 0; i < HalfSize; ++i) {
4500 if (SVOp->getMaskElt(i) > 0) {
4501 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4502 break;
4503 }
4504 }
4505 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4506 if (SVOp->getMaskElt(i) > 0) {
4507 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4508 break;
4509 }
4510 }
4512 return (FstHalf | (SndHalf << 4));
4513 }
4515 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4516 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4517 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4518 if (EltSize < 32)
4519 return false;
4521 unsigned NumElts = VT.getVectorNumElements();
4522 Imm8 = 0;
4523 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4524 for (unsigned i = 0; i != NumElts; ++i) {
4525 if (Mask[i] < 0)
4526 continue;
4527 Imm8 |= Mask[i] << (i*2);
4528 }
4529 return true;
4530 }
4532 unsigned LaneSize = 4;
4533 SmallVector<int, 4> MaskVal(LaneSize, -1);
4535 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4536 for (unsigned i = 0; i != LaneSize; ++i) {
4537 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4538 return false;
4539 if (Mask[i+l] < 0)
4540 continue;
4541 if (MaskVal[i] < 0) {
4542 MaskVal[i] = Mask[i+l] - l;
4543 Imm8 |= MaskVal[i] << (i*2);
4544 continue;
4545 }
4546 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4547 return false;
4548 }
4549 }
4550 return true;
4551 }
4553 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4554 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4555 /// Note that VPERMIL mask matching is different depending whether theunderlying
4556 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4557 /// to the same elements of the low, but to the higher half of the source.
4558 /// In VPERMILPD the two lanes could be shuffled independently of each other
4559 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4560 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4561 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4562 if (VT.getSizeInBits() < 256 || EltSize < 32)
4563 return false;
4564 bool symetricMaskRequired = (EltSize == 32);
4565 unsigned NumElts = VT.getVectorNumElements();
4567 unsigned NumLanes = VT.getSizeInBits()/128;
4568 unsigned LaneSize = NumElts/NumLanes;
4569 // 2 or 4 elements in one lane
4571 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4572 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4573 for (unsigned i = 0; i != LaneSize; ++i) {
4574 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4575 return false;
4576 if (symetricMaskRequired) {
4577 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4578 ExpectedMaskVal[i] = Mask[i+l] - l;
4579 continue;
4580 }
4581 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4582 return false;
4583 }
4584 }
4585 }
4586 return true;
4587 }
4589 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4590 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4591 /// element of vector 2 and the other elements to come from vector 1 in order.
4592 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4593 bool V2IsSplat = false, bool V2IsUndef = false) {
4594 if (!VT.is128BitVector())
4595 return false;
4597 unsigned NumOps = VT.getVectorNumElements();
4598 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4599 return false;
4601 if (!isUndefOrEqual(Mask[0], 0))
4602 return false;
4604 for (unsigned i = 1; i != NumOps; ++i)
4605 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4606 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4607 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4608 return false;
4610 return true;
4611 }
4613 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4614 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4615 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4616 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4617 const X86Subtarget *Subtarget) {
4618 if (!Subtarget->hasSSE3())
4619 return false;
4621 unsigned NumElems = VT.getVectorNumElements();
4623 if ((VT.is128BitVector() && NumElems != 4) ||
4624 (VT.is256BitVector() && NumElems != 8) ||
4625 (VT.is512BitVector() && NumElems != 16))
4626 return false;
4628 // "i+1" is the value the indexed mask element must have
4629 for (unsigned i = 0; i != NumElems; i += 2)
4630 if (!isUndefOrEqual(Mask[i], i+1) ||
4631 !isUndefOrEqual(Mask[i+1], i+1))
4632 return false;
4634 return true;
4635 }
4637 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4638 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4639 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4640 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4641 const X86Subtarget *Subtarget) {
4642 if (!Subtarget->hasSSE3())
4643 return false;
4645 unsigned NumElems = VT.getVectorNumElements();
4647 if ((VT.is128BitVector() && NumElems != 4) ||
4648 (VT.is256BitVector() && NumElems != 8) ||
4649 (VT.is512BitVector() && NumElems != 16))
4650 return false;
4652 // "i" is the value the indexed mask element must have
4653 for (unsigned i = 0; i != NumElems; i += 2)
4654 if (!isUndefOrEqual(Mask[i], i) ||
4655 !isUndefOrEqual(Mask[i+1], i))
4656 return false;
4658 return true;
4659 }
4661 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4662 /// specifies a shuffle of elements that is suitable for input to 256-bit
4663 /// version of MOVDDUP.
4664 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4665 if (!HasFp256 || !VT.is256BitVector())
4666 return false;
4668 unsigned NumElts = VT.getVectorNumElements();
4669 if (NumElts != 4)
4670 return false;
4672 for (unsigned i = 0; i != NumElts/2; ++i)
4673 if (!isUndefOrEqual(Mask[i], 0))
4674 return false;
4675 for (unsigned i = NumElts/2; i != NumElts; ++i)
4676 if (!isUndefOrEqual(Mask[i], NumElts/2))
4677 return false;
4678 return true;
4679 }
4681 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4682 /// specifies a shuffle of elements that is suitable for input to 128-bit
4683 /// version of MOVDDUP.
4684 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4685 if (!VT.is128BitVector())
4686 return false;
4688 unsigned e = VT.getVectorNumElements() / 2;
4689 for (unsigned i = 0; i != e; ++i)
4690 if (!isUndefOrEqual(Mask[i], i))
4691 return false;
4692 for (unsigned i = 0; i != e; ++i)
4693 if (!isUndefOrEqual(Mask[e+i], i))
4694 return false;
4695 return true;
4696 }
4698 /// isVEXTRACTIndex - Return true if the specified
4699 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4700 /// suitable for instruction that extract 128 or 256 bit vectors
4701 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4702 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4703 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4704 return false;
4706 // The index should be aligned on a vecWidth-bit boundary.
4707 uint64_t Index =
4708 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4710 MVT VT = N->getSimpleValueType(0);
4711 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4712 bool Result = (Index * ElSize) % vecWidth == 0;
4714 return Result;
4715 }
4717 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4718 /// operand specifies a subvector insert that is suitable for input to
4719 /// insertion of 128 or 256-bit subvectors
4720 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4721 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4722 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4723 return false;
4724 // The index should be aligned on a vecWidth-bit boundary.
4725 uint64_t Index =
4726 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4728 MVT VT = N->getSimpleValueType(0);
4729 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4730 bool Result = (Index * ElSize) % vecWidth == 0;
4732 return Result;
4733 }
4735 bool X86::isVINSERT128Index(SDNode *N) {
4736 return isVINSERTIndex(N, 128);
4737 }
4739 bool X86::isVINSERT256Index(SDNode *N) {
4740 return isVINSERTIndex(N, 256);
4741 }
4743 bool X86::isVEXTRACT128Index(SDNode *N) {
4744 return isVEXTRACTIndex(N, 128);
4745 }
4747 bool X86::isVEXTRACT256Index(SDNode *N) {
4748 return isVEXTRACTIndex(N, 256);
4749 }
4751 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4752 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4753 /// Handles 128-bit and 256-bit.
4754 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4755 MVT VT = N->getSimpleValueType(0);
4757 assert((VT.getSizeInBits() >= 128) &&
4758 "Unsupported vector type for PSHUF/SHUFP");
4760 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4761 // independently on 128-bit lanes.
4762 unsigned NumElts = VT.getVectorNumElements();
4763 unsigned NumLanes = VT.getSizeInBits()/128;
4764 unsigned NumLaneElts = NumElts/NumLanes;
4766 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4767 "Only supports 2, 4 or 8 elements per lane");
4769 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4770 unsigned Mask = 0;
4771 for (unsigned i = 0; i != NumElts; ++i) {
4772 int Elt = N->getMaskElt(i);
4773 if (Elt < 0) continue;
4774 Elt &= NumLaneElts - 1;
4775 unsigned ShAmt = (i << Shift) % 8;
4776 Mask |= Elt << ShAmt;
4777 }
4779 return Mask;
4780 }
4782 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4783 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4784 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4785 MVT VT = N->getSimpleValueType(0);
4787 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4788 "Unsupported vector type for PSHUFHW");
4790 unsigned NumElts = VT.getVectorNumElements();
4792 unsigned Mask = 0;
4793 for (unsigned l = 0; l != NumElts; l += 8) {
4794 // 8 nodes per lane, but we only care about the last 4.
4795 for (unsigned i = 0; i < 4; ++i) {
4796 int Elt = N->getMaskElt(l+i+4);
4797 if (Elt < 0) continue;
4798 Elt &= 0x3; // only 2-bits.
4799 Mask |= Elt << (i * 2);
4800 }
4801 }
4803 return Mask;
4804 }
4806 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4807 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4808 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4809 MVT VT = N->getSimpleValueType(0);
4811 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4812 "Unsupported vector type for PSHUFHW");
4814 unsigned NumElts = VT.getVectorNumElements();
4816 unsigned Mask = 0;
4817 for (unsigned l = 0; l != NumElts; l += 8) {
4818 // 8 nodes per lane, but we only care about the first 4.
4819 for (unsigned i = 0; i < 4; ++i) {
4820 int Elt = N->getMaskElt(l+i);
4821 if (Elt < 0) continue;
4822 Elt &= 0x3; // only 2-bits
4823 Mask |= Elt << (i * 2);
4824 }
4825 }
4827 return Mask;
4828 }
4830 /// \brief Return the appropriate immediate to shuffle the specified
4831 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4832 /// VALIGN (if Interlane is true) instructions.
4833 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4834 bool InterLane) {
4835 MVT VT = SVOp->getSimpleValueType(0);
4836 unsigned EltSize = InterLane ? 1 :
4837 VT.getVectorElementType().getSizeInBits() >> 3;
4839 unsigned NumElts = VT.getVectorNumElements();
4840 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4841 unsigned NumLaneElts = NumElts/NumLanes;
4843 int Val = 0;
4844 unsigned i;
4845 for (i = 0; i != NumElts; ++i) {
4846 Val = SVOp->getMaskElt(i);
4847 if (Val >= 0)
4848 break;
4849 }
4850 if (Val >= (int)NumElts)
4851 Val -= NumElts - NumLaneElts;
4853 assert(Val - i > 0 && "PALIGNR imm should be positive");
4854 return (Val - i) * EltSize;
4855 }
4857 /// \brief Return the appropriate immediate to shuffle the specified
4858 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4859 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4860 return getShuffleAlignrImmediate(SVOp, false);
4861 }
4863 /// \brief Return the appropriate immediate to shuffle the specified
4864 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4865 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4866 return getShuffleAlignrImmediate(SVOp, true);
4867 }
4870 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4871 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4872 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4873 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4875 uint64_t Index =
4876 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4878 MVT VecVT = N->getOperand(0).getSimpleValueType();
4879 MVT ElVT = VecVT.getVectorElementType();
4881 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4882 return Index / NumElemsPerChunk;
4883 }
4885 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4886 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4887 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4888 llvm_unreachable("Illegal insert subvector for VINSERT");
4890 uint64_t Index =
4891 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4893 MVT VecVT = N->getSimpleValueType(0);
4894 MVT ElVT = VecVT.getVectorElementType();
4896 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4897 return Index / NumElemsPerChunk;
4898 }
4900 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4901 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4902 /// and VINSERTI128 instructions.
4903 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4904 return getExtractVEXTRACTImmediate(N, 128);
4905 }
4907 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4908 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4909 /// and VINSERTI64x4 instructions.
4910 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4911 return getExtractVEXTRACTImmediate(N, 256);
4912 }
4914 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4915 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4916 /// and VINSERTI128 instructions.
4917 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4918 return getInsertVINSERTImmediate(N, 128);
4919 }
4921 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4922 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4923 /// and VINSERTI64x4 instructions.
4924 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4925 return getInsertVINSERTImmediate(N, 256);
4926 }
4928 /// isZero - Returns true if Elt is a constant integer zero
4929 static bool isZero(SDValue V) {
4930 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4931 return C && C->isNullValue();
4932 }
4934 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4935 /// constant +0.0.
4936 bool X86::isZeroNode(SDValue Elt) {
4937 if (isZero(Elt))
4938 return true;
4939 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4940 return CFP->getValueAPF().isPosZero();
4941 return false;
4942 }
4944 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4945 /// match movhlps. The lower half elements should come from upper half of
4946 /// V1 (and in order), and the upper half elements should come from the upper
4947 /// half of V2 (and in order).
4948 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4949 if (!VT.is128BitVector())
4950 return false;
4951 if (VT.getVectorNumElements() != 4)
4952 return false;
4953 for (unsigned i = 0, e = 2; i != e; ++i)
4954 if (!isUndefOrEqual(Mask[i], i+2))
4955 return false;
4956 for (unsigned i = 2; i != 4; ++i)
4957 if (!isUndefOrEqual(Mask[i], i+4))
4958 return false;
4959 return true;
4960 }
4962 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4963 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4964 /// required.
4965 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4966 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4967 return false;
4968 N = N->getOperand(0).getNode();
4969 if (!ISD::isNON_EXTLoad(N))
4970 return false;
4971 if (LD)
4972 *LD = cast<LoadSDNode>(N);
4973 return true;
4974 }
4976 // Test whether the given value is a vector value which will be legalized
4977 // into a load.
4978 static bool WillBeConstantPoolLoad(SDNode *N) {
4979 if (N->getOpcode() != ISD::BUILD_VECTOR)
4980 return false;
4982 // Check for any non-constant elements.
4983 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4984 switch (N->getOperand(i).getNode()->getOpcode()) {
4985 case ISD::UNDEF:
4986 case ISD::ConstantFP:
4987 case ISD::Constant:
4988 break;
4989 default:
4990 return false;
4991 }
4993 // Vectors of all-zeros and all-ones are materialized with special
4994 // instructions rather than being loaded.
4995 return !ISD::isBuildVectorAllZeros(N) &&
4996 !ISD::isBuildVectorAllOnes(N);
4997 }
4999 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
5000 /// match movlp{s|d}. The lower half elements should come from lower half of
5001 /// V1 (and in order), and the upper half elements should come from the upper
5002 /// half of V2 (and in order). And since V1 will become the source of the
5003 /// MOVLP, it must be either a vector load or a scalar load to vector.
5004 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5005 ArrayRef<int> Mask, MVT VT) {
5006 if (!VT.is128BitVector())
5007 return false;
5009 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5010 return false;
5011 // Is V2 is a vector load, don't do this transformation. We will try to use
5012 // load folding shufps op.
5013 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5014 return false;
5016 unsigned NumElems = VT.getVectorNumElements();
5018 if (NumElems != 2 && NumElems != 4)
5019 return false;
5020 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5021 if (!isUndefOrEqual(Mask[i], i))
5022 return false;
5023 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5024 if (!isUndefOrEqual(Mask[i], i+NumElems))
5025 return false;
5026 return true;
5027 }
5029 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5030 /// to an zero vector.
5031 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5032 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5033 SDValue V1 = N->getOperand(0);
5034 SDValue V2 = N->getOperand(1);
5035 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5036 for (unsigned i = 0; i != NumElems; ++i) {
5037 int Idx = N->getMaskElt(i);
5038 if (Idx >= (int)NumElems) {
5039 unsigned Opc = V2.getOpcode();
5040 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5041 continue;
5042 if (Opc != ISD::BUILD_VECTOR ||
5043 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5044 return false;
5045 } else if (Idx >= 0) {
5046 unsigned Opc = V1.getOpcode();
5047 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5048 continue;
5049 if (Opc != ISD::BUILD_VECTOR ||
5050 !X86::isZeroNode(V1.getOperand(Idx)))
5051 return false;
5052 }
5053 }
5054 return true;
5055 }
5057 /// getZeroVector - Returns a vector of specified type with all zero elements.
5058 ///
5059 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5060 SelectionDAG &DAG, SDLoc dl) {
5061 assert(VT.isVector() && "Expected a vector type");
5063 // Always build SSE zero vectors as <4 x i32> bitcasted
5064 // to their dest type. This ensures they get CSE'd.
5065 SDValue Vec;
5066 if (VT.is128BitVector()) { // SSE
5067 if (Subtarget->hasSSE2()) { // SSE2
5068 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5069 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5070 } else { // SSE1
5071 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5072 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5073 }
5074 } else if (VT.is256BitVector()) { // AVX
5075 if (Subtarget->hasInt256()) { // AVX2
5076 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5077 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5078 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5079 } else {
5080 // 256-bit logic and arithmetic instructions in AVX are all
5081 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5082 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5083 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5084 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5085 }
5086 } else if (VT.is512BitVector()) { // AVX-512
5087 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5088 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5089 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5090 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5091 } else if (VT.getScalarType() == MVT::i1) {
5092 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5093 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5094 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5095 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5096 } else
5097 llvm_unreachable("Unexpected vector type");
5099 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5100 }
5102 /// getOnesVector - Returns a vector of specified type with all bits set.
5103 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5104 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5105 /// Then bitcast to their original type, ensuring they get CSE'd.
5106 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5107 SDLoc dl) {
5108 assert(VT.isVector() && "Expected a vector type");
5110 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
5111 SDValue Vec;
5112 if (VT.is256BitVector()) {
5113 if (HasInt256) { // AVX2
5114 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5115 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5116 } else { // AVX
5117 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5118 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5119 }
5120 } else if (VT.is128BitVector()) {
5121 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5122 } else
5123 llvm_unreachable("Unexpected vector type");
5125 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5126 }
5128 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5129 /// that point to V2 points to its first element.
5130 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5131 for (unsigned i = 0; i != NumElems; ++i) {
5132 if (Mask[i] > (int)NumElems) {
5133 Mask[i] = NumElems;
5134 }
5135 }
5136 }
5138 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5139 /// operation of specified width.
5140 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5141 SDValue V2) {
5142 unsigned NumElems = VT.getVectorNumElements();
5143 SmallVector<int, 8> Mask;
5144 Mask.push_back(NumElems);
5145 for (unsigned i = 1; i != NumElems; ++i)
5146 Mask.push_back(i);
5147 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5148 }
5150 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5151 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5152 SDValue V2) {
5153 unsigned NumElems = VT.getVectorNumElements();
5154 SmallVector<int, 8> Mask;
5155 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5156 Mask.push_back(i);
5157 Mask.push_back(i + NumElems);
5158 }
5159 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5160 }
5162 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5163 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5164 SDValue V2) {
5165 unsigned NumElems = VT.getVectorNumElements();
5166 SmallVector<int, 8> Mask;
5167 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5168 Mask.push_back(i + Half);
5169 Mask.push_back(i + NumElems + Half);
5170 }
5171 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5172 }
5174 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5175 // a generic shuffle instruction because the target has no such instructions.
5176 // Generate shuffles which repeat i16 and i8 several times until they can be
5177 // represented by v4f32 and then be manipulated by target suported shuffles.
5178 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5179 MVT VT = V.getSimpleValueType();
5180 int NumElems = VT.getVectorNumElements();
5181 SDLoc dl(V);
5183 while (NumElems > 4) {
5184 if (EltNo < NumElems/2) {
5185 V = getUnpackl(DAG, dl, VT, V, V);
5186 } else {
5187 V = getUnpackh(DAG, dl, VT, V, V);
5188 EltNo -= NumElems/2;
5189 }
5190 NumElems >>= 1;
5191 }
5192 return V;
5193 }
5195 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5196 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5197 MVT VT = V.getSimpleValueType();
5198 SDLoc dl(V);
5200 if (VT.is128BitVector()) {
5201 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5202 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5203 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5204 &SplatMask[0]);
5205 } else if (VT.is256BitVector()) {
5206 // To use VPERMILPS to splat scalars, the second half of indicies must
5207 // refer to the higher part, which is a duplication of the lower one,
5208 // because VPERMILPS can only handle in-lane permutations.
5209 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5210 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5212 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5213 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5214 &SplatMask[0]);
5215 } else
5216 llvm_unreachable("Vector size not supported");
5218 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5219 }
5221 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5222 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5223 MVT SrcVT = SV->getSimpleValueType(0);
5224 SDValue V1 = SV->getOperand(0);
5225 SDLoc dl(SV);
5227 int EltNo = SV->getSplatIndex();
5228 int NumElems = SrcVT.getVectorNumElements();
5229 bool Is256BitVec = SrcVT.is256BitVector();
5231 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5232 "Unknown how to promote splat for type");
5234 // Extract the 128-bit part containing the splat element and update
5235 // the splat element index when it refers to the higher register.
5236 if (Is256BitVec) {
5237 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5238 if (EltNo >= NumElems/2)
5239 EltNo -= NumElems/2;
5240 }
5242 // All i16 and i8 vector types can't be used directly by a generic shuffle
5243 // instruction because the target has no such instruction. Generate shuffles
5244 // which repeat i16 and i8 several times until they fit in i32, and then can
5245 // be manipulated by target suported shuffles.
5246 MVT EltVT = SrcVT.getVectorElementType();
5247 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5248 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5250 // Recreate the 256-bit vector and place the same 128-bit vector
5251 // into the low and high part. This is necessary because we want
5252 // to use VPERM* to shuffle the vectors
5253 if (Is256BitVec) {
5254 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5255 }
5257 return getLegalSplat(DAG, V1, EltNo);
5258 }
5260 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5261 /// vector of zero or undef vector. This produces a shuffle where the low
5262 /// element of V2 is swizzled into the zero/undef vector, landing at element
5263 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5264 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5265 bool IsZero,
5266 const X86Subtarget *Subtarget,
5267 SelectionDAG &DAG) {
5268 MVT VT = V2.getSimpleValueType();
5269 SDValue V1 = IsZero
5270 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5271 unsigned NumElems = VT.getVectorNumElements();
5272 SmallVector<int, 16> MaskVec;
5273 for (unsigned i = 0; i != NumElems; ++i)
5274 // If this is the insertion idx, put the low elt of V2 here.
5275 MaskVec.push_back(i == Idx ? NumElems : i);
5276 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5277 }
5279 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5280 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5281 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5282 /// shuffles which use a single input multiple times, and in those cases it will
5283 /// adjust the mask to only have indices within that single input.
5284 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5285 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5286 unsigned NumElems = VT.getVectorNumElements();
5287 SDValue ImmN;
5289 IsUnary = false;
5290 bool IsFakeUnary = false;
5291 switch(N->getOpcode()) {
5292 case X86ISD::BLENDI:
5293 ImmN = N->getOperand(N->getNumOperands()-1);
5294 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5295 break;
5296 case X86ISD::SHUFP:
5297 ImmN = N->getOperand(N->getNumOperands()-1);
5298 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5299 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5300 break;
5301 case X86ISD::UNPCKH:
5302 DecodeUNPCKHMask(VT, Mask);
5303 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5304 break;
5305 case X86ISD::UNPCKL:
5306 DecodeUNPCKLMask(VT, Mask);
5307 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5308 break;
5309 case X86ISD::MOVHLPS:
5310 DecodeMOVHLPSMask(NumElems, Mask);
5311 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5312 break;
5313 case X86ISD::MOVLHPS:
5314 DecodeMOVLHPSMask(NumElems, Mask);
5315 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5316 break;
5317 case X86ISD::PALIGNR:
5318 ImmN = N->getOperand(N->getNumOperands()-1);
5319 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5320 break;
5321 case X86ISD::PSHUFD:
5322 case X86ISD::VPERMILPI:
5323 ImmN = N->getOperand(N->getNumOperands()-1);
5324 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5325 IsUnary = true;
5326 break;
5327 case X86ISD::PSHUFHW:
5328 ImmN = N->getOperand(N->getNumOperands()-1);
5329 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5330 IsUnary = true;
5331 break;
5332 case X86ISD::PSHUFLW:
5333 ImmN = N->getOperand(N->getNumOperands()-1);
5334 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5335 IsUnary = true;
5336 break;
5337 case X86ISD::PSHUFB: {
5338 IsUnary = true;
5339 SDValue MaskNode = N->getOperand(1);
5340 while (MaskNode->getOpcode() == ISD::BITCAST)
5341 MaskNode = MaskNode->getOperand(0);
5343 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5344 // If we have a build-vector, then things are easy.
5345 EVT VT = MaskNode.getValueType();
5346 assert(VT.isVector() &&
5347 "Can't produce a non-vector with a build_vector!");
5348 if (!VT.isInteger())
5349 return false;
5351 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5353 SmallVector<uint64_t, 32> RawMask;
5354 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5355 SDValue Op = MaskNode->getOperand(i);
5356 if (Op->getOpcode() == ISD::UNDEF) {
5357 RawMask.push_back((uint64_t)SM_SentinelUndef);
5358 continue;
5359 }
5360 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
5361 if (!CN)
5362 return false;
5363 APInt MaskElement = CN->getAPIntValue();
5365 // We now have to decode the element which could be any integer size and
5366 // extract each byte of it.
5367 for (int j = 0; j < NumBytesPerElement; ++j) {
5368 // Note that this is x86 and so always little endian: the low byte is
5369 // the first byte of the mask.
5370 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5371 MaskElement = MaskElement.lshr(8);
5372 }
5373 }
5374 DecodePSHUFBMask(RawMask, Mask);
5375 break;
5376 }
5378 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5379 if (!MaskLoad)
5380 return false;
5382 SDValue Ptr = MaskLoad->getBasePtr();
5383 if (Ptr->getOpcode() == X86ISD::Wrapper)
5384 Ptr = Ptr->getOperand(0);
5386 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5387 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5388 return false;
5390 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
5391 // FIXME: Support AVX-512 here.
5392 Type *Ty = C->getType();
5393 if (!Ty->isVectorTy() || (Ty->getVectorNumElements() != 16 &&
5394 Ty->getVectorNumElements() != 32))
5395 return false;
5397 DecodePSHUFBMask(C, Mask);
5398 break;
5399 }
5401 return false;
5402 }
5403 case X86ISD::VPERMI:
5404 ImmN = N->getOperand(N->getNumOperands()-1);
5405 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5406 IsUnary = true;
5407 break;
5408 case X86ISD::MOVSS:
5409 case X86ISD::MOVSD: {
5410 // The index 0 always comes from the first element of the second source,
5411 // this is why MOVSS and MOVSD are used in the first place. The other
5412 // elements come from the other positions of the first source vector
5413 Mask.push_back(NumElems);
5414 for (unsigned i = 1; i != NumElems; ++i) {
5415 Mask.push_back(i);
5416 }
5417 break;
5418 }
5419 case X86ISD::VPERM2X128:
5420 ImmN = N->getOperand(N->getNumOperands()-1);
5421 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5422 if (Mask.empty()) return false;
5423 break;
5424 case X86ISD::MOVSLDUP:
5425 DecodeMOVSLDUPMask(VT, Mask);
5426 break;
5427 case X86ISD::MOVSHDUP:
5428 DecodeMOVSHDUPMask(VT, Mask);
5429 break;
5430 case X86ISD::MOVDDUP:
5431 case X86ISD::MOVLHPD:
5432 case X86ISD::MOVLPD:
5433 case X86ISD::MOVLPS:
5434 // Not yet implemented
5435 return false;
5436 default: llvm_unreachable("unknown target shuffle node");
5437 }
5439 // If we have a fake unary shuffle, the shuffle mask is spread across two
5440 // inputs that are actually the same node. Re-map the mask to always point
5441 // into the first input.
5442 if (IsFakeUnary)
5443 for (int &M : Mask)
5444 if (M >= (int)Mask.size())
5445 M -= Mask.size();
5447 return true;
5448 }
5450 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5451 /// element of the result of the vector shuffle.
5452 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5453 unsigned Depth) {
5454 if (Depth == 6)
5455 return SDValue(); // Limit search depth.
5457 SDValue V = SDValue(N, 0);
5458 EVT VT = V.getValueType();
5459 unsigned Opcode = V.getOpcode();
5461 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5462 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5463 int Elt = SV->getMaskElt(Index);
5465 if (Elt < 0)
5466 return DAG.getUNDEF(VT.getVectorElementType());
5468 unsigned NumElems = VT.getVectorNumElements();
5469 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5470 : SV->getOperand(1);
5471 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5472 }
5474 // Recurse into target specific vector shuffles to find scalars.
5475 if (isTargetShuffle(Opcode)) {
5476 MVT ShufVT = V.getSimpleValueType();
5477 unsigned NumElems = ShufVT.getVectorNumElements();
5478 SmallVector<int, 16> ShuffleMask;
5479 bool IsUnary;
5481 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5482 return SDValue();
5484 int Elt = ShuffleMask[Index];
5485 if (Elt < 0)
5486 return DAG.getUNDEF(ShufVT.getVectorElementType());
5488 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5489 : N->getOperand(1);
5490 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5491 Depth+1);
5492 }
5494 // Actual nodes that may contain scalar elements
5495 if (Opcode == ISD::BITCAST) {
5496 V = V.getOperand(0);
5497 EVT SrcVT = V.getValueType();
5498 unsigned NumElems = VT.getVectorNumElements();
5500 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5501 return SDValue();
5502 }
5504 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5505 return (Index == 0) ? V.getOperand(0)
5506 : DAG.getUNDEF(VT.getVectorElementType());
5508 if (V.getOpcode() == ISD::BUILD_VECTOR)
5509 return V.getOperand(Index);
5511 return SDValue();
5512 }
5514 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5515 /// shuffle operation which come from a consecutively from a zero. The
5516 /// search can start in two different directions, from left or right.
5517 /// We count undefs as zeros until PreferredNum is reached.
5518 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5519 unsigned NumElems, bool ZerosFromLeft,
5520 SelectionDAG &DAG,
5521 unsigned PreferredNum = -1U) {
5522 unsigned NumZeros = 0;
5523 for (unsigned i = 0; i != NumElems; ++i) {
5524 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5525 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5526 if (!Elt.getNode())
5527 break;
5529 if (X86::isZeroNode(Elt))
5530 ++NumZeros;
5531 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5532 NumZeros = std::min(NumZeros + 1, PreferredNum);
5533 else
5534 break;
5535 }
5537 return NumZeros;
5538 }
5540 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5541 /// correspond consecutively to elements from one of the vector operands,
5542 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5543 static
5544 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5545 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5546 unsigned NumElems, unsigned &OpNum) {
5547 bool SeenV1 = false;
5548 bool SeenV2 = false;
5550 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5551 int Idx = SVOp->getMaskElt(i);
5552 // Ignore undef indicies
5553 if (Idx < 0)
5554 continue;
5556 if (Idx < (int)NumElems)
5557 SeenV1 = true;
5558 else
5559 SeenV2 = true;
5561 // Only accept consecutive elements from the same vector
5562 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5563 return false;
5564 }
5566 OpNum = SeenV1 ? 0 : 1;
5567 return true;
5568 }
5570 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5571 /// logical left shift of a vector.
5572 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5573 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5574 unsigned NumElems =
5575 SVOp->getSimpleValueType(0).getVectorNumElements();
5576 unsigned NumZeros = getNumOfConsecutiveZeros(
5577 SVOp, NumElems, false /* check zeros from right */, DAG,
5578 SVOp->getMaskElt(0));
5579 unsigned OpSrc;
5581 if (!NumZeros)
5582 return false;
5584 // Considering the elements in the mask that are not consecutive zeros,
5585 // check if they consecutively come from only one of the source vectors.
5586 //
5587 // V1 = {X, A, B, C} 0
5588 // \ \ \ /
5589 // vector_shuffle V1, V2 <1, 2, 3, X>
5590 //
5591 if (!isShuffleMaskConsecutive(SVOp,
5592 0, // Mask Start Index
5593 NumElems-NumZeros, // Mask End Index(exclusive)
5594 NumZeros, // Where to start looking in the src vector
5595 NumElems, // Number of elements in vector
5596 OpSrc)) // Which source operand ?
5597 return false;
5599 isLeft = false;
5600 ShAmt = NumZeros;
5601 ShVal = SVOp->getOperand(OpSrc);
5602 return true;
5603 }
5605 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5606 /// logical left shift of a vector.
5607 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5608 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5609 unsigned NumElems =
5610 SVOp->getSimpleValueType(0).getVectorNumElements();
5611 unsigned NumZeros = getNumOfConsecutiveZeros(
5612 SVOp, NumElems, true /* check zeros from left */, DAG,
5613 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5614 unsigned OpSrc;
5616 if (!NumZeros)
5617 return false;
5619 // Considering the elements in the mask that are not consecutive zeros,
5620 // check if they consecutively come from only one of the source vectors.
5621 //
5622 // 0 { A, B, X, X } = V2
5623 // / \ / /
5624 // vector_shuffle V1, V2 <X, X, 4, 5>
5625 //
5626 if (!isShuffleMaskConsecutive(SVOp,
5627 NumZeros, // Mask Start Index
5628 NumElems, // Mask End Index(exclusive)
5629 0, // Where to start looking in the src vector
5630 NumElems, // Number of elements in vector
5631 OpSrc)) // Which source operand ?
5632 return false;
5634 isLeft = true;
5635 ShAmt = NumZeros;
5636 ShVal = SVOp->getOperand(OpSrc);
5637 return true;
5638 }
5640 /// isVectorShift - Returns true if the shuffle can be implemented as a
5641 /// logical left or right shift of a vector.
5642 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5643 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5644 // Although the logic below support any bitwidth size, there are no
5645 // shift instructions which handle more than 128-bit vectors.
5646 if (!SVOp->getSimpleValueType(0).is128BitVector())
5647 return false;
5649 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5650 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5651 return true;
5653 return false;
5654 }
5656 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5657 ///
5658 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5659 unsigned NumNonZero, unsigned NumZero,
5660 SelectionDAG &DAG,
5661 const X86Subtarget* Subtarget,
5662 const TargetLowering &TLI) {
5663 if (NumNonZero > 8)
5664 return SDValue();
5666 SDLoc dl(Op);
5667 SDValue V;
5668 bool First = true;
5669 for (unsigned i = 0; i < 16; ++i) {
5670 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5671 if (ThisIsNonZero && First) {
5672 if (NumZero)
5673 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5674 else
5675 V = DAG.getUNDEF(MVT::v8i16);
5676 First = false;
5677 }
5679 if ((i & 1) != 0) {
5680 SDValue ThisElt, LastElt;
5681 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5682 if (LastIsNonZero) {
5683 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5684 MVT::i16, Op.getOperand(i-1));
5685 }
5686 if (ThisIsNonZero) {
5687 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5688 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5689 ThisElt, DAG.getConstant(8, MVT::i8));
5690 if (LastIsNonZero)
5691 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5692 } else
5693 ThisElt = LastElt;
5695 if (ThisElt.getNode())
5696 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5697 DAG.getIntPtrConstant(i/2));
5698 }
5699 }
5701 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5702 }
5704 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5705 ///
5706 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5707 unsigned NumNonZero, unsigned NumZero,
5708 SelectionDAG &DAG,
5709 const X86Subtarget* Subtarget,
5710 const TargetLowering &TLI) {
5711 if (NumNonZero > 4)
5712 return SDValue();
5714 SDLoc dl(Op);
5715 SDValue V;
5716 bool First = true;
5717 for (unsigned i = 0; i < 8; ++i) {
5718 bool isNonZero = (NonZeros & (1 << i)) != 0;
5719 if (isNonZero) {
5720 if (First) {
5721 if (NumZero)
5722 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5723 else
5724 V = DAG.getUNDEF(MVT::v8i16);
5725 First = false;
5726 }
5727 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5728 MVT::v8i16, V, Op.getOperand(i),
5729 DAG.getIntPtrConstant(i));
5730 }
5731 }
5733 return V;
5734 }
5736 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5737 static SDValue LowerBuildVectorv4x32(SDValue Op, unsigned NumElems,
5738 unsigned NonZeros, unsigned NumNonZero,
5739 unsigned NumZero, SelectionDAG &DAG,
5740 const X86Subtarget *Subtarget,
5741 const TargetLowering &TLI) {
5742 // We know there's at least one non-zero element
5743 unsigned FirstNonZeroIdx = 0;
5744 SDValue FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5745 while (FirstNonZero.getOpcode() == ISD::UNDEF ||
5746 X86::isZeroNode(FirstNonZero)) {
5747 ++FirstNonZeroIdx;
5748 FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5749 }
5751 if (FirstNonZero.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5752 !isa<ConstantSDNode>(FirstNonZero.getOperand(1)))
5753 return SDValue();
5755 SDValue V = FirstNonZero.getOperand(0);
5756 MVT VVT = V.getSimpleValueType();
5757 if (!Subtarget->hasSSE41() || (VVT != MVT::v4f32 && VVT != MVT::v4i32))
5758 return SDValue();
5760 unsigned FirstNonZeroDst =
5761 cast<ConstantSDNode>(FirstNonZero.getOperand(1))->getZExtValue();
5762 unsigned CorrectIdx = FirstNonZeroDst == FirstNonZeroIdx;
5763 unsigned IncorrectIdx = CorrectIdx ? -1U : FirstNonZeroIdx;
5764 unsigned IncorrectDst = CorrectIdx ? -1U : FirstNonZeroDst;
5766 for (unsigned Idx = FirstNonZeroIdx + 1; Idx < NumElems; ++Idx) {
5767 SDValue Elem = Op.getOperand(Idx);
5768 if (Elem.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elem))
5769 continue;
5771 // TODO: What else can be here? Deal with it.
5772 if (Elem.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5773 return SDValue();
5775 // TODO: Some optimizations are still possible here
5776 // ex: Getting one element from a vector, and the rest from another.
5777 if (Elem.getOperand(0) != V)
5778 return SDValue();
5780 unsigned Dst = cast<ConstantSDNode>(Elem.getOperand(1))->getZExtValue();
5781 if (Dst == Idx)
5782 ++CorrectIdx;
5783 else if (IncorrectIdx == -1U) {
5784 IncorrectIdx = Idx;
5785 IncorrectDst = Dst;
5786 } else
5787 // There was already one element with an incorrect index.
5788 // We can't optimize this case to an insertps.
5789 return SDValue();
5790 }
5792 if (NumNonZero == CorrectIdx || NumNonZero == CorrectIdx + 1) {
5793 SDLoc dl(Op);
5794 EVT VT = Op.getSimpleValueType();
5795 unsigned ElementMoveMask = 0;
5796 if (IncorrectIdx == -1U)
5797 ElementMoveMask = FirstNonZeroIdx << 6 | FirstNonZeroIdx << 4;
5798 else
5799 ElementMoveMask = IncorrectDst << 6 | IncorrectIdx << 4;
5801 SDValue InsertpsMask =
5802 DAG.getIntPtrConstant(ElementMoveMask | (~NonZeros & 0xf));
5803 return DAG.getNode(X86ISD::INSERTPS, dl, VT, V, V, InsertpsMask);
5804 }
5806 return SDValue();
5807 }
5809 /// getVShift - Return a vector logical shift node.
5810 ///
5811 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5812 unsigned NumBits, SelectionDAG &DAG,
5813 const TargetLowering &TLI, SDLoc dl) {
5814 assert(VT.is128BitVector() && "Unknown type for VShift");
5815 EVT ShVT = MVT::v2i64;
5816 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5817 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5818 return DAG.getNode(ISD::BITCAST, dl, VT,
5819 DAG.getNode(Opc, dl, ShVT, SrcOp,
5820 DAG.getConstant(NumBits,
5821 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5822 }
5824 static SDValue
5825 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5827 // Check if the scalar load can be widened into a vector load. And if
5828 // the address is "base + cst" see if the cst can be "absorbed" into
5829 // the shuffle mask.
5830 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5831 SDValue Ptr = LD->getBasePtr();
5832 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5833 return SDValue();
5834 EVT PVT = LD->getValueType(0);
5835 if (PVT != MVT::i32 && PVT != MVT::f32)
5836 return SDValue();
5838 int FI = -1;
5839 int64_t Offset = 0;
5840 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5841 FI = FINode->getIndex();
5842 Offset = 0;
5843 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5844 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5845 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5846 Offset = Ptr.getConstantOperandVal(1);
5847 Ptr = Ptr.getOperand(0);
5848 } else {
5849 return SDValue();
5850 }
5852 // FIXME: 256-bit vector instructions don't require a strict alignment,
5853 // improve this code to support it better.
5854 unsigned RequiredAlign = VT.getSizeInBits()/8;
5855 SDValue Chain = LD->getChain();
5856 // Make sure the stack object alignment is at least 16 or 32.
5857 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5858 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5859 if (MFI->isFixedObjectIndex(FI)) {
5860 // Can't change the alignment. FIXME: It's possible to compute
5861 // the exact stack offset and reference FI + adjust offset instead.
5862 // If someone *really* cares about this. That's the way to implement it.
5863 return SDValue();
5864 } else {
5865 MFI->setObjectAlignment(FI, RequiredAlign);
5866 }
5867 }
5869 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5870 // Ptr + (Offset & ~15).
5871 if (Offset < 0)
5872 return SDValue();
5873 if ((Offset % RequiredAlign) & 3)
5874 return SDValue();
5875 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5876 if (StartOffset)
5877 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5878 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5880 int EltNo = (Offset - StartOffset) >> 2;
5881 unsigned NumElems = VT.getVectorNumElements();
5883 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5884 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5885 LD->getPointerInfo().getWithOffset(StartOffset),
5886 false, false, false, 0);
5888 SmallVector<int, 8> Mask;
5889 for (unsigned i = 0; i != NumElems; ++i)
5890 Mask.push_back(EltNo);
5892 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5893 }
5895 return SDValue();
5896 }
5898 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5899 /// vector of type 'VT', see if the elements can be replaced by a single large
5900 /// load which has the same value as a build_vector whose operands are 'elts'.
5901 ///
5902 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5903 ///
5904 /// FIXME: we'd also like to handle the case where the last elements are zero
5905 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5906 /// There's even a handy isZeroNode for that purpose.
5907 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5908 SDLoc &DL, SelectionDAG &DAG,
5909 bool isAfterLegalize) {
5910 EVT EltVT = VT.getVectorElementType();
5911 unsigned NumElems = Elts.size();
5913 LoadSDNode *LDBase = nullptr;
5914 unsigned LastLoadedElt = -1U;
5916 // For each element in the initializer, see if we've found a load or an undef.
5917 // If we don't find an initial load element, or later load elements are
5918 // non-consecutive, bail out.
5919 for (unsigned i = 0; i < NumElems; ++i) {
5920 SDValue Elt = Elts[i];
5922 if (!Elt.getNode() ||
5923 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5924 return SDValue();
5925 if (!LDBase) {
5926 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5927 return SDValue();
5928 LDBase = cast<LoadSDNode>(Elt.getNode());
5929 LastLoadedElt = i;
5930 continue;
5931 }
5932 if (Elt.getOpcode() == ISD::UNDEF)
5933 continue;
5935 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5936 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5937 return SDValue();
5938 LastLoadedElt = i;
5939 }
5941 // If we have found an entire vector of loads and undefs, then return a large
5942 // load of the entire vector width starting at the base pointer. If we found
5943 // consecutive loads for the low half, generate a vzext_load node.
5944 if (LastLoadedElt == NumElems - 1) {
5946 if (isAfterLegalize &&
5947 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5948 return SDValue();
5950 SDValue NewLd = SDValue();
5952 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5953 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5954 LDBase->getPointerInfo(),
5955 LDBase->isVolatile(), LDBase->isNonTemporal(),
5956 LDBase->isInvariant(), 0);
5957 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5958 LDBase->getPointerInfo(),
5959 LDBase->isVolatile(), LDBase->isNonTemporal(),
5960 LDBase->isInvariant(), LDBase->getAlignment());
5962 if (LDBase->hasAnyUseOfValue(1)) {
5963 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5964 SDValue(LDBase, 1),
5965 SDValue(NewLd.getNode(), 1));
5966 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5967 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5968 SDValue(NewLd.getNode(), 1));
5969 }
5971 return NewLd;
5972 }
5973 if (NumElems == 4 && LastLoadedElt == 1 &&
5974 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5975 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5976 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5977 SDValue ResNode =
5978 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5979 LDBase->getPointerInfo(),
5980 LDBase->getAlignment(),
5981 false/*isVolatile*/, true/*ReadMem*/,
5982 false/*WriteMem*/);
5984 // Make sure the newly-created LOAD is in the same position as LDBase in
5985 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5986 // update uses of LDBase's output chain to use the TokenFactor.
5987 if (LDBase->hasAnyUseOfValue(1)) {
5988 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5989 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5990 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5991 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5992 SDValue(ResNode.getNode(), 1));
5993 }
5995 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5996 }
5997 return SDValue();
5998 }
6000 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
6001 /// to generate a splat value for the following cases:
6002 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
6003 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
6004 /// a scalar load, or a constant.
6005 /// The VBROADCAST node is returned when a pattern is found,
6006 /// or SDValue() otherwise.
6007 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
6008 SelectionDAG &DAG) {
6009 // VBROADCAST requires AVX.
6010 // TODO: Splats could be generated for non-AVX CPUs using SSE
6011 // instructions, but there's less potential gain for only 128-bit vectors.
6012 if (!Subtarget->hasAVX())
6013 return SDValue();
6015 MVT VT = Op.getSimpleValueType();
6016 SDLoc dl(Op);
6018 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6019 "Unsupported vector type for broadcast.");
6021 SDValue Ld;
6022 bool ConstSplatVal;
6024 switch (Op.getOpcode()) {
6025 default:
6026 // Unknown pattern found.
6027 return SDValue();
6029 case ISD::BUILD_VECTOR: {
6030 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6031 BitVector UndefElements;
6032 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6034 // We need a splat of a single value to use broadcast, and it doesn't
6035 // make any sense if the value is only in one element of the vector.
6036 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6037 return SDValue();
6039 Ld = Splat;
6040 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6041 Ld.getOpcode() == ISD::ConstantFP);
6043 // Make sure that all of the users of a non-constant load are from the
6044 // BUILD_VECTOR node.
6045 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6046 return SDValue();
6047 break;
6048 }
6050 case ISD::VECTOR_SHUFFLE: {
6051 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6053 // Shuffles must have a splat mask where the first element is
6054 // broadcasted.
6055 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6056 return SDValue();
6058 SDValue Sc = Op.getOperand(0);
6059 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6060 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6062 if (!Subtarget->hasInt256())
6063 return SDValue();
6065 // Use the register form of the broadcast instruction available on AVX2.
6066 if (VT.getSizeInBits() >= 256)
6067 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6068 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6069 }
6071 Ld = Sc.getOperand(0);
6072 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6073 Ld.getOpcode() == ISD::ConstantFP);
6075 // The scalar_to_vector node and the suspected
6076 // load node must have exactly one user.
6077 // Constants may have multiple users.
6079 // AVX-512 has register version of the broadcast
6080 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6081 Ld.getValueType().getSizeInBits() >= 32;
6082 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6083 !hasRegVer))
6084 return SDValue();
6085 break;
6086 }
6087 }
6089 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6090 bool IsGE256 = (VT.getSizeInBits() >= 256);
6092 // When optimizing for size, generate up to 5 extra bytes for a broadcast
6093 // instruction to save 8 or more bytes of constant pool data.
6094 // TODO: If multiple splats are generated to load the same constant,
6095 // it may be detrimental to overall size. There needs to be a way to detect
6096 // that condition to know if this is truly a size win.
6097 const Function *F = DAG.getMachineFunction().getFunction();
6098 bool OptForSize = F->getAttributes().
6099 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6101 // Handle broadcasting a single constant scalar from the constant pool
6102 // into a vector.
6103 // On Sandybridge (no AVX2), it is still better to load a constant vector
6104 // from the constant pool and not to broadcast it from a scalar.
6105 // But override that restriction when optimizing for size.
6106 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
6107 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
6108 EVT CVT = Ld.getValueType();
6109 assert(!CVT.isVector() && "Must not broadcast a vector type");
6111 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
6112 // For size optimization, also splat v2f64 and v2i64, and for size opt
6113 // with AVX2, also splat i8 and i16.
6114 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
6115 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6116 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
6117 const Constant *C = nullptr;
6118 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6119 C = CI->getConstantIntValue();
6120 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6121 C = CF->getConstantFPValue();
6123 assert(C && "Invalid constant type");
6125 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6126 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6127 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6128 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6129 MachinePointerInfo::getConstantPool(),
6130 false, false, false, Alignment);
6132 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6133 }
6134 }
6136 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6138 // Handle AVX2 in-register broadcasts.
6139 if (!IsLoad && Subtarget->hasInt256() &&
6140 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6141 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6143 // The scalar source must be a normal load.
6144 if (!IsLoad)
6145 return SDValue();
6147 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
6148 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6150 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6151 // double since there is no vbroadcastsd xmm
6152 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6153 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6154 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6155 }
6157 // Unsupported broadcast.
6158 return SDValue();
6159 }
6161 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6162 /// underlying vector and index.
6163 ///
6164 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6165 /// index.
6166 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6167 SDValue ExtIdx) {
6168 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6169 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6170 return Idx;
6172 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6173 // lowered this:
6174 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6175 // to:
6176 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6177 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6178 // undef)
6179 // Constant<0>)
6180 // In this case the vector is the extract_subvector expression and the index
6181 // is 2, as specified by the shuffle.
6182 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6183 SDValue ShuffleVec = SVOp->getOperand(0);
6184 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6185 assert(ShuffleVecVT.getVectorElementType() ==
6186 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6188 int ShuffleIdx = SVOp->getMaskElt(Idx);
6189 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6190 ExtractedFromVec = ShuffleVec;
6191 return ShuffleIdx;
6192 }
6193 return Idx;
6194 }
6196 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6197 MVT VT = Op.getSimpleValueType();
6199 // Skip if insert_vec_elt is not supported.
6200 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6201 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6202 return SDValue();
6204 SDLoc DL(Op);
6205 unsigned NumElems = Op.getNumOperands();
6207 SDValue VecIn1;
6208 SDValue VecIn2;
6209 SmallVector<unsigned, 4> InsertIndices;
6210 SmallVector<int, 8> Mask(NumElems, -1);
6212 for (unsigned i = 0; i != NumElems; ++i) {
6213 unsigned Opc = Op.getOperand(i).getOpcode();
6215 if (Opc == ISD::UNDEF)
6216 continue;
6218 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6219 // Quit if more than 1 elements need inserting.
6220 if (InsertIndices.size() > 1)
6221 return SDValue();
6223 InsertIndices.push_back(i);
6224 continue;
6225 }
6227 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6228 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6229 // Quit if non-constant index.
6230 if (!isa<ConstantSDNode>(ExtIdx))
6231 return SDValue();
6232 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6234 // Quit if extracted from vector of different type.
6235 if (ExtractedFromVec.getValueType() != VT)
6236 return SDValue();
6238 if (!VecIn1.getNode())
6239 VecIn1 = ExtractedFromVec;
6240 else if (VecIn1 != ExtractedFromVec) {
6241 if (!VecIn2.getNode())
6242 VecIn2 = ExtractedFromVec;
6243 else if (VecIn2 != ExtractedFromVec)
6244 // Quit if more than 2 vectors to shuffle
6245 return SDValue();
6246 }
6248 if (ExtractedFromVec == VecIn1)
6249 Mask[i] = Idx;
6250 else if (ExtractedFromVec == VecIn2)
6251 Mask[i] = Idx + NumElems;
6252 }
6254 if (!VecIn1.getNode())
6255 return SDValue();
6257 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6258 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6259 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6260 unsigned Idx = InsertIndices[i];
6261 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6262 DAG.getIntPtrConstant(Idx));
6263 }
6265 return NV;
6266 }
6268 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6269 SDValue
6270 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6272 MVT VT = Op.getSimpleValueType();
6273 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6274 "Unexpected type in LowerBUILD_VECTORvXi1!");
6276 SDLoc dl(Op);
6277 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6278 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6279 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6280 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6281 }
6283 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6284 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6285 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6286 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6287 }
6289 bool AllContants = true;
6290 uint64_t Immediate = 0;
6291 int NonConstIdx = -1;
6292 bool IsSplat = true;
6293 unsigned NumNonConsts = 0;
6294 unsigned NumConsts = 0;
6295 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6296 SDValue In = Op.getOperand(idx);
6297 if (In.getOpcode() == ISD::UNDEF)
6298 continue;
6299 if (!isa<ConstantSDNode>(In)) {
6300 AllContants = false;
6301 NonConstIdx = idx;
6302 NumNonConsts++;
6303 }
6304 else {
6305 NumConsts++;
6306 if (cast<ConstantSDNode>(In)->getZExtValue())
6307 Immediate |= (1ULL << idx);
6308 }
6309 if (In != Op.getOperand(0))
6310 IsSplat = false;
6311 }
6313 if (AllContants) {
6314 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6315 DAG.getConstant(Immediate, MVT::i16));
6316 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6317 DAG.getIntPtrConstant(0));
6318 }
6320 if (NumNonConsts == 1 && NonConstIdx != 0) {
6321 SDValue DstVec;
6322 if (NumConsts) {
6323 SDValue VecAsImm = DAG.getConstant(Immediate,
6324 MVT::getIntegerVT(VT.getSizeInBits()));
6325 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6326 }
6327 else
6328 DstVec = DAG.getUNDEF(VT);
6329 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6330 Op.getOperand(NonConstIdx),
6331 DAG.getIntPtrConstant(NonConstIdx));
6332 }
6333 if (!IsSplat && (NonConstIdx != 0))
6334 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6335 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6336 SDValue Select;
6337 if (IsSplat)
6338 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6339 DAG.getConstant(-1, SelectVT),
6340 DAG.getConstant(0, SelectVT));
6341 else
6342 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6343 DAG.getConstant((Immediate | 1), SelectVT),
6344 DAG.getConstant(Immediate, SelectVT));
6345 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6346 }
6348 /// \brief Return true if \p N implements a horizontal binop and return the
6349 /// operands for the horizontal binop into V0 and V1.
6350 ///
6351 /// This is a helper function of PerformBUILD_VECTORCombine.
6352 /// This function checks that the build_vector \p N in input implements a
6353 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6354 /// operation to match.
6355 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6356 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6357 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6358 /// arithmetic sub.
6359 ///
6360 /// This function only analyzes elements of \p N whose indices are
6361 /// in range [BaseIdx, LastIdx).
6362 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6363 SelectionDAG &DAG,
6364 unsigned BaseIdx, unsigned LastIdx,
6365 SDValue &V0, SDValue &V1) {
6366 EVT VT = N->getValueType(0);
6368 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6369 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6370 "Invalid Vector in input!");
6372 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6373 bool CanFold = true;
6374 unsigned ExpectedVExtractIdx = BaseIdx;
6375 unsigned NumElts = LastIdx - BaseIdx;
6376 V0 = DAG.getUNDEF(VT);
6377 V1 = DAG.getUNDEF(VT);
6379 // Check if N implements a horizontal binop.
6380 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6381 SDValue Op = N->getOperand(i + BaseIdx);
6383 // Skip UNDEFs.
6384 if (Op->getOpcode() == ISD::UNDEF) {
6385 // Update the expected vector extract index.
6386 if (i * 2 == NumElts)
6387 ExpectedVExtractIdx = BaseIdx;
6388 ExpectedVExtractIdx += 2;
6389 continue;
6390 }
6392 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6394 if (!CanFold)
6395 break;
6397 SDValue Op0 = Op.getOperand(0);
6398 SDValue Op1 = Op.getOperand(1);
6400 // Try to match the following pattern:
6401 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6402 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6403 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6404 Op0.getOperand(0) == Op1.getOperand(0) &&
6405 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6406 isa<ConstantSDNode>(Op1.getOperand(1)));
6407 if (!CanFold)
6408 break;
6410 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6411 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6413 if (i * 2 < NumElts) {
6414 if (V0.getOpcode() == ISD::UNDEF)
6415 V0 = Op0.getOperand(0);
6416 } else {
6417 if (V1.getOpcode() == ISD::UNDEF)
6418 V1 = Op0.getOperand(0);
6419 if (i * 2 == NumElts)
6420 ExpectedVExtractIdx = BaseIdx;
6421 }
6423 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6424 if (I0 == ExpectedVExtractIdx)
6425 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6426 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6427 // Try to match the following dag sequence:
6428 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6429 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6430 } else
6431 CanFold = false;
6433 ExpectedVExtractIdx += 2;
6434 }
6436 return CanFold;
6437 }
6439 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6440 /// a concat_vector.
6441 ///
6442 /// This is a helper function of PerformBUILD_VECTORCombine.
6443 /// This function expects two 256-bit vectors called V0 and V1.
6444 /// At first, each vector is split into two separate 128-bit vectors.
6445 /// Then, the resulting 128-bit vectors are used to implement two
6446 /// horizontal binary operations.
6447 ///
6448 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6449 ///
6450 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6451 /// the two new horizontal binop.
6452 /// When Mode is set, the first horizontal binop dag node would take as input
6453 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6454 /// horizontal binop dag node would take as input the lower 128-bit of V1
6455 /// and the upper 128-bit of V1.
6456 /// Example:
6457 /// HADD V0_LO, V0_HI
6458 /// HADD V1_LO, V1_HI
6459 ///
6460 /// Otherwise, the first horizontal binop dag node takes as input the lower
6461 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6462 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6463 /// Example:
6464 /// HADD V0_LO, V1_LO
6465 /// HADD V0_HI, V1_HI
6466 ///
6467 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6468 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6469 /// the upper 128-bits of the result.
6470 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6471 SDLoc DL, SelectionDAG &DAG,
6472 unsigned X86Opcode, bool Mode,
6473 bool isUndefLO, bool isUndefHI) {
6474 EVT VT = V0.getValueType();
6475 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6476 "Invalid nodes in input!");
6478 unsigned NumElts = VT.getVectorNumElements();
6479 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6480 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6481 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6482 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6483 EVT NewVT = V0_LO.getValueType();
6485 SDValue LO = DAG.getUNDEF(NewVT);
6486 SDValue HI = DAG.getUNDEF(NewVT);
6488 if (Mode) {
6489 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6490 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6491 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6492 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6493 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6494 } else {
6495 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6496 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6497 V1_LO->getOpcode() != ISD::UNDEF))
6498 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6500 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6501 V1_HI->getOpcode() != ISD::UNDEF))
6502 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6503 }
6505 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6506 }
6508 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6509 /// sequence of 'vadd + vsub + blendi'.
6510 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6511 const X86Subtarget *Subtarget) {
6512 SDLoc DL(BV);
6513 EVT VT = BV->getValueType(0);
6514 unsigned NumElts = VT.getVectorNumElements();
6515 SDValue InVec0 = DAG.getUNDEF(VT);
6516 SDValue InVec1 = DAG.getUNDEF(VT);
6518 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6519 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6521 // Odd-numbered elements in the input build vector are obtained from
6522 // adding two integer/float elements.
6523 // Even-numbered elements in the input build vector are obtained from
6524 // subtracting two integer/float elements.
6525 unsigned ExpectedOpcode = ISD::FSUB;
6526 unsigned NextExpectedOpcode = ISD::FADD;
6527 bool AddFound = false;
6528 bool SubFound = false;
6530 for (unsigned i = 0, e = NumElts; i != e; i++) {
6531 SDValue Op = BV->getOperand(i);
6533 // Skip 'undef' values.
6534 unsigned Opcode = Op.getOpcode();
6535 if (Opcode == ISD::UNDEF) {
6536 std::swap(ExpectedOpcode, NextExpectedOpcode);
6537 continue;
6538 }
6540 // Early exit if we found an unexpected opcode.
6541 if (Opcode != ExpectedOpcode)
6542 return SDValue();
6544 SDValue Op0 = Op.getOperand(0);
6545 SDValue Op1 = Op.getOperand(1);
6547 // Try to match the following pattern:
6548 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6549 // Early exit if we cannot match that sequence.
6550 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6551 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6552 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6553 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6554 Op0.getOperand(1) != Op1.getOperand(1))
6555 return SDValue();
6557 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6558 if (I0 != i)
6559 return SDValue();
6561 // We found a valid add/sub node. Update the information accordingly.
6562 if (i & 1)
6563 AddFound = true;
6564 else
6565 SubFound = true;
6567 // Update InVec0 and InVec1.
6568 if (InVec0.getOpcode() == ISD::UNDEF)
6569 InVec0 = Op0.getOperand(0);
6570 if (InVec1.getOpcode() == ISD::UNDEF)
6571 InVec1 = Op1.getOperand(0);
6573 // Make sure that operands in input to each add/sub node always
6574 // come from a same pair of vectors.
6575 if (InVec0 != Op0.getOperand(0)) {
6576 if (ExpectedOpcode == ISD::FSUB)
6577 return SDValue();
6579 // FADD is commutable. Try to commute the operands
6580 // and then test again.
6581 std::swap(Op0, Op1);
6582 if (InVec0 != Op0.getOperand(0))
6583 return SDValue();
6584 }
6586 if (InVec1 != Op1.getOperand(0))
6587 return SDValue();
6589 // Update the pair of expected opcodes.
6590 std::swap(ExpectedOpcode, NextExpectedOpcode);
6591 }
6593 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6594 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6595 InVec1.getOpcode() != ISD::UNDEF)
6596 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6598 return SDValue();
6599 }
6601 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6602 const X86Subtarget *Subtarget) {
6603 SDLoc DL(N);
6604 EVT VT = N->getValueType(0);
6605 unsigned NumElts = VT.getVectorNumElements();
6606 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6607 SDValue InVec0, InVec1;
6609 // Try to match an ADDSUB.
6610 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6611 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6612 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6613 if (Value.getNode())
6614 return Value;
6615 }
6617 // Try to match horizontal ADD/SUB.
6618 unsigned NumUndefsLO = 0;
6619 unsigned NumUndefsHI = 0;
6620 unsigned Half = NumElts/2;
6622 // Count the number of UNDEF operands in the build_vector in input.
6623 for (unsigned i = 0, e = Half; i != e; ++i)
6624 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6625 NumUndefsLO++;
6627 for (unsigned i = Half, e = NumElts; i != e; ++i)
6628 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6629 NumUndefsHI++;
6631 // Early exit if this is either a build_vector of all UNDEFs or all the
6632 // operands but one are UNDEF.
6633 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6634 return SDValue();
6636 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6637 // Try to match an SSE3 float HADD/HSUB.
6638 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6639 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6641 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6642 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6643 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6644 // Try to match an SSSE3 integer HADD/HSUB.
6645 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6646 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6648 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6649 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6650 }
6652 if (!Subtarget->hasAVX())
6653 return SDValue();
6655 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6656 // Try to match an AVX horizontal add/sub of packed single/double
6657 // precision floating point values from 256-bit vectors.
6658 SDValue InVec2, InVec3;
6659 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6660 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6661 ((InVec0.getOpcode() == ISD::UNDEF ||
6662 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6663 ((InVec1.getOpcode() == ISD::UNDEF ||
6664 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6665 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6667 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6668 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6669 ((InVec0.getOpcode() == ISD::UNDEF ||
6670 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6671 ((InVec1.getOpcode() == ISD::UNDEF ||
6672 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6673 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6674 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6675 // Try to match an AVX2 horizontal add/sub of signed integers.
6676 SDValue InVec2, InVec3;
6677 unsigned X86Opcode;
6678 bool CanFold = true;
6680 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6681 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6682 ((InVec0.getOpcode() == ISD::UNDEF ||
6683 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6684 ((InVec1.getOpcode() == ISD::UNDEF ||
6685 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6686 X86Opcode = X86ISD::HADD;
6687 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6688 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6689 ((InVec0.getOpcode() == ISD::UNDEF ||
6690 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6691 ((InVec1.getOpcode() == ISD::UNDEF ||
6692 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6693 X86Opcode = X86ISD::HSUB;
6694 else
6695 CanFold = false;
6697 if (CanFold) {
6698 // Fold this build_vector into a single horizontal add/sub.
6699 // Do this only if the target has AVX2.
6700 if (Subtarget->hasAVX2())
6701 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6703 // Do not try to expand this build_vector into a pair of horizontal
6704 // add/sub if we can emit a pair of scalar add/sub.
6705 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6706 return SDValue();
6708 // Convert this build_vector into a pair of horizontal binop followed by
6709 // a concat vector.
6710 bool isUndefLO = NumUndefsLO == Half;
6711 bool isUndefHI = NumUndefsHI == Half;
6712 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6713 isUndefLO, isUndefHI);
6714 }
6715 }
6717 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6718 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6719 unsigned X86Opcode;
6720 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6721 X86Opcode = X86ISD::HADD;
6722 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6723 X86Opcode = X86ISD::HSUB;
6724 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6725 X86Opcode = X86ISD::FHADD;
6726 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6727 X86Opcode = X86ISD::FHSUB;
6728 else
6729 return SDValue();
6731 // Don't try to expand this build_vector into a pair of horizontal add/sub
6732 // if we can simply emit a pair of scalar add/sub.
6733 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6734 return SDValue();
6736 // Convert this build_vector into two horizontal add/sub followed by
6737 // a concat vector.
6738 bool isUndefLO = NumUndefsLO == Half;
6739 bool isUndefHI = NumUndefsHI == Half;
6740 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6741 isUndefLO, isUndefHI);
6742 }
6744 return SDValue();
6745 }
6747 SDValue
6748 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6749 SDLoc dl(Op);
6751 MVT VT = Op.getSimpleValueType();
6752 MVT ExtVT = VT.getVectorElementType();
6753 unsigned NumElems = Op.getNumOperands();
6755 // Generate vectors for predicate vectors.
6756 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6757 return LowerBUILD_VECTORvXi1(Op, DAG);
6759 // Vectors containing all zeros can be matched by pxor and xorps later
6760 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6761 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6762 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6763 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6764 return Op;
6766 return getZeroVector(VT, Subtarget, DAG, dl);
6767 }
6769 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6770 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6771 // vpcmpeqd on 256-bit vectors.
6772 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6773 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6774 return Op;
6776 if (!VT.is512BitVector())
6777 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6778 }
6780 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6781 if (Broadcast.getNode())
6782 return Broadcast;
6784 unsigned EVTBits = ExtVT.getSizeInBits();
6786 unsigned NumZero = 0;
6787 unsigned NumNonZero = 0;
6788 unsigned NonZeros = 0;
6789 bool IsAllConstants = true;
6790 SmallSet<SDValue, 8> Values;
6791 for (unsigned i = 0; i < NumElems; ++i) {
6792 SDValue Elt = Op.getOperand(i);
6793 if (Elt.getOpcode() == ISD::UNDEF)
6794 continue;
6795 Values.insert(Elt);
6796 if (Elt.getOpcode() != ISD::Constant &&
6797 Elt.getOpcode() != ISD::ConstantFP)
6798 IsAllConstants = false;
6799 if (X86::isZeroNode(Elt))
6800 NumZero++;
6801 else {
6802 NonZeros |= (1 << i);
6803 NumNonZero++;
6804 }
6805 }
6807 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6808 if (NumNonZero == 0)
6809 return DAG.getUNDEF(VT);
6811 // Special case for single non-zero, non-undef, element.
6812 if (NumNonZero == 1) {
6813 unsigned Idx = countTrailingZeros(NonZeros);
6814 SDValue Item = Op.getOperand(Idx);
6816 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6817 // the value are obviously zero, truncate the value to i32 and do the
6818 // insertion that way. Only do this if the value is non-constant or if the
6819 // value is a constant being inserted into element 0. It is cheaper to do
6820 // a constant pool load than it is to do a movd + shuffle.
6821 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6822 (!IsAllConstants || Idx == 0)) {
6823 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6824 // Handle SSE only.
6825 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6826 EVT VecVT = MVT::v4i32;
6827 unsigned VecElts = 4;
6829 // Truncate the value (which may itself be a constant) to i32, and
6830 // convert it to a vector with movd (S2V+shuffle to zero extend).
6831 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6832 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6834 // If using the new shuffle lowering, just directly insert this.
6835 if (ExperimentalVectorShuffleLowering)
6836 return DAG.getNode(
6837 ISD::BITCAST, dl, VT,
6838 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6840 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6842 // Now we have our 32-bit value zero extended in the low element of
6843 // a vector. If Idx != 0, swizzle it into place.
6844 if (Idx != 0) {
6845 SmallVector<int, 4> Mask;
6846 Mask.push_back(Idx);
6847 for (unsigned i = 1; i != VecElts; ++i)
6848 Mask.push_back(i);
6849 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6850 &Mask[0]);
6851 }
6852 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6853 }
6854 }
6856 // If we have a constant or non-constant insertion into the low element of
6857 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6858 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6859 // depending on what the source datatype is.
6860 if (Idx == 0) {
6861 if (NumZero == 0)
6862 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6864 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6865 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6866 if (VT.is256BitVector() || VT.is512BitVector()) {
6867 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6868 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6869 Item, DAG.getIntPtrConstant(0));
6870 }
6871 assert(VT.is128BitVector() && "Expected an SSE value type!");
6872 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6873 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6874 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6875 }
6877 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6878 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6879 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6880 if (VT.is256BitVector()) {
6881 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6882 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6883 } else {
6884 assert(VT.is128BitVector() && "Expected an SSE value type!");
6885 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6886 }
6887 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6888 }
6889 }
6891 // Is it a vector logical left shift?
6892 if (NumElems == 2 && Idx == 1 &&
6893 X86::isZeroNode(Op.getOperand(0)) &&
6894 !X86::isZeroNode(Op.getOperand(1))) {
6895 unsigned NumBits = VT.getSizeInBits();
6896 return getVShift(true, VT,
6897 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6898 VT, Op.getOperand(1)),
6899 NumBits/2, DAG, *this, dl);
6900 }
6902 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6903 return SDValue();
6905 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6906 // is a non-constant being inserted into an element other than the low one,
6907 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6908 // movd/movss) to move this into the low element, then shuffle it into
6909 // place.
6910 if (EVTBits == 32) {
6911 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6913 // If using the new shuffle lowering, just directly insert this.
6914 if (ExperimentalVectorShuffleLowering)
6915 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6917 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6918 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6919 SmallVector<int, 8> MaskVec;
6920 for (unsigned i = 0; i != NumElems; ++i)
6921 MaskVec.push_back(i == Idx ? 0 : 1);
6922 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6923 }
6924 }
6926 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6927 if (Values.size() == 1) {
6928 if (EVTBits == 32) {
6929 // Instead of a shuffle like this:
6930 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6931 // Check if it's possible to issue this instead.
6932 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6933 unsigned Idx = countTrailingZeros(NonZeros);
6934 SDValue Item = Op.getOperand(Idx);
6935 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6936 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6937 }
6938 return SDValue();
6939 }
6941 // A vector full of immediates; various special cases are already
6942 // handled, so this is best done with a single constant-pool load.
6943 if (IsAllConstants)
6944 return SDValue();
6946 // For AVX-length vectors, build the individual 128-bit pieces and use
6947 // shuffles to put them in place.
6948 if (VT.is256BitVector() || VT.is512BitVector()) {
6949 SmallVector<SDValue, 64> V;
6950 for (unsigned i = 0; i != NumElems; ++i)
6951 V.push_back(Op.getOperand(i));
6953 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6955 // Build both the lower and upper subvector.
6956 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6957 makeArrayRef(&V[0], NumElems/2));
6958 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6959 makeArrayRef(&V[NumElems / 2], NumElems/2));
6961 // Recreate the wider vector with the lower and upper part.
6962 if (VT.is256BitVector())
6963 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6964 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6965 }
6967 // Let legalizer expand 2-wide build_vectors.
6968 if (EVTBits == 64) {
6969 if (NumNonZero == 1) {
6970 // One half is zero or undef.
6971 unsigned Idx = countTrailingZeros(NonZeros);
6972 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6973 Op.getOperand(Idx));
6974 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6975 }
6976 return SDValue();
6977 }
6979 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6980 if (EVTBits == 8 && NumElems == 16) {
6981 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6982 Subtarget, *this);
6983 if (V.getNode()) return V;
6984 }
6986 if (EVTBits == 16 && NumElems == 8) {
6987 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6988 Subtarget, *this);
6989 if (V.getNode()) return V;
6990 }
6992 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6993 if (EVTBits == 32 && NumElems == 4) {
6994 SDValue V = LowerBuildVectorv4x32(Op, NumElems, NonZeros, NumNonZero,
6995 NumZero, DAG, Subtarget, *this);
6996 if (V.getNode())
6997 return V;
6998 }
7000 // If element VT is == 32 bits, turn it into a number of shuffles.
7001 SmallVector<SDValue, 8> V(NumElems);
7002 if (NumElems == 4 && NumZero > 0) {
7003 for (unsigned i = 0; i < 4; ++i) {
7004 bool isZero = !(NonZeros & (1 << i));
7005 if (isZero)
7006 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
7007 else
7008 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7009 }
7011 for (unsigned i = 0; i < 2; ++i) {
7012 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7013 default: break;
7014 case 0:
7015 V[i] = V[i*2]; // Must be a zero vector.
7016 break;
7017 case 1:
7018 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7019 break;
7020 case 2:
7021 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7022 break;
7023 case 3:
7024 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7025 break;
7026 }
7027 }
7029 bool Reverse1 = (NonZeros & 0x3) == 2;
7030 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7031 int MaskVec[] = {
7032 Reverse1 ? 1 : 0,
7033 Reverse1 ? 0 : 1,
7034 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7035 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7036 };
7037 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7038 }
7040 if (Values.size() > 1 && VT.is128BitVector()) {
7041 // Check for a build vector of consecutive loads.
7042 for (unsigned i = 0; i < NumElems; ++i)
7043 V[i] = Op.getOperand(i);
7045 // Check for elements which are consecutive loads.
7046 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7047 if (LD.getNode())
7048 return LD;
7050 // Check for a build vector from mostly shuffle plus few inserting.
7051 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7052 if (Sh.getNode())
7053 return Sh;
7055 // For SSE 4.1, use insertps to put the high elements into the low element.
7056 if (getSubtarget()->hasSSE41()) {
7057 SDValue Result;
7058 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7059 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7060 else
7061 Result = DAG.getUNDEF(VT);
7063 for (unsigned i = 1; i < NumElems; ++i) {
7064 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7065 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7066 Op.getOperand(i), DAG.getIntPtrConstant(i));
7067 }
7068 return Result;
7069 }
7071 // Otherwise, expand into a number of unpckl*, start by extending each of
7072 // our (non-undef) elements to the full vector width with the element in the
7073 // bottom slot of the vector (which generates no code for SSE).
7074 for (unsigned i = 0; i < NumElems; ++i) {
7075 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7076 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7077 else
7078 V[i] = DAG.getUNDEF(VT);
7079 }
7081 // Next, we iteratively mix elements, e.g. for v4f32:
7082 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7083 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7084 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7085 unsigned EltStride = NumElems >> 1;
7086 while (EltStride != 0) {
7087 for (unsigned i = 0; i < EltStride; ++i) {
7088 // If V[i+EltStride] is undef and this is the first round of mixing,
7089 // then it is safe to just drop this shuffle: V[i] is already in the
7090 // right place, the one element (since it's the first round) being
7091 // inserted as undef can be dropped. This isn't safe for successive
7092 // rounds because they will permute elements within both vectors.
7093 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7094 EltStride == NumElems/2)
7095 continue;
7097 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7098 }
7099 EltStride >>= 1;
7100 }
7101 return V[0];
7102 }
7103 return SDValue();
7104 }
7106 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7107 // to create 256-bit vectors from two other 128-bit ones.
7108 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7109 SDLoc dl(Op);
7110 MVT ResVT = Op.getSimpleValueType();
7112 assert((ResVT.is256BitVector() ||
7113 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7115 SDValue V1 = Op.getOperand(0);
7116 SDValue V2 = Op.getOperand(1);
7117 unsigned NumElems = ResVT.getVectorNumElements();
7118 if(ResVT.is256BitVector())
7119 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7121 if (Op.getNumOperands() == 4) {
7122 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7123 ResVT.getVectorNumElements()/2);
7124 SDValue V3 = Op.getOperand(2);
7125 SDValue V4 = Op.getOperand(3);
7126 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7127 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7128 }
7129 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7130 }
7132 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7133 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7134 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7135 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7136 Op.getNumOperands() == 4)));
7138 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7139 // from two other 128-bit ones.
7141 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7142 return LowerAVXCONCAT_VECTORS(Op, DAG);
7143 }
7146 //===----------------------------------------------------------------------===//
7147 // Vector shuffle lowering
7148 //
7149 // This is an experimental code path for lowering vector shuffles on x86. It is
7150 // designed to handle arbitrary vector shuffles and blends, gracefully
7151 // degrading performance as necessary. It works hard to recognize idiomatic
7152 // shuffles and lower them to optimal instruction patterns without leaving
7153 // a framework that allows reasonably efficient handling of all vector shuffle
7154 // patterns.
7155 //===----------------------------------------------------------------------===//
7157 /// \brief Tiny helper function to identify a no-op mask.
7158 ///
7159 /// This is a somewhat boring predicate function. It checks whether the mask
7160 /// array input, which is assumed to be a single-input shuffle mask of the kind
7161 /// used by the X86 shuffle instructions (not a fully general
7162 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7163 /// in-place shuffle are 'no-op's.
7164 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7165 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7166 if (Mask[i] != -1 && Mask[i] != i)
7167 return false;
7168 return true;
7169 }
7171 /// \brief Helper function to classify a mask as a single-input mask.
7172 ///
7173 /// This isn't a generic single-input test because in the vector shuffle
7174 /// lowering we canonicalize single inputs to be the first input operand. This
7175 /// means we can more quickly test for a single input by only checking whether
7176 /// an input from the second operand exists. We also assume that the size of
7177 /// mask corresponds to the size of the input vectors which isn't true in the
7178 /// fully general case.
7179 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7180 for (int M : Mask)
7181 if (M >= (int)Mask.size())
7182 return false;
7183 return true;
7184 }
7186 /// \brief Test whether there are elements crossing 128-bit lanes in this
7187 /// shuffle mask.
7188 ///
7189 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
7190 /// and we routinely test for these.
7191 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
7192 int LaneSize = 128 / VT.getScalarSizeInBits();
7193 int Size = Mask.size();
7194 for (int i = 0; i < Size; ++i)
7195 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
7196 return true;
7197 return false;
7198 }
7200 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
7201 ///
7202 /// This checks a shuffle mask to see if it is performing the same
7203 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
7204 /// that it is also not lane-crossing. It may however involve a blend from the
7205 /// same lane of a second vector.
7206 ///
7207 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
7208 /// non-trivial to compute in the face of undef lanes. The representation is
7209 /// *not* suitable for use with existing 128-bit shuffles as it will contain
7210 /// entries from both V1 and V2 inputs to the wider mask.
7211 static bool
7212 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
7213 SmallVectorImpl<int> &RepeatedMask) {
7214 int LaneSize = 128 / VT.getScalarSizeInBits();
7215 RepeatedMask.resize(LaneSize, -1);
7216 int Size = Mask.size();
7217 for (int i = 0; i < Size; ++i) {
7218 if (Mask[i] < 0)
7219 continue;
7220 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
7221 // This entry crosses lanes, so there is no way to model this shuffle.
7222 return false;
7224 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
7225 if (RepeatedMask[i % LaneSize] == -1)
7226 // This is the first non-undef entry in this slot of a 128-bit lane.
7227 RepeatedMask[i % LaneSize] =
7228 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
7229 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
7230 // Found a mismatch with the repeated mask.
7231 return false;
7232 }
7233 return true;
7234 }
7236 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7237 // 2013 will allow us to use it as a non-type template parameter.
7238 namespace {
7240 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7241 ///
7242 /// See its documentation for details.
7243 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7244 if (Mask.size() != Args.size())
7245 return false;
7246 for (int i = 0, e = Mask.size(); i < e; ++i) {
7247 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7248 if (Mask[i] != -1 && Mask[i] != *Args[i])
7249 return false;
7250 }
7251 return true;
7252 }
7254 } // namespace
7256 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7257 /// arguments.
7258 ///
7259 /// This is a fast way to test a shuffle mask against a fixed pattern:
7260 ///
7261 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7262 ///
7263 /// It returns true if the mask is exactly as wide as the argument list, and
7264 /// each element of the mask is either -1 (signifying undef) or the value given
7265 /// in the argument.
7266 static const VariadicFunction1<
7267 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7269 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7270 ///
7271 /// This helper function produces an 8-bit shuffle immediate corresponding to
7272 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7273 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7274 /// example.
7275 ///
7276 /// NB: We rely heavily on "undef" masks preserving the input lane.
7277 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7278 SelectionDAG &DAG) {
7279 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7280 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7281 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7282 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7283 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7285 unsigned Imm = 0;
7286 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7287 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7288 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7289 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7290 return DAG.getConstant(Imm, MVT::i8);
7291 }
7293 /// \brief Try to emit a blend instruction for a shuffle.
7294 ///
7295 /// This doesn't do any checks for the availability of instructions for blending
7296 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7297 /// be matched in the backend with the type given. What it does check for is
7298 /// that the shuffle mask is in fact a blend.
7299 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7300 SDValue V2, ArrayRef<int> Mask,
7301 const X86Subtarget *Subtarget,
7302 SelectionDAG &DAG) {
7304 unsigned BlendMask = 0;
7305 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7306 if (Mask[i] >= Size) {
7307 if (Mask[i] != i + Size)
7308 return SDValue(); // Shuffled V2 input!
7309 BlendMask |= 1u << i;
7310 continue;
7311 }
7312 if (Mask[i] >= 0 && Mask[i] != i)
7313 return SDValue(); // Shuffled V1 input!
7314 }
7315 switch (VT.SimpleTy) {
7316 case MVT::v2f64:
7317 case MVT::v4f32:
7318 case MVT::v4f64:
7319 case MVT::v8f32:
7320 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7321 DAG.getConstant(BlendMask, MVT::i8));
7323 case MVT::v4i64:
7324 case MVT::v8i32:
7325 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7326 // FALLTHROUGH
7327 case MVT::v2i64:
7328 case MVT::v4i32:
7329 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7330 // that instruction.
7331 if (Subtarget->hasAVX2()) {
7332 // Scale the blend by the number of 32-bit dwords per element.
7333 int Scale = VT.getScalarSizeInBits() / 32;
7334 BlendMask = 0;
7335 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7336 if (Mask[i] >= Size)
7337 for (int j = 0; j < Scale; ++j)
7338 BlendMask |= 1u << (i * Scale + j);
7340 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7341 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
7342 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
7343 return DAG.getNode(ISD::BITCAST, DL, VT,
7344 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7345 DAG.getConstant(BlendMask, MVT::i8)));
7346 }
7347 // FALLTHROUGH
7348 case MVT::v8i16: {
7349 // For integer shuffles we need to expand the mask and cast the inputs to
7350 // v8i16s prior to blending.
7351 int Scale = 8 / VT.getVectorNumElements();
7352 BlendMask = 0;
7353 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7354 if (Mask[i] >= Size)
7355 for (int j = 0; j < Scale; ++j)
7356 BlendMask |= 1u << (i * Scale + j);
7358 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7359 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7360 return DAG.getNode(ISD::BITCAST, DL, VT,
7361 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7362 DAG.getConstant(BlendMask, MVT::i8)));
7363 }
7365 case MVT::v16i16: {
7366 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7367 SmallVector<int, 8> RepeatedMask;
7368 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7369 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7370 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7371 BlendMask = 0;
7372 for (int i = 0; i < 8; ++i)
7373 if (RepeatedMask[i] >= 16)
7374 BlendMask |= 1u << i;
7375 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7376 DAG.getConstant(BlendMask, MVT::i8));
7377 }
7379 // Fall back to a fully general variable byte blend.
7380 SDValue PBLENDVMask[32];
7381 // Scale the blend by the number of bytes per element.
7382 int Scale = VT.getScalarSizeInBits() / 8;
7383 assert(Mask.size() * Scale == 32 && "Not a 256-bit vector!");
7384 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7385 for (int j = 0; j < Scale; ++j)
7386 PBLENDVMask[Scale * i + j] =
7387 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7388 : DAG.getConstant(Mask[i] < Size ? 0 : 0x80, MVT::i8);
7390 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1);
7391 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V2);
7392 return DAG.getNode(ISD::BITCAST, DL, VT, DAG.getNode(
7393 X86ISD::BLENDV, DL, MVT::v32i8, V1, V2,
7394 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PBLENDVMask)));
7395 }
7397 default:
7398 llvm_unreachable("Not a supported integer vector type!");
7399 }
7400 }
7402 /// \brief Generic routine to lower a shuffle and blend as a decomposed set of
7403 /// unblended shuffles followed by an unshuffled blend.
7404 ///
7405 /// This matches the extremely common pattern for handling combined
7406 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7407 /// operations.
7408 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7409 SDValue V1,
7410 SDValue V2,
7411 ArrayRef<int> Mask,
7412 SelectionDAG &DAG) {
7413 // Shuffle the input elements into the desired positions in V1 and V2 and
7414 // blend them together.
7415 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7416 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7417 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7418 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7419 if (Mask[i] >= 0 && Mask[i] < Size) {
7420 V1Mask[i] = Mask[i];
7421 BlendMask[i] = i;
7422 } else if (Mask[i] >= Size) {
7423 V2Mask[i] = Mask[i] - Size;
7424 BlendMask[i] = i + Size;
7425 }
7427 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7428 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7429 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7430 }
7432 /// \brief Try to lower a vector shuffle as a byte rotation.
7433 ///
7434 /// We have a generic PALIGNR instruction in x86 that will do an arbitrary
7435 /// byte-rotation of a the concatentation of two vectors. This routine will
7436 /// try to generically lower a vector shuffle through such an instruction. It
7437 /// does not check for the availability of PALIGNR-based lowerings, only the
7438 /// applicability of this strategy to the given mask. This matches shuffle
7439 /// vectors that look like:
7440 ///
7441 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7442 ///
7443 /// Essentially it concatenates V1 and V2, shifts right by some number of
7444 /// elements, and takes the low elements as the result. Note that while this is
7445 /// specified as a *right shift* because x86 is little-endian, it is a *left
7446 /// rotate* of the vector lanes.
7447 ///
7448 /// Note that this only handles 128-bit vector widths currently.
7449 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7450 SDValue V2,
7451 ArrayRef<int> Mask,
7452 SelectionDAG &DAG) {
7453 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7455 // We need to detect various ways of spelling a rotation:
7456 // [11, 12, 13, 14, 15, 0, 1, 2]
7457 // [-1, 12, 13, 14, -1, -1, 1, -1]
7458 // [-1, -1, -1, -1, -1, -1, 1, 2]
7459 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7460 // [-1, 4, 5, 6, -1, -1, 9, -1]
7461 // [-1, 4, 5, 6, -1, -1, -1, -1]
7462 int Rotation = 0;
7463 SDValue Lo, Hi;
7464 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7465 if (Mask[i] == -1)
7466 continue;
7467 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7469 // Based on the mod-Size value of this mask element determine where
7470 // a rotated vector would have started.
7471 int StartIdx = i - (Mask[i] % Size);
7472 if (StartIdx == 0)
7473 // The identity rotation isn't interesting, stop.
7474 return SDValue();
7476 // If we found the tail of a vector the rotation must be the missing
7477 // front. If we found the head of a vector, it must be how much of the head.
7478 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7480 if (Rotation == 0)
7481 Rotation = CandidateRotation;
7482 else if (Rotation != CandidateRotation)
7483 // The rotations don't match, so we can't match this mask.
7484 return SDValue();
7486 // Compute which value this mask is pointing at.
7487 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7489 // Compute which of the two target values this index should be assigned to.
7490 // This reflects whether the high elements are remaining or the low elements
7491 // are remaining.
7492 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7494 // Either set up this value if we've not encountered it before, or check
7495 // that it remains consistent.
7496 if (!TargetV)
7497 TargetV = MaskV;
7498 else if (TargetV != MaskV)
7499 // This may be a rotation, but it pulls from the inputs in some
7500 // unsupported interleaving.
7501 return SDValue();
7502 }
7504 // Check that we successfully analyzed the mask, and normalize the results.
7505 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7506 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7507 if (!Lo)
7508 Lo = Hi;
7509 else if (!Hi)
7510 Hi = Lo;
7512 // Cast the inputs to v16i8 to match PALIGNR.
7513 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7514 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7516 assert(VT.getSizeInBits() == 128 &&
7517 "Rotate-based lowering only supports 128-bit lowering!");
7518 assert(Mask.size() <= 16 &&
7519 "Can shuffle at most 16 bytes in a 128-bit vector!");
7520 // The actual rotate instruction rotates bytes, so we need to scale the
7521 // rotation based on how many bytes are in the vector.
7522 int Scale = 16 / Mask.size();
7524 return DAG.getNode(ISD::BITCAST, DL, VT,
7525 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7526 DAG.getConstant(Rotation * Scale, MVT::i8)));
7527 }
7529 /// \brief Compute whether each element of a shuffle is zeroable.
7530 ///
7531 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7532 /// Either it is an undef element in the shuffle mask, the element of the input
7533 /// referenced is undef, or the element of the input referenced is known to be
7534 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7535 /// as many lanes with this technique as possible to simplify the remaining
7536 /// shuffle.
7537 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7538 SDValue V1, SDValue V2) {
7539 SmallBitVector Zeroable(Mask.size(), false);
7541 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7542 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7544 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7545 int M = Mask[i];
7546 // Handle the easy cases.
7547 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7548 Zeroable[i] = true;
7549 continue;
7550 }
7552 // If this is an index into a build_vector node, dig out the input value and
7553 // use it.
7554 SDValue V = M < Size ? V1 : V2;
7555 if (V.getOpcode() != ISD::BUILD_VECTOR)
7556 continue;
7558 SDValue Input = V.getOperand(M % Size);
7559 // The UNDEF opcode check really should be dead code here, but not quite
7560 // worth asserting on (it isn't invalid, just unexpected).
7561 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7562 Zeroable[i] = true;
7563 }
7565 return Zeroable;
7566 }
7568 /// \brief Lower a vector shuffle as a zero or any extension.
7569 ///
7570 /// Given a specific number of elements, element bit width, and extension
7571 /// stride, produce either a zero or any extension based on the available
7572 /// features of the subtarget.
7573 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7574 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7575 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7576 assert(Scale > 1 && "Need a scale to extend.");
7577 int EltBits = VT.getSizeInBits() / NumElements;
7578 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7579 "Only 8, 16, and 32 bit elements can be extended.");
7580 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7582 // Found a valid zext mask! Try various lowering strategies based on the
7583 // input type and available ISA extensions.
7584 if (Subtarget->hasSSE41()) {
7585 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7586 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7587 NumElements / Scale);
7588 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7589 return DAG.getNode(ISD::BITCAST, DL, VT,
7590 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7591 }
7593 // For any extends we can cheat for larger element sizes and use shuffle
7594 // instructions that can fold with a load and/or copy.
7595 if (AnyExt && EltBits == 32) {
7596 int PSHUFDMask[4] = {0, -1, 1, -1};
7597 return DAG.getNode(
7598 ISD::BITCAST, DL, VT,
7599 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7600 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7601 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7602 }
7603 if (AnyExt && EltBits == 16 && Scale > 2) {
7604 int PSHUFDMask[4] = {0, -1, 0, -1};
7605 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7606 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7607 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7608 int PSHUFHWMask[4] = {1, -1, -1, -1};
7609 return DAG.getNode(
7610 ISD::BITCAST, DL, VT,
7611 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7612 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7613 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7614 }
7616 // If this would require more than 2 unpack instructions to expand, use
7617 // pshufb when available. We can only use more than 2 unpack instructions
7618 // when zero extending i8 elements which also makes it easier to use pshufb.
7619 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7620 assert(NumElements == 16 && "Unexpected byte vector width!");
7621 SDValue PSHUFBMask[16];
7622 for (int i = 0; i < 16; ++i)
7623 PSHUFBMask[i] =
7624 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7625 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7626 return DAG.getNode(ISD::BITCAST, DL, VT,
7627 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7628 DAG.getNode(ISD::BUILD_VECTOR, DL,
7629 MVT::v16i8, PSHUFBMask)));
7630 }
7632 // Otherwise emit a sequence of unpacks.
7633 do {
7634 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7635 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7636 : getZeroVector(InputVT, Subtarget, DAG, DL);
7637 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7638 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7639 Scale /= 2;
7640 EltBits *= 2;
7641 NumElements /= 2;
7642 } while (Scale > 1);
7643 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7644 }
7646 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7647 ///
7648 /// This routine will try to do everything in its power to cleverly lower
7649 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7650 /// check for the profitability of this lowering, it tries to aggressively
7651 /// match this pattern. It will use all of the micro-architectural details it
7652 /// can to emit an efficient lowering. It handles both blends with all-zero
7653 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7654 /// masking out later).
7655 ///
7656 /// The reason we have dedicated lowering for zext-style shuffles is that they
7657 /// are both incredibly common and often quite performance sensitive.
7658 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7659 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7660 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7661 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7663 int Bits = VT.getSizeInBits();
7664 int NumElements = Mask.size();
7666 // Define a helper function to check a particular ext-scale and lower to it if
7667 // valid.
7668 auto Lower = [&](int Scale) -> SDValue {
7669 SDValue InputV;
7670 bool AnyExt = true;
7671 for (int i = 0; i < NumElements; ++i) {
7672 if (Mask[i] == -1)
7673 continue; // Valid anywhere but doesn't tell us anything.
7674 if (i % Scale != 0) {
7675 // Each of the extend elements needs to be zeroable.
7676 if (!Zeroable[i])
7677 return SDValue();
7679 // We no lorger are in the anyext case.
7680 AnyExt = false;
7681 continue;
7682 }
7684 // Each of the base elements needs to be consecutive indices into the
7685 // same input vector.
7686 SDValue V = Mask[i] < NumElements ? V1 : V2;
7687 if (!InputV)
7688 InputV = V;
7689 else if (InputV != V)
7690 return SDValue(); // Flip-flopping inputs.
7692 if (Mask[i] % NumElements != i / Scale)
7693 return SDValue(); // Non-consecutive strided elemenst.
7694 }
7696 // If we fail to find an input, we have a zero-shuffle which should always
7697 // have already been handled.
7698 // FIXME: Maybe handle this here in case during blending we end up with one?
7699 if (!InputV)
7700 return SDValue();
7702 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7703 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7704 };
7706 // The widest scale possible for extending is to a 64-bit integer.
7707 assert(Bits % 64 == 0 &&
7708 "The number of bits in a vector must be divisible by 64 on x86!");
7709 int NumExtElements = Bits / 64;
7711 // Each iteration, try extending the elements half as much, but into twice as
7712 // many elements.
7713 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7714 assert(NumElements % NumExtElements == 0 &&
7715 "The input vector size must be divisble by the extended size.");
7716 if (SDValue V = Lower(NumElements / NumExtElements))
7717 return V;
7718 }
7720 // No viable ext lowering found.
7721 return SDValue();
7722 }
7724 /// \brief Try to lower insertion of a single element into a zero vector.
7725 ///
7726 /// This is a common pattern that we have especially efficient patterns to lower
7727 /// across all subtarget feature sets.
7728 static SDValue lowerVectorShuffleAsElementInsertion(
7729 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7730 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7731 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7733 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7734 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7735 Mask.begin();
7736 if (Mask.size() == 2) {
7737 if (!Zeroable[V2Index ^ 1]) {
7738 // For 2-wide masks we may be able to just invert the inputs. We use an xor
7739 // with 2 to flip from {2,3} to {0,1} and vice versa.
7740 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
7741 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
7742 if (Zeroable[V2Index])
7743 return lowerVectorShuffleAsElementInsertion(VT, DL, V2, V1, InverseMask,
7744 Subtarget, DAG);
7745 else
7746 return SDValue();
7747 }
7748 } else {
7749 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7750 if (i != V2Index && !Zeroable[i])
7751 return SDValue(); // Not inserting into a zero vector.
7752 }
7754 // Step over any bitcasts on either input so we can scan the actual
7755 // BUILD_VECTOR nodes.
7756 while (V1.getOpcode() == ISD::BITCAST)
7757 V1 = V1.getOperand(0);
7758 while (V2.getOpcode() == ISD::BITCAST)
7759 V2 = V2.getOperand(0);
7761 // Check for a single input from a SCALAR_TO_VECTOR node.
7762 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7763 // all the smarts here sunk into that routine. However, the current
7764 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7765 // vector shuffle lowering is dead.
7766 if (!((V2.getOpcode() == ISD::SCALAR_TO_VECTOR &&
7767 Mask[V2Index] == (int)Mask.size()) ||
7768 V2.getOpcode() == ISD::BUILD_VECTOR))
7769 return SDValue();
7771 SDValue V2S = V2.getOperand(Mask[V2Index] - Mask.size());
7773 // First, we need to zext the scalar if it is smaller than an i32.
7774 MVT ExtVT = VT;
7775 MVT EltVT = VT.getVectorElementType();
7776 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
7777 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7778 // Zero-extend directly to i32.
7779 ExtVT = MVT::v4i32;
7780 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7781 }
7783 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT,
7784 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S));
7785 if (ExtVT != VT)
7786 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7788 if (V2Index != 0) {
7789 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7790 // the desired position. Otherwise it is more efficient to do a vector
7791 // shift left. We know that we can do a vector shift left because all
7792 // the inputs are zero.
7793 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7794 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7795 V2Shuffle[V2Index] = 0;
7796 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7797 } else {
7798 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
7799 V2 = DAG.getNode(
7800 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7801 DAG.getConstant(
7802 V2Index * EltVT.getSizeInBits(),
7803 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
7804 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7805 }
7806 }
7807 return V2;
7808 }
7810 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7811 ///
7812 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7813 /// support for floating point shuffles but not integer shuffles. These
7814 /// instructions will incur a domain crossing penalty on some chips though so
7815 /// it is better to avoid lowering through this for integer vectors where
7816 /// possible.
7817 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7818 const X86Subtarget *Subtarget,
7819 SelectionDAG &DAG) {
7820 SDLoc DL(Op);
7821 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7822 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7823 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7824 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7825 ArrayRef<int> Mask = SVOp->getMask();
7826 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7828 if (isSingleInputShuffleMask(Mask)) {
7829 // Straight shuffle of a single input vector. Simulate this by using the
7830 // single input as both of the "inputs" to this instruction..
7831 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7833 if (Subtarget->hasAVX()) {
7834 // If we have AVX, we can use VPERMILPS which will allow folding a load
7835 // into the shuffle.
7836 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
7837 DAG.getConstant(SHUFPDMask, MVT::i8));
7838 }
7840 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
7841 DAG.getConstant(SHUFPDMask, MVT::i8));
7842 }
7843 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7844 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7846 // Use dedicated unpack instructions for masks that match their pattern.
7847 if (isShuffleEquivalent(Mask, 0, 2))
7848 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
7849 if (isShuffleEquivalent(Mask, 1, 3))
7850 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
7852 // If we have a single input, insert that into V1 if we can do so cheaply.
7853 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1)
7854 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7855 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
7856 return Insertion;
7858 if (Subtarget->hasSSE41())
7859 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
7860 Subtarget, DAG))
7861 return Blend;
7863 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
7864 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
7865 DAG.getConstant(SHUFPDMask, MVT::i8));
7866 }
7868 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
7869 ///
7870 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
7871 /// the integer unit to minimize domain crossing penalties. However, for blends
7872 /// it falls back to the floating point shuffle operation with appropriate bit
7873 /// casting.
7874 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7875 const X86Subtarget *Subtarget,
7876 SelectionDAG &DAG) {
7877 SDLoc DL(Op);
7878 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
7879 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7880 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7881 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7882 ArrayRef<int> Mask = SVOp->getMask();
7883 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7885 if (isSingleInputShuffleMask(Mask)) {
7886 // Straight shuffle of a single input vector. For everything from SSE2
7887 // onward this has a single fast instruction with no scary immediates.
7888 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7889 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
7890 int WidenedMask[4] = {
7891 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7892 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7893 return DAG.getNode(
7894 ISD::BITCAST, DL, MVT::v2i64,
7895 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
7896 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
7897 }
7899 // Use dedicated unpack instructions for masks that match their pattern.
7900 if (isShuffleEquivalent(Mask, 0, 2))
7901 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
7902 if (isShuffleEquivalent(Mask, 1, 3))
7903 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
7905 // If we have a single input from V2 insert that into V1 if we can do so
7906 // cheaply.
7907 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1)
7908 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7909 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
7910 return Insertion;
7912 if (Subtarget->hasSSE41())
7913 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
7914 Subtarget, DAG))
7915 return Blend;
7917 // Try to use rotation instructions if available.
7918 if (Subtarget->hasSSSE3())
7919 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7920 DL, MVT::v2i64, V1, V2, Mask, DAG))
7921 return Rotate;
7923 // We implement this with SHUFPD which is pretty lame because it will likely
7924 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7925 // However, all the alternatives are still more cycles and newer chips don't
7926 // have this problem. It would be really nice if x86 had better shuffles here.
7927 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
7928 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
7929 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7930 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7931 }
7933 /// \brief Lower a vector shuffle using the SHUFPS instruction.
7934 ///
7935 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
7936 /// It makes no assumptions about whether this is the *best* lowering, it simply
7937 /// uses it.
7938 static SDValue lowerVectorShuffleWithSHUPFS(SDLoc DL, MVT VT,
7939 ArrayRef<int> Mask, SDValue V1,
7940 SDValue V2, SelectionDAG &DAG) {
7941 SDValue LowV = V1, HighV = V2;
7942 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
7944 int NumV2Elements =
7945 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7947 if (NumV2Elements == 1) {
7948 int V2Index =
7949 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7950 Mask.begin();
7952 // Compute the index adjacent to V2Index and in the same half by toggling
7953 // the low bit.
7954 int V2AdjIndex = V2Index ^ 1;
7956 if (Mask[V2AdjIndex] == -1) {
7957 // Handles all the cases where we have a single V2 element and an undef.
7958 // This will only ever happen in the high lanes because we commute the
7959 // vector otherwise.
7960 if (V2Index < 2)
7961 std::swap(LowV, HighV);
7962 NewMask[V2Index] -= 4;
7963 } else {
7964 // Handle the case where the V2 element ends up adjacent to a V1 element.
7965 // To make this work, blend them together as the first step.
7966 int V1Index = V2AdjIndex;
7967 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
7968 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
7969 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7971 // Now proceed to reconstruct the final blend as we have the necessary
7972 // high or low half formed.
7973 if (V2Index < 2) {
7974 LowV = V2;
7975 HighV = V1;
7976 } else {
7977 HighV = V2;
7978 }
7979 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
7980 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
7981 }
7982 } else if (NumV2Elements == 2) {
7983 if (Mask[0] < 4 && Mask[1] < 4) {
7984 // Handle the easy case where we have V1 in the low lanes and V2 in the
7985 // high lanes. We never see this reversed because we sort the shuffle.
7986 NewMask[2] -= 4;
7987 NewMask[3] -= 4;
7988 } else {
7989 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
7990 // trying to place elements directly, just blend them and set up the final
7991 // shuffle to place them.
7993 // The first two blend mask elements are for V1, the second two are for
7994 // V2.
7995 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
7996 Mask[2] < 4 ? Mask[2] : Mask[3],
7997 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
7998 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
7999 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8000 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8002 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8003 // a blend.
8004 LowV = HighV = V1;
8005 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8006 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8007 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8008 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8009 }
8010 }
8011 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8012 getV4X86ShuffleImm8ForMask(NewMask, DAG));
8013 }
8015 /// \brief Lower 4-lane 32-bit floating point shuffles.
8016 ///
8017 /// Uses instructions exclusively from the floating point unit to minimize
8018 /// domain crossing penalties, as these are sufficient to implement all v4f32
8019 /// shuffles.
8020 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8021 const X86Subtarget *Subtarget,
8022 SelectionDAG &DAG) {
8023 SDLoc DL(Op);
8024 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8025 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8026 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8027 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8028 ArrayRef<int> Mask = SVOp->getMask();
8029 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8031 int NumV2Elements =
8032 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8034 if (NumV2Elements == 0) {
8035 if (Subtarget->hasAVX()) {
8036 // If we have AVX, we can use VPERMILPS which will allow folding a load
8037 // into the shuffle.
8038 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8039 getV4X86ShuffleImm8ForMask(Mask, DAG));
8040 }
8042 // Otherwise, use a straight shuffle of a single input vector. We pass the
8043 // input vector to both operands to simulate this with a SHUFPS.
8044 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8045 getV4X86ShuffleImm8ForMask(Mask, DAG));
8046 }
8048 // Use dedicated unpack instructions for masks that match their pattern.
8049 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8050 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8051 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8052 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8054 // There are special ways we can lower some single-element blends. However, we
8055 // have custom ways we can lower more complex single-element blends below that
8056 // we defer to if both this and BLENDPS fail to match, so restrict this to
8057 // when the V2 input is targeting element 0 of the mask -- that is the fast
8058 // case here.
8059 if (NumV2Elements == 1 && Mask[0] >= 4)
8060 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
8061 Mask, Subtarget, DAG))
8062 return V;
8064 if (Subtarget->hasSSE41())
8065 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8066 Subtarget, DAG))
8067 return Blend;
8069 // Check for whether we can use INSERTPS to perform the blend. We only use
8070 // INSERTPS when the V1 elements are already in the correct locations
8071 // because otherwise we can just always use two SHUFPS instructions which
8072 // are much smaller to encode than a SHUFPS and an INSERTPS.
8073 if (NumV2Elements == 1 && Subtarget->hasSSE41()) {
8074 int V2Index =
8075 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8076 Mask.begin();
8078 // When using INSERTPS we can zero any lane of the destination. Collect
8079 // the zero inputs into a mask and drop them from the lanes of V1 which
8080 // actually need to be present as inputs to the INSERTPS.
8081 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8083 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
8084 bool InsertNeedsShuffle = false;
8085 unsigned ZMask = 0;
8086 for (int i = 0; i < 4; ++i)
8087 if (i != V2Index) {
8088 if (Zeroable[i]) {
8089 ZMask |= 1 << i;
8090 } else if (Mask[i] != i) {
8091 InsertNeedsShuffle = true;
8092 break;
8093 }
8094 }
8096 // We don't want to use INSERTPS or other insertion techniques if it will
8097 // require shuffling anyways.
8098 if (!InsertNeedsShuffle) {
8099 // If all of V1 is zeroable, replace it with undef.
8100 if ((ZMask | 1 << V2Index) == 0xF)
8101 V1 = DAG.getUNDEF(MVT::v4f32);
8103 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
8104 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8106 // Insert the V2 element into the desired position.
8107 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8108 DAG.getConstant(InsertPSMask, MVT::i8));
8109 }
8110 }
8112 // Otherwise fall back to a SHUFPS lowering strategy.
8113 return lowerVectorShuffleWithSHUPFS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8114 }
8116 /// \brief Lower 4-lane i32 vector shuffles.
8117 ///
8118 /// We try to handle these with integer-domain shuffles where we can, but for
8119 /// blends we use the floating point domain blend instructions.
8120 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8121 const X86Subtarget *Subtarget,
8122 SelectionDAG &DAG) {
8123 SDLoc DL(Op);
8124 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8125 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8126 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8127 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8128 ArrayRef<int> Mask = SVOp->getMask();
8129 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8131 int NumV2Elements =
8132 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8134 if (NumV2Elements == 0) {
8135 // Straight shuffle of a single input vector. For everything from SSE2
8136 // onward this has a single fast instruction with no scary immediates.
8137 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8138 // but we aren't actually going to use the UNPCK instruction because doing
8139 // so prevents folding a load into this instruction or making a copy.
8140 const int UnpackLoMask[] = {0, 0, 1, 1};
8141 const int UnpackHiMask[] = {2, 2, 3, 3};
8142 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
8143 Mask = UnpackLoMask;
8144 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
8145 Mask = UnpackHiMask;
8147 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8148 getV4X86ShuffleImm8ForMask(Mask, DAG));
8149 }
8151 // Whenever we can lower this as a zext, that instruction is strictly faster
8152 // than any alternative.
8153 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8154 Mask, Subtarget, DAG))
8155 return ZExt;
8157 // Use dedicated unpack instructions for masks that match their pattern.
8158 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8159 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8160 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8161 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8163 // There are special ways we can lower some single-element blends.
8164 if (NumV2Elements == 1)
8165 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
8166 Mask, Subtarget, DAG))
8167 return V;
8169 if (Subtarget->hasSSE41())
8170 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8171 Subtarget, DAG))
8172 return Blend;
8174 // Try to use rotation instructions if available.
8175 if (Subtarget->hasSSSE3())
8176 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8177 DL, MVT::v4i32, V1, V2, Mask, DAG))
8178 return Rotate;
8180 // We implement this with SHUFPS because it can blend from two vectors.
8181 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8182 // up the inputs, bypassing domain shift penalties that we would encur if we
8183 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8184 // relevant.
8185 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8186 DAG.getVectorShuffle(
8187 MVT::v4f32, DL,
8188 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
8189 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8190 }
8192 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8193 /// shuffle lowering, and the most complex part.
8194 ///
8195 /// The lowering strategy is to try to form pairs of input lanes which are
8196 /// targeted at the same half of the final vector, and then use a dword shuffle
8197 /// to place them onto the right half, and finally unpack the paired lanes into
8198 /// their final position.
8199 ///
8200 /// The exact breakdown of how to form these dword pairs and align them on the
8201 /// correct sides is really tricky. See the comments within the function for
8202 /// more of the details.
8203 static SDValue lowerV8I16SingleInputVectorShuffle(
8204 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8205 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8206 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8207 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8208 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8210 SmallVector<int, 4> LoInputs;
8211 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8212 [](int M) { return M >= 0; });
8213 std::sort(LoInputs.begin(), LoInputs.end());
8214 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8215 SmallVector<int, 4> HiInputs;
8216 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8217 [](int M) { return M >= 0; });
8218 std::sort(HiInputs.begin(), HiInputs.end());
8219 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8220 int NumLToL =
8221 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8222 int NumHToL = LoInputs.size() - NumLToL;
8223 int NumLToH =
8224 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8225 int NumHToH = HiInputs.size() - NumLToH;
8226 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8227 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8228 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8229 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8231 // Use dedicated unpack instructions for masks that match their pattern.
8232 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8233 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8234 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8235 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8237 // Try to use rotation instructions if available.
8238 if (Subtarget->hasSSSE3())
8239 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8240 DL, MVT::v8i16, V, V, Mask, DAG))
8241 return Rotate;
8243 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8244 // such inputs we can swap two of the dwords across the half mark and end up
8245 // with <=2 inputs to each half in each half. Once there, we can fall through
8246 // to the generic code below. For example:
8247 //
8248 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8249 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8250 //
8251 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8252 // and an existing 2-into-2 on the other half. In this case we may have to
8253 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8254 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8255 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8256 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8257 // half than the one we target for fixing) will be fixed when we re-enter this
8258 // path. We will also combine away any sequence of PSHUFD instructions that
8259 // result into a single instruction. Here is an example of the tricky case:
8260 //
8261 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8262 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8263 //
8264 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8265 //
8266 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8267 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8268 //
8269 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8270 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8271 //
8272 // The result is fine to be handled by the generic logic.
8273 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8274 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8275 int AOffset, int BOffset) {
8276 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8277 "Must call this with A having 3 or 1 inputs from the A half.");
8278 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8279 "Must call this with B having 1 or 3 inputs from the B half.");
8280 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8281 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8283 // Compute the index of dword with only one word among the three inputs in
8284 // a half by taking the sum of the half with three inputs and subtracting
8285 // the sum of the actual three inputs. The difference is the remaining
8286 // slot.
8287 int ADWord, BDWord;
8288 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8289 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8290 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8291 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8292 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8293 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8294 int TripleNonInputIdx =
8295 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8296 TripleDWord = TripleNonInputIdx / 2;
8298 // We use xor with one to compute the adjacent DWord to whichever one the
8299 // OneInput is in.
8300 OneInputDWord = (OneInput / 2) ^ 1;
8302 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8303 // and BToA inputs. If there is also such a problem with the BToB and AToB
8304 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8305 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8306 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8307 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8308 // Compute how many inputs will be flipped by swapping these DWords. We
8309 // need
8310 // to balance this to ensure we don't form a 3-1 shuffle in the other
8311 // half.
8312 int NumFlippedAToBInputs =
8313 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8314 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8315 int NumFlippedBToBInputs =
8316 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8317 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8318 if ((NumFlippedAToBInputs == 1 &&
8319 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8320 (NumFlippedBToBInputs == 1 &&
8321 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8322 // We choose whether to fix the A half or B half based on whether that
8323 // half has zero flipped inputs. At zero, we may not be able to fix it
8324 // with that half. We also bias towards fixing the B half because that
8325 // will more commonly be the high half, and we have to bias one way.
8326 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8327 ArrayRef<int> Inputs) {
8328 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8329 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8330 PinnedIdx ^ 1) != Inputs.end();
8331 // Determine whether the free index is in the flipped dword or the
8332 // unflipped dword based on where the pinned index is. We use this bit
8333 // in an xor to conditionally select the adjacent dword.
8334 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8335 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8336 FixFreeIdx) != Inputs.end();
8337 if (IsFixIdxInput == IsFixFreeIdxInput)
8338 FixFreeIdx += 1;
8339 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8340 FixFreeIdx) != Inputs.end();
8341 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8342 "We need to be changing the number of flipped inputs!");
8343 int PSHUFHalfMask[] = {0, 1, 2, 3};
8344 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8345 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8346 MVT::v8i16, V,
8347 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8349 for (int &M : Mask)
8350 if (M != -1 && M == FixIdx)
8351 M = FixFreeIdx;
8352 else if (M != -1 && M == FixFreeIdx)
8353 M = FixIdx;
8354 };
8355 if (NumFlippedBToBInputs != 0) {
8356 int BPinnedIdx =
8357 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8358 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8359 } else {
8360 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8361 int APinnedIdx =
8362 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8363 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8364 }
8365 }
8366 }
8368 int PSHUFDMask[] = {0, 1, 2, 3};
8369 PSHUFDMask[ADWord] = BDWord;
8370 PSHUFDMask[BDWord] = ADWord;
8371 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8372 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8373 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8374 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8376 // Adjust the mask to match the new locations of A and B.
8377 for (int &M : Mask)
8378 if (M != -1 && M/2 == ADWord)
8379 M = 2 * BDWord + M % 2;
8380 else if (M != -1 && M/2 == BDWord)
8381 M = 2 * ADWord + M % 2;
8383 // Recurse back into this routine to re-compute state now that this isn't
8384 // a 3 and 1 problem.
8385 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8386 Mask);
8387 };
8388 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8389 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8390 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8391 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8393 // At this point there are at most two inputs to the low and high halves from
8394 // each half. That means the inputs can always be grouped into dwords and
8395 // those dwords can then be moved to the correct half with a dword shuffle.
8396 // We use at most one low and one high word shuffle to collect these paired
8397 // inputs into dwords, and finally a dword shuffle to place them.
8398 int PSHUFLMask[4] = {-1, -1, -1, -1};
8399 int PSHUFHMask[4] = {-1, -1, -1, -1};
8400 int PSHUFDMask[4] = {-1, -1, -1, -1};
8402 // First fix the masks for all the inputs that are staying in their
8403 // original halves. This will then dictate the targets of the cross-half
8404 // shuffles.
8405 auto fixInPlaceInputs =
8406 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8407 MutableArrayRef<int> SourceHalfMask,
8408 MutableArrayRef<int> HalfMask, int HalfOffset) {
8409 if (InPlaceInputs.empty())
8410 return;
8411 if (InPlaceInputs.size() == 1) {
8412 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8413 InPlaceInputs[0] - HalfOffset;
8414 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8415 return;
8416 }
8417 if (IncomingInputs.empty()) {
8418 // Just fix all of the in place inputs.
8419 for (int Input : InPlaceInputs) {
8420 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8421 PSHUFDMask[Input / 2] = Input / 2;
8422 }
8423 return;
8424 }
8426 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8427 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8428 InPlaceInputs[0] - HalfOffset;
8429 // Put the second input next to the first so that they are packed into
8430 // a dword. We find the adjacent index by toggling the low bit.
8431 int AdjIndex = InPlaceInputs[0] ^ 1;
8432 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8433 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8434 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8435 };
8436 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8437 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8439 // Now gather the cross-half inputs and place them into a free dword of
8440 // their target half.
8441 // FIXME: This operation could almost certainly be simplified dramatically to
8442 // look more like the 3-1 fixing operation.
8443 auto moveInputsToRightHalf = [&PSHUFDMask](
8444 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8445 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8446 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8447 int DestOffset) {
8448 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8449 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8450 };
8451 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8452 int Word) {
8453 int LowWord = Word & ~1;
8454 int HighWord = Word | 1;
8455 return isWordClobbered(SourceHalfMask, LowWord) ||
8456 isWordClobbered(SourceHalfMask, HighWord);
8457 };
8459 if (IncomingInputs.empty())
8460 return;
8462 if (ExistingInputs.empty()) {
8463 // Map any dwords with inputs from them into the right half.
8464 for (int Input : IncomingInputs) {
8465 // If the source half mask maps over the inputs, turn those into
8466 // swaps and use the swapped lane.
8467 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8468 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8469 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8470 Input - SourceOffset;
8471 // We have to swap the uses in our half mask in one sweep.
8472 for (int &M : HalfMask)
8473 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8474 M = Input;
8475 else if (M == Input)
8476 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8477 } else {
8478 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8479 Input - SourceOffset &&
8480 "Previous placement doesn't match!");
8481 }
8482 // Note that this correctly re-maps both when we do a swap and when
8483 // we observe the other side of the swap above. We rely on that to
8484 // avoid swapping the members of the input list directly.
8485 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8486 }
8488 // Map the input's dword into the correct half.
8489 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8490 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8491 else
8492 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8493 Input / 2 &&
8494 "Previous placement doesn't match!");
8495 }
8497 // And just directly shift any other-half mask elements to be same-half
8498 // as we will have mirrored the dword containing the element into the
8499 // same position within that half.
8500 for (int &M : HalfMask)
8501 if (M >= SourceOffset && M < SourceOffset + 4) {
8502 M = M - SourceOffset + DestOffset;
8503 assert(M >= 0 && "This should never wrap below zero!");
8504 }
8505 return;
8506 }
8508 // Ensure we have the input in a viable dword of its current half. This
8509 // is particularly tricky because the original position may be clobbered
8510 // by inputs being moved and *staying* in that half.
8511 if (IncomingInputs.size() == 1) {
8512 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8513 int InputFixed = std::find(std::begin(SourceHalfMask),
8514 std::end(SourceHalfMask), -1) -
8515 std::begin(SourceHalfMask) + SourceOffset;
8516 SourceHalfMask[InputFixed - SourceOffset] =
8517 IncomingInputs[0] - SourceOffset;
8518 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8519 InputFixed);
8520 IncomingInputs[0] = InputFixed;
8521 }
8522 } else if (IncomingInputs.size() == 2) {
8523 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8524 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8525 // We have two non-adjacent or clobbered inputs we need to extract from
8526 // the source half. To do this, we need to map them into some adjacent
8527 // dword slot in the source mask.
8528 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8529 IncomingInputs[1] - SourceOffset};
8531 // If there is a free slot in the source half mask adjacent to one of
8532 // the inputs, place the other input in it. We use (Index XOR 1) to
8533 // compute an adjacent index.
8534 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8535 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8536 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8537 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8538 InputsFixed[1] = InputsFixed[0] ^ 1;
8539 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8540 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8541 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8542 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8543 InputsFixed[0] = InputsFixed[1] ^ 1;
8544 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8545 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8546 // The two inputs are in the same DWord but it is clobbered and the
8547 // adjacent DWord isn't used at all. Move both inputs to the free
8548 // slot.
8549 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8550 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8551 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8552 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8553 } else {
8554 // The only way we hit this point is if there is no clobbering
8555 // (because there are no off-half inputs to this half) and there is no
8556 // free slot adjacent to one of the inputs. In this case, we have to
8557 // swap an input with a non-input.
8558 for (int i = 0; i < 4; ++i)
8559 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8560 "We can't handle any clobbers here!");
8561 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8562 "Cannot have adjacent inputs here!");
8564 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8565 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8567 // We also have to update the final source mask in this case because
8568 // it may need to undo the above swap.
8569 for (int &M : FinalSourceHalfMask)
8570 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8571 M = InputsFixed[1] + SourceOffset;
8572 else if (M == InputsFixed[1] + SourceOffset)
8573 M = (InputsFixed[0] ^ 1) + SourceOffset;
8575 InputsFixed[1] = InputsFixed[0] ^ 1;
8576 }
8578 // Point everything at the fixed inputs.
8579 for (int &M : HalfMask)
8580 if (M == IncomingInputs[0])
8581 M = InputsFixed[0] + SourceOffset;
8582 else if (M == IncomingInputs[1])
8583 M = InputsFixed[1] + SourceOffset;
8585 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8586 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8587 }
8588 } else {
8589 llvm_unreachable("Unhandled input size!");
8590 }
8592 // Now hoist the DWord down to the right half.
8593 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8594 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8595 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8596 for (int &M : HalfMask)
8597 for (int Input : IncomingInputs)
8598 if (M == Input)
8599 M = FreeDWord * 2 + Input % 2;
8600 };
8601 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8602 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8603 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8604 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8606 // Now enact all the shuffles we've computed to move the inputs into their
8607 // target half.
8608 if (!isNoopShuffleMask(PSHUFLMask))
8609 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8610 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
8611 if (!isNoopShuffleMask(PSHUFHMask))
8612 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8613 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
8614 if (!isNoopShuffleMask(PSHUFDMask))
8615 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8616 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8617 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8618 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8620 // At this point, each half should contain all its inputs, and we can then
8621 // just shuffle them into their final position.
8622 assert(std::count_if(LoMask.begin(), LoMask.end(),
8623 [](int M) { return M >= 4; }) == 0 &&
8624 "Failed to lift all the high half inputs to the low mask!");
8625 assert(std::count_if(HiMask.begin(), HiMask.end(),
8626 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8627 "Failed to lift all the low half inputs to the high mask!");
8629 // Do a half shuffle for the low mask.
8630 if (!isNoopShuffleMask(LoMask))
8631 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8632 getV4X86ShuffleImm8ForMask(LoMask, DAG));
8634 // Do a half shuffle with the high mask after shifting its values down.
8635 for (int &M : HiMask)
8636 if (M >= 0)
8637 M -= 4;
8638 if (!isNoopShuffleMask(HiMask))
8639 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8640 getV4X86ShuffleImm8ForMask(HiMask, DAG));
8642 return V;
8643 }
8645 /// \brief Detect whether the mask pattern should be lowered through
8646 /// interleaving.
8647 ///
8648 /// This essentially tests whether viewing the mask as an interleaving of two
8649 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
8650 /// lowering it through interleaving is a significantly better strategy.
8651 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
8652 int NumEvenInputs[2] = {0, 0};
8653 int NumOddInputs[2] = {0, 0};
8654 int NumLoInputs[2] = {0, 0};
8655 int NumHiInputs[2] = {0, 0};
8656 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
8657 if (Mask[i] < 0)
8658 continue;
8660 int InputIdx = Mask[i] >= Size;
8662 if (i < Size / 2)
8663 ++NumLoInputs[InputIdx];
8664 else
8665 ++NumHiInputs[InputIdx];
8667 if ((i % 2) == 0)
8668 ++NumEvenInputs[InputIdx];
8669 else
8670 ++NumOddInputs[InputIdx];
8671 }
8673 // The minimum number of cross-input results for both the interleaved and
8674 // split cases. If interleaving results in fewer cross-input results, return
8675 // true.
8676 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
8677 NumEvenInputs[0] + NumOddInputs[1]);
8678 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
8679 NumLoInputs[0] + NumHiInputs[1]);
8680 return InterleavedCrosses < SplitCrosses;
8681 }
8683 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
8684 ///
8685 /// This strategy only works when the inputs from each vector fit into a single
8686 /// half of that vector, and generally there are not so many inputs as to leave
8687 /// the in-place shuffles required highly constrained (and thus expensive). It
8688 /// shifts all the inputs into a single side of both input vectors and then
8689 /// uses an unpack to interleave these inputs in a single vector. At that
8690 /// point, we will fall back on the generic single input shuffle lowering.
8691 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
8692 SDValue V2,
8693 MutableArrayRef<int> Mask,
8694 const X86Subtarget *Subtarget,
8695 SelectionDAG &DAG) {
8696 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8697 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8698 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
8699 for (int i = 0; i < 8; ++i)
8700 if (Mask[i] >= 0 && Mask[i] < 4)
8701 LoV1Inputs.push_back(i);
8702 else if (Mask[i] >= 4 && Mask[i] < 8)
8703 HiV1Inputs.push_back(i);
8704 else if (Mask[i] >= 8 && Mask[i] < 12)
8705 LoV2Inputs.push_back(i);
8706 else if (Mask[i] >= 12)
8707 HiV2Inputs.push_back(i);
8709 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
8710 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
8711 (void)NumV1Inputs;
8712 (void)NumV2Inputs;
8713 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
8714 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
8715 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
8717 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
8718 HiV1Inputs.size() + HiV2Inputs.size();
8720 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
8721 ArrayRef<int> HiInputs, bool MoveToLo,
8722 int MaskOffset) {
8723 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
8724 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
8725 if (BadInputs.empty())
8726 return V;
8728 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8729 int MoveOffset = MoveToLo ? 0 : 4;
8731 if (GoodInputs.empty()) {
8732 for (int BadInput : BadInputs) {
8733 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
8734 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
8735 }
8736 } else {
8737 if (GoodInputs.size() == 2) {
8738 // If the low inputs are spread across two dwords, pack them into
8739 // a single dword.
8740 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
8741 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
8742 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
8743 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
8744 } else {
8745 // Otherwise pin the good inputs.
8746 for (int GoodInput : GoodInputs)
8747 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
8748 }
8750 if (BadInputs.size() == 2) {
8751 // If we have two bad inputs then there may be either one or two good
8752 // inputs fixed in place. Find a fixed input, and then find the *other*
8753 // two adjacent indices by using modular arithmetic.
8754 int GoodMaskIdx =
8755 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
8756 [](int M) { return M >= 0; }) -
8757 std::begin(MoveMask);
8758 int MoveMaskIdx =
8759 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
8760 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
8761 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
8762 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8763 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
8764 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8765 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
8766 } else {
8767 assert(BadInputs.size() == 1 && "All sizes handled");
8768 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
8769 std::end(MoveMask), -1) -
8770 std::begin(MoveMask);
8771 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8772 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8773 }
8774 }
8776 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8777 MoveMask);
8778 };
8779 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
8780 /*MaskOffset*/ 0);
8781 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
8782 /*MaskOffset*/ 8);
8784 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
8785 // cross-half traffic in the final shuffle.
8787 // Munge the mask to be a single-input mask after the unpack merges the
8788 // results.
8789 for (int &M : Mask)
8790 if (M != -1)
8791 M = 2 * (M % 4) + (M / 8);
8793 return DAG.getVectorShuffle(
8794 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
8795 DL, MVT::v8i16, V1, V2),
8796 DAG.getUNDEF(MVT::v8i16), Mask);
8797 }
8799 /// \brief Generic lowering of 8-lane i16 shuffles.
8800 ///
8801 /// This handles both single-input shuffles and combined shuffle/blends with
8802 /// two inputs. The single input shuffles are immediately delegated to
8803 /// a dedicated lowering routine.
8804 ///
8805 /// The blends are lowered in one of three fundamental ways. If there are few
8806 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
8807 /// of the input is significantly cheaper when lowered as an interleaving of
8808 /// the two inputs, try to interleave them. Otherwise, blend the low and high
8809 /// halves of the inputs separately (making them have relatively few inputs)
8810 /// and then concatenate them.
8811 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8812 const X86Subtarget *Subtarget,
8813 SelectionDAG &DAG) {
8814 SDLoc DL(Op);
8815 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
8816 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8817 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8818 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8819 ArrayRef<int> OrigMask = SVOp->getMask();
8820 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8821 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
8822 MutableArrayRef<int> Mask(MaskStorage);
8824 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
8826 // Whenever we can lower this as a zext, that instruction is strictly faster
8827 // than any alternative.
8828 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8829 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
8830 return ZExt;
8832 auto isV1 = [](int M) { return M >= 0 && M < 8; };
8833 auto isV2 = [](int M) { return M >= 8; };
8835 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
8836 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
8838 if (NumV2Inputs == 0)
8839 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
8841 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
8842 "to be V1-input shuffles.");
8844 // There are special ways we can lower some single-element blends.
8845 if (NumV2Inputs == 1)
8846 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
8847 Mask, Subtarget, DAG))
8848 return V;
8850 if (Subtarget->hasSSE41())
8851 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
8852 Subtarget, DAG))
8853 return Blend;
8855 // Try to use rotation instructions if available.
8856 if (Subtarget->hasSSSE3())
8857 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V2, Mask, DAG))
8858 return Rotate;
8860 if (NumV1Inputs + NumV2Inputs <= 4)
8861 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
8863 // Check whether an interleaving lowering is likely to be more efficient.
8864 // This isn't perfect but it is a strong heuristic that tends to work well on
8865 // the kinds of shuffles that show up in practice.
8866 //
8867 // FIXME: Handle 1x, 2x, and 4x interleaving.
8868 if (shouldLowerAsInterleaving(Mask)) {
8869 // FIXME: Figure out whether we should pack these into the low or high
8870 // halves.
8872 int EMask[8], OMask[8];
8873 for (int i = 0; i < 4; ++i) {
8874 EMask[i] = Mask[2*i];
8875 OMask[i] = Mask[2*i + 1];
8876 EMask[i + 4] = -1;
8877 OMask[i + 4] = -1;
8878 }
8880 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
8881 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
8883 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
8884 }
8886 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8887 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8889 for (int i = 0; i < 4; ++i) {
8890 LoBlendMask[i] = Mask[i];
8891 HiBlendMask[i] = Mask[i + 4];
8892 }
8894 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
8895 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
8896 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
8897 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
8899 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8900 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
8901 }
8903 /// \brief Check whether a compaction lowering can be done by dropping even
8904 /// elements and compute how many times even elements must be dropped.
8905 ///
8906 /// This handles shuffles which take every Nth element where N is a power of
8907 /// two. Example shuffle masks:
8908 ///
8909 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
8910 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
8911 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
8912 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
8913 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
8914 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
8915 ///
8916 /// Any of these lanes can of course be undef.
8917 ///
8918 /// This routine only supports N <= 3.
8919 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
8920 /// for larger N.
8921 ///
8922 /// \returns N above, or the number of times even elements must be dropped if
8923 /// there is such a number. Otherwise returns zero.
8924 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
8925 // Figure out whether we're looping over two inputs or just one.
8926 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8928 // The modulus for the shuffle vector entries is based on whether this is
8929 // a single input or not.
8930 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
8931 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
8932 "We should only be called with masks with a power-of-2 size!");
8934 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
8936 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
8937 // and 2^3 simultaneously. This is because we may have ambiguity with
8938 // partially undef inputs.
8939 bool ViableForN[3] = {true, true, true};
8941 for (int i = 0, e = Mask.size(); i < e; ++i) {
8942 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
8943 // want.
8944 if (Mask[i] == -1)
8945 continue;
8947 bool IsAnyViable = false;
8948 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8949 if (ViableForN[j]) {
8950 uint64_t N = j + 1;
8952 // The shuffle mask must be equal to (i * 2^N) % M.
8953 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
8954 IsAnyViable = true;
8955 else
8956 ViableForN[j] = false;
8957 }
8958 // Early exit if we exhaust the possible powers of two.
8959 if (!IsAnyViable)
8960 break;
8961 }
8963 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8964 if (ViableForN[j])
8965 return j + 1;
8967 // Return 0 as there is no viable power of two.
8968 return 0;
8969 }
8971 /// \brief Generic lowering of v16i8 shuffles.
8972 ///
8973 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
8974 /// detect any complexity reducing interleaving. If that doesn't help, it uses
8975 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
8976 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
8977 /// back together.
8978 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8979 const X86Subtarget *Subtarget,
8980 SelectionDAG &DAG) {
8981 SDLoc DL(Op);
8982 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
8983 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8984 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8985 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8986 ArrayRef<int> OrigMask = SVOp->getMask();
8987 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
8989 // Try to use rotation instructions if available.
8990 if (Subtarget->hasSSSE3())
8991 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v16i8, V1, V2,
8992 OrigMask, DAG))
8993 return Rotate;
8995 // Try to use a zext lowering.
8996 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8997 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
8998 return ZExt;
9000 int MaskStorage[16] = {
9001 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9002 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
9003 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
9004 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
9005 MutableArrayRef<int> Mask(MaskStorage);
9006 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
9007 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
9009 int NumV2Elements =
9010 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9012 // For single-input shuffles, there are some nicer lowering tricks we can use.
9013 if (NumV2Elements == 0) {
9014 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9015 // Notably, this handles splat and partial-splat shuffles more efficiently.
9016 // However, it only makes sense if the pre-duplication shuffle simplifies
9017 // things significantly. Currently, this means we need to be able to
9018 // express the pre-duplication shuffle as an i16 shuffle.
9019 //
9020 // FIXME: We should check for other patterns which can be widened into an
9021 // i16 shuffle as well.
9022 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9023 for (int i = 0; i < 16; i += 2)
9024 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9025 return false;
9027 return true;
9028 };
9029 auto tryToWidenViaDuplication = [&]() -> SDValue {
9030 if (!canWidenViaDuplication(Mask))
9031 return SDValue();
9032 SmallVector<int, 4> LoInputs;
9033 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9034 [](int M) { return M >= 0 && M < 8; });
9035 std::sort(LoInputs.begin(), LoInputs.end());
9036 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9037 LoInputs.end());
9038 SmallVector<int, 4> HiInputs;
9039 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9040 [](int M) { return M >= 8; });
9041 std::sort(HiInputs.begin(), HiInputs.end());
9042 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9043 HiInputs.end());
9045 bool TargetLo = LoInputs.size() >= HiInputs.size();
9046 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9047 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9049 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9050 SmallDenseMap<int, int, 8> LaneMap;
9051 for (int I : InPlaceInputs) {
9052 PreDupI16Shuffle[I/2] = I/2;
9053 LaneMap[I] = I;
9054 }
9055 int j = TargetLo ? 0 : 4, je = j + 4;
9056 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9057 // Check if j is already a shuffle of this input. This happens when
9058 // there are two adjacent bytes after we move the low one.
9059 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9060 // If we haven't yet mapped the input, search for a slot into which
9061 // we can map it.
9062 while (j < je && PreDupI16Shuffle[j] != -1)
9063 ++j;
9065 if (j == je)
9066 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9067 return SDValue();
9069 // Map this input with the i16 shuffle.
9070 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9071 }
9073 // Update the lane map based on the mapping we ended up with.
9074 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9075 }
9076 V1 = DAG.getNode(
9077 ISD::BITCAST, DL, MVT::v16i8,
9078 DAG.getVectorShuffle(MVT::v8i16, DL,
9079 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9080 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9082 // Unpack the bytes to form the i16s that will be shuffled into place.
9083 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9084 MVT::v16i8, V1, V1);
9086 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9087 for (int i = 0; i < 16; i += 2) {
9088 if (Mask[i] != -1)
9089 PostDupI16Shuffle[i / 2] = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9090 assert(PostDupI16Shuffle[i / 2] < 8 && "Invalid v8 shuffle mask!");
9091 }
9092 return DAG.getNode(
9093 ISD::BITCAST, DL, MVT::v16i8,
9094 DAG.getVectorShuffle(MVT::v8i16, DL,
9095 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9096 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9097 };
9098 if (SDValue V = tryToWidenViaDuplication())
9099 return V;
9100 }
9102 // Check whether an interleaving lowering is likely to be more efficient.
9103 // This isn't perfect but it is a strong heuristic that tends to work well on
9104 // the kinds of shuffles that show up in practice.
9105 //
9106 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
9107 if (shouldLowerAsInterleaving(Mask)) {
9108 // FIXME: Figure out whether we should pack these into the low or high
9109 // halves.
9111 int EMask[16], OMask[16];
9112 for (int i = 0; i < 8; ++i) {
9113 EMask[i] = Mask[2*i];
9114 OMask[i] = Mask[2*i + 1];
9115 EMask[i + 8] = -1;
9116 OMask[i + 8] = -1;
9117 }
9119 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
9120 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
9122 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, Evens, Odds);
9123 }
9125 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9126 // with PSHUFB. It is important to do this before we attempt to generate any
9127 // blends but after all of the single-input lowerings. If the single input
9128 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9129 // want to preserve that and we can DAG combine any longer sequences into
9130 // a PSHUFB in the end. But once we start blending from multiple inputs,
9131 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9132 // and there are *very* few patterns that would actually be faster than the
9133 // PSHUFB approach because of its ability to zero lanes.
9134 //
9135 // FIXME: The only exceptions to the above are blends which are exact
9136 // interleavings with direct instructions supporting them. We currently don't
9137 // handle those well here.
9138 if (Subtarget->hasSSSE3()) {
9139 SDValue V1Mask[16];
9140 SDValue V2Mask[16];
9141 for (int i = 0; i < 16; ++i)
9142 if (Mask[i] == -1) {
9143 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9144 } else {
9145 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
9146 V2Mask[i] =
9147 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
9148 }
9149 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
9150 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9151 if (isSingleInputShuffleMask(Mask))
9152 return V1; // Single inputs are easy.
9154 // Otherwise, blend the two.
9155 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
9156 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9157 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9158 }
9160 // There are special ways we can lower some single-element blends.
9161 if (NumV2Elements == 1)
9162 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
9163 Mask, Subtarget, DAG))
9164 return V;
9166 // Check whether a compaction lowering can be done. This handles shuffles
9167 // which take every Nth element for some even N. See the helper function for
9168 // details.
9169 //
9170 // We special case these as they can be particularly efficiently handled with
9171 // the PACKUSB instruction on x86 and they show up in common patterns of
9172 // rearranging bytes to truncate wide elements.
9173 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9174 // NumEvenDrops is the power of two stride of the elements. Another way of
9175 // thinking about it is that we need to drop the even elements this many
9176 // times to get the original input.
9177 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9179 // First we need to zero all the dropped bytes.
9180 assert(NumEvenDrops <= 3 &&
9181 "No support for dropping even elements more than 3 times.");
9182 // We use the mask type to pick which bytes are preserved based on how many
9183 // elements are dropped.
9184 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9185 SDValue ByteClearMask =
9186 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
9187 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
9188 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9189 if (!IsSingleInput)
9190 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9192 // Now pack things back together.
9193 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9194 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9195 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9196 for (int i = 1; i < NumEvenDrops; ++i) {
9197 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9198 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9199 }
9201 return Result;
9202 }
9204 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9205 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9206 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9207 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9209 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9210 MutableArrayRef<int> V1HalfBlendMask,
9211 MutableArrayRef<int> V2HalfBlendMask) {
9212 for (int i = 0; i < 8; ++i)
9213 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9214 V1HalfBlendMask[i] = HalfMask[i];
9215 HalfMask[i] = i;
9216 } else if (HalfMask[i] >= 16) {
9217 V2HalfBlendMask[i] = HalfMask[i] - 16;
9218 HalfMask[i] = i + 8;
9219 }
9220 };
9221 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9222 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9224 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9226 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9227 MutableArrayRef<int> HiBlendMask) {
9228 SDValue V1, V2;
9229 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9230 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9231 // i16s.
9232 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9233 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9234 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9235 [](int M) { return M >= 0 && M % 2 == 1; })) {
9236 // Use a mask to drop the high bytes.
9237 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9238 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9239 DAG.getConstant(0x00FF, MVT::v8i16));
9241 // This will be a single vector shuffle instead of a blend so nuke V2.
9242 V2 = DAG.getUNDEF(MVT::v8i16);
9244 // Squash the masks to point directly into V1.
9245 for (int &M : LoBlendMask)
9246 if (M >= 0)
9247 M /= 2;
9248 for (int &M : HiBlendMask)
9249 if (M >= 0)
9250 M /= 2;
9251 } else {
9252 // Otherwise just unpack the low half of V into V1 and the high half into
9253 // V2 so that we can blend them as i16s.
9254 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9255 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9256 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9257 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9258 }
9260 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9261 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9262 return std::make_pair(BlendedLo, BlendedHi);
9263 };
9264 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9265 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9266 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9268 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9269 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9271 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9272 }
9274 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9275 ///
9276 /// This routine breaks down the specific type of 128-bit shuffle and
9277 /// dispatches to the lowering routines accordingly.
9278 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9279 MVT VT, const X86Subtarget *Subtarget,
9280 SelectionDAG &DAG) {
9281 switch (VT.SimpleTy) {
9282 case MVT::v2i64:
9283 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9284 case MVT::v2f64:
9285 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9286 case MVT::v4i32:
9287 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9288 case MVT::v4f32:
9289 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9290 case MVT::v8i16:
9291 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9292 case MVT::v16i8:
9293 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9295 default:
9296 llvm_unreachable("Unimplemented!");
9297 }
9298 }
9300 /// \brief Generic routine to split a 256-bit vector shuffle into 128-bit
9301 /// shuffles.
9302 ///
9303 /// There is a severely limited set of shuffles available in AVX1 for 256-bit
9304 /// vectors resulting in routinely needing to split the shuffle into two 128-bit
9305 /// shuffles. This can be done generically for any 256-bit vector shuffle and so
9306 /// we encode the logic here for specific shuffle lowering routines to bail to
9307 /// when they exhaust the features avaible to more directly handle the shuffle.
9308 static SDValue splitAndLower256BitVectorShuffle(SDValue Op, SDValue V1,
9309 SDValue V2,
9310 const X86Subtarget *Subtarget,
9311 SelectionDAG &DAG) {
9312 SDLoc DL(Op);
9313 MVT VT = Op.getSimpleValueType();
9314 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9315 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9316 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9317 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9318 ArrayRef<int> Mask = SVOp->getMask();
9320 ArrayRef<int> LoMask = Mask.slice(0, Mask.size()/2);
9321 ArrayRef<int> HiMask = Mask.slice(Mask.size()/2);
9323 int NumElements = VT.getVectorNumElements();
9324 int SplitNumElements = NumElements / 2;
9325 MVT ScalarVT = VT.getScalarType();
9326 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9328 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9329 DAG.getIntPtrConstant(0));
9330 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9331 DAG.getIntPtrConstant(SplitNumElements));
9332 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9333 DAG.getIntPtrConstant(0));
9334 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9335 DAG.getIntPtrConstant(SplitNumElements));
9337 // Now create two 4-way blends of these half-width vectors.
9338 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9339 SmallVector<int, 16> V1BlendMask, V2BlendMask, BlendMask;
9340 for (int i = 0; i < SplitNumElements; ++i) {
9341 int M = HalfMask[i];
9342 if (M >= NumElements) {
9343 V2BlendMask.push_back(M - NumElements);
9344 V1BlendMask.push_back(-1);
9345 BlendMask.push_back(SplitNumElements + i);
9346 } else if (M >= 0) {
9347 V2BlendMask.push_back(-1);
9348 V1BlendMask.push_back(M);
9349 BlendMask.push_back(i);
9350 } else {
9351 V2BlendMask.push_back(-1);
9352 V1BlendMask.push_back(-1);
9353 BlendMask.push_back(-1);
9354 }
9355 }
9356 SDValue V1Blend = DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9357 SDValue V2Blend = DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9358 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9359 };
9360 SDValue Lo = HalfBlend(LoMask);
9361 SDValue Hi = HalfBlend(HiMask);
9362 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9363 }
9365 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9366 ///
9367 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9368 /// isn't available.
9369 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9370 const X86Subtarget *Subtarget,
9371 SelectionDAG &DAG) {
9372 SDLoc DL(Op);
9373 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9374 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9375 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9376 ArrayRef<int> Mask = SVOp->getMask();
9377 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9379 if (is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask))
9380 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9382 if (isSingleInputShuffleMask(Mask)) {
9383 // Non-half-crossing single input shuffles can be lowerid with an
9384 // interleaved permutation.
9385 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
9386 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
9387 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
9388 DAG.getConstant(VPERMILPMask, MVT::i8));
9389 }
9391 // X86 has dedicated unpack instructions that can handle specific blend
9392 // operations: UNPCKH and UNPCKL.
9393 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
9394 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
9395 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
9396 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
9398 // If we have a single input to the zero element, insert that into V1 if we
9399 // can do so cheaply.
9400 int NumV2Elements =
9401 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
9402 if (NumV2Elements == 1 && Mask[0] >= 4)
9403 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
9404 MVT::v4f64, DL, V1, V2, Mask, Subtarget, DAG))
9405 return Insertion;
9407 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
9408 Subtarget, DAG))
9409 return Blend;
9411 // Check if the blend happens to exactly fit that of SHUFPD.
9412 if (Mask[0] < 4 && (Mask[1] == -1 || Mask[1] >= 4) &&
9413 Mask[2] < 4 && (Mask[3] == -1 || Mask[3] >= 4)) {
9414 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
9415 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
9416 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
9417 DAG.getConstant(SHUFPDMask, MVT::i8));
9418 }
9419 if ((Mask[0] == -1 || Mask[0] >= 4) && Mask[1] < 4 &&
9420 (Mask[2] == -1 || Mask[2] >= 4) && Mask[3] < 4) {
9421 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
9422 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
9423 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
9424 DAG.getConstant(SHUFPDMask, MVT::i8));
9425 }
9427 // Otherwise fall back on generic blend lowering.
9428 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
9429 Mask, DAG);
9430 }
9432 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
9433 ///
9434 /// This routine is only called when we have AVX2 and thus a reasonable
9435 /// instruction set for v4i64 shuffling..
9436 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9437 const X86Subtarget *Subtarget,
9438 SelectionDAG &DAG) {
9439 SDLoc DL(Op);
9440 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9441 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9442 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9443 ArrayRef<int> Mask = SVOp->getMask();
9444 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9445 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
9447 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
9448 Subtarget, DAG))
9449 return Blend;
9451 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
9452 // use lower latency instructions that will operate on both 128-bit lanes.
9453 SmallVector<int, 2> RepeatedMask;
9454 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
9455 if (isSingleInputShuffleMask(Mask)) {
9456 int PSHUFDMask[] = {-1, -1, -1, -1};
9457 for (int i = 0; i < 2; ++i)
9458 if (RepeatedMask[i] >= 0) {
9459 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
9460 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
9461 }
9462 return DAG.getNode(
9463 ISD::BITCAST, DL, MVT::v4i64,
9464 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
9465 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
9466 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
9467 }
9469 // Use dedicated unpack instructions for masks that match their pattern.
9470 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
9471 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
9472 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
9473 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
9474 }
9476 // AVX2 provides a direct instruction for permuting a single input across
9477 // lanes.
9478 if (isSingleInputShuffleMask(Mask))
9479 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
9480 getV4X86ShuffleImm8ForMask(Mask, DAG));
9482 // Otherwise fall back on generic blend lowering.
9483 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
9484 Mask, DAG);
9485 }
9487 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
9488 ///
9489 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
9490 /// isn't available.
9491 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9492 const X86Subtarget *Subtarget,
9493 SelectionDAG &DAG) {
9494 SDLoc DL(Op);
9495 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9496 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9497 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9498 ArrayRef<int> Mask = SVOp->getMask();
9499 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9501 if (is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
9502 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9504 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
9505 Subtarget, DAG))
9506 return Blend;
9508 // If the shuffle mask is repeated in each 128-bit lane, we have many more
9509 // options to efficiently lower the shuffle.
9510 SmallVector<int, 2> RepeatedMask;
9511 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
9512 if (isSingleInputShuffleMask(Mask))
9513 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
9514 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
9516 // Use dedicated unpack instructions for masks that match their pattern.
9517 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
9518 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
9519 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
9520 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
9522 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
9523 // have already handled any direct blends.
9524 int SHUFPSMask[] = {Mask[0], Mask[1], Mask[2], Mask[3]};
9525 for (int &M : SHUFPSMask)
9526 if (M >= 8)
9527 M -= 4;
9528 return lowerVectorShuffleWithSHUPFS(DL, MVT::v8f32, SHUFPSMask, V1, V2, DAG);
9529 }
9531 // If we have a single input shuffle with different shuffle patterns in the
9532 // two 128-bit lanes use the variable mask to VPERMILPS.
9533 if (isSingleInputShuffleMask(Mask)) {
9534 SDValue VPermMask[8];
9535 for (int i = 0; i < 8; ++i)
9536 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9537 : DAG.getConstant(Mask[i], MVT::i32);
9538 return DAG.getNode(
9539 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
9540 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
9541 }
9543 // Otherwise fall back on generic blend lowering.
9544 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
9545 Mask, DAG);
9546 }
9548 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
9549 ///
9550 /// This routine is only called when we have AVX2 and thus a reasonable
9551 /// instruction set for v8i32 shuffling..
9552 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9553 const X86Subtarget *Subtarget,
9554 SelectionDAG &DAG) {
9555 SDLoc DL(Op);
9556 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9557 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9558 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9559 ArrayRef<int> Mask = SVOp->getMask();
9560 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9561 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
9563 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
9564 Subtarget, DAG))
9565 return Blend;
9567 // If the shuffle mask is repeated in each 128-bit lane we can use more
9568 // efficient instructions that mirror the shuffles across the two 128-bit
9569 // lanes.
9570 SmallVector<int, 4> RepeatedMask;
9571 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
9572 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
9573 if (isSingleInputShuffleMask(Mask))
9574 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
9575 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
9577 // Use dedicated unpack instructions for masks that match their pattern.
9578 if (isShuffleEquivalent(Mask, 0, 8, 1, 9))
9579 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
9580 if (isShuffleEquivalent(Mask, 2, 10, 3, 11))
9581 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
9582 }
9584 // If the shuffle patterns aren't repeated but it is a single input, directly
9585 // generate a cross-lane VPERMD instruction.
9586 if (isSingleInputShuffleMask(Mask)) {
9587 SDValue VPermMask[8];
9588 for (int i = 0; i < 8; ++i)
9589 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9590 : DAG.getConstant(Mask[i], MVT::i32);
9591 return DAG.getNode(
9592 X86ISD::VPERMV, DL, MVT::v8i32,
9593 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
9594 }
9596 // Otherwise fall back on generic blend lowering.
9597 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
9598 Mask, DAG);
9599 }
9601 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
9602 ///
9603 /// This routine is only called when we have AVX2 and thus a reasonable
9604 /// instruction set for v16i16 shuffling..
9605 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9606 const X86Subtarget *Subtarget,
9607 SelectionDAG &DAG) {
9608 SDLoc DL(Op);
9609 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9610 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9611 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9612 ArrayRef<int> Mask = SVOp->getMask();
9613 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9614 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
9616 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
9617 Subtarget, DAG))
9618 return Blend;
9620 // If the shuffle mask is repeated in each 128-bit lane we can use more
9621 // efficient instructions that mirror the shuffles across the two 128-bit
9622 // lanes.
9623 SmallVector<int, 4> RepeatedMask;
9624 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
9625 assert(RepeatedMask.size() == 8 && "Unexpected repeated mask size!");
9626 // FIXME: It might be worth it to call into the (terribly complex) v8i16
9627 // lowering here.
9629 // Use dedicated unpack instructions for masks that match their pattern.
9630 //
9631 if (isShuffleEquivalent(Mask,
9632 // First 128-bit lane:
9633 0, 16, 1, 17, 2, 18, 3, 19,
9634 // Second 128-bit lane:
9635 8, 24, 9, 25, 10, 26, 11, 27))
9636 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
9637 if (isShuffleEquivalent(Mask,
9638 // First 128-bit lane:
9639 4, 20, 5, 21, 6, 22, 7, 23,
9640 // Second 128-bit lane:
9641 12, 28, 13, 29, 14, 30, 15, 31))
9642 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
9643 }
9645 // There are no generalized cross-lane shuffle operations available on i16
9646 // element types.
9647 // FIXME: We should teach the "split and lower" path to do something more
9648 // clever, or do it ourselves here. The optimal lowering of cross-lane
9649 // shuffles I am aware of is to swap the lanes into a copy, shuffle both the
9650 // original and the copy, and then blend to pick up the cross-lane elements.
9651 // This is four instructions with a tree height of three which is better than
9652 // the worst case for a gather-cross-scatter approach such as used in SSE2
9653 // v8i16 lowering (where we don't have blends). While for cross-lane blends it
9654 // results in a blend tree, blends are very cheap in AVX2 and newer chips. We
9655 // might also want to special case situations where we can always do a single
9656 // VPERMD to produce a non-lane-crossing shuffle.
9657 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
9658 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9660 if (isSingleInputShuffleMask(Mask)) {
9661 SDValue PSHUFBMask[32];
9662 for (int i = 0; i < 16; ++i) {
9663 if (Mask[i] == -1) {
9664 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
9665 continue;
9666 }
9668 int M = i < 8 ? Mask[i] : Mask[i] - 8;
9669 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
9670 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, MVT::i8);
9671 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, MVT::i8);
9672 }
9673 return DAG.getNode(
9674 ISD::BITCAST, DL, MVT::v16i16,
9675 DAG.getNode(
9676 X86ISD::PSHUFB, DL, MVT::v32i8,
9677 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
9678 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
9679 }
9681 // Otherwise fall back on generic blend lowering.
9682 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i16, V1, V2,
9683 Mask, DAG);
9684 }
9686 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
9687 ///
9688 /// This routine is only called when we have AVX2 and thus a reasonable
9689 /// instruction set for v32i8 shuffling..
9690 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9691 const X86Subtarget *Subtarget,
9692 SelectionDAG &DAG) {
9693 SDLoc DL(Op);
9694 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9695 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9696 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9697 ArrayRef<int> Mask = SVOp->getMask();
9698 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
9699 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
9701 // FIXME: Actually implement this using AVX2!!!
9702 (void)Mask;
9703 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9704 }
9706 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
9707 ///
9708 /// This routine either breaks down the specific type of a 256-bit x86 vector
9709 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
9710 /// together based on the available instructions.
9711 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9712 MVT VT, const X86Subtarget *Subtarget,
9713 SelectionDAG &DAG) {
9714 SDLoc DL(Op);
9715 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9716 ArrayRef<int> Mask = SVOp->getMask();
9718 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
9719 // check for those subtargets here and avoid much of the subtarget querying in
9720 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
9721 // ability to manipulate a 256-bit vector with integer types. Since we'll use
9722 // floating point types there eventually, just immediately cast everything to
9723 // a float and operate entirely in that domain.
9724 if (VT.isInteger() && !Subtarget->hasAVX2()) {
9725 int ElementBits = VT.getScalarSizeInBits();
9726 if (ElementBits < 32)
9727 // No floating point type available, decompose into 128-bit vectors.
9728 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9730 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
9731 VT.getVectorNumElements());
9732 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
9733 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
9734 return DAG.getNode(ISD::BITCAST, DL, VT,
9735 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
9736 }
9738 switch (VT.SimpleTy) {
9739 case MVT::v4f64:
9740 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9741 case MVT::v4i64:
9742 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9743 case MVT::v8f32:
9744 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9745 case MVT::v8i32:
9746 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9747 case MVT::v16i16:
9748 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9749 case MVT::v32i8:
9750 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9752 default:
9753 llvm_unreachable("Not a valid 256-bit x86 vector type!");
9754 }
9755 }
9757 /// \brief Tiny helper function to test whether a shuffle mask could be
9758 /// simplified by widening the elements being shuffled.
9759 static bool canWidenShuffleElements(ArrayRef<int> Mask) {
9760 for (int i = 0, Size = Mask.size(); i < Size; i += 2)
9761 if ((Mask[i] != -1 && Mask[i] % 2 != 0) ||
9762 (Mask[i + 1] != -1 && (Mask[i + 1] % 2 != 1 ||
9763 (Mask[i] != -1 && Mask[i] + 1 != Mask[i + 1]))))
9764 return false;
9766 return true;
9767 }
9769 /// \brief Top-level lowering for x86 vector shuffles.
9770 ///
9771 /// This handles decomposition, canonicalization, and lowering of all x86
9772 /// vector shuffles. Most of the specific lowering strategies are encapsulated
9773 /// above in helper routines. The canonicalization attempts to widen shuffles
9774 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
9775 /// s.t. only one of the two inputs needs to be tested, etc.
9776 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
9777 SelectionDAG &DAG) {
9778 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9779 ArrayRef<int> Mask = SVOp->getMask();
9780 SDValue V1 = Op.getOperand(0);
9781 SDValue V2 = Op.getOperand(1);
9782 MVT VT = Op.getSimpleValueType();
9783 int NumElements = VT.getVectorNumElements();
9784 SDLoc dl(Op);
9786 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
9788 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
9789 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
9790 if (V1IsUndef && V2IsUndef)
9791 return DAG.getUNDEF(VT);
9793 // When we create a shuffle node we put the UNDEF node to second operand,
9794 // but in some cases the first operand may be transformed to UNDEF.
9795 // In this case we should just commute the node.
9796 if (V1IsUndef)
9797 return DAG.getCommutedVectorShuffle(*SVOp);
9799 // Check for non-undef masks pointing at an undef vector and make the masks
9800 // undef as well. This makes it easier to match the shuffle based solely on
9801 // the mask.
9802 if (V2IsUndef)
9803 for (int M : Mask)
9804 if (M >= NumElements) {
9805 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
9806 for (int &M : NewMask)
9807 if (M >= NumElements)
9808 M = -1;
9809 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
9810 }
9812 // For integer vector shuffles, try to collapse them into a shuffle of fewer
9813 // lanes but wider integers. We cap this to not form integers larger than i64
9814 // but it might be interesting to form i128 integers to handle flipping the
9815 // low and high halves of AVX 256-bit vectors.
9816 if (VT.isInteger() && VT.getScalarSizeInBits() < 64 &&
9817 canWidenShuffleElements(Mask)) {
9818 SmallVector<int, 8> NewMask;
9819 for (int i = 0, Size = Mask.size(); i < Size; i += 2)
9820 NewMask.push_back(Mask[i] != -1
9821 ? Mask[i] / 2
9822 : (Mask[i + 1] != -1 ? Mask[i + 1] / 2 : -1));
9823 MVT NewVT =
9824 MVT::getVectorVT(MVT::getIntegerVT(VT.getScalarSizeInBits() * 2),
9825 VT.getVectorNumElements() / 2);
9826 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
9827 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
9828 return DAG.getNode(ISD::BITCAST, dl, VT,
9829 DAG.getVectorShuffle(NewVT, dl, V1, V2, NewMask));
9830 }
9832 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
9833 for (int M : SVOp->getMask())
9834 if (M < 0)
9835 ++NumUndefElements;
9836 else if (M < NumElements)
9837 ++NumV1Elements;
9838 else
9839 ++NumV2Elements;
9841 // Commute the shuffle as needed such that more elements come from V1 than
9842 // V2. This allows us to match the shuffle pattern strictly on how many
9843 // elements come from V1 without handling the symmetric cases.
9844 if (NumV2Elements > NumV1Elements)
9845 return DAG.getCommutedVectorShuffle(*SVOp);
9847 // When the number of V1 and V2 elements are the same, try to minimize the
9848 // number of uses of V2 in the low half of the vector. When that is tied,
9849 // ensure that the sum of indices for V1 is equal to or lower than the sum
9850 // indices for V2.
9851 if (NumV1Elements == NumV2Elements) {
9852 int LowV1Elements = 0, LowV2Elements = 0;
9853 for (int M : SVOp->getMask().slice(0, NumElements / 2))
9854 if (M >= NumElements)
9855 ++LowV2Elements;
9856 else if (M >= 0)
9857 ++LowV1Elements;
9858 if (LowV2Elements > LowV1Elements)
9859 return DAG.getCommutedVectorShuffle(*SVOp);
9861 int SumV1Indices = 0, SumV2Indices = 0;
9862 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
9863 if (SVOp->getMask()[i] >= NumElements)
9864 SumV2Indices += i;
9865 else if (SVOp->getMask()[i] >= 0)
9866 SumV1Indices += i;
9867 if (SumV2Indices < SumV1Indices)
9868 return DAG.getCommutedVectorShuffle(*SVOp);
9869 }
9871 // For each vector width, delegate to a specialized lowering routine.
9872 if (VT.getSizeInBits() == 128)
9873 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
9875 if (VT.getSizeInBits() == 256)
9876 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
9878 llvm_unreachable("Unimplemented!");
9879 }
9882 //===----------------------------------------------------------------------===//
9883 // Legacy vector shuffle lowering
9884 //
9885 // This code is the legacy code handling vector shuffles until the above
9886 // replaces its functionality and performance.
9887 //===----------------------------------------------------------------------===//
9889 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
9890 bool hasInt256, unsigned *MaskOut = nullptr) {
9891 MVT EltVT = VT.getVectorElementType();
9893 // There is no blend with immediate in AVX-512.
9894 if (VT.is512BitVector())
9895 return false;
9897 if (!hasSSE41 || EltVT == MVT::i8)
9898 return false;
9899 if (!hasInt256 && VT == MVT::v16i16)
9900 return false;
9902 unsigned MaskValue = 0;
9903 unsigned NumElems = VT.getVectorNumElements();
9904 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
9905 unsigned NumLanes = (NumElems - 1) / 8 + 1;
9906 unsigned NumElemsInLane = NumElems / NumLanes;
9908 // Blend for v16i16 should be symetric for the both lanes.
9909 for (unsigned i = 0; i < NumElemsInLane; ++i) {
9911 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
9912 int EltIdx = MaskVals[i];
9914 if ((EltIdx < 0 || EltIdx == (int)i) &&
9915 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
9916 continue;
9918 if (((unsigned)EltIdx == (i + NumElems)) &&
9919 (SndLaneEltIdx < 0 ||
9920 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
9921 MaskValue |= (1 << i);
9922 else
9923 return false;
9924 }
9926 if (MaskOut)
9927 *MaskOut = MaskValue;
9928 return true;
9929 }
9931 // Try to lower a shuffle node into a simple blend instruction.
9932 // This function assumes isBlendMask returns true for this
9933 // SuffleVectorSDNode
9934 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
9935 unsigned MaskValue,
9936 const X86Subtarget *Subtarget,
9937 SelectionDAG &DAG) {
9938 MVT VT = SVOp->getSimpleValueType(0);
9939 MVT EltVT = VT.getVectorElementType();
9940 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
9941 Subtarget->hasInt256() && "Trying to lower a "
9942 "VECTOR_SHUFFLE to a Blend but "
9943 "with the wrong mask"));
9944 SDValue V1 = SVOp->getOperand(0);
9945 SDValue V2 = SVOp->getOperand(1);
9946 SDLoc dl(SVOp);
9947 unsigned NumElems = VT.getVectorNumElements();
9949 // Convert i32 vectors to floating point if it is not AVX2.
9950 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
9951 MVT BlendVT = VT;
9952 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
9953 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
9954 NumElems);
9955 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
9956 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
9957 }
9959 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
9960 DAG.getConstant(MaskValue, MVT::i32));
9961 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
9962 }
9964 /// In vector type \p VT, return true if the element at index \p InputIdx
9965 /// falls on a different 128-bit lane than \p OutputIdx.
9966 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
9967 unsigned OutputIdx) {
9968 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
9969 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
9970 }
9972 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
9973 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
9974 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
9975 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
9976 /// zero.
9977 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
9978 SelectionDAG &DAG) {
9979 MVT VT = V1.getSimpleValueType();
9980 assert(VT.is128BitVector() || VT.is256BitVector());
9982 MVT EltVT = VT.getVectorElementType();
9983 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
9984 unsigned NumElts = VT.getVectorNumElements();
9986 SmallVector<SDValue, 32> PshufbMask;
9987 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
9988 int InputIdx = MaskVals[OutputIdx];
9989 unsigned InputByteIdx;
9991 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
9992 InputByteIdx = 0x80;
9993 else {
9994 // Cross lane is not allowed.
9995 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
9996 return SDValue();
9997 InputByteIdx = InputIdx * EltSizeInBytes;
9998 // Index is an byte offset within the 128-bit lane.
9999 InputByteIdx &= 0xf;
10000 }
10002 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
10003 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
10004 if (InputByteIdx != 0x80)
10005 ++InputByteIdx;
10006 }
10007 }
10009 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
10010 if (ShufVT != VT)
10011 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
10012 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
10013 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
10014 }
10016 // v8i16 shuffles - Prefer shuffles in the following order:
10017 // 1. [all] pshuflw, pshufhw, optional move
10018 // 2. [ssse3] 1 x pshufb
10019 // 3. [ssse3] 2 x pshufb + 1 x por
10020 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
10021 static SDValue
10022 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
10023 SelectionDAG &DAG) {
10024 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10025 SDValue V1 = SVOp->getOperand(0);
10026 SDValue V2 = SVOp->getOperand(1);
10027 SDLoc dl(SVOp);
10028 SmallVector<int, 8> MaskVals;
10030 // Determine if more than 1 of the words in each of the low and high quadwords
10031 // of the result come from the same quadword of one of the two inputs. Undef
10032 // mask values count as coming from any quadword, for better codegen.
10033 //
10034 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
10035 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
10036 unsigned LoQuad[] = { 0, 0, 0, 0 };
10037 unsigned HiQuad[] = { 0, 0, 0, 0 };
10038 // Indices of quads used.
10039 std::bitset<4> InputQuads;
10040 for (unsigned i = 0; i < 8; ++i) {
10041 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
10042 int EltIdx = SVOp->getMaskElt(i);
10043 MaskVals.push_back(EltIdx);
10044 if (EltIdx < 0) {
10045 ++Quad[0];
10046 ++Quad[1];
10047 ++Quad[2];
10048 ++Quad[3];
10049 continue;
10050 }
10051 ++Quad[EltIdx / 4];
10052 InputQuads.set(EltIdx / 4);
10053 }
10055 int BestLoQuad = -1;
10056 unsigned MaxQuad = 1;
10057 for (unsigned i = 0; i < 4; ++i) {
10058 if (LoQuad[i] > MaxQuad) {
10059 BestLoQuad = i;
10060 MaxQuad = LoQuad[i];
10061 }
10062 }
10064 int BestHiQuad = -1;
10065 MaxQuad = 1;
10066 for (unsigned i = 0; i < 4; ++i) {
10067 if (HiQuad[i] > MaxQuad) {
10068 BestHiQuad = i;
10069 MaxQuad = HiQuad[i];
10070 }
10071 }
10073 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
10074 // of the two input vectors, shuffle them into one input vector so only a
10075 // single pshufb instruction is necessary. If there are more than 2 input
10076 // quads, disable the next transformation since it does not help SSSE3.
10077 bool V1Used = InputQuads[0] || InputQuads[1];
10078 bool V2Used = InputQuads[2] || InputQuads[3];
10079 if (Subtarget->hasSSSE3()) {
10080 if (InputQuads.count() == 2 && V1Used && V2Used) {
10081 BestLoQuad = InputQuads[0] ? 0 : 1;
10082 BestHiQuad = InputQuads[2] ? 2 : 3;
10083 }
10084 if (InputQuads.count() > 2) {
10085 BestLoQuad = -1;
10086 BestHiQuad = -1;
10087 }
10088 }
10090 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
10091 // the shuffle mask. If a quad is scored as -1, that means that it contains
10092 // words from all 4 input quadwords.
10093 SDValue NewV;
10094 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
10095 int MaskV[] = {
10096 BestLoQuad < 0 ? 0 : BestLoQuad,
10097 BestHiQuad < 0 ? 1 : BestHiQuad
10098 };
10099 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
10100 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
10101 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
10102 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
10104 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
10105 // source words for the shuffle, to aid later transformations.
10106 bool AllWordsInNewV = true;
10107 bool InOrder[2] = { true, true };
10108 for (unsigned i = 0; i != 8; ++i) {
10109 int idx = MaskVals[i];
10110 if (idx != (int)i)
10111 InOrder[i/4] = false;
10112 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
10113 continue;
10114 AllWordsInNewV = false;
10115 break;
10116 }
10118 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
10119 if (AllWordsInNewV) {
10120 for (int i = 0; i != 8; ++i) {
10121 int idx = MaskVals[i];
10122 if (idx < 0)
10123 continue;
10124 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
10125 if ((idx != i) && idx < 4)
10126 pshufhw = false;
10127 if ((idx != i) && idx > 3)
10128 pshuflw = false;
10129 }
10130 V1 = NewV;
10131 V2Used = false;
10132 BestLoQuad = 0;
10133 BestHiQuad = 1;
10134 }
10136 // If we've eliminated the use of V2, and the new mask is a pshuflw or
10137 // pshufhw, that's as cheap as it gets. Return the new shuffle.
10138 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
10139 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
10140 unsigned TargetMask = 0;
10141 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
10142 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
10143 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10144 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
10145 getShufflePSHUFLWImmediate(SVOp);
10146 V1 = NewV.getOperand(0);
10147 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
10148 }
10149 }
10151 // Promote splats to a larger type which usually leads to more efficient code.
10152 // FIXME: Is this true if pshufb is available?
10153 if (SVOp->isSplat())
10154 return PromoteSplat(SVOp, DAG);
10156 // If we have SSSE3, and all words of the result are from 1 input vector,
10157 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
10158 // is present, fall back to case 4.
10159 if (Subtarget->hasSSSE3()) {
10160 SmallVector<SDValue,16> pshufbMask;
10162 // If we have elements from both input vectors, set the high bit of the
10163 // shuffle mask element to zero out elements that come from V2 in the V1
10164 // mask, and elements that come from V1 in the V2 mask, so that the two
10165 // results can be OR'd together.
10166 bool TwoInputs = V1Used && V2Used;
10167 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
10168 if (!TwoInputs)
10169 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10171 // Calculate the shuffle mask for the second input, shuffle it, and
10172 // OR it with the first shuffled input.
10173 CommuteVectorShuffleMask(MaskVals, 8);
10174 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
10175 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
10176 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10177 }
10179 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
10180 // and update MaskVals with new element order.
10181 std::bitset<8> InOrder;
10182 if (BestLoQuad >= 0) {
10183 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
10184 for (int i = 0; i != 4; ++i) {
10185 int idx = MaskVals[i];
10186 if (idx < 0) {
10187 InOrder.set(i);
10188 } else if ((idx / 4) == BestLoQuad) {
10189 MaskV[i] = idx & 3;
10190 InOrder.set(i);
10191 }
10192 }
10193 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
10194 &MaskV[0]);
10196 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
10197 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10198 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
10199 NewV.getOperand(0),
10200 getShufflePSHUFLWImmediate(SVOp), DAG);
10201 }
10202 }
10204 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
10205 // and update MaskVals with the new element order.
10206 if (BestHiQuad >= 0) {
10207 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
10208 for (unsigned i = 4; i != 8; ++i) {
10209 int idx = MaskVals[i];
10210 if (idx < 0) {
10211 InOrder.set(i);
10212 } else if ((idx / 4) == BestHiQuad) {
10213 MaskV[i] = (idx & 3) + 4;
10214 InOrder.set(i);
10215 }
10216 }
10217 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
10218 &MaskV[0]);
10220 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
10221 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10222 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
10223 NewV.getOperand(0),
10224 getShufflePSHUFHWImmediate(SVOp), DAG);
10225 }
10226 }
10228 // In case BestHi & BestLo were both -1, which means each quadword has a word
10229 // from each of the four input quadwords, calculate the InOrder bitvector now
10230 // before falling through to the insert/extract cleanup.
10231 if (BestLoQuad == -1 && BestHiQuad == -1) {
10232 NewV = V1;
10233 for (int i = 0; i != 8; ++i)
10234 if (MaskVals[i] < 0 || MaskVals[i] == i)
10235 InOrder.set(i);
10236 }
10238 // The other elements are put in the right place using pextrw and pinsrw.
10239 for (unsigned i = 0; i != 8; ++i) {
10240 if (InOrder[i])
10241 continue;
10242 int EltIdx = MaskVals[i];
10243 if (EltIdx < 0)
10244 continue;
10245 SDValue ExtOp = (EltIdx < 8) ?
10246 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
10247 DAG.getIntPtrConstant(EltIdx)) :
10248 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
10249 DAG.getIntPtrConstant(EltIdx - 8));
10250 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
10251 DAG.getIntPtrConstant(i));
10252 }
10253 return NewV;
10254 }
10256 /// \brief v16i16 shuffles
10257 ///
10258 /// FIXME: We only support generation of a single pshufb currently. We can
10259 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
10260 /// well (e.g 2 x pshufb + 1 x por).
10261 static SDValue
10262 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
10263 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10264 SDValue V1 = SVOp->getOperand(0);
10265 SDValue V2 = SVOp->getOperand(1);
10266 SDLoc dl(SVOp);
10268 if (V2.getOpcode() != ISD::UNDEF)
10269 return SDValue();
10271 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
10272 return getPSHUFB(MaskVals, V1, dl, DAG);
10273 }
10275 // v16i8 shuffles - Prefer shuffles in the following order:
10276 // 1. [ssse3] 1 x pshufb
10277 // 2. [ssse3] 2 x pshufb + 1 x por
10278 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
10279 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
10280 const X86Subtarget* Subtarget,
10281 SelectionDAG &DAG) {
10282 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10283 SDValue V1 = SVOp->getOperand(0);
10284 SDValue V2 = SVOp->getOperand(1);
10285 SDLoc dl(SVOp);
10286 ArrayRef<int> MaskVals = SVOp->getMask();
10288 // Promote splats to a larger type which usually leads to more efficient code.
10289 // FIXME: Is this true if pshufb is available?
10290 if (SVOp->isSplat())
10291 return PromoteSplat(SVOp, DAG);
10293 // If we have SSSE3, case 1 is generated when all result bytes come from
10294 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
10295 // present, fall back to case 3.
10297 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
10298 if (Subtarget->hasSSSE3()) {
10299 SmallVector<SDValue,16> pshufbMask;
10301 // If all result elements are from one input vector, then only translate
10302 // undef mask values to 0x80 (zero out result) in the pshufb mask.
10303 //
10304 // Otherwise, we have elements from both input vectors, and must zero out
10305 // elements that come from V2 in the first mask, and V1 in the second mask
10306 // so that we can OR them together.
10307 for (unsigned i = 0; i != 16; ++i) {
10308 int EltIdx = MaskVals[i];
10309 if (EltIdx < 0 || EltIdx >= 16)
10310 EltIdx = 0x80;
10311 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
10312 }
10313 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
10314 DAG.getNode(ISD::BUILD_VECTOR, dl,
10315 MVT::v16i8, pshufbMask));
10317 // As PSHUFB will zero elements with negative indices, it's safe to ignore
10318 // the 2nd operand if it's undefined or zero.
10319 if (V2.getOpcode() == ISD::UNDEF ||
10320 ISD::isBuildVectorAllZeros(V2.getNode()))
10321 return V1;
10323 // Calculate the shuffle mask for the second input, shuffle it, and
10324 // OR it with the first shuffled input.
10325 pshufbMask.clear();
10326 for (unsigned i = 0; i != 16; ++i) {
10327 int EltIdx = MaskVals[i];
10328 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
10329 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
10330 }
10331 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
10332 DAG.getNode(ISD::BUILD_VECTOR, dl,
10333 MVT::v16i8, pshufbMask));
10334 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
10335 }
10337 // No SSSE3 - Calculate in place words and then fix all out of place words
10338 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
10339 // the 16 different words that comprise the two doublequadword input vectors.
10340 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10341 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
10342 SDValue NewV = V1;
10343 for (int i = 0; i != 8; ++i) {
10344 int Elt0 = MaskVals[i*2];
10345 int Elt1 = MaskVals[i*2+1];
10347 // This word of the result is all undef, skip it.
10348 if (Elt0 < 0 && Elt1 < 0)
10349 continue;
10351 // This word of the result is already in the correct place, skip it.
10352 if ((Elt0 == i*2) && (Elt1 == i*2+1))
10353 continue;
10355 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
10356 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
10357 SDValue InsElt;
10359 // If Elt0 and Elt1 are defined, are consecutive, and can be load
10360 // using a single extract together, load it and store it.
10361 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
10362 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
10363 DAG.getIntPtrConstant(Elt1 / 2));
10364 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
10365 DAG.getIntPtrConstant(i));
10366 continue;
10367 }
10369 // If Elt1 is defined, extract it from the appropriate source. If the
10370 // source byte is not also odd, shift the extracted word left 8 bits
10371 // otherwise clear the bottom 8 bits if we need to do an or.
10372 if (Elt1 >= 0) {
10373 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
10374 DAG.getIntPtrConstant(Elt1 / 2));
10375 if ((Elt1 & 1) == 0)
10376 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
10377 DAG.getConstant(8,
10378 TLI.getShiftAmountTy(InsElt.getValueType())));
10379 else if (Elt0 >= 0)
10380 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
10381 DAG.getConstant(0xFF00, MVT::i16));
10382 }
10383 // If Elt0 is defined, extract it from the appropriate source. If the
10384 // source byte is not also even, shift the extracted word right 8 bits. If
10385 // Elt1 was also defined, OR the extracted values together before
10386 // inserting them in the result.
10387 if (Elt0 >= 0) {
10388 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
10389 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
10390 if ((Elt0 & 1) != 0)
10391 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
10392 DAG.getConstant(8,
10393 TLI.getShiftAmountTy(InsElt0.getValueType())));
10394 else if (Elt1 >= 0)
10395 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
10396 DAG.getConstant(0x00FF, MVT::i16));
10397 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
10398 : InsElt0;
10399 }
10400 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
10401 DAG.getIntPtrConstant(i));
10402 }
10403 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
10404 }
10406 // v32i8 shuffles - Translate to VPSHUFB if possible.
10407 static
10408 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
10409 const X86Subtarget *Subtarget,
10410 SelectionDAG &DAG) {
10411 MVT VT = SVOp->getSimpleValueType(0);
10412 SDValue V1 = SVOp->getOperand(0);
10413 SDValue V2 = SVOp->getOperand(1);
10414 SDLoc dl(SVOp);
10415 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
10417 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10418 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
10419 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
10421 // VPSHUFB may be generated if
10422 // (1) one of input vector is undefined or zeroinitializer.
10423 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
10424 // And (2) the mask indexes don't cross the 128-bit lane.
10425 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
10426 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
10427 return SDValue();
10429 if (V1IsAllZero && !V2IsAllZero) {
10430 CommuteVectorShuffleMask(MaskVals, 32);
10431 V1 = V2;
10432 }
10433 return getPSHUFB(MaskVals, V1, dl, DAG);
10434 }
10436 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
10437 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
10438 /// done when every pair / quad of shuffle mask elements point to elements in
10439 /// the right sequence. e.g.
10440 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
10441 static
10442 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
10443 SelectionDAG &DAG) {
10444 MVT VT = SVOp->getSimpleValueType(0);
10445 SDLoc dl(SVOp);
10446 unsigned NumElems = VT.getVectorNumElements();
10447 MVT NewVT;
10448 unsigned Scale;
10449 switch (VT.SimpleTy) {
10450 default: llvm_unreachable("Unexpected!");
10451 case MVT::v2i64:
10452 case MVT::v2f64:
10453 return SDValue(SVOp, 0);
10454 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
10455 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
10456 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
10457 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
10458 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
10459 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
10460 }
10462 SmallVector<int, 8> MaskVec;
10463 for (unsigned i = 0; i != NumElems; i += Scale) {
10464 int StartIdx = -1;
10465 for (unsigned j = 0; j != Scale; ++j) {
10466 int EltIdx = SVOp->getMaskElt(i+j);
10467 if (EltIdx < 0)
10468 continue;
10469 if (StartIdx < 0)
10470 StartIdx = (EltIdx / Scale);
10471 if (EltIdx != (int)(StartIdx*Scale + j))
10472 return SDValue();
10473 }
10474 MaskVec.push_back(StartIdx);
10475 }
10477 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
10478 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
10479 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
10480 }
10482 /// getVZextMovL - Return a zero-extending vector move low node.
10483 ///
10484 static SDValue getVZextMovL(MVT VT, MVT OpVT,
10485 SDValue SrcOp, SelectionDAG &DAG,
10486 const X86Subtarget *Subtarget, SDLoc dl) {
10487 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
10488 LoadSDNode *LD = nullptr;
10489 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
10490 LD = dyn_cast<LoadSDNode>(SrcOp);
10491 if (!LD) {
10492 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
10493 // instead.
10494 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
10495 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
10496 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
10497 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
10498 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
10499 // PR2108
10500 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
10501 return DAG.getNode(ISD::BITCAST, dl, VT,
10502 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
10503 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
10504 OpVT,
10505 SrcOp.getOperand(0)
10506 .getOperand(0))));
10507 }
10508 }
10509 }
10511 return DAG.getNode(ISD::BITCAST, dl, VT,
10512 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
10513 DAG.getNode(ISD::BITCAST, dl,
10514 OpVT, SrcOp)));
10515 }
10517 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
10518 /// which could not be matched by any known target speficic shuffle
10519 static SDValue
10520 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
10522 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
10523 if (NewOp.getNode())
10524 return NewOp;
10526 MVT VT = SVOp->getSimpleValueType(0);
10528 unsigned NumElems = VT.getVectorNumElements();
10529 unsigned NumLaneElems = NumElems / 2;
10531 SDLoc dl(SVOp);
10532 MVT EltVT = VT.getVectorElementType();
10533 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
10534 SDValue Output[2];
10536 SmallVector<int, 16> Mask;
10537 for (unsigned l = 0; l < 2; ++l) {
10538 // Build a shuffle mask for the output, discovering on the fly which
10539 // input vectors to use as shuffle operands (recorded in InputUsed).
10540 // If building a suitable shuffle vector proves too hard, then bail
10541 // out with UseBuildVector set.
10542 bool UseBuildVector = false;
10543 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
10544 unsigned LaneStart = l * NumLaneElems;
10545 for (unsigned i = 0; i != NumLaneElems; ++i) {
10546 // The mask element. This indexes into the input.
10547 int Idx = SVOp->getMaskElt(i+LaneStart);
10548 if (Idx < 0) {
10549 // the mask element does not index into any input vector.
10550 Mask.push_back(-1);
10551 continue;
10552 }
10554 // The input vector this mask element indexes into.
10555 int Input = Idx / NumLaneElems;
10557 // Turn the index into an offset from the start of the input vector.
10558 Idx -= Input * NumLaneElems;
10560 // Find or create a shuffle vector operand to hold this input.
10561 unsigned OpNo;
10562 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
10563 if (InputUsed[OpNo] == Input)
10564 // This input vector is already an operand.
10565 break;
10566 if (InputUsed[OpNo] < 0) {
10567 // Create a new operand for this input vector.
10568 InputUsed[OpNo] = Input;
10569 break;
10570 }
10571 }
10573 if (OpNo >= array_lengthof(InputUsed)) {
10574 // More than two input vectors used! Give up on trying to create a
10575 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
10576 UseBuildVector = true;
10577 break;
10578 }
10580 // Add the mask index for the new shuffle vector.
10581 Mask.push_back(Idx + OpNo * NumLaneElems);
10582 }
10584 if (UseBuildVector) {
10585 SmallVector<SDValue, 16> SVOps;
10586 for (unsigned i = 0; i != NumLaneElems; ++i) {
10587 // The mask element. This indexes into the input.
10588 int Idx = SVOp->getMaskElt(i+LaneStart);
10589 if (Idx < 0) {
10590 SVOps.push_back(DAG.getUNDEF(EltVT));
10591 continue;
10592 }
10594 // The input vector this mask element indexes into.
10595 int Input = Idx / NumElems;
10597 // Turn the index into an offset from the start of the input vector.
10598 Idx -= Input * NumElems;
10600 // Extract the vector element by hand.
10601 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
10602 SVOp->getOperand(Input),
10603 DAG.getIntPtrConstant(Idx)));
10604 }
10606 // Construct the output using a BUILD_VECTOR.
10607 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
10608 } else if (InputUsed[0] < 0) {
10609 // No input vectors were used! The result is undefined.
10610 Output[l] = DAG.getUNDEF(NVT);
10611 } else {
10612 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
10613 (InputUsed[0] % 2) * NumLaneElems,
10614 DAG, dl);
10615 // If only one input was used, use an undefined vector for the other.
10616 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
10617 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
10618 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
10619 // At least one input vector was used. Create a new shuffle vector.
10620 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
10621 }
10623 Mask.clear();
10624 }
10626 // Concatenate the result back
10627 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
10628 }
10630 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
10631 /// 4 elements, and match them with several different shuffle types.
10632 static SDValue
10633 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
10634 SDValue V1 = SVOp->getOperand(0);
10635 SDValue V2 = SVOp->getOperand(1);
10636 SDLoc dl(SVOp);
10637 MVT VT = SVOp->getSimpleValueType(0);
10639 assert(VT.is128BitVector() && "Unsupported vector size");
10641 std::pair<int, int> Locs[4];
10642 int Mask1[] = { -1, -1, -1, -1 };
10643 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
10645 unsigned NumHi = 0;
10646 unsigned NumLo = 0;
10647 for (unsigned i = 0; i != 4; ++i) {
10648 int Idx = PermMask[i];
10649 if (Idx < 0) {
10650 Locs[i] = std::make_pair(-1, -1);
10651 } else {
10652 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
10653 if (Idx < 4) {
10654 Locs[i] = std::make_pair(0, NumLo);
10655 Mask1[NumLo] = Idx;
10656 NumLo++;
10657 } else {
10658 Locs[i] = std::make_pair(1, NumHi);
10659 if (2+NumHi < 4)
10660 Mask1[2+NumHi] = Idx;
10661 NumHi++;
10662 }
10663 }
10664 }
10666 if (NumLo <= 2 && NumHi <= 2) {
10667 // If no more than two elements come from either vector. This can be
10668 // implemented with two shuffles. First shuffle gather the elements.
10669 // The second shuffle, which takes the first shuffle as both of its
10670 // vector operands, put the elements into the right order.
10671 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
10673 int Mask2[] = { -1, -1, -1, -1 };
10675 for (unsigned i = 0; i != 4; ++i)
10676 if (Locs[i].first != -1) {
10677 unsigned Idx = (i < 2) ? 0 : 4;
10678 Idx += Locs[i].first * 2 + Locs[i].second;
10679 Mask2[i] = Idx;
10680 }
10682 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
10683 }
10685 if (NumLo == 3 || NumHi == 3) {
10686 // Otherwise, we must have three elements from one vector, call it X, and
10687 // one element from the other, call it Y. First, use a shufps to build an
10688 // intermediate vector with the one element from Y and the element from X
10689 // that will be in the same half in the final destination (the indexes don't
10690 // matter). Then, use a shufps to build the final vector, taking the half
10691 // containing the element from Y from the intermediate, and the other half
10692 // from X.
10693 if (NumHi == 3) {
10694 // Normalize it so the 3 elements come from V1.
10695 CommuteVectorShuffleMask(PermMask, 4);
10696 std::swap(V1, V2);
10697 }
10699 // Find the element from V2.
10700 unsigned HiIndex;
10701 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
10702 int Val = PermMask[HiIndex];
10703 if (Val < 0)
10704 continue;
10705 if (Val >= 4)
10706 break;
10707 }
10709 Mask1[0] = PermMask[HiIndex];
10710 Mask1[1] = -1;
10711 Mask1[2] = PermMask[HiIndex^1];
10712 Mask1[3] = -1;
10713 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
10715 if (HiIndex >= 2) {
10716 Mask1[0] = PermMask[0];
10717 Mask1[1] = PermMask[1];
10718 Mask1[2] = HiIndex & 1 ? 6 : 4;
10719 Mask1[3] = HiIndex & 1 ? 4 : 6;
10720 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
10721 }
10723 Mask1[0] = HiIndex & 1 ? 2 : 0;
10724 Mask1[1] = HiIndex & 1 ? 0 : 2;
10725 Mask1[2] = PermMask[2];
10726 Mask1[3] = PermMask[3];
10727 if (Mask1[2] >= 0)
10728 Mask1[2] += 4;
10729 if (Mask1[3] >= 0)
10730 Mask1[3] += 4;
10731 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
10732 }
10734 // Break it into (shuffle shuffle_hi, shuffle_lo).
10735 int LoMask[] = { -1, -1, -1, -1 };
10736 int HiMask[] = { -1, -1, -1, -1 };
10738 int *MaskPtr = LoMask;
10739 unsigned MaskIdx = 0;
10740 unsigned LoIdx = 0;
10741 unsigned HiIdx = 2;
10742 for (unsigned i = 0; i != 4; ++i) {
10743 if (i == 2) {
10744 MaskPtr = HiMask;
10745 MaskIdx = 1;
10746 LoIdx = 0;
10747 HiIdx = 2;
10748 }
10749 int Idx = PermMask[i];
10750 if (Idx < 0) {
10751 Locs[i] = std::make_pair(-1, -1);
10752 } else if (Idx < 4) {
10753 Locs[i] = std::make_pair(MaskIdx, LoIdx);
10754 MaskPtr[LoIdx] = Idx;
10755 LoIdx++;
10756 } else {
10757 Locs[i] = std::make_pair(MaskIdx, HiIdx);
10758 MaskPtr[HiIdx] = Idx;
10759 HiIdx++;
10760 }
10761 }
10763 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
10764 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
10765 int MaskOps[] = { -1, -1, -1, -1 };
10766 for (unsigned i = 0; i != 4; ++i)
10767 if (Locs[i].first != -1)
10768 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
10769 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
10770 }
10772 static bool MayFoldVectorLoad(SDValue V) {
10773 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
10774 V = V.getOperand(0);
10776 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
10777 V = V.getOperand(0);
10778 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
10779 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
10780 // BUILD_VECTOR (load), undef
10781 V = V.getOperand(0);
10783 return MayFoldLoad(V);
10784 }
10786 static
10787 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
10788 MVT VT = Op.getSimpleValueType();
10790 // Canonizalize to v2f64.
10791 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
10792 return DAG.getNode(ISD::BITCAST, dl, VT,
10793 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
10794 V1, DAG));
10795 }
10797 static
10798 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
10799 bool HasSSE2) {
10800 SDValue V1 = Op.getOperand(0);
10801 SDValue V2 = Op.getOperand(1);
10802 MVT VT = Op.getSimpleValueType();
10804 assert(VT != MVT::v2i64 && "unsupported shuffle type");
10806 if (HasSSE2 && VT == MVT::v2f64)
10807 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
10809 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
10810 return DAG.getNode(ISD::BITCAST, dl, VT,
10811 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
10812 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
10813 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
10814 }
10816 static
10817 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
10818 SDValue V1 = Op.getOperand(0);
10819 SDValue V2 = Op.getOperand(1);
10820 MVT VT = Op.getSimpleValueType();
10822 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
10823 "unsupported shuffle type");
10825 if (V2.getOpcode() == ISD::UNDEF)
10826 V2 = V1;
10828 // v4i32 or v4f32
10829 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
10830 }
10832 static
10833 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
10834 SDValue V1 = Op.getOperand(0);
10835 SDValue V2 = Op.getOperand(1);
10836 MVT VT = Op.getSimpleValueType();
10837 unsigned NumElems = VT.getVectorNumElements();
10839 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
10840 // operand of these instructions is only memory, so check if there's a
10841 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
10842 // same masks.
10843 bool CanFoldLoad = false;
10845 // Trivial case, when V2 comes from a load.
10846 if (MayFoldVectorLoad(V2))
10847 CanFoldLoad = true;
10849 // When V1 is a load, it can be folded later into a store in isel, example:
10850 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
10851 // turns into:
10852 // (MOVLPSmr addr:$src1, VR128:$src2)
10853 // So, recognize this potential and also use MOVLPS or MOVLPD
10854 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
10855 CanFoldLoad = true;
10857 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10858 if (CanFoldLoad) {
10859 if (HasSSE2 && NumElems == 2)
10860 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
10862 if (NumElems == 4)
10863 // If we don't care about the second element, proceed to use movss.
10864 if (SVOp->getMaskElt(1) != -1)
10865 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
10866 }
10868 // movl and movlp will both match v2i64, but v2i64 is never matched by
10869 // movl earlier because we make it strict to avoid messing with the movlp load
10870 // folding logic (see the code above getMOVLP call). Match it here then,
10871 // this is horrible, but will stay like this until we move all shuffle
10872 // matching to x86 specific nodes. Note that for the 1st condition all
10873 // types are matched with movsd.
10874 if (HasSSE2) {
10875 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
10876 // as to remove this logic from here, as much as possible
10877 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
10878 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
10879 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
10880 }
10882 assert(VT != MVT::v4i32 && "unsupported shuffle type");
10884 // Invert the operand order and use SHUFPS to match it.
10885 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
10886 getShuffleSHUFImmediate(SVOp), DAG);
10887 }
10889 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
10890 SelectionDAG &DAG) {
10891 SDLoc dl(Load);
10892 MVT VT = Load->getSimpleValueType(0);
10893 MVT EVT = VT.getVectorElementType();
10894 SDValue Addr = Load->getOperand(1);
10895 SDValue NewAddr = DAG.getNode(
10896 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
10897 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
10899 SDValue NewLoad =
10900 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
10901 DAG.getMachineFunction().getMachineMemOperand(
10902 Load->getMemOperand(), 0, EVT.getStoreSize()));
10903 return NewLoad;
10904 }
10906 // It is only safe to call this function if isINSERTPSMask is true for
10907 // this shufflevector mask.
10908 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
10909 SelectionDAG &DAG) {
10910 // Generate an insertps instruction when inserting an f32 from memory onto a
10911 // v4f32 or when copying a member from one v4f32 to another.
10912 // We also use it for transferring i32 from one register to another,
10913 // since it simply copies the same bits.
10914 // If we're transferring an i32 from memory to a specific element in a
10915 // register, we output a generic DAG that will match the PINSRD
10916 // instruction.
10917 MVT VT = SVOp->getSimpleValueType(0);
10918 MVT EVT = VT.getVectorElementType();
10919 SDValue V1 = SVOp->getOperand(0);
10920 SDValue V2 = SVOp->getOperand(1);
10921 auto Mask = SVOp->getMask();
10922 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
10923 "unsupported vector type for insertps/pinsrd");
10925 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
10926 auto FromV2Predicate = [](const int &i) { return i >= 4; };
10927 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
10929 SDValue From;
10930 SDValue To;
10931 unsigned DestIndex;
10932 if (FromV1 == 1) {
10933 From = V1;
10934 To = V2;
10935 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
10936 Mask.begin();
10938 // If we have 1 element from each vector, we have to check if we're
10939 // changing V1's element's place. If so, we're done. Otherwise, we
10940 // should assume we're changing V2's element's place and behave
10941 // accordingly.
10942 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
10943 assert(DestIndex <= INT32_MAX && "truncated destination index");
10944 if (FromV1 == FromV2 &&
10945 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
10946 From = V2;
10947 To = V1;
10948 DestIndex =
10949 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
10950 }
10951 } else {
10952 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
10953 "More than one element from V1 and from V2, or no elements from one "
10954 "of the vectors. This case should not have returned true from "
10955 "isINSERTPSMask");
10956 From = V2;
10957 To = V1;
10958 DestIndex =
10959 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
10960 }
10962 // Get an index into the source vector in the range [0,4) (the mask is
10963 // in the range [0,8) because it can address V1 and V2)
10964 unsigned SrcIndex = Mask[DestIndex] % 4;
10965 if (MayFoldLoad(From)) {
10966 // Trivial case, when From comes from a load and is only used by the
10967 // shuffle. Make it use insertps from the vector that we need from that
10968 // load.
10969 SDValue NewLoad =
10970 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
10971 if (!NewLoad.getNode())
10972 return SDValue();
10974 if (EVT == MVT::f32) {
10975 // Create this as a scalar to vector to match the instruction pattern.
10976 SDValue LoadScalarToVector =
10977 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
10978 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
10979 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
10980 InsertpsMask);
10981 } else { // EVT == MVT::i32
10982 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
10983 // instruction, to match the PINSRD instruction, which loads an i32 to a
10984 // certain vector element.
10985 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
10986 DAG.getConstant(DestIndex, MVT::i32));
10987 }
10988 }
10990 // Vector-element-to-vector
10991 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
10992 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
10993 }
10995 // Reduce a vector shuffle to zext.
10996 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
10997 SelectionDAG &DAG) {
10998 // PMOVZX is only available from SSE41.
10999 if (!Subtarget->hasSSE41())
11000 return SDValue();
11002 MVT VT = Op.getSimpleValueType();
11004 // Only AVX2 support 256-bit vector integer extending.
11005 if (!Subtarget->hasInt256() && VT.is256BitVector())
11006 return SDValue();
11008 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11009 SDLoc DL(Op);
11010 SDValue V1 = Op.getOperand(0);
11011 SDValue V2 = Op.getOperand(1);
11012 unsigned NumElems = VT.getVectorNumElements();
11014 // Extending is an unary operation and the element type of the source vector
11015 // won't be equal to or larger than i64.
11016 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
11017 VT.getVectorElementType() == MVT::i64)
11018 return SDValue();
11020 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
11021 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
11022 while ((1U << Shift) < NumElems) {
11023 if (SVOp->getMaskElt(1U << Shift) == 1)
11024 break;
11025 Shift += 1;
11026 // The maximal ratio is 8, i.e. from i8 to i64.
11027 if (Shift > 3)
11028 return SDValue();
11029 }
11031 // Check the shuffle mask.
11032 unsigned Mask = (1U << Shift) - 1;
11033 for (unsigned i = 0; i != NumElems; ++i) {
11034 int EltIdx = SVOp->getMaskElt(i);
11035 if ((i & Mask) != 0 && EltIdx != -1)
11036 return SDValue();
11037 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
11038 return SDValue();
11039 }
11041 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
11042 MVT NeVT = MVT::getIntegerVT(NBits);
11043 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
11045 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
11046 return SDValue();
11048 // Simplify the operand as it's prepared to be fed into shuffle.
11049 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
11050 if (V1.getOpcode() == ISD::BITCAST &&
11051 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
11052 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
11053 V1.getOperand(0).getOperand(0)
11054 .getSimpleValueType().getSizeInBits() == SignificantBits) {
11055 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
11056 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
11057 ConstantSDNode *CIdx =
11058 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
11059 // If it's foldable, i.e. normal load with single use, we will let code
11060 // selection to fold it. Otherwise, we will short the conversion sequence.
11061 if (CIdx && CIdx->getZExtValue() == 0 &&
11062 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
11063 MVT FullVT = V.getSimpleValueType();
11064 MVT V1VT = V1.getSimpleValueType();
11065 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
11066 // The "ext_vec_elt" node is wider than the result node.
11067 // In this case we should extract subvector from V.
11068 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
11069 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
11070 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
11071 FullVT.getVectorNumElements()/Ratio);
11072 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
11073 DAG.getIntPtrConstant(0));
11074 }
11075 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
11076 }
11077 }
11079 return DAG.getNode(ISD::BITCAST, DL, VT,
11080 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
11081 }
11083 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
11084 SelectionDAG &DAG) {
11085 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11086 MVT VT = Op.getSimpleValueType();
11087 SDLoc dl(Op);
11088 SDValue V1 = Op.getOperand(0);
11089 SDValue V2 = Op.getOperand(1);
11091 if (isZeroShuffle(SVOp))
11092 return getZeroVector(VT, Subtarget, DAG, dl);
11094 // Handle splat operations
11095 if (SVOp->isSplat()) {
11096 // Use vbroadcast whenever the splat comes from a foldable load
11097 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
11098 if (Broadcast.getNode())
11099 return Broadcast;
11100 }
11102 // Check integer expanding shuffles.
11103 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
11104 if (NewOp.getNode())
11105 return NewOp;
11107 // If the shuffle can be profitably rewritten as a narrower shuffle, then
11108 // do it!
11109 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
11110 VT == MVT::v32i8) {
11111 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11112 if (NewOp.getNode())
11113 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
11114 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
11115 // FIXME: Figure out a cleaner way to do this.
11116 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
11117 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11118 if (NewOp.getNode()) {
11119 MVT NewVT = NewOp.getSimpleValueType();
11120 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
11121 NewVT, true, false))
11122 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
11123 dl);
11124 }
11125 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
11126 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11127 if (NewOp.getNode()) {
11128 MVT NewVT = NewOp.getSimpleValueType();
11129 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
11130 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
11131 dl);
11132 }
11133 }
11134 }
11135 return SDValue();
11136 }
11138 SDValue
11139 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
11140 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11141 SDValue V1 = Op.getOperand(0);
11142 SDValue V2 = Op.getOperand(1);
11143 MVT VT = Op.getSimpleValueType();
11144 SDLoc dl(Op);
11145 unsigned NumElems = VT.getVectorNumElements();
11146 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
11147 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11148 bool V1IsSplat = false;
11149 bool V2IsSplat = false;
11150 bool HasSSE2 = Subtarget->hasSSE2();
11151 bool HasFp256 = Subtarget->hasFp256();
11152 bool HasInt256 = Subtarget->hasInt256();
11153 MachineFunction &MF = DAG.getMachineFunction();
11154 bool OptForSize = MF.getFunction()->getAttributes().
11155 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
11157 // Check if we should use the experimental vector shuffle lowering. If so,
11158 // delegate completely to that code path.
11159 if (ExperimentalVectorShuffleLowering)
11160 return lowerVectorShuffle(Op, Subtarget, DAG);
11162 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
11164 if (V1IsUndef && V2IsUndef)
11165 return DAG.getUNDEF(VT);
11167 // When we create a shuffle node we put the UNDEF node to second operand,
11168 // but in some cases the first operand may be transformed to UNDEF.
11169 // In this case we should just commute the node.
11170 if (V1IsUndef)
11171 return DAG.getCommutedVectorShuffle(*SVOp);
11173 // Vector shuffle lowering takes 3 steps:
11174 //
11175 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
11176 // narrowing and commutation of operands should be handled.
11177 // 2) Matching of shuffles with known shuffle masks to x86 target specific
11178 // shuffle nodes.
11179 // 3) Rewriting of unmatched masks into new generic shuffle operations,
11180 // so the shuffle can be broken into other shuffles and the legalizer can
11181 // try the lowering again.
11182 //
11183 // The general idea is that no vector_shuffle operation should be left to
11184 // be matched during isel, all of them must be converted to a target specific
11185 // node here.
11187 // Normalize the input vectors. Here splats, zeroed vectors, profitable
11188 // narrowing and commutation of operands should be handled. The actual code
11189 // doesn't include all of those, work in progress...
11190 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
11191 if (NewOp.getNode())
11192 return NewOp;
11194 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
11196 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
11197 // unpckh_undef). Only use pshufd if speed is more important than size.
11198 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
11199 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11200 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
11201 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11203 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
11204 V2IsUndef && MayFoldVectorLoad(V1))
11205 return getMOVDDup(Op, dl, V1, DAG);
11207 if (isMOVHLPS_v_undef_Mask(M, VT))
11208 return getMOVHighToLow(Op, dl, DAG);
11210 // Use to match splats
11211 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
11212 (VT == MVT::v2f64 || VT == MVT::v2i64))
11213 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11215 if (isPSHUFDMask(M, VT)) {
11216 // The actual implementation will match the mask in the if above and then
11217 // during isel it can match several different instructions, not only pshufd
11218 // as its name says, sad but true, emulate the behavior for now...
11219 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
11220 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
11222 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
11224 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
11225 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
11227 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
11228 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1, TargetMask,
11229 DAG);
11231 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
11232 TargetMask, DAG);
11233 }
11235 if (isPALIGNRMask(M, VT, Subtarget))
11236 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
11237 getShufflePALIGNRImmediate(SVOp),
11238 DAG);
11240 if (isVALIGNMask(M, VT, Subtarget))
11241 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
11242 getShuffleVALIGNImmediate(SVOp),
11243 DAG);
11245 // Check if this can be converted into a logical shift.
11246 bool isLeft = false;
11247 unsigned ShAmt = 0;
11248 SDValue ShVal;
11249 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
11250 if (isShift && ShVal.hasOneUse()) {
11251 // If the shifted value has multiple uses, it may be cheaper to use
11252 // v_set0 + movlhps or movhlps, etc.
11253 MVT EltVT = VT.getVectorElementType();
11254 ShAmt *= EltVT.getSizeInBits();
11255 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
11256 }
11258 if (isMOVLMask(M, VT)) {
11259 if (ISD::isBuildVectorAllZeros(V1.getNode()))
11260 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
11261 if (!isMOVLPMask(M, VT)) {
11262 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
11263 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11265 if (VT == MVT::v4i32 || VT == MVT::v4f32)
11266 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11267 }
11268 }
11270 // FIXME: fold these into legal mask.
11271 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
11272 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
11274 if (isMOVHLPSMask(M, VT))
11275 return getMOVHighToLow(Op, dl, DAG);
11277 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
11278 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
11280 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
11281 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
11283 if (isMOVLPMask(M, VT))
11284 return getMOVLP(Op, dl, DAG, HasSSE2);
11286 if (ShouldXformToMOVHLPS(M, VT) ||
11287 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
11288 return DAG.getCommutedVectorShuffle(*SVOp);
11290 if (isShift) {
11291 // No better options. Use a vshldq / vsrldq.
11292 MVT EltVT = VT.getVectorElementType();
11293 ShAmt *= EltVT.getSizeInBits();
11294 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
11295 }
11297 bool Commuted = false;
11298 // FIXME: This should also accept a bitcast of a splat? Be careful, not
11299 // 1,1,1,1 -> v8i16 though.
11300 BitVector UndefElements;
11301 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
11302 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
11303 V1IsSplat = true;
11304 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
11305 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
11306 V2IsSplat = true;
11308 // Canonicalize the splat or undef, if present, to be on the RHS.
11309 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
11310 CommuteVectorShuffleMask(M, NumElems);
11311 std::swap(V1, V2);
11312 std::swap(V1IsSplat, V2IsSplat);
11313 Commuted = true;
11314 }
11316 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
11317 // Shuffling low element of v1 into undef, just return v1.
11318 if (V2IsUndef)
11319 return V1;
11320 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
11321 // the instruction selector will not match, so get a canonical MOVL with
11322 // swapped operands to undo the commute.
11323 return getMOVL(DAG, dl, VT, V2, V1);
11324 }
11326 if (isUNPCKLMask(M, VT, HasInt256))
11327 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11329 if (isUNPCKHMask(M, VT, HasInt256))
11330 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11332 if (V2IsSplat) {
11333 // Normalize mask so all entries that point to V2 points to its first
11334 // element then try to match unpck{h|l} again. If match, return a
11335 // new vector_shuffle with the corrected mask.p
11336 SmallVector<int, 8> NewMask(M.begin(), M.end());
11337 NormalizeMask(NewMask, NumElems);
11338 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
11339 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11340 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
11341 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11342 }
11344 if (Commuted) {
11345 // Commute is back and try unpck* again.
11346 // FIXME: this seems wrong.
11347 CommuteVectorShuffleMask(M, NumElems);
11348 std::swap(V1, V2);
11349 std::swap(V1IsSplat, V2IsSplat);
11351 if (isUNPCKLMask(M, VT, HasInt256))
11352 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11354 if (isUNPCKHMask(M, VT, HasInt256))
11355 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11356 }
11358 // Normalize the node to match x86 shuffle ops if needed
11359 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
11360 return DAG.getCommutedVectorShuffle(*SVOp);
11362 // The checks below are all present in isShuffleMaskLegal, but they are
11363 // inlined here right now to enable us to directly emit target specific
11364 // nodes, and remove one by one until they don't return Op anymore.
11366 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
11367 SVOp->getSplatIndex() == 0 && V2IsUndef) {
11368 if (VT == MVT::v2f64 || VT == MVT::v2i64)
11369 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11370 }
11372 if (isPSHUFHWMask(M, VT, HasInt256))
11373 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
11374 getShufflePSHUFHWImmediate(SVOp),
11375 DAG);
11377 if (isPSHUFLWMask(M, VT, HasInt256))
11378 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
11379 getShufflePSHUFLWImmediate(SVOp),
11380 DAG);
11382 unsigned MaskValue;
11383 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
11384 &MaskValue))
11385 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
11387 if (isSHUFPMask(M, VT))
11388 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
11389 getShuffleSHUFImmediate(SVOp), DAG);
11391 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
11392 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11393 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
11394 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11396 //===--------------------------------------------------------------------===//
11397 // Generate target specific nodes for 128 or 256-bit shuffles only
11398 // supported in the AVX instruction set.
11399 //
11401 // Handle VMOVDDUPY permutations
11402 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
11403 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
11405 // Handle VPERMILPS/D* permutations
11406 if (isVPERMILPMask(M, VT)) {
11407 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
11408 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
11409 getShuffleSHUFImmediate(SVOp), DAG);
11410 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1,
11411 getShuffleSHUFImmediate(SVOp), DAG);
11412 }
11414 unsigned Idx;
11415 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
11416 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
11417 Idx*(NumElems/2), DAG, dl);
11419 // Handle VPERM2F128/VPERM2I128 permutations
11420 if (isVPERM2X128Mask(M, VT, HasFp256))
11421 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
11422 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
11424 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
11425 return getINSERTPS(SVOp, dl, DAG);
11427 unsigned Imm8;
11428 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
11429 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
11431 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
11432 VT.is512BitVector()) {
11433 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
11434 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
11435 SmallVector<SDValue, 16> permclMask;
11436 for (unsigned i = 0; i != NumElems; ++i) {
11437 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
11438 }
11440 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
11441 if (V2IsUndef)
11442 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
11443 return DAG.getNode(X86ISD::VPERMV, dl, VT,
11444 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
11445 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
11446 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
11447 }
11449 //===--------------------------------------------------------------------===//
11450 // Since no target specific shuffle was selected for this generic one,
11451 // lower it into other known shuffles. FIXME: this isn't true yet, but
11452 // this is the plan.
11453 //
11455 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
11456 if (VT == MVT::v8i16) {
11457 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
11458 if (NewOp.getNode())
11459 return NewOp;
11460 }
11462 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
11463 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
11464 if (NewOp.getNode())
11465 return NewOp;
11466 }
11468 if (VT == MVT::v16i8) {
11469 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
11470 if (NewOp.getNode())
11471 return NewOp;
11472 }
11474 if (VT == MVT::v32i8) {
11475 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
11476 if (NewOp.getNode())
11477 return NewOp;
11478 }
11480 // Handle all 128-bit wide vectors with 4 elements, and match them with
11481 // several different shuffle types.
11482 if (NumElems == 4 && VT.is128BitVector())
11483 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
11485 // Handle general 256-bit shuffles
11486 if (VT.is256BitVector())
11487 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
11489 return SDValue();
11490 }
11492 // This function assumes its argument is a BUILD_VECTOR of constants or
11493 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
11494 // true.
11495 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
11496 unsigned &MaskValue) {
11497 MaskValue = 0;
11498 unsigned NumElems = BuildVector->getNumOperands();
11499 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
11500 unsigned NumLanes = (NumElems - 1) / 8 + 1;
11501 unsigned NumElemsInLane = NumElems / NumLanes;
11503 // Blend for v16i16 should be symetric for the both lanes.
11504 for (unsigned i = 0; i < NumElemsInLane; ++i) {
11505 SDValue EltCond = BuildVector->getOperand(i);
11506 SDValue SndLaneEltCond =
11507 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
11509 int Lane1Cond = -1, Lane2Cond = -1;
11510 if (isa<ConstantSDNode>(EltCond))
11511 Lane1Cond = !isZero(EltCond);
11512 if (isa<ConstantSDNode>(SndLaneEltCond))
11513 Lane2Cond = !isZero(SndLaneEltCond);
11515 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
11516 // Lane1Cond != 0, means we want the first argument.
11517 // Lane1Cond == 0, means we want the second argument.
11518 // The encoding of this argument is 0 for the first argument, 1
11519 // for the second. Therefore, invert the condition.
11520 MaskValue |= !Lane1Cond << i;
11521 else if (Lane1Cond < 0)
11522 MaskValue |= !Lane2Cond << i;
11523 else
11524 return false;
11525 }
11526 return true;
11527 }
11529 // Try to lower a vselect node into a simple blend instruction.
11530 static SDValue LowerVSELECTtoBlend(SDValue Op, const X86Subtarget *Subtarget,
11531 SelectionDAG &DAG) {
11532 SDValue Cond = Op.getOperand(0);
11533 SDValue LHS = Op.getOperand(1);
11534 SDValue RHS = Op.getOperand(2);
11535 SDLoc dl(Op);
11536 MVT VT = Op.getSimpleValueType();
11537 MVT EltVT = VT.getVectorElementType();
11538 unsigned NumElems = VT.getVectorNumElements();
11540 // There is no blend with immediate in AVX-512.
11541 if (VT.is512BitVector())
11542 return SDValue();
11544 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
11545 return SDValue();
11546 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
11547 return SDValue();
11549 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
11550 return SDValue();
11552 // Check the mask for BLEND and build the value.
11553 unsigned MaskValue = 0;
11554 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
11555 return SDValue();
11557 // Convert i32 vectors to floating point if it is not AVX2.
11558 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
11559 MVT BlendVT = VT;
11560 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
11561 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
11562 NumElems);
11563 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
11564 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
11565 }
11567 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
11568 DAG.getConstant(MaskValue, MVT::i32));
11569 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
11570 }
11572 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
11573 // A vselect where all conditions and data are constants can be optimized into
11574 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
11575 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
11576 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
11577 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
11578 return SDValue();
11580 SDValue BlendOp = LowerVSELECTtoBlend(Op, Subtarget, DAG);
11581 if (BlendOp.getNode())
11582 return BlendOp;
11584 // Some types for vselect were previously set to Expand, not Legal or
11585 // Custom. Return an empty SDValue so we fall-through to Expand, after
11586 // the Custom lowering phase.
11587 MVT VT = Op.getSimpleValueType();
11588 switch (VT.SimpleTy) {
11589 default:
11590 break;
11591 case MVT::v8i16:
11592 case MVT::v16i16:
11593 if (Subtarget->hasBWI() && Subtarget->hasVLX())
11594 break;
11595 return SDValue();
11596 }
11598 // We couldn't create a "Blend with immediate" node.
11599 // This node should still be legal, but we'll have to emit a blendv*
11600 // instruction.
11601 return Op;
11602 }
11604 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
11605 MVT VT = Op.getSimpleValueType();
11606 SDLoc dl(Op);
11608 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
11609 return SDValue();
11611 if (VT.getSizeInBits() == 8) {
11612 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
11613 Op.getOperand(0), Op.getOperand(1));
11614 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11615 DAG.getValueType(VT));
11616 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11617 }
11619 if (VT.getSizeInBits() == 16) {
11620 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11621 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
11622 if (Idx == 0)
11623 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11624 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11625 DAG.getNode(ISD::BITCAST, dl,
11626 MVT::v4i32,
11627 Op.getOperand(0)),
11628 Op.getOperand(1)));
11629 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
11630 Op.getOperand(0), Op.getOperand(1));
11631 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11632 DAG.getValueType(VT));
11633 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11634 }
11636 if (VT == MVT::f32) {
11637 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
11638 // the result back to FR32 register. It's only worth matching if the
11639 // result has a single use which is a store or a bitcast to i32. And in
11640 // the case of a store, it's not worth it if the index is a constant 0,
11641 // because a MOVSSmr can be used instead, which is smaller and faster.
11642 if (!Op.hasOneUse())
11643 return SDValue();
11644 SDNode *User = *Op.getNode()->use_begin();
11645 if ((User->getOpcode() != ISD::STORE ||
11646 (isa<ConstantSDNode>(Op.getOperand(1)) &&
11647 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
11648 (User->getOpcode() != ISD::BITCAST ||
11649 User->getValueType(0) != MVT::i32))
11650 return SDValue();
11651 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11652 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
11653 Op.getOperand(0)),
11654 Op.getOperand(1));
11655 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
11656 }
11658 if (VT == MVT::i32 || VT == MVT::i64) {
11659 // ExtractPS/pextrq works with constant index.
11660 if (isa<ConstantSDNode>(Op.getOperand(1)))
11661 return Op;
11662 }
11663 return SDValue();
11664 }
11666 /// Extract one bit from mask vector, like v16i1 or v8i1.
11667 /// AVX-512 feature.
11668 SDValue
11669 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
11670 SDValue Vec = Op.getOperand(0);
11671 SDLoc dl(Vec);
11672 MVT VecVT = Vec.getSimpleValueType();
11673 SDValue Idx = Op.getOperand(1);
11674 MVT EltVT = Op.getSimpleValueType();
11676 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
11678 // variable index can't be handled in mask registers,
11679 // extend vector to VR512
11680 if (!isa<ConstantSDNode>(Idx)) {
11681 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11682 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
11683 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
11684 ExtVT.getVectorElementType(), Ext, Idx);
11685 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
11686 }
11688 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11689 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11690 unsigned MaxSift = rc->getSize()*8 - 1;
11691 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
11692 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
11693 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
11694 DAG.getConstant(MaxSift, MVT::i8));
11695 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
11696 DAG.getIntPtrConstant(0));
11697 }
11699 SDValue
11700 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
11701 SelectionDAG &DAG) const {
11702 SDLoc dl(Op);
11703 SDValue Vec = Op.getOperand(0);
11704 MVT VecVT = Vec.getSimpleValueType();
11705 SDValue Idx = Op.getOperand(1);
11707 if (Op.getSimpleValueType() == MVT::i1)
11708 return ExtractBitFromMaskVector(Op, DAG);
11710 if (!isa<ConstantSDNode>(Idx)) {
11711 if (VecVT.is512BitVector() ||
11712 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
11713 VecVT.getVectorElementType().getSizeInBits() == 32)) {
11715 MVT MaskEltVT =
11716 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
11717 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
11718 MaskEltVT.getSizeInBits());
11720 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
11721 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
11722 getZeroVector(MaskVT, Subtarget, DAG, dl),
11723 Idx, DAG.getConstant(0, getPointerTy()));
11724 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
11725 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
11726 Perm, DAG.getConstant(0, getPointerTy()));
11727 }
11728 return SDValue();
11729 }
11731 // If this is a 256-bit vector result, first extract the 128-bit vector and
11732 // then extract the element from the 128-bit vector.
11733 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
11735 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11736 // Get the 128-bit vector.
11737 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
11738 MVT EltVT = VecVT.getVectorElementType();
11740 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
11742 //if (IdxVal >= NumElems/2)
11743 // IdxVal -= NumElems/2;
11744 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
11745 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
11746 DAG.getConstant(IdxVal, MVT::i32));
11747 }
11749 assert(VecVT.is128BitVector() && "Unexpected vector length");
11751 if (Subtarget->hasSSE41()) {
11752 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
11753 if (Res.getNode())
11754 return Res;
11755 }
11757 MVT VT = Op.getSimpleValueType();
11758 // TODO: handle v16i8.
11759 if (VT.getSizeInBits() == 16) {
11760 SDValue Vec = Op.getOperand(0);
11761 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11762 if (Idx == 0)
11763 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11764 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11765 DAG.getNode(ISD::BITCAST, dl,
11766 MVT::v4i32, Vec),
11767 Op.getOperand(1)));
11768 // Transform it so it match pextrw which produces a 32-bit result.
11769 MVT EltVT = MVT::i32;
11770 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
11771 Op.getOperand(0), Op.getOperand(1));
11772 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
11773 DAG.getValueType(VT));
11774 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11775 }
11777 if (VT.getSizeInBits() == 32) {
11778 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11779 if (Idx == 0)
11780 return Op;
11782 // SHUFPS the element to the lowest double word, then movss.
11783 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
11784 MVT VVT = Op.getOperand(0).getSimpleValueType();
11785 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11786 DAG.getUNDEF(VVT), Mask);
11787 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11788 DAG.getIntPtrConstant(0));
11789 }
11791 if (VT.getSizeInBits() == 64) {
11792 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
11793 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
11794 // to match extract_elt for f64.
11795 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11796 if (Idx == 0)
11797 return Op;
11799 // UNPCKHPD the element to the lowest double word, then movsd.
11800 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
11801 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
11802 int Mask[2] = { 1, -1 };
11803 MVT VVT = Op.getOperand(0).getSimpleValueType();
11804 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11805 DAG.getUNDEF(VVT), Mask);
11806 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11807 DAG.getIntPtrConstant(0));
11808 }
11810 return SDValue();
11811 }
11813 /// Insert one bit to mask vector, like v16i1 or v8i1.
11814 /// AVX-512 feature.
11815 SDValue
11816 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
11817 SDLoc dl(Op);
11818 SDValue Vec = Op.getOperand(0);
11819 SDValue Elt = Op.getOperand(1);
11820 SDValue Idx = Op.getOperand(2);
11821 MVT VecVT = Vec.getSimpleValueType();
11823 if (!isa<ConstantSDNode>(Idx)) {
11824 // Non constant index. Extend source and destination,
11825 // insert element and then truncate the result.
11826 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11827 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
11828 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
11829 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
11830 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
11831 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
11832 }
11834 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11835 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
11836 if (Vec.getOpcode() == ISD::UNDEF)
11837 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11838 DAG.getConstant(IdxVal, MVT::i8));
11839 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11840 unsigned MaxSift = rc->getSize()*8 - 1;
11841 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11842 DAG.getConstant(MaxSift, MVT::i8));
11843 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
11844 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
11845 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
11846 }
11848 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
11849 SelectionDAG &DAG) const {
11850 MVT VT = Op.getSimpleValueType();
11851 MVT EltVT = VT.getVectorElementType();
11853 if (EltVT == MVT::i1)
11854 return InsertBitToMaskVector(Op, DAG);
11856 SDLoc dl(Op);
11857 SDValue N0 = Op.getOperand(0);
11858 SDValue N1 = Op.getOperand(1);
11859 SDValue N2 = Op.getOperand(2);
11860 if (!isa<ConstantSDNode>(N2))
11861 return SDValue();
11862 auto *N2C = cast<ConstantSDNode>(N2);
11863 unsigned IdxVal = N2C->getZExtValue();
11865 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
11866 // into that, and then insert the subvector back into the result.
11867 if (VT.is256BitVector() || VT.is512BitVector()) {
11868 // Get the desired 128-bit vector half.
11869 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
11871 // Insert the element into the desired half.
11872 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
11873 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
11875 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
11876 DAG.getConstant(IdxIn128, MVT::i32));
11878 // Insert the changed part back to the 256-bit vector
11879 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
11880 }
11881 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
11883 if (Subtarget->hasSSE41()) {
11884 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
11885 unsigned Opc;
11886 if (VT == MVT::v8i16) {
11887 Opc = X86ISD::PINSRW;
11888 } else {
11889 assert(VT == MVT::v16i8);
11890 Opc = X86ISD::PINSRB;
11891 }
11893 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
11894 // argument.
11895 if (N1.getValueType() != MVT::i32)
11896 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11897 if (N2.getValueType() != MVT::i32)
11898 N2 = DAG.getIntPtrConstant(IdxVal);
11899 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
11900 }
11902 if (EltVT == MVT::f32) {
11903 // Bits [7:6] of the constant are the source select. This will always be
11904 // zero here. The DAG Combiner may combine an extract_elt index into
11905 // these
11906 // bits. For example (insert (extract, 3), 2) could be matched by
11907 // putting
11908 // the '3' into bits [7:6] of X86ISD::INSERTPS.
11909 // Bits [5:4] of the constant are the destination select. This is the
11910 // value of the incoming immediate.
11911 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
11912 // combine either bitwise AND or insert of float 0.0 to set these bits.
11913 N2 = DAG.getIntPtrConstant(IdxVal << 4);
11914 // Create this as a scalar to vector..
11915 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11916 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
11917 }
11919 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
11920 // PINSR* works with constant index.
11921 return Op;
11922 }
11923 }
11925 if (EltVT == MVT::i8)
11926 return SDValue();
11928 if (EltVT.getSizeInBits() == 16) {
11929 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
11930 // as its second argument.
11931 if (N1.getValueType() != MVT::i32)
11932 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11933 if (N2.getValueType() != MVT::i32)
11934 N2 = DAG.getIntPtrConstant(IdxVal);
11935 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
11936 }
11937 return SDValue();
11938 }
11940 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
11941 SDLoc dl(Op);
11942 MVT OpVT = Op.getSimpleValueType();
11944 // If this is a 256-bit vector result, first insert into a 128-bit
11945 // vector and then insert into the 256-bit vector.
11946 if (!OpVT.is128BitVector()) {
11947 // Insert into a 128-bit vector.
11948 unsigned SizeFactor = OpVT.getSizeInBits()/128;
11949 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
11950 OpVT.getVectorNumElements() / SizeFactor);
11952 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
11954 // Insert the 128-bit vector.
11955 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
11956 }
11958 if (OpVT == MVT::v1i64 &&
11959 Op.getOperand(0).getValueType() == MVT::i64)
11960 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
11962 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
11963 assert(OpVT.is128BitVector() && "Expected an SSE type!");
11964 return DAG.getNode(ISD::BITCAST, dl, OpVT,
11965 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
11966 }
11968 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
11969 // a simple subregister reference or explicit instructions to grab
11970 // upper bits of a vector.
11971 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11972 SelectionDAG &DAG) {
11973 SDLoc dl(Op);
11974 SDValue In = Op.getOperand(0);
11975 SDValue Idx = Op.getOperand(1);
11976 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11977 MVT ResVT = Op.getSimpleValueType();
11978 MVT InVT = In.getSimpleValueType();
11980 if (Subtarget->hasFp256()) {
11981 if (ResVT.is128BitVector() &&
11982 (InVT.is256BitVector() || InVT.is512BitVector()) &&
11983 isa<ConstantSDNode>(Idx)) {
11984 return Extract128BitVector(In, IdxVal, DAG, dl);
11985 }
11986 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
11987 isa<ConstantSDNode>(Idx)) {
11988 return Extract256BitVector(In, IdxVal, DAG, dl);
11989 }
11990 }
11991 return SDValue();
11992 }
11994 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
11995 // simple superregister reference or explicit instructions to insert
11996 // the upper bits of a vector.
11997 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11998 SelectionDAG &DAG) {
11999 if (Subtarget->hasFp256()) {
12000 SDLoc dl(Op.getNode());
12001 SDValue Vec = Op.getNode()->getOperand(0);
12002 SDValue SubVec = Op.getNode()->getOperand(1);
12003 SDValue Idx = Op.getNode()->getOperand(2);
12005 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
12006 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
12007 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
12008 isa<ConstantSDNode>(Idx)) {
12009 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12010 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
12011 }
12013 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
12014 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
12015 isa<ConstantSDNode>(Idx)) {
12016 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12017 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
12018 }
12019 }
12020 return SDValue();
12021 }
12023 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
12024 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
12025 // one of the above mentioned nodes. It has to be wrapped because otherwise
12026 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
12027 // be used to form addressing mode. These wrapped nodes will be selected
12028 // into MOV32ri.
12029 SDValue
12030 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
12031 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
12033 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12034 // global base reg.
12035 unsigned char OpFlag = 0;
12036 unsigned WrapperKind = X86ISD::Wrapper;
12037 CodeModel::Model M = DAG.getTarget().getCodeModel();
12039 if (Subtarget->isPICStyleRIPRel() &&
12040 (M == CodeModel::Small || M == CodeModel::Kernel))
12041 WrapperKind = X86ISD::WrapperRIP;
12042 else if (Subtarget->isPICStyleGOT())
12043 OpFlag = X86II::MO_GOTOFF;
12044 else if (Subtarget->isPICStyleStubPIC())
12045 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12047 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
12048 CP->getAlignment(),
12049 CP->getOffset(), OpFlag);
12050 SDLoc DL(CP);
12051 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12052 // With PIC, the address is actually $g + Offset.
12053 if (OpFlag) {
12054 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12055 DAG.getNode(X86ISD::GlobalBaseReg,
12056 SDLoc(), getPointerTy()),
12057 Result);
12058 }
12060 return Result;
12061 }
12063 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
12064 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
12066 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12067 // global base reg.
12068 unsigned char OpFlag = 0;
12069 unsigned WrapperKind = X86ISD::Wrapper;
12070 CodeModel::Model M = DAG.getTarget().getCodeModel();
12072 if (Subtarget->isPICStyleRIPRel() &&
12073 (M == CodeModel::Small || M == CodeModel::Kernel))
12074 WrapperKind = X86ISD::WrapperRIP;
12075 else if (Subtarget->isPICStyleGOT())
12076 OpFlag = X86II::MO_GOTOFF;
12077 else if (Subtarget->isPICStyleStubPIC())
12078 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12080 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
12081 OpFlag);
12082 SDLoc DL(JT);
12083 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12085 // With PIC, the address is actually $g + Offset.
12086 if (OpFlag)
12087 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12088 DAG.getNode(X86ISD::GlobalBaseReg,
12089 SDLoc(), getPointerTy()),
12090 Result);
12092 return Result;
12093 }
12095 SDValue
12096 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
12097 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
12099 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12100 // global base reg.
12101 unsigned char OpFlag = 0;
12102 unsigned WrapperKind = X86ISD::Wrapper;
12103 CodeModel::Model M = DAG.getTarget().getCodeModel();
12105 if (Subtarget->isPICStyleRIPRel() &&
12106 (M == CodeModel::Small || M == CodeModel::Kernel)) {
12107 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
12108 OpFlag = X86II::MO_GOTPCREL;
12109 WrapperKind = X86ISD::WrapperRIP;
12110 } else if (Subtarget->isPICStyleGOT()) {
12111 OpFlag = X86II::MO_GOT;
12112 } else if (Subtarget->isPICStyleStubPIC()) {
12113 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
12114 } else if (Subtarget->isPICStyleStubNoDynamic()) {
12115 OpFlag = X86II::MO_DARWIN_NONLAZY;
12116 }
12118 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
12120 SDLoc DL(Op);
12121 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12123 // With PIC, the address is actually $g + Offset.
12124 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
12125 !Subtarget->is64Bit()) {
12126 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12127 DAG.getNode(X86ISD::GlobalBaseReg,
12128 SDLoc(), getPointerTy()),
12129 Result);
12130 }
12132 // For symbols that require a load from a stub to get the address, emit the
12133 // load.
12134 if (isGlobalStubReference(OpFlag))
12135 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
12136 MachinePointerInfo::getGOT(), false, false, false, 0);
12138 return Result;
12139 }
12141 SDValue
12142 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
12143 // Create the TargetBlockAddressAddress node.
12144 unsigned char OpFlags =
12145 Subtarget->ClassifyBlockAddressReference();
12146 CodeModel::Model M = DAG.getTarget().getCodeModel();
12147 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
12148 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
12149 SDLoc dl(Op);
12150 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
12151 OpFlags);
12153 if (Subtarget->isPICStyleRIPRel() &&
12154 (M == CodeModel::Small || M == CodeModel::Kernel))
12155 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
12156 else
12157 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
12159 // With PIC, the address is actually $g + Offset.
12160 if (isGlobalRelativeToPICBase(OpFlags)) {
12161 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
12162 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
12163 Result);
12164 }
12166 return Result;
12167 }
12169 SDValue
12170 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
12171 int64_t Offset, SelectionDAG &DAG) const {
12172 // Create the TargetGlobalAddress node, folding in the constant
12173 // offset if it is legal.
12174 unsigned char OpFlags =
12175 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
12176 CodeModel::Model M = DAG.getTarget().getCodeModel();
12177 SDValue Result;
12178 if (OpFlags == X86II::MO_NO_FLAG &&
12179 X86::isOffsetSuitableForCodeModel(Offset, M)) {
12180 // A direct static reference to a global.
12181 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
12182 Offset = 0;
12183 } else {
12184 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
12185 }
12187 if (Subtarget->isPICStyleRIPRel() &&
12188 (M == CodeModel::Small || M == CodeModel::Kernel))
12189 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
12190 else
12191 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
12193 // With PIC, the address is actually $g + Offset.
12194 if (isGlobalRelativeToPICBase(OpFlags)) {
12195 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
12196 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
12197 Result);
12198 }
12200 // For globals that require a load from a stub to get the address, emit the
12201 // load.
12202 if (isGlobalStubReference(OpFlags))
12203 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
12204 MachinePointerInfo::getGOT(), false, false, false, 0);
12206 // If there was a non-zero offset that we didn't fold, create an explicit
12207 // addition for it.
12208 if (Offset != 0)
12209 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
12210 DAG.getConstant(Offset, getPointerTy()));
12212 return Result;
12213 }
12215 SDValue
12216 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
12217 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
12218 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
12219 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
12220 }
12222 static SDValue
12223 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
12224 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
12225 unsigned char OperandFlags, bool LocalDynamic = false) {
12226 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12227 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12228 SDLoc dl(GA);
12229 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12230 GA->getValueType(0),
12231 GA->getOffset(),
12232 OperandFlags);
12234 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
12235 : X86ISD::TLSADDR;
12237 if (InFlag) {
12238 SDValue Ops[] = { Chain, TGA, *InFlag };
12239 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12240 } else {
12241 SDValue Ops[] = { Chain, TGA };
12242 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12243 }
12245 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
12246 MFI->setAdjustsStack(true);
12248 SDValue Flag = Chain.getValue(1);
12249 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
12250 }
12252 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
12253 static SDValue
12254 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12255 const EVT PtrVT) {
12256 SDValue InFlag;
12257 SDLoc dl(GA); // ? function entry point might be better
12258 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12259 DAG.getNode(X86ISD::GlobalBaseReg,
12260 SDLoc(), PtrVT), InFlag);
12261 InFlag = Chain.getValue(1);
12263 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
12264 }
12266 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
12267 static SDValue
12268 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12269 const EVT PtrVT) {
12270 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
12271 X86::RAX, X86II::MO_TLSGD);
12272 }
12274 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
12275 SelectionDAG &DAG,
12276 const EVT PtrVT,
12277 bool is64Bit) {
12278 SDLoc dl(GA);
12280 // Get the start address of the TLS block for this module.
12281 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
12282 .getInfo<X86MachineFunctionInfo>();
12283 MFI->incNumLocalDynamicTLSAccesses();
12285 SDValue Base;
12286 if (is64Bit) {
12287 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
12288 X86II::MO_TLSLD, /*LocalDynamic=*/true);
12289 } else {
12290 SDValue InFlag;
12291 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12292 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
12293 InFlag = Chain.getValue(1);
12294 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
12295 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
12296 }
12298 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
12299 // of Base.
12301 // Build x@dtpoff.
12302 unsigned char OperandFlags = X86II::MO_DTPOFF;
12303 unsigned WrapperKind = X86ISD::Wrapper;
12304 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12305 GA->getValueType(0),
12306 GA->getOffset(), OperandFlags);
12307 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12309 // Add x@dtpoff with the base.
12310 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
12311 }
12313 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
12314 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12315 const EVT PtrVT, TLSModel::Model model,
12316 bool is64Bit, bool isPIC) {
12317 SDLoc dl(GA);
12319 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
12320 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
12321 is64Bit ? 257 : 256));
12323 SDValue ThreadPointer =
12324 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
12325 MachinePointerInfo(Ptr), false, false, false, 0);
12327 unsigned char OperandFlags = 0;
12328 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
12329 // initialexec.
12330 unsigned WrapperKind = X86ISD::Wrapper;
12331 if (model == TLSModel::LocalExec) {
12332 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
12333 } else if (model == TLSModel::InitialExec) {
12334 if (is64Bit) {
12335 OperandFlags = X86II::MO_GOTTPOFF;
12336 WrapperKind = X86ISD::WrapperRIP;
12337 } else {
12338 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
12339 }
12340 } else {
12341 llvm_unreachable("Unexpected model");
12342 }
12344 // emit "addl x@ntpoff,%eax" (local exec)
12345 // or "addl x@indntpoff,%eax" (initial exec)
12346 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
12347 SDValue TGA =
12348 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
12349 GA->getOffset(), OperandFlags);
12350 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12352 if (model == TLSModel::InitialExec) {
12353 if (isPIC && !is64Bit) {
12354 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
12355 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12356 Offset);
12357 }
12359 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
12360 MachinePointerInfo::getGOT(), false, false, false, 0);
12361 }
12363 // The address of the thread local variable is the add of the thread
12364 // pointer with the offset of the variable.
12365 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
12366 }
12368 SDValue
12369 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
12371 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
12372 const GlobalValue *GV = GA->getGlobal();
12374 if (Subtarget->isTargetELF()) {
12375 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
12377 switch (model) {
12378 case TLSModel::GeneralDynamic:
12379 if (Subtarget->is64Bit())
12380 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
12381 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
12382 case TLSModel::LocalDynamic:
12383 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
12384 Subtarget->is64Bit());
12385 case TLSModel::InitialExec:
12386 case TLSModel::LocalExec:
12387 return LowerToTLSExecModel(
12388 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
12389 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
12390 }
12391 llvm_unreachable("Unknown TLS model.");
12392 }
12394 if (Subtarget->isTargetDarwin()) {
12395 // Darwin only has one model of TLS. Lower to that.
12396 unsigned char OpFlag = 0;
12397 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
12398 X86ISD::WrapperRIP : X86ISD::Wrapper;
12400 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12401 // global base reg.
12402 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
12403 !Subtarget->is64Bit();
12404 if (PIC32)
12405 OpFlag = X86II::MO_TLVP_PIC_BASE;
12406 else
12407 OpFlag = X86II::MO_TLVP;
12408 SDLoc DL(Op);
12409 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
12410 GA->getValueType(0),
12411 GA->getOffset(), OpFlag);
12412 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12414 // With PIC32, the address is actually $g + Offset.
12415 if (PIC32)
12416 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12417 DAG.getNode(X86ISD::GlobalBaseReg,
12418 SDLoc(), getPointerTy()),
12419 Offset);
12421 // Lowering the machine isd will make sure everything is in the right
12422 // location.
12423 SDValue Chain = DAG.getEntryNode();
12424 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12425 SDValue Args[] = { Chain, Offset };
12426 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
12428 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
12429 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12430 MFI->setAdjustsStack(true);
12432 // And our return value (tls address) is in the standard call return value
12433 // location.
12434 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12435 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
12436 Chain.getValue(1));
12437 }
12439 if (Subtarget->isTargetKnownWindowsMSVC() ||
12440 Subtarget->isTargetWindowsGNU()) {
12441 // Just use the implicit TLS architecture
12442 // Need to generate someting similar to:
12443 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
12444 // ; from TEB
12445 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
12446 // mov rcx, qword [rdx+rcx*8]
12447 // mov eax, .tls$:tlsvar
12448 // [rax+rcx] contains the address
12449 // Windows 64bit: gs:0x58
12450 // Windows 32bit: fs:__tls_array
12452 SDLoc dl(GA);
12453 SDValue Chain = DAG.getEntryNode();
12455 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
12456 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
12457 // use its literal value of 0x2C.
12458 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
12459 ? Type::getInt8PtrTy(*DAG.getContext(),
12460 256)
12461 : Type::getInt32PtrTy(*DAG.getContext(),
12462 257));
12464 SDValue TlsArray =
12465 Subtarget->is64Bit()
12466 ? DAG.getIntPtrConstant(0x58)
12467 : (Subtarget->isTargetWindowsGNU()
12468 ? DAG.getIntPtrConstant(0x2C)
12469 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
12471 SDValue ThreadPointer =
12472 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
12473 MachinePointerInfo(Ptr), false, false, false, 0);
12475 // Load the _tls_index variable
12476 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
12477 if (Subtarget->is64Bit())
12478 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
12479 IDX, MachinePointerInfo(), MVT::i32,
12480 false, false, false, 0);
12481 else
12482 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
12483 false, false, false, 0);
12485 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
12486 getPointerTy());
12487 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
12489 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
12490 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
12491 false, false, false, 0);
12493 // Get the offset of start of .tls section
12494 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12495 GA->getValueType(0),
12496 GA->getOffset(), X86II::MO_SECREL);
12497 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
12499 // The address of the thread local variable is the add of the thread
12500 // pointer with the offset of the variable.
12501 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
12502 }
12504 llvm_unreachable("TLS not implemented for this target.");
12505 }
12507 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
12508 /// and take a 2 x i32 value to shift plus a shift amount.
12509 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
12510 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
12511 MVT VT = Op.getSimpleValueType();
12512 unsigned VTBits = VT.getSizeInBits();
12513 SDLoc dl(Op);
12514 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
12515 SDValue ShOpLo = Op.getOperand(0);
12516 SDValue ShOpHi = Op.getOperand(1);
12517 SDValue ShAmt = Op.getOperand(2);
12518 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
12519 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
12520 // during isel.
12521 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12522 DAG.getConstant(VTBits - 1, MVT::i8));
12523 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
12524 DAG.getConstant(VTBits - 1, MVT::i8))
12525 : DAG.getConstant(0, VT);
12527 SDValue Tmp2, Tmp3;
12528 if (Op.getOpcode() == ISD::SHL_PARTS) {
12529 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
12530 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
12531 } else {
12532 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
12533 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
12534 }
12536 // If the shift amount is larger or equal than the width of a part we can't
12537 // rely on the results of shld/shrd. Insert a test and select the appropriate
12538 // values for large shift amounts.
12539 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12540 DAG.getConstant(VTBits, MVT::i8));
12541 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
12542 AndNode, DAG.getConstant(0, MVT::i8));
12544 SDValue Hi, Lo;
12545 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
12546 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
12547 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
12549 if (Op.getOpcode() == ISD::SHL_PARTS) {
12550 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12551 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12552 } else {
12553 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12554 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12555 }
12557 SDValue Ops[2] = { Lo, Hi };
12558 return DAG.getMergeValues(Ops, dl);
12559 }
12561 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
12562 SelectionDAG &DAG) const {
12563 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
12565 if (SrcVT.isVector())
12566 return SDValue();
12568 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
12569 "Unknown SINT_TO_FP to lower!");
12571 // These are really Legal; return the operand so the caller accepts it as
12572 // Legal.
12573 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
12574 return Op;
12575 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
12576 Subtarget->is64Bit()) {
12577 return Op;
12578 }
12580 SDLoc dl(Op);
12581 unsigned Size = SrcVT.getSizeInBits()/8;
12582 MachineFunction &MF = DAG.getMachineFunction();
12583 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
12584 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12585 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12586 StackSlot,
12587 MachinePointerInfo::getFixedStack(SSFI),
12588 false, false, 0);
12589 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
12590 }
12592 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
12593 SDValue StackSlot,
12594 SelectionDAG &DAG) const {
12595 // Build the FILD
12596 SDLoc DL(Op);
12597 SDVTList Tys;
12598 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
12599 if (useSSE)
12600 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
12601 else
12602 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
12604 unsigned ByteSize = SrcVT.getSizeInBits()/8;
12606 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
12607 MachineMemOperand *MMO;
12608 if (FI) {
12609 int SSFI = FI->getIndex();
12610 MMO =
12611 DAG.getMachineFunction()
12612 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12613 MachineMemOperand::MOLoad, ByteSize, ByteSize);
12614 } else {
12615 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
12616 StackSlot = StackSlot.getOperand(1);
12617 }
12618 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
12619 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
12620 X86ISD::FILD, DL,
12621 Tys, Ops, SrcVT, MMO);
12623 if (useSSE) {
12624 Chain = Result.getValue(1);
12625 SDValue InFlag = Result.getValue(2);
12627 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
12628 // shouldn't be necessary except that RFP cannot be live across
12629 // multiple blocks. When stackifier is fixed, they can be uncoupled.
12630 MachineFunction &MF = DAG.getMachineFunction();
12631 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
12632 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
12633 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12634 Tys = DAG.getVTList(MVT::Other);
12635 SDValue Ops[] = {
12636 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
12637 };
12638 MachineMemOperand *MMO =
12639 DAG.getMachineFunction()
12640 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12641 MachineMemOperand::MOStore, SSFISize, SSFISize);
12643 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
12644 Ops, Op.getValueType(), MMO);
12645 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
12646 MachinePointerInfo::getFixedStack(SSFI),
12647 false, false, false, 0);
12648 }
12650 return Result;
12651 }
12653 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
12654 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
12655 SelectionDAG &DAG) const {
12656 // This algorithm is not obvious. Here it is what we're trying to output:
12657 /*
12658 movq %rax, %xmm0
12659 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
12660 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
12661 #ifdef __SSE3__
12662 haddpd %xmm0, %xmm0
12663 #else
12664 pshufd $0x4e, %xmm0, %xmm1
12665 addpd %xmm1, %xmm0
12666 #endif
12667 */
12669 SDLoc dl(Op);
12670 LLVMContext *Context = DAG.getContext();
12672 // Build some magic constants.
12673 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
12674 Constant *C0 = ConstantDataVector::get(*Context, CV0);
12675 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
12677 SmallVector<Constant*,2> CV1;
12678 CV1.push_back(
12679 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12680 APInt(64, 0x4330000000000000ULL))));
12681 CV1.push_back(
12682 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12683 APInt(64, 0x4530000000000000ULL))));
12684 Constant *C1 = ConstantVector::get(CV1);
12685 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
12687 // Load the 64-bit value into an XMM register.
12688 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
12689 Op.getOperand(0));
12690 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
12691 MachinePointerInfo::getConstantPool(),
12692 false, false, false, 16);
12693 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
12694 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
12695 CLod0);
12697 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
12698 MachinePointerInfo::getConstantPool(),
12699 false, false, false, 16);
12700 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
12701 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
12702 SDValue Result;
12704 if (Subtarget->hasSSE3()) {
12705 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
12706 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
12707 } else {
12708 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
12709 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
12710 S2F, 0x4E, DAG);
12711 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
12712 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
12713 Sub);
12714 }
12716 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
12717 DAG.getIntPtrConstant(0));
12718 }
12720 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
12721 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
12722 SelectionDAG &DAG) const {
12723 SDLoc dl(Op);
12724 // FP constant to bias correct the final result.
12725 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
12726 MVT::f64);
12728 // Load the 32-bit value into an XMM register.
12729 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
12730 Op.getOperand(0));
12732 // Zero out the upper parts of the register.
12733 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
12735 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12736 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
12737 DAG.getIntPtrConstant(0));
12739 // Or the load with the bias.
12740 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
12741 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
12742 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
12743 MVT::v2f64, Load)),
12744 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
12745 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
12746 MVT::v2f64, Bias)));
12747 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12748 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
12749 DAG.getIntPtrConstant(0));
12751 // Subtract the bias.
12752 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
12754 // Handle final rounding.
12755 EVT DestVT = Op.getValueType();
12757 if (DestVT.bitsLT(MVT::f64))
12758 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
12759 DAG.getIntPtrConstant(0));
12760 if (DestVT.bitsGT(MVT::f64))
12761 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
12763 // Handle final rounding.
12764 return Sub;
12765 }
12767 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
12768 SelectionDAG &DAG) const {
12769 SDValue N0 = Op.getOperand(0);
12770 MVT SVT = N0.getSimpleValueType();
12771 SDLoc dl(Op);
12773 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
12774 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
12775 "Custom UINT_TO_FP is not supported!");
12777 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
12778 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12779 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
12780 }
12782 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
12783 SelectionDAG &DAG) const {
12784 SDValue N0 = Op.getOperand(0);
12785 SDLoc dl(Op);
12787 if (Op.getValueType().isVector())
12788 return lowerUINT_TO_FP_vec(Op, DAG);
12790 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
12791 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
12792 // the optimization here.
12793 if (DAG.SignBitIsZero(N0))
12794 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
12796 MVT SrcVT = N0.getSimpleValueType();
12797 MVT DstVT = Op.getSimpleValueType();
12798 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
12799 return LowerUINT_TO_FP_i64(Op, DAG);
12800 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
12801 return LowerUINT_TO_FP_i32(Op, DAG);
12802 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
12803 return SDValue();
12805 // Make a 64-bit buffer, and use it to build an FILD.
12806 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
12807 if (SrcVT == MVT::i32) {
12808 SDValue WordOff = DAG.getConstant(4, getPointerTy());
12809 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
12810 getPointerTy(), StackSlot, WordOff);
12811 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12812 StackSlot, MachinePointerInfo(),
12813 false, false, 0);
12814 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
12815 OffsetSlot, MachinePointerInfo(),
12816 false, false, 0);
12817 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
12818 return Fild;
12819 }
12821 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
12822 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12823 StackSlot, MachinePointerInfo(),
12824 false, false, 0);
12825 // For i64 source, we need to add the appropriate power of 2 if the input
12826 // was negative. This is the same as the optimization in
12827 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
12828 // we must be careful to do the computation in x87 extended precision, not
12829 // in SSE. (The generic code can't know it's OK to do this, or how to.)
12830 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
12831 MachineMemOperand *MMO =
12832 DAG.getMachineFunction()
12833 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12834 MachineMemOperand::MOLoad, 8, 8);
12836 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
12837 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
12838 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
12839 MVT::i64, MMO);
12841 APInt FF(32, 0x5F800000ULL);
12843 // Check whether the sign bit is set.
12844 SDValue SignSet = DAG.getSetCC(dl,
12845 getSetCCResultType(*DAG.getContext(), MVT::i64),
12846 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
12847 ISD::SETLT);
12849 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
12850 SDValue FudgePtr = DAG.getConstantPool(
12851 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
12852 getPointerTy());
12854 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
12855 SDValue Zero = DAG.getIntPtrConstant(0);
12856 SDValue Four = DAG.getIntPtrConstant(4);
12857 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
12858 Zero, Four);
12859 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
12861 // Load the value out, extending it from f32 to f80.
12862 // FIXME: Avoid the extend by constructing the right constant pool?
12863 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
12864 FudgePtr, MachinePointerInfo::getConstantPool(),
12865 MVT::f32, false, false, false, 4);
12866 // Extend everything to 80 bits to force it to be done on x87.
12867 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
12868 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
12869 }
12871 std::pair<SDValue,SDValue>
12872 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
12873 bool IsSigned, bool IsReplace) const {
12874 SDLoc DL(Op);
12876 EVT DstTy = Op.getValueType();
12878 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
12879 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
12880 DstTy = MVT::i64;
12881 }
12883 assert(DstTy.getSimpleVT() <= MVT::i64 &&
12884 DstTy.getSimpleVT() >= MVT::i16 &&
12885 "Unknown FP_TO_INT to lower!");
12887 // These are really Legal.
12888 if (DstTy == MVT::i32 &&
12889 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12890 return std::make_pair(SDValue(), SDValue());
12891 if (Subtarget->is64Bit() &&
12892 DstTy == MVT::i64 &&
12893 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12894 return std::make_pair(SDValue(), SDValue());
12896 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
12897 // stack slot, or into the FTOL runtime function.
12898 MachineFunction &MF = DAG.getMachineFunction();
12899 unsigned MemSize = DstTy.getSizeInBits()/8;
12900 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12901 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12903 unsigned Opc;
12904 if (!IsSigned && isIntegerTypeFTOL(DstTy))
12905 Opc = X86ISD::WIN_FTOL;
12906 else
12907 switch (DstTy.getSimpleVT().SimpleTy) {
12908 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
12909 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
12910 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
12911 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
12912 }
12914 SDValue Chain = DAG.getEntryNode();
12915 SDValue Value = Op.getOperand(0);
12916 EVT TheVT = Op.getOperand(0).getValueType();
12917 // FIXME This causes a redundant load/store if the SSE-class value is already
12918 // in memory, such as if it is on the callstack.
12919 if (isScalarFPTypeInSSEReg(TheVT)) {
12920 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
12921 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
12922 MachinePointerInfo::getFixedStack(SSFI),
12923 false, false, 0);
12924 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
12925 SDValue Ops[] = {
12926 Chain, StackSlot, DAG.getValueType(TheVT)
12927 };
12929 MachineMemOperand *MMO =
12930 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12931 MachineMemOperand::MOLoad, MemSize, MemSize);
12932 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
12933 Chain = Value.getValue(1);
12934 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12935 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12936 }
12938 MachineMemOperand *MMO =
12939 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12940 MachineMemOperand::MOStore, MemSize, MemSize);
12942 if (Opc != X86ISD::WIN_FTOL) {
12943 // Build the FP_TO_INT*_IN_MEM
12944 SDValue Ops[] = { Chain, Value, StackSlot };
12945 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12946 Ops, DstTy, MMO);
12947 return std::make_pair(FIST, StackSlot);
12948 } else {
12949 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
12950 DAG.getVTList(MVT::Other, MVT::Glue),
12951 Chain, Value);
12952 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
12953 MVT::i32, ftol.getValue(1));
12954 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
12955 MVT::i32, eax.getValue(2));
12956 SDValue Ops[] = { eax, edx };
12957 SDValue pair = IsReplace
12958 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
12959 : DAG.getMergeValues(Ops, DL);
12960 return std::make_pair(pair, SDValue());
12961 }
12962 }
12964 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
12965 const X86Subtarget *Subtarget) {
12966 MVT VT = Op->getSimpleValueType(0);
12967 SDValue In = Op->getOperand(0);
12968 MVT InVT = In.getSimpleValueType();
12969 SDLoc dl(Op);
12971 // Optimize vectors in AVX mode:
12972 //
12973 // v8i16 -> v8i32
12974 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
12975 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
12976 // Concat upper and lower parts.
12977 //
12978 // v4i32 -> v4i64
12979 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
12980 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
12981 // Concat upper and lower parts.
12982 //
12984 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
12985 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
12986 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
12987 return SDValue();
12989 if (Subtarget->hasInt256())
12990 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
12992 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
12993 SDValue Undef = DAG.getUNDEF(InVT);
12994 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
12995 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12996 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12998 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
12999 VT.getVectorNumElements()/2);
13001 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
13002 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
13004 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13005 }
13007 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
13008 SelectionDAG &DAG) {
13009 MVT VT = Op->getSimpleValueType(0);
13010 SDValue In = Op->getOperand(0);
13011 MVT InVT = In.getSimpleValueType();
13012 SDLoc DL(Op);
13013 unsigned int NumElts = VT.getVectorNumElements();
13014 if (NumElts != 8 && NumElts != 16)
13015 return SDValue();
13017 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
13018 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
13020 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
13021 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13022 // Now we have only mask extension
13023 assert(InVT.getVectorElementType() == MVT::i1);
13024 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
13025 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
13026 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
13027 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13028 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
13029 MachinePointerInfo::getConstantPool(),
13030 false, false, false, Alignment);
13032 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
13033 if (VT.is512BitVector())
13034 return Brcst;
13035 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
13036 }
13038 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13039 SelectionDAG &DAG) {
13040 if (Subtarget->hasFp256()) {
13041 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
13042 if (Res.getNode())
13043 return Res;
13044 }
13046 return SDValue();
13047 }
13049 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13050 SelectionDAG &DAG) {
13051 SDLoc DL(Op);
13052 MVT VT = Op.getSimpleValueType();
13053 SDValue In = Op.getOperand(0);
13054 MVT SVT = In.getSimpleValueType();
13056 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
13057 return LowerZERO_EXTEND_AVX512(Op, DAG);
13059 if (Subtarget->hasFp256()) {
13060 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
13061 if (Res.getNode())
13062 return Res;
13063 }
13065 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
13066 VT.getVectorNumElements() != SVT.getVectorNumElements());
13067 return SDValue();
13068 }
13070 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
13071 SDLoc DL(Op);
13072 MVT VT = Op.getSimpleValueType();
13073 SDValue In = Op.getOperand(0);
13074 MVT InVT = In.getSimpleValueType();
13076 if (VT == MVT::i1) {
13077 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
13078 "Invalid scalar TRUNCATE operation");
13079 if (InVT.getSizeInBits() >= 32)
13080 return SDValue();
13081 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
13082 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
13083 }
13084 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
13085 "Invalid TRUNCATE operation");
13087 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
13088 if (VT.getVectorElementType().getSizeInBits() >=8)
13089 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
13091 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13092 unsigned NumElts = InVT.getVectorNumElements();
13093 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
13094 if (InVT.getSizeInBits() < 512) {
13095 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
13096 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
13097 InVT = ExtVT;
13098 }
13100 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
13101 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
13102 SDValue CP = DAG.getConstantPool(C, getPointerTy());
13103 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13104 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
13105 MachinePointerInfo::getConstantPool(),
13106 false, false, false, Alignment);
13107 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
13108 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
13109 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
13110 }
13112 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
13113 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
13114 if (Subtarget->hasInt256()) {
13115 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13116 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
13117 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
13118 ShufMask);
13119 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
13120 DAG.getIntPtrConstant(0));
13121 }
13123 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13124 DAG.getIntPtrConstant(0));
13125 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13126 DAG.getIntPtrConstant(2));
13127 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
13128 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
13129 static const int ShufMask[] = {0, 2, 4, 6};
13130 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
13131 }
13133 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
13134 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
13135 if (Subtarget->hasInt256()) {
13136 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
13138 SmallVector<SDValue,32> pshufbMask;
13139 for (unsigned i = 0; i < 2; ++i) {
13140 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
13141 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
13142 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
13143 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
13144 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
13145 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
13146 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
13147 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
13148 for (unsigned j = 0; j < 8; ++j)
13149 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
13150 }
13151 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
13152 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
13153 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
13155 static const int ShufMask[] = {0, 2, -1, -1};
13156 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
13157 &ShufMask[0]);
13158 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13159 DAG.getIntPtrConstant(0));
13160 return DAG.getNode(ISD::BITCAST, DL, VT, In);
13161 }
13163 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13164 DAG.getIntPtrConstant(0));
13166 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13167 DAG.getIntPtrConstant(4));
13169 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
13170 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
13172 // The PSHUFB mask:
13173 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13174 -1, -1, -1, -1, -1, -1, -1, -1};
13176 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
13177 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
13178 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
13180 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
13181 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
13183 // The MOVLHPS Mask:
13184 static const int ShufMask2[] = {0, 1, 4, 5};
13185 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
13186 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
13187 }
13189 // Handle truncation of V256 to V128 using shuffles.
13190 if (!VT.is128BitVector() || !InVT.is256BitVector())
13191 return SDValue();
13193 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
13195 unsigned NumElems = VT.getVectorNumElements();
13196 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
13198 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
13199 // Prepare truncation shuffle mask
13200 for (unsigned i = 0; i != NumElems; ++i)
13201 MaskVec[i] = i * 2;
13202 SDValue V = DAG.getVectorShuffle(NVT, DL,
13203 DAG.getNode(ISD::BITCAST, DL, NVT, In),
13204 DAG.getUNDEF(NVT), &MaskVec[0]);
13205 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
13206 DAG.getIntPtrConstant(0));
13207 }
13209 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
13210 SelectionDAG &DAG) const {
13211 assert(!Op.getSimpleValueType().isVector());
13213 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13214 /*IsSigned=*/ true, /*IsReplace=*/ false);
13215 SDValue FIST = Vals.first, StackSlot = Vals.second;
13216 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13217 if (!FIST.getNode()) return Op;
13219 if (StackSlot.getNode())
13220 // Load the result.
13221 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13222 FIST, StackSlot, MachinePointerInfo(),
13223 false, false, false, 0);
13225 // The node is the result.
13226 return FIST;
13227 }
13229 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
13230 SelectionDAG &DAG) const {
13231 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13232 /*IsSigned=*/ false, /*IsReplace=*/ false);
13233 SDValue FIST = Vals.first, StackSlot = Vals.second;
13234 assert(FIST.getNode() && "Unexpected failure");
13236 if (StackSlot.getNode())
13237 // Load the result.
13238 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13239 FIST, StackSlot, MachinePointerInfo(),
13240 false, false, false, 0);
13242 // The node is the result.
13243 return FIST;
13244 }
13246 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
13247 SDLoc DL(Op);
13248 MVT VT = Op.getSimpleValueType();
13249 SDValue In = Op.getOperand(0);
13250 MVT SVT = In.getSimpleValueType();
13252 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
13254 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
13255 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
13256 In, DAG.getUNDEF(SVT)));
13257 }
13259 // The only differences between FABS and FNEG are the mask and the logic op.
13260 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
13261 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
13262 "Wrong opcode for lowering FABS or FNEG.");
13264 bool IsFABS = (Op.getOpcode() == ISD::FABS);
13265 SDLoc dl(Op);
13266 MVT VT = Op.getSimpleValueType();
13267 // Assume scalar op for initialization; update for vector if needed.
13268 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
13269 // generate a 16-byte vector constant and logic op even for the scalar case.
13270 // Using a 16-byte mask allows folding the load of the mask with
13271 // the logic op, so it can save (~4 bytes) on code size.
13272 MVT EltVT = VT;
13273 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
13274 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
13275 // decide if we should generate a 16-byte constant mask when we only need 4 or
13276 // 8 bytes for the scalar case.
13277 if (VT.isVector()) {
13278 EltVT = VT.getVectorElementType();
13279 NumElts = VT.getVectorNumElements();
13280 }
13282 unsigned EltBits = EltVT.getSizeInBits();
13283 LLVMContext *Context = DAG.getContext();
13284 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
13285 APInt MaskElt =
13286 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
13287 Constant *C = ConstantInt::get(*Context, MaskElt);
13288 C = ConstantVector::getSplat(NumElts, C);
13289 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13290 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
13291 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13292 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
13293 MachinePointerInfo::getConstantPool(),
13294 false, false, false, Alignment);
13296 if (VT.isVector()) {
13297 // For a vector, cast operands to a vector type, perform the logic op,
13298 // and cast the result back to the original value type.
13299 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
13300 SDValue Op0Casted = DAG.getNode(ISD::BITCAST, dl, VecVT, Op.getOperand(0));
13301 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
13302 unsigned LogicOp = IsFABS ? ISD::AND : ISD::XOR;
13303 return DAG.getNode(ISD::BITCAST, dl, VT,
13304 DAG.getNode(LogicOp, dl, VecVT, Op0Casted, MaskCasted));
13305 }
13306 // If not vector, then scalar.
13307 unsigned LogicOp = IsFABS ? X86ISD::FAND : X86ISD::FXOR;
13308 return DAG.getNode(LogicOp, dl, VT, Op.getOperand(0), Mask);
13309 }
13311 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
13312 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13313 LLVMContext *Context = DAG.getContext();
13314 SDValue Op0 = Op.getOperand(0);
13315 SDValue Op1 = Op.getOperand(1);
13316 SDLoc dl(Op);
13317 MVT VT = Op.getSimpleValueType();
13318 MVT SrcVT = Op1.getSimpleValueType();
13320 // If second operand is smaller, extend it first.
13321 if (SrcVT.bitsLT(VT)) {
13322 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
13323 SrcVT = VT;
13324 }
13325 // And if it is bigger, shrink it first.
13326 if (SrcVT.bitsGT(VT)) {
13327 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
13328 SrcVT = VT;
13329 }
13331 // At this point the operands and the result should have the same
13332 // type, and that won't be f80 since that is not custom lowered.
13334 // First get the sign bit of second operand.
13335 SmallVector<Constant*,4> CV;
13336 if (SrcVT == MVT::f64) {
13337 const fltSemantics &Sem = APFloat::IEEEdouble;
13338 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
13339 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
13340 } else {
13341 const fltSemantics &Sem = APFloat::IEEEsingle;
13342 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
13343 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13344 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13345 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13346 }
13347 Constant *C = ConstantVector::get(CV);
13348 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
13349 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
13350 MachinePointerInfo::getConstantPool(),
13351 false, false, false, 16);
13352 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
13354 // Shift sign bit right or left if the two operands have different types.
13355 if (SrcVT.bitsGT(VT)) {
13356 // Op0 is MVT::f32, Op1 is MVT::f64.
13357 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
13358 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
13359 DAG.getConstant(32, MVT::i32));
13360 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
13361 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
13362 DAG.getIntPtrConstant(0));
13363 }
13365 // Clear first operand sign bit.
13366 CV.clear();
13367 if (VT == MVT::f64) {
13368 const fltSemantics &Sem = APFloat::IEEEdouble;
13369 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
13370 APInt(64, ~(1ULL << 63)))));
13371 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
13372 } else {
13373 const fltSemantics &Sem = APFloat::IEEEsingle;
13374 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
13375 APInt(32, ~(1U << 31)))));
13376 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13377 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13378 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13379 }
13380 C = ConstantVector::get(CV);
13381 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
13382 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
13383 MachinePointerInfo::getConstantPool(),
13384 false, false, false, 16);
13385 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
13387 // Or the value with the sign bit.
13388 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
13389 }
13391 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
13392 SDValue N0 = Op.getOperand(0);
13393 SDLoc dl(Op);
13394 MVT VT = Op.getSimpleValueType();
13396 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
13397 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
13398 DAG.getConstant(1, VT));
13399 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
13400 }
13402 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
13403 //
13404 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
13405 SelectionDAG &DAG) {
13406 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
13408 if (!Subtarget->hasSSE41())
13409 return SDValue();
13411 if (!Op->hasOneUse())
13412 return SDValue();
13414 SDNode *N = Op.getNode();
13415 SDLoc DL(N);
13417 SmallVector<SDValue, 8> Opnds;
13418 DenseMap<SDValue, unsigned> VecInMap;
13419 SmallVector<SDValue, 8> VecIns;
13420 EVT VT = MVT::Other;
13422 // Recognize a special case where a vector is casted into wide integer to
13423 // test all 0s.
13424 Opnds.push_back(N->getOperand(0));
13425 Opnds.push_back(N->getOperand(1));
13427 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
13428 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
13429 // BFS traverse all OR'd operands.
13430 if (I->getOpcode() == ISD::OR) {
13431 Opnds.push_back(I->getOperand(0));
13432 Opnds.push_back(I->getOperand(1));
13433 // Re-evaluate the number of nodes to be traversed.
13434 e += 2; // 2 more nodes (LHS and RHS) are pushed.
13435 continue;
13436 }
13438 // Quit if a non-EXTRACT_VECTOR_ELT
13439 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13440 return SDValue();
13442 // Quit if without a constant index.
13443 SDValue Idx = I->getOperand(1);
13444 if (!isa<ConstantSDNode>(Idx))
13445 return SDValue();
13447 SDValue ExtractedFromVec = I->getOperand(0);
13448 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
13449 if (M == VecInMap.end()) {
13450 VT = ExtractedFromVec.getValueType();
13451 // Quit if not 128/256-bit vector.
13452 if (!VT.is128BitVector() && !VT.is256BitVector())
13453 return SDValue();
13454 // Quit if not the same type.
13455 if (VecInMap.begin() != VecInMap.end() &&
13456 VT != VecInMap.begin()->first.getValueType())
13457 return SDValue();
13458 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
13459 VecIns.push_back(ExtractedFromVec);
13460 }
13461 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
13462 }
13464 assert((VT.is128BitVector() || VT.is256BitVector()) &&
13465 "Not extracted from 128-/256-bit vector.");
13467 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
13469 for (DenseMap<SDValue, unsigned>::const_iterator
13470 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
13471 // Quit if not all elements are used.
13472 if (I->second != FullMask)
13473 return SDValue();
13474 }
13476 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
13478 // Cast all vectors into TestVT for PTEST.
13479 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
13480 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
13482 // If more than one full vectors are evaluated, OR them first before PTEST.
13483 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
13484 // Each iteration will OR 2 nodes and append the result until there is only
13485 // 1 node left, i.e. the final OR'd value of all vectors.
13486 SDValue LHS = VecIns[Slot];
13487 SDValue RHS = VecIns[Slot + 1];
13488 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
13489 }
13491 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
13492 VecIns.back(), VecIns.back());
13493 }
13495 /// \brief return true if \c Op has a use that doesn't just read flags.
13496 static bool hasNonFlagsUse(SDValue Op) {
13497 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
13498 ++UI) {
13499 SDNode *User = *UI;
13500 unsigned UOpNo = UI.getOperandNo();
13501 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
13502 // Look pass truncate.
13503 UOpNo = User->use_begin().getOperandNo();
13504 User = *User->use_begin();
13505 }
13507 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
13508 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
13509 return true;
13510 }
13511 return false;
13512 }
13514 /// Emit nodes that will be selected as "test Op0,Op0", or something
13515 /// equivalent.
13516 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
13517 SelectionDAG &DAG) const {
13518 if (Op.getValueType() == MVT::i1)
13519 // KORTEST instruction should be selected
13520 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13521 DAG.getConstant(0, Op.getValueType()));
13523 // CF and OF aren't always set the way we want. Determine which
13524 // of these we need.
13525 bool NeedCF = false;
13526 bool NeedOF = false;
13527 switch (X86CC) {
13528 default: break;
13529 case X86::COND_A: case X86::COND_AE:
13530 case X86::COND_B: case X86::COND_BE:
13531 NeedCF = true;
13532 break;
13533 case X86::COND_G: case X86::COND_GE:
13534 case X86::COND_L: case X86::COND_LE:
13535 case X86::COND_O: case X86::COND_NO: {
13536 // Check if we really need to set the
13537 // Overflow flag. If NoSignedWrap is present
13538 // that is not actually needed.
13539 switch (Op->getOpcode()) {
13540 case ISD::ADD:
13541 case ISD::SUB:
13542 case ISD::MUL:
13543 case ISD::SHL: {
13544 const BinaryWithFlagsSDNode *BinNode =
13545 cast<BinaryWithFlagsSDNode>(Op.getNode());
13546 if (BinNode->hasNoSignedWrap())
13547 break;
13548 }
13549 default:
13550 NeedOF = true;
13551 break;
13552 }
13553 break;
13554 }
13555 }
13556 // See if we can use the EFLAGS value from the operand instead of
13557 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
13558 // we prove that the arithmetic won't overflow, we can't use OF or CF.
13559 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
13560 // Emit a CMP with 0, which is the TEST pattern.
13561 //if (Op.getValueType() == MVT::i1)
13562 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
13563 // DAG.getConstant(0, MVT::i1));
13564 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13565 DAG.getConstant(0, Op.getValueType()));
13566 }
13567 unsigned Opcode = 0;
13568 unsigned NumOperands = 0;
13570 // Truncate operations may prevent the merge of the SETCC instruction
13571 // and the arithmetic instruction before it. Attempt to truncate the operands
13572 // of the arithmetic instruction and use a reduced bit-width instruction.
13573 bool NeedTruncation = false;
13574 SDValue ArithOp = Op;
13575 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
13576 SDValue Arith = Op->getOperand(0);
13577 // Both the trunc and the arithmetic op need to have one user each.
13578 if (Arith->hasOneUse())
13579 switch (Arith.getOpcode()) {
13580 default: break;
13581 case ISD::ADD:
13582 case ISD::SUB:
13583 case ISD::AND:
13584 case ISD::OR:
13585 case ISD::XOR: {
13586 NeedTruncation = true;
13587 ArithOp = Arith;
13588 }
13589 }
13590 }
13592 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
13593 // which may be the result of a CAST. We use the variable 'Op', which is the
13594 // non-casted variable when we check for possible users.
13595 switch (ArithOp.getOpcode()) {
13596 case ISD::ADD:
13597 // Due to an isel shortcoming, be conservative if this add is likely to be
13598 // selected as part of a load-modify-store instruction. When the root node
13599 // in a match is a store, isel doesn't know how to remap non-chain non-flag
13600 // uses of other nodes in the match, such as the ADD in this case. This
13601 // leads to the ADD being left around and reselected, with the result being
13602 // two adds in the output. Alas, even if none our users are stores, that
13603 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
13604 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
13605 // climbing the DAG back to the root, and it doesn't seem to be worth the
13606 // effort.
13607 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13608 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13609 if (UI->getOpcode() != ISD::CopyToReg &&
13610 UI->getOpcode() != ISD::SETCC &&
13611 UI->getOpcode() != ISD::STORE)
13612 goto default_case;
13614 if (ConstantSDNode *C =
13615 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
13616 // An add of one will be selected as an INC.
13617 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
13618 Opcode = X86ISD::INC;
13619 NumOperands = 1;
13620 break;
13621 }
13623 // An add of negative one (subtract of one) will be selected as a DEC.
13624 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
13625 Opcode = X86ISD::DEC;
13626 NumOperands = 1;
13627 break;
13628 }
13629 }
13631 // Otherwise use a regular EFLAGS-setting add.
13632 Opcode = X86ISD::ADD;
13633 NumOperands = 2;
13634 break;
13635 case ISD::SHL:
13636 case ISD::SRL:
13637 // If we have a constant logical shift that's only used in a comparison
13638 // against zero turn it into an equivalent AND. This allows turning it into
13639 // a TEST instruction later.
13640 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
13641 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
13642 EVT VT = Op.getValueType();
13643 unsigned BitWidth = VT.getSizeInBits();
13644 unsigned ShAmt = Op->getConstantOperandVal(1);
13645 if (ShAmt >= BitWidth) // Avoid undefined shifts.
13646 break;
13647 APInt Mask = ArithOp.getOpcode() == ISD::SRL
13648 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
13649 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
13650 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
13651 break;
13652 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
13653 DAG.getConstant(Mask, VT));
13654 DAG.ReplaceAllUsesWith(Op, New);
13655 Op = New;
13656 }
13657 break;
13659 case ISD::AND:
13660 // If the primary and result isn't used, don't bother using X86ISD::AND,
13661 // because a TEST instruction will be better.
13662 if (!hasNonFlagsUse(Op))
13663 break;
13664 // FALL THROUGH
13665 case ISD::SUB:
13666 case ISD::OR:
13667 case ISD::XOR:
13668 // Due to the ISEL shortcoming noted above, be conservative if this op is
13669 // likely to be selected as part of a load-modify-store instruction.
13670 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13671 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13672 if (UI->getOpcode() == ISD::STORE)
13673 goto default_case;
13675 // Otherwise use a regular EFLAGS-setting instruction.
13676 switch (ArithOp.getOpcode()) {
13677 default: llvm_unreachable("unexpected operator!");
13678 case ISD::SUB: Opcode = X86ISD::SUB; break;
13679 case ISD::XOR: Opcode = X86ISD::XOR; break;
13680 case ISD::AND: Opcode = X86ISD::AND; break;
13681 case ISD::OR: {
13682 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
13683 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
13684 if (EFLAGS.getNode())
13685 return EFLAGS;
13686 }
13687 Opcode = X86ISD::OR;
13688 break;
13689 }
13690 }
13692 NumOperands = 2;
13693 break;
13694 case X86ISD::ADD:
13695 case X86ISD::SUB:
13696 case X86ISD::INC:
13697 case X86ISD::DEC:
13698 case X86ISD::OR:
13699 case X86ISD::XOR:
13700 case X86ISD::AND:
13701 return SDValue(Op.getNode(), 1);
13702 default:
13703 default_case:
13704 break;
13705 }
13707 // If we found that truncation is beneficial, perform the truncation and
13708 // update 'Op'.
13709 if (NeedTruncation) {
13710 EVT VT = Op.getValueType();
13711 SDValue WideVal = Op->getOperand(0);
13712 EVT WideVT = WideVal.getValueType();
13713 unsigned ConvertedOp = 0;
13714 // Use a target machine opcode to prevent further DAGCombine
13715 // optimizations that may separate the arithmetic operations
13716 // from the setcc node.
13717 switch (WideVal.getOpcode()) {
13718 default: break;
13719 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
13720 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
13721 case ISD::AND: ConvertedOp = X86ISD::AND; break;
13722 case ISD::OR: ConvertedOp = X86ISD::OR; break;
13723 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
13724 }
13726 if (ConvertedOp) {
13727 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13728 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
13729 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
13730 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
13731 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
13732 }
13733 }
13734 }
13736 if (Opcode == 0)
13737 // Emit a CMP with 0, which is the TEST pattern.
13738 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13739 DAG.getConstant(0, Op.getValueType()));
13741 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
13742 SmallVector<SDValue, 4> Ops;
13743 for (unsigned i = 0; i != NumOperands; ++i)
13744 Ops.push_back(Op.getOperand(i));
13746 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
13747 DAG.ReplaceAllUsesWith(Op, New);
13748 return SDValue(New.getNode(), 1);
13749 }
13751 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
13752 /// equivalent.
13753 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
13754 SDLoc dl, SelectionDAG &DAG) const {
13755 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
13756 if (C->getAPIntValue() == 0)
13757 return EmitTest(Op0, X86CC, dl, DAG);
13759 if (Op0.getValueType() == MVT::i1)
13760 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
13761 }
13763 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
13764 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
13765 // Do the comparison at i32 if it's smaller, besides the Atom case.
13766 // This avoids subregister aliasing issues. Keep the smaller reference
13767 // if we're optimizing for size, however, as that'll allow better folding
13768 // of memory operations.
13769 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
13770 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
13771 AttributeSet::FunctionIndex, Attribute::MinSize) &&
13772 !Subtarget->isAtom()) {
13773 unsigned ExtendOp =
13774 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
13775 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
13776 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
13777 }
13778 // Use SUB instead of CMP to enable CSE between SUB and CMP.
13779 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
13780 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
13781 Op0, Op1);
13782 return SDValue(Sub.getNode(), 1);
13783 }
13784 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
13785 }
13787 /// Convert a comparison if required by the subtarget.
13788 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
13789 SelectionDAG &DAG) const {
13790 // If the subtarget does not support the FUCOMI instruction, floating-point
13791 // comparisons have to be converted.
13792 if (Subtarget->hasCMov() ||
13793 Cmp.getOpcode() != X86ISD::CMP ||
13794 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
13795 !Cmp.getOperand(1).getValueType().isFloatingPoint())
13796 return Cmp;
13798 // The instruction selector will select an FUCOM instruction instead of
13799 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
13800 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
13801 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
13802 SDLoc dl(Cmp);
13803 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
13804 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
13805 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
13806 DAG.getConstant(8, MVT::i8));
13807 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
13808 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
13809 }
13811 static bool isAllOnes(SDValue V) {
13812 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
13813 return C && C->isAllOnesValue();
13814 }
13816 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
13817 /// if it's possible.
13818 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
13819 SDLoc dl, SelectionDAG &DAG) const {
13820 SDValue Op0 = And.getOperand(0);
13821 SDValue Op1 = And.getOperand(1);
13822 if (Op0.getOpcode() == ISD::TRUNCATE)
13823 Op0 = Op0.getOperand(0);
13824 if (Op1.getOpcode() == ISD::TRUNCATE)
13825 Op1 = Op1.getOperand(0);
13827 SDValue LHS, RHS;
13828 if (Op1.getOpcode() == ISD::SHL)
13829 std::swap(Op0, Op1);
13830 if (Op0.getOpcode() == ISD::SHL) {
13831 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
13832 if (And00C->getZExtValue() == 1) {
13833 // If we looked past a truncate, check that it's only truncating away
13834 // known zeros.
13835 unsigned BitWidth = Op0.getValueSizeInBits();
13836 unsigned AndBitWidth = And.getValueSizeInBits();
13837 if (BitWidth > AndBitWidth) {
13838 APInt Zeros, Ones;
13839 DAG.computeKnownBits(Op0, Zeros, Ones);
13840 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
13841 return SDValue();
13842 }
13843 LHS = Op1;
13844 RHS = Op0.getOperand(1);
13845 }
13846 } else if (Op1.getOpcode() == ISD::Constant) {
13847 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
13848 uint64_t AndRHSVal = AndRHS->getZExtValue();
13849 SDValue AndLHS = Op0;
13851 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
13852 LHS = AndLHS.getOperand(0);
13853 RHS = AndLHS.getOperand(1);
13854 }
13856 // Use BT if the immediate can't be encoded in a TEST instruction.
13857 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
13858 LHS = AndLHS;
13859 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
13860 }
13861 }
13863 if (LHS.getNode()) {
13864 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
13865 // instruction. Since the shift amount is in-range-or-undefined, we know
13866 // that doing a bittest on the i32 value is ok. We extend to i32 because
13867 // the encoding for the i16 version is larger than the i32 version.
13868 // Also promote i16 to i32 for performance / code size reason.
13869 if (LHS.getValueType() == MVT::i8 ||
13870 LHS.getValueType() == MVT::i16)
13871 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
13873 // If the operand types disagree, extend the shift amount to match. Since
13874 // BT ignores high bits (like shifts) we can use anyextend.
13875 if (LHS.getValueType() != RHS.getValueType())
13876 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
13878 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
13879 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
13880 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13881 DAG.getConstant(Cond, MVT::i8), BT);
13882 }
13884 return SDValue();
13885 }
13887 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
13888 /// mask CMPs.
13889 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
13890 SDValue &Op1) {
13891 unsigned SSECC;
13892 bool Swap = false;
13894 // SSE Condition code mapping:
13895 // 0 - EQ
13896 // 1 - LT
13897 // 2 - LE
13898 // 3 - UNORD
13899 // 4 - NEQ
13900 // 5 - NLT
13901 // 6 - NLE
13902 // 7 - ORD
13903 switch (SetCCOpcode) {
13904 default: llvm_unreachable("Unexpected SETCC condition");
13905 case ISD::SETOEQ:
13906 case ISD::SETEQ: SSECC = 0; break;
13907 case ISD::SETOGT:
13908 case ISD::SETGT: Swap = true; // Fallthrough
13909 case ISD::SETLT:
13910 case ISD::SETOLT: SSECC = 1; break;
13911 case ISD::SETOGE:
13912 case ISD::SETGE: Swap = true; // Fallthrough
13913 case ISD::SETLE:
13914 case ISD::SETOLE: SSECC = 2; break;
13915 case ISD::SETUO: SSECC = 3; break;
13916 case ISD::SETUNE:
13917 case ISD::SETNE: SSECC = 4; break;
13918 case ISD::SETULE: Swap = true; // Fallthrough
13919 case ISD::SETUGE: SSECC = 5; break;
13920 case ISD::SETULT: Swap = true; // Fallthrough
13921 case ISD::SETUGT: SSECC = 6; break;
13922 case ISD::SETO: SSECC = 7; break;
13923 case ISD::SETUEQ:
13924 case ISD::SETONE: SSECC = 8; break;
13925 }
13926 if (Swap)
13927 std::swap(Op0, Op1);
13929 return SSECC;
13930 }
13932 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
13933 // ones, and then concatenate the result back.
13934 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
13935 MVT VT = Op.getSimpleValueType();
13937 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
13938 "Unsupported value type for operation");
13940 unsigned NumElems = VT.getVectorNumElements();
13941 SDLoc dl(Op);
13942 SDValue CC = Op.getOperand(2);
13944 // Extract the LHS vectors
13945 SDValue LHS = Op.getOperand(0);
13946 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13947 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13949 // Extract the RHS vectors
13950 SDValue RHS = Op.getOperand(1);
13951 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
13952 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
13954 // Issue the operation on the smaller types and concatenate the result back
13955 MVT EltVT = VT.getVectorElementType();
13956 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13957 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
13958 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
13959 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
13960 }
13962 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
13963 const X86Subtarget *Subtarget) {
13964 SDValue Op0 = Op.getOperand(0);
13965 SDValue Op1 = Op.getOperand(1);
13966 SDValue CC = Op.getOperand(2);
13967 MVT VT = Op.getSimpleValueType();
13968 SDLoc dl(Op);
13970 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
13971 Op.getValueType().getScalarType() == MVT::i1 &&
13972 "Cannot set masked compare for this operation");
13974 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13975 unsigned Opc = 0;
13976 bool Unsigned = false;
13977 bool Swap = false;
13978 unsigned SSECC;
13979 switch (SetCCOpcode) {
13980 default: llvm_unreachable("Unexpected SETCC condition");
13981 case ISD::SETNE: SSECC = 4; break;
13982 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
13983 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
13984 case ISD::SETLT: Swap = true; //fall-through
13985 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
13986 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
13987 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
13988 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
13989 case ISD::SETULE: Unsigned = true; //fall-through
13990 case ISD::SETLE: SSECC = 2; break;
13991 }
13993 if (Swap)
13994 std::swap(Op0, Op1);
13995 if (Opc)
13996 return DAG.getNode(Opc, dl, VT, Op0, Op1);
13997 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
13998 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13999 DAG.getConstant(SSECC, MVT::i8));
14000 }
14002 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
14003 /// operand \p Op1. If non-trivial (for example because it's not constant)
14004 /// return an empty value.
14005 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
14006 {
14007 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
14008 if (!BV)
14009 return SDValue();
14011 MVT VT = Op1.getSimpleValueType();
14012 MVT EVT = VT.getVectorElementType();
14013 unsigned n = VT.getVectorNumElements();
14014 SmallVector<SDValue, 8> ULTOp1;
14016 for (unsigned i = 0; i < n; ++i) {
14017 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
14018 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
14019 return SDValue();
14021 // Avoid underflow.
14022 APInt Val = Elt->getAPIntValue();
14023 if (Val == 0)
14024 return SDValue();
14026 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
14027 }
14029 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
14030 }
14032 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
14033 SelectionDAG &DAG) {
14034 SDValue Op0 = Op.getOperand(0);
14035 SDValue Op1 = Op.getOperand(1);
14036 SDValue CC = Op.getOperand(2);
14037 MVT VT = Op.getSimpleValueType();
14038 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14039 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
14040 SDLoc dl(Op);
14042 if (isFP) {
14043 #ifndef NDEBUG
14044 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
14045 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
14046 #endif
14048 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
14049 unsigned Opc = X86ISD::CMPP;
14050 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
14051 assert(VT.getVectorNumElements() <= 16);
14052 Opc = X86ISD::CMPM;
14053 }
14054 // In the two special cases we can't handle, emit two comparisons.
14055 if (SSECC == 8) {
14056 unsigned CC0, CC1;
14057 unsigned CombineOpc;
14058 if (SetCCOpcode == ISD::SETUEQ) {
14059 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
14060 } else {
14061 assert(SetCCOpcode == ISD::SETONE);
14062 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
14063 }
14065 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14066 DAG.getConstant(CC0, MVT::i8));
14067 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14068 DAG.getConstant(CC1, MVT::i8));
14069 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
14070 }
14071 // Handle all other FP comparisons here.
14072 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14073 DAG.getConstant(SSECC, MVT::i8));
14074 }
14076 // Break 256-bit integer vector compare into smaller ones.
14077 if (VT.is256BitVector() && !Subtarget->hasInt256())
14078 return Lower256IntVSETCC(Op, DAG);
14080 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
14081 EVT OpVT = Op1.getValueType();
14082 if (Subtarget->hasAVX512()) {
14083 if (Op1.getValueType().is512BitVector() ||
14084 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
14085 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
14086 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
14088 // In AVX-512 architecture setcc returns mask with i1 elements,
14089 // But there is no compare instruction for i8 and i16 elements in KNL.
14090 // We are not talking about 512-bit operands in this case, these
14091 // types are illegal.
14092 if (MaskResult &&
14093 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
14094 OpVT.getVectorElementType().getSizeInBits() >= 8))
14095 return DAG.getNode(ISD::TRUNCATE, dl, VT,
14096 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
14097 }
14099 // We are handling one of the integer comparisons here. Since SSE only has
14100 // GT and EQ comparisons for integer, swapping operands and multiple
14101 // operations may be required for some comparisons.
14102 unsigned Opc;
14103 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
14104 bool Subus = false;
14106 switch (SetCCOpcode) {
14107 default: llvm_unreachable("Unexpected SETCC condition");
14108 case ISD::SETNE: Invert = true;
14109 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
14110 case ISD::SETLT: Swap = true;
14111 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
14112 case ISD::SETGE: Swap = true;
14113 case ISD::SETLE: Opc = X86ISD::PCMPGT;
14114 Invert = true; break;
14115 case ISD::SETULT: Swap = true;
14116 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
14117 FlipSigns = true; break;
14118 case ISD::SETUGE: Swap = true;
14119 case ISD::SETULE: Opc = X86ISD::PCMPGT;
14120 FlipSigns = true; Invert = true; break;
14121 }
14123 // Special case: Use min/max operations for SETULE/SETUGE
14124 MVT VET = VT.getVectorElementType();
14125 bool hasMinMax =
14126 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
14127 || (Subtarget->hasSSE2() && (VET == MVT::i8));
14129 if (hasMinMax) {
14130 switch (SetCCOpcode) {
14131 default: break;
14132 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
14133 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
14134 }
14136 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
14137 }
14139 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
14140 if (!MinMax && hasSubus) {
14141 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
14142 // Op0 u<= Op1:
14143 // t = psubus Op0, Op1
14144 // pcmpeq t, <0..0>
14145 switch (SetCCOpcode) {
14146 default: break;
14147 case ISD::SETULT: {
14148 // If the comparison is against a constant we can turn this into a
14149 // setule. With psubus, setule does not require a swap. This is
14150 // beneficial because the constant in the register is no longer
14151 // destructed as the destination so it can be hoisted out of a loop.
14152 // Only do this pre-AVX since vpcmp* is no longer destructive.
14153 if (Subtarget->hasAVX())
14154 break;
14155 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
14156 if (ULEOp1.getNode()) {
14157 Op1 = ULEOp1;
14158 Subus = true; Invert = false; Swap = false;
14159 }
14160 break;
14161 }
14162 // Psubus is better than flip-sign because it requires no inversion.
14163 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
14164 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
14165 }
14167 if (Subus) {
14168 Opc = X86ISD::SUBUS;
14169 FlipSigns = false;
14170 }
14171 }
14173 if (Swap)
14174 std::swap(Op0, Op1);
14176 // Check that the operation in question is available (most are plain SSE2,
14177 // but PCMPGTQ and PCMPEQQ have different requirements).
14178 if (VT == MVT::v2i64) {
14179 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
14180 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
14182 // First cast everything to the right type.
14183 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
14184 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
14186 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14187 // bits of the inputs before performing those operations. The lower
14188 // compare is always unsigned.
14189 SDValue SB;
14190 if (FlipSigns) {
14191 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
14192 } else {
14193 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
14194 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
14195 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
14196 Sign, Zero, Sign, Zero);
14197 }
14198 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
14199 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
14201 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
14202 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
14203 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
14205 // Create masks for only the low parts/high parts of the 64 bit integers.
14206 static const int MaskHi[] = { 1, 1, 3, 3 };
14207 static const int MaskLo[] = { 0, 0, 2, 2 };
14208 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
14209 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
14210 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
14212 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
14213 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
14215 if (Invert)
14216 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14218 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
14219 }
14221 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
14222 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
14223 // pcmpeqd + pshufd + pand.
14224 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
14226 // First cast everything to the right type.
14227 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
14228 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
14230 // Do the compare.
14231 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
14233 // Make sure the lower and upper halves are both all-ones.
14234 static const int Mask[] = { 1, 0, 3, 2 };
14235 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
14236 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
14238 if (Invert)
14239 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14241 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
14242 }
14243 }
14245 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14246 // bits of the inputs before performing those operations.
14247 if (FlipSigns) {
14248 EVT EltVT = VT.getVectorElementType();
14249 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
14250 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
14251 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
14252 }
14254 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
14256 // If the logical-not of the result is required, perform that now.
14257 if (Invert)
14258 Result = DAG.getNOT(dl, Result, VT);
14260 if (MinMax)
14261 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
14263 if (Subus)
14264 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
14265 getZeroVector(VT, Subtarget, DAG, dl));
14267 return Result;
14268 }
14270 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
14272 MVT VT = Op.getSimpleValueType();
14274 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
14276 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
14277 && "SetCC type must be 8-bit or 1-bit integer");
14278 SDValue Op0 = Op.getOperand(0);
14279 SDValue Op1 = Op.getOperand(1);
14280 SDLoc dl(Op);
14281 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
14283 // Optimize to BT if possible.
14284 // Lower (X & (1 << N)) == 0 to BT(X, N).
14285 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
14286 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
14287 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
14288 Op1.getOpcode() == ISD::Constant &&
14289 cast<ConstantSDNode>(Op1)->isNullValue() &&
14290 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14291 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
14292 if (NewSetCC.getNode())
14293 return NewSetCC;
14294 }
14296 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
14297 // these.
14298 if (Op1.getOpcode() == ISD::Constant &&
14299 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
14300 cast<ConstantSDNode>(Op1)->isNullValue()) &&
14301 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14303 // If the input is a setcc, then reuse the input setcc or use a new one with
14304 // the inverted condition.
14305 if (Op0.getOpcode() == X86ISD::SETCC) {
14306 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
14307 bool Invert = (CC == ISD::SETNE) ^
14308 cast<ConstantSDNode>(Op1)->isNullValue();
14309 if (!Invert)
14310 return Op0;
14312 CCode = X86::GetOppositeBranchCondition(CCode);
14313 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14314 DAG.getConstant(CCode, MVT::i8),
14315 Op0.getOperand(1));
14316 if (VT == MVT::i1)
14317 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14318 return SetCC;
14319 }
14320 }
14321 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
14322 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
14323 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14325 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
14326 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
14327 }
14329 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
14330 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
14331 if (X86CC == X86::COND_INVALID)
14332 return SDValue();
14334 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
14335 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
14336 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14337 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
14338 if (VT == MVT::i1)
14339 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14340 return SetCC;
14341 }
14343 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
14344 static bool isX86LogicalCmp(SDValue Op) {
14345 unsigned Opc = Op.getNode()->getOpcode();
14346 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
14347 Opc == X86ISD::SAHF)
14348 return true;
14349 if (Op.getResNo() == 1 &&
14350 (Opc == X86ISD::ADD ||
14351 Opc == X86ISD::SUB ||
14352 Opc == X86ISD::ADC ||
14353 Opc == X86ISD::SBB ||
14354 Opc == X86ISD::SMUL ||
14355 Opc == X86ISD::UMUL ||
14356 Opc == X86ISD::INC ||
14357 Opc == X86ISD::DEC ||
14358 Opc == X86ISD::OR ||
14359 Opc == X86ISD::XOR ||
14360 Opc == X86ISD::AND))
14361 return true;
14363 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
14364 return true;
14366 return false;
14367 }
14369 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
14370 if (V.getOpcode() != ISD::TRUNCATE)
14371 return false;
14373 SDValue VOp0 = V.getOperand(0);
14374 unsigned InBits = VOp0.getValueSizeInBits();
14375 unsigned Bits = V.getValueSizeInBits();
14376 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
14377 }
14379 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
14380 bool addTest = true;
14381 SDValue Cond = Op.getOperand(0);
14382 SDValue Op1 = Op.getOperand(1);
14383 SDValue Op2 = Op.getOperand(2);
14384 SDLoc DL(Op);
14385 EVT VT = Op1.getValueType();
14386 SDValue CC;
14388 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
14389 // are available. Otherwise fp cmovs get lowered into a less efficient branch
14390 // sequence later on.
14391 if (Cond.getOpcode() == ISD::SETCC &&
14392 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
14393 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
14394 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
14395 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
14396 int SSECC = translateX86FSETCC(
14397 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
14399 if (SSECC != 8) {
14400 if (Subtarget->hasAVX512()) {
14401 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
14402 DAG.getConstant(SSECC, MVT::i8));
14403 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
14404 }
14405 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
14406 DAG.getConstant(SSECC, MVT::i8));
14407 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
14408 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
14409 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
14410 }
14411 }
14413 if (Cond.getOpcode() == ISD::SETCC) {
14414 SDValue NewCond = LowerSETCC(Cond, DAG);
14415 if (NewCond.getNode())
14416 Cond = NewCond;
14417 }
14419 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
14420 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
14421 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
14422 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
14423 if (Cond.getOpcode() == X86ISD::SETCC &&
14424 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
14425 isZero(Cond.getOperand(1).getOperand(1))) {
14426 SDValue Cmp = Cond.getOperand(1);
14428 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
14430 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
14431 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
14432 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
14434 SDValue CmpOp0 = Cmp.getOperand(0);
14435 // Apply further optimizations for special cases
14436 // (select (x != 0), -1, 0) -> neg & sbb
14437 // (select (x == 0), 0, -1) -> neg & sbb
14438 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
14439 if (YC->isNullValue() &&
14440 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
14441 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
14442 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
14443 DAG.getConstant(0, CmpOp0.getValueType()),
14444 CmpOp0);
14445 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14446 DAG.getConstant(X86::COND_B, MVT::i8),
14447 SDValue(Neg.getNode(), 1));
14448 return Res;
14449 }
14451 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
14452 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
14453 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14455 SDValue Res = // Res = 0 or -1.
14456 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14457 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
14459 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
14460 Res = DAG.getNOT(DL, Res, Res.getValueType());
14462 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
14463 if (!N2C || !N2C->isNullValue())
14464 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
14465 return Res;
14466 }
14467 }
14469 // Look past (and (setcc_carry (cmp ...)), 1).
14470 if (Cond.getOpcode() == ISD::AND &&
14471 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14472 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14473 if (C && C->getAPIntValue() == 1)
14474 Cond = Cond.getOperand(0);
14475 }
14477 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14478 // setting operand in place of the X86ISD::SETCC.
14479 unsigned CondOpcode = Cond.getOpcode();
14480 if (CondOpcode == X86ISD::SETCC ||
14481 CondOpcode == X86ISD::SETCC_CARRY) {
14482 CC = Cond.getOperand(0);
14484 SDValue Cmp = Cond.getOperand(1);
14485 unsigned Opc = Cmp.getOpcode();
14486 MVT VT = Op.getSimpleValueType();
14488 bool IllegalFPCMov = false;
14489 if (VT.isFloatingPoint() && !VT.isVector() &&
14490 !isScalarFPTypeInSSEReg(VT)) // FPStack?
14491 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
14493 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
14494 Opc == X86ISD::BT) { // FIXME
14495 Cond = Cmp;
14496 addTest = false;
14497 }
14498 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14499 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14500 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14501 Cond.getOperand(0).getValueType() != MVT::i8)) {
14502 SDValue LHS = Cond.getOperand(0);
14503 SDValue RHS = Cond.getOperand(1);
14504 unsigned X86Opcode;
14505 unsigned X86Cond;
14506 SDVTList VTs;
14507 switch (CondOpcode) {
14508 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14509 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14510 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14511 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14512 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14513 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14514 default: llvm_unreachable("unexpected overflowing operator");
14515 }
14516 if (CondOpcode == ISD::UMULO)
14517 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14518 MVT::i32);
14519 else
14520 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14522 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
14524 if (CondOpcode == ISD::UMULO)
14525 Cond = X86Op.getValue(2);
14526 else
14527 Cond = X86Op.getValue(1);
14529 CC = DAG.getConstant(X86Cond, MVT::i8);
14530 addTest = false;
14531 }
14533 if (addTest) {
14534 // Look pass the truncate if the high bits are known zero.
14535 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14536 Cond = Cond.getOperand(0);
14538 // We know the result of AND is compared against zero. Try to match
14539 // it to BT.
14540 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14541 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
14542 if (NewSetCC.getNode()) {
14543 CC = NewSetCC.getOperand(0);
14544 Cond = NewSetCC.getOperand(1);
14545 addTest = false;
14546 }
14547 }
14548 }
14550 if (addTest) {
14551 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
14552 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
14553 }
14555 // a < b ? -1 : 0 -> RES = ~setcc_carry
14556 // a < b ? 0 : -1 -> RES = setcc_carry
14557 // a >= b ? -1 : 0 -> RES = setcc_carry
14558 // a >= b ? 0 : -1 -> RES = ~setcc_carry
14559 if (Cond.getOpcode() == X86ISD::SUB) {
14560 Cond = ConvertCmpIfNecessary(Cond, DAG);
14561 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
14563 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
14564 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
14565 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14566 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
14567 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
14568 return DAG.getNOT(DL, Res, Res.getValueType());
14569 return Res;
14570 }
14571 }
14573 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
14574 // widen the cmov and push the truncate through. This avoids introducing a new
14575 // branch during isel and doesn't add any extensions.
14576 if (Op.getValueType() == MVT::i8 &&
14577 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
14578 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
14579 if (T1.getValueType() == T2.getValueType() &&
14580 // Blacklist CopyFromReg to avoid partial register stalls.
14581 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
14582 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
14583 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
14584 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
14585 }
14586 }
14588 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
14589 // condition is true.
14590 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
14591 SDValue Ops[] = { Op2, Op1, CC, Cond };
14592 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
14593 }
14595 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
14596 MVT VT = Op->getSimpleValueType(0);
14597 SDValue In = Op->getOperand(0);
14598 MVT InVT = In.getSimpleValueType();
14599 SDLoc dl(Op);
14601 unsigned int NumElts = VT.getVectorNumElements();
14602 if (NumElts != 8 && NumElts != 16)
14603 return SDValue();
14605 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
14606 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14608 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14609 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14611 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
14612 Constant *C = ConstantInt::get(*DAG.getContext(),
14613 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
14615 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
14616 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14617 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
14618 MachinePointerInfo::getConstantPool(),
14619 false, false, false, Alignment);
14620 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
14621 if (VT.is512BitVector())
14622 return Brcst;
14623 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
14624 }
14626 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14627 SelectionDAG &DAG) {
14628 MVT VT = Op->getSimpleValueType(0);
14629 SDValue In = Op->getOperand(0);
14630 MVT InVT = In.getSimpleValueType();
14631 SDLoc dl(Op);
14633 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
14634 return LowerSIGN_EXTEND_AVX512(Op, DAG);
14636 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
14637 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
14638 (VT != MVT::v16i16 || InVT != MVT::v16i8))
14639 return SDValue();
14641 if (Subtarget->hasInt256())
14642 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14644 // Optimize vectors in AVX mode
14645 // Sign extend v8i16 to v8i32 and
14646 // v4i32 to v4i64
14647 //
14648 // Divide input vector into two parts
14649 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14650 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14651 // concat the vectors to original VT
14653 unsigned NumElems = InVT.getVectorNumElements();
14654 SDValue Undef = DAG.getUNDEF(InVT);
14656 SmallVector<int,8> ShufMask1(NumElems, -1);
14657 for (unsigned i = 0; i != NumElems/2; ++i)
14658 ShufMask1[i] = i;
14660 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
14662 SmallVector<int,8> ShufMask2(NumElems, -1);
14663 for (unsigned i = 0; i != NumElems/2; ++i)
14664 ShufMask2[i] = i + NumElems/2;
14666 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
14668 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
14669 VT.getVectorNumElements()/2);
14671 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
14672 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
14674 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14675 }
14677 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
14678 // may emit an illegal shuffle but the expansion is still better than scalar
14679 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
14680 // we'll emit a shuffle and a arithmetic shift.
14681 // TODO: It is possible to support ZExt by zeroing the undef values during
14682 // the shuffle phase or after the shuffle.
14683 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
14684 SelectionDAG &DAG) {
14685 MVT RegVT = Op.getSimpleValueType();
14686 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
14687 assert(RegVT.isInteger() &&
14688 "We only custom lower integer vector sext loads.");
14690 // Nothing useful we can do without SSE2 shuffles.
14691 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
14693 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
14694 SDLoc dl(Ld);
14695 EVT MemVT = Ld->getMemoryVT();
14696 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14697 unsigned RegSz = RegVT.getSizeInBits();
14699 ISD::LoadExtType Ext = Ld->getExtensionType();
14701 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
14702 && "Only anyext and sext are currently implemented.");
14703 assert(MemVT != RegVT && "Cannot extend to the same type");
14704 assert(MemVT.isVector() && "Must load a vector from memory");
14706 unsigned NumElems = RegVT.getVectorNumElements();
14707 unsigned MemSz = MemVT.getSizeInBits();
14708 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14710 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
14711 // The only way in which we have a legal 256-bit vector result but not the
14712 // integer 256-bit operations needed to directly lower a sextload is if we
14713 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
14714 // a 128-bit vector and a normal sign_extend to 256-bits that should get
14715 // correctly legalized. We do this late to allow the canonical form of
14716 // sextload to persist throughout the rest of the DAG combiner -- it wants
14717 // to fold together any extensions it can, and so will fuse a sign_extend
14718 // of an sextload into a sextload targeting a wider value.
14719 SDValue Load;
14720 if (MemSz == 128) {
14721 // Just switch this to a normal load.
14722 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
14723 "it must be a legal 128-bit vector "
14724 "type!");
14725 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
14726 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
14727 Ld->isInvariant(), Ld->getAlignment());
14728 } else {
14729 assert(MemSz < 128 &&
14730 "Can't extend a type wider than 128 bits to a 256 bit vector!");
14731 // Do an sext load to a 128-bit vector type. We want to use the same
14732 // number of elements, but elements half as wide. This will end up being
14733 // recursively lowered by this routine, but will succeed as we definitely
14734 // have all the necessary features if we're using AVX1.
14735 EVT HalfEltVT =
14736 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
14737 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
14738 Load =
14739 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
14740 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
14741 Ld->isNonTemporal(), Ld->isInvariant(),
14742 Ld->getAlignment());
14743 }
14745 // Replace chain users with the new chain.
14746 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
14747 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
14749 // Finally, do a normal sign-extend to the desired register.
14750 return DAG.getSExtOrTrunc(Load, dl, RegVT);
14751 }
14753 // All sizes must be a power of two.
14754 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
14755 "Non-power-of-two elements are not custom lowered!");
14757 // Attempt to load the original value using scalar loads.
14758 // Find the largest scalar type that divides the total loaded size.
14759 MVT SclrLoadTy = MVT::i8;
14760 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14761 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14762 MVT Tp = (MVT::SimpleValueType)tp;
14763 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
14764 SclrLoadTy = Tp;
14765 }
14766 }
14768 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
14769 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
14770 (64 <= MemSz))
14771 SclrLoadTy = MVT::f64;
14773 // Calculate the number of scalar loads that we need to perform
14774 // in order to load our vector from memory.
14775 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
14777 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
14778 "Can only lower sext loads with a single scalar load!");
14780 unsigned loadRegZize = RegSz;
14781 if (Ext == ISD::SEXTLOAD && RegSz == 256)
14782 loadRegZize /= 2;
14784 // Represent our vector as a sequence of elements which are the
14785 // largest scalar that we can load.
14786 EVT LoadUnitVecVT = EVT::getVectorVT(
14787 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
14789 // Represent the data using the same element type that is stored in
14790 // memory. In practice, we ''widen'' MemVT.
14791 EVT WideVecVT =
14792 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14793 loadRegZize / MemVT.getScalarType().getSizeInBits());
14795 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
14796 "Invalid vector type");
14798 // We can't shuffle using an illegal type.
14799 assert(TLI.isTypeLegal(WideVecVT) &&
14800 "We only lower types that form legal widened vector types");
14802 SmallVector<SDValue, 8> Chains;
14803 SDValue Ptr = Ld->getBasePtr();
14804 SDValue Increment =
14805 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
14806 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
14808 for (unsigned i = 0; i < NumLoads; ++i) {
14809 // Perform a single load.
14810 SDValue ScalarLoad =
14811 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
14812 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
14813 Ld->getAlignment());
14814 Chains.push_back(ScalarLoad.getValue(1));
14815 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
14816 // another round of DAGCombining.
14817 if (i == 0)
14818 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
14819 else
14820 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
14821 ScalarLoad, DAG.getIntPtrConstant(i));
14823 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14824 }
14826 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
14828 // Bitcast the loaded value to a vector of the original element type, in
14829 // the size of the target vector type.
14830 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
14831 unsigned SizeRatio = RegSz / MemSz;
14833 if (Ext == ISD::SEXTLOAD) {
14834 // If we have SSE4.1, we can directly emit a VSEXT node.
14835 if (Subtarget->hasSSE41()) {
14836 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
14837 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14838 return Sext;
14839 }
14841 // Otherwise we'll shuffle the small elements in the high bits of the
14842 // larger type and perform an arithmetic shift. If the shift is not legal
14843 // it's better to scalarize.
14844 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
14845 "We can't implement a sext load without an arithmetic right shift!");
14847 // Redistribute the loaded elements into the different locations.
14848 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14849 for (unsigned i = 0; i != NumElems; ++i)
14850 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
14852 SDValue Shuff = DAG.getVectorShuffle(
14853 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14855 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14857 // Build the arithmetic shift.
14858 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
14859 MemVT.getVectorElementType().getSizeInBits();
14860 Shuff =
14861 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
14863 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14864 return Shuff;
14865 }
14867 // Redistribute the loaded elements into the different locations.
14868 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14869 for (unsigned i = 0; i != NumElems; ++i)
14870 ShuffleVec[i * SizeRatio] = i;
14872 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14873 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14875 // Bitcast to the requested type.
14876 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14877 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14878 return Shuff;
14879 }
14881 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
14882 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
14883 // from the AND / OR.
14884 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
14885 Opc = Op.getOpcode();
14886 if (Opc != ISD::OR && Opc != ISD::AND)
14887 return false;
14888 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14889 Op.getOperand(0).hasOneUse() &&
14890 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
14891 Op.getOperand(1).hasOneUse());
14892 }
14894 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
14895 // 1 and that the SETCC node has a single use.
14896 static bool isXor1OfSetCC(SDValue Op) {
14897 if (Op.getOpcode() != ISD::XOR)
14898 return false;
14899 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
14900 if (N1C && N1C->getAPIntValue() == 1) {
14901 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14902 Op.getOperand(0).hasOneUse();
14903 }
14904 return false;
14905 }
14907 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
14908 bool addTest = true;
14909 SDValue Chain = Op.getOperand(0);
14910 SDValue Cond = Op.getOperand(1);
14911 SDValue Dest = Op.getOperand(2);
14912 SDLoc dl(Op);
14913 SDValue CC;
14914 bool Inverted = false;
14916 if (Cond.getOpcode() == ISD::SETCC) {
14917 // Check for setcc([su]{add,sub,mul}o == 0).
14918 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
14919 isa<ConstantSDNode>(Cond.getOperand(1)) &&
14920 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
14921 Cond.getOperand(0).getResNo() == 1 &&
14922 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
14923 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
14924 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
14925 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
14926 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
14927 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
14928 Inverted = true;
14929 Cond = Cond.getOperand(0);
14930 } else {
14931 SDValue NewCond = LowerSETCC(Cond, DAG);
14932 if (NewCond.getNode())
14933 Cond = NewCond;
14934 }
14935 }
14936 #if 0
14937 // FIXME: LowerXALUO doesn't handle these!!
14938 else if (Cond.getOpcode() == X86ISD::ADD ||
14939 Cond.getOpcode() == X86ISD::SUB ||
14940 Cond.getOpcode() == X86ISD::SMUL ||
14941 Cond.getOpcode() == X86ISD::UMUL)
14942 Cond = LowerXALUO(Cond, DAG);
14943 #endif
14945 // Look pass (and (setcc_carry (cmp ...)), 1).
14946 if (Cond.getOpcode() == ISD::AND &&
14947 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14948 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14949 if (C && C->getAPIntValue() == 1)
14950 Cond = Cond.getOperand(0);
14951 }
14953 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14954 // setting operand in place of the X86ISD::SETCC.
14955 unsigned CondOpcode = Cond.getOpcode();
14956 if (CondOpcode == X86ISD::SETCC ||
14957 CondOpcode == X86ISD::SETCC_CARRY) {
14958 CC = Cond.getOperand(0);
14960 SDValue Cmp = Cond.getOperand(1);
14961 unsigned Opc = Cmp.getOpcode();
14962 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
14963 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
14964 Cond = Cmp;
14965 addTest = false;
14966 } else {
14967 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
14968 default: break;
14969 case X86::COND_O:
14970 case X86::COND_B:
14971 // These can only come from an arithmetic instruction with overflow,
14972 // e.g. SADDO, UADDO.
14973 Cond = Cond.getNode()->getOperand(1);
14974 addTest = false;
14975 break;
14976 }
14977 }
14978 }
14979 CondOpcode = Cond.getOpcode();
14980 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14981 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14982 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14983 Cond.getOperand(0).getValueType() != MVT::i8)) {
14984 SDValue LHS = Cond.getOperand(0);
14985 SDValue RHS = Cond.getOperand(1);
14986 unsigned X86Opcode;
14987 unsigned X86Cond;
14988 SDVTList VTs;
14989 // Keep this in sync with LowerXALUO, otherwise we might create redundant
14990 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
14991 // X86ISD::INC).
14992 switch (CondOpcode) {
14993 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14994 case ISD::SADDO:
14995 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14996 if (C->isOne()) {
14997 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
14998 break;
14999 }
15000 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15001 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15002 case ISD::SSUBO:
15003 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15004 if (C->isOne()) {
15005 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
15006 break;
15007 }
15008 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15009 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15010 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15011 default: llvm_unreachable("unexpected overflowing operator");
15012 }
15013 if (Inverted)
15014 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
15015 if (CondOpcode == ISD::UMULO)
15016 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15017 MVT::i32);
15018 else
15019 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15021 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
15023 if (CondOpcode == ISD::UMULO)
15024 Cond = X86Op.getValue(2);
15025 else
15026 Cond = X86Op.getValue(1);
15028 CC = DAG.getConstant(X86Cond, MVT::i8);
15029 addTest = false;
15030 } else {
15031 unsigned CondOpc;
15032 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
15033 SDValue Cmp = Cond.getOperand(0).getOperand(1);
15034 if (CondOpc == ISD::OR) {
15035 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
15036 // two branches instead of an explicit OR instruction with a
15037 // separate test.
15038 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15039 isX86LogicalCmp(Cmp)) {
15040 CC = Cond.getOperand(0).getOperand(0);
15041 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15042 Chain, Dest, CC, Cmp);
15043 CC = Cond.getOperand(1).getOperand(0);
15044 Cond = Cmp;
15045 addTest = false;
15046 }
15047 } else { // ISD::AND
15048 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
15049 // two branches instead of an explicit AND instruction with a
15050 // separate test. However, we only do this if this block doesn't
15051 // have a fall-through edge, because this requires an explicit
15052 // jmp when the condition is false.
15053 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15054 isX86LogicalCmp(Cmp) &&
15055 Op.getNode()->hasOneUse()) {
15056 X86::CondCode CCode =
15057 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15058 CCode = X86::GetOppositeBranchCondition(CCode);
15059 CC = DAG.getConstant(CCode, MVT::i8);
15060 SDNode *User = *Op.getNode()->use_begin();
15061 // Look for an unconditional branch following this conditional branch.
15062 // We need this because we need to reverse the successors in order
15063 // to implement FCMP_OEQ.
15064 if (User->getOpcode() == ISD::BR) {
15065 SDValue FalseBB = User->getOperand(1);
15066 SDNode *NewBR =
15067 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15068 assert(NewBR == User);
15069 (void)NewBR;
15070 Dest = FalseBB;
15072 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15073 Chain, Dest, CC, Cmp);
15074 X86::CondCode CCode =
15075 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
15076 CCode = X86::GetOppositeBranchCondition(CCode);
15077 CC = DAG.getConstant(CCode, MVT::i8);
15078 Cond = Cmp;
15079 addTest = false;
15080 }
15081 }
15082 }
15083 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
15084 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
15085 // It should be transformed during dag combiner except when the condition
15086 // is set by a arithmetics with overflow node.
15087 X86::CondCode CCode =
15088 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15089 CCode = X86::GetOppositeBranchCondition(CCode);
15090 CC = DAG.getConstant(CCode, MVT::i8);
15091 Cond = Cond.getOperand(0).getOperand(1);
15092 addTest = false;
15093 } else if (Cond.getOpcode() == ISD::SETCC &&
15094 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
15095 // For FCMP_OEQ, we can emit
15096 // two branches instead of an explicit AND instruction with a
15097 // separate test. However, we only do this if this block doesn't
15098 // have a fall-through edge, because this requires an explicit
15099 // jmp when the condition is false.
15100 if (Op.getNode()->hasOneUse()) {
15101 SDNode *User = *Op.getNode()->use_begin();
15102 // Look for an unconditional branch following this conditional branch.
15103 // We need this because we need to reverse the successors in order
15104 // to implement FCMP_OEQ.
15105 if (User->getOpcode() == ISD::BR) {
15106 SDValue FalseBB = User->getOperand(1);
15107 SDNode *NewBR =
15108 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15109 assert(NewBR == User);
15110 (void)NewBR;
15111 Dest = FalseBB;
15113 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15114 Cond.getOperand(0), Cond.getOperand(1));
15115 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15116 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15117 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15118 Chain, Dest, CC, Cmp);
15119 CC = DAG.getConstant(X86::COND_P, MVT::i8);
15120 Cond = Cmp;
15121 addTest = false;
15122 }
15123 }
15124 } else if (Cond.getOpcode() == ISD::SETCC &&
15125 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
15126 // For FCMP_UNE, we can emit
15127 // two branches instead of an explicit AND instruction with a
15128 // separate test. However, we only do this if this block doesn't
15129 // have a fall-through edge, because this requires an explicit
15130 // jmp when the condition is false.
15131 if (Op.getNode()->hasOneUse()) {
15132 SDNode *User = *Op.getNode()->use_begin();
15133 // Look for an unconditional branch following this conditional branch.
15134 // We need this because we need to reverse the successors in order
15135 // to implement FCMP_UNE.
15136 if (User->getOpcode() == ISD::BR) {
15137 SDValue FalseBB = User->getOperand(1);
15138 SDNode *NewBR =
15139 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15140 assert(NewBR == User);
15141 (void)NewBR;
15143 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15144 Cond.getOperand(0), Cond.getOperand(1));
15145 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15146 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15147 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15148 Chain, Dest, CC, Cmp);
15149 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
15150 Cond = Cmp;
15151 addTest = false;
15152 Dest = FalseBB;
15153 }
15154 }
15155 }
15156 }
15158 if (addTest) {
15159 // Look pass the truncate if the high bits are known zero.
15160 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15161 Cond = Cond.getOperand(0);
15163 // We know the result of AND is compared against zero. Try to match
15164 // it to BT.
15165 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15166 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
15167 if (NewSetCC.getNode()) {
15168 CC = NewSetCC.getOperand(0);
15169 Cond = NewSetCC.getOperand(1);
15170 addTest = false;
15171 }
15172 }
15173 }
15175 if (addTest) {
15176 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
15177 CC = DAG.getConstant(X86Cond, MVT::i8);
15178 Cond = EmitTest(Cond, X86Cond, dl, DAG);
15179 }
15180 Cond = ConvertCmpIfNecessary(Cond, DAG);
15181 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15182 Chain, Dest, CC, Cond);
15183 }
15185 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
15186 // Calls to _alloca are needed to probe the stack when allocating more than 4k
15187 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
15188 // that the guard pages used by the OS virtual memory manager are allocated in
15189 // correct sequence.
15190 SDValue
15191 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
15192 SelectionDAG &DAG) const {
15193 MachineFunction &MF = DAG.getMachineFunction();
15194 bool SplitStack = MF.shouldSplitStack();
15195 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
15196 SplitStack;
15197 SDLoc dl(Op);
15199 if (!Lower) {
15200 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15201 SDNode* Node = Op.getNode();
15203 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
15204 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
15205 " not tell us which reg is the stack pointer!");
15206 EVT VT = Node->getValueType(0);
15207 SDValue Tmp1 = SDValue(Node, 0);
15208 SDValue Tmp2 = SDValue(Node, 1);
15209 SDValue Tmp3 = Node->getOperand(2);
15210 SDValue Chain = Tmp1.getOperand(0);
15212 // Chain the dynamic stack allocation so that it doesn't modify the stack
15213 // pointer when other instructions are using the stack.
15214 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
15215 SDLoc(Node));
15217 SDValue Size = Tmp2.getOperand(1);
15218 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
15219 Chain = SP.getValue(1);
15220 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
15221 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
15222 unsigned StackAlign = TFI.getStackAlignment();
15223 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
15224 if (Align > StackAlign)
15225 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
15226 DAG.getConstant(-(uint64_t)Align, VT));
15227 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
15229 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
15230 DAG.getIntPtrConstant(0, true), SDValue(),
15231 SDLoc(Node));
15233 SDValue Ops[2] = { Tmp1, Tmp2 };
15234 return DAG.getMergeValues(Ops, dl);
15235 }
15237 // Get the inputs.
15238 SDValue Chain = Op.getOperand(0);
15239 SDValue Size = Op.getOperand(1);
15240 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
15241 EVT VT = Op.getNode()->getValueType(0);
15243 bool Is64Bit = Subtarget->is64Bit();
15244 EVT SPTy = getPointerTy();
15246 if (SplitStack) {
15247 MachineRegisterInfo &MRI = MF.getRegInfo();
15249 if (Is64Bit) {
15250 // The 64 bit implementation of segmented stacks needs to clobber both r10
15251 // r11. This makes it impossible to use it along with nested parameters.
15252 const Function *F = MF.getFunction();
15254 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
15255 I != E; ++I)
15256 if (I->hasNestAttr())
15257 report_fatal_error("Cannot use segmented stacks with functions that "
15258 "have nested arguments.");
15259 }
15261 const TargetRegisterClass *AddrRegClass =
15262 getRegClassFor(getPointerTy());
15263 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
15264 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
15265 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
15266 DAG.getRegister(Vreg, SPTy));
15267 SDValue Ops1[2] = { Value, Chain };
15268 return DAG.getMergeValues(Ops1, dl);
15269 } else {
15270 SDValue Flag;
15271 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
15273 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
15274 Flag = Chain.getValue(1);
15275 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
15277 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
15279 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15280 DAG.getSubtarget().getRegisterInfo());
15281 unsigned SPReg = RegInfo->getStackRegister();
15282 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
15283 Chain = SP.getValue(1);
15285 if (Align) {
15286 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
15287 DAG.getConstant(-(uint64_t)Align, VT));
15288 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
15289 }
15291 SDValue Ops1[2] = { SP, Chain };
15292 return DAG.getMergeValues(Ops1, dl);
15293 }
15294 }
15296 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
15297 MachineFunction &MF = DAG.getMachineFunction();
15298 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15300 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15301 SDLoc DL(Op);
15303 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
15304 // vastart just stores the address of the VarArgsFrameIndex slot into the
15305 // memory location argument.
15306 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
15307 getPointerTy());
15308 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
15309 MachinePointerInfo(SV), false, false, 0);
15310 }
15312 // __va_list_tag:
15313 // gp_offset (0 - 6 * 8)
15314 // fp_offset (48 - 48 + 8 * 16)
15315 // overflow_arg_area (point to parameters coming in memory).
15316 // reg_save_area
15317 SmallVector<SDValue, 8> MemOps;
15318 SDValue FIN = Op.getOperand(1);
15319 // Store gp_offset
15320 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
15321 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
15322 MVT::i32),
15323 FIN, MachinePointerInfo(SV), false, false, 0);
15324 MemOps.push_back(Store);
15326 // Store fp_offset
15327 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15328 FIN, DAG.getIntPtrConstant(4));
15329 Store = DAG.getStore(Op.getOperand(0), DL,
15330 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
15331 MVT::i32),
15332 FIN, MachinePointerInfo(SV, 4), false, false, 0);
15333 MemOps.push_back(Store);
15335 // Store ptr to overflow_arg_area
15336 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15337 FIN, DAG.getIntPtrConstant(4));
15338 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
15339 getPointerTy());
15340 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
15341 MachinePointerInfo(SV, 8),
15342 false, false, 0);
15343 MemOps.push_back(Store);
15345 // Store ptr to reg_save_area.
15346 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15347 FIN, DAG.getIntPtrConstant(8));
15348 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
15349 getPointerTy());
15350 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
15351 MachinePointerInfo(SV, 16), false, false, 0);
15352 MemOps.push_back(Store);
15353 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
15354 }
15356 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
15357 assert(Subtarget->is64Bit() &&
15358 "LowerVAARG only handles 64-bit va_arg!");
15359 assert((Subtarget->isTargetLinux() ||
15360 Subtarget->isTargetDarwin()) &&
15361 "Unhandled target in LowerVAARG");
15362 assert(Op.getNode()->getNumOperands() == 4);
15363 SDValue Chain = Op.getOperand(0);
15364 SDValue SrcPtr = Op.getOperand(1);
15365 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15366 unsigned Align = Op.getConstantOperandVal(3);
15367 SDLoc dl(Op);
15369 EVT ArgVT = Op.getNode()->getValueType(0);
15370 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15371 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
15372 uint8_t ArgMode;
15374 // Decide which area this value should be read from.
15375 // TODO: Implement the AMD64 ABI in its entirety. This simple
15376 // selection mechanism works only for the basic types.
15377 if (ArgVT == MVT::f80) {
15378 llvm_unreachable("va_arg for f80 not yet implemented");
15379 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
15380 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
15381 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
15382 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
15383 } else {
15384 llvm_unreachable("Unhandled argument type in LowerVAARG");
15385 }
15387 if (ArgMode == 2) {
15388 // Sanity Check: Make sure using fp_offset makes sense.
15389 assert(!DAG.getTarget().Options.UseSoftFloat &&
15390 !(DAG.getMachineFunction()
15391 .getFunction()->getAttributes()
15392 .hasAttribute(AttributeSet::FunctionIndex,
15393 Attribute::NoImplicitFloat)) &&
15394 Subtarget->hasSSE1());
15395 }
15397 // Insert VAARG_64 node into the DAG
15398 // VAARG_64 returns two values: Variable Argument Address, Chain
15399 SmallVector<SDValue, 11> InstOps;
15400 InstOps.push_back(Chain);
15401 InstOps.push_back(SrcPtr);
15402 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
15403 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
15404 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
15405 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
15406 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
15407 VTs, InstOps, MVT::i64,
15408 MachinePointerInfo(SV),
15409 /*Align=*/0,
15410 /*Volatile=*/false,
15411 /*ReadMem=*/true,
15412 /*WriteMem=*/true);
15413 Chain = VAARG.getValue(1);
15415 // Load the next argument and return it
15416 return DAG.getLoad(ArgVT, dl,
15417 Chain,
15418 VAARG,
15419 MachinePointerInfo(),
15420 false, false, false, 0);
15421 }
15423 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
15424 SelectionDAG &DAG) {
15425 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
15426 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
15427 SDValue Chain = Op.getOperand(0);
15428 SDValue DstPtr = Op.getOperand(1);
15429 SDValue SrcPtr = Op.getOperand(2);
15430 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
15431 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15432 SDLoc DL(Op);
15434 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
15435 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
15436 false,
15437 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
15438 }
15440 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
15441 // amount is a constant. Takes immediate version of shift as input.
15442 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
15443 SDValue SrcOp, uint64_t ShiftAmt,
15444 SelectionDAG &DAG) {
15445 MVT ElementType = VT.getVectorElementType();
15447 // Fold this packed shift into its first operand if ShiftAmt is 0.
15448 if (ShiftAmt == 0)
15449 return SrcOp;
15451 // Check for ShiftAmt >= element width
15452 if (ShiftAmt >= ElementType.getSizeInBits()) {
15453 if (Opc == X86ISD::VSRAI)
15454 ShiftAmt = ElementType.getSizeInBits() - 1;
15455 else
15456 return DAG.getConstant(0, VT);
15457 }
15459 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
15460 && "Unknown target vector shift-by-constant node");
15462 // Fold this packed vector shift into a build vector if SrcOp is a
15463 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
15464 if (VT == SrcOp.getSimpleValueType() &&
15465 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
15466 SmallVector<SDValue, 8> Elts;
15467 unsigned NumElts = SrcOp->getNumOperands();
15468 ConstantSDNode *ND;
15470 switch(Opc) {
15471 default: llvm_unreachable(nullptr);
15472 case X86ISD::VSHLI:
15473 for (unsigned i=0; i!=NumElts; ++i) {
15474 SDValue CurrentOp = SrcOp->getOperand(i);
15475 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15476 Elts.push_back(CurrentOp);
15477 continue;
15478 }
15479 ND = cast<ConstantSDNode>(CurrentOp);
15480 const APInt &C = ND->getAPIntValue();
15481 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
15482 }
15483 break;
15484 case X86ISD::VSRLI:
15485 for (unsigned i=0; i!=NumElts; ++i) {
15486 SDValue CurrentOp = SrcOp->getOperand(i);
15487 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15488 Elts.push_back(CurrentOp);
15489 continue;
15490 }
15491 ND = cast<ConstantSDNode>(CurrentOp);
15492 const APInt &C = ND->getAPIntValue();
15493 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
15494 }
15495 break;
15496 case X86ISD::VSRAI:
15497 for (unsigned i=0; i!=NumElts; ++i) {
15498 SDValue CurrentOp = SrcOp->getOperand(i);
15499 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15500 Elts.push_back(CurrentOp);
15501 continue;
15502 }
15503 ND = cast<ConstantSDNode>(CurrentOp);
15504 const APInt &C = ND->getAPIntValue();
15505 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
15506 }
15507 break;
15508 }
15510 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15511 }
15513 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
15514 }
15516 // getTargetVShiftNode - Handle vector element shifts where the shift amount
15517 // may or may not be a constant. Takes immediate version of shift as input.
15518 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
15519 SDValue SrcOp, SDValue ShAmt,
15520 SelectionDAG &DAG) {
15521 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
15523 // Catch shift-by-constant.
15524 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
15525 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
15526 CShAmt->getZExtValue(), DAG);
15528 // Change opcode to non-immediate version
15529 switch (Opc) {
15530 default: llvm_unreachable("Unknown target vector shift node");
15531 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
15532 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
15533 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
15534 }
15536 // Need to build a vector containing shift amount
15537 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
15538 SDValue ShOps[4];
15539 ShOps[0] = ShAmt;
15540 ShOps[1] = DAG.getConstant(0, MVT::i32);
15541 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
15542 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
15544 // The return type has to be a 128-bit type with the same element
15545 // type as the input type.
15546 MVT EltVT = VT.getVectorElementType();
15547 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
15549 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
15550 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
15551 }
15553 /// \brief Return (vselect \p Mask, \p Op, \p PreservedSrc) along with the
15554 /// necessary casting for \p Mask when lowering masking intrinsics.
15555 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
15556 SDValue PreservedSrc, SelectionDAG &DAG) {
15557 EVT VT = Op.getValueType();
15558 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
15559 MVT::i1, VT.getVectorNumElements());
15560 SDLoc dl(Op);
15562 assert(MaskVT.isSimple() && "invalid mask type");
15563 return DAG.getNode(ISD::VSELECT, dl, VT,
15564 DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask),
15565 Op, PreservedSrc);
15566 }
15568 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
15569 switch (IntNo) {
15570 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15571 case Intrinsic::x86_fma_vfmadd_ps:
15572 case Intrinsic::x86_fma_vfmadd_pd:
15573 case Intrinsic::x86_fma_vfmadd_ps_256:
15574 case Intrinsic::x86_fma_vfmadd_pd_256:
15575 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
15576 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
15577 return X86ISD::FMADD;
15578 case Intrinsic::x86_fma_vfmsub_ps:
15579 case Intrinsic::x86_fma_vfmsub_pd:
15580 case Intrinsic::x86_fma_vfmsub_ps_256:
15581 case Intrinsic::x86_fma_vfmsub_pd_256:
15582 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
15583 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
15584 return X86ISD::FMSUB;
15585 case Intrinsic::x86_fma_vfnmadd_ps:
15586 case Intrinsic::x86_fma_vfnmadd_pd:
15587 case Intrinsic::x86_fma_vfnmadd_ps_256:
15588 case Intrinsic::x86_fma_vfnmadd_pd_256:
15589 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
15590 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
15591 return X86ISD::FNMADD;
15592 case Intrinsic::x86_fma_vfnmsub_ps:
15593 case Intrinsic::x86_fma_vfnmsub_pd:
15594 case Intrinsic::x86_fma_vfnmsub_ps_256:
15595 case Intrinsic::x86_fma_vfnmsub_pd_256:
15596 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
15597 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
15598 return X86ISD::FNMSUB;
15599 case Intrinsic::x86_fma_vfmaddsub_ps:
15600 case Intrinsic::x86_fma_vfmaddsub_pd:
15601 case Intrinsic::x86_fma_vfmaddsub_ps_256:
15602 case Intrinsic::x86_fma_vfmaddsub_pd_256:
15603 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
15604 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
15605 return X86ISD::FMADDSUB;
15606 case Intrinsic::x86_fma_vfmsubadd_ps:
15607 case Intrinsic::x86_fma_vfmsubadd_pd:
15608 case Intrinsic::x86_fma_vfmsubadd_ps_256:
15609 case Intrinsic::x86_fma_vfmsubadd_pd_256:
15610 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
15611 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
15612 return X86ISD::FMSUBADD;
15613 }
15614 }
15616 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
15617 SDLoc dl(Op);
15618 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15620 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
15621 if (IntrData) {
15622 switch(IntrData->Type) {
15623 case INTR_TYPE_1OP:
15624 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
15625 case INTR_TYPE_2OP:
15626 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15627 Op.getOperand(2));
15628 case INTR_TYPE_3OP:
15629 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15630 Op.getOperand(2), Op.getOperand(3));
15631 case COMI: { // Comparison intrinsics
15632 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
15633 SDValue LHS = Op.getOperand(1);
15634 SDValue RHS = Op.getOperand(2);
15635 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
15636 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
15637 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
15638 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15639 DAG.getConstant(X86CC, MVT::i8), Cond);
15640 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15641 }
15642 case VSHIFT:
15643 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
15644 Op.getOperand(1), Op.getOperand(2), DAG);
15645 default:
15646 break;
15647 }
15648 }
15650 switch (IntNo) {
15651 default: return SDValue(); // Don't custom lower most intrinsics.
15653 // Arithmetic intrinsics.
15654 case Intrinsic::x86_sse2_pmulu_dq:
15655 case Intrinsic::x86_avx2_pmulu_dq:
15656 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
15657 Op.getOperand(1), Op.getOperand(2));
15659 case Intrinsic::x86_sse41_pmuldq:
15660 case Intrinsic::x86_avx2_pmul_dq:
15661 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
15662 Op.getOperand(1), Op.getOperand(2));
15664 case Intrinsic::x86_sse2_pmulhu_w:
15665 case Intrinsic::x86_avx2_pmulhu_w:
15666 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
15667 Op.getOperand(1), Op.getOperand(2));
15669 case Intrinsic::x86_sse2_pmulh_w:
15670 case Intrinsic::x86_avx2_pmulh_w:
15671 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
15672 Op.getOperand(1), Op.getOperand(2));
15674 // SSE/SSE2/AVX floating point max/min intrinsics.
15675 case Intrinsic::x86_sse_max_ps:
15676 case Intrinsic::x86_sse2_max_pd:
15677 case Intrinsic::x86_avx_max_ps_256:
15678 case Intrinsic::x86_avx_max_pd_256:
15679 case Intrinsic::x86_sse_min_ps:
15680 case Intrinsic::x86_sse2_min_pd:
15681 case Intrinsic::x86_avx_min_ps_256:
15682 case Intrinsic::x86_avx_min_pd_256: {
15683 unsigned Opcode;
15684 switch (IntNo) {
15685 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15686 case Intrinsic::x86_sse_max_ps:
15687 case Intrinsic::x86_sse2_max_pd:
15688 case Intrinsic::x86_avx_max_ps_256:
15689 case Intrinsic::x86_avx_max_pd_256:
15690 Opcode = X86ISD::FMAX;
15691 break;
15692 case Intrinsic::x86_sse_min_ps:
15693 case Intrinsic::x86_sse2_min_pd:
15694 case Intrinsic::x86_avx_min_ps_256:
15695 case Intrinsic::x86_avx_min_pd_256:
15696 Opcode = X86ISD::FMIN;
15697 break;
15698 }
15699 return DAG.getNode(Opcode, dl, Op.getValueType(),
15700 Op.getOperand(1), Op.getOperand(2));
15701 }
15703 // AVX2 variable shift intrinsics
15704 case Intrinsic::x86_avx2_psllv_d:
15705 case Intrinsic::x86_avx2_psllv_q:
15706 case Intrinsic::x86_avx2_psllv_d_256:
15707 case Intrinsic::x86_avx2_psllv_q_256:
15708 case Intrinsic::x86_avx2_psrlv_d:
15709 case Intrinsic::x86_avx2_psrlv_q:
15710 case Intrinsic::x86_avx2_psrlv_d_256:
15711 case Intrinsic::x86_avx2_psrlv_q_256:
15712 case Intrinsic::x86_avx2_psrav_d:
15713 case Intrinsic::x86_avx2_psrav_d_256: {
15714 unsigned Opcode;
15715 switch (IntNo) {
15716 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15717 case Intrinsic::x86_avx2_psllv_d:
15718 case Intrinsic::x86_avx2_psllv_q:
15719 case Intrinsic::x86_avx2_psllv_d_256:
15720 case Intrinsic::x86_avx2_psllv_q_256:
15721 Opcode = ISD::SHL;
15722 break;
15723 case Intrinsic::x86_avx2_psrlv_d:
15724 case Intrinsic::x86_avx2_psrlv_q:
15725 case Intrinsic::x86_avx2_psrlv_d_256:
15726 case Intrinsic::x86_avx2_psrlv_q_256:
15727 Opcode = ISD::SRL;
15728 break;
15729 case Intrinsic::x86_avx2_psrav_d:
15730 case Intrinsic::x86_avx2_psrav_d_256:
15731 Opcode = ISD::SRA;
15732 break;
15733 }
15734 return DAG.getNode(Opcode, dl, Op.getValueType(),
15735 Op.getOperand(1), Op.getOperand(2));
15736 }
15738 case Intrinsic::x86_sse2_packssdw_128:
15739 case Intrinsic::x86_sse2_packsswb_128:
15740 case Intrinsic::x86_avx2_packssdw:
15741 case Intrinsic::x86_avx2_packsswb:
15742 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
15743 Op.getOperand(1), Op.getOperand(2));
15745 case Intrinsic::x86_sse2_packuswb_128:
15746 case Intrinsic::x86_sse41_packusdw:
15747 case Intrinsic::x86_avx2_packuswb:
15748 case Intrinsic::x86_avx2_packusdw:
15749 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
15750 Op.getOperand(1), Op.getOperand(2));
15752 case Intrinsic::x86_ssse3_pshuf_b_128:
15753 case Intrinsic::x86_avx2_pshuf_b:
15754 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
15755 Op.getOperand(1), Op.getOperand(2));
15757 case Intrinsic::x86_sse2_pshuf_d:
15758 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
15759 Op.getOperand(1), Op.getOperand(2));
15761 case Intrinsic::x86_sse2_pshufl_w:
15762 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
15763 Op.getOperand(1), Op.getOperand(2));
15765 case Intrinsic::x86_sse2_pshufh_w:
15766 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
15767 Op.getOperand(1), Op.getOperand(2));
15769 case Intrinsic::x86_ssse3_psign_b_128:
15770 case Intrinsic::x86_ssse3_psign_w_128:
15771 case Intrinsic::x86_ssse3_psign_d_128:
15772 case Intrinsic::x86_avx2_psign_b:
15773 case Intrinsic::x86_avx2_psign_w:
15774 case Intrinsic::x86_avx2_psign_d:
15775 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
15776 Op.getOperand(1), Op.getOperand(2));
15778 case Intrinsic::x86_avx2_permd:
15779 case Intrinsic::x86_avx2_permps:
15780 // Operands intentionally swapped. Mask is last operand to intrinsic,
15781 // but second operand for node/instruction.
15782 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
15783 Op.getOperand(2), Op.getOperand(1));
15785 case Intrinsic::x86_avx512_mask_valign_q_512:
15786 case Intrinsic::x86_avx512_mask_valign_d_512:
15787 // Vector source operands are swapped.
15788 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
15789 Op.getValueType(), Op.getOperand(2),
15790 Op.getOperand(1),
15791 Op.getOperand(3)),
15792 Op.getOperand(5), Op.getOperand(4), DAG);
15794 // ptest and testp intrinsics. The intrinsic these come from are designed to
15795 // return an integer value, not just an instruction so lower it to the ptest
15796 // or testp pattern and a setcc for the result.
15797 case Intrinsic::x86_sse41_ptestz:
15798 case Intrinsic::x86_sse41_ptestc:
15799 case Intrinsic::x86_sse41_ptestnzc:
15800 case Intrinsic::x86_avx_ptestz_256:
15801 case Intrinsic::x86_avx_ptestc_256:
15802 case Intrinsic::x86_avx_ptestnzc_256:
15803 case Intrinsic::x86_avx_vtestz_ps:
15804 case Intrinsic::x86_avx_vtestc_ps:
15805 case Intrinsic::x86_avx_vtestnzc_ps:
15806 case Intrinsic::x86_avx_vtestz_pd:
15807 case Intrinsic::x86_avx_vtestc_pd:
15808 case Intrinsic::x86_avx_vtestnzc_pd:
15809 case Intrinsic::x86_avx_vtestz_ps_256:
15810 case Intrinsic::x86_avx_vtestc_ps_256:
15811 case Intrinsic::x86_avx_vtestnzc_ps_256:
15812 case Intrinsic::x86_avx_vtestz_pd_256:
15813 case Intrinsic::x86_avx_vtestc_pd_256:
15814 case Intrinsic::x86_avx_vtestnzc_pd_256: {
15815 bool IsTestPacked = false;
15816 unsigned X86CC;
15817 switch (IntNo) {
15818 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
15819 case Intrinsic::x86_avx_vtestz_ps:
15820 case Intrinsic::x86_avx_vtestz_pd:
15821 case Intrinsic::x86_avx_vtestz_ps_256:
15822 case Intrinsic::x86_avx_vtestz_pd_256:
15823 IsTestPacked = true; // Fallthrough
15824 case Intrinsic::x86_sse41_ptestz:
15825 case Intrinsic::x86_avx_ptestz_256:
15826 // ZF = 1
15827 X86CC = X86::COND_E;
15828 break;
15829 case Intrinsic::x86_avx_vtestc_ps:
15830 case Intrinsic::x86_avx_vtestc_pd:
15831 case Intrinsic::x86_avx_vtestc_ps_256:
15832 case Intrinsic::x86_avx_vtestc_pd_256:
15833 IsTestPacked = true; // Fallthrough
15834 case Intrinsic::x86_sse41_ptestc:
15835 case Intrinsic::x86_avx_ptestc_256:
15836 // CF = 1
15837 X86CC = X86::COND_B;
15838 break;
15839 case Intrinsic::x86_avx_vtestnzc_ps:
15840 case Intrinsic::x86_avx_vtestnzc_pd:
15841 case Intrinsic::x86_avx_vtestnzc_ps_256:
15842 case Intrinsic::x86_avx_vtestnzc_pd_256:
15843 IsTestPacked = true; // Fallthrough
15844 case Intrinsic::x86_sse41_ptestnzc:
15845 case Intrinsic::x86_avx_ptestnzc_256:
15846 // ZF and CF = 0
15847 X86CC = X86::COND_A;
15848 break;
15849 }
15851 SDValue LHS = Op.getOperand(1);
15852 SDValue RHS = Op.getOperand(2);
15853 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
15854 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
15855 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
15856 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
15857 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15858 }
15859 case Intrinsic::x86_avx512_kortestz_w:
15860 case Intrinsic::x86_avx512_kortestc_w: {
15861 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
15862 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
15863 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
15864 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
15865 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
15866 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
15867 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15868 }
15870 case Intrinsic::x86_sse42_pcmpistria128:
15871 case Intrinsic::x86_sse42_pcmpestria128:
15872 case Intrinsic::x86_sse42_pcmpistric128:
15873 case Intrinsic::x86_sse42_pcmpestric128:
15874 case Intrinsic::x86_sse42_pcmpistrio128:
15875 case Intrinsic::x86_sse42_pcmpestrio128:
15876 case Intrinsic::x86_sse42_pcmpistris128:
15877 case Intrinsic::x86_sse42_pcmpestris128:
15878 case Intrinsic::x86_sse42_pcmpistriz128:
15879 case Intrinsic::x86_sse42_pcmpestriz128: {
15880 unsigned Opcode;
15881 unsigned X86CC;
15882 switch (IntNo) {
15883 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15884 case Intrinsic::x86_sse42_pcmpistria128:
15885 Opcode = X86ISD::PCMPISTRI;
15886 X86CC = X86::COND_A;
15887 break;
15888 case Intrinsic::x86_sse42_pcmpestria128:
15889 Opcode = X86ISD::PCMPESTRI;
15890 X86CC = X86::COND_A;
15891 break;
15892 case Intrinsic::x86_sse42_pcmpistric128:
15893 Opcode = X86ISD::PCMPISTRI;
15894 X86CC = X86::COND_B;
15895 break;
15896 case Intrinsic::x86_sse42_pcmpestric128:
15897 Opcode = X86ISD::PCMPESTRI;
15898 X86CC = X86::COND_B;
15899 break;
15900 case Intrinsic::x86_sse42_pcmpistrio128:
15901 Opcode = X86ISD::PCMPISTRI;
15902 X86CC = X86::COND_O;
15903 break;
15904 case Intrinsic::x86_sse42_pcmpestrio128:
15905 Opcode = X86ISD::PCMPESTRI;
15906 X86CC = X86::COND_O;
15907 break;
15908 case Intrinsic::x86_sse42_pcmpistris128:
15909 Opcode = X86ISD::PCMPISTRI;
15910 X86CC = X86::COND_S;
15911 break;
15912 case Intrinsic::x86_sse42_pcmpestris128:
15913 Opcode = X86ISD::PCMPESTRI;
15914 X86CC = X86::COND_S;
15915 break;
15916 case Intrinsic::x86_sse42_pcmpistriz128:
15917 Opcode = X86ISD::PCMPISTRI;
15918 X86CC = X86::COND_E;
15919 break;
15920 case Intrinsic::x86_sse42_pcmpestriz128:
15921 Opcode = X86ISD::PCMPESTRI;
15922 X86CC = X86::COND_E;
15923 break;
15924 }
15925 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15926 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15927 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
15928 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15929 DAG.getConstant(X86CC, MVT::i8),
15930 SDValue(PCMP.getNode(), 1));
15931 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15932 }
15934 case Intrinsic::x86_sse42_pcmpistri128:
15935 case Intrinsic::x86_sse42_pcmpestri128: {
15936 unsigned Opcode;
15937 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
15938 Opcode = X86ISD::PCMPISTRI;
15939 else
15940 Opcode = X86ISD::PCMPESTRI;
15942 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15943 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15944 return DAG.getNode(Opcode, dl, VTs, NewOps);
15945 }
15947 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
15948 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
15949 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
15950 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
15951 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
15952 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
15953 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
15954 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
15955 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
15956 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
15957 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
15958 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
15959 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
15960 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
15961 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
15962 dl, Op.getValueType(),
15963 Op.getOperand(1),
15964 Op.getOperand(2),
15965 Op.getOperand(3)),
15966 Op.getOperand(4), Op.getOperand(1), DAG);
15967 else
15968 return SDValue();
15969 }
15971 case Intrinsic::x86_fma_vfmadd_ps:
15972 case Intrinsic::x86_fma_vfmadd_pd:
15973 case Intrinsic::x86_fma_vfmsub_ps:
15974 case Intrinsic::x86_fma_vfmsub_pd:
15975 case Intrinsic::x86_fma_vfnmadd_ps:
15976 case Intrinsic::x86_fma_vfnmadd_pd:
15977 case Intrinsic::x86_fma_vfnmsub_ps:
15978 case Intrinsic::x86_fma_vfnmsub_pd:
15979 case Intrinsic::x86_fma_vfmaddsub_ps:
15980 case Intrinsic::x86_fma_vfmaddsub_pd:
15981 case Intrinsic::x86_fma_vfmsubadd_ps:
15982 case Intrinsic::x86_fma_vfmsubadd_pd:
15983 case Intrinsic::x86_fma_vfmadd_ps_256:
15984 case Intrinsic::x86_fma_vfmadd_pd_256:
15985 case Intrinsic::x86_fma_vfmsub_ps_256:
15986 case Intrinsic::x86_fma_vfmsub_pd_256:
15987 case Intrinsic::x86_fma_vfnmadd_ps_256:
15988 case Intrinsic::x86_fma_vfnmadd_pd_256:
15989 case Intrinsic::x86_fma_vfnmsub_ps_256:
15990 case Intrinsic::x86_fma_vfnmsub_pd_256:
15991 case Intrinsic::x86_fma_vfmaddsub_ps_256:
15992 case Intrinsic::x86_fma_vfmaddsub_pd_256:
15993 case Intrinsic::x86_fma_vfmsubadd_ps_256:
15994 case Intrinsic::x86_fma_vfmsubadd_pd_256:
15995 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
15996 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
15997 }
15998 }
16000 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16001 SDValue Src, SDValue Mask, SDValue Base,
16002 SDValue Index, SDValue ScaleOp, SDValue Chain,
16003 const X86Subtarget * Subtarget) {
16004 SDLoc dl(Op);
16005 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16006 assert(C && "Invalid scale type");
16007 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16008 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16009 Index.getSimpleValueType().getVectorNumElements());
16010 SDValue MaskInReg;
16011 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16012 if (MaskC)
16013 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16014 else
16015 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16016 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
16017 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16018 SDValue Segment = DAG.getRegister(0, MVT::i32);
16019 if (Src.getOpcode() == ISD::UNDEF)
16020 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
16021 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16022 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16023 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
16024 return DAG.getMergeValues(RetOps, dl);
16025 }
16027 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16028 SDValue Src, SDValue Mask, SDValue Base,
16029 SDValue Index, SDValue ScaleOp, SDValue Chain) {
16030 SDLoc dl(Op);
16031 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16032 assert(C && "Invalid scale type");
16033 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16034 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16035 SDValue Segment = DAG.getRegister(0, MVT::i32);
16036 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16037 Index.getSimpleValueType().getVectorNumElements());
16038 SDValue MaskInReg;
16039 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16040 if (MaskC)
16041 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16042 else
16043 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16044 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
16045 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
16046 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16047 return SDValue(Res, 1);
16048 }
16050 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16051 SDValue Mask, SDValue Base, SDValue Index,
16052 SDValue ScaleOp, SDValue Chain) {
16053 SDLoc dl(Op);
16054 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16055 assert(C && "Invalid scale type");
16056 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16057 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16058 SDValue Segment = DAG.getRegister(0, MVT::i32);
16059 EVT MaskVT =
16060 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
16061 SDValue MaskInReg;
16062 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16063 if (MaskC)
16064 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16065 else
16066 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16067 //SDVTList VTs = DAG.getVTList(MVT::Other);
16068 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16069 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
16070 return SDValue(Res, 0);
16071 }
16073 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
16074 // read performance monitor counters (x86_rdpmc).
16075 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
16076 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16077 SmallVectorImpl<SDValue> &Results) {
16078 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16079 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16080 SDValue LO, HI;
16082 // The ECX register is used to select the index of the performance counter
16083 // to read.
16084 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
16085 N->getOperand(2));
16086 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
16088 // Reads the content of a 64-bit performance counter and returns it in the
16089 // registers EDX:EAX.
16090 if (Subtarget->is64Bit()) {
16091 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16092 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16093 LO.getValue(2));
16094 } else {
16095 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16096 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16097 LO.getValue(2));
16098 }
16099 Chain = HI.getValue(1);
16101 if (Subtarget->is64Bit()) {
16102 // The EAX register is loaded with the low-order 32 bits. The EDX register
16103 // is loaded with the supported high-order bits of the counter.
16104 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16105 DAG.getConstant(32, MVT::i8));
16106 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16107 Results.push_back(Chain);
16108 return;
16109 }
16111 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16112 SDValue Ops[] = { LO, HI };
16113 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16114 Results.push_back(Pair);
16115 Results.push_back(Chain);
16116 }
16118 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
16119 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
16120 // also used to custom lower READCYCLECOUNTER nodes.
16121 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
16122 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16123 SmallVectorImpl<SDValue> &Results) {
16124 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16125 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
16126 SDValue LO, HI;
16128 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
16129 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
16130 // and the EAX register is loaded with the low-order 32 bits.
16131 if (Subtarget->is64Bit()) {
16132 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16133 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16134 LO.getValue(2));
16135 } else {
16136 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16137 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16138 LO.getValue(2));
16139 }
16140 SDValue Chain = HI.getValue(1);
16142 if (Opcode == X86ISD::RDTSCP_DAG) {
16143 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16145 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
16146 // the ECX register. Add 'ecx' explicitly to the chain.
16147 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
16148 HI.getValue(2));
16149 // Explicitly store the content of ECX at the location passed in input
16150 // to the 'rdtscp' intrinsic.
16151 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
16152 MachinePointerInfo(), false, false, 0);
16153 }
16155 if (Subtarget->is64Bit()) {
16156 // The EDX register is loaded with the high-order 32 bits of the MSR, and
16157 // the EAX register is loaded with the low-order 32 bits.
16158 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16159 DAG.getConstant(32, MVT::i8));
16160 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16161 Results.push_back(Chain);
16162 return;
16163 }
16165 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16166 SDValue Ops[] = { LO, HI };
16167 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16168 Results.push_back(Pair);
16169 Results.push_back(Chain);
16170 }
16172 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
16173 SelectionDAG &DAG) {
16174 SmallVector<SDValue, 2> Results;
16175 SDLoc DL(Op);
16176 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
16177 Results);
16178 return DAG.getMergeValues(Results, DL);
16179 }
16182 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16183 SelectionDAG &DAG) {
16184 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
16186 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
16187 if (!IntrData)
16188 return SDValue();
16190 SDLoc dl(Op);
16191 switch(IntrData->Type) {
16192 default:
16193 llvm_unreachable("Unknown Intrinsic Type");
16194 break;
16195 case RDSEED:
16196 case RDRAND: {
16197 // Emit the node with the right value type.
16198 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
16199 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16201 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
16202 // Otherwise return the value from Rand, which is always 0, casted to i32.
16203 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
16204 DAG.getConstant(1, Op->getValueType(1)),
16205 DAG.getConstant(X86::COND_B, MVT::i32),
16206 SDValue(Result.getNode(), 1) };
16207 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
16208 DAG.getVTList(Op->getValueType(1), MVT::Glue),
16209 Ops);
16211 // Return { result, isValid, chain }.
16212 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
16213 SDValue(Result.getNode(), 2));
16214 }
16215 case GATHER: {
16216 //gather(v1, mask, index, base, scale);
16217 SDValue Chain = Op.getOperand(0);
16218 SDValue Src = Op.getOperand(2);
16219 SDValue Base = Op.getOperand(3);
16220 SDValue Index = Op.getOperand(4);
16221 SDValue Mask = Op.getOperand(5);
16222 SDValue Scale = Op.getOperand(6);
16223 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
16224 Subtarget);
16225 }
16226 case SCATTER: {
16227 //scatter(base, mask, index, v1, scale);
16228 SDValue Chain = Op.getOperand(0);
16229 SDValue Base = Op.getOperand(2);
16230 SDValue Mask = Op.getOperand(3);
16231 SDValue Index = Op.getOperand(4);
16232 SDValue Src = Op.getOperand(5);
16233 SDValue Scale = Op.getOperand(6);
16234 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
16235 }
16236 case PREFETCH: {
16237 SDValue Hint = Op.getOperand(6);
16238 unsigned HintVal;
16239 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
16240 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
16241 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
16242 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
16243 SDValue Chain = Op.getOperand(0);
16244 SDValue Mask = Op.getOperand(2);
16245 SDValue Index = Op.getOperand(3);
16246 SDValue Base = Op.getOperand(4);
16247 SDValue Scale = Op.getOperand(5);
16248 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
16249 }
16250 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
16251 case RDTSC: {
16252 SmallVector<SDValue, 2> Results;
16253 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
16254 return DAG.getMergeValues(Results, dl);
16255 }
16256 // Read Performance Monitoring Counters.
16257 case RDPMC: {
16258 SmallVector<SDValue, 2> Results;
16259 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
16260 return DAG.getMergeValues(Results, dl);
16261 }
16262 // XTEST intrinsics.
16263 case XTEST: {
16264 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16265 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16266 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16267 DAG.getConstant(X86::COND_NE, MVT::i8),
16268 InTrans);
16269 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
16270 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
16271 Ret, SDValue(InTrans.getNode(), 1));
16272 }
16273 // ADC/ADCX/SBB
16274 case ADX: {
16275 SmallVector<SDValue, 2> Results;
16276 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16277 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
16278 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
16279 DAG.getConstant(-1, MVT::i8));
16280 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
16281 Op.getOperand(4), GenCF.getValue(1));
16282 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
16283 Op.getOperand(5), MachinePointerInfo(),
16284 false, false, 0);
16285 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16286 DAG.getConstant(X86::COND_B, MVT::i8),
16287 Res.getValue(1));
16288 Results.push_back(SetCC);
16289 Results.push_back(Store);
16290 return DAG.getMergeValues(Results, dl);
16291 }
16292 }
16293 }
16295 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
16296 SelectionDAG &DAG) const {
16297 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16298 MFI->setReturnAddressIsTaken(true);
16300 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
16301 return SDValue();
16303 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16304 SDLoc dl(Op);
16305 EVT PtrVT = getPointerTy();
16307 if (Depth > 0) {
16308 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
16309 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16310 DAG.getSubtarget().getRegisterInfo());
16311 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
16312 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16313 DAG.getNode(ISD::ADD, dl, PtrVT,
16314 FrameAddr, Offset),
16315 MachinePointerInfo(), false, false, false, 0);
16316 }
16318 // Just load the return address.
16319 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
16320 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16321 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
16322 }
16324 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
16325 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16326 MFI->setFrameAddressIsTaken(true);
16328 EVT VT = Op.getValueType();
16329 SDLoc dl(Op); // FIXME probably not meaningful
16330 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16331 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16332 DAG.getSubtarget().getRegisterInfo());
16333 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
16334 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
16335 (FrameReg == X86::EBP && VT == MVT::i32)) &&
16336 "Invalid Frame Register!");
16337 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
16338 while (Depth--)
16339 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
16340 MachinePointerInfo(),
16341 false, false, false, 0);
16342 return FrameAddr;
16343 }
16345 // FIXME? Maybe this could be a TableGen attribute on some registers and
16346 // this table could be generated automatically from RegInfo.
16347 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
16348 EVT VT) const {
16349 unsigned Reg = StringSwitch<unsigned>(RegName)
16350 .Case("esp", X86::ESP)
16351 .Case("rsp", X86::RSP)
16352 .Default(0);
16353 if (Reg)
16354 return Reg;
16355 report_fatal_error("Invalid register name global variable");
16356 }
16358 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
16359 SelectionDAG &DAG) const {
16360 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16361 DAG.getSubtarget().getRegisterInfo());
16362 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
16363 }
16365 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
16366 SDValue Chain = Op.getOperand(0);
16367 SDValue Offset = Op.getOperand(1);
16368 SDValue Handler = Op.getOperand(2);
16369 SDLoc dl (Op);
16371 EVT PtrVT = getPointerTy();
16372 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16373 DAG.getSubtarget().getRegisterInfo());
16374 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
16375 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
16376 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
16377 "Invalid Frame Register!");
16378 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
16379 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
16381 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
16382 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
16383 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
16384 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
16385 false, false, 0);
16386 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
16388 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
16389 DAG.getRegister(StoreAddrReg, PtrVT));
16390 }
16392 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
16393 SelectionDAG &DAG) const {
16394 SDLoc DL(Op);
16395 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
16396 DAG.getVTList(MVT::i32, MVT::Other),
16397 Op.getOperand(0), Op.getOperand(1));
16398 }
16400 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
16401 SelectionDAG &DAG) const {
16402 SDLoc DL(Op);
16403 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
16404 Op.getOperand(0), Op.getOperand(1));
16405 }
16407 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
16408 return Op.getOperand(0);
16409 }
16411 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
16412 SelectionDAG &DAG) const {
16413 SDValue Root = Op.getOperand(0);
16414 SDValue Trmp = Op.getOperand(1); // trampoline
16415 SDValue FPtr = Op.getOperand(2); // nested function
16416 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
16417 SDLoc dl (Op);
16419 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16420 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
16422 if (Subtarget->is64Bit()) {
16423 SDValue OutChains[6];
16425 // Large code-model.
16426 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
16427 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
16429 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
16430 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
16432 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
16434 // Load the pointer to the nested function into R11.
16435 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
16436 SDValue Addr = Trmp;
16437 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16438 Addr, MachinePointerInfo(TrmpAddr),
16439 false, false, 0);
16441 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16442 DAG.getConstant(2, MVT::i64));
16443 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
16444 MachinePointerInfo(TrmpAddr, 2),
16445 false, false, 2);
16447 // Load the 'nest' parameter value into R10.
16448 // R10 is specified in X86CallingConv.td
16449 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
16450 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16451 DAG.getConstant(10, MVT::i64));
16452 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16453 Addr, MachinePointerInfo(TrmpAddr, 10),
16454 false, false, 0);
16456 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16457 DAG.getConstant(12, MVT::i64));
16458 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
16459 MachinePointerInfo(TrmpAddr, 12),
16460 false, false, 2);
16462 // Jump to the nested function.
16463 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
16464 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16465 DAG.getConstant(20, MVT::i64));
16466 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16467 Addr, MachinePointerInfo(TrmpAddr, 20),
16468 false, false, 0);
16470 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
16471 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16472 DAG.getConstant(22, MVT::i64));
16473 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
16474 MachinePointerInfo(TrmpAddr, 22),
16475 false, false, 0);
16477 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16478 } else {
16479 const Function *Func =
16480 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
16481 CallingConv::ID CC = Func->getCallingConv();
16482 unsigned NestReg;
16484 switch (CC) {
16485 default:
16486 llvm_unreachable("Unsupported calling convention");
16487 case CallingConv::C:
16488 case CallingConv::X86_StdCall: {
16489 // Pass 'nest' parameter in ECX.
16490 // Must be kept in sync with X86CallingConv.td
16491 NestReg = X86::ECX;
16493 // Check that ECX wasn't needed by an 'inreg' parameter.
16494 FunctionType *FTy = Func->getFunctionType();
16495 const AttributeSet &Attrs = Func->getAttributes();
16497 if (!Attrs.isEmpty() && !Func->isVarArg()) {
16498 unsigned InRegCount = 0;
16499 unsigned Idx = 1;
16501 for (FunctionType::param_iterator I = FTy->param_begin(),
16502 E = FTy->param_end(); I != E; ++I, ++Idx)
16503 if (Attrs.hasAttribute(Idx, Attribute::InReg))
16504 // FIXME: should only count parameters that are lowered to integers.
16505 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
16507 if (InRegCount > 2) {
16508 report_fatal_error("Nest register in use - reduce number of inreg"
16509 " parameters!");
16510 }
16511 }
16512 break;
16513 }
16514 case CallingConv::X86_FastCall:
16515 case CallingConv::X86_ThisCall:
16516 case CallingConv::Fast:
16517 // Pass 'nest' parameter in EAX.
16518 // Must be kept in sync with X86CallingConv.td
16519 NestReg = X86::EAX;
16520 break;
16521 }
16523 SDValue OutChains[4];
16524 SDValue Addr, Disp;
16526 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16527 DAG.getConstant(10, MVT::i32));
16528 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
16530 // This is storing the opcode for MOV32ri.
16531 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
16532 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
16533 OutChains[0] = DAG.getStore(Root, dl,
16534 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
16535 Trmp, MachinePointerInfo(TrmpAddr),
16536 false, false, 0);
16538 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16539 DAG.getConstant(1, MVT::i32));
16540 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
16541 MachinePointerInfo(TrmpAddr, 1),
16542 false, false, 1);
16544 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
16545 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16546 DAG.getConstant(5, MVT::i32));
16547 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
16548 MachinePointerInfo(TrmpAddr, 5),
16549 false, false, 1);
16551 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16552 DAG.getConstant(6, MVT::i32));
16553 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
16554 MachinePointerInfo(TrmpAddr, 6),
16555 false, false, 1);
16557 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16558 }
16559 }
16561 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
16562 SelectionDAG &DAG) const {
16563 /*
16564 The rounding mode is in bits 11:10 of FPSR, and has the following
16565 settings:
16566 00 Round to nearest
16567 01 Round to -inf
16568 10 Round to +inf
16569 11 Round to 0
16571 FLT_ROUNDS, on the other hand, expects the following:
16572 -1 Undefined
16573 0 Round to 0
16574 1 Round to nearest
16575 2 Round to +inf
16576 3 Round to -inf
16578 To perform the conversion, we do:
16579 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
16580 */
16582 MachineFunction &MF = DAG.getMachineFunction();
16583 const TargetMachine &TM = MF.getTarget();
16584 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
16585 unsigned StackAlignment = TFI.getStackAlignment();
16586 MVT VT = Op.getSimpleValueType();
16587 SDLoc DL(Op);
16589 // Save FP Control Word to stack slot
16590 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
16591 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
16593 MachineMemOperand *MMO =
16594 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
16595 MachineMemOperand::MOStore, 2, 2);
16597 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
16598 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
16599 DAG.getVTList(MVT::Other),
16600 Ops, MVT::i16, MMO);
16602 // Load FP Control Word from stack slot
16603 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
16604 MachinePointerInfo(), false, false, false, 0);
16606 // Transform as necessary
16607 SDValue CWD1 =
16608 DAG.getNode(ISD::SRL, DL, MVT::i16,
16609 DAG.getNode(ISD::AND, DL, MVT::i16,
16610 CWD, DAG.getConstant(0x800, MVT::i16)),
16611 DAG.getConstant(11, MVT::i8));
16612 SDValue CWD2 =
16613 DAG.getNode(ISD::SRL, DL, MVT::i16,
16614 DAG.getNode(ISD::AND, DL, MVT::i16,
16615 CWD, DAG.getConstant(0x400, MVT::i16)),
16616 DAG.getConstant(9, MVT::i8));
16618 SDValue RetVal =
16619 DAG.getNode(ISD::AND, DL, MVT::i16,
16620 DAG.getNode(ISD::ADD, DL, MVT::i16,
16621 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
16622 DAG.getConstant(1, MVT::i16)),
16623 DAG.getConstant(3, MVT::i16));
16625 return DAG.getNode((VT.getSizeInBits() < 16 ?
16626 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
16627 }
16629 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
16630 MVT VT = Op.getSimpleValueType();
16631 EVT OpVT = VT;
16632 unsigned NumBits = VT.getSizeInBits();
16633 SDLoc dl(Op);
16635 Op = Op.getOperand(0);
16636 if (VT == MVT::i8) {
16637 // Zero extend to i32 since there is not an i8 bsr.
16638 OpVT = MVT::i32;
16639 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16640 }
16642 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
16643 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16644 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16646 // If src is zero (i.e. bsr sets ZF), returns NumBits.
16647 SDValue Ops[] = {
16648 Op,
16649 DAG.getConstant(NumBits+NumBits-1, OpVT),
16650 DAG.getConstant(X86::COND_E, MVT::i8),
16651 Op.getValue(1)
16652 };
16653 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
16655 // Finally xor with NumBits-1.
16656 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
16658 if (VT == MVT::i8)
16659 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16660 return Op;
16661 }
16663 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
16664 MVT VT = Op.getSimpleValueType();
16665 EVT OpVT = VT;
16666 unsigned NumBits = VT.getSizeInBits();
16667 SDLoc dl(Op);
16669 Op = Op.getOperand(0);
16670 if (VT == MVT::i8) {
16671 // Zero extend to i32 since there is not an i8 bsr.
16672 OpVT = MVT::i32;
16673 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16674 }
16676 // Issue a bsr (scan bits in reverse).
16677 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16678 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16680 // And xor with NumBits-1.
16681 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
16683 if (VT == MVT::i8)
16684 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16685 return Op;
16686 }
16688 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
16689 MVT VT = Op.getSimpleValueType();
16690 unsigned NumBits = VT.getSizeInBits();
16691 SDLoc dl(Op);
16692 Op = Op.getOperand(0);
16694 // Issue a bsf (scan bits forward) which also sets EFLAGS.
16695 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
16696 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
16698 // If src is zero (i.e. bsf sets ZF), returns NumBits.
16699 SDValue Ops[] = {
16700 Op,
16701 DAG.getConstant(NumBits, VT),
16702 DAG.getConstant(X86::COND_E, MVT::i8),
16703 Op.getValue(1)
16704 };
16705 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
16706 }
16708 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
16709 // ones, and then concatenate the result back.
16710 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
16711 MVT VT = Op.getSimpleValueType();
16713 assert(VT.is256BitVector() && VT.isInteger() &&
16714 "Unsupported value type for operation");
16716 unsigned NumElems = VT.getVectorNumElements();
16717 SDLoc dl(Op);
16719 // Extract the LHS vectors
16720 SDValue LHS = Op.getOperand(0);
16721 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
16722 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
16724 // Extract the RHS vectors
16725 SDValue RHS = Op.getOperand(1);
16726 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
16727 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
16729 MVT EltVT = VT.getVectorElementType();
16730 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16732 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
16733 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
16734 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
16735 }
16737 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
16738 assert(Op.getSimpleValueType().is256BitVector() &&
16739 Op.getSimpleValueType().isInteger() &&
16740 "Only handle AVX 256-bit vector integer operation");
16741 return Lower256IntArith(Op, DAG);
16742 }
16744 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
16745 assert(Op.getSimpleValueType().is256BitVector() &&
16746 Op.getSimpleValueType().isInteger() &&
16747 "Only handle AVX 256-bit vector integer operation");
16748 return Lower256IntArith(Op, DAG);
16749 }
16751 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
16752 SelectionDAG &DAG) {
16753 SDLoc dl(Op);
16754 MVT VT = Op.getSimpleValueType();
16756 // Decompose 256-bit ops into smaller 128-bit ops.
16757 if (VT.is256BitVector() && !Subtarget->hasInt256())
16758 return Lower256IntArith(Op, DAG);
16760 SDValue A = Op.getOperand(0);
16761 SDValue B = Op.getOperand(1);
16763 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
16764 if (VT == MVT::v4i32) {
16765 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
16766 "Should not custom lower when pmuldq is available!");
16768 // Extract the odd parts.
16769 static const int UnpackMask[] = { 1, -1, 3, -1 };
16770 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
16771 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
16773 // Multiply the even parts.
16774 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
16775 // Now multiply odd parts.
16776 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
16778 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
16779 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
16781 // Merge the two vectors back together with a shuffle. This expands into 2
16782 // shuffles.
16783 static const int ShufMask[] = { 0, 4, 2, 6 };
16784 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
16785 }
16787 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
16788 "Only know how to lower V2I64/V4I64/V8I64 multiply");
16790 // Ahi = psrlqi(a, 32);
16791 // Bhi = psrlqi(b, 32);
16792 //
16793 // AloBlo = pmuludq(a, b);
16794 // AloBhi = pmuludq(a, Bhi);
16795 // AhiBlo = pmuludq(Ahi, b);
16797 // AloBhi = psllqi(AloBhi, 32);
16798 // AhiBlo = psllqi(AhiBlo, 32);
16799 // return AloBlo + AloBhi + AhiBlo;
16801 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
16802 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
16804 // Bit cast to 32-bit vectors for MULUDQ
16805 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
16806 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
16807 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
16808 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
16809 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
16810 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
16812 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
16813 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
16814 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
16816 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
16817 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
16819 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
16820 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
16821 }
16823 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
16824 assert(Subtarget->isTargetWin64() && "Unexpected target");
16825 EVT VT = Op.getValueType();
16826 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
16827 "Unexpected return type for lowering");
16829 RTLIB::Libcall LC;
16830 bool isSigned;
16831 switch (Op->getOpcode()) {
16832 default: llvm_unreachable("Unexpected request for libcall!");
16833 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
16834 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
16835 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
16836 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
16837 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
16838 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
16839 }
16841 SDLoc dl(Op);
16842 SDValue InChain = DAG.getEntryNode();
16844 TargetLowering::ArgListTy Args;
16845 TargetLowering::ArgListEntry Entry;
16846 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
16847 EVT ArgVT = Op->getOperand(i).getValueType();
16848 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
16849 "Unexpected argument type for lowering");
16850 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
16851 Entry.Node = StackPtr;
16852 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
16853 false, false, 16);
16854 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16855 Entry.Ty = PointerType::get(ArgTy,0);
16856 Entry.isSExt = false;
16857 Entry.isZExt = false;
16858 Args.push_back(Entry);
16859 }
16861 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
16862 getPointerTy());
16864 TargetLowering::CallLoweringInfo CLI(DAG);
16865 CLI.setDebugLoc(dl).setChain(InChain)
16866 .setCallee(getLibcallCallingConv(LC),
16867 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
16868 Callee, std::move(Args), 0)
16869 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
16871 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
16872 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
16873 }
16875 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
16876 SelectionDAG &DAG) {
16877 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
16878 EVT VT = Op0.getValueType();
16879 SDLoc dl(Op);
16881 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
16882 (VT == MVT::v8i32 && Subtarget->hasInt256()));
16884 // PMULxD operations multiply each even value (starting at 0) of LHS with
16885 // the related value of RHS and produce a widen result.
16886 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16887 // => <2 x i64> <ae|cg>
16888 //
16889 // In other word, to have all the results, we need to perform two PMULxD:
16890 // 1. one with the even values.
16891 // 2. one with the odd values.
16892 // To achieve #2, with need to place the odd values at an even position.
16893 //
16894 // Place the odd value at an even position (basically, shift all values 1
16895 // step to the left):
16896 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
16897 // <a|b|c|d> => <b|undef|d|undef>
16898 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
16899 // <e|f|g|h> => <f|undef|h|undef>
16900 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
16902 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
16903 // ints.
16904 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
16905 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
16906 unsigned Opcode =
16907 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
16908 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16909 // => <2 x i64> <ae|cg>
16910 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
16911 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
16912 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
16913 // => <2 x i64> <bf|dh>
16914 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
16915 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
16917 // Shuffle it back into the right order.
16918 SDValue Highs, Lows;
16919 if (VT == MVT::v8i32) {
16920 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
16921 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16922 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
16923 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16924 } else {
16925 const int HighMask[] = {1, 5, 3, 7};
16926 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16927 const int LowMask[] = {0, 4, 2, 6};
16928 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16929 }
16931 // If we have a signed multiply but no PMULDQ fix up the high parts of a
16932 // unsigned multiply.
16933 if (IsSigned && !Subtarget->hasSSE41()) {
16934 SDValue ShAmt =
16935 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
16936 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
16937 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
16938 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
16939 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
16941 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
16942 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
16943 }
16945 // The first result of MUL_LOHI is actually the low value, followed by the
16946 // high value.
16947 SDValue Ops[] = {Lows, Highs};
16948 return DAG.getMergeValues(Ops, dl);
16949 }
16951 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
16952 const X86Subtarget *Subtarget) {
16953 MVT VT = Op.getSimpleValueType();
16954 SDLoc dl(Op);
16955 SDValue R = Op.getOperand(0);
16956 SDValue Amt = Op.getOperand(1);
16958 // Optimize shl/srl/sra with constant shift amount.
16959 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
16960 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
16961 uint64_t ShiftAmt = ShiftConst->getZExtValue();
16963 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
16964 (Subtarget->hasInt256() &&
16965 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
16966 (Subtarget->hasAVX512() &&
16967 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
16968 if (Op.getOpcode() == ISD::SHL)
16969 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
16970 DAG);
16971 if (Op.getOpcode() == ISD::SRL)
16972 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
16973 DAG);
16974 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
16975 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
16976 DAG);
16977 }
16979 if (VT == MVT::v16i8) {
16980 if (Op.getOpcode() == ISD::SHL) {
16981 // Make a large shift.
16982 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
16983 MVT::v8i16, R, ShiftAmt,
16984 DAG);
16985 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
16986 // Zero out the rightmost bits.
16987 SmallVector<SDValue, 16> V(16,
16988 DAG.getConstant(uint8_t(-1U << ShiftAmt),
16989 MVT::i8));
16990 return DAG.getNode(ISD::AND, dl, VT, SHL,
16991 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16992 }
16993 if (Op.getOpcode() == ISD::SRL) {
16994 // Make a large shift.
16995 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
16996 MVT::v8i16, R, ShiftAmt,
16997 DAG);
16998 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
16999 // Zero out the leftmost bits.
17000 SmallVector<SDValue, 16> V(16,
17001 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
17002 MVT::i8));
17003 return DAG.getNode(ISD::AND, dl, VT, SRL,
17004 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17005 }
17006 if (Op.getOpcode() == ISD::SRA) {
17007 if (ShiftAmt == 7) {
17008 // R s>> 7 === R s< 0
17009 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
17010 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
17011 }
17013 // R s>> a === ((R u>> a) ^ m) - m
17014 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
17015 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
17016 MVT::i8));
17017 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
17018 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
17019 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
17020 return Res;
17021 }
17022 llvm_unreachable("Unknown shift opcode.");
17023 }
17025 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
17026 if (Op.getOpcode() == ISD::SHL) {
17027 // Make a large shift.
17028 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
17029 MVT::v16i16, R, ShiftAmt,
17030 DAG);
17031 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
17032 // Zero out the rightmost bits.
17033 SmallVector<SDValue, 32> V(32,
17034 DAG.getConstant(uint8_t(-1U << ShiftAmt),
17035 MVT::i8));
17036 return DAG.getNode(ISD::AND, dl, VT, SHL,
17037 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17038 }
17039 if (Op.getOpcode() == ISD::SRL) {
17040 // Make a large shift.
17041 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
17042 MVT::v16i16, R, ShiftAmt,
17043 DAG);
17044 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
17045 // Zero out the leftmost bits.
17046 SmallVector<SDValue, 32> V(32,
17047 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
17048 MVT::i8));
17049 return DAG.getNode(ISD::AND, dl, VT, SRL,
17050 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17051 }
17052 if (Op.getOpcode() == ISD::SRA) {
17053 if (ShiftAmt == 7) {
17054 // R s>> 7 === R s< 0
17055 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
17056 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
17057 }
17059 // R s>> a === ((R u>> a) ^ m) - m
17060 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
17061 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
17062 MVT::i8));
17063 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
17064 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
17065 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
17066 return Res;
17067 }
17068 llvm_unreachable("Unknown shift opcode.");
17069 }
17070 }
17071 }
17073 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17074 if (!Subtarget->is64Bit() &&
17075 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
17076 Amt.getOpcode() == ISD::BITCAST &&
17077 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
17078 Amt = Amt.getOperand(0);
17079 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17080 VT.getVectorNumElements();
17081 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
17082 uint64_t ShiftAmt = 0;
17083 for (unsigned i = 0; i != Ratio; ++i) {
17084 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
17085 if (!C)
17086 return SDValue();
17087 // 6 == Log2(64)
17088 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
17089 }
17090 // Check remaining shift amounts.
17091 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17092 uint64_t ShAmt = 0;
17093 for (unsigned j = 0; j != Ratio; ++j) {
17094 ConstantSDNode *C =
17095 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
17096 if (!C)
17097 return SDValue();
17098 // 6 == Log2(64)
17099 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
17100 }
17101 if (ShAmt != ShiftAmt)
17102 return SDValue();
17103 }
17104 switch (Op.getOpcode()) {
17105 default:
17106 llvm_unreachable("Unknown shift opcode!");
17107 case ISD::SHL:
17108 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
17109 DAG);
17110 case ISD::SRL:
17111 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
17112 DAG);
17113 case ISD::SRA:
17114 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
17115 DAG);
17116 }
17117 }
17119 return SDValue();
17120 }
17122 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
17123 const X86Subtarget* Subtarget) {
17124 MVT VT = Op.getSimpleValueType();
17125 SDLoc dl(Op);
17126 SDValue R = Op.getOperand(0);
17127 SDValue Amt = Op.getOperand(1);
17129 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
17130 VT == MVT::v4i32 || VT == MVT::v8i16 ||
17131 (Subtarget->hasInt256() &&
17132 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
17133 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
17134 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
17135 SDValue BaseShAmt;
17136 EVT EltVT = VT.getVectorElementType();
17138 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
17139 unsigned NumElts = VT.getVectorNumElements();
17140 unsigned i, j;
17141 for (i = 0; i != NumElts; ++i) {
17142 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
17143 continue;
17144 break;
17145 }
17146 for (j = i; j != NumElts; ++j) {
17147 SDValue Arg = Amt.getOperand(j);
17148 if (Arg.getOpcode() == ISD::UNDEF) continue;
17149 if (Arg != Amt.getOperand(i))
17150 break;
17151 }
17152 if (i != NumElts && j == NumElts)
17153 BaseShAmt = Amt.getOperand(i);
17154 } else {
17155 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
17156 Amt = Amt.getOperand(0);
17157 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
17158 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
17159 SDValue InVec = Amt.getOperand(0);
17160 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
17161 unsigned NumElts = InVec.getValueType().getVectorNumElements();
17162 unsigned i = 0;
17163 for (; i != NumElts; ++i) {
17164 SDValue Arg = InVec.getOperand(i);
17165 if (Arg.getOpcode() == ISD::UNDEF) continue;
17166 BaseShAmt = Arg;
17167 break;
17168 }
17169 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
17170 if (ConstantSDNode *C =
17171 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
17172 unsigned SplatIdx =
17173 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
17174 if (C->getZExtValue() == SplatIdx)
17175 BaseShAmt = InVec.getOperand(1);
17176 }
17177 }
17178 if (!BaseShAmt.getNode())
17179 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
17180 DAG.getIntPtrConstant(0));
17181 }
17182 }
17184 if (BaseShAmt.getNode()) {
17185 if (EltVT.bitsGT(MVT::i32))
17186 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
17187 else if (EltVT.bitsLT(MVT::i32))
17188 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
17190 switch (Op.getOpcode()) {
17191 default:
17192 llvm_unreachable("Unknown shift opcode!");
17193 case ISD::SHL:
17194 switch (VT.SimpleTy) {
17195 default: return SDValue();
17196 case MVT::v2i64:
17197 case MVT::v4i32:
17198 case MVT::v8i16:
17199 case MVT::v4i64:
17200 case MVT::v8i32:
17201 case MVT::v16i16:
17202 case MVT::v16i32:
17203 case MVT::v8i64:
17204 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
17205 }
17206 case ISD::SRA:
17207 switch (VT.SimpleTy) {
17208 default: return SDValue();
17209 case MVT::v4i32:
17210 case MVT::v8i16:
17211 case MVT::v8i32:
17212 case MVT::v16i16:
17213 case MVT::v16i32:
17214 case MVT::v8i64:
17215 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
17216 }
17217 case ISD::SRL:
17218 switch (VT.SimpleTy) {
17219 default: return SDValue();
17220 case MVT::v2i64:
17221 case MVT::v4i32:
17222 case MVT::v8i16:
17223 case MVT::v4i64:
17224 case MVT::v8i32:
17225 case MVT::v16i16:
17226 case MVT::v16i32:
17227 case MVT::v8i64:
17228 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
17229 }
17230 }
17231 }
17232 }
17234 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17235 if (!Subtarget->is64Bit() &&
17236 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
17237 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
17238 Amt.getOpcode() == ISD::BITCAST &&
17239 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
17240 Amt = Amt.getOperand(0);
17241 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17242 VT.getVectorNumElements();
17243 std::vector<SDValue> Vals(Ratio);
17244 for (unsigned i = 0; i != Ratio; ++i)
17245 Vals[i] = Amt.getOperand(i);
17246 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17247 for (unsigned j = 0; j != Ratio; ++j)
17248 if (Vals[j] != Amt.getOperand(i + j))
17249 return SDValue();
17250 }
17251 switch (Op.getOpcode()) {
17252 default:
17253 llvm_unreachable("Unknown shift opcode!");
17254 case ISD::SHL:
17255 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
17256 case ISD::SRL:
17257 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
17258 case ISD::SRA:
17259 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
17260 }
17261 }
17263 return SDValue();
17264 }
17266 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
17267 SelectionDAG &DAG) {
17268 MVT VT = Op.getSimpleValueType();
17269 SDLoc dl(Op);
17270 SDValue R = Op.getOperand(0);
17271 SDValue Amt = Op.getOperand(1);
17272 SDValue V;
17274 assert(VT.isVector() && "Custom lowering only for vector shifts!");
17275 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
17277 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
17278 if (V.getNode())
17279 return V;
17281 V = LowerScalarVariableShift(Op, DAG, Subtarget);
17282 if (V.getNode())
17283 return V;
17285 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
17286 return Op;
17287 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
17288 if (Subtarget->hasInt256()) {
17289 if (Op.getOpcode() == ISD::SRL &&
17290 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
17291 VT == MVT::v4i64 || VT == MVT::v8i32))
17292 return Op;
17293 if (Op.getOpcode() == ISD::SHL &&
17294 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
17295 VT == MVT::v4i64 || VT == MVT::v8i32))
17296 return Op;
17297 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
17298 return Op;
17299 }
17301 // If possible, lower this packed shift into a vector multiply instead of
17302 // expanding it into a sequence of scalar shifts.
17303 // Do this only if the vector shift count is a constant build_vector.
17304 if (Op.getOpcode() == ISD::SHL &&
17305 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
17306 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
17307 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17308 SmallVector<SDValue, 8> Elts;
17309 EVT SVT = VT.getScalarType();
17310 unsigned SVTBits = SVT.getSizeInBits();
17311 const APInt &One = APInt(SVTBits, 1);
17312 unsigned NumElems = VT.getVectorNumElements();
17314 for (unsigned i=0; i !=NumElems; ++i) {
17315 SDValue Op = Amt->getOperand(i);
17316 if (Op->getOpcode() == ISD::UNDEF) {
17317 Elts.push_back(Op);
17318 continue;
17319 }
17321 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
17322 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
17323 uint64_t ShAmt = C.getZExtValue();
17324 if (ShAmt >= SVTBits) {
17325 Elts.push_back(DAG.getUNDEF(SVT));
17326 continue;
17327 }
17328 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
17329 }
17330 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
17331 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
17332 }
17334 // Lower SHL with variable shift amount.
17335 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
17336 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
17338 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
17339 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
17340 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
17341 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
17342 }
17344 // If possible, lower this shift as a sequence of two shifts by
17345 // constant plus a MOVSS/MOVSD instead of scalarizing it.
17346 // Example:
17347 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
17348 //
17349 // Could be rewritten as:
17350 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
17351 //
17352 // The advantage is that the two shifts from the example would be
17353 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
17354 // the vector shift into four scalar shifts plus four pairs of vector
17355 // insert/extract.
17356 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
17357 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17358 unsigned TargetOpcode = X86ISD::MOVSS;
17359 bool CanBeSimplified;
17360 // The splat value for the first packed shift (the 'X' from the example).
17361 SDValue Amt1 = Amt->getOperand(0);
17362 // The splat value for the second packed shift (the 'Y' from the example).
17363 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
17364 Amt->getOperand(2);
17366 // See if it is possible to replace this node with a sequence of
17367 // two shifts followed by a MOVSS/MOVSD
17368 if (VT == MVT::v4i32) {
17369 // Check if it is legal to use a MOVSS.
17370 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
17371 Amt2 == Amt->getOperand(3);
17372 if (!CanBeSimplified) {
17373 // Otherwise, check if we can still simplify this node using a MOVSD.
17374 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
17375 Amt->getOperand(2) == Amt->getOperand(3);
17376 TargetOpcode = X86ISD::MOVSD;
17377 Amt2 = Amt->getOperand(2);
17378 }
17379 } else {
17380 // Do similar checks for the case where the machine value type
17381 // is MVT::v8i16.
17382 CanBeSimplified = Amt1 == Amt->getOperand(1);
17383 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
17384 CanBeSimplified = Amt2 == Amt->getOperand(i);
17386 if (!CanBeSimplified) {
17387 TargetOpcode = X86ISD::MOVSD;
17388 CanBeSimplified = true;
17389 Amt2 = Amt->getOperand(4);
17390 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
17391 CanBeSimplified = Amt1 == Amt->getOperand(i);
17392 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
17393 CanBeSimplified = Amt2 == Amt->getOperand(j);
17394 }
17395 }
17397 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
17398 isa<ConstantSDNode>(Amt2)) {
17399 // Replace this node with two shifts followed by a MOVSS/MOVSD.
17400 EVT CastVT = MVT::v4i32;
17401 SDValue Splat1 =
17402 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
17403 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
17404 SDValue Splat2 =
17405 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
17406 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
17407 if (TargetOpcode == X86ISD::MOVSD)
17408 CastVT = MVT::v2i64;
17409 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
17410 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
17411 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
17412 BitCast1, DAG);
17413 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
17414 }
17415 }
17417 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
17418 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
17420 // a = a << 5;
17421 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
17422 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
17424 // Turn 'a' into a mask suitable for VSELECT
17425 SDValue VSelM = DAG.getConstant(0x80, VT);
17426 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17427 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17429 SDValue CM1 = DAG.getConstant(0x0f, VT);
17430 SDValue CM2 = DAG.getConstant(0x3f, VT);
17432 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
17433 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
17434 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
17435 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
17436 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
17438 // a += a
17439 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
17440 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17441 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17443 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
17444 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
17445 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
17446 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
17447 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
17449 // a += a
17450 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
17451 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17452 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17454 // return VSELECT(r, r+r, a);
17455 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
17456 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
17457 return R;
17458 }
17460 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
17461 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
17462 // solution better.
17463 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
17464 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
17465 unsigned ExtOpc =
17466 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
17467 R = DAG.getNode(ExtOpc, dl, NewVT, R);
17468 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
17469 return DAG.getNode(ISD::TRUNCATE, dl, VT,
17470 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
17471 }
17473 // Decompose 256-bit shifts into smaller 128-bit shifts.
17474 if (VT.is256BitVector()) {
17475 unsigned NumElems = VT.getVectorNumElements();
17476 MVT EltVT = VT.getVectorElementType();
17477 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17479 // Extract the two vectors
17480 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
17481 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
17483 // Recreate the shift amount vectors
17484 SDValue Amt1, Amt2;
17485 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
17486 // Constant shift amount
17487 SmallVector<SDValue, 4> Amt1Csts;
17488 SmallVector<SDValue, 4> Amt2Csts;
17489 for (unsigned i = 0; i != NumElems/2; ++i)
17490 Amt1Csts.push_back(Amt->getOperand(i));
17491 for (unsigned i = NumElems/2; i != NumElems; ++i)
17492 Amt2Csts.push_back(Amt->getOperand(i));
17494 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
17495 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
17496 } else {
17497 // Variable shift amount
17498 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
17499 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
17500 }
17502 // Issue new vector shifts for the smaller types
17503 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
17504 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
17506 // Concatenate the result back
17507 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
17508 }
17510 return SDValue();
17511 }
17513 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
17514 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
17515 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
17516 // looks for this combo and may remove the "setcc" instruction if the "setcc"
17517 // has only one use.
17518 SDNode *N = Op.getNode();
17519 SDValue LHS = N->getOperand(0);
17520 SDValue RHS = N->getOperand(1);
17521 unsigned BaseOp = 0;
17522 unsigned Cond = 0;
17523 SDLoc DL(Op);
17524 switch (Op.getOpcode()) {
17525 default: llvm_unreachable("Unknown ovf instruction!");
17526 case ISD::SADDO:
17527 // A subtract of one will be selected as a INC. Note that INC doesn't
17528 // set CF, so we can't do this for UADDO.
17529 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17530 if (C->isOne()) {
17531 BaseOp = X86ISD::INC;
17532 Cond = X86::COND_O;
17533 break;
17534 }
17535 BaseOp = X86ISD::ADD;
17536 Cond = X86::COND_O;
17537 break;
17538 case ISD::UADDO:
17539 BaseOp = X86ISD::ADD;
17540 Cond = X86::COND_B;
17541 break;
17542 case ISD::SSUBO:
17543 // A subtract of one will be selected as a DEC. Note that DEC doesn't
17544 // set CF, so we can't do this for USUBO.
17545 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17546 if (C->isOne()) {
17547 BaseOp = X86ISD::DEC;
17548 Cond = X86::COND_O;
17549 break;
17550 }
17551 BaseOp = X86ISD::SUB;
17552 Cond = X86::COND_O;
17553 break;
17554 case ISD::USUBO:
17555 BaseOp = X86ISD::SUB;
17556 Cond = X86::COND_B;
17557 break;
17558 case ISD::SMULO:
17559 BaseOp = X86ISD::SMUL;
17560 Cond = X86::COND_O;
17561 break;
17562 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
17563 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
17564 MVT::i32);
17565 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
17567 SDValue SetCC =
17568 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17569 DAG.getConstant(X86::COND_O, MVT::i32),
17570 SDValue(Sum.getNode(), 2));
17572 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17573 }
17574 }
17576 // Also sets EFLAGS.
17577 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
17578 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
17580 SDValue SetCC =
17581 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
17582 DAG.getConstant(Cond, MVT::i32),
17583 SDValue(Sum.getNode(), 1));
17585 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17586 }
17588 // Sign extension of the low part of vector elements. This may be used either
17589 // when sign extend instructions are not available or if the vector element
17590 // sizes already match the sign-extended size. If the vector elements are in
17591 // their pre-extended size and sign extend instructions are available, that will
17592 // be handled by LowerSIGN_EXTEND.
17593 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
17594 SelectionDAG &DAG) const {
17595 SDLoc dl(Op);
17596 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
17597 MVT VT = Op.getSimpleValueType();
17599 if (!Subtarget->hasSSE2() || !VT.isVector())
17600 return SDValue();
17602 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
17603 ExtraVT.getScalarType().getSizeInBits();
17605 switch (VT.SimpleTy) {
17606 default: return SDValue();
17607 case MVT::v8i32:
17608 case MVT::v16i16:
17609 if (!Subtarget->hasFp256())
17610 return SDValue();
17611 if (!Subtarget->hasInt256()) {
17612 // needs to be split
17613 unsigned NumElems = VT.getVectorNumElements();
17615 // Extract the LHS vectors
17616 SDValue LHS = Op.getOperand(0);
17617 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17618 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17620 MVT EltVT = VT.getVectorElementType();
17621 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17623 EVT ExtraEltVT = ExtraVT.getVectorElementType();
17624 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
17625 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
17626 ExtraNumElems/2);
17627 SDValue Extra = DAG.getValueType(ExtraVT);
17629 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
17630 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
17632 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
17633 }
17634 // fall through
17635 case MVT::v4i32:
17636 case MVT::v8i16: {
17637 SDValue Op0 = Op.getOperand(0);
17639 // This is a sign extension of some low part of vector elements without
17640 // changing the size of the vector elements themselves:
17641 // Shift-Left + Shift-Right-Algebraic.
17642 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
17643 BitsDiff, DAG);
17644 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
17645 DAG);
17646 }
17647 }
17648 }
17650 /// Returns true if the operand type is exactly twice the native width, and
17651 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
17652 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
17653 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
17654 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
17655 const X86Subtarget &Subtarget =
17656 getTargetMachine().getSubtarget<X86Subtarget>();
17657 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
17659 if (OpWidth == 64)
17660 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
17661 else if (OpWidth == 128)
17662 return Subtarget.hasCmpxchg16b();
17663 else
17664 return false;
17665 }
17667 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
17668 return needsCmpXchgNb(SI->getValueOperand()->getType());
17669 }
17671 // Note: this turns large loads into lock cmpxchg8b/16b.
17672 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
17673 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
17674 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
17675 return needsCmpXchgNb(PTy->getElementType());
17676 }
17678 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
17679 const X86Subtarget &Subtarget =
17680 getTargetMachine().getSubtarget<X86Subtarget>();
17681 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
17682 const Type *MemType = AI->getType();
17684 // If the operand is too big, we must see if cmpxchg8/16b is available
17685 // and default to library calls otherwise.
17686 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
17687 return needsCmpXchgNb(MemType);
17689 AtomicRMWInst::BinOp Op = AI->getOperation();
17690 switch (Op) {
17691 default:
17692 llvm_unreachable("Unknown atomic operation");
17693 case AtomicRMWInst::Xchg:
17694 case AtomicRMWInst::Add:
17695 case AtomicRMWInst::Sub:
17696 // It's better to use xadd, xsub or xchg for these in all cases.
17697 return false;
17698 case AtomicRMWInst::Or:
17699 case AtomicRMWInst::And:
17700 case AtomicRMWInst::Xor:
17701 // If the atomicrmw's result isn't actually used, we can just add a "lock"
17702 // prefix to a normal instruction for these operations.
17703 return !AI->use_empty();
17704 case AtomicRMWInst::Nand:
17705 case AtomicRMWInst::Max:
17706 case AtomicRMWInst::Min:
17707 case AtomicRMWInst::UMax:
17708 case AtomicRMWInst::UMin:
17709 // These always require a non-trivial set of data operations on x86. We must
17710 // use a cmpxchg loop.
17711 return true;
17712 }
17713 }
17715 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
17716 SelectionDAG &DAG) {
17717 SDLoc dl(Op);
17718 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
17719 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
17720 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
17721 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
17723 // The only fence that needs an instruction is a sequentially-consistent
17724 // cross-thread fence.
17725 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
17726 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
17727 // no-sse2). There isn't any reason to disable it if the target processor
17728 // supports it.
17729 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
17730 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
17732 SDValue Chain = Op.getOperand(0);
17733 SDValue Zero = DAG.getConstant(0, MVT::i32);
17734 SDValue Ops[] = {
17735 DAG.getRegister(X86::ESP, MVT::i32), // Base
17736 DAG.getTargetConstant(1, MVT::i8), // Scale
17737 DAG.getRegister(0, MVT::i32), // Index
17738 DAG.getTargetConstant(0, MVT::i32), // Disp
17739 DAG.getRegister(0, MVT::i32), // Segment.
17740 Zero,
17741 Chain
17742 };
17743 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
17744 return SDValue(Res, 0);
17745 }
17747 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
17748 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
17749 }
17751 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
17752 SelectionDAG &DAG) {
17753 MVT T = Op.getSimpleValueType();
17754 SDLoc DL(Op);
17755 unsigned Reg = 0;
17756 unsigned size = 0;
17757 switch(T.SimpleTy) {
17758 default: llvm_unreachable("Invalid value type!");
17759 case MVT::i8: Reg = X86::AL; size = 1; break;
17760 case MVT::i16: Reg = X86::AX; size = 2; break;
17761 case MVT::i32: Reg = X86::EAX; size = 4; break;
17762 case MVT::i64:
17763 assert(Subtarget->is64Bit() && "Node not type legal!");
17764 Reg = X86::RAX; size = 8;
17765 break;
17766 }
17767 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
17768 Op.getOperand(2), SDValue());
17769 SDValue Ops[] = { cpIn.getValue(0),
17770 Op.getOperand(1),
17771 Op.getOperand(3),
17772 DAG.getTargetConstant(size, MVT::i8),
17773 cpIn.getValue(1) };
17774 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17775 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
17776 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
17777 Ops, T, MMO);
17779 SDValue cpOut =
17780 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
17781 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
17782 MVT::i32, cpOut.getValue(2));
17783 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
17784 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
17786 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
17787 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
17788 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
17789 return SDValue();
17790 }
17792 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
17793 SelectionDAG &DAG) {
17794 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
17795 MVT DstVT = Op.getSimpleValueType();
17797 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
17798 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17799 if (DstVT != MVT::f64)
17800 // This conversion needs to be expanded.
17801 return SDValue();
17803 SDValue InVec = Op->getOperand(0);
17804 SDLoc dl(Op);
17805 unsigned NumElts = SrcVT.getVectorNumElements();
17806 EVT SVT = SrcVT.getVectorElementType();
17808 // Widen the vector in input in the case of MVT::v2i32.
17809 // Example: from MVT::v2i32 to MVT::v4i32.
17810 SmallVector<SDValue, 16> Elts;
17811 for (unsigned i = 0, e = NumElts; i != e; ++i)
17812 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
17813 DAG.getIntPtrConstant(i)));
17815 // Explicitly mark the extra elements as Undef.
17816 SDValue Undef = DAG.getUNDEF(SVT);
17817 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
17818 Elts.push_back(Undef);
17820 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
17821 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
17822 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
17823 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
17824 DAG.getIntPtrConstant(0));
17825 }
17827 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
17828 Subtarget->hasMMX() && "Unexpected custom BITCAST");
17829 assert((DstVT == MVT::i64 ||
17830 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
17831 "Unexpected custom BITCAST");
17832 // i64 <=> MMX conversions are Legal.
17833 if (SrcVT==MVT::i64 && DstVT.isVector())
17834 return Op;
17835 if (DstVT==MVT::i64 && SrcVT.isVector())
17836 return Op;
17837 // MMX <=> MMX conversions are Legal.
17838 if (SrcVT.isVector() && DstVT.isVector())
17839 return Op;
17840 // All other conversions need to be expanded.
17841 return SDValue();
17842 }
17844 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
17845 SDNode *Node = Op.getNode();
17846 SDLoc dl(Node);
17847 EVT T = Node->getValueType(0);
17848 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
17849 DAG.getConstant(0, T), Node->getOperand(2));
17850 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
17851 cast<AtomicSDNode>(Node)->getMemoryVT(),
17852 Node->getOperand(0),
17853 Node->getOperand(1), negOp,
17854 cast<AtomicSDNode>(Node)->getMemOperand(),
17855 cast<AtomicSDNode>(Node)->getOrdering(),
17856 cast<AtomicSDNode>(Node)->getSynchScope());
17857 }
17859 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
17860 SDNode *Node = Op.getNode();
17861 SDLoc dl(Node);
17862 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
17864 // Convert seq_cst store -> xchg
17865 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
17866 // FIXME: On 32-bit, store -> fist or movq would be more efficient
17867 // (The only way to get a 16-byte store is cmpxchg16b)
17868 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
17869 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
17870 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
17871 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
17872 cast<AtomicSDNode>(Node)->getMemoryVT(),
17873 Node->getOperand(0),
17874 Node->getOperand(1), Node->getOperand(2),
17875 cast<AtomicSDNode>(Node)->getMemOperand(),
17876 cast<AtomicSDNode>(Node)->getOrdering(),
17877 cast<AtomicSDNode>(Node)->getSynchScope());
17878 return Swap.getValue(1);
17879 }
17880 // Other atomic stores have a simple pattern.
17881 return Op;
17882 }
17884 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
17885 EVT VT = Op.getNode()->getSimpleValueType(0);
17887 // Let legalize expand this if it isn't a legal type yet.
17888 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
17889 return SDValue();
17891 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17893 unsigned Opc;
17894 bool ExtraOp = false;
17895 switch (Op.getOpcode()) {
17896 default: llvm_unreachable("Invalid code");
17897 case ISD::ADDC: Opc = X86ISD::ADD; break;
17898 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
17899 case ISD::SUBC: Opc = X86ISD::SUB; break;
17900 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
17901 }
17903 if (!ExtraOp)
17904 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17905 Op.getOperand(1));
17906 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17907 Op.getOperand(1), Op.getOperand(2));
17908 }
17910 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
17911 SelectionDAG &DAG) {
17912 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
17914 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
17915 // which returns the values as { float, float } (in XMM0) or
17916 // { double, double } (which is returned in XMM0, XMM1).
17917 SDLoc dl(Op);
17918 SDValue Arg = Op.getOperand(0);
17919 EVT ArgVT = Arg.getValueType();
17920 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17922 TargetLowering::ArgListTy Args;
17923 TargetLowering::ArgListEntry Entry;
17925 Entry.Node = Arg;
17926 Entry.Ty = ArgTy;
17927 Entry.isSExt = false;
17928 Entry.isZExt = false;
17929 Args.push_back(Entry);
17931 bool isF64 = ArgVT == MVT::f64;
17932 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
17933 // the small struct {f32, f32} is returned in (eax, edx). For f64,
17934 // the results are returned via SRet in memory.
17935 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
17936 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17937 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
17939 Type *RetTy = isF64
17940 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
17941 : (Type*)VectorType::get(ArgTy, 4);
17943 TargetLowering::CallLoweringInfo CLI(DAG);
17944 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
17945 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
17947 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
17949 if (isF64)
17950 // Returned in xmm0 and xmm1.
17951 return CallResult.first;
17953 // Returned in bits 0:31 and 32:64 xmm0.
17954 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17955 CallResult.first, DAG.getIntPtrConstant(0));
17956 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17957 CallResult.first, DAG.getIntPtrConstant(1));
17958 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
17959 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
17960 }
17962 /// LowerOperation - Provide custom lowering hooks for some operations.
17963 ///
17964 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
17965 switch (Op.getOpcode()) {
17966 default: llvm_unreachable("Should not custom lower this!");
17967 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
17968 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
17969 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
17970 return LowerCMP_SWAP(Op, Subtarget, DAG);
17971 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
17972 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
17973 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
17974 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
17975 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
17976 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
17977 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
17978 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
17979 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
17980 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
17981 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
17982 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
17983 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
17984 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
17985 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
17986 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
17987 case ISD::SHL_PARTS:
17988 case ISD::SRA_PARTS:
17989 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
17990 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
17991 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
17992 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
17993 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
17994 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
17995 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
17996 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
17997 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
17998 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
17999 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
18000 case ISD::FABS:
18001 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
18002 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
18003 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
18004 case ISD::SETCC: return LowerSETCC(Op, DAG);
18005 case ISD::SELECT: return LowerSELECT(Op, DAG);
18006 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
18007 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
18008 case ISD::VASTART: return LowerVASTART(Op, DAG);
18009 case ISD::VAARG: return LowerVAARG(Op, DAG);
18010 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
18011 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
18012 case ISD::INTRINSIC_VOID:
18013 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
18014 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
18015 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
18016 case ISD::FRAME_TO_ARGS_OFFSET:
18017 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
18018 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
18019 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
18020 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
18021 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
18022 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
18023 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
18024 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
18025 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
18026 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
18027 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
18028 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
18029 case ISD::UMUL_LOHI:
18030 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
18031 case ISD::SRA:
18032 case ISD::SRL:
18033 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
18034 case ISD::SADDO:
18035 case ISD::UADDO:
18036 case ISD::SSUBO:
18037 case ISD::USUBO:
18038 case ISD::SMULO:
18039 case ISD::UMULO: return LowerXALUO(Op, DAG);
18040 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
18041 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
18042 case ISD::ADDC:
18043 case ISD::ADDE:
18044 case ISD::SUBC:
18045 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
18046 case ISD::ADD: return LowerADD(Op, DAG);
18047 case ISD::SUB: return LowerSUB(Op, DAG);
18048 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
18049 }
18050 }
18052 /// ReplaceNodeResults - Replace a node with an illegal result type
18053 /// with a new node built out of custom code.
18054 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
18055 SmallVectorImpl<SDValue>&Results,
18056 SelectionDAG &DAG) const {
18057 SDLoc dl(N);
18058 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18059 switch (N->getOpcode()) {
18060 default:
18061 llvm_unreachable("Do not know how to custom type legalize this operation!");
18062 case ISD::SIGN_EXTEND_INREG:
18063 case ISD::ADDC:
18064 case ISD::ADDE:
18065 case ISD::SUBC:
18066 case ISD::SUBE:
18067 // We don't want to expand or promote these.
18068 return;
18069 case ISD::SDIV:
18070 case ISD::UDIV:
18071 case ISD::SREM:
18072 case ISD::UREM:
18073 case ISD::SDIVREM:
18074 case ISD::UDIVREM: {
18075 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
18076 Results.push_back(V);
18077 return;
18078 }
18079 case ISD::FP_TO_SINT:
18080 case ISD::FP_TO_UINT: {
18081 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
18083 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
18084 return;
18086 std::pair<SDValue,SDValue> Vals =
18087 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
18088 SDValue FIST = Vals.first, StackSlot = Vals.second;
18089 if (FIST.getNode()) {
18090 EVT VT = N->getValueType(0);
18091 // Return a load from the stack slot.
18092 if (StackSlot.getNode())
18093 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
18094 MachinePointerInfo(),
18095 false, false, false, 0));
18096 else
18097 Results.push_back(FIST);
18098 }
18099 return;
18100 }
18101 case ISD::UINT_TO_FP: {
18102 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18103 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
18104 N->getValueType(0) != MVT::v2f32)
18105 return;
18106 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
18107 N->getOperand(0));
18108 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
18109 MVT::f64);
18110 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
18111 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
18112 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
18113 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
18114 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
18115 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
18116 return;
18117 }
18118 case ISD::FP_ROUND: {
18119 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
18120 return;
18121 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
18122 Results.push_back(V);
18123 return;
18124 }
18125 case ISD::INTRINSIC_W_CHAIN: {
18126 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
18127 switch (IntNo) {
18128 default : llvm_unreachable("Do not know how to custom type "
18129 "legalize this intrinsic operation!");
18130 case Intrinsic::x86_rdtsc:
18131 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18132 Results);
18133 case Intrinsic::x86_rdtscp:
18134 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
18135 Results);
18136 case Intrinsic::x86_rdpmc:
18137 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
18138 }
18139 }
18140 case ISD::READCYCLECOUNTER: {
18141 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18142 Results);
18143 }
18144 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
18145 EVT T = N->getValueType(0);
18146 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
18147 bool Regs64bit = T == MVT::i128;
18148 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
18149 SDValue cpInL, cpInH;
18150 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18151 DAG.getConstant(0, HalfT));
18152 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18153 DAG.getConstant(1, HalfT));
18154 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
18155 Regs64bit ? X86::RAX : X86::EAX,
18156 cpInL, SDValue());
18157 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
18158 Regs64bit ? X86::RDX : X86::EDX,
18159 cpInH, cpInL.getValue(1));
18160 SDValue swapInL, swapInH;
18161 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18162 DAG.getConstant(0, HalfT));
18163 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18164 DAG.getConstant(1, HalfT));
18165 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
18166 Regs64bit ? X86::RBX : X86::EBX,
18167 swapInL, cpInH.getValue(1));
18168 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
18169 Regs64bit ? X86::RCX : X86::ECX,
18170 swapInH, swapInL.getValue(1));
18171 SDValue Ops[] = { swapInH.getValue(0),
18172 N->getOperand(1),
18173 swapInH.getValue(1) };
18174 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18175 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
18176 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
18177 X86ISD::LCMPXCHG8_DAG;
18178 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
18179 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
18180 Regs64bit ? X86::RAX : X86::EAX,
18181 HalfT, Result.getValue(1));
18182 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
18183 Regs64bit ? X86::RDX : X86::EDX,
18184 HalfT, cpOutL.getValue(2));
18185 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
18187 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
18188 MVT::i32, cpOutH.getValue(2));
18189 SDValue Success =
18190 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
18191 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
18192 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
18194 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
18195 Results.push_back(Success);
18196 Results.push_back(EFLAGS.getValue(1));
18197 return;
18198 }
18199 case ISD::ATOMIC_SWAP:
18200 case ISD::ATOMIC_LOAD_ADD:
18201 case ISD::ATOMIC_LOAD_SUB:
18202 case ISD::ATOMIC_LOAD_AND:
18203 case ISD::ATOMIC_LOAD_OR:
18204 case ISD::ATOMIC_LOAD_XOR:
18205 case ISD::ATOMIC_LOAD_NAND:
18206 case ISD::ATOMIC_LOAD_MIN:
18207 case ISD::ATOMIC_LOAD_MAX:
18208 case ISD::ATOMIC_LOAD_UMIN:
18209 case ISD::ATOMIC_LOAD_UMAX:
18210 case ISD::ATOMIC_LOAD: {
18211 // Delegate to generic TypeLegalization. Situations we can really handle
18212 // should have already been dealt with by AtomicExpandPass.cpp.
18213 break;
18214 }
18215 case ISD::BITCAST: {
18216 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18217 EVT DstVT = N->getValueType(0);
18218 EVT SrcVT = N->getOperand(0)->getValueType(0);
18220 if (SrcVT != MVT::f64 ||
18221 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
18222 return;
18224 unsigned NumElts = DstVT.getVectorNumElements();
18225 EVT SVT = DstVT.getVectorElementType();
18226 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18227 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
18228 MVT::v2f64, N->getOperand(0));
18229 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
18231 if (ExperimentalVectorWideningLegalization) {
18232 // If we are legalizing vectors by widening, we already have the desired
18233 // legal vector type, just return it.
18234 Results.push_back(ToVecInt);
18235 return;
18236 }
18238 SmallVector<SDValue, 8> Elts;
18239 for (unsigned i = 0, e = NumElts; i != e; ++i)
18240 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
18241 ToVecInt, DAG.getIntPtrConstant(i)));
18243 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
18244 }
18245 }
18246 }
18248 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
18249 switch (Opcode) {
18250 default: return nullptr;
18251 case X86ISD::BSF: return "X86ISD::BSF";
18252 case X86ISD::BSR: return "X86ISD::BSR";
18253 case X86ISD::SHLD: return "X86ISD::SHLD";
18254 case X86ISD::SHRD: return "X86ISD::SHRD";
18255 case X86ISD::FAND: return "X86ISD::FAND";
18256 case X86ISD::FANDN: return "X86ISD::FANDN";
18257 case X86ISD::FOR: return "X86ISD::FOR";
18258 case X86ISD::FXOR: return "X86ISD::FXOR";
18259 case X86ISD::FSRL: return "X86ISD::FSRL";
18260 case X86ISD::FILD: return "X86ISD::FILD";
18261 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
18262 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
18263 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
18264 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
18265 case X86ISD::FLD: return "X86ISD::FLD";
18266 case X86ISD::FST: return "X86ISD::FST";
18267 case X86ISD::CALL: return "X86ISD::CALL";
18268 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
18269 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
18270 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
18271 case X86ISD::BT: return "X86ISD::BT";
18272 case X86ISD::CMP: return "X86ISD::CMP";
18273 case X86ISD::COMI: return "X86ISD::COMI";
18274 case X86ISD::UCOMI: return "X86ISD::UCOMI";
18275 case X86ISD::CMPM: return "X86ISD::CMPM";
18276 case X86ISD::CMPMU: return "X86ISD::CMPMU";
18277 case X86ISD::SETCC: return "X86ISD::SETCC";
18278 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
18279 case X86ISD::FSETCC: return "X86ISD::FSETCC";
18280 case X86ISD::CMOV: return "X86ISD::CMOV";
18281 case X86ISD::BRCOND: return "X86ISD::BRCOND";
18282 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
18283 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
18284 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
18285 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
18286 case X86ISD::Wrapper: return "X86ISD::Wrapper";
18287 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
18288 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
18289 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
18290 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
18291 case X86ISD::PINSRB: return "X86ISD::PINSRB";
18292 case X86ISD::PINSRW: return "X86ISD::PINSRW";
18293 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
18294 case X86ISD::ANDNP: return "X86ISD::ANDNP";
18295 case X86ISD::PSIGN: return "X86ISD::PSIGN";
18296 case X86ISD::BLENDV: return "X86ISD::BLENDV";
18297 case X86ISD::BLENDI: return "X86ISD::BLENDI";
18298 case X86ISD::SUBUS: return "X86ISD::SUBUS";
18299 case X86ISD::HADD: return "X86ISD::HADD";
18300 case X86ISD::HSUB: return "X86ISD::HSUB";
18301 case X86ISD::FHADD: return "X86ISD::FHADD";
18302 case X86ISD::FHSUB: return "X86ISD::FHSUB";
18303 case X86ISD::UMAX: return "X86ISD::UMAX";
18304 case X86ISD::UMIN: return "X86ISD::UMIN";
18305 case X86ISD::SMAX: return "X86ISD::SMAX";
18306 case X86ISD::SMIN: return "X86ISD::SMIN";
18307 case X86ISD::FMAX: return "X86ISD::FMAX";
18308 case X86ISD::FMIN: return "X86ISD::FMIN";
18309 case X86ISD::FMAXC: return "X86ISD::FMAXC";
18310 case X86ISD::FMINC: return "X86ISD::FMINC";
18311 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
18312 case X86ISD::FRCP: return "X86ISD::FRCP";
18313 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
18314 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
18315 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
18316 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
18317 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
18318 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
18319 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
18320 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
18321 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
18322 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
18323 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
18324 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
18325 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
18326 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
18327 case X86ISD::VZEXT: return "X86ISD::VZEXT";
18328 case X86ISD::VSEXT: return "X86ISD::VSEXT";
18329 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
18330 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
18331 case X86ISD::VINSERT: return "X86ISD::VINSERT";
18332 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
18333 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
18334 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
18335 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
18336 case X86ISD::VSHL: return "X86ISD::VSHL";
18337 case X86ISD::VSRL: return "X86ISD::VSRL";
18338 case X86ISD::VSRA: return "X86ISD::VSRA";
18339 case X86ISD::VSHLI: return "X86ISD::VSHLI";
18340 case X86ISD::VSRLI: return "X86ISD::VSRLI";
18341 case X86ISD::VSRAI: return "X86ISD::VSRAI";
18342 case X86ISD::CMPP: return "X86ISD::CMPP";
18343 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
18344 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
18345 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
18346 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
18347 case X86ISD::ADD: return "X86ISD::ADD";
18348 case X86ISD::SUB: return "X86ISD::SUB";
18349 case X86ISD::ADC: return "X86ISD::ADC";
18350 case X86ISD::SBB: return "X86ISD::SBB";
18351 case X86ISD::SMUL: return "X86ISD::SMUL";
18352 case X86ISD::UMUL: return "X86ISD::UMUL";
18353 case X86ISD::INC: return "X86ISD::INC";
18354 case X86ISD::DEC: return "X86ISD::DEC";
18355 case X86ISD::OR: return "X86ISD::OR";
18356 case X86ISD::XOR: return "X86ISD::XOR";
18357 case X86ISD::AND: return "X86ISD::AND";
18358 case X86ISD::BEXTR: return "X86ISD::BEXTR";
18359 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
18360 case X86ISD::PTEST: return "X86ISD::PTEST";
18361 case X86ISD::TESTP: return "X86ISD::TESTP";
18362 case X86ISD::TESTM: return "X86ISD::TESTM";
18363 case X86ISD::TESTNM: return "X86ISD::TESTNM";
18364 case X86ISD::KORTEST: return "X86ISD::KORTEST";
18365 case X86ISD::PACKSS: return "X86ISD::PACKSS";
18366 case X86ISD::PACKUS: return "X86ISD::PACKUS";
18367 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
18368 case X86ISD::VALIGN: return "X86ISD::VALIGN";
18369 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
18370 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
18371 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
18372 case X86ISD::SHUFP: return "X86ISD::SHUFP";
18373 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
18374 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
18375 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
18376 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
18377 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
18378 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
18379 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
18380 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
18381 case X86ISD::MOVSD: return "X86ISD::MOVSD";
18382 case X86ISD::MOVSS: return "X86ISD::MOVSS";
18383 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
18384 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
18385 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
18386 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
18387 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
18388 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
18389 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
18390 case X86ISD::VPERMV: return "X86ISD::VPERMV";
18391 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
18392 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
18393 case X86ISD::VPERMI: return "X86ISD::VPERMI";
18394 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
18395 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
18396 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
18397 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
18398 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
18399 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
18400 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
18401 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
18402 case X86ISD::SAHF: return "X86ISD::SAHF";
18403 case X86ISD::RDRAND: return "X86ISD::RDRAND";
18404 case X86ISD::RDSEED: return "X86ISD::RDSEED";
18405 case X86ISD::FMADD: return "X86ISD::FMADD";
18406 case X86ISD::FMSUB: return "X86ISD::FMSUB";
18407 case X86ISD::FNMADD: return "X86ISD::FNMADD";
18408 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
18409 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
18410 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
18411 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
18412 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
18413 case X86ISD::XTEST: return "X86ISD::XTEST";
18414 }
18415 }
18417 // isLegalAddressingMode - Return true if the addressing mode represented
18418 // by AM is legal for this target, for a load/store of the specified type.
18419 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
18420 Type *Ty) const {
18421 // X86 supports extremely general addressing modes.
18422 CodeModel::Model M = getTargetMachine().getCodeModel();
18423 Reloc::Model R = getTargetMachine().getRelocationModel();
18425 // X86 allows a sign-extended 32-bit immediate field as a displacement.
18426 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
18427 return false;
18429 if (AM.BaseGV) {
18430 unsigned GVFlags =
18431 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
18433 // If a reference to this global requires an extra load, we can't fold it.
18434 if (isGlobalStubReference(GVFlags))
18435 return false;
18437 // If BaseGV requires a register for the PIC base, we cannot also have a
18438 // BaseReg specified.
18439 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
18440 return false;
18442 // If lower 4G is not available, then we must use rip-relative addressing.
18443 if ((M != CodeModel::Small || R != Reloc::Static) &&
18444 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
18445 return false;
18446 }
18448 switch (AM.Scale) {
18449 case 0:
18450 case 1:
18451 case 2:
18452 case 4:
18453 case 8:
18454 // These scales always work.
18455 break;
18456 case 3:
18457 case 5:
18458 case 9:
18459 // These scales are formed with basereg+scalereg. Only accept if there is
18460 // no basereg yet.
18461 if (AM.HasBaseReg)
18462 return false;
18463 break;
18464 default: // Other stuff never works.
18465 return false;
18466 }
18468 return true;
18469 }
18471 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
18472 unsigned Bits = Ty->getScalarSizeInBits();
18474 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
18475 // particularly cheaper than those without.
18476 if (Bits == 8)
18477 return false;
18479 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
18480 // variable shifts just as cheap as scalar ones.
18481 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
18482 return false;
18484 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
18485 // fully general vector.
18486 return true;
18487 }
18489 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
18490 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18491 return false;
18492 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
18493 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
18494 return NumBits1 > NumBits2;
18495 }
18497 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
18498 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18499 return false;
18501 if (!isTypeLegal(EVT::getEVT(Ty1)))
18502 return false;
18504 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
18506 // Assuming the caller doesn't have a zeroext or signext return parameter,
18507 // truncation all the way down to i1 is valid.
18508 return true;
18509 }
18511 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
18512 return isInt<32>(Imm);
18513 }
18515 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
18516 // Can also use sub to handle negated immediates.
18517 return isInt<32>(Imm);
18518 }
18520 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
18521 if (!VT1.isInteger() || !VT2.isInteger())
18522 return false;
18523 unsigned NumBits1 = VT1.getSizeInBits();
18524 unsigned NumBits2 = VT2.getSizeInBits();
18525 return NumBits1 > NumBits2;
18526 }
18528 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
18529 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18530 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
18531 }
18533 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
18534 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18535 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
18536 }
18538 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
18539 EVT VT1 = Val.getValueType();
18540 if (isZExtFree(VT1, VT2))
18541 return true;
18543 if (Val.getOpcode() != ISD::LOAD)
18544 return false;
18546 if (!VT1.isSimple() || !VT1.isInteger() ||
18547 !VT2.isSimple() || !VT2.isInteger())
18548 return false;
18550 switch (VT1.getSimpleVT().SimpleTy) {
18551 default: break;
18552 case MVT::i8:
18553 case MVT::i16:
18554 case MVT::i32:
18555 // X86 has 8, 16, and 32-bit zero-extending loads.
18556 return true;
18557 }
18559 return false;
18560 }
18562 bool
18563 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
18564 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
18565 return false;
18567 VT = VT.getScalarType();
18569 if (!VT.isSimple())
18570 return false;
18572 switch (VT.getSimpleVT().SimpleTy) {
18573 case MVT::f32:
18574 case MVT::f64:
18575 return true;
18576 default:
18577 break;
18578 }
18580 return false;
18581 }
18583 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
18584 // i16 instructions are longer (0x66 prefix) and potentially slower.
18585 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
18586 }
18588 /// isShuffleMaskLegal - Targets can use this to indicate that they only
18589 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
18590 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
18591 /// are assumed to be legal.
18592 bool
18593 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
18594 EVT VT) const {
18595 if (!VT.isSimple())
18596 return false;
18598 MVT SVT = VT.getSimpleVT();
18600 // Very little shuffling can be done for 64-bit vectors right now.
18601 if (VT.getSizeInBits() == 64)
18602 return false;
18604 // If this is a single-input shuffle with no 128 bit lane crossings we can
18605 // lower it into pshufb.
18606 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
18607 (SVT.is256BitVector() && Subtarget->hasInt256())) {
18608 bool isLegal = true;
18609 for (unsigned I = 0, E = M.size(); I != E; ++I) {
18610 if (M[I] >= (int)SVT.getVectorNumElements() ||
18611 ShuffleCrosses128bitLane(SVT, I, M[I])) {
18612 isLegal = false;
18613 break;
18614 }
18615 }
18616 if (isLegal)
18617 return true;
18618 }
18620 // FIXME: blends, shifts.
18621 return (SVT.getVectorNumElements() == 2 ||
18622 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
18623 isMOVLMask(M, SVT) ||
18624 isMOVHLPSMask(M, SVT) ||
18625 isSHUFPMask(M, SVT) ||
18626 isPSHUFDMask(M, SVT) ||
18627 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
18628 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
18629 isPALIGNRMask(M, SVT, Subtarget) ||
18630 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
18631 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
18632 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
18633 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
18634 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()));
18635 }
18637 bool
18638 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
18639 EVT VT) const {
18640 if (!VT.isSimple())
18641 return false;
18643 MVT SVT = VT.getSimpleVT();
18644 unsigned NumElts = SVT.getVectorNumElements();
18645 // FIXME: This collection of masks seems suspect.
18646 if (NumElts == 2)
18647 return true;
18648 if (NumElts == 4 && SVT.is128BitVector()) {
18649 return (isMOVLMask(Mask, SVT) ||
18650 isCommutedMOVLMask(Mask, SVT, true) ||
18651 isSHUFPMask(Mask, SVT) ||
18652 isSHUFPMask(Mask, SVT, /* Commuted */ true));
18653 }
18654 return false;
18655 }
18657 //===----------------------------------------------------------------------===//
18658 // X86 Scheduler Hooks
18659 //===----------------------------------------------------------------------===//
18661 /// Utility function to emit xbegin specifying the start of an RTM region.
18662 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
18663 const TargetInstrInfo *TII) {
18664 DebugLoc DL = MI->getDebugLoc();
18666 const BasicBlock *BB = MBB->getBasicBlock();
18667 MachineFunction::iterator I = MBB;
18668 ++I;
18670 // For the v = xbegin(), we generate
18671 //
18672 // thisMBB:
18673 // xbegin sinkMBB
18674 //
18675 // mainMBB:
18676 // eax = -1
18677 //
18678 // sinkMBB:
18679 // v = eax
18681 MachineBasicBlock *thisMBB = MBB;
18682 MachineFunction *MF = MBB->getParent();
18683 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
18684 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
18685 MF->insert(I, mainMBB);
18686 MF->insert(I, sinkMBB);
18688 // Transfer the remainder of BB and its successor edges to sinkMBB.
18689 sinkMBB->splice(sinkMBB->begin(), MBB,
18690 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18691 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
18693 // thisMBB:
18694 // xbegin sinkMBB
18695 // # fallthrough to mainMBB
18696 // # abortion to sinkMBB
18697 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
18698 thisMBB->addSuccessor(mainMBB);
18699 thisMBB->addSuccessor(sinkMBB);
18701 // mainMBB:
18702 // EAX = -1
18703 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
18704 mainMBB->addSuccessor(sinkMBB);
18706 // sinkMBB:
18707 // EAX is live into the sinkMBB
18708 sinkMBB->addLiveIn(X86::EAX);
18709 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
18710 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18711 .addReg(X86::EAX);
18713 MI->eraseFromParent();
18714 return sinkMBB;
18715 }
18717 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
18718 // or XMM0_V32I8 in AVX all of this code can be replaced with that
18719 // in the .td file.
18720 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
18721 const TargetInstrInfo *TII) {
18722 unsigned Opc;
18723 switch (MI->getOpcode()) {
18724 default: llvm_unreachable("illegal opcode!");
18725 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
18726 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
18727 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
18728 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
18729 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
18730 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
18731 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
18732 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
18733 }
18735 DebugLoc dl = MI->getDebugLoc();
18736 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
18738 unsigned NumArgs = MI->getNumOperands();
18739 for (unsigned i = 1; i < NumArgs; ++i) {
18740 MachineOperand &Op = MI->getOperand(i);
18741 if (!(Op.isReg() && Op.isImplicit()))
18742 MIB.addOperand(Op);
18743 }
18744 if (MI->hasOneMemOperand())
18745 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
18747 BuildMI(*BB, MI, dl,
18748 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18749 .addReg(X86::XMM0);
18751 MI->eraseFromParent();
18752 return BB;
18753 }
18755 // FIXME: Custom handling because TableGen doesn't support multiple implicit
18756 // defs in an instruction pattern
18757 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
18758 const TargetInstrInfo *TII) {
18759 unsigned Opc;
18760 switch (MI->getOpcode()) {
18761 default: llvm_unreachable("illegal opcode!");
18762 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
18763 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
18764 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
18765 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
18766 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
18767 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
18768 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
18769 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
18770 }
18772 DebugLoc dl = MI->getDebugLoc();
18773 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
18775 unsigned NumArgs = MI->getNumOperands(); // remove the results
18776 for (unsigned i = 1; i < NumArgs; ++i) {
18777 MachineOperand &Op = MI->getOperand(i);
18778 if (!(Op.isReg() && Op.isImplicit()))
18779 MIB.addOperand(Op);
18780 }
18781 if (MI->hasOneMemOperand())
18782 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
18784 BuildMI(*BB, MI, dl,
18785 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18786 .addReg(X86::ECX);
18788 MI->eraseFromParent();
18789 return BB;
18790 }
18792 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
18793 const TargetInstrInfo *TII,
18794 const X86Subtarget* Subtarget) {
18795 DebugLoc dl = MI->getDebugLoc();
18797 // Address into RAX/EAX, other two args into ECX, EDX.
18798 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
18799 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
18800 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
18801 for (int i = 0; i < X86::AddrNumOperands; ++i)
18802 MIB.addOperand(MI->getOperand(i));
18804 unsigned ValOps = X86::AddrNumOperands;
18805 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
18806 .addReg(MI->getOperand(ValOps).getReg());
18807 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
18808 .addReg(MI->getOperand(ValOps+1).getReg());
18810 // The instruction doesn't actually take any operands though.
18811 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
18813 MI->eraseFromParent(); // The pseudo is gone now.
18814 return BB;
18815 }
18817 MachineBasicBlock *
18818 X86TargetLowering::EmitVAARG64WithCustomInserter(
18819 MachineInstr *MI,
18820 MachineBasicBlock *MBB) const {
18821 // Emit va_arg instruction on X86-64.
18823 // Operands to this pseudo-instruction:
18824 // 0 ) Output : destination address (reg)
18825 // 1-5) Input : va_list address (addr, i64mem)
18826 // 6 ) ArgSize : Size (in bytes) of vararg type
18827 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
18828 // 8 ) Align : Alignment of type
18829 // 9 ) EFLAGS (implicit-def)
18831 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
18832 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
18834 unsigned DestReg = MI->getOperand(0).getReg();
18835 MachineOperand &Base = MI->getOperand(1);
18836 MachineOperand &Scale = MI->getOperand(2);
18837 MachineOperand &Index = MI->getOperand(3);
18838 MachineOperand &Disp = MI->getOperand(4);
18839 MachineOperand &Segment = MI->getOperand(5);
18840 unsigned ArgSize = MI->getOperand(6).getImm();
18841 unsigned ArgMode = MI->getOperand(7).getImm();
18842 unsigned Align = MI->getOperand(8).getImm();
18844 // Memory Reference
18845 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
18846 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18847 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18849 // Machine Information
18850 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
18851 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
18852 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
18853 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
18854 DebugLoc DL = MI->getDebugLoc();
18856 // struct va_list {
18857 // i32 gp_offset
18858 // i32 fp_offset
18859 // i64 overflow_area (address)
18860 // i64 reg_save_area (address)
18861 // }
18862 // sizeof(va_list) = 24
18863 // alignment(va_list) = 8
18865 unsigned TotalNumIntRegs = 6;
18866 unsigned TotalNumXMMRegs = 8;
18867 bool UseGPOffset = (ArgMode == 1);
18868 bool UseFPOffset = (ArgMode == 2);
18869 unsigned MaxOffset = TotalNumIntRegs * 8 +
18870 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
18872 /* Align ArgSize to a multiple of 8 */
18873 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
18874 bool NeedsAlign = (Align > 8);
18876 MachineBasicBlock *thisMBB = MBB;
18877 MachineBasicBlock *overflowMBB;
18878 MachineBasicBlock *offsetMBB;
18879 MachineBasicBlock *endMBB;
18881 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
18882 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
18883 unsigned OffsetReg = 0;
18885 if (!UseGPOffset && !UseFPOffset) {
18886 // If we only pull from the overflow region, we don't create a branch.
18887 // We don't need to alter control flow.
18888 OffsetDestReg = 0; // unused
18889 OverflowDestReg = DestReg;
18891 offsetMBB = nullptr;
18892 overflowMBB = thisMBB;
18893 endMBB = thisMBB;
18894 } else {
18895 // First emit code to check if gp_offset (or fp_offset) is below the bound.
18896 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
18897 // If not, pull from overflow_area. (branch to overflowMBB)
18898 //
18899 // thisMBB
18900 // | .
18901 // | .
18902 // offsetMBB overflowMBB
18903 // | .
18904 // | .
18905 // endMBB
18907 // Registers for the PHI in endMBB
18908 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
18909 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
18911 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
18912 MachineFunction *MF = MBB->getParent();
18913 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18914 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18915 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18917 MachineFunction::iterator MBBIter = MBB;
18918 ++MBBIter;
18920 // Insert the new basic blocks
18921 MF->insert(MBBIter, offsetMBB);
18922 MF->insert(MBBIter, overflowMBB);
18923 MF->insert(MBBIter, endMBB);
18925 // Transfer the remainder of MBB and its successor edges to endMBB.
18926 endMBB->splice(endMBB->begin(), thisMBB,
18927 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
18928 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
18930 // Make offsetMBB and overflowMBB successors of thisMBB
18931 thisMBB->addSuccessor(offsetMBB);
18932 thisMBB->addSuccessor(overflowMBB);
18934 // endMBB is a successor of both offsetMBB and overflowMBB
18935 offsetMBB->addSuccessor(endMBB);
18936 overflowMBB->addSuccessor(endMBB);
18938 // Load the offset value into a register
18939 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
18940 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
18941 .addOperand(Base)
18942 .addOperand(Scale)
18943 .addOperand(Index)
18944 .addDisp(Disp, UseFPOffset ? 4 : 0)
18945 .addOperand(Segment)
18946 .setMemRefs(MMOBegin, MMOEnd);
18948 // Check if there is enough room left to pull this argument.
18949 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
18950 .addReg(OffsetReg)
18951 .addImm(MaxOffset + 8 - ArgSizeA8);
18953 // Branch to "overflowMBB" if offset >= max
18954 // Fall through to "offsetMBB" otherwise
18955 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
18956 .addMBB(overflowMBB);
18957 }
18959 // In offsetMBB, emit code to use the reg_save_area.
18960 if (offsetMBB) {
18961 assert(OffsetReg != 0);
18963 // Read the reg_save_area address.
18964 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
18965 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
18966 .addOperand(Base)
18967 .addOperand(Scale)
18968 .addOperand(Index)
18969 .addDisp(Disp, 16)
18970 .addOperand(Segment)
18971 .setMemRefs(MMOBegin, MMOEnd);
18973 // Zero-extend the offset
18974 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
18975 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
18976 .addImm(0)
18977 .addReg(OffsetReg)
18978 .addImm(X86::sub_32bit);
18980 // Add the offset to the reg_save_area to get the final address.
18981 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
18982 .addReg(OffsetReg64)
18983 .addReg(RegSaveReg);
18985 // Compute the offset for the next argument
18986 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
18987 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
18988 .addReg(OffsetReg)
18989 .addImm(UseFPOffset ? 16 : 8);
18991 // Store it back into the va_list.
18992 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
18993 .addOperand(Base)
18994 .addOperand(Scale)
18995 .addOperand(Index)
18996 .addDisp(Disp, UseFPOffset ? 4 : 0)
18997 .addOperand(Segment)
18998 .addReg(NextOffsetReg)
18999 .setMemRefs(MMOBegin, MMOEnd);
19001 // Jump to endMBB
19002 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
19003 .addMBB(endMBB);
19004 }
19006 //
19007 // Emit code to use overflow area
19008 //
19010 // Load the overflow_area address into a register.
19011 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
19012 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
19013 .addOperand(Base)
19014 .addOperand(Scale)
19015 .addOperand(Index)
19016 .addDisp(Disp, 8)
19017 .addOperand(Segment)
19018 .setMemRefs(MMOBegin, MMOEnd);
19020 // If we need to align it, do so. Otherwise, just copy the address
19021 // to OverflowDestReg.
19022 if (NeedsAlign) {
19023 // Align the overflow address
19024 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
19025 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
19027 // aligned_addr = (addr + (align-1)) & ~(align-1)
19028 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
19029 .addReg(OverflowAddrReg)
19030 .addImm(Align-1);
19032 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
19033 .addReg(TmpReg)
19034 .addImm(~(uint64_t)(Align-1));
19035 } else {
19036 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
19037 .addReg(OverflowAddrReg);
19038 }
19040 // Compute the next overflow address after this argument.
19041 // (the overflow address should be kept 8-byte aligned)
19042 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
19043 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
19044 .addReg(OverflowDestReg)
19045 .addImm(ArgSizeA8);
19047 // Store the new overflow address.
19048 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
19049 .addOperand(Base)
19050 .addOperand(Scale)
19051 .addOperand(Index)
19052 .addDisp(Disp, 8)
19053 .addOperand(Segment)
19054 .addReg(NextAddrReg)
19055 .setMemRefs(MMOBegin, MMOEnd);
19057 // If we branched, emit the PHI to the front of endMBB.
19058 if (offsetMBB) {
19059 BuildMI(*endMBB, endMBB->begin(), DL,
19060 TII->get(X86::PHI), DestReg)
19061 .addReg(OffsetDestReg).addMBB(offsetMBB)
19062 .addReg(OverflowDestReg).addMBB(overflowMBB);
19063 }
19065 // Erase the pseudo instruction
19066 MI->eraseFromParent();
19068 return endMBB;
19069 }
19071 MachineBasicBlock *
19072 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
19073 MachineInstr *MI,
19074 MachineBasicBlock *MBB) const {
19075 // Emit code to save XMM registers to the stack. The ABI says that the
19076 // number of registers to save is given in %al, so it's theoretically
19077 // possible to do an indirect jump trick to avoid saving all of them,
19078 // however this code takes a simpler approach and just executes all
19079 // of the stores if %al is non-zero. It's less code, and it's probably
19080 // easier on the hardware branch predictor, and stores aren't all that
19081 // expensive anyway.
19083 // Create the new basic blocks. One block contains all the XMM stores,
19084 // and one block is the final destination regardless of whether any
19085 // stores were performed.
19086 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
19087 MachineFunction *F = MBB->getParent();
19088 MachineFunction::iterator MBBIter = MBB;
19089 ++MBBIter;
19090 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
19091 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
19092 F->insert(MBBIter, XMMSaveMBB);
19093 F->insert(MBBIter, EndMBB);
19095 // Transfer the remainder of MBB and its successor edges to EndMBB.
19096 EndMBB->splice(EndMBB->begin(), MBB,
19097 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19098 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
19100 // The original block will now fall through to the XMM save block.
19101 MBB->addSuccessor(XMMSaveMBB);
19102 // The XMMSaveMBB will fall through to the end block.
19103 XMMSaveMBB->addSuccessor(EndMBB);
19105 // Now add the instructions.
19106 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
19107 DebugLoc DL = MI->getDebugLoc();
19109 unsigned CountReg = MI->getOperand(0).getReg();
19110 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
19111 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
19113 if (!Subtarget->isTargetWin64()) {
19114 // If %al is 0, branch around the XMM save block.
19115 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
19116 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
19117 MBB->addSuccessor(EndMBB);
19118 }
19120 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
19121 // that was just emitted, but clearly shouldn't be "saved".
19122 assert((MI->getNumOperands() <= 3 ||
19123 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
19124 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
19125 && "Expected last argument to be EFLAGS");
19126 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
19127 // In the XMM save block, save all the XMM argument registers.
19128 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
19129 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
19130 MachineMemOperand *MMO =
19131 F->getMachineMemOperand(
19132 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
19133 MachineMemOperand::MOStore,
19134 /*Size=*/16, /*Align=*/16);
19135 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
19136 .addFrameIndex(RegSaveFrameIndex)
19137 .addImm(/*Scale=*/1)
19138 .addReg(/*IndexReg=*/0)
19139 .addImm(/*Disp=*/Offset)
19140 .addReg(/*Segment=*/0)
19141 .addReg(MI->getOperand(i).getReg())
19142 .addMemOperand(MMO);
19143 }
19145 MI->eraseFromParent(); // The pseudo instruction is gone now.
19147 return EndMBB;
19148 }
19150 // The EFLAGS operand of SelectItr might be missing a kill marker
19151 // because there were multiple uses of EFLAGS, and ISel didn't know
19152 // which to mark. Figure out whether SelectItr should have had a
19153 // kill marker, and set it if it should. Returns the correct kill
19154 // marker value.
19155 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
19156 MachineBasicBlock* BB,
19157 const TargetRegisterInfo* TRI) {
19158 // Scan forward through BB for a use/def of EFLAGS.
19159 MachineBasicBlock::iterator miI(std::next(SelectItr));
19160 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
19161 const MachineInstr& mi = *miI;
19162 if (mi.readsRegister(X86::EFLAGS))
19163 return false;
19164 if (mi.definesRegister(X86::EFLAGS))
19165 break; // Should have kill-flag - update below.
19166 }
19168 // If we hit the end of the block, check whether EFLAGS is live into a
19169 // successor.
19170 if (miI == BB->end()) {
19171 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
19172 sEnd = BB->succ_end();
19173 sItr != sEnd; ++sItr) {
19174 MachineBasicBlock* succ = *sItr;
19175 if (succ->isLiveIn(X86::EFLAGS))
19176 return false;
19177 }
19178 }
19180 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
19181 // out. SelectMI should have a kill flag on EFLAGS.
19182 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
19183 return true;
19184 }
19186 MachineBasicBlock *
19187 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
19188 MachineBasicBlock *BB) const {
19189 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
19190 DebugLoc DL = MI->getDebugLoc();
19192 // To "insert" a SELECT_CC instruction, we actually have to insert the
19193 // diamond control-flow pattern. The incoming instruction knows the
19194 // destination vreg to set, the condition code register to branch on, the
19195 // true/false values to select between, and a branch opcode to use.
19196 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19197 MachineFunction::iterator It = BB;
19198 ++It;
19200 // thisMBB:
19201 // ...
19202 // TrueVal = ...
19203 // cmpTY ccX, r1, r2
19204 // bCC copy1MBB
19205 // fallthrough --> copy0MBB
19206 MachineBasicBlock *thisMBB = BB;
19207 MachineFunction *F = BB->getParent();
19208 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
19209 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
19210 F->insert(It, copy0MBB);
19211 F->insert(It, sinkMBB);
19213 // If the EFLAGS register isn't dead in the terminator, then claim that it's
19214 // live into the sink and copy blocks.
19215 const TargetRegisterInfo *TRI =
19216 BB->getParent()->getSubtarget().getRegisterInfo();
19217 if (!MI->killsRegister(X86::EFLAGS) &&
19218 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
19219 copy0MBB->addLiveIn(X86::EFLAGS);
19220 sinkMBB->addLiveIn(X86::EFLAGS);
19221 }
19223 // Transfer the remainder of BB and its successor edges to sinkMBB.
19224 sinkMBB->splice(sinkMBB->begin(), BB,
19225 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19226 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
19228 // Add the true and fallthrough blocks as its successors.
19229 BB->addSuccessor(copy0MBB);
19230 BB->addSuccessor(sinkMBB);
19232 // Create the conditional branch instruction.
19233 unsigned Opc =
19234 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
19235 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
19237 // copy0MBB:
19238 // %FalseValue = ...
19239 // # fallthrough to sinkMBB
19240 copy0MBB->addSuccessor(sinkMBB);
19242 // sinkMBB:
19243 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
19244 // ...
19245 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19246 TII->get(X86::PHI), MI->getOperand(0).getReg())
19247 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
19248 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
19250 MI->eraseFromParent(); // The pseudo instruction is gone now.
19251 return sinkMBB;
19252 }
19254 MachineBasicBlock *
19255 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
19256 MachineBasicBlock *BB) const {
19257 MachineFunction *MF = BB->getParent();
19258 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
19259 DebugLoc DL = MI->getDebugLoc();
19260 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19262 assert(MF->shouldSplitStack());
19264 const bool Is64Bit = Subtarget->is64Bit();
19265 const bool IsLP64 = Subtarget->isTarget64BitLP64();
19267 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
19268 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
19270 // BB:
19271 // ... [Till the alloca]
19272 // If stacklet is not large enough, jump to mallocMBB
19273 //
19274 // bumpMBB:
19275 // Allocate by subtracting from RSP
19276 // Jump to continueMBB
19277 //
19278 // mallocMBB:
19279 // Allocate by call to runtime
19280 //
19281 // continueMBB:
19282 // ...
19283 // [rest of original BB]
19284 //
19286 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19287 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19288 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19290 MachineRegisterInfo &MRI = MF->getRegInfo();
19291 const TargetRegisterClass *AddrRegClass =
19292 getRegClassFor(getPointerTy());
19294 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19295 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19296 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
19297 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
19298 sizeVReg = MI->getOperand(1).getReg(),
19299 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
19301 MachineFunction::iterator MBBIter = BB;
19302 ++MBBIter;
19304 MF->insert(MBBIter, bumpMBB);
19305 MF->insert(MBBIter, mallocMBB);
19306 MF->insert(MBBIter, continueMBB);
19308 continueMBB->splice(continueMBB->begin(), BB,
19309 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19310 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
19312 // Add code to the main basic block to check if the stack limit has been hit,
19313 // and if so, jump to mallocMBB otherwise to bumpMBB.
19314 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
19315 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
19316 .addReg(tmpSPVReg).addReg(sizeVReg);
19317 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
19318 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
19319 .addReg(SPLimitVReg);
19320 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
19322 // bumpMBB simply decreases the stack pointer, since we know the current
19323 // stacklet has enough space.
19324 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
19325 .addReg(SPLimitVReg);
19326 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
19327 .addReg(SPLimitVReg);
19328 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
19330 // Calls into a routine in libgcc to allocate more space from the heap.
19331 const uint32_t *RegMask = MF->getTarget()
19332 .getSubtargetImpl()
19333 ->getRegisterInfo()
19334 ->getCallPreservedMask(CallingConv::C);
19335 if (IsLP64) {
19336 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
19337 .addReg(sizeVReg);
19338 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19339 .addExternalSymbol("__morestack_allocate_stack_space")
19340 .addRegMask(RegMask)
19341 .addReg(X86::RDI, RegState::Implicit)
19342 .addReg(X86::RAX, RegState::ImplicitDefine);
19343 } else if (Is64Bit) {
19344 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
19345 .addReg(sizeVReg);
19346 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19347 .addExternalSymbol("__morestack_allocate_stack_space")
19348 .addRegMask(RegMask)
19349 .addReg(X86::EDI, RegState::Implicit)
19350 .addReg(X86::EAX, RegState::ImplicitDefine);
19351 } else {
19352 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
19353 .addImm(12);
19354 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
19355 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
19356 .addExternalSymbol("__morestack_allocate_stack_space")
19357 .addRegMask(RegMask)
19358 .addReg(X86::EAX, RegState::ImplicitDefine);
19359 }
19361 if (!Is64Bit)
19362 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
19363 .addImm(16);
19365 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
19366 .addReg(IsLP64 ? X86::RAX : X86::EAX);
19367 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
19369 // Set up the CFG correctly.
19370 BB->addSuccessor(bumpMBB);
19371 BB->addSuccessor(mallocMBB);
19372 mallocMBB->addSuccessor(continueMBB);
19373 bumpMBB->addSuccessor(continueMBB);
19375 // Take care of the PHI nodes.
19376 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
19377 MI->getOperand(0).getReg())
19378 .addReg(mallocPtrVReg).addMBB(mallocMBB)
19379 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
19381 // Delete the original pseudo instruction.
19382 MI->eraseFromParent();
19384 // And we're done.
19385 return continueMBB;
19386 }
19388 MachineBasicBlock *
19389 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
19390 MachineBasicBlock *BB) const {
19391 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
19392 DebugLoc DL = MI->getDebugLoc();
19394 assert(!Subtarget->isTargetMacho());
19396 // The lowering is pretty easy: we're just emitting the call to _alloca. The
19397 // non-trivial part is impdef of ESP.
19399 if (Subtarget->isTargetWin64()) {
19400 if (Subtarget->isTargetCygMing()) {
19401 // ___chkstk(Mingw64):
19402 // Clobbers R10, R11, RAX and EFLAGS.
19403 // Updates RSP.
19404 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
19405 .addExternalSymbol("___chkstk")
19406 .addReg(X86::RAX, RegState::Implicit)
19407 .addReg(X86::RSP, RegState::Implicit)
19408 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
19409 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
19410 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19411 } else {
19412 // __chkstk(MSVCRT): does not update stack pointer.
19413 // Clobbers R10, R11 and EFLAGS.
19414 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
19415 .addExternalSymbol("__chkstk")
19416 .addReg(X86::RAX, RegState::Implicit)
19417 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19418 // RAX has the offset to be subtracted from RSP.
19419 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
19420 .addReg(X86::RSP)
19421 .addReg(X86::RAX);
19422 }
19423 } else {
19424 const char *StackProbeSymbol =
19425 Subtarget->isTargetKnownWindowsMSVC() ? "_chkstk" : "_alloca";
19427 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
19428 .addExternalSymbol(StackProbeSymbol)
19429 .addReg(X86::EAX, RegState::Implicit)
19430 .addReg(X86::ESP, RegState::Implicit)
19431 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
19432 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
19433 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19434 }
19436 MI->eraseFromParent(); // The pseudo instruction is gone now.
19437 return BB;
19438 }
19440 MachineBasicBlock *
19441 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
19442 MachineBasicBlock *BB) const {
19443 // This is pretty easy. We're taking the value that we received from
19444 // our load from the relocation, sticking it in either RDI (x86-64)
19445 // or EAX and doing an indirect call. The return value will then
19446 // be in the normal return register.
19447 MachineFunction *F = BB->getParent();
19448 const X86InstrInfo *TII =
19449 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
19450 DebugLoc DL = MI->getDebugLoc();
19452 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
19453 assert(MI->getOperand(3).isGlobal() && "This should be a global");
19455 // Get a register mask for the lowered call.
19456 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
19457 // proper register mask.
19458 const uint32_t *RegMask = F->getTarget()
19459 .getSubtargetImpl()
19460 ->getRegisterInfo()
19461 ->getCallPreservedMask(CallingConv::C);
19462 if (Subtarget->is64Bit()) {
19463 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19464 TII->get(X86::MOV64rm), X86::RDI)
19465 .addReg(X86::RIP)
19466 .addImm(0).addReg(0)
19467 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19468 MI->getOperand(3).getTargetFlags())
19469 .addReg(0);
19470 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
19471 addDirectMem(MIB, X86::RDI);
19472 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
19473 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
19474 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19475 TII->get(X86::MOV32rm), X86::EAX)
19476 .addReg(0)
19477 .addImm(0).addReg(0)
19478 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19479 MI->getOperand(3).getTargetFlags())
19480 .addReg(0);
19481 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19482 addDirectMem(MIB, X86::EAX);
19483 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19484 } else {
19485 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19486 TII->get(X86::MOV32rm), X86::EAX)
19487 .addReg(TII->getGlobalBaseReg(F))
19488 .addImm(0).addReg(0)
19489 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19490 MI->getOperand(3).getTargetFlags())
19491 .addReg(0);
19492 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19493 addDirectMem(MIB, X86::EAX);
19494 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19495 }
19497 MI->eraseFromParent(); // The pseudo instruction is gone now.
19498 return BB;
19499 }
19501 MachineBasicBlock *
19502 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
19503 MachineBasicBlock *MBB) const {
19504 DebugLoc DL = MI->getDebugLoc();
19505 MachineFunction *MF = MBB->getParent();
19506 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
19507 MachineRegisterInfo &MRI = MF->getRegInfo();
19509 const BasicBlock *BB = MBB->getBasicBlock();
19510 MachineFunction::iterator I = MBB;
19511 ++I;
19513 // Memory Reference
19514 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19515 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19517 unsigned DstReg;
19518 unsigned MemOpndSlot = 0;
19520 unsigned CurOp = 0;
19522 DstReg = MI->getOperand(CurOp++).getReg();
19523 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
19524 assert(RC->hasType(MVT::i32) && "Invalid destination!");
19525 unsigned mainDstReg = MRI.createVirtualRegister(RC);
19526 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
19528 MemOpndSlot = CurOp;
19530 MVT PVT = getPointerTy();
19531 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19532 "Invalid Pointer Size!");
19534 // For v = setjmp(buf), we generate
19535 //
19536 // thisMBB:
19537 // buf[LabelOffset] = restoreMBB
19538 // SjLjSetup restoreMBB
19539 //
19540 // mainMBB:
19541 // v_main = 0
19542 //
19543 // sinkMBB:
19544 // v = phi(main, restore)
19545 //
19546 // restoreMBB:
19547 // v_restore = 1
19549 MachineBasicBlock *thisMBB = MBB;
19550 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19551 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19552 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
19553 MF->insert(I, mainMBB);
19554 MF->insert(I, sinkMBB);
19555 MF->push_back(restoreMBB);
19557 MachineInstrBuilder MIB;
19559 // Transfer the remainder of BB and its successor edges to sinkMBB.
19560 sinkMBB->splice(sinkMBB->begin(), MBB,
19561 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19562 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19564 // thisMBB:
19565 unsigned PtrStoreOpc = 0;
19566 unsigned LabelReg = 0;
19567 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19568 Reloc::Model RM = MF->getTarget().getRelocationModel();
19569 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
19570 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
19572 // Prepare IP either in reg or imm.
19573 if (!UseImmLabel) {
19574 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
19575 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
19576 LabelReg = MRI.createVirtualRegister(PtrRC);
19577 if (Subtarget->is64Bit()) {
19578 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
19579 .addReg(X86::RIP)
19580 .addImm(0)
19581 .addReg(0)
19582 .addMBB(restoreMBB)
19583 .addReg(0);
19584 } else {
19585 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
19586 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
19587 .addReg(XII->getGlobalBaseReg(MF))
19588 .addImm(0)
19589 .addReg(0)
19590 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
19591 .addReg(0);
19592 }
19593 } else
19594 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
19595 // Store IP
19596 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
19597 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19598 if (i == X86::AddrDisp)
19599 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
19600 else
19601 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
19602 }
19603 if (!UseImmLabel)
19604 MIB.addReg(LabelReg);
19605 else
19606 MIB.addMBB(restoreMBB);
19607 MIB.setMemRefs(MMOBegin, MMOEnd);
19608 // Setup
19609 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
19610 .addMBB(restoreMBB);
19612 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
19613 MF->getSubtarget().getRegisterInfo());
19614 MIB.addRegMask(RegInfo->getNoPreservedMask());
19615 thisMBB->addSuccessor(mainMBB);
19616 thisMBB->addSuccessor(restoreMBB);
19618 // mainMBB:
19619 // EAX = 0
19620 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
19621 mainMBB->addSuccessor(sinkMBB);
19623 // sinkMBB:
19624 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19625 TII->get(X86::PHI), DstReg)
19626 .addReg(mainDstReg).addMBB(mainMBB)
19627 .addReg(restoreDstReg).addMBB(restoreMBB);
19629 // restoreMBB:
19630 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
19631 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
19632 restoreMBB->addSuccessor(sinkMBB);
19634 MI->eraseFromParent();
19635 return sinkMBB;
19636 }
19638 MachineBasicBlock *
19639 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
19640 MachineBasicBlock *MBB) const {
19641 DebugLoc DL = MI->getDebugLoc();
19642 MachineFunction *MF = MBB->getParent();
19643 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
19644 MachineRegisterInfo &MRI = MF->getRegInfo();
19646 // Memory Reference
19647 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19648 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19650 MVT PVT = getPointerTy();
19651 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19652 "Invalid Pointer Size!");
19654 const TargetRegisterClass *RC =
19655 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
19656 unsigned Tmp = MRI.createVirtualRegister(RC);
19657 // Since FP is only updated here but NOT referenced, it's treated as GPR.
19658 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
19659 MF->getSubtarget().getRegisterInfo());
19660 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
19661 unsigned SP = RegInfo->getStackRegister();
19663 MachineInstrBuilder MIB;
19665 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19666 const int64_t SPOffset = 2 * PVT.getStoreSize();
19668 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
19669 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
19671 // Reload FP
19672 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
19673 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
19674 MIB.addOperand(MI->getOperand(i));
19675 MIB.setMemRefs(MMOBegin, MMOEnd);
19676 // Reload IP
19677 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
19678 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19679 if (i == X86::AddrDisp)
19680 MIB.addDisp(MI->getOperand(i), LabelOffset);
19681 else
19682 MIB.addOperand(MI->getOperand(i));
19683 }
19684 MIB.setMemRefs(MMOBegin, MMOEnd);
19685 // Reload SP
19686 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
19687 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19688 if (i == X86::AddrDisp)
19689 MIB.addDisp(MI->getOperand(i), SPOffset);
19690 else
19691 MIB.addOperand(MI->getOperand(i));
19692 }
19693 MIB.setMemRefs(MMOBegin, MMOEnd);
19694 // Jump
19695 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
19697 MI->eraseFromParent();
19698 return MBB;
19699 }
19701 // Replace 213-type (isel default) FMA3 instructions with 231-type for
19702 // accumulator loops. Writing back to the accumulator allows the coalescer
19703 // to remove extra copies in the loop.
19704 MachineBasicBlock *
19705 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
19706 MachineBasicBlock *MBB) const {
19707 MachineOperand &AddendOp = MI->getOperand(3);
19709 // Bail out early if the addend isn't a register - we can't switch these.
19710 if (!AddendOp.isReg())
19711 return MBB;
19713 MachineFunction &MF = *MBB->getParent();
19714 MachineRegisterInfo &MRI = MF.getRegInfo();
19716 // Check whether the addend is defined by a PHI:
19717 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
19718 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
19719 if (!AddendDef.isPHI())
19720 return MBB;
19722 // Look for the following pattern:
19723 // loop:
19724 // %addend = phi [%entry, 0], [%loop, %result]
19725 // ...
19726 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
19728 // Replace with:
19729 // loop:
19730 // %addend = phi [%entry, 0], [%loop, %result]
19731 // ...
19732 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
19734 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
19735 assert(AddendDef.getOperand(i).isReg());
19736 MachineOperand PHISrcOp = AddendDef.getOperand(i);
19737 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
19738 if (&PHISrcInst == MI) {
19739 // Found a matching instruction.
19740 unsigned NewFMAOpc = 0;
19741 switch (MI->getOpcode()) {
19742 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
19743 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
19744 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
19745 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
19746 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
19747 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
19748 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
19749 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
19750 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
19751 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
19752 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
19753 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
19754 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
19755 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
19756 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
19757 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
19758 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
19759 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
19760 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
19761 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
19762 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
19763 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
19764 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
19765 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
19766 default: llvm_unreachable("Unrecognized FMA variant.");
19767 }
19769 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
19770 MachineInstrBuilder MIB =
19771 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
19772 .addOperand(MI->getOperand(0))
19773 .addOperand(MI->getOperand(3))
19774 .addOperand(MI->getOperand(2))
19775 .addOperand(MI->getOperand(1));
19776 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
19777 MI->eraseFromParent();
19778 }
19779 }
19781 return MBB;
19782 }
19784 MachineBasicBlock *
19785 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
19786 MachineBasicBlock *BB) const {
19787 switch (MI->getOpcode()) {
19788 default: llvm_unreachable("Unexpected instr type to insert");
19789 case X86::TAILJMPd64:
19790 case X86::TAILJMPr64:
19791 case X86::TAILJMPm64:
19792 llvm_unreachable("TAILJMP64 would not be touched here.");
19793 case X86::TCRETURNdi64:
19794 case X86::TCRETURNri64:
19795 case X86::TCRETURNmi64:
19796 return BB;
19797 case X86::WIN_ALLOCA:
19798 return EmitLoweredWinAlloca(MI, BB);
19799 case X86::SEG_ALLOCA_32:
19800 case X86::SEG_ALLOCA_64:
19801 return EmitLoweredSegAlloca(MI, BB);
19802 case X86::TLSCall_32:
19803 case X86::TLSCall_64:
19804 return EmitLoweredTLSCall(MI, BB);
19805 case X86::CMOV_GR8:
19806 case X86::CMOV_FR32:
19807 case X86::CMOV_FR64:
19808 case X86::CMOV_V4F32:
19809 case X86::CMOV_V2F64:
19810 case X86::CMOV_V2I64:
19811 case X86::CMOV_V8F32:
19812 case X86::CMOV_V4F64:
19813 case X86::CMOV_V4I64:
19814 case X86::CMOV_V16F32:
19815 case X86::CMOV_V8F64:
19816 case X86::CMOV_V8I64:
19817 case X86::CMOV_GR16:
19818 case X86::CMOV_GR32:
19819 case X86::CMOV_RFP32:
19820 case X86::CMOV_RFP64:
19821 case X86::CMOV_RFP80:
19822 return EmitLoweredSelect(MI, BB);
19824 case X86::FP32_TO_INT16_IN_MEM:
19825 case X86::FP32_TO_INT32_IN_MEM:
19826 case X86::FP32_TO_INT64_IN_MEM:
19827 case X86::FP64_TO_INT16_IN_MEM:
19828 case X86::FP64_TO_INT32_IN_MEM:
19829 case X86::FP64_TO_INT64_IN_MEM:
19830 case X86::FP80_TO_INT16_IN_MEM:
19831 case X86::FP80_TO_INT32_IN_MEM:
19832 case X86::FP80_TO_INT64_IN_MEM: {
19833 MachineFunction *F = BB->getParent();
19834 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
19835 DebugLoc DL = MI->getDebugLoc();
19837 // Change the floating point control register to use "round towards zero"
19838 // mode when truncating to an integer value.
19839 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
19840 addFrameReference(BuildMI(*BB, MI, DL,
19841 TII->get(X86::FNSTCW16m)), CWFrameIdx);
19843 // Load the old value of the high byte of the control word...
19844 unsigned OldCW =
19845 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
19846 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
19847 CWFrameIdx);
19849 // Set the high part to be round to zero...
19850 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
19851 .addImm(0xC7F);
19853 // Reload the modified control word now...
19854 addFrameReference(BuildMI(*BB, MI, DL,
19855 TII->get(X86::FLDCW16m)), CWFrameIdx);
19857 // Restore the memory image of control word to original value
19858 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
19859 .addReg(OldCW);
19861 // Get the X86 opcode to use.
19862 unsigned Opc;
19863 switch (MI->getOpcode()) {
19864 default: llvm_unreachable("illegal opcode!");
19865 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
19866 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
19867 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
19868 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
19869 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
19870 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
19871 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
19872 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
19873 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
19874 }
19876 X86AddressMode AM;
19877 MachineOperand &Op = MI->getOperand(0);
19878 if (Op.isReg()) {
19879 AM.BaseType = X86AddressMode::RegBase;
19880 AM.Base.Reg = Op.getReg();
19881 } else {
19882 AM.BaseType = X86AddressMode::FrameIndexBase;
19883 AM.Base.FrameIndex = Op.getIndex();
19884 }
19885 Op = MI->getOperand(1);
19886 if (Op.isImm())
19887 AM.Scale = Op.getImm();
19888 Op = MI->getOperand(2);
19889 if (Op.isImm())
19890 AM.IndexReg = Op.getImm();
19891 Op = MI->getOperand(3);
19892 if (Op.isGlobal()) {
19893 AM.GV = Op.getGlobal();
19894 } else {
19895 AM.Disp = Op.getImm();
19896 }
19897 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
19898 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
19900 // Reload the original control word now.
19901 addFrameReference(BuildMI(*BB, MI, DL,
19902 TII->get(X86::FLDCW16m)), CWFrameIdx);
19904 MI->eraseFromParent(); // The pseudo instruction is gone now.
19905 return BB;
19906 }
19907 // String/text processing lowering.
19908 case X86::PCMPISTRM128REG:
19909 case X86::VPCMPISTRM128REG:
19910 case X86::PCMPISTRM128MEM:
19911 case X86::VPCMPISTRM128MEM:
19912 case X86::PCMPESTRM128REG:
19913 case X86::VPCMPESTRM128REG:
19914 case X86::PCMPESTRM128MEM:
19915 case X86::VPCMPESTRM128MEM:
19916 assert(Subtarget->hasSSE42() &&
19917 "Target must have SSE4.2 or AVX features enabled");
19918 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
19920 // String/text processing lowering.
19921 case X86::PCMPISTRIREG:
19922 case X86::VPCMPISTRIREG:
19923 case X86::PCMPISTRIMEM:
19924 case X86::VPCMPISTRIMEM:
19925 case X86::PCMPESTRIREG:
19926 case X86::VPCMPESTRIREG:
19927 case X86::PCMPESTRIMEM:
19928 case X86::VPCMPESTRIMEM:
19929 assert(Subtarget->hasSSE42() &&
19930 "Target must have SSE4.2 or AVX features enabled");
19931 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
19933 // Thread synchronization.
19934 case X86::MONITOR:
19935 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
19936 Subtarget);
19938 // xbegin
19939 case X86::XBEGIN:
19940 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
19942 case X86::VASTART_SAVE_XMM_REGS:
19943 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
19945 case X86::VAARG_64:
19946 return EmitVAARG64WithCustomInserter(MI, BB);
19948 case X86::EH_SjLj_SetJmp32:
19949 case X86::EH_SjLj_SetJmp64:
19950 return emitEHSjLjSetJmp(MI, BB);
19952 case X86::EH_SjLj_LongJmp32:
19953 case X86::EH_SjLj_LongJmp64:
19954 return emitEHSjLjLongJmp(MI, BB);
19956 case TargetOpcode::STACKMAP:
19957 case TargetOpcode::PATCHPOINT:
19958 return emitPatchPoint(MI, BB);
19960 case X86::VFMADDPDr213r:
19961 case X86::VFMADDPSr213r:
19962 case X86::VFMADDSDr213r:
19963 case X86::VFMADDSSr213r:
19964 case X86::VFMSUBPDr213r:
19965 case X86::VFMSUBPSr213r:
19966 case X86::VFMSUBSDr213r:
19967 case X86::VFMSUBSSr213r:
19968 case X86::VFNMADDPDr213r:
19969 case X86::VFNMADDPSr213r:
19970 case X86::VFNMADDSDr213r:
19971 case X86::VFNMADDSSr213r:
19972 case X86::VFNMSUBPDr213r:
19973 case X86::VFNMSUBPSr213r:
19974 case X86::VFNMSUBSDr213r:
19975 case X86::VFNMSUBSSr213r:
19976 case X86::VFMADDPDr213rY:
19977 case X86::VFMADDPSr213rY:
19978 case X86::VFMSUBPDr213rY:
19979 case X86::VFMSUBPSr213rY:
19980 case X86::VFNMADDPDr213rY:
19981 case X86::VFNMADDPSr213rY:
19982 case X86::VFNMSUBPDr213rY:
19983 case X86::VFNMSUBPSr213rY:
19984 return emitFMA3Instr(MI, BB);
19985 }
19986 }
19988 //===----------------------------------------------------------------------===//
19989 // X86 Optimization Hooks
19990 //===----------------------------------------------------------------------===//
19992 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
19993 APInt &KnownZero,
19994 APInt &KnownOne,
19995 const SelectionDAG &DAG,
19996 unsigned Depth) const {
19997 unsigned BitWidth = KnownZero.getBitWidth();
19998 unsigned Opc = Op.getOpcode();
19999 assert((Opc >= ISD::BUILTIN_OP_END ||
20000 Opc == ISD::INTRINSIC_WO_CHAIN ||
20001 Opc == ISD::INTRINSIC_W_CHAIN ||
20002 Opc == ISD::INTRINSIC_VOID) &&
20003 "Should use MaskedValueIsZero if you don't know whether Op"
20004 " is a target node!");
20006 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
20007 switch (Opc) {
20008 default: break;
20009 case X86ISD::ADD:
20010 case X86ISD::SUB:
20011 case X86ISD::ADC:
20012 case X86ISD::SBB:
20013 case X86ISD::SMUL:
20014 case X86ISD::UMUL:
20015 case X86ISD::INC:
20016 case X86ISD::DEC:
20017 case X86ISD::OR:
20018 case X86ISD::XOR:
20019 case X86ISD::AND:
20020 // These nodes' second result is a boolean.
20021 if (Op.getResNo() == 0)
20022 break;
20023 // Fallthrough
20024 case X86ISD::SETCC:
20025 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
20026 break;
20027 case ISD::INTRINSIC_WO_CHAIN: {
20028 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
20029 unsigned NumLoBits = 0;
20030 switch (IntId) {
20031 default: break;
20032 case Intrinsic::x86_sse_movmsk_ps:
20033 case Intrinsic::x86_avx_movmsk_ps_256:
20034 case Intrinsic::x86_sse2_movmsk_pd:
20035 case Intrinsic::x86_avx_movmsk_pd_256:
20036 case Intrinsic::x86_mmx_pmovmskb:
20037 case Intrinsic::x86_sse2_pmovmskb_128:
20038 case Intrinsic::x86_avx2_pmovmskb: {
20039 // High bits of movmskp{s|d}, pmovmskb are known zero.
20040 switch (IntId) {
20041 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
20042 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
20043 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
20044 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
20045 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
20046 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
20047 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
20048 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
20049 }
20050 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
20051 break;
20052 }
20053 }
20054 break;
20055 }
20056 }
20057 }
20059 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
20060 SDValue Op,
20061 const SelectionDAG &,
20062 unsigned Depth) const {
20063 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
20064 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
20065 return Op.getValueType().getScalarType().getSizeInBits();
20067 // Fallback case.
20068 return 1;
20069 }
20071 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
20072 /// node is a GlobalAddress + offset.
20073 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
20074 const GlobalValue* &GA,
20075 int64_t &Offset) const {
20076 if (N->getOpcode() == X86ISD::Wrapper) {
20077 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
20078 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
20079 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
20080 return true;
20081 }
20082 }
20083 return TargetLowering::isGAPlusOffset(N, GA, Offset);
20084 }
20086 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
20087 /// same as extracting the high 128-bit part of 256-bit vector and then
20088 /// inserting the result into the low part of a new 256-bit vector
20089 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
20090 EVT VT = SVOp->getValueType(0);
20091 unsigned NumElems = VT.getVectorNumElements();
20093 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20094 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
20095 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
20096 SVOp->getMaskElt(j) >= 0)
20097 return false;
20099 return true;
20100 }
20102 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
20103 /// same as extracting the low 128-bit part of 256-bit vector and then
20104 /// inserting the result into the high part of a new 256-bit vector
20105 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
20106 EVT VT = SVOp->getValueType(0);
20107 unsigned NumElems = VT.getVectorNumElements();
20109 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20110 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
20111 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
20112 SVOp->getMaskElt(j) >= 0)
20113 return false;
20115 return true;
20116 }
20118 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
20119 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
20120 TargetLowering::DAGCombinerInfo &DCI,
20121 const X86Subtarget* Subtarget) {
20122 SDLoc dl(N);
20123 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
20124 SDValue V1 = SVOp->getOperand(0);
20125 SDValue V2 = SVOp->getOperand(1);
20126 EVT VT = SVOp->getValueType(0);
20127 unsigned NumElems = VT.getVectorNumElements();
20129 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
20130 V2.getOpcode() == ISD::CONCAT_VECTORS) {
20131 //
20132 // 0,0,0,...
20133 // |
20134 // V UNDEF BUILD_VECTOR UNDEF
20135 // \ / \ /
20136 // CONCAT_VECTOR CONCAT_VECTOR
20137 // \ /
20138 // \ /
20139 // RESULT: V + zero extended
20140 //
20141 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
20142 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
20143 V1.getOperand(1).getOpcode() != ISD::UNDEF)
20144 return SDValue();
20146 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
20147 return SDValue();
20149 // To match the shuffle mask, the first half of the mask should
20150 // be exactly the first vector, and all the rest a splat with the
20151 // first element of the second one.
20152 for (unsigned i = 0; i != NumElems/2; ++i)
20153 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
20154 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
20155 return SDValue();
20157 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
20158 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
20159 if (Ld->hasNUsesOfValue(1, 0)) {
20160 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
20161 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
20162 SDValue ResNode =
20163 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
20164 Ld->getMemoryVT(),
20165 Ld->getPointerInfo(),
20166 Ld->getAlignment(),
20167 false/*isVolatile*/, true/*ReadMem*/,
20168 false/*WriteMem*/);
20170 // Make sure the newly-created LOAD is in the same position as Ld in
20171 // terms of dependency. We create a TokenFactor for Ld and ResNode,
20172 // and update uses of Ld's output chain to use the TokenFactor.
20173 if (Ld->hasAnyUseOfValue(1)) {
20174 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
20175 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
20176 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
20177 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
20178 SDValue(ResNode.getNode(), 1));
20179 }
20181 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
20182 }
20183 }
20185 // Emit a zeroed vector and insert the desired subvector on its
20186 // first half.
20187 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
20188 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
20189 return DCI.CombineTo(N, InsV);
20190 }
20192 //===--------------------------------------------------------------------===//
20193 // Combine some shuffles into subvector extracts and inserts:
20194 //
20196 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20197 if (isShuffleHigh128VectorInsertLow(SVOp)) {
20198 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
20199 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
20200 return DCI.CombineTo(N, InsV);
20201 }
20203 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20204 if (isShuffleLow128VectorInsertHigh(SVOp)) {
20205 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
20206 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
20207 return DCI.CombineTo(N, InsV);
20208 }
20210 return SDValue();
20211 }
20213 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
20214 /// possible.
20215 ///
20216 /// This is the leaf of the recursive combinine below. When we have found some
20217 /// chain of single-use x86 shuffle instructions and accumulated the combined
20218 /// shuffle mask represented by them, this will try to pattern match that mask
20219 /// into either a single instruction if there is a special purpose instruction
20220 /// for this operation, or into a PSHUFB instruction which is a fully general
20221 /// instruction but should only be used to replace chains over a certain depth.
20222 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
20223 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
20224 TargetLowering::DAGCombinerInfo &DCI,
20225 const X86Subtarget *Subtarget) {
20226 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
20228 // Find the operand that enters the chain. Note that multiple uses are OK
20229 // here, we're not going to remove the operand we find.
20230 SDValue Input = Op.getOperand(0);
20231 while (Input.getOpcode() == ISD::BITCAST)
20232 Input = Input.getOperand(0);
20234 MVT VT = Input.getSimpleValueType();
20235 MVT RootVT = Root.getSimpleValueType();
20236 SDLoc DL(Root);
20238 // Just remove no-op shuffle masks.
20239 if (Mask.size() == 1) {
20240 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
20241 /*AddTo*/ true);
20242 return true;
20243 }
20245 // Use the float domain if the operand type is a floating point type.
20246 bool FloatDomain = VT.isFloatingPoint();
20248 // For floating point shuffles, we don't have free copies in the shuffle
20249 // instructions or the ability to load as part of the instruction, so
20250 // canonicalize their shuffles to UNPCK or MOV variants.
20251 //
20252 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
20253 // vectors because it can have a load folded into it that UNPCK cannot. This
20254 // doesn't preclude something switching to the shorter encoding post-RA.
20255 if (FloatDomain) {
20256 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
20257 bool Lo = Mask.equals(0, 0);
20258 unsigned Shuffle;
20259 MVT ShuffleVT;
20260 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
20261 // is no slower than UNPCKLPD but has the option to fold the input operand
20262 // into even an unaligned memory load.
20263 if (Lo && Subtarget->hasSSE3()) {
20264 Shuffle = X86ISD::MOVDDUP;
20265 ShuffleVT = MVT::v2f64;
20266 } else {
20267 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
20268 // than the UNPCK variants.
20269 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
20270 ShuffleVT = MVT::v4f32;
20271 }
20272 if (Depth == 1 && Root->getOpcode() == Shuffle)
20273 return false; // Nothing to do!
20274 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20275 DCI.AddToWorklist(Op.getNode());
20276 if (Shuffle == X86ISD::MOVDDUP)
20277 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20278 else
20279 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20280 DCI.AddToWorklist(Op.getNode());
20281 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20282 /*AddTo*/ true);
20283 return true;
20284 }
20285 if (Subtarget->hasSSE3() &&
20286 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
20287 bool Lo = Mask.equals(0, 0, 2, 2);
20288 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
20289 MVT ShuffleVT = MVT::v4f32;
20290 if (Depth == 1 && Root->getOpcode() == Shuffle)
20291 return false; // Nothing to do!
20292 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20293 DCI.AddToWorklist(Op.getNode());
20294 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20295 DCI.AddToWorklist(Op.getNode());
20296 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20297 /*AddTo*/ true);
20298 return true;
20299 }
20300 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
20301 bool Lo = Mask.equals(0, 0, 1, 1);
20302 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20303 MVT ShuffleVT = MVT::v4f32;
20304 if (Depth == 1 && Root->getOpcode() == Shuffle)
20305 return false; // Nothing to do!
20306 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20307 DCI.AddToWorklist(Op.getNode());
20308 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20309 DCI.AddToWorklist(Op.getNode());
20310 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20311 /*AddTo*/ true);
20312 return true;
20313 }
20314 }
20316 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
20317 // variants as none of these have single-instruction variants that are
20318 // superior to the UNPCK formulation.
20319 if (!FloatDomain &&
20320 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
20321 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
20322 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
20323 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
20324 15))) {
20325 bool Lo = Mask[0] == 0;
20326 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20327 if (Depth == 1 && Root->getOpcode() == Shuffle)
20328 return false; // Nothing to do!
20329 MVT ShuffleVT;
20330 switch (Mask.size()) {
20331 case 8:
20332 ShuffleVT = MVT::v8i16;
20333 break;
20334 case 16:
20335 ShuffleVT = MVT::v16i8;
20336 break;
20337 default:
20338 llvm_unreachable("Impossible mask size!");
20339 };
20340 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20341 DCI.AddToWorklist(Op.getNode());
20342 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20343 DCI.AddToWorklist(Op.getNode());
20344 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20345 /*AddTo*/ true);
20346 return true;
20347 }
20349 // Don't try to re-form single instruction chains under any circumstances now
20350 // that we've done encoding canonicalization for them.
20351 if (Depth < 2)
20352 return false;
20354 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
20355 // can replace them with a single PSHUFB instruction profitably. Intel's
20356 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
20357 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
20358 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
20359 SmallVector<SDValue, 16> PSHUFBMask;
20360 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
20361 int Ratio = 16 / Mask.size();
20362 for (unsigned i = 0; i < 16; ++i) {
20363 if (Mask[i / Ratio] == SM_SentinelUndef) {
20364 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
20365 continue;
20366 }
20367 int M = Mask[i / Ratio] != SM_SentinelZero
20368 ? Ratio * Mask[i / Ratio] + i % Ratio
20369 : 255;
20370 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
20371 }
20372 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
20373 DCI.AddToWorklist(Op.getNode());
20374 SDValue PSHUFBMaskOp =
20375 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
20376 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
20377 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
20378 DCI.AddToWorklist(Op.getNode());
20379 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20380 /*AddTo*/ true);
20381 return true;
20382 }
20384 // Failed to find any combines.
20385 return false;
20386 }
20388 /// \brief Fully generic combining of x86 shuffle instructions.
20389 ///
20390 /// This should be the last combine run over the x86 shuffle instructions. Once
20391 /// they have been fully optimized, this will recursively consider all chains
20392 /// of single-use shuffle instructions, build a generic model of the cumulative
20393 /// shuffle operation, and check for simpler instructions which implement this
20394 /// operation. We use this primarily for two purposes:
20395 ///
20396 /// 1) Collapse generic shuffles to specialized single instructions when
20397 /// equivalent. In most cases, this is just an encoding size win, but
20398 /// sometimes we will collapse multiple generic shuffles into a single
20399 /// special-purpose shuffle.
20400 /// 2) Look for sequences of shuffle instructions with 3 or more total
20401 /// instructions, and replace them with the slightly more expensive SSSE3
20402 /// PSHUFB instruction if available. We do this as the last combining step
20403 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
20404 /// a suitable short sequence of other instructions. The PHUFB will either
20405 /// use a register or have to read from memory and so is slightly (but only
20406 /// slightly) more expensive than the other shuffle instructions.
20407 ///
20408 /// Because this is inherently a quadratic operation (for each shuffle in
20409 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
20410 /// This should never be an issue in practice as the shuffle lowering doesn't
20411 /// produce sequences of more than 8 instructions.
20412 ///
20413 /// FIXME: We will currently miss some cases where the redundant shuffling
20414 /// would simplify under the threshold for PSHUFB formation because of
20415 /// combine-ordering. To fix this, we should do the redundant instruction
20416 /// combining in this recursive walk.
20417 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
20418 ArrayRef<int> RootMask,
20419 int Depth, bool HasPSHUFB,
20420 SelectionDAG &DAG,
20421 TargetLowering::DAGCombinerInfo &DCI,
20422 const X86Subtarget *Subtarget) {
20423 // Bound the depth of our recursive combine because this is ultimately
20424 // quadratic in nature.
20425 if (Depth > 8)
20426 return false;
20428 // Directly rip through bitcasts to find the underlying operand.
20429 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
20430 Op = Op.getOperand(0);
20432 MVT VT = Op.getSimpleValueType();
20433 if (!VT.isVector())
20434 return false; // Bail if we hit a non-vector.
20435 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
20436 // version should be added.
20437 if (VT.getSizeInBits() != 128)
20438 return false;
20440 assert(Root.getSimpleValueType().isVector() &&
20441 "Shuffles operate on vector types!");
20442 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
20443 "Can only combine shuffles of the same vector register size.");
20445 if (!isTargetShuffle(Op.getOpcode()))
20446 return false;
20447 SmallVector<int, 16> OpMask;
20448 bool IsUnary;
20449 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
20450 // We only can combine unary shuffles which we can decode the mask for.
20451 if (!HaveMask || !IsUnary)
20452 return false;
20454 assert(VT.getVectorNumElements() == OpMask.size() &&
20455 "Different mask size from vector size!");
20456 assert(((RootMask.size() > OpMask.size() &&
20457 RootMask.size() % OpMask.size() == 0) ||
20458 (OpMask.size() > RootMask.size() &&
20459 OpMask.size() % RootMask.size() == 0) ||
20460 OpMask.size() == RootMask.size()) &&
20461 "The smaller number of elements must divide the larger.");
20462 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
20463 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
20464 assert(((RootRatio == 1 && OpRatio == 1) ||
20465 (RootRatio == 1) != (OpRatio == 1)) &&
20466 "Must not have a ratio for both incoming and op masks!");
20468 SmallVector<int, 16> Mask;
20469 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
20471 // Merge this shuffle operation's mask into our accumulated mask. Note that
20472 // this shuffle's mask will be the first applied to the input, followed by the
20473 // root mask to get us all the way to the root value arrangement. The reason
20474 // for this order is that we are recursing up the operation chain.
20475 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
20476 int RootIdx = i / RootRatio;
20477 if (RootMask[RootIdx] < 0) {
20478 // This is a zero or undef lane, we're done.
20479 Mask.push_back(RootMask[RootIdx]);
20480 continue;
20481 }
20483 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
20484 int OpIdx = RootMaskedIdx / OpRatio;
20485 if (OpMask[OpIdx] < 0) {
20486 // The incoming lanes are zero or undef, it doesn't matter which ones we
20487 // are using.
20488 Mask.push_back(OpMask[OpIdx]);
20489 continue;
20490 }
20492 // Ok, we have non-zero lanes, map them through.
20493 Mask.push_back(OpMask[OpIdx] * OpRatio +
20494 RootMaskedIdx % OpRatio);
20495 }
20497 // See if we can recurse into the operand to combine more things.
20498 switch (Op.getOpcode()) {
20499 case X86ISD::PSHUFB:
20500 HasPSHUFB = true;
20501 case X86ISD::PSHUFD:
20502 case X86ISD::PSHUFHW:
20503 case X86ISD::PSHUFLW:
20504 if (Op.getOperand(0).hasOneUse() &&
20505 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20506 HasPSHUFB, DAG, DCI, Subtarget))
20507 return true;
20508 break;
20510 case X86ISD::UNPCKL:
20511 case X86ISD::UNPCKH:
20512 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
20513 // We can't check for single use, we have to check that this shuffle is the only user.
20514 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
20515 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20516 HasPSHUFB, DAG, DCI, Subtarget))
20517 return true;
20518 break;
20519 }
20521 // Minor canonicalization of the accumulated shuffle mask to make it easier
20522 // to match below. All this does is detect masks with squential pairs of
20523 // elements, and shrink them to the half-width mask. It does this in a loop
20524 // so it will reduce the size of the mask to the minimal width mask which
20525 // performs an equivalent shuffle.
20526 while (Mask.size() > 1 && canWidenShuffleElements(Mask)) {
20527 for (int i = 0, e = Mask.size() / 2; i < e; ++i)
20528 Mask[i] = Mask[2 * i] / 2;
20529 Mask.resize(Mask.size() / 2);
20530 }
20532 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
20533 Subtarget);
20534 }
20536 /// \brief Get the PSHUF-style mask from PSHUF node.
20537 ///
20538 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
20539 /// PSHUF-style masks that can be reused with such instructions.
20540 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
20541 SmallVector<int, 4> Mask;
20542 bool IsUnary;
20543 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
20544 (void)HaveMask;
20545 assert(HaveMask);
20547 switch (N.getOpcode()) {
20548 case X86ISD::PSHUFD:
20549 return Mask;
20550 case X86ISD::PSHUFLW:
20551 Mask.resize(4);
20552 return Mask;
20553 case X86ISD::PSHUFHW:
20554 Mask.erase(Mask.begin(), Mask.begin() + 4);
20555 for (int &M : Mask)
20556 M -= 4;
20557 return Mask;
20558 default:
20559 llvm_unreachable("No valid shuffle instruction found!");
20560 }
20561 }
20563 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
20564 ///
20565 /// We walk up the chain and look for a combinable shuffle, skipping over
20566 /// shuffles that we could hoist this shuffle's transformation past without
20567 /// altering anything.
20568 static SDValue
20569 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
20570 SelectionDAG &DAG,
20571 TargetLowering::DAGCombinerInfo &DCI) {
20572 assert(N.getOpcode() == X86ISD::PSHUFD &&
20573 "Called with something other than an x86 128-bit half shuffle!");
20574 SDLoc DL(N);
20576 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
20577 // of the shuffles in the chain so that we can form a fresh chain to replace
20578 // this one.
20579 SmallVector<SDValue, 8> Chain;
20580 SDValue V = N.getOperand(0);
20581 for (; V.hasOneUse(); V = V.getOperand(0)) {
20582 switch (V.getOpcode()) {
20583 default:
20584 return SDValue(); // Nothing combined!
20586 case ISD::BITCAST:
20587 // Skip bitcasts as we always know the type for the target specific
20588 // instructions.
20589 continue;
20591 case X86ISD::PSHUFD:
20592 // Found another dword shuffle.
20593 break;
20595 case X86ISD::PSHUFLW:
20596 // Check that the low words (being shuffled) are the identity in the
20597 // dword shuffle, and the high words are self-contained.
20598 if (Mask[0] != 0 || Mask[1] != 1 ||
20599 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
20600 return SDValue();
20602 Chain.push_back(V);
20603 continue;
20605 case X86ISD::PSHUFHW:
20606 // Check that the high words (being shuffled) are the identity in the
20607 // dword shuffle, and the low words are self-contained.
20608 if (Mask[2] != 2 || Mask[3] != 3 ||
20609 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
20610 return SDValue();
20612 Chain.push_back(V);
20613 continue;
20615 case X86ISD::UNPCKL:
20616 case X86ISD::UNPCKH:
20617 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
20618 // shuffle into a preceding word shuffle.
20619 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
20620 return SDValue();
20622 // Search for a half-shuffle which we can combine with.
20623 unsigned CombineOp =
20624 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
20625 if (V.getOperand(0) != V.getOperand(1) ||
20626 !V->isOnlyUserOf(V.getOperand(0).getNode()))
20627 return SDValue();
20628 Chain.push_back(V);
20629 V = V.getOperand(0);
20630 do {
20631 switch (V.getOpcode()) {
20632 default:
20633 return SDValue(); // Nothing to combine.
20635 case X86ISD::PSHUFLW:
20636 case X86ISD::PSHUFHW:
20637 if (V.getOpcode() == CombineOp)
20638 break;
20640 Chain.push_back(V);
20642 // Fallthrough!
20643 case ISD::BITCAST:
20644 V = V.getOperand(0);
20645 continue;
20646 }
20647 break;
20648 } while (V.hasOneUse());
20649 break;
20650 }
20651 // Break out of the loop if we break out of the switch.
20652 break;
20653 }
20655 if (!V.hasOneUse())
20656 // We fell out of the loop without finding a viable combining instruction.
20657 return SDValue();
20659 // Merge this node's mask and our incoming mask.
20660 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20661 for (int &M : Mask)
20662 M = VMask[M];
20663 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
20664 getV4X86ShuffleImm8ForMask(Mask, DAG));
20666 // Rebuild the chain around this new shuffle.
20667 while (!Chain.empty()) {
20668 SDValue W = Chain.pop_back_val();
20670 if (V.getValueType() != W.getOperand(0).getValueType())
20671 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
20673 switch (W.getOpcode()) {
20674 default:
20675 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
20677 case X86ISD::UNPCKL:
20678 case X86ISD::UNPCKH:
20679 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
20680 break;
20682 case X86ISD::PSHUFD:
20683 case X86ISD::PSHUFLW:
20684 case X86ISD::PSHUFHW:
20685 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
20686 break;
20687 }
20688 }
20689 if (V.getValueType() != N.getValueType())
20690 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
20692 // Return the new chain to replace N.
20693 return V;
20694 }
20696 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
20697 ///
20698 /// We walk up the chain, skipping shuffles of the other half and looking
20699 /// through shuffles which switch halves trying to find a shuffle of the same
20700 /// pair of dwords.
20701 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
20702 SelectionDAG &DAG,
20703 TargetLowering::DAGCombinerInfo &DCI) {
20704 assert(
20705 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
20706 "Called with something other than an x86 128-bit half shuffle!");
20707 SDLoc DL(N);
20708 unsigned CombineOpcode = N.getOpcode();
20710 // Walk up a single-use chain looking for a combinable shuffle.
20711 SDValue V = N.getOperand(0);
20712 for (; V.hasOneUse(); V = V.getOperand(0)) {
20713 switch (V.getOpcode()) {
20714 default:
20715 return false; // Nothing combined!
20717 case ISD::BITCAST:
20718 // Skip bitcasts as we always know the type for the target specific
20719 // instructions.
20720 continue;
20722 case X86ISD::PSHUFLW:
20723 case X86ISD::PSHUFHW:
20724 if (V.getOpcode() == CombineOpcode)
20725 break;
20727 // Other-half shuffles are no-ops.
20728 continue;
20729 }
20730 // Break out of the loop if we break out of the switch.
20731 break;
20732 }
20734 if (!V.hasOneUse())
20735 // We fell out of the loop without finding a viable combining instruction.
20736 return false;
20738 // Combine away the bottom node as its shuffle will be accumulated into
20739 // a preceding shuffle.
20740 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
20742 // Record the old value.
20743 SDValue Old = V;
20745 // Merge this node's mask and our incoming mask (adjusted to account for all
20746 // the pshufd instructions encountered).
20747 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20748 for (int &M : Mask)
20749 M = VMask[M];
20750 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
20751 getV4X86ShuffleImm8ForMask(Mask, DAG));
20753 // Check that the shuffles didn't cancel each other out. If not, we need to
20754 // combine to the new one.
20755 if (Old != V)
20756 // Replace the combinable shuffle with the combined one, updating all users
20757 // so that we re-evaluate the chain here.
20758 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
20760 return true;
20761 }
20763 /// \brief Try to combine x86 target specific shuffles.
20764 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
20765 TargetLowering::DAGCombinerInfo &DCI,
20766 const X86Subtarget *Subtarget) {
20767 SDLoc DL(N);
20768 MVT VT = N.getSimpleValueType();
20769 SmallVector<int, 4> Mask;
20771 switch (N.getOpcode()) {
20772 case X86ISD::PSHUFD:
20773 case X86ISD::PSHUFLW:
20774 case X86ISD::PSHUFHW:
20775 Mask = getPSHUFShuffleMask(N);
20776 assert(Mask.size() == 4);
20777 break;
20778 default:
20779 return SDValue();
20780 }
20782 // Nuke no-op shuffles that show up after combining.
20783 if (isNoopShuffleMask(Mask))
20784 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
20786 // Look for simplifications involving one or two shuffle instructions.
20787 SDValue V = N.getOperand(0);
20788 switch (N.getOpcode()) {
20789 default:
20790 break;
20791 case X86ISD::PSHUFLW:
20792 case X86ISD::PSHUFHW:
20793 assert(VT == MVT::v8i16);
20794 (void)VT;
20796 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
20797 return SDValue(); // We combined away this shuffle, so we're done.
20799 // See if this reduces to a PSHUFD which is no more expensive and can
20800 // combine with more operations.
20801 if (canWidenShuffleElements(Mask)) {
20802 int DMask[] = {-1, -1, -1, -1};
20803 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
20804 DMask[DOffset + 0] = DOffset + Mask[0] / 2;
20805 DMask[DOffset + 1] = DOffset + Mask[2] / 2;
20806 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
20807 DCI.AddToWorklist(V.getNode());
20808 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
20809 getV4X86ShuffleImm8ForMask(DMask, DAG));
20810 DCI.AddToWorklist(V.getNode());
20811 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
20812 }
20814 // Look for shuffle patterns which can be implemented as a single unpack.
20815 // FIXME: This doesn't handle the location of the PSHUFD generically, and
20816 // only works when we have a PSHUFD followed by two half-shuffles.
20817 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
20818 (V.getOpcode() == X86ISD::PSHUFLW ||
20819 V.getOpcode() == X86ISD::PSHUFHW) &&
20820 V.getOpcode() != N.getOpcode() &&
20821 V.hasOneUse()) {
20822 SDValue D = V.getOperand(0);
20823 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
20824 D = D.getOperand(0);
20825 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
20826 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20827 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
20828 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
20829 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
20830 int WordMask[8];
20831 for (int i = 0; i < 4; ++i) {
20832 WordMask[i + NOffset] = Mask[i] + NOffset;
20833 WordMask[i + VOffset] = VMask[i] + VOffset;
20834 }
20835 // Map the word mask through the DWord mask.
20836 int MappedMask[8];
20837 for (int i = 0; i < 8; ++i)
20838 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
20839 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
20840 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
20841 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
20842 std::begin(UnpackLoMask)) ||
20843 std::equal(std::begin(MappedMask), std::end(MappedMask),
20844 std::begin(UnpackHiMask))) {
20845 // We can replace all three shuffles with an unpack.
20846 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
20847 DCI.AddToWorklist(V.getNode());
20848 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
20849 : X86ISD::UNPCKH,
20850 DL, MVT::v8i16, V, V);
20851 }
20852 }
20853 }
20855 break;
20857 case X86ISD::PSHUFD:
20858 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
20859 return NewN;
20861 break;
20862 }
20864 return SDValue();
20865 }
20867 /// \brief Try to combine a shuffle into a target-specific add-sub node.
20868 ///
20869 /// We combine this directly on the abstract vector shuffle nodes so it is
20870 /// easier to generically match. We also insert dummy vector shuffle nodes for
20871 /// the operands which explicitly discard the lanes which are unused by this
20872 /// operation to try to flow through the rest of the combiner the fact that
20873 /// they're unused.
20874 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
20875 SDLoc DL(N);
20876 EVT VT = N->getValueType(0);
20878 // We only handle target-independent shuffles.
20879 // FIXME: It would be easy and harmless to use the target shuffle mask
20880 // extraction tool to support more.
20881 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
20882 return SDValue();
20884 auto *SVN = cast<ShuffleVectorSDNode>(N);
20885 ArrayRef<int> Mask = SVN->getMask();
20886 SDValue V1 = N->getOperand(0);
20887 SDValue V2 = N->getOperand(1);
20889 // We require the first shuffle operand to be the SUB node, and the second to
20890 // be the ADD node.
20891 // FIXME: We should support the commuted patterns.
20892 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
20893 return SDValue();
20895 // If there are other uses of these operations we can't fold them.
20896 if (!V1->hasOneUse() || !V2->hasOneUse())
20897 return SDValue();
20899 // Ensure that both operations have the same operands. Note that we can
20900 // commute the FADD operands.
20901 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
20902 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
20903 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
20904 return SDValue();
20906 // We're looking for blends between FADD and FSUB nodes. We insist on these
20907 // nodes being lined up in a specific expected pattern.
20908 if (!(isShuffleEquivalent(Mask, 0, 3) ||
20909 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
20910 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
20911 return SDValue();
20913 // Only specific types are legal at this point, assert so we notice if and
20914 // when these change.
20915 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
20916 VT == MVT::v4f64) &&
20917 "Unknown vector type encountered!");
20919 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
20920 }
20922 /// PerformShuffleCombine - Performs several different shuffle combines.
20923 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
20924 TargetLowering::DAGCombinerInfo &DCI,
20925 const X86Subtarget *Subtarget) {
20926 SDLoc dl(N);
20927 SDValue N0 = N->getOperand(0);
20928 SDValue N1 = N->getOperand(1);
20929 EVT VT = N->getValueType(0);
20931 // Don't create instructions with illegal types after legalize types has run.
20932 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20933 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
20934 return SDValue();
20936 // If we have legalized the vector types, look for blends of FADD and FSUB
20937 // nodes that we can fuse into an ADDSUB node.
20938 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
20939 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
20940 return AddSub;
20942 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
20943 if (Subtarget->hasFp256() && VT.is256BitVector() &&
20944 N->getOpcode() == ISD::VECTOR_SHUFFLE)
20945 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
20947 // During Type Legalization, when promoting illegal vector types,
20948 // the backend might introduce new shuffle dag nodes and bitcasts.
20949 //
20950 // This code performs the following transformation:
20951 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
20952 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
20953 //
20954 // We do this only if both the bitcast and the BINOP dag nodes have
20955 // one use. Also, perform this transformation only if the new binary
20956 // operation is legal. This is to avoid introducing dag nodes that
20957 // potentially need to be further expanded (or custom lowered) into a
20958 // less optimal sequence of dag nodes.
20959 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
20960 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
20961 N0.getOpcode() == ISD::BITCAST) {
20962 SDValue BC0 = N0.getOperand(0);
20963 EVT SVT = BC0.getValueType();
20964 unsigned Opcode = BC0.getOpcode();
20965 unsigned NumElts = VT.getVectorNumElements();
20967 if (BC0.hasOneUse() && SVT.isVector() &&
20968 SVT.getVectorNumElements() * 2 == NumElts &&
20969 TLI.isOperationLegal(Opcode, VT)) {
20970 bool CanFold = false;
20971 switch (Opcode) {
20972 default : break;
20973 case ISD::ADD :
20974 case ISD::FADD :
20975 case ISD::SUB :
20976 case ISD::FSUB :
20977 case ISD::MUL :
20978 case ISD::FMUL :
20979 CanFold = true;
20980 }
20982 unsigned SVTNumElts = SVT.getVectorNumElements();
20983 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
20984 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
20985 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
20986 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
20987 CanFold = SVOp->getMaskElt(i) < 0;
20989 if (CanFold) {
20990 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
20991 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
20992 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
20993 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
20994 }
20995 }
20996 }
20998 // Only handle 128 wide vector from here on.
20999 if (!VT.is128BitVector())
21000 return SDValue();
21002 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
21003 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
21004 // consecutive, non-overlapping, and in the right order.
21005 SmallVector<SDValue, 16> Elts;
21006 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
21007 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
21009 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
21010 if (LD.getNode())
21011 return LD;
21013 if (isTargetShuffle(N->getOpcode())) {
21014 SDValue Shuffle =
21015 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
21016 if (Shuffle.getNode())
21017 return Shuffle;
21019 // Try recursively combining arbitrary sequences of x86 shuffle
21020 // instructions into higher-order shuffles. We do this after combining
21021 // specific PSHUF instruction sequences into their minimal form so that we
21022 // can evaluate how many specialized shuffle instructions are involved in
21023 // a particular chain.
21024 SmallVector<int, 1> NonceMask; // Just a placeholder.
21025 NonceMask.push_back(0);
21026 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
21027 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
21028 DCI, Subtarget))
21029 return SDValue(); // This routine will use CombineTo to replace N.
21030 }
21032 return SDValue();
21033 }
21035 /// PerformTruncateCombine - Converts truncate operation to
21036 /// a sequence of vector shuffle operations.
21037 /// It is possible when we truncate 256-bit vector to 128-bit vector
21038 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
21039 TargetLowering::DAGCombinerInfo &DCI,
21040 const X86Subtarget *Subtarget) {
21041 return SDValue();
21042 }
21044 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
21045 /// specific shuffle of a load can be folded into a single element load.
21046 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
21047 /// shuffles have been customed lowered so we need to handle those here.
21048 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
21049 TargetLowering::DAGCombinerInfo &DCI) {
21050 if (DCI.isBeforeLegalizeOps())
21051 return SDValue();
21053 SDValue InVec = N->getOperand(0);
21054 SDValue EltNo = N->getOperand(1);
21056 if (!isa<ConstantSDNode>(EltNo))
21057 return SDValue();
21059 EVT VT = InVec.getValueType();
21061 if (InVec.getOpcode() == ISD::BITCAST) {
21062 // Don't duplicate a load with other uses.
21063 if (!InVec.hasOneUse())
21064 return SDValue();
21065 EVT BCVT = InVec.getOperand(0).getValueType();
21066 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
21067 return SDValue();
21068 InVec = InVec.getOperand(0);
21069 }
21071 if (!isTargetShuffle(InVec.getOpcode()))
21072 return SDValue();
21074 // Don't duplicate a load with other uses.
21075 if (!InVec.hasOneUse())
21076 return SDValue();
21078 SmallVector<int, 16> ShuffleMask;
21079 bool UnaryShuffle;
21080 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
21081 UnaryShuffle))
21082 return SDValue();
21084 // Select the input vector, guarding against out of range extract vector.
21085 unsigned NumElems = VT.getVectorNumElements();
21086 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
21087 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
21088 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
21089 : InVec.getOperand(1);
21091 // If inputs to shuffle are the same for both ops, then allow 2 uses
21092 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
21094 if (LdNode.getOpcode() == ISD::BITCAST) {
21095 // Don't duplicate a load with other uses.
21096 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
21097 return SDValue();
21099 AllowedUses = 1; // only allow 1 load use if we have a bitcast
21100 LdNode = LdNode.getOperand(0);
21101 }
21103 if (!ISD::isNormalLoad(LdNode.getNode()))
21104 return SDValue();
21106 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
21108 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
21109 return SDValue();
21111 EVT EltVT = N->getValueType(0);
21112 // If there's a bitcast before the shuffle, check if the load type and
21113 // alignment is valid.
21114 unsigned Align = LN0->getAlignment();
21115 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21116 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
21117 EltVT.getTypeForEVT(*DAG.getContext()));
21119 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
21120 return SDValue();
21122 // All checks match so transform back to vector_shuffle so that DAG combiner
21123 // can finish the job
21124 SDLoc dl(N);
21126 // Create shuffle node taking into account the case that its a unary shuffle
21127 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
21128 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
21129 InVec.getOperand(0), Shuffle,
21130 &ShuffleMask[0]);
21131 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
21132 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
21133 EltNo);
21134 }
21136 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
21137 /// generation and convert it from being a bunch of shuffles and extracts
21138 /// to a simple store and scalar loads to extract the elements.
21139 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
21140 TargetLowering::DAGCombinerInfo &DCI) {
21141 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
21142 if (NewOp.getNode())
21143 return NewOp;
21145 SDValue InputVector = N->getOperand(0);
21147 // Detect whether we are trying to convert from mmx to i32 and the bitcast
21148 // from mmx to v2i32 has a single usage.
21149 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
21150 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
21151 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
21152 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
21153 N->getValueType(0),
21154 InputVector.getNode()->getOperand(0));
21156 // Only operate on vectors of 4 elements, where the alternative shuffling
21157 // gets to be more expensive.
21158 if (InputVector.getValueType() != MVT::v4i32)
21159 return SDValue();
21161 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
21162 // single use which is a sign-extend or zero-extend, and all elements are
21163 // used.
21164 SmallVector<SDNode *, 4> Uses;
21165 unsigned ExtractedElements = 0;
21166 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
21167 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
21168 if (UI.getUse().getResNo() != InputVector.getResNo())
21169 return SDValue();
21171 SDNode *Extract = *UI;
21172 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
21173 return SDValue();
21175 if (Extract->getValueType(0) != MVT::i32)
21176 return SDValue();
21177 if (!Extract->hasOneUse())
21178 return SDValue();
21179 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
21180 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
21181 return SDValue();
21182 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
21183 return SDValue();
21185 // Record which element was extracted.
21186 ExtractedElements |=
21187 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
21189 Uses.push_back(Extract);
21190 }
21192 // If not all the elements were used, this may not be worthwhile.
21193 if (ExtractedElements != 15)
21194 return SDValue();
21196 // Ok, we've now decided to do the transformation.
21197 SDLoc dl(InputVector);
21199 // Store the value to a temporary stack slot.
21200 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
21201 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
21202 MachinePointerInfo(), false, false, 0);
21204 // Replace each use (extract) with a load of the appropriate element.
21205 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
21206 UE = Uses.end(); UI != UE; ++UI) {
21207 SDNode *Extract = *UI;
21209 // cOMpute the element's address.
21210 SDValue Idx = Extract->getOperand(1);
21211 unsigned EltSize =
21212 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
21213 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
21214 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21215 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
21217 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
21218 StackPtr, OffsetVal);
21220 // Load the scalar.
21221 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
21222 ScalarAddr, MachinePointerInfo(),
21223 false, false, false, 0);
21225 // Replace the exact with the load.
21226 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
21227 }
21229 // The replacement was made in place; don't return anything.
21230 return SDValue();
21231 }
21233 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
21234 static std::pair<unsigned, bool>
21235 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
21236 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
21237 if (!VT.isVector())
21238 return std::make_pair(0, false);
21240 bool NeedSplit = false;
21241 switch (VT.getSimpleVT().SimpleTy) {
21242 default: return std::make_pair(0, false);
21243 case MVT::v32i8:
21244 case MVT::v16i16:
21245 case MVT::v8i32:
21246 if (!Subtarget->hasAVX2())
21247 NeedSplit = true;
21248 if (!Subtarget->hasAVX())
21249 return std::make_pair(0, false);
21250 break;
21251 case MVT::v16i8:
21252 case MVT::v8i16:
21253 case MVT::v4i32:
21254 if (!Subtarget->hasSSE2())
21255 return std::make_pair(0, false);
21256 }
21258 // SSE2 has only a small subset of the operations.
21259 bool hasUnsigned = Subtarget->hasSSE41() ||
21260 (Subtarget->hasSSE2() && VT == MVT::v16i8);
21261 bool hasSigned = Subtarget->hasSSE41() ||
21262 (Subtarget->hasSSE2() && VT == MVT::v8i16);
21264 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21266 unsigned Opc = 0;
21267 // Check for x CC y ? x : y.
21268 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21269 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21270 switch (CC) {
21271 default: break;
21272 case ISD::SETULT:
21273 case ISD::SETULE:
21274 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
21275 case ISD::SETUGT:
21276 case ISD::SETUGE:
21277 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
21278 case ISD::SETLT:
21279 case ISD::SETLE:
21280 Opc = hasSigned ? X86ISD::SMIN : 0; break;
21281 case ISD::SETGT:
21282 case ISD::SETGE:
21283 Opc = hasSigned ? X86ISD::SMAX : 0; break;
21284 }
21285 // Check for x CC y ? y : x -- a min/max with reversed arms.
21286 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21287 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21288 switch (CC) {
21289 default: break;
21290 case ISD::SETULT:
21291 case ISD::SETULE:
21292 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
21293 case ISD::SETUGT:
21294 case ISD::SETUGE:
21295 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
21296 case ISD::SETLT:
21297 case ISD::SETLE:
21298 Opc = hasSigned ? X86ISD::SMAX : 0; break;
21299 case ISD::SETGT:
21300 case ISD::SETGE:
21301 Opc = hasSigned ? X86ISD::SMIN : 0; break;
21302 }
21303 }
21305 return std::make_pair(Opc, NeedSplit);
21306 }
21308 static SDValue
21309 TransformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
21310 const X86Subtarget *Subtarget) {
21311 SDLoc dl(N);
21312 SDValue Cond = N->getOperand(0);
21313 SDValue LHS = N->getOperand(1);
21314 SDValue RHS = N->getOperand(2);
21316 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
21317 SDValue CondSrc = Cond->getOperand(0);
21318 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
21319 Cond = CondSrc->getOperand(0);
21320 }
21322 MVT VT = N->getSimpleValueType(0);
21323 MVT EltVT = VT.getVectorElementType();
21324 unsigned NumElems = VT.getVectorNumElements();
21325 // There is no blend with immediate in AVX-512.
21326 if (VT.is512BitVector())
21327 return SDValue();
21329 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
21330 return SDValue();
21331 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
21332 return SDValue();
21334 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
21335 return SDValue();
21337 // A vselect where all conditions and data are constants can be optimized into
21338 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
21339 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
21340 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
21341 return SDValue();
21343 unsigned MaskValue = 0;
21344 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
21345 return SDValue();
21347 SmallVector<int, 8> ShuffleMask(NumElems, -1);
21348 for (unsigned i = 0; i < NumElems; ++i) {
21349 // Be sure we emit undef where we can.
21350 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
21351 ShuffleMask[i] = -1;
21352 else
21353 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
21354 }
21356 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
21357 }
21359 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
21360 /// nodes.
21361 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
21362 TargetLowering::DAGCombinerInfo &DCI,
21363 const X86Subtarget *Subtarget) {
21364 SDLoc DL(N);
21365 SDValue Cond = N->getOperand(0);
21366 // Get the LHS/RHS of the select.
21367 SDValue LHS = N->getOperand(1);
21368 SDValue RHS = N->getOperand(2);
21369 EVT VT = LHS.getValueType();
21370 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21372 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
21373 // instructions match the semantics of the common C idiom x<y?x:y but not
21374 // x<=y?x:y, because of how they handle negative zero (which can be
21375 // ignored in unsafe-math mode).
21376 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
21377 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
21378 (Subtarget->hasSSE2() ||
21379 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
21380 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21382 unsigned Opcode = 0;
21383 // Check for x CC y ? x : y.
21384 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21385 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21386 switch (CC) {
21387 default: break;
21388 case ISD::SETULT:
21389 // Converting this to a min would handle NaNs incorrectly, and swapping
21390 // the operands would cause it to handle comparisons between positive
21391 // and negative zero incorrectly.
21392 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21393 if (!DAG.getTarget().Options.UnsafeFPMath &&
21394 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21395 break;
21396 std::swap(LHS, RHS);
21397 }
21398 Opcode = X86ISD::FMIN;
21399 break;
21400 case ISD::SETOLE:
21401 // Converting this to a min would handle comparisons between positive
21402 // and negative zero incorrectly.
21403 if (!DAG.getTarget().Options.UnsafeFPMath &&
21404 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21405 break;
21406 Opcode = X86ISD::FMIN;
21407 break;
21408 case ISD::SETULE:
21409 // Converting this to a min would handle both negative zeros and NaNs
21410 // incorrectly, but we can swap the operands to fix both.
21411 std::swap(LHS, RHS);
21412 case ISD::SETOLT:
21413 case ISD::SETLT:
21414 case ISD::SETLE:
21415 Opcode = X86ISD::FMIN;
21416 break;
21418 case ISD::SETOGE:
21419 // Converting this to a max would handle comparisons between positive
21420 // and negative zero incorrectly.
21421 if (!DAG.getTarget().Options.UnsafeFPMath &&
21422 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21423 break;
21424 Opcode = X86ISD::FMAX;
21425 break;
21426 case ISD::SETUGT:
21427 // Converting this to a max would handle NaNs incorrectly, and swapping
21428 // the operands would cause it to handle comparisons between positive
21429 // and negative zero incorrectly.
21430 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21431 if (!DAG.getTarget().Options.UnsafeFPMath &&
21432 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21433 break;
21434 std::swap(LHS, RHS);
21435 }
21436 Opcode = X86ISD::FMAX;
21437 break;
21438 case ISD::SETUGE:
21439 // Converting this to a max would handle both negative zeros and NaNs
21440 // incorrectly, but we can swap the operands to fix both.
21441 std::swap(LHS, RHS);
21442 case ISD::SETOGT:
21443 case ISD::SETGT:
21444 case ISD::SETGE:
21445 Opcode = X86ISD::FMAX;
21446 break;
21447 }
21448 // Check for x CC y ? y : x -- a min/max with reversed arms.
21449 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21450 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21451 switch (CC) {
21452 default: break;
21453 case ISD::SETOGE:
21454 // Converting this to a min would handle comparisons between positive
21455 // and negative zero incorrectly, and swapping the operands would
21456 // cause it to handle NaNs incorrectly.
21457 if (!DAG.getTarget().Options.UnsafeFPMath &&
21458 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
21459 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21460 break;
21461 std::swap(LHS, RHS);
21462 }
21463 Opcode = X86ISD::FMIN;
21464 break;
21465 case ISD::SETUGT:
21466 // Converting this to a min would handle NaNs incorrectly.
21467 if (!DAG.getTarget().Options.UnsafeFPMath &&
21468 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
21469 break;
21470 Opcode = X86ISD::FMIN;
21471 break;
21472 case ISD::SETUGE:
21473 // Converting this to a min would handle both negative zeros and NaNs
21474 // incorrectly, but we can swap the operands to fix both.
21475 std::swap(LHS, RHS);
21476 case ISD::SETOGT:
21477 case ISD::SETGT:
21478 case ISD::SETGE:
21479 Opcode = X86ISD::FMIN;
21480 break;
21482 case ISD::SETULT:
21483 // Converting this to a max would handle NaNs incorrectly.
21484 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21485 break;
21486 Opcode = X86ISD::FMAX;
21487 break;
21488 case ISD::SETOLE:
21489 // Converting this to a max would handle comparisons between positive
21490 // and negative zero incorrectly, and swapping the operands would
21491 // cause it to handle NaNs incorrectly.
21492 if (!DAG.getTarget().Options.UnsafeFPMath &&
21493 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
21494 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21495 break;
21496 std::swap(LHS, RHS);
21497 }
21498 Opcode = X86ISD::FMAX;
21499 break;
21500 case ISD::SETULE:
21501 // Converting this to a max would handle both negative zeros and NaNs
21502 // incorrectly, but we can swap the operands to fix both.
21503 std::swap(LHS, RHS);
21504 case ISD::SETOLT:
21505 case ISD::SETLT:
21506 case ISD::SETLE:
21507 Opcode = X86ISD::FMAX;
21508 break;
21509 }
21510 }
21512 if (Opcode)
21513 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
21514 }
21516 EVT CondVT = Cond.getValueType();
21517 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
21518 CondVT.getVectorElementType() == MVT::i1) {
21519 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
21520 // lowering on KNL. In this case we convert it to
21521 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
21522 // The same situation for all 128 and 256-bit vectors of i8 and i16.
21523 // Since SKX these selects have a proper lowering.
21524 EVT OpVT = LHS.getValueType();
21525 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
21526 (OpVT.getVectorElementType() == MVT::i8 ||
21527 OpVT.getVectorElementType() == MVT::i16) &&
21528 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
21529 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
21530 DCI.AddToWorklist(Cond.getNode());
21531 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
21532 }
21533 }
21534 // If this is a select between two integer constants, try to do some
21535 // optimizations.
21536 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
21537 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
21538 // Don't do this for crazy integer types.
21539 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
21540 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
21541 // so that TrueC (the true value) is larger than FalseC.
21542 bool NeedsCondInvert = false;
21544 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
21545 // Efficiently invertible.
21546 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
21547 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
21548 isa<ConstantSDNode>(Cond.getOperand(1))))) {
21549 NeedsCondInvert = true;
21550 std::swap(TrueC, FalseC);
21551 }
21553 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
21554 if (FalseC->getAPIntValue() == 0 &&
21555 TrueC->getAPIntValue().isPowerOf2()) {
21556 if (NeedsCondInvert) // Invert the condition if needed.
21557 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21558 DAG.getConstant(1, Cond.getValueType()));
21560 // Zero extend the condition if needed.
21561 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
21563 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
21564 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
21565 DAG.getConstant(ShAmt, MVT::i8));
21566 }
21568 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
21569 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
21570 if (NeedsCondInvert) // Invert the condition if needed.
21571 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21572 DAG.getConstant(1, Cond.getValueType()));
21574 // Zero extend the condition if needed.
21575 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
21576 FalseC->getValueType(0), Cond);
21577 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21578 SDValue(FalseC, 0));
21579 }
21581 // Optimize cases that will turn into an LEA instruction. This requires
21582 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
21583 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
21584 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
21585 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
21587 bool isFastMultiplier = false;
21588 if (Diff < 10) {
21589 switch ((unsigned char)Diff) {
21590 default: break;
21591 case 1: // result = add base, cond
21592 case 2: // result = lea base( , cond*2)
21593 case 3: // result = lea base(cond, cond*2)
21594 case 4: // result = lea base( , cond*4)
21595 case 5: // result = lea base(cond, cond*4)
21596 case 8: // result = lea base( , cond*8)
21597 case 9: // result = lea base(cond, cond*8)
21598 isFastMultiplier = true;
21599 break;
21600 }
21601 }
21603 if (isFastMultiplier) {
21604 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
21605 if (NeedsCondInvert) // Invert the condition if needed.
21606 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21607 DAG.getConstant(1, Cond.getValueType()));
21609 // Zero extend the condition if needed.
21610 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
21611 Cond);
21612 // Scale the condition by the difference.
21613 if (Diff != 1)
21614 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
21615 DAG.getConstant(Diff, Cond.getValueType()));
21617 // Add the base if non-zero.
21618 if (FalseC->getAPIntValue() != 0)
21619 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21620 SDValue(FalseC, 0));
21621 return Cond;
21622 }
21623 }
21624 }
21625 }
21627 // Canonicalize max and min:
21628 // (x > y) ? x : y -> (x >= y) ? x : y
21629 // (x < y) ? x : y -> (x <= y) ? x : y
21630 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
21631 // the need for an extra compare
21632 // against zero. e.g.
21633 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
21634 // subl %esi, %edi
21635 // testl %edi, %edi
21636 // movl $0, %eax
21637 // cmovgl %edi, %eax
21638 // =>
21639 // xorl %eax, %eax
21640 // subl %esi, $edi
21641 // cmovsl %eax, %edi
21642 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
21643 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21644 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21645 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21646 switch (CC) {
21647 default: break;
21648 case ISD::SETLT:
21649 case ISD::SETGT: {
21650 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
21651 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
21652 Cond.getOperand(0), Cond.getOperand(1), NewCC);
21653 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
21654 }
21655 }
21656 }
21658 // Early exit check
21659 if (!TLI.isTypeLegal(VT))
21660 return SDValue();
21662 // Match VSELECTs into subs with unsigned saturation.
21663 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
21664 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
21665 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
21666 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
21667 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21669 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
21670 // left side invert the predicate to simplify logic below.
21671 SDValue Other;
21672 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
21673 Other = RHS;
21674 CC = ISD::getSetCCInverse(CC, true);
21675 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
21676 Other = LHS;
21677 }
21679 if (Other.getNode() && Other->getNumOperands() == 2 &&
21680 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
21681 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
21682 SDValue CondRHS = Cond->getOperand(1);
21684 // Look for a general sub with unsigned saturation first.
21685 // x >= y ? x-y : 0 --> subus x, y
21686 // x > y ? x-y : 0 --> subus x, y
21687 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
21688 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
21689 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
21691 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
21692 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
21693 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
21694 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
21695 // If the RHS is a constant we have to reverse the const
21696 // canonicalization.
21697 // x > C-1 ? x+-C : 0 --> subus x, C
21698 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
21699 CondRHSConst->getAPIntValue() ==
21700 (-OpRHSConst->getAPIntValue() - 1))
21701 return DAG.getNode(
21702 X86ISD::SUBUS, DL, VT, OpLHS,
21703 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
21705 // Another special case: If C was a sign bit, the sub has been
21706 // canonicalized into a xor.
21707 // FIXME: Would it be better to use computeKnownBits to determine
21708 // whether it's safe to decanonicalize the xor?
21709 // x s< 0 ? x^C : 0 --> subus x, C
21710 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
21711 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
21712 OpRHSConst->getAPIntValue().isSignBit())
21713 // Note that we have to rebuild the RHS constant here to ensure we
21714 // don't rely on particular values of undef lanes.
21715 return DAG.getNode(
21716 X86ISD::SUBUS, DL, VT, OpLHS,
21717 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
21718 }
21719 }
21720 }
21722 // Try to match a min/max vector operation.
21723 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
21724 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
21725 unsigned Opc = ret.first;
21726 bool NeedSplit = ret.second;
21728 if (Opc && NeedSplit) {
21729 unsigned NumElems = VT.getVectorNumElements();
21730 // Extract the LHS vectors
21731 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
21732 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
21734 // Extract the RHS vectors
21735 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
21736 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
21738 // Create min/max for each subvector
21739 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
21740 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
21742 // Merge the result
21743 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
21744 } else if (Opc)
21745 return DAG.getNode(Opc, DL, VT, LHS, RHS);
21746 }
21748 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
21749 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
21750 // Check if SETCC has already been promoted
21751 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT &&
21752 // Check that condition value type matches vselect operand type
21753 CondVT == VT) {
21755 assert(Cond.getValueType().isVector() &&
21756 "vector select expects a vector selector!");
21758 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
21759 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
21761 if (!TValIsAllOnes && !FValIsAllZeros) {
21762 // Try invert the condition if true value is not all 1s and false value
21763 // is not all 0s.
21764 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
21765 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
21767 if (TValIsAllZeros || FValIsAllOnes) {
21768 SDValue CC = Cond.getOperand(2);
21769 ISD::CondCode NewCC =
21770 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
21771 Cond.getOperand(0).getValueType().isInteger());
21772 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
21773 std::swap(LHS, RHS);
21774 TValIsAllOnes = FValIsAllOnes;
21775 FValIsAllZeros = TValIsAllZeros;
21776 }
21777 }
21779 if (TValIsAllOnes || FValIsAllZeros) {
21780 SDValue Ret;
21782 if (TValIsAllOnes && FValIsAllZeros)
21783 Ret = Cond;
21784 else if (TValIsAllOnes)
21785 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
21786 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
21787 else if (FValIsAllZeros)
21788 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
21789 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
21791 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
21792 }
21793 }
21795 // Try to fold this VSELECT into a MOVSS/MOVSD
21796 if (N->getOpcode() == ISD::VSELECT &&
21797 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
21798 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
21799 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
21800 bool CanFold = false;
21801 unsigned NumElems = Cond.getNumOperands();
21802 SDValue A = LHS;
21803 SDValue B = RHS;
21805 if (isZero(Cond.getOperand(0))) {
21806 CanFold = true;
21808 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
21809 // fold (vselect <0,-1> -> (movsd A, B)
21810 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
21811 CanFold = isAllOnes(Cond.getOperand(i));
21812 } else if (isAllOnes(Cond.getOperand(0))) {
21813 CanFold = true;
21814 std::swap(A, B);
21816 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
21817 // fold (vselect <-1,0> -> (movsd B, A)
21818 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
21819 CanFold = isZero(Cond.getOperand(i));
21820 }
21822 if (CanFold) {
21823 if (VT == MVT::v4i32 || VT == MVT::v4f32)
21824 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
21825 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
21826 }
21828 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
21829 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
21830 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
21831 // (v2i64 (bitcast B)))))
21832 //
21833 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
21834 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
21835 // (v2f64 (bitcast B)))))
21836 //
21837 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
21838 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
21839 // (v2i64 (bitcast A)))))
21840 //
21841 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
21842 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
21843 // (v2f64 (bitcast A)))))
21845 CanFold = (isZero(Cond.getOperand(0)) &&
21846 isZero(Cond.getOperand(1)) &&
21847 isAllOnes(Cond.getOperand(2)) &&
21848 isAllOnes(Cond.getOperand(3)));
21850 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
21851 isAllOnes(Cond.getOperand(1)) &&
21852 isZero(Cond.getOperand(2)) &&
21853 isZero(Cond.getOperand(3))) {
21854 CanFold = true;
21855 std::swap(LHS, RHS);
21856 }
21858 if (CanFold) {
21859 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
21860 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
21861 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
21862 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
21863 NewB, DAG);
21864 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
21865 }
21866 }
21867 }
21868 }
21870 // If we know that this node is legal then we know that it is going to be
21871 // matched by one of the SSE/AVX BLEND instructions. These instructions only
21872 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
21873 // to simplify previous instructions.
21874 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
21875 !DCI.isBeforeLegalize() &&
21876 // We explicitly check against v8i16 and v16i16 because, although
21877 // they're marked as Custom, they might only be legal when Cond is a
21878 // build_vector of constants. This will be taken care in a later
21879 // condition.
21880 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
21881 VT != MVT::v8i16)) {
21882 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
21884 // Don't optimize vector selects that map to mask-registers.
21885 if (BitWidth == 1)
21886 return SDValue();
21888 // Check all uses of that condition operand to check whether it will be
21889 // consumed by non-BLEND instructions, which may depend on all bits are set
21890 // properly.
21891 for (SDNode::use_iterator I = Cond->use_begin(),
21892 E = Cond->use_end(); I != E; ++I)
21893 if (I->getOpcode() != ISD::VSELECT)
21894 // TODO: Add other opcodes eventually lowered into BLEND.
21895 return SDValue();
21897 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
21898 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
21900 APInt KnownZero, KnownOne;
21901 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
21902 DCI.isBeforeLegalizeOps());
21903 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
21904 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
21905 DCI.CommitTargetLoweringOpt(TLO);
21906 }
21908 // We should generate an X86ISD::BLENDI from a vselect if its argument
21909 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
21910 // constants. This specific pattern gets generated when we split a
21911 // selector for a 512 bit vector in a machine without AVX512 (but with
21912 // 256-bit vectors), during legalization:
21913 //
21914 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
21915 //
21916 // Iff we find this pattern and the build_vectors are built from
21917 // constants, we translate the vselect into a shuffle_vector that we
21918 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
21919 if (N->getOpcode() == ISD::VSELECT && !DCI.isBeforeLegalize()) {
21920 SDValue Shuffle = TransformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
21921 if (Shuffle.getNode())
21922 return Shuffle;
21923 }
21925 return SDValue();
21926 }
21928 // Check whether a boolean test is testing a boolean value generated by
21929 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
21930 // code.
21931 //
21932 // Simplify the following patterns:
21933 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
21934 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
21935 // to (Op EFLAGS Cond)
21936 //
21937 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
21938 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
21939 // to (Op EFLAGS !Cond)
21940 //
21941 // where Op could be BRCOND or CMOV.
21942 //
21943 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
21944 // Quit if not CMP and SUB with its value result used.
21945 if (Cmp.getOpcode() != X86ISD::CMP &&
21946 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
21947 return SDValue();
21949 // Quit if not used as a boolean value.
21950 if (CC != X86::COND_E && CC != X86::COND_NE)
21951 return SDValue();
21953 // Check CMP operands. One of them should be 0 or 1 and the other should be
21954 // an SetCC or extended from it.
21955 SDValue Op1 = Cmp.getOperand(0);
21956 SDValue Op2 = Cmp.getOperand(1);
21958 SDValue SetCC;
21959 const ConstantSDNode* C = nullptr;
21960 bool needOppositeCond = (CC == X86::COND_E);
21961 bool checkAgainstTrue = false; // Is it a comparison against 1?
21963 if ((C = dyn_cast<ConstantSDNode>(Op1)))
21964 SetCC = Op2;
21965 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
21966 SetCC = Op1;
21967 else // Quit if all operands are not constants.
21968 return SDValue();
21970 if (C->getZExtValue() == 1) {
21971 needOppositeCond = !needOppositeCond;
21972 checkAgainstTrue = true;
21973 } else if (C->getZExtValue() != 0)
21974 // Quit if the constant is neither 0 or 1.
21975 return SDValue();
21977 bool truncatedToBoolWithAnd = false;
21978 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
21979 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
21980 SetCC.getOpcode() == ISD::TRUNCATE ||
21981 SetCC.getOpcode() == ISD::AND) {
21982 if (SetCC.getOpcode() == ISD::AND) {
21983 int OpIdx = -1;
21984 ConstantSDNode *CS;
21985 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
21986 CS->getZExtValue() == 1)
21987 OpIdx = 1;
21988 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
21989 CS->getZExtValue() == 1)
21990 OpIdx = 0;
21991 if (OpIdx == -1)
21992 break;
21993 SetCC = SetCC.getOperand(OpIdx);
21994 truncatedToBoolWithAnd = true;
21995 } else
21996 SetCC = SetCC.getOperand(0);
21997 }
21999 switch (SetCC.getOpcode()) {
22000 case X86ISD::SETCC_CARRY:
22001 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
22002 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
22003 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
22004 // truncated to i1 using 'and'.
22005 if (checkAgainstTrue && !truncatedToBoolWithAnd)
22006 break;
22007 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
22008 "Invalid use of SETCC_CARRY!");
22009 // FALL THROUGH
22010 case X86ISD::SETCC:
22011 // Set the condition code or opposite one if necessary.
22012 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
22013 if (needOppositeCond)
22014 CC = X86::GetOppositeBranchCondition(CC);
22015 return SetCC.getOperand(1);
22016 case X86ISD::CMOV: {
22017 // Check whether false/true value has canonical one, i.e. 0 or 1.
22018 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
22019 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
22020 // Quit if true value is not a constant.
22021 if (!TVal)
22022 return SDValue();
22023 // Quit if false value is not a constant.
22024 if (!FVal) {
22025 SDValue Op = SetCC.getOperand(0);
22026 // Skip 'zext' or 'trunc' node.
22027 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
22028 Op.getOpcode() == ISD::TRUNCATE)
22029 Op = Op.getOperand(0);
22030 // A special case for rdrand/rdseed, where 0 is set if false cond is
22031 // found.
22032 if ((Op.getOpcode() != X86ISD::RDRAND &&
22033 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
22034 return SDValue();
22035 }
22036 // Quit if false value is not the constant 0 or 1.
22037 bool FValIsFalse = true;
22038 if (FVal && FVal->getZExtValue() != 0) {
22039 if (FVal->getZExtValue() != 1)
22040 return SDValue();
22041 // If FVal is 1, opposite cond is needed.
22042 needOppositeCond = !needOppositeCond;
22043 FValIsFalse = false;
22044 }
22045 // Quit if TVal is not the constant opposite of FVal.
22046 if (FValIsFalse && TVal->getZExtValue() != 1)
22047 return SDValue();
22048 if (!FValIsFalse && TVal->getZExtValue() != 0)
22049 return SDValue();
22050 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
22051 if (needOppositeCond)
22052 CC = X86::GetOppositeBranchCondition(CC);
22053 return SetCC.getOperand(3);
22054 }
22055 }
22057 return SDValue();
22058 }
22060 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
22061 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
22062 TargetLowering::DAGCombinerInfo &DCI,
22063 const X86Subtarget *Subtarget) {
22064 SDLoc DL(N);
22066 // If the flag operand isn't dead, don't touch this CMOV.
22067 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
22068 return SDValue();
22070 SDValue FalseOp = N->getOperand(0);
22071 SDValue TrueOp = N->getOperand(1);
22072 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
22073 SDValue Cond = N->getOperand(3);
22075 if (CC == X86::COND_E || CC == X86::COND_NE) {
22076 switch (Cond.getOpcode()) {
22077 default: break;
22078 case X86ISD::BSR:
22079 case X86ISD::BSF:
22080 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
22081 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
22082 return (CC == X86::COND_E) ? FalseOp : TrueOp;
22083 }
22084 }
22086 SDValue Flags;
22088 Flags = checkBoolTestSetCCCombine(Cond, CC);
22089 if (Flags.getNode() &&
22090 // Extra check as FCMOV only supports a subset of X86 cond.
22091 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
22092 SDValue Ops[] = { FalseOp, TrueOp,
22093 DAG.getConstant(CC, MVT::i8), Flags };
22094 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
22095 }
22097 // If this is a select between two integer constants, try to do some
22098 // optimizations. Note that the operands are ordered the opposite of SELECT
22099 // operands.
22100 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
22101 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
22102 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
22103 // larger than FalseC (the false value).
22104 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
22105 CC = X86::GetOppositeBranchCondition(CC);
22106 std::swap(TrueC, FalseC);
22107 std::swap(TrueOp, FalseOp);
22108 }
22110 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
22111 // This is efficient for any integer data type (including i8/i16) and
22112 // shift amount.
22113 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
22114 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22115 DAG.getConstant(CC, MVT::i8), Cond);
22117 // Zero extend the condition if needed.
22118 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
22120 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22121 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
22122 DAG.getConstant(ShAmt, MVT::i8));
22123 if (N->getNumValues() == 2) // Dead flag value?
22124 return DCI.CombineTo(N, Cond, SDValue());
22125 return Cond;
22126 }
22128 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
22129 // for any integer data type, including i8/i16.
22130 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22131 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22132 DAG.getConstant(CC, MVT::i8), Cond);
22134 // Zero extend the condition if needed.
22135 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22136 FalseC->getValueType(0), Cond);
22137 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22138 SDValue(FalseC, 0));
22140 if (N->getNumValues() == 2) // Dead flag value?
22141 return DCI.CombineTo(N, Cond, SDValue());
22142 return Cond;
22143 }
22145 // Optimize cases that will turn into an LEA instruction. This requires
22146 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22147 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22148 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22149 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22151 bool isFastMultiplier = false;
22152 if (Diff < 10) {
22153 switch ((unsigned char)Diff) {
22154 default: break;
22155 case 1: // result = add base, cond
22156 case 2: // result = lea base( , cond*2)
22157 case 3: // result = lea base(cond, cond*2)
22158 case 4: // result = lea base( , cond*4)
22159 case 5: // result = lea base(cond, cond*4)
22160 case 8: // result = lea base( , cond*8)
22161 case 9: // result = lea base(cond, cond*8)
22162 isFastMultiplier = true;
22163 break;
22164 }
22165 }
22167 if (isFastMultiplier) {
22168 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22169 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22170 DAG.getConstant(CC, MVT::i8), Cond);
22171 // Zero extend the condition if needed.
22172 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22173 Cond);
22174 // Scale the condition by the difference.
22175 if (Diff != 1)
22176 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22177 DAG.getConstant(Diff, Cond.getValueType()));
22179 // Add the base if non-zero.
22180 if (FalseC->getAPIntValue() != 0)
22181 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22182 SDValue(FalseC, 0));
22183 if (N->getNumValues() == 2) // Dead flag value?
22184 return DCI.CombineTo(N, Cond, SDValue());
22185 return Cond;
22186 }
22187 }
22188 }
22189 }
22191 // Handle these cases:
22192 // (select (x != c), e, c) -> select (x != c), e, x),
22193 // (select (x == c), c, e) -> select (x == c), x, e)
22194 // where the c is an integer constant, and the "select" is the combination
22195 // of CMOV and CMP.
22196 //
22197 // The rationale for this change is that the conditional-move from a constant
22198 // needs two instructions, however, conditional-move from a register needs
22199 // only one instruction.
22200 //
22201 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
22202 // some instruction-combining opportunities. This opt needs to be
22203 // postponed as late as possible.
22204 //
22205 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
22206 // the DCI.xxxx conditions are provided to postpone the optimization as
22207 // late as possible.
22209 ConstantSDNode *CmpAgainst = nullptr;
22210 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
22211 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
22212 !isa<ConstantSDNode>(Cond.getOperand(0))) {
22214 if (CC == X86::COND_NE &&
22215 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
22216 CC = X86::GetOppositeBranchCondition(CC);
22217 std::swap(TrueOp, FalseOp);
22218 }
22220 if (CC == X86::COND_E &&
22221 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
22222 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
22223 DAG.getConstant(CC, MVT::i8), Cond };
22224 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
22225 }
22226 }
22227 }
22229 return SDValue();
22230 }
22232 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
22233 const X86Subtarget *Subtarget) {
22234 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
22235 switch (IntNo) {
22236 default: return SDValue();
22237 // SSE/AVX/AVX2 blend intrinsics.
22238 case Intrinsic::x86_avx2_pblendvb:
22239 case Intrinsic::x86_avx2_pblendw:
22240 case Intrinsic::x86_avx2_pblendd_128:
22241 case Intrinsic::x86_avx2_pblendd_256:
22242 // Don't try to simplify this intrinsic if we don't have AVX2.
22243 if (!Subtarget->hasAVX2())
22244 return SDValue();
22245 // FALL-THROUGH
22246 case Intrinsic::x86_avx_blend_pd_256:
22247 case Intrinsic::x86_avx_blend_ps_256:
22248 case Intrinsic::x86_avx_blendv_pd_256:
22249 case Intrinsic::x86_avx_blendv_ps_256:
22250 // Don't try to simplify this intrinsic if we don't have AVX.
22251 if (!Subtarget->hasAVX())
22252 return SDValue();
22253 // FALL-THROUGH
22254 case Intrinsic::x86_sse41_pblendw:
22255 case Intrinsic::x86_sse41_blendpd:
22256 case Intrinsic::x86_sse41_blendps:
22257 case Intrinsic::x86_sse41_blendvps:
22258 case Intrinsic::x86_sse41_blendvpd:
22259 case Intrinsic::x86_sse41_pblendvb: {
22260 SDValue Op0 = N->getOperand(1);
22261 SDValue Op1 = N->getOperand(2);
22262 SDValue Mask = N->getOperand(3);
22264 // Don't try to simplify this intrinsic if we don't have SSE4.1.
22265 if (!Subtarget->hasSSE41())
22266 return SDValue();
22268 // fold (blend A, A, Mask) -> A
22269 if (Op0 == Op1)
22270 return Op0;
22271 // fold (blend A, B, allZeros) -> A
22272 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
22273 return Op0;
22274 // fold (blend A, B, allOnes) -> B
22275 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
22276 return Op1;
22278 // Simplify the case where the mask is a constant i32 value.
22279 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
22280 if (C->isNullValue())
22281 return Op0;
22282 if (C->isAllOnesValue())
22283 return Op1;
22284 }
22286 return SDValue();
22287 }
22289 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
22290 case Intrinsic::x86_sse2_psrai_w:
22291 case Intrinsic::x86_sse2_psrai_d:
22292 case Intrinsic::x86_avx2_psrai_w:
22293 case Intrinsic::x86_avx2_psrai_d:
22294 case Intrinsic::x86_sse2_psra_w:
22295 case Intrinsic::x86_sse2_psra_d:
22296 case Intrinsic::x86_avx2_psra_w:
22297 case Intrinsic::x86_avx2_psra_d: {
22298 SDValue Op0 = N->getOperand(1);
22299 SDValue Op1 = N->getOperand(2);
22300 EVT VT = Op0.getValueType();
22301 assert(VT.isVector() && "Expected a vector type!");
22303 if (isa<BuildVectorSDNode>(Op1))
22304 Op1 = Op1.getOperand(0);
22306 if (!isa<ConstantSDNode>(Op1))
22307 return SDValue();
22309 EVT SVT = VT.getVectorElementType();
22310 unsigned SVTBits = SVT.getSizeInBits();
22312 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
22313 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
22314 uint64_t ShAmt = C.getZExtValue();
22316 // Don't try to convert this shift into a ISD::SRA if the shift
22317 // count is bigger than or equal to the element size.
22318 if (ShAmt >= SVTBits)
22319 return SDValue();
22321 // Trivial case: if the shift count is zero, then fold this
22322 // into the first operand.
22323 if (ShAmt == 0)
22324 return Op0;
22326 // Replace this packed shift intrinsic with a target independent
22327 // shift dag node.
22328 SDValue Splat = DAG.getConstant(C, VT);
22329 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
22330 }
22331 }
22332 }
22334 /// PerformMulCombine - Optimize a single multiply with constant into two
22335 /// in order to implement it with two cheaper instructions, e.g.
22336 /// LEA + SHL, LEA + LEA.
22337 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
22338 TargetLowering::DAGCombinerInfo &DCI) {
22339 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
22340 return SDValue();
22342 EVT VT = N->getValueType(0);
22343 if (VT != MVT::i64)
22344 return SDValue();
22346 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
22347 if (!C)
22348 return SDValue();
22349 uint64_t MulAmt = C->getZExtValue();
22350 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
22351 return SDValue();
22353 uint64_t MulAmt1 = 0;
22354 uint64_t MulAmt2 = 0;
22355 if ((MulAmt % 9) == 0) {
22356 MulAmt1 = 9;
22357 MulAmt2 = MulAmt / 9;
22358 } else if ((MulAmt % 5) == 0) {
22359 MulAmt1 = 5;
22360 MulAmt2 = MulAmt / 5;
22361 } else if ((MulAmt % 3) == 0) {
22362 MulAmt1 = 3;
22363 MulAmt2 = MulAmt / 3;
22364 }
22365 if (MulAmt2 &&
22366 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
22367 SDLoc DL(N);
22369 if (isPowerOf2_64(MulAmt2) &&
22370 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
22371 // If second multiplifer is pow2, issue it first. We want the multiply by
22372 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
22373 // is an add.
22374 std::swap(MulAmt1, MulAmt2);
22376 SDValue NewMul;
22377 if (isPowerOf2_64(MulAmt1))
22378 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
22379 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
22380 else
22381 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
22382 DAG.getConstant(MulAmt1, VT));
22384 if (isPowerOf2_64(MulAmt2))
22385 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
22386 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
22387 else
22388 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
22389 DAG.getConstant(MulAmt2, VT));
22391 // Do not add new nodes to DAG combiner worklist.
22392 DCI.CombineTo(N, NewMul, false);
22393 }
22394 return SDValue();
22395 }
22397 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
22398 SDValue N0 = N->getOperand(0);
22399 SDValue N1 = N->getOperand(1);
22400 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
22401 EVT VT = N0.getValueType();
22403 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
22404 // since the result of setcc_c is all zero's or all ones.
22405 if (VT.isInteger() && !VT.isVector() &&
22406 N1C && N0.getOpcode() == ISD::AND &&
22407 N0.getOperand(1).getOpcode() == ISD::Constant) {
22408 SDValue N00 = N0.getOperand(0);
22409 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
22410 ((N00.getOpcode() == ISD::ANY_EXTEND ||
22411 N00.getOpcode() == ISD::ZERO_EXTEND) &&
22412 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
22413 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
22414 APInt ShAmt = N1C->getAPIntValue();
22415 Mask = Mask.shl(ShAmt);
22416 if (Mask != 0)
22417 return DAG.getNode(ISD::AND, SDLoc(N), VT,
22418 N00, DAG.getConstant(Mask, VT));
22419 }
22420 }
22422 // Hardware support for vector shifts is sparse which makes us scalarize the
22423 // vector operations in many cases. Also, on sandybridge ADD is faster than
22424 // shl.
22425 // (shl V, 1) -> add V,V
22426 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
22427 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
22428 assert(N0.getValueType().isVector() && "Invalid vector shift type");
22429 // We shift all of the values by one. In many cases we do not have
22430 // hardware support for this operation. This is better expressed as an ADD
22431 // of two values.
22432 if (N1SplatC->getZExtValue() == 1)
22433 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
22434 }
22436 return SDValue();
22437 }
22439 /// \brief Returns a vector of 0s if the node in input is a vector logical
22440 /// shift by a constant amount which is known to be bigger than or equal
22441 /// to the vector element size in bits.
22442 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
22443 const X86Subtarget *Subtarget) {
22444 EVT VT = N->getValueType(0);
22446 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
22447 (!Subtarget->hasInt256() ||
22448 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
22449 return SDValue();
22451 SDValue Amt = N->getOperand(1);
22452 SDLoc DL(N);
22453 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
22454 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
22455 APInt ShiftAmt = AmtSplat->getAPIntValue();
22456 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
22458 // SSE2/AVX2 logical shifts always return a vector of 0s
22459 // if the shift amount is bigger than or equal to
22460 // the element size. The constant shift amount will be
22461 // encoded as a 8-bit immediate.
22462 if (ShiftAmt.trunc(8).uge(MaxAmount))
22463 return getZeroVector(VT, Subtarget, DAG, DL);
22464 }
22466 return SDValue();
22467 }
22469 /// PerformShiftCombine - Combine shifts.
22470 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
22471 TargetLowering::DAGCombinerInfo &DCI,
22472 const X86Subtarget *Subtarget) {
22473 if (N->getOpcode() == ISD::SHL) {
22474 SDValue V = PerformSHLCombine(N, DAG);
22475 if (V.getNode()) return V;
22476 }
22478 if (N->getOpcode() != ISD::SRA) {
22479 // Try to fold this logical shift into a zero vector.
22480 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
22481 if (V.getNode()) return V;
22482 }
22484 return SDValue();
22485 }
22487 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
22488 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
22489 // and friends. Likewise for OR -> CMPNEQSS.
22490 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
22491 TargetLowering::DAGCombinerInfo &DCI,
22492 const X86Subtarget *Subtarget) {
22493 unsigned opcode;
22495 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
22496 // we're requiring SSE2 for both.
22497 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
22498 SDValue N0 = N->getOperand(0);
22499 SDValue N1 = N->getOperand(1);
22500 SDValue CMP0 = N0->getOperand(1);
22501 SDValue CMP1 = N1->getOperand(1);
22502 SDLoc DL(N);
22504 // The SETCCs should both refer to the same CMP.
22505 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
22506 return SDValue();
22508 SDValue CMP00 = CMP0->getOperand(0);
22509 SDValue CMP01 = CMP0->getOperand(1);
22510 EVT VT = CMP00.getValueType();
22512 if (VT == MVT::f32 || VT == MVT::f64) {
22513 bool ExpectingFlags = false;
22514 // Check for any users that want flags:
22515 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
22516 !ExpectingFlags && UI != UE; ++UI)
22517 switch (UI->getOpcode()) {
22518 default:
22519 case ISD::BR_CC:
22520 case ISD::BRCOND:
22521 case ISD::SELECT:
22522 ExpectingFlags = true;
22523 break;
22524 case ISD::CopyToReg:
22525 case ISD::SIGN_EXTEND:
22526 case ISD::ZERO_EXTEND:
22527 case ISD::ANY_EXTEND:
22528 break;
22529 }
22531 if (!ExpectingFlags) {
22532 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
22533 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
22535 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
22536 X86::CondCode tmp = cc0;
22537 cc0 = cc1;
22538 cc1 = tmp;
22539 }
22541 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
22542 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
22543 // FIXME: need symbolic constants for these magic numbers.
22544 // See X86ATTInstPrinter.cpp:printSSECC().
22545 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
22546 if (Subtarget->hasAVX512()) {
22547 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
22548 CMP01, DAG.getConstant(x86cc, MVT::i8));
22549 if (N->getValueType(0) != MVT::i1)
22550 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
22551 FSetCC);
22552 return FSetCC;
22553 }
22554 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
22555 CMP00.getValueType(), CMP00, CMP01,
22556 DAG.getConstant(x86cc, MVT::i8));
22558 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
22559 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
22561 if (is64BitFP && !Subtarget->is64Bit()) {
22562 // On a 32-bit target, we cannot bitcast the 64-bit float to a
22563 // 64-bit integer, since that's not a legal type. Since
22564 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
22565 // bits, but can do this little dance to extract the lowest 32 bits
22566 // and work with those going forward.
22567 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
22568 OnesOrZeroesF);
22569 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
22570 Vector64);
22571 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
22572 Vector32, DAG.getIntPtrConstant(0));
22573 IntVT = MVT::i32;
22574 }
22576 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
22577 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
22578 DAG.getConstant(1, IntVT));
22579 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
22580 return OneBitOfTruth;
22581 }
22582 }
22583 }
22584 }
22585 return SDValue();
22586 }
22588 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
22589 /// so it can be folded inside ANDNP.
22590 static bool CanFoldXORWithAllOnes(const SDNode *N) {
22591 EVT VT = N->getValueType(0);
22593 // Match direct AllOnes for 128 and 256-bit vectors
22594 if (ISD::isBuildVectorAllOnes(N))
22595 return true;
22597 // Look through a bit convert.
22598 if (N->getOpcode() == ISD::BITCAST)
22599 N = N->getOperand(0).getNode();
22601 // Sometimes the operand may come from a insert_subvector building a 256-bit
22602 // allones vector
22603 if (VT.is256BitVector() &&
22604 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
22605 SDValue V1 = N->getOperand(0);
22606 SDValue V2 = N->getOperand(1);
22608 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
22609 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
22610 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
22611 ISD::isBuildVectorAllOnes(V2.getNode()))
22612 return true;
22613 }
22615 return false;
22616 }
22618 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
22619 // register. In most cases we actually compare or select YMM-sized registers
22620 // and mixing the two types creates horrible code. This method optimizes
22621 // some of the transition sequences.
22622 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
22623 TargetLowering::DAGCombinerInfo &DCI,
22624 const X86Subtarget *Subtarget) {
22625 EVT VT = N->getValueType(0);
22626 if (!VT.is256BitVector())
22627 return SDValue();
22629 assert((N->getOpcode() == ISD::ANY_EXTEND ||
22630 N->getOpcode() == ISD::ZERO_EXTEND ||
22631 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
22633 SDValue Narrow = N->getOperand(0);
22634 EVT NarrowVT = Narrow->getValueType(0);
22635 if (!NarrowVT.is128BitVector())
22636 return SDValue();
22638 if (Narrow->getOpcode() != ISD::XOR &&
22639 Narrow->getOpcode() != ISD::AND &&
22640 Narrow->getOpcode() != ISD::OR)
22641 return SDValue();
22643 SDValue N0 = Narrow->getOperand(0);
22644 SDValue N1 = Narrow->getOperand(1);
22645 SDLoc DL(Narrow);
22647 // The Left side has to be a trunc.
22648 if (N0.getOpcode() != ISD::TRUNCATE)
22649 return SDValue();
22651 // The type of the truncated inputs.
22652 EVT WideVT = N0->getOperand(0)->getValueType(0);
22653 if (WideVT != VT)
22654 return SDValue();
22656 // The right side has to be a 'trunc' or a constant vector.
22657 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
22658 ConstantSDNode *RHSConstSplat = nullptr;
22659 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
22660 RHSConstSplat = RHSBV->getConstantSplatNode();
22661 if (!RHSTrunc && !RHSConstSplat)
22662 return SDValue();
22664 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22666 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
22667 return SDValue();
22669 // Set N0 and N1 to hold the inputs to the new wide operation.
22670 N0 = N0->getOperand(0);
22671 if (RHSConstSplat) {
22672 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
22673 SDValue(RHSConstSplat, 0));
22674 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
22675 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
22676 } else if (RHSTrunc) {
22677 N1 = N1->getOperand(0);
22678 }
22680 // Generate the wide operation.
22681 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
22682 unsigned Opcode = N->getOpcode();
22683 switch (Opcode) {
22684 case ISD::ANY_EXTEND:
22685 return Op;
22686 case ISD::ZERO_EXTEND: {
22687 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
22688 APInt Mask = APInt::getAllOnesValue(InBits);
22689 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
22690 return DAG.getNode(ISD::AND, DL, VT,
22691 Op, DAG.getConstant(Mask, VT));
22692 }
22693 case ISD::SIGN_EXTEND:
22694 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
22695 Op, DAG.getValueType(NarrowVT));
22696 default:
22697 llvm_unreachable("Unexpected opcode");
22698 }
22699 }
22701 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
22702 TargetLowering::DAGCombinerInfo &DCI,
22703 const X86Subtarget *Subtarget) {
22704 EVT VT = N->getValueType(0);
22705 if (DCI.isBeforeLegalizeOps())
22706 return SDValue();
22708 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
22709 if (R.getNode())
22710 return R;
22712 // Create BEXTR instructions
22713 // BEXTR is ((X >> imm) & (2**size-1))
22714 if (VT == MVT::i32 || VT == MVT::i64) {
22715 SDValue N0 = N->getOperand(0);
22716 SDValue N1 = N->getOperand(1);
22717 SDLoc DL(N);
22719 // Check for BEXTR.
22720 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
22721 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
22722 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
22723 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
22724 if (MaskNode && ShiftNode) {
22725 uint64_t Mask = MaskNode->getZExtValue();
22726 uint64_t Shift = ShiftNode->getZExtValue();
22727 if (isMask_64(Mask)) {
22728 uint64_t MaskSize = CountPopulation_64(Mask);
22729 if (Shift + MaskSize <= VT.getSizeInBits())
22730 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
22731 DAG.getConstant(Shift | (MaskSize << 8), VT));
22732 }
22733 }
22734 } // BEXTR
22736 return SDValue();
22737 }
22739 // Want to form ANDNP nodes:
22740 // 1) In the hopes of then easily combining them with OR and AND nodes
22741 // to form PBLEND/PSIGN.
22742 // 2) To match ANDN packed intrinsics
22743 if (VT != MVT::v2i64 && VT != MVT::v4i64)
22744 return SDValue();
22746 SDValue N0 = N->getOperand(0);
22747 SDValue N1 = N->getOperand(1);
22748 SDLoc DL(N);
22750 // Check LHS for vnot
22751 if (N0.getOpcode() == ISD::XOR &&
22752 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
22753 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
22754 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
22756 // Check RHS for vnot
22757 if (N1.getOpcode() == ISD::XOR &&
22758 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
22759 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
22760 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
22762 return SDValue();
22763 }
22765 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
22766 TargetLowering::DAGCombinerInfo &DCI,
22767 const X86Subtarget *Subtarget) {
22768 if (DCI.isBeforeLegalizeOps())
22769 return SDValue();
22771 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
22772 if (R.getNode())
22773 return R;
22775 SDValue N0 = N->getOperand(0);
22776 SDValue N1 = N->getOperand(1);
22777 EVT VT = N->getValueType(0);
22779 // look for psign/blend
22780 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
22781 if (!Subtarget->hasSSSE3() ||
22782 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
22783 return SDValue();
22785 // Canonicalize pandn to RHS
22786 if (N0.getOpcode() == X86ISD::ANDNP)
22787 std::swap(N0, N1);
22788 // or (and (m, y), (pandn m, x))
22789 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
22790 SDValue Mask = N1.getOperand(0);
22791 SDValue X = N1.getOperand(1);
22792 SDValue Y;
22793 if (N0.getOperand(0) == Mask)
22794 Y = N0.getOperand(1);
22795 if (N0.getOperand(1) == Mask)
22796 Y = N0.getOperand(0);
22798 // Check to see if the mask appeared in both the AND and ANDNP and
22799 if (!Y.getNode())
22800 return SDValue();
22802 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
22803 // Look through mask bitcast.
22804 if (Mask.getOpcode() == ISD::BITCAST)
22805 Mask = Mask.getOperand(0);
22806 if (X.getOpcode() == ISD::BITCAST)
22807 X = X.getOperand(0);
22808 if (Y.getOpcode() == ISD::BITCAST)
22809 Y = Y.getOperand(0);
22811 EVT MaskVT = Mask.getValueType();
22813 // Validate that the Mask operand is a vector sra node.
22814 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
22815 // there is no psrai.b
22816 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
22817 unsigned SraAmt = ~0;
22818 if (Mask.getOpcode() == ISD::SRA) {
22819 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
22820 if (auto *AmtConst = AmtBV->getConstantSplatNode())
22821 SraAmt = AmtConst->getZExtValue();
22822 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
22823 SDValue SraC = Mask.getOperand(1);
22824 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
22825 }
22826 if ((SraAmt + 1) != EltBits)
22827 return SDValue();
22829 SDLoc DL(N);
22831 // Now we know we at least have a plendvb with the mask val. See if
22832 // we can form a psignb/w/d.
22833 // psign = x.type == y.type == mask.type && y = sub(0, x);
22834 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
22835 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
22836 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
22837 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
22838 "Unsupported VT for PSIGN");
22839 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
22840 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
22841 }
22842 // PBLENDVB only available on SSE 4.1
22843 if (!Subtarget->hasSSE41())
22844 return SDValue();
22846 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
22848 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
22849 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
22850 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
22851 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
22852 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
22853 }
22854 }
22856 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
22857 return SDValue();
22859 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
22860 MachineFunction &MF = DAG.getMachineFunction();
22861 bool OptForSize = MF.getFunction()->getAttributes().
22862 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
22864 // SHLD/SHRD instructions have lower register pressure, but on some
22865 // platforms they have higher latency than the equivalent
22866 // series of shifts/or that would otherwise be generated.
22867 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
22868 // have higher latencies and we are not optimizing for size.
22869 if (!OptForSize && Subtarget->isSHLDSlow())
22870 return SDValue();
22872 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
22873 std::swap(N0, N1);
22874 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
22875 return SDValue();
22876 if (!N0.hasOneUse() || !N1.hasOneUse())
22877 return SDValue();
22879 SDValue ShAmt0 = N0.getOperand(1);
22880 if (ShAmt0.getValueType() != MVT::i8)
22881 return SDValue();
22882 SDValue ShAmt1 = N1.getOperand(1);
22883 if (ShAmt1.getValueType() != MVT::i8)
22884 return SDValue();
22885 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
22886 ShAmt0 = ShAmt0.getOperand(0);
22887 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
22888 ShAmt1 = ShAmt1.getOperand(0);
22890 SDLoc DL(N);
22891 unsigned Opc = X86ISD::SHLD;
22892 SDValue Op0 = N0.getOperand(0);
22893 SDValue Op1 = N1.getOperand(0);
22894 if (ShAmt0.getOpcode() == ISD::SUB) {
22895 Opc = X86ISD::SHRD;
22896 std::swap(Op0, Op1);
22897 std::swap(ShAmt0, ShAmt1);
22898 }
22900 unsigned Bits = VT.getSizeInBits();
22901 if (ShAmt1.getOpcode() == ISD::SUB) {
22902 SDValue Sum = ShAmt1.getOperand(0);
22903 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
22904 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
22905 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
22906 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
22907 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
22908 return DAG.getNode(Opc, DL, VT,
22909 Op0, Op1,
22910 DAG.getNode(ISD::TRUNCATE, DL,
22911 MVT::i8, ShAmt0));
22912 }
22913 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
22914 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
22915 if (ShAmt0C &&
22916 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
22917 return DAG.getNode(Opc, DL, VT,
22918 N0.getOperand(0), N1.getOperand(0),
22919 DAG.getNode(ISD::TRUNCATE, DL,
22920 MVT::i8, ShAmt0));
22921 }
22923 return SDValue();
22924 }
22926 // Generate NEG and CMOV for integer abs.
22927 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
22928 EVT VT = N->getValueType(0);
22930 // Since X86 does not have CMOV for 8-bit integer, we don't convert
22931 // 8-bit integer abs to NEG and CMOV.
22932 if (VT.isInteger() && VT.getSizeInBits() == 8)
22933 return SDValue();
22935 SDValue N0 = N->getOperand(0);
22936 SDValue N1 = N->getOperand(1);
22937 SDLoc DL(N);
22939 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
22940 // and change it to SUB and CMOV.
22941 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
22942 N0.getOpcode() == ISD::ADD &&
22943 N0.getOperand(1) == N1 &&
22944 N1.getOpcode() == ISD::SRA &&
22945 N1.getOperand(0) == N0.getOperand(0))
22946 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
22947 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
22948 // Generate SUB & CMOV.
22949 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
22950 DAG.getConstant(0, VT), N0.getOperand(0));
22952 SDValue Ops[] = { N0.getOperand(0), Neg,
22953 DAG.getConstant(X86::COND_GE, MVT::i8),
22954 SDValue(Neg.getNode(), 1) };
22955 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
22956 }
22957 return SDValue();
22958 }
22960 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
22961 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
22962 TargetLowering::DAGCombinerInfo &DCI,
22963 const X86Subtarget *Subtarget) {
22964 if (DCI.isBeforeLegalizeOps())
22965 return SDValue();
22967 if (Subtarget->hasCMov()) {
22968 SDValue RV = performIntegerAbsCombine(N, DAG);
22969 if (RV.getNode())
22970 return RV;
22971 }
22973 return SDValue();
22974 }
22976 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
22977 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
22978 TargetLowering::DAGCombinerInfo &DCI,
22979 const X86Subtarget *Subtarget) {
22980 LoadSDNode *Ld = cast<LoadSDNode>(N);
22981 EVT RegVT = Ld->getValueType(0);
22982 EVT MemVT = Ld->getMemoryVT();
22983 SDLoc dl(Ld);
22984 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22986 // On Sandybridge unaligned 256bit loads are inefficient.
22987 ISD::LoadExtType Ext = Ld->getExtensionType();
22988 unsigned Alignment = Ld->getAlignment();
22989 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
22990 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
22991 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
22992 unsigned NumElems = RegVT.getVectorNumElements();
22993 if (NumElems < 2)
22994 return SDValue();
22996 SDValue Ptr = Ld->getBasePtr();
22997 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
22999 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
23000 NumElems/2);
23001 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23002 Ld->getPointerInfo(), Ld->isVolatile(),
23003 Ld->isNonTemporal(), Ld->isInvariant(),
23004 Alignment);
23005 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23006 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23007 Ld->getPointerInfo(), Ld->isVolatile(),
23008 Ld->isNonTemporal(), Ld->isInvariant(),
23009 std::min(16U, Alignment));
23010 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
23011 Load1.getValue(1),
23012 Load2.getValue(1));
23014 SDValue NewVec = DAG.getUNDEF(RegVT);
23015 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
23016 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
23017 return DCI.CombineTo(N, NewVec, TF, true);
23018 }
23020 return SDValue();
23021 }
23023 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
23024 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
23025 const X86Subtarget *Subtarget) {
23026 StoreSDNode *St = cast<StoreSDNode>(N);
23027 EVT VT = St->getValue().getValueType();
23028 EVT StVT = St->getMemoryVT();
23029 SDLoc dl(St);
23030 SDValue StoredVal = St->getOperand(1);
23031 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23033 // If we are saving a concatenation of two XMM registers, perform two stores.
23034 // On Sandy Bridge, 256-bit memory operations are executed by two
23035 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
23036 // memory operation.
23037 unsigned Alignment = St->getAlignment();
23038 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
23039 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
23040 StVT == VT && !IsAligned) {
23041 unsigned NumElems = VT.getVectorNumElements();
23042 if (NumElems < 2)
23043 return SDValue();
23045 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
23046 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
23048 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
23049 SDValue Ptr0 = St->getBasePtr();
23050 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
23052 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
23053 St->getPointerInfo(), St->isVolatile(),
23054 St->isNonTemporal(), Alignment);
23055 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
23056 St->getPointerInfo(), St->isVolatile(),
23057 St->isNonTemporal(),
23058 std::min(16U, Alignment));
23059 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
23060 }
23062 // Optimize trunc store (of multiple scalars) to shuffle and store.
23063 // First, pack all of the elements in one place. Next, store to memory
23064 // in fewer chunks.
23065 if (St->isTruncatingStore() && VT.isVector()) {
23066 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23067 unsigned NumElems = VT.getVectorNumElements();
23068 assert(StVT != VT && "Cannot truncate to the same type");
23069 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
23070 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
23072 // From, To sizes and ElemCount must be pow of two
23073 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
23074 // We are going to use the original vector elt for storing.
23075 // Accumulated smaller vector elements must be a multiple of the store size.
23076 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
23078 unsigned SizeRatio = FromSz / ToSz;
23080 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
23082 // Create a type on which we perform the shuffle
23083 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23084 StVT.getScalarType(), NumElems*SizeRatio);
23086 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23088 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
23089 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
23090 for (unsigned i = 0; i != NumElems; ++i)
23091 ShuffleVec[i] = i * SizeRatio;
23093 // Can't shuffle using an illegal type.
23094 if (!TLI.isTypeLegal(WideVecVT))
23095 return SDValue();
23097 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
23098 DAG.getUNDEF(WideVecVT),
23099 &ShuffleVec[0]);
23100 // At this point all of the data is stored at the bottom of the
23101 // register. We now need to save it to mem.
23103 // Find the largest store unit
23104 MVT StoreType = MVT::i8;
23105 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
23106 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
23107 MVT Tp = (MVT::SimpleValueType)tp;
23108 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
23109 StoreType = Tp;
23110 }
23112 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
23113 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
23114 (64 <= NumElems * ToSz))
23115 StoreType = MVT::f64;
23117 // Bitcast the original vector into a vector of store-size units
23118 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
23119 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
23120 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
23121 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
23122 SmallVector<SDValue, 8> Chains;
23123 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
23124 TLI.getPointerTy());
23125 SDValue Ptr = St->getBasePtr();
23127 // Perform one or more big stores into memory.
23128 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
23129 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
23130 StoreType, ShuffWide,
23131 DAG.getIntPtrConstant(i));
23132 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
23133 St->getPointerInfo(), St->isVolatile(),
23134 St->isNonTemporal(), St->getAlignment());
23135 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23136 Chains.push_back(Ch);
23137 }
23139 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
23140 }
23142 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
23143 // the FP state in cases where an emms may be missing.
23144 // A preferable solution to the general problem is to figure out the right
23145 // places to insert EMMS. This qualifies as a quick hack.
23147 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
23148 if (VT.getSizeInBits() != 64)
23149 return SDValue();
23151 const Function *F = DAG.getMachineFunction().getFunction();
23152 bool NoImplicitFloatOps = F->getAttributes().
23153 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
23154 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
23155 && Subtarget->hasSSE2();
23156 if ((VT.isVector() ||
23157 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
23158 isa<LoadSDNode>(St->getValue()) &&
23159 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
23160 St->getChain().hasOneUse() && !St->isVolatile()) {
23161 SDNode* LdVal = St->getValue().getNode();
23162 LoadSDNode *Ld = nullptr;
23163 int TokenFactorIndex = -1;
23164 SmallVector<SDValue, 8> Ops;
23165 SDNode* ChainVal = St->getChain().getNode();
23166 // Must be a store of a load. We currently handle two cases: the load
23167 // is a direct child, and it's under an intervening TokenFactor. It is
23168 // possible to dig deeper under nested TokenFactors.
23169 if (ChainVal == LdVal)
23170 Ld = cast<LoadSDNode>(St->getChain());
23171 else if (St->getValue().hasOneUse() &&
23172 ChainVal->getOpcode() == ISD::TokenFactor) {
23173 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
23174 if (ChainVal->getOperand(i).getNode() == LdVal) {
23175 TokenFactorIndex = i;
23176 Ld = cast<LoadSDNode>(St->getValue());
23177 } else
23178 Ops.push_back(ChainVal->getOperand(i));
23179 }
23180 }
23182 if (!Ld || !ISD::isNormalLoad(Ld))
23183 return SDValue();
23185 // If this is not the MMX case, i.e. we are just turning i64 load/store
23186 // into f64 load/store, avoid the transformation if there are multiple
23187 // uses of the loaded value.
23188 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
23189 return SDValue();
23191 SDLoc LdDL(Ld);
23192 SDLoc StDL(N);
23193 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
23194 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
23195 // pair instead.
23196 if (Subtarget->is64Bit() || F64IsLegal) {
23197 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
23198 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
23199 Ld->getPointerInfo(), Ld->isVolatile(),
23200 Ld->isNonTemporal(), Ld->isInvariant(),
23201 Ld->getAlignment());
23202 SDValue NewChain = NewLd.getValue(1);
23203 if (TokenFactorIndex != -1) {
23204 Ops.push_back(NewChain);
23205 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23206 }
23207 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
23208 St->getPointerInfo(),
23209 St->isVolatile(), St->isNonTemporal(),
23210 St->getAlignment());
23211 }
23213 // Otherwise, lower to two pairs of 32-bit loads / stores.
23214 SDValue LoAddr = Ld->getBasePtr();
23215 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
23216 DAG.getConstant(4, MVT::i32));
23218 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
23219 Ld->getPointerInfo(),
23220 Ld->isVolatile(), Ld->isNonTemporal(),
23221 Ld->isInvariant(), Ld->getAlignment());
23222 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
23223 Ld->getPointerInfo().getWithOffset(4),
23224 Ld->isVolatile(), Ld->isNonTemporal(),
23225 Ld->isInvariant(),
23226 MinAlign(Ld->getAlignment(), 4));
23228 SDValue NewChain = LoLd.getValue(1);
23229 if (TokenFactorIndex != -1) {
23230 Ops.push_back(LoLd);
23231 Ops.push_back(HiLd);
23232 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23233 }
23235 LoAddr = St->getBasePtr();
23236 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
23237 DAG.getConstant(4, MVT::i32));
23239 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
23240 St->getPointerInfo(),
23241 St->isVolatile(), St->isNonTemporal(),
23242 St->getAlignment());
23243 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
23244 St->getPointerInfo().getWithOffset(4),
23245 St->isVolatile(),
23246 St->isNonTemporal(),
23247 MinAlign(St->getAlignment(), 4));
23248 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
23249 }
23250 return SDValue();
23251 }
23253 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
23254 /// and return the operands for the horizontal operation in LHS and RHS. A
23255 /// horizontal operation performs the binary operation on successive elements
23256 /// of its first operand, then on successive elements of its second operand,
23257 /// returning the resulting values in a vector. For example, if
23258 /// A = < float a0, float a1, float a2, float a3 >
23259 /// and
23260 /// B = < float b0, float b1, float b2, float b3 >
23261 /// then the result of doing a horizontal operation on A and B is
23262 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
23263 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
23264 /// A horizontal-op B, for some already available A and B, and if so then LHS is
23265 /// set to A, RHS to B, and the routine returns 'true'.
23266 /// Note that the binary operation should have the property that if one of the
23267 /// operands is UNDEF then the result is UNDEF.
23268 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
23269 // Look for the following pattern: if
23270 // A = < float a0, float a1, float a2, float a3 >
23271 // B = < float b0, float b1, float b2, float b3 >
23272 // and
23273 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
23274 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
23275 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
23276 // which is A horizontal-op B.
23278 // At least one of the operands should be a vector shuffle.
23279 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
23280 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
23281 return false;
23283 MVT VT = LHS.getSimpleValueType();
23285 assert((VT.is128BitVector() || VT.is256BitVector()) &&
23286 "Unsupported vector type for horizontal add/sub");
23288 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
23289 // operate independently on 128-bit lanes.
23290 unsigned NumElts = VT.getVectorNumElements();
23291 unsigned NumLanes = VT.getSizeInBits()/128;
23292 unsigned NumLaneElts = NumElts / NumLanes;
23293 assert((NumLaneElts % 2 == 0) &&
23294 "Vector type should have an even number of elements in each lane");
23295 unsigned HalfLaneElts = NumLaneElts/2;
23297 // View LHS in the form
23298 // LHS = VECTOR_SHUFFLE A, B, LMask
23299 // If LHS is not a shuffle then pretend it is the shuffle
23300 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
23301 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
23302 // type VT.
23303 SDValue A, B;
23304 SmallVector<int, 16> LMask(NumElts);
23305 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23306 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
23307 A = LHS.getOperand(0);
23308 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
23309 B = LHS.getOperand(1);
23310 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
23311 std::copy(Mask.begin(), Mask.end(), LMask.begin());
23312 } else {
23313 if (LHS.getOpcode() != ISD::UNDEF)
23314 A = LHS;
23315 for (unsigned i = 0; i != NumElts; ++i)
23316 LMask[i] = i;
23317 }
23319 // Likewise, view RHS in the form
23320 // RHS = VECTOR_SHUFFLE C, D, RMask
23321 SDValue C, D;
23322 SmallVector<int, 16> RMask(NumElts);
23323 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23324 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
23325 C = RHS.getOperand(0);
23326 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
23327 D = RHS.getOperand(1);
23328 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
23329 std::copy(Mask.begin(), Mask.end(), RMask.begin());
23330 } else {
23331 if (RHS.getOpcode() != ISD::UNDEF)
23332 C = RHS;
23333 for (unsigned i = 0; i != NumElts; ++i)
23334 RMask[i] = i;
23335 }
23337 // Check that the shuffles are both shuffling the same vectors.
23338 if (!(A == C && B == D) && !(A == D && B == C))
23339 return false;
23341 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
23342 if (!A.getNode() && !B.getNode())
23343 return false;
23345 // If A and B occur in reverse order in RHS, then "swap" them (which means
23346 // rewriting the mask).
23347 if (A != C)
23348 CommuteVectorShuffleMask(RMask, NumElts);
23350 // At this point LHS and RHS are equivalent to
23351 // LHS = VECTOR_SHUFFLE A, B, LMask
23352 // RHS = VECTOR_SHUFFLE A, B, RMask
23353 // Check that the masks correspond to performing a horizontal operation.
23354 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
23355 for (unsigned i = 0; i != NumLaneElts; ++i) {
23356 int LIdx = LMask[i+l], RIdx = RMask[i+l];
23358 // Ignore any UNDEF components.
23359 if (LIdx < 0 || RIdx < 0 ||
23360 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
23361 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
23362 continue;
23364 // Check that successive elements are being operated on. If not, this is
23365 // not a horizontal operation.
23366 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
23367 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
23368 if (!(LIdx == Index && RIdx == Index + 1) &&
23369 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
23370 return false;
23371 }
23372 }
23374 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
23375 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
23376 return true;
23377 }
23379 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
23380 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
23381 const X86Subtarget *Subtarget) {
23382 EVT VT = N->getValueType(0);
23383 SDValue LHS = N->getOperand(0);
23384 SDValue RHS = N->getOperand(1);
23386 // Try to synthesize horizontal adds from adds of shuffles.
23387 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23388 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23389 isHorizontalBinOp(LHS, RHS, true))
23390 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
23391 return SDValue();
23392 }
23394 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
23395 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
23396 const X86Subtarget *Subtarget) {
23397 EVT VT = N->getValueType(0);
23398 SDValue LHS = N->getOperand(0);
23399 SDValue RHS = N->getOperand(1);
23401 // Try to synthesize horizontal subs from subs of shuffles.
23402 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23403 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23404 isHorizontalBinOp(LHS, RHS, false))
23405 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
23406 return SDValue();
23407 }
23409 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
23410 /// X86ISD::FXOR nodes.
23411 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
23412 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
23413 // F[X]OR(0.0, x) -> x
23414 // F[X]OR(x, 0.0) -> x
23415 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23416 if (C->getValueAPF().isPosZero())
23417 return N->getOperand(1);
23418 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23419 if (C->getValueAPF().isPosZero())
23420 return N->getOperand(0);
23421 return SDValue();
23422 }
23424 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
23425 /// X86ISD::FMAX nodes.
23426 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
23427 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
23429 // Only perform optimizations if UnsafeMath is used.
23430 if (!DAG.getTarget().Options.UnsafeFPMath)
23431 return SDValue();
23433 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
23434 // into FMINC and FMAXC, which are Commutative operations.
23435 unsigned NewOp = 0;
23436 switch (N->getOpcode()) {
23437 default: llvm_unreachable("unknown opcode");
23438 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
23439 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
23440 }
23442 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
23443 N->getOperand(0), N->getOperand(1));
23444 }
23446 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
23447 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
23448 // FAND(0.0, x) -> 0.0
23449 // FAND(x, 0.0) -> 0.0
23450 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23451 if (C->getValueAPF().isPosZero())
23452 return N->getOperand(0);
23453 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23454 if (C->getValueAPF().isPosZero())
23455 return N->getOperand(1);
23456 return SDValue();
23457 }
23459 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
23460 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
23461 // FANDN(x, 0.0) -> 0.0
23462 // FANDN(0.0, x) -> x
23463 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23464 if (C->getValueAPF().isPosZero())
23465 return N->getOperand(1);
23466 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23467 if (C->getValueAPF().isPosZero())
23468 return N->getOperand(1);
23469 return SDValue();
23470 }
23472 static SDValue PerformBTCombine(SDNode *N,
23473 SelectionDAG &DAG,
23474 TargetLowering::DAGCombinerInfo &DCI) {
23475 // BT ignores high bits in the bit index operand.
23476 SDValue Op1 = N->getOperand(1);
23477 if (Op1.hasOneUse()) {
23478 unsigned BitWidth = Op1.getValueSizeInBits();
23479 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
23480 APInt KnownZero, KnownOne;
23481 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
23482 !DCI.isBeforeLegalizeOps());
23483 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23484 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
23485 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
23486 DCI.CommitTargetLoweringOpt(TLO);
23487 }
23488 return SDValue();
23489 }
23491 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
23492 SDValue Op = N->getOperand(0);
23493 if (Op.getOpcode() == ISD::BITCAST)
23494 Op = Op.getOperand(0);
23495 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
23496 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
23497 VT.getVectorElementType().getSizeInBits() ==
23498 OpVT.getVectorElementType().getSizeInBits()) {
23499 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
23500 }
23501 return SDValue();
23502 }
23504 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
23505 const X86Subtarget *Subtarget) {
23506 EVT VT = N->getValueType(0);
23507 if (!VT.isVector())
23508 return SDValue();
23510 SDValue N0 = N->getOperand(0);
23511 SDValue N1 = N->getOperand(1);
23512 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
23513 SDLoc dl(N);
23515 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
23516 // both SSE and AVX2 since there is no sign-extended shift right
23517 // operation on a vector with 64-bit elements.
23518 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
23519 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
23520 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
23521 N0.getOpcode() == ISD::SIGN_EXTEND)) {
23522 SDValue N00 = N0.getOperand(0);
23524 // EXTLOAD has a better solution on AVX2,
23525 // it may be replaced with X86ISD::VSEXT node.
23526 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
23527 if (!ISD::isNormalLoad(N00.getNode()))
23528 return SDValue();
23530 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
23531 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
23532 N00, N1);
23533 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
23534 }
23535 }
23536 return SDValue();
23537 }
23539 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
23540 TargetLowering::DAGCombinerInfo &DCI,
23541 const X86Subtarget *Subtarget) {
23542 if (!DCI.isBeforeLegalizeOps())
23543 return SDValue();
23545 if (!Subtarget->hasFp256())
23546 return SDValue();
23548 EVT VT = N->getValueType(0);
23549 if (VT.isVector() && VT.getSizeInBits() == 256) {
23550 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
23551 if (R.getNode())
23552 return R;
23553 }
23555 return SDValue();
23556 }
23558 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
23559 const X86Subtarget* Subtarget) {
23560 SDLoc dl(N);
23561 EVT VT = N->getValueType(0);
23563 // Let legalize expand this if it isn't a legal type yet.
23564 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
23565 return SDValue();
23567 EVT ScalarVT = VT.getScalarType();
23568 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
23569 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
23570 return SDValue();
23572 SDValue A = N->getOperand(0);
23573 SDValue B = N->getOperand(1);
23574 SDValue C = N->getOperand(2);
23576 bool NegA = (A.getOpcode() == ISD::FNEG);
23577 bool NegB = (B.getOpcode() == ISD::FNEG);
23578 bool NegC = (C.getOpcode() == ISD::FNEG);
23580 // Negative multiplication when NegA xor NegB
23581 bool NegMul = (NegA != NegB);
23582 if (NegA)
23583 A = A.getOperand(0);
23584 if (NegB)
23585 B = B.getOperand(0);
23586 if (NegC)
23587 C = C.getOperand(0);
23589 unsigned Opcode;
23590 if (!NegMul)
23591 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
23592 else
23593 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
23595 return DAG.getNode(Opcode, dl, VT, A, B, C);
23596 }
23598 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
23599 TargetLowering::DAGCombinerInfo &DCI,
23600 const X86Subtarget *Subtarget) {
23601 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
23602 // (and (i32 x86isd::setcc_carry), 1)
23603 // This eliminates the zext. This transformation is necessary because
23604 // ISD::SETCC is always legalized to i8.
23605 SDLoc dl(N);
23606 SDValue N0 = N->getOperand(0);
23607 EVT VT = N->getValueType(0);
23609 if (N0.getOpcode() == ISD::AND &&
23610 N0.hasOneUse() &&
23611 N0.getOperand(0).hasOneUse()) {
23612 SDValue N00 = N0.getOperand(0);
23613 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
23614 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
23615 if (!C || C->getZExtValue() != 1)
23616 return SDValue();
23617 return DAG.getNode(ISD::AND, dl, VT,
23618 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
23619 N00.getOperand(0), N00.getOperand(1)),
23620 DAG.getConstant(1, VT));
23621 }
23622 }
23624 if (N0.getOpcode() == ISD::TRUNCATE &&
23625 N0.hasOneUse() &&
23626 N0.getOperand(0).hasOneUse()) {
23627 SDValue N00 = N0.getOperand(0);
23628 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
23629 return DAG.getNode(ISD::AND, dl, VT,
23630 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
23631 N00.getOperand(0), N00.getOperand(1)),
23632 DAG.getConstant(1, VT));
23633 }
23634 }
23635 if (VT.is256BitVector()) {
23636 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
23637 if (R.getNode())
23638 return R;
23639 }
23641 return SDValue();
23642 }
23644 // Optimize x == -y --> x+y == 0
23645 // x != -y --> x+y != 0
23646 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
23647 const X86Subtarget* Subtarget) {
23648 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
23649 SDValue LHS = N->getOperand(0);
23650 SDValue RHS = N->getOperand(1);
23651 EVT VT = N->getValueType(0);
23652 SDLoc DL(N);
23654 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
23655 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
23656 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
23657 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
23658 LHS.getValueType(), RHS, LHS.getOperand(1));
23659 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
23660 addV, DAG.getConstant(0, addV.getValueType()), CC);
23661 }
23662 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
23663 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
23664 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
23665 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
23666 RHS.getValueType(), LHS, RHS.getOperand(1));
23667 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
23668 addV, DAG.getConstant(0, addV.getValueType()), CC);
23669 }
23671 if (VT.getScalarType() == MVT::i1) {
23672 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
23673 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
23674 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
23675 if (!IsSEXT0 && !IsVZero0)
23676 return SDValue();
23677 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
23678 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
23679 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
23681 if (!IsSEXT1 && !IsVZero1)
23682 return SDValue();
23684 if (IsSEXT0 && IsVZero1) {
23685 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
23686 if (CC == ISD::SETEQ)
23687 return DAG.getNOT(DL, LHS.getOperand(0), VT);
23688 return LHS.getOperand(0);
23689 }
23690 if (IsSEXT1 && IsVZero0) {
23691 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
23692 if (CC == ISD::SETEQ)
23693 return DAG.getNOT(DL, RHS.getOperand(0), VT);
23694 return RHS.getOperand(0);
23695 }
23696 }
23698 return SDValue();
23699 }
23701 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
23702 const X86Subtarget *Subtarget) {
23703 SDLoc dl(N);
23704 MVT VT = N->getOperand(1)->getSimpleValueType(0);
23705 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
23706 "X86insertps is only defined for v4x32");
23708 SDValue Ld = N->getOperand(1);
23709 if (MayFoldLoad(Ld)) {
23710 // Extract the countS bits from the immediate so we can get the proper
23711 // address when narrowing the vector load to a specific element.
23712 // When the second source op is a memory address, interps doesn't use
23713 // countS and just gets an f32 from that address.
23714 unsigned DestIndex =
23715 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
23716 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
23717 } else
23718 return SDValue();
23720 // Create this as a scalar to vector to match the instruction pattern.
23721 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
23722 // countS bits are ignored when loading from memory on insertps, which
23723 // means we don't need to explicitly set them to 0.
23724 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
23725 LoadScalarToVector, N->getOperand(2));
23726 }
23728 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
23729 // as "sbb reg,reg", since it can be extended without zext and produces
23730 // an all-ones bit which is more useful than 0/1 in some cases.
23731 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
23732 MVT VT) {
23733 if (VT == MVT::i8)
23734 return DAG.getNode(ISD::AND, DL, VT,
23735 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
23736 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
23737 DAG.getConstant(1, VT));
23738 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
23739 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
23740 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
23741 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
23742 }
23744 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
23745 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
23746 TargetLowering::DAGCombinerInfo &DCI,
23747 const X86Subtarget *Subtarget) {
23748 SDLoc DL(N);
23749 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
23750 SDValue EFLAGS = N->getOperand(1);
23752 if (CC == X86::COND_A) {
23753 // Try to convert COND_A into COND_B in an attempt to facilitate
23754 // materializing "setb reg".
23755 //
23756 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
23757 // cannot take an immediate as its first operand.
23758 //
23759 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
23760 EFLAGS.getValueType().isInteger() &&
23761 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
23762 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
23763 EFLAGS.getNode()->getVTList(),
23764 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
23765 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
23766 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
23767 }
23768 }
23770 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
23771 // a zext and produces an all-ones bit which is more useful than 0/1 in some
23772 // cases.
23773 if (CC == X86::COND_B)
23774 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
23776 SDValue Flags;
23778 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
23779 if (Flags.getNode()) {
23780 SDValue Cond = DAG.getConstant(CC, MVT::i8);
23781 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
23782 }
23784 return SDValue();
23785 }
23787 // Optimize branch condition evaluation.
23788 //
23789 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
23790 TargetLowering::DAGCombinerInfo &DCI,
23791 const X86Subtarget *Subtarget) {
23792 SDLoc DL(N);
23793 SDValue Chain = N->getOperand(0);
23794 SDValue Dest = N->getOperand(1);
23795 SDValue EFLAGS = N->getOperand(3);
23796 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
23798 SDValue Flags;
23800 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
23801 if (Flags.getNode()) {
23802 SDValue Cond = DAG.getConstant(CC, MVT::i8);
23803 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
23804 Flags);
23805 }
23807 return SDValue();
23808 }
23810 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
23811 SelectionDAG &DAG) {
23812 // Take advantage of vector comparisons producing 0 or -1 in each lane to
23813 // optimize away operation when it's from a constant.
23814 //
23815 // The general transformation is:
23816 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
23817 // AND(VECTOR_CMP(x,y), constant2)
23818 // constant2 = UNARYOP(constant)
23820 // Early exit if this isn't a vector operation, the operand of the
23821 // unary operation isn't a bitwise AND, or if the sizes of the operations
23822 // aren't the same.
23823 EVT VT = N->getValueType(0);
23824 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
23825 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
23826 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
23827 return SDValue();
23829 // Now check that the other operand of the AND is a constant. We could
23830 // make the transformation for non-constant splats as well, but it's unclear
23831 // that would be a benefit as it would not eliminate any operations, just
23832 // perform one more step in scalar code before moving to the vector unit.
23833 if (BuildVectorSDNode *BV =
23834 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
23835 // Bail out if the vector isn't a constant.
23836 if (!BV->isConstant())
23837 return SDValue();
23839 // Everything checks out. Build up the new and improved node.
23840 SDLoc DL(N);
23841 EVT IntVT = BV->getValueType(0);
23842 // Create a new constant of the appropriate type for the transformed
23843 // DAG.
23844 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
23845 // The AND node needs bitcasts to/from an integer vector type around it.
23846 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
23847 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
23848 N->getOperand(0)->getOperand(0), MaskConst);
23849 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
23850 return Res;
23851 }
23853 return SDValue();
23854 }
23856 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
23857 const X86TargetLowering *XTLI) {
23858 // First try to optimize away the conversion entirely when it's
23859 // conditionally from a constant. Vectors only.
23860 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
23861 if (Res != SDValue())
23862 return Res;
23864 // Now move on to more general possibilities.
23865 SDValue Op0 = N->getOperand(0);
23866 EVT InVT = Op0->getValueType(0);
23868 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
23869 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
23870 SDLoc dl(N);
23871 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
23872 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
23873 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
23874 }
23876 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
23877 // a 32-bit target where SSE doesn't support i64->FP operations.
23878 if (Op0.getOpcode() == ISD::LOAD) {
23879 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
23880 EVT VT = Ld->getValueType(0);
23881 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
23882 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
23883 !XTLI->getSubtarget()->is64Bit() &&
23884 VT == MVT::i64) {
23885 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
23886 Ld->getChain(), Op0, DAG);
23887 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
23888 return FILDChain;
23889 }
23890 }
23891 return SDValue();
23892 }
23894 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
23895 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
23896 X86TargetLowering::DAGCombinerInfo &DCI) {
23897 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
23898 // the result is either zero or one (depending on the input carry bit).
23899 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
23900 if (X86::isZeroNode(N->getOperand(0)) &&
23901 X86::isZeroNode(N->getOperand(1)) &&
23902 // We don't have a good way to replace an EFLAGS use, so only do this when
23903 // dead right now.
23904 SDValue(N, 1).use_empty()) {
23905 SDLoc DL(N);
23906 EVT VT = N->getValueType(0);
23907 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
23908 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
23909 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
23910 DAG.getConstant(X86::COND_B,MVT::i8),
23911 N->getOperand(2)),
23912 DAG.getConstant(1, VT));
23913 return DCI.CombineTo(N, Res1, CarryOut);
23914 }
23916 return SDValue();
23917 }
23919 // fold (add Y, (sete X, 0)) -> adc 0, Y
23920 // (add Y, (setne X, 0)) -> sbb -1, Y
23921 // (sub (sete X, 0), Y) -> sbb 0, Y
23922 // (sub (setne X, 0), Y) -> adc -1, Y
23923 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
23924 SDLoc DL(N);
23926 // Look through ZExts.
23927 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
23928 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
23929 return SDValue();
23931 SDValue SetCC = Ext.getOperand(0);
23932 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
23933 return SDValue();
23935 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
23936 if (CC != X86::COND_E && CC != X86::COND_NE)
23937 return SDValue();
23939 SDValue Cmp = SetCC.getOperand(1);
23940 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
23941 !X86::isZeroNode(Cmp.getOperand(1)) ||
23942 !Cmp.getOperand(0).getValueType().isInteger())
23943 return SDValue();
23945 SDValue CmpOp0 = Cmp.getOperand(0);
23946 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
23947 DAG.getConstant(1, CmpOp0.getValueType()));
23949 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
23950 if (CC == X86::COND_NE)
23951 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
23952 DL, OtherVal.getValueType(), OtherVal,
23953 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
23954 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
23955 DL, OtherVal.getValueType(), OtherVal,
23956 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
23957 }
23959 /// PerformADDCombine - Do target-specific dag combines on integer adds.
23960 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
23961 const X86Subtarget *Subtarget) {
23962 EVT VT = N->getValueType(0);
23963 SDValue Op0 = N->getOperand(0);
23964 SDValue Op1 = N->getOperand(1);
23966 // Try to synthesize horizontal adds from adds of shuffles.
23967 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
23968 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
23969 isHorizontalBinOp(Op0, Op1, true))
23970 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
23972 return OptimizeConditionalInDecrement(N, DAG);
23973 }
23975 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
23976 const X86Subtarget *Subtarget) {
23977 SDValue Op0 = N->getOperand(0);
23978 SDValue Op1 = N->getOperand(1);
23980 // X86 can't encode an immediate LHS of a sub. See if we can push the
23981 // negation into a preceding instruction.
23982 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
23983 // If the RHS of the sub is a XOR with one use and a constant, invert the
23984 // immediate. Then add one to the LHS of the sub so we can turn
23985 // X-Y -> X+~Y+1, saving one register.
23986 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
23987 isa<ConstantSDNode>(Op1.getOperand(1))) {
23988 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
23989 EVT VT = Op0.getValueType();
23990 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
23991 Op1.getOperand(0),
23992 DAG.getConstant(~XorC, VT));
23993 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
23994 DAG.getConstant(C->getAPIntValue()+1, VT));
23995 }
23996 }
23998 // Try to synthesize horizontal adds from adds of shuffles.
23999 EVT VT = N->getValueType(0);
24000 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24001 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24002 isHorizontalBinOp(Op0, Op1, true))
24003 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
24005 return OptimizeConditionalInDecrement(N, DAG);
24006 }
24008 /// performVZEXTCombine - Performs build vector combines
24009 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
24010 TargetLowering::DAGCombinerInfo &DCI,
24011 const X86Subtarget *Subtarget) {
24012 // (vzext (bitcast (vzext (x)) -> (vzext x)
24013 SDValue In = N->getOperand(0);
24014 while (In.getOpcode() == ISD::BITCAST)
24015 In = In.getOperand(0);
24017 if (In.getOpcode() != X86ISD::VZEXT)
24018 return SDValue();
24020 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
24021 In.getOperand(0));
24022 }
24024 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
24025 DAGCombinerInfo &DCI) const {
24026 SelectionDAG &DAG = DCI.DAG;
24027 switch (N->getOpcode()) {
24028 default: break;
24029 case ISD::EXTRACT_VECTOR_ELT:
24030 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
24031 case ISD::VSELECT:
24032 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
24033 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
24034 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
24035 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
24036 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
24037 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
24038 case ISD::SHL:
24039 case ISD::SRA:
24040 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
24041 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
24042 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
24043 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
24044 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
24045 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
24046 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
24047 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
24048 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
24049 case X86ISD::FXOR:
24050 case X86ISD::FOR: return PerformFORCombine(N, DAG);
24051 case X86ISD::FMIN:
24052 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
24053 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
24054 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
24055 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
24056 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
24057 case ISD::ANY_EXTEND:
24058 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
24059 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
24060 case ISD::SIGN_EXTEND_INREG:
24061 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
24062 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
24063 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
24064 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
24065 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
24066 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
24067 case X86ISD::SHUFP: // Handle all target specific shuffles
24068 case X86ISD::PALIGNR:
24069 case X86ISD::UNPCKH:
24070 case X86ISD::UNPCKL:
24071 case X86ISD::MOVHLPS:
24072 case X86ISD::MOVLHPS:
24073 case X86ISD::PSHUFB:
24074 case X86ISD::PSHUFD:
24075 case X86ISD::PSHUFHW:
24076 case X86ISD::PSHUFLW:
24077 case X86ISD::MOVSS:
24078 case X86ISD::MOVSD:
24079 case X86ISD::VPERMILPI:
24080 case X86ISD::VPERM2X128:
24081 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
24082 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
24083 case ISD::INTRINSIC_WO_CHAIN:
24084 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
24085 case X86ISD::INSERTPS:
24086 return PerformINSERTPSCombine(N, DAG, Subtarget);
24087 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
24088 }
24090 return SDValue();
24091 }
24093 /// isTypeDesirableForOp - Return true if the target has native support for
24094 /// the specified value type and it is 'desirable' to use the type for the
24095 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
24096 /// instruction encodings are longer and some i16 instructions are slow.
24097 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
24098 if (!isTypeLegal(VT))
24099 return false;
24100 if (VT != MVT::i16)
24101 return true;
24103 switch (Opc) {
24104 default:
24105 return true;
24106 case ISD::LOAD:
24107 case ISD::SIGN_EXTEND:
24108 case ISD::ZERO_EXTEND:
24109 case ISD::ANY_EXTEND:
24110 case ISD::SHL:
24111 case ISD::SRL:
24112 case ISD::SUB:
24113 case ISD::ADD:
24114 case ISD::MUL:
24115 case ISD::AND:
24116 case ISD::OR:
24117 case ISD::XOR:
24118 return false;
24119 }
24120 }
24122 /// IsDesirableToPromoteOp - This method query the target whether it is
24123 /// beneficial for dag combiner to promote the specified node. If true, it
24124 /// should return the desired promotion type by reference.
24125 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
24126 EVT VT = Op.getValueType();
24127 if (VT != MVT::i16)
24128 return false;
24130 bool Promote = false;
24131 bool Commute = false;
24132 switch (Op.getOpcode()) {
24133 default: break;
24134 case ISD::LOAD: {
24135 LoadSDNode *LD = cast<LoadSDNode>(Op);
24136 // If the non-extending load has a single use and it's not live out, then it
24137 // might be folded.
24138 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
24139 Op.hasOneUse()*/) {
24140 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
24141 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
24142 // The only case where we'd want to promote LOAD (rather then it being
24143 // promoted as an operand is when it's only use is liveout.
24144 if (UI->getOpcode() != ISD::CopyToReg)
24145 return false;
24146 }
24147 }
24148 Promote = true;
24149 break;
24150 }
24151 case ISD::SIGN_EXTEND:
24152 case ISD::ZERO_EXTEND:
24153 case ISD::ANY_EXTEND:
24154 Promote = true;
24155 break;
24156 case ISD::SHL:
24157 case ISD::SRL: {
24158 SDValue N0 = Op.getOperand(0);
24159 // Look out for (store (shl (load), x)).
24160 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
24161 return false;
24162 Promote = true;
24163 break;
24164 }
24165 case ISD::ADD:
24166 case ISD::MUL:
24167 case ISD::AND:
24168 case ISD::OR:
24169 case ISD::XOR:
24170 Commute = true;
24171 // fallthrough
24172 case ISD::SUB: {
24173 SDValue N0 = Op.getOperand(0);
24174 SDValue N1 = Op.getOperand(1);
24175 if (!Commute && MayFoldLoad(N1))
24176 return false;
24177 // Avoid disabling potential load folding opportunities.
24178 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
24179 return false;
24180 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
24181 return false;
24182 Promote = true;
24183 }
24184 }
24186 PVT = MVT::i32;
24187 return Promote;
24188 }
24190 //===----------------------------------------------------------------------===//
24191 // X86 Inline Assembly Support
24192 //===----------------------------------------------------------------------===//
24194 namespace {
24195 // Helper to match a string separated by whitespace.
24196 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
24197 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
24199 for (unsigned i = 0, e = args.size(); i != e; ++i) {
24200 StringRef piece(*args[i]);
24201 if (!s.startswith(piece)) // Check if the piece matches.
24202 return false;
24204 s = s.substr(piece.size());
24205 StringRef::size_type pos = s.find_first_not_of(" \t");
24206 if (pos == 0) // We matched a prefix.
24207 return false;
24209 s = s.substr(pos);
24210 }
24212 return s.empty();
24213 }
24214 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
24215 }
24217 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
24219 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
24220 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
24221 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
24222 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
24224 if (AsmPieces.size() == 3)
24225 return true;
24226 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
24227 return true;
24228 }
24229 }
24230 return false;
24231 }
24233 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
24234 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
24236 std::string AsmStr = IA->getAsmString();
24238 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
24239 if (!Ty || Ty->getBitWidth() % 16 != 0)
24240 return false;
24242 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
24243 SmallVector<StringRef, 4> AsmPieces;
24244 SplitString(AsmStr, AsmPieces, ";\n");
24246 switch (AsmPieces.size()) {
24247 default: return false;
24248 case 1:
24249 // FIXME: this should verify that we are targeting a 486 or better. If not,
24250 // we will turn this bswap into something that will be lowered to logical
24251 // ops instead of emitting the bswap asm. For now, we don't support 486 or
24252 // lower so don't worry about this.
24253 // bswap $0
24254 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
24255 matchAsm(AsmPieces[0], "bswapl", "$0") ||
24256 matchAsm(AsmPieces[0], "bswapq", "$0") ||
24257 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
24258 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
24259 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
24260 // No need to check constraints, nothing other than the equivalent of
24261 // "=r,0" would be valid here.
24262 return IntrinsicLowering::LowerToByteSwap(CI);
24263 }
24265 // rorw $$8, ${0:w} --> llvm.bswap.i16
24266 if (CI->getType()->isIntegerTy(16) &&
24267 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24268 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
24269 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
24270 AsmPieces.clear();
24271 const std::string &ConstraintsStr = IA->getConstraintString();
24272 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24273 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24274 if (clobbersFlagRegisters(AsmPieces))
24275 return IntrinsicLowering::LowerToByteSwap(CI);
24276 }
24277 break;
24278 case 3:
24279 if (CI->getType()->isIntegerTy(32) &&
24280 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24281 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
24282 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
24283 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
24284 AsmPieces.clear();
24285 const std::string &ConstraintsStr = IA->getConstraintString();
24286 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24287 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24288 if (clobbersFlagRegisters(AsmPieces))
24289 return IntrinsicLowering::LowerToByteSwap(CI);
24290 }
24292 if (CI->getType()->isIntegerTy(64)) {
24293 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
24294 if (Constraints.size() >= 2 &&
24295 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
24296 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
24297 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
24298 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
24299 matchAsm(AsmPieces[1], "bswap", "%edx") &&
24300 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
24301 return IntrinsicLowering::LowerToByteSwap(CI);
24302 }
24303 }
24304 break;
24305 }
24306 return false;
24307 }
24309 /// getConstraintType - Given a constraint letter, return the type of
24310 /// constraint it is for this target.
24311 X86TargetLowering::ConstraintType
24312 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
24313 if (Constraint.size() == 1) {
24314 switch (Constraint[0]) {
24315 case 'R':
24316 case 'q':
24317 case 'Q':
24318 case 'f':
24319 case 't':
24320 case 'u':
24321 case 'y':
24322 case 'x':
24323 case 'Y':
24324 case 'l':
24325 return C_RegisterClass;
24326 case 'a':
24327 case 'b':
24328 case 'c':
24329 case 'd':
24330 case 'S':
24331 case 'D':
24332 case 'A':
24333 return C_Register;
24334 case 'I':
24335 case 'J':
24336 case 'K':
24337 case 'L':
24338 case 'M':
24339 case 'N':
24340 case 'G':
24341 case 'C':
24342 case 'e':
24343 case 'Z':
24344 return C_Other;
24345 default:
24346 break;
24347 }
24348 }
24349 return TargetLowering::getConstraintType(Constraint);
24350 }
24352 /// Examine constraint type and operand type and determine a weight value.
24353 /// This object must already have been set up with the operand type
24354 /// and the current alternative constraint selected.
24355 TargetLowering::ConstraintWeight
24356 X86TargetLowering::getSingleConstraintMatchWeight(
24357 AsmOperandInfo &info, const char *constraint) const {
24358 ConstraintWeight weight = CW_Invalid;
24359 Value *CallOperandVal = info.CallOperandVal;
24360 // If we don't have a value, we can't do a match,
24361 // but allow it at the lowest weight.
24362 if (!CallOperandVal)
24363 return CW_Default;
24364 Type *type = CallOperandVal->getType();
24365 // Look at the constraint type.
24366 switch (*constraint) {
24367 default:
24368 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
24369 case 'R':
24370 case 'q':
24371 case 'Q':
24372 case 'a':
24373 case 'b':
24374 case 'c':
24375 case 'd':
24376 case 'S':
24377 case 'D':
24378 case 'A':
24379 if (CallOperandVal->getType()->isIntegerTy())
24380 weight = CW_SpecificReg;
24381 break;
24382 case 'f':
24383 case 't':
24384 case 'u':
24385 if (type->isFloatingPointTy())
24386 weight = CW_SpecificReg;
24387 break;
24388 case 'y':
24389 if (type->isX86_MMXTy() && Subtarget->hasMMX())
24390 weight = CW_SpecificReg;
24391 break;
24392 case 'x':
24393 case 'Y':
24394 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
24395 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
24396 weight = CW_Register;
24397 break;
24398 case 'I':
24399 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
24400 if (C->getZExtValue() <= 31)
24401 weight = CW_Constant;
24402 }
24403 break;
24404 case 'J':
24405 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24406 if (C->getZExtValue() <= 63)
24407 weight = CW_Constant;
24408 }
24409 break;
24410 case 'K':
24411 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24412 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
24413 weight = CW_Constant;
24414 }
24415 break;
24416 case 'L':
24417 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24418 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
24419 weight = CW_Constant;
24420 }
24421 break;
24422 case 'M':
24423 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24424 if (C->getZExtValue() <= 3)
24425 weight = CW_Constant;
24426 }
24427 break;
24428 case 'N':
24429 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24430 if (C->getZExtValue() <= 0xff)
24431 weight = CW_Constant;
24432 }
24433 break;
24434 case 'G':
24435 case 'C':
24436 if (dyn_cast<ConstantFP>(CallOperandVal)) {
24437 weight = CW_Constant;
24438 }
24439 break;
24440 case 'e':
24441 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24442 if ((C->getSExtValue() >= -0x80000000LL) &&
24443 (C->getSExtValue() <= 0x7fffffffLL))
24444 weight = CW_Constant;
24445 }
24446 break;
24447 case 'Z':
24448 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24449 if (C->getZExtValue() <= 0xffffffff)
24450 weight = CW_Constant;
24451 }
24452 break;
24453 }
24454 return weight;
24455 }
24457 /// LowerXConstraint - try to replace an X constraint, which matches anything,
24458 /// with another that has more specific requirements based on the type of the
24459 /// corresponding operand.
24460 const char *X86TargetLowering::
24461 LowerXConstraint(EVT ConstraintVT) const {
24462 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
24463 // 'f' like normal targets.
24464 if (ConstraintVT.isFloatingPoint()) {
24465 if (Subtarget->hasSSE2())
24466 return "Y";
24467 if (Subtarget->hasSSE1())
24468 return "x";
24469 }
24471 return TargetLowering::LowerXConstraint(ConstraintVT);
24472 }
24474 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
24475 /// vector. If it is invalid, don't add anything to Ops.
24476 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
24477 std::string &Constraint,
24478 std::vector<SDValue>&Ops,
24479 SelectionDAG &DAG) const {
24480 SDValue Result;
24482 // Only support length 1 constraints for now.
24483 if (Constraint.length() > 1) return;
24485 char ConstraintLetter = Constraint[0];
24486 switch (ConstraintLetter) {
24487 default: break;
24488 case 'I':
24489 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24490 if (C->getZExtValue() <= 31) {
24491 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24492 break;
24493 }
24494 }
24495 return;
24496 case 'J':
24497 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24498 if (C->getZExtValue() <= 63) {
24499 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24500 break;
24501 }
24502 }
24503 return;
24504 case 'K':
24505 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24506 if (isInt<8>(C->getSExtValue())) {
24507 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24508 break;
24509 }
24510 }
24511 return;
24512 case 'N':
24513 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24514 if (C->getZExtValue() <= 255) {
24515 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24516 break;
24517 }
24518 }
24519 return;
24520 case 'e': {
24521 // 32-bit signed value
24522 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24523 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
24524 C->getSExtValue())) {
24525 // Widen to 64 bits here to get it sign extended.
24526 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
24527 break;
24528 }
24529 // FIXME gcc accepts some relocatable values here too, but only in certain
24530 // memory models; it's complicated.
24531 }
24532 return;
24533 }
24534 case 'Z': {
24535 // 32-bit unsigned value
24536 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24537 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
24538 C->getZExtValue())) {
24539 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24540 break;
24541 }
24542 }
24543 // FIXME gcc accepts some relocatable values here too, but only in certain
24544 // memory models; it's complicated.
24545 return;
24546 }
24547 case 'i': {
24548 // Literal immediates are always ok.
24549 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
24550 // Widen to 64 bits here to get it sign extended.
24551 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
24552 break;
24553 }
24555 // In any sort of PIC mode addresses need to be computed at runtime by
24556 // adding in a register or some sort of table lookup. These can't
24557 // be used as immediates.
24558 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
24559 return;
24561 // If we are in non-pic codegen mode, we allow the address of a global (with
24562 // an optional displacement) to be used with 'i'.
24563 GlobalAddressSDNode *GA = nullptr;
24564 int64_t Offset = 0;
24566 // Match either (GA), (GA+C), (GA+C1+C2), etc.
24567 while (1) {
24568 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
24569 Offset += GA->getOffset();
24570 break;
24571 } else if (Op.getOpcode() == ISD::ADD) {
24572 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
24573 Offset += C->getZExtValue();
24574 Op = Op.getOperand(0);
24575 continue;
24576 }
24577 } else if (Op.getOpcode() == ISD::SUB) {
24578 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
24579 Offset += -C->getZExtValue();
24580 Op = Op.getOperand(0);
24581 continue;
24582 }
24583 }
24585 // Otherwise, this isn't something we can handle, reject it.
24586 return;
24587 }
24589 const GlobalValue *GV = GA->getGlobal();
24590 // If we require an extra load to get this address, as in PIC mode, we
24591 // can't accept it.
24592 if (isGlobalStubReference(
24593 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
24594 return;
24596 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
24597 GA->getValueType(0), Offset);
24598 break;
24599 }
24600 }
24602 if (Result.getNode()) {
24603 Ops.push_back(Result);
24604 return;
24605 }
24606 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
24607 }
24609 std::pair<unsigned, const TargetRegisterClass*>
24610 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
24611 MVT VT) const {
24612 // First, see if this is a constraint that directly corresponds to an LLVM
24613 // register class.
24614 if (Constraint.size() == 1) {
24615 // GCC Constraint Letters
24616 switch (Constraint[0]) {
24617 default: break;
24618 // TODO: Slight differences here in allocation order and leaving
24619 // RIP in the class. Do they matter any more here than they do
24620 // in the normal allocation?
24621 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
24622 if (Subtarget->is64Bit()) {
24623 if (VT == MVT::i32 || VT == MVT::f32)
24624 return std::make_pair(0U, &X86::GR32RegClass);
24625 if (VT == MVT::i16)
24626 return std::make_pair(0U, &X86::GR16RegClass);
24627 if (VT == MVT::i8 || VT == MVT::i1)
24628 return std::make_pair(0U, &X86::GR8RegClass);
24629 if (VT == MVT::i64 || VT == MVT::f64)
24630 return std::make_pair(0U, &X86::GR64RegClass);
24631 break;
24632 }
24633 // 32-bit fallthrough
24634 case 'Q': // Q_REGS
24635 if (VT == MVT::i32 || VT == MVT::f32)
24636 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
24637 if (VT == MVT::i16)
24638 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
24639 if (VT == MVT::i8 || VT == MVT::i1)
24640 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
24641 if (VT == MVT::i64)
24642 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
24643 break;
24644 case 'r': // GENERAL_REGS
24645 case 'l': // INDEX_REGS
24646 if (VT == MVT::i8 || VT == MVT::i1)
24647 return std::make_pair(0U, &X86::GR8RegClass);
24648 if (VT == MVT::i16)
24649 return std::make_pair(0U, &X86::GR16RegClass);
24650 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
24651 return std::make_pair(0U, &X86::GR32RegClass);
24652 return std::make_pair(0U, &X86::GR64RegClass);
24653 case 'R': // LEGACY_REGS
24654 if (VT == MVT::i8 || VT == MVT::i1)
24655 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
24656 if (VT == MVT::i16)
24657 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
24658 if (VT == MVT::i32 || !Subtarget->is64Bit())
24659 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
24660 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
24661 case 'f': // FP Stack registers.
24662 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
24663 // value to the correct fpstack register class.
24664 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
24665 return std::make_pair(0U, &X86::RFP32RegClass);
24666 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
24667 return std::make_pair(0U, &X86::RFP64RegClass);
24668 return std::make_pair(0U, &X86::RFP80RegClass);
24669 case 'y': // MMX_REGS if MMX allowed.
24670 if (!Subtarget->hasMMX()) break;
24671 return std::make_pair(0U, &X86::VR64RegClass);
24672 case 'Y': // SSE_REGS if SSE2 allowed
24673 if (!Subtarget->hasSSE2()) break;
24674 // FALL THROUGH.
24675 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
24676 if (!Subtarget->hasSSE1()) break;
24678 switch (VT.SimpleTy) {
24679 default: break;
24680 // Scalar SSE types.
24681 case MVT::f32:
24682 case MVT::i32:
24683 return std::make_pair(0U, &X86::FR32RegClass);
24684 case MVT::f64:
24685 case MVT::i64:
24686 return std::make_pair(0U, &X86::FR64RegClass);
24687 // Vector types.
24688 case MVT::v16i8:
24689 case MVT::v8i16:
24690 case MVT::v4i32:
24691 case MVT::v2i64:
24692 case MVT::v4f32:
24693 case MVT::v2f64:
24694 return std::make_pair(0U, &X86::VR128RegClass);
24695 // AVX types.
24696 case MVT::v32i8:
24697 case MVT::v16i16:
24698 case MVT::v8i32:
24699 case MVT::v4i64:
24700 case MVT::v8f32:
24701 case MVT::v4f64:
24702 return std::make_pair(0U, &X86::VR256RegClass);
24703 case MVT::v8f64:
24704 case MVT::v16f32:
24705 case MVT::v16i32:
24706 case MVT::v8i64:
24707 return std::make_pair(0U, &X86::VR512RegClass);
24708 }
24709 break;
24710 }
24711 }
24713 // Use the default implementation in TargetLowering to convert the register
24714 // constraint into a member of a register class.
24715 std::pair<unsigned, const TargetRegisterClass*> Res;
24716 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
24718 // Not found as a standard register?
24719 if (!Res.second) {
24720 // Map st(0) -> st(7) -> ST0
24721 if (Constraint.size() == 7 && Constraint[0] == '{' &&
24722 tolower(Constraint[1]) == 's' &&
24723 tolower(Constraint[2]) == 't' &&
24724 Constraint[3] == '(' &&
24725 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
24726 Constraint[5] == ')' &&
24727 Constraint[6] == '}') {
24729 Res.first = X86::FP0+Constraint[4]-'0';
24730 Res.second = &X86::RFP80RegClass;
24731 return Res;
24732 }
24734 // GCC allows "st(0)" to be called just plain "st".
24735 if (StringRef("{st}").equals_lower(Constraint)) {
24736 Res.first = X86::FP0;
24737 Res.second = &X86::RFP80RegClass;
24738 return Res;
24739 }
24741 // flags -> EFLAGS
24742 if (StringRef("{flags}").equals_lower(Constraint)) {
24743 Res.first = X86::EFLAGS;
24744 Res.second = &X86::CCRRegClass;
24745 return Res;
24746 }
24748 // 'A' means EAX + EDX.
24749 if (Constraint == "A") {
24750 Res.first = X86::EAX;
24751 Res.second = &X86::GR32_ADRegClass;
24752 return Res;
24753 }
24754 return Res;
24755 }
24757 // Otherwise, check to see if this is a register class of the wrong value
24758 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
24759 // turn into {ax},{dx}.
24760 if (Res.second->hasType(VT))
24761 return Res; // Correct type already, nothing to do.
24763 // All of the single-register GCC register classes map their values onto
24764 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
24765 // really want an 8-bit or 32-bit register, map to the appropriate register
24766 // class and return the appropriate register.
24767 if (Res.second == &X86::GR16RegClass) {
24768 if (VT == MVT::i8 || VT == MVT::i1) {
24769 unsigned DestReg = 0;
24770 switch (Res.first) {
24771 default: break;
24772 case X86::AX: DestReg = X86::AL; break;
24773 case X86::DX: DestReg = X86::DL; break;
24774 case X86::CX: DestReg = X86::CL; break;
24775 case X86::BX: DestReg = X86::BL; break;
24776 }
24777 if (DestReg) {
24778 Res.first = DestReg;
24779 Res.second = &X86::GR8RegClass;
24780 }
24781 } else if (VT == MVT::i32 || VT == MVT::f32) {
24782 unsigned DestReg = 0;
24783 switch (Res.first) {
24784 default: break;
24785 case X86::AX: DestReg = X86::EAX; break;
24786 case X86::DX: DestReg = X86::EDX; break;
24787 case X86::CX: DestReg = X86::ECX; break;
24788 case X86::BX: DestReg = X86::EBX; break;
24789 case X86::SI: DestReg = X86::ESI; break;
24790 case X86::DI: DestReg = X86::EDI; break;
24791 case X86::BP: DestReg = X86::EBP; break;
24792 case X86::SP: DestReg = X86::ESP; break;
24793 }
24794 if (DestReg) {
24795 Res.first = DestReg;
24796 Res.second = &X86::GR32RegClass;
24797 }
24798 } else if (VT == MVT::i64 || VT == MVT::f64) {
24799 unsigned DestReg = 0;
24800 switch (Res.first) {
24801 default: break;
24802 case X86::AX: DestReg = X86::RAX; break;
24803 case X86::DX: DestReg = X86::RDX; break;
24804 case X86::CX: DestReg = X86::RCX; break;
24805 case X86::BX: DestReg = X86::RBX; break;
24806 case X86::SI: DestReg = X86::RSI; break;
24807 case X86::DI: DestReg = X86::RDI; break;
24808 case X86::BP: DestReg = X86::RBP; break;
24809 case X86::SP: DestReg = X86::RSP; break;
24810 }
24811 if (DestReg) {
24812 Res.first = DestReg;
24813 Res.second = &X86::GR64RegClass;
24814 }
24815 }
24816 } else if (Res.second == &X86::FR32RegClass ||
24817 Res.second == &X86::FR64RegClass ||
24818 Res.second == &X86::VR128RegClass ||
24819 Res.second == &X86::VR256RegClass ||
24820 Res.second == &X86::FR32XRegClass ||
24821 Res.second == &X86::FR64XRegClass ||
24822 Res.second == &X86::VR128XRegClass ||
24823 Res.second == &X86::VR256XRegClass ||
24824 Res.second == &X86::VR512RegClass) {
24825 // Handle references to XMM physical registers that got mapped into the
24826 // wrong class. This can happen with constraints like {xmm0} where the
24827 // target independent register mapper will just pick the first match it can
24828 // find, ignoring the required type.
24830 if (VT == MVT::f32 || VT == MVT::i32)
24831 Res.second = &X86::FR32RegClass;
24832 else if (VT == MVT::f64 || VT == MVT::i64)
24833 Res.second = &X86::FR64RegClass;
24834 else if (X86::VR128RegClass.hasType(VT))
24835 Res.second = &X86::VR128RegClass;
24836 else if (X86::VR256RegClass.hasType(VT))
24837 Res.second = &X86::VR256RegClass;
24838 else if (X86::VR512RegClass.hasType(VT))
24839 Res.second = &X86::VR512RegClass;
24840 }
24842 return Res;
24843 }
24845 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
24846 Type *Ty) const {
24847 // Scaling factors are not free at all.
24848 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
24849 // will take 2 allocations in the out of order engine instead of 1
24850 // for plain addressing mode, i.e. inst (reg1).
24851 // E.g.,
24852 // vaddps (%rsi,%drx), %ymm0, %ymm1
24853 // Requires two allocations (one for the load, one for the computation)
24854 // whereas:
24855 // vaddps (%rsi), %ymm0, %ymm1
24856 // Requires just 1 allocation, i.e., freeing allocations for other operations
24857 // and having less micro operations to execute.
24858 //
24859 // For some X86 architectures, this is even worse because for instance for
24860 // stores, the complex addressing mode forces the instruction to use the
24861 // "load" ports instead of the dedicated "store" port.
24862 // E.g., on Haswell:
24863 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
24864 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
24865 if (isLegalAddressingMode(AM, Ty))
24866 // Scale represents reg2 * scale, thus account for 1
24867 // as soon as we use a second register.
24868 return AM.Scale != 0;
24869 return -1;
24870 }
24872 bool X86TargetLowering::isTargetFTOL() const {
24873 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();
24874 }