1 multiclass AVX512_masking<bits<8> O, Format F, dag Outs, dag Ins,
2 string OpcodeStr,
3 string AttSrcAsm, string IntelSrcAsm,
4 dag RHS,
5 RegisterClass RC, RegisterClass KRC> {
6 def NAME: AVX512<O, F, Outs, Ins,
7 OpcodeStr#" \t{"#AttSrcAsm#", $dst|"#
8 "$dst, "#IntelSrcAsm#"}",
9 [(set RC:$dst, RHS)]>;
11 let Constraints = "$src0 = $dst" in
12 def NAME#k: AVX512<O, F, Outs,
13 !con((ins RC:$src0, KRC:$mask), Ins),
14 OpcodeStr#" \t{"#AttSrcAsm#", $dst {${mask}}|"#
15 "$dst {${mask}}, "#IntelSrcAsm#"}",
16 [(set RC:$dst,
17 (vselect KRC:$mask, RHS, RC:$src0))]>,
18 EVEX_K;
19 }
21 // Bitcasts between 512-bit vector types. Return the original type since
22 // no instruction is needed for the conversion
23 let Predicates = [HasAVX512] in {
24 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
25 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
26 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
27 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
28 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
29 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
30 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
31 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
32 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
33 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
34 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
35 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
36 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
37 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
38 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
39 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
40 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
41 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
42 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
43 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
44 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
45 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
46 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
47 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
48 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
49 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
50 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
51 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
52 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
53 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
55 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
56 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
57 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
58 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
59 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
60 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
61 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
62 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
63 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
64 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
65 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
66 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
67 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
68 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
69 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
70 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
71 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
72 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
73 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
74 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
75 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
76 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
77 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
78 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
79 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
80 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
81 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
82 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
83 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
84 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
86 // Bitcasts between 256-bit vector types. Return the original type since
87 // no instruction is needed for the conversion
88 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
89 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
90 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
91 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
92 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
93 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
94 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
95 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
96 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
97 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
98 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
99 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
100 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
101 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
102 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
103 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
104 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
105 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
106 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
107 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
108 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
109 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
110 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
111 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
112 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
113 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
114 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
115 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
116 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
117 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
118 }
120 //
121 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
122 //
124 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
125 isPseudo = 1, Predicates = [HasAVX512] in {
126 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
127 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
128 }
130 let Predicates = [HasAVX512] in {
131 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
132 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
133 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
134 }
136 //===----------------------------------------------------------------------===//
137 // AVX-512 - VECTOR INSERT
138 //
139 // -- 32x8 form --
140 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
141 def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
142 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
143 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
144 []>, EVEX_4V, EVEX_V512;
145 let mayLoad = 1 in
146 def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst),
147 (ins VR512:$src1, f128mem:$src2, i8imm:$src3),
148 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
149 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
150 }
152 // -- 64x4 fp form --
153 let hasSideEffects = 0, ExeDomain = SSEPackedDouble in {
154 def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
155 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
156 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
157 []>, EVEX_4V, EVEX_V512, VEX_W;
158 let mayLoad = 1 in
159 def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst),
160 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
161 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
162 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
163 }
164 // -- 32x4 integer form --
165 let hasSideEffects = 0 in {
166 def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
167 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
168 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
169 []>, EVEX_4V, EVEX_V512;
170 let mayLoad = 1 in
171 def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst),
172 (ins VR512:$src1, i128mem:$src2, i8imm:$src3),
173 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
174 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
175 }
177 let hasSideEffects = 0 in {
178 // -- 64x4 form --
179 def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
180 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
181 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
182 []>, EVEX_4V, EVEX_V512, VEX_W;
183 let mayLoad = 1 in
184 def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst),
185 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
186 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
187 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
188 }
190 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
191 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
192 (INSERT_get_vinsert128_imm VR512:$ins))>;
193 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
194 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
195 (INSERT_get_vinsert128_imm VR512:$ins))>;
196 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
197 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
198 (INSERT_get_vinsert128_imm VR512:$ins))>;
199 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2),
200 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
201 (INSERT_get_vinsert128_imm VR512:$ins))>;
203 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
204 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
205 (INSERT_get_vinsert128_imm VR512:$ins))>;
206 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1),
207 (bc_v4i32 (loadv2i64 addr:$src2)),
208 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
209 (INSERT_get_vinsert128_imm VR512:$ins))>;
210 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
211 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
212 (INSERT_get_vinsert128_imm VR512:$ins))>;
213 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
214 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
215 (INSERT_get_vinsert128_imm VR512:$ins))>;
217 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
218 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
219 (INSERT_get_vinsert256_imm VR512:$ins))>;
220 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2),
221 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
222 (INSERT_get_vinsert256_imm VR512:$ins))>;
223 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2),
224 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
225 (INSERT_get_vinsert256_imm VR512:$ins))>;
226 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2),
227 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
228 (INSERT_get_vinsert256_imm VR512:$ins))>;
230 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
231 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
232 (INSERT_get_vinsert256_imm VR512:$ins))>;
233 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2),
234 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
235 (INSERT_get_vinsert256_imm VR512:$ins))>;
236 def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2),
237 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
238 (INSERT_get_vinsert256_imm VR512:$ins))>;
239 def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
240 (bc_v8i32 (loadv4i64 addr:$src2)),
241 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
242 (INSERT_get_vinsert256_imm VR512:$ins))>;
244 // vinsertps - insert f32 to XMM
245 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
246 (ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
247 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
248 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
249 EVEX_4V;
250 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
251 (ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
252 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
253 [(set VR128X:$dst, (X86insertps VR128X:$src1,
254 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
255 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
257 //===----------------------------------------------------------------------===//
258 // AVX-512 VECTOR EXTRACT
259 //---
260 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
261 // -- 32x4 form --
262 def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
263 (ins VR512:$src1, i8imm:$src2),
264 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
265 []>, EVEX, EVEX_V512;
266 def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs),
267 (ins f128mem:$dst, VR512:$src1, i8imm:$src2),
268 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
269 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
271 // -- 64x4 form --
272 def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
273 (ins VR512:$src1, i8imm:$src2),
274 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
275 []>, EVEX, EVEX_V512, VEX_W;
276 let mayStore = 1 in
277 def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs),
278 (ins f256mem:$dst, VR512:$src1, i8imm:$src2),
279 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
280 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
281 }
283 let hasSideEffects = 0 in {
284 // -- 32x4 form --
285 def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
286 (ins VR512:$src1, i8imm:$src2),
287 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
288 []>, EVEX, EVEX_V512;
289 def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs),
290 (ins i128mem:$dst, VR512:$src1, i8imm:$src2),
291 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
292 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
294 // -- 64x4 form --
295 def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
296 (ins VR512:$src1, i8imm:$src2),
297 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
298 []>, EVEX, EVEX_V512, VEX_W;
299 let mayStore = 1 in
300 def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs),
301 (ins i256mem:$dst, VR512:$src1, i8imm:$src2),
302 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
303 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
304 }
306 def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
307 (v4f32 (VEXTRACTF32x4rr VR512:$src1,
308 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
310 def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)),
311 (v4i32 (VEXTRACTF32x4rr VR512:$src1,
312 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
314 def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
315 (v2f64 (VEXTRACTF32x4rr VR512:$src1,
316 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
318 def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
319 (v2i64 (VEXTRACTI32x4rr VR512:$src1,
320 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
323 def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
324 (v8f32 (VEXTRACTF64x4rr VR512:$src1,
325 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
327 def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)),
328 (v8i32 (VEXTRACTI64x4rr VR512:$src1,
329 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
331 def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
332 (v4f64 (VEXTRACTF64x4rr VR512:$src1,
333 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
335 def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
336 (v4i64 (VEXTRACTI64x4rr VR512:$src1,
337 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
339 // A 256-bit subvector extract from the first 512-bit vector position
340 // is a subregister copy that needs no instruction.
341 def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
342 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
343 def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
344 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
345 def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
346 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
347 def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
348 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
350 // zmm -> xmm
351 def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
352 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
353 def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
354 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
355 def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
356 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
357 def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
358 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
361 // A 128-bit subvector insert to the first 512-bit vector position
362 // is a subregister copy that needs no instruction.
363 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
364 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
365 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
366 sub_ymm)>;
367 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
368 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
369 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
370 sub_ymm)>;
371 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
372 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
373 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
374 sub_ymm)>;
375 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
376 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
377 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
378 sub_ymm)>;
380 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
381 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
382 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
383 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
384 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
385 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
386 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
387 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
389 // vextractps - extract 32 bits from XMM
390 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
391 (ins VR128X:$src1, u32u8imm:$src2),
392 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
393 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
394 EVEX;
396 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
397 (ins f32mem:$dst, VR128X:$src1, u32u8imm:$src2),
398 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
399 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
400 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
402 //===---------------------------------------------------------------------===//
403 // AVX-512 BROADCAST
404 //---
405 multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
406 RegisterClass DestRC,
407 RegisterClass SrcRC, X86MemOperand x86memop> {
408 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
409 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
410 []>, EVEX;
411 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
412 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),[]>, EVEX;
413 }
414 let ExeDomain = SSEPackedSingle in {
415 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss", VR512,
416 VR128X, f32mem>,
417 EVEX_V512, EVEX_CD8<32, CD8VT1>;
418 }
420 let ExeDomain = SSEPackedDouble in {
421 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd", VR512,
422 VR128X, f64mem>,
423 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
424 }
426 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
427 (VBROADCASTSSZrm addr:$src)>;
428 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
429 (VBROADCASTSDZrm addr:$src)>;
431 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
432 (VBROADCASTSSZrm addr:$src)>;
433 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
434 (VBROADCASTSDZrm addr:$src)>;
436 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
437 RegisterClass SrcRC, RegisterClass KRC> {
438 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
439 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
440 []>, EVEX, EVEX_V512;
441 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
442 (ins KRC:$mask, SrcRC:$src),
443 !strconcat(OpcodeStr,
444 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
445 []>, EVEX, EVEX_V512, EVEX_KZ;
446 }
448 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
449 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
450 VEX_W;
452 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
453 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
455 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
456 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
458 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
459 (VPBROADCASTDrZrr GR32:$src)>;
460 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
461 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
462 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
463 (VPBROADCASTQrZrr GR64:$src)>;
464 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
465 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
467 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
468 (VPBROADCASTDrZrr GR32:$src)>;
469 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
470 (VPBROADCASTQrZrr GR64:$src)>;
472 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
473 (v16i32 immAllZerosV), (i16 GR16:$mask))),
474 (VPBROADCASTDrZkrr (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
475 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
476 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
477 (VPBROADCASTQrZkrr (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
479 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
480 X86MemOperand x86memop, PatFrag ld_frag,
481 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
482 RegisterClass KRC> {
483 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
484 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
485 [(set DstRC:$dst,
486 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
487 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
488 VR128X:$src),
489 !strconcat(OpcodeStr,
490 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
491 [(set DstRC:$dst,
492 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
493 EVEX, EVEX_KZ;
494 let mayLoad = 1 in {
495 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
496 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
497 [(set DstRC:$dst,
498 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
499 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
500 x86memop:$src),
501 !strconcat(OpcodeStr,
502 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
503 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
504 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
505 }
506 }
508 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
509 loadi32, VR512, v16i32, v4i32, VK16WM>,
510 EVEX_V512, EVEX_CD8<32, CD8VT1>;
511 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
512 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
513 EVEX_CD8<64, CD8VT1>;
515 multiclass avx512_int_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
516 X86MemOperand x86memop, PatFrag ld_frag,
517 RegisterClass KRC> {
518 let mayLoad = 1 in {
519 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins x86memop:$src),
520 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
521 []>, EVEX;
522 def krm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins KRC:$mask,
523 x86memop:$src),
524 !strconcat(OpcodeStr,
525 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
526 []>, EVEX, EVEX_KZ;
527 }
528 }
530 defm VBROADCASTI32X4 : avx512_int_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
531 i128mem, loadv2i64, VK16WM>,
532 EVEX_V512, EVEX_CD8<32, CD8VT4>;
533 defm VBROADCASTI64X4 : avx512_int_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
534 i256mem, loadv4i64, VK16WM>, VEX_W,
535 EVEX_V512, EVEX_CD8<64, CD8VT4>;
537 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
538 (VPBROADCASTDZrr VR128X:$src)>;
539 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
540 (VPBROADCASTQZrr VR128X:$src)>;
542 def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
543 (VBROADCASTSSZrr VR128X:$src)>;
544 def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
545 (VBROADCASTSDZrr VR128X:$src)>;
547 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
548 (VBROADCASTSSZrr VR128X:$src)>;
549 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
550 (VBROADCASTSDZrr VR128X:$src)>;
552 // Provide fallback in case the load node that is used in the patterns above
553 // is used by additional users, which prevents the pattern selection.
554 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
555 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
556 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
557 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
560 let Predicates = [HasAVX512] in {
561 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
562 (EXTRACT_SUBREG
563 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
564 addr:$src)), sub_ymm)>;
565 }
566 //===----------------------------------------------------------------------===//
567 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
568 //---
570 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
571 RegisterClass DstRC, RegisterClass KRC,
572 ValueType OpVT, ValueType SrcVT> {
573 def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
574 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
575 []>, EVEX;
576 }
578 let Predicates = [HasCDI] in {
579 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
580 VK16, v16i32, v16i1>, EVEX_V512;
581 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
582 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
583 }
585 //===----------------------------------------------------------------------===//
586 // AVX-512 - VPERM
587 //
588 // -- immediate form --
589 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
590 SDNode OpNode, PatFrag mem_frag,
591 X86MemOperand x86memop, ValueType OpVT> {
592 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
593 (ins RC:$src1, i8imm:$src2),
594 !strconcat(OpcodeStr,
595 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
596 [(set RC:$dst,
597 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
598 EVEX;
599 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
600 (ins x86memop:$src1, i8imm:$src2),
601 !strconcat(OpcodeStr,
602 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
603 [(set RC:$dst,
604 (OpVT (OpNode (mem_frag addr:$src1),
605 (i8 imm:$src2))))]>, EVEX;
606 }
608 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
609 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
610 let ExeDomain = SSEPackedDouble in
611 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
612 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
614 // -- VPERM - register form --
615 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
616 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
618 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
619 (ins RC:$src1, RC:$src2),
620 !strconcat(OpcodeStr,
621 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
622 [(set RC:$dst,
623 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
625 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
626 (ins RC:$src1, x86memop:$src2),
627 !strconcat(OpcodeStr,
628 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
629 [(set RC:$dst,
630 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
631 EVEX_4V;
632 }
634 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
635 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
636 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
637 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
638 let ExeDomain = SSEPackedSingle in
639 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
640 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
641 let ExeDomain = SSEPackedDouble in
642 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
643 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
645 // -- VPERM2I - 3 source operands form --
646 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
647 PatFrag mem_frag, X86MemOperand x86memop,
648 SDNode OpNode, ValueType OpVT, RegisterClass KRC> {
649 let Constraints = "$src1 = $dst" in {
650 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
651 (ins RC:$src1, RC:$src2, RC:$src3),
652 !strconcat(OpcodeStr,
653 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
654 [(set RC:$dst,
655 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
656 EVEX_4V;
658 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
659 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
660 !strconcat(OpcodeStr,
661 " \t{$src3, $src2, $dst {${mask}}|"
662 "$dst {${mask}}, $src2, $src3}"),
663 [(set RC:$dst, (OpVT (vselect KRC:$mask,
664 (OpNode RC:$src1, RC:$src2,
665 RC:$src3),
666 RC:$src1)))]>,
667 EVEX_4V, EVEX_K;
669 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
670 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
671 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
672 !strconcat(OpcodeStr,
673 " \t{$src3, $src2, $dst {${mask}} {z} |",
674 "$dst {${mask}} {z}, $src2, $src3}"),
675 [(set RC:$dst, (OpVT (vselect KRC:$mask,
676 (OpNode RC:$src1, RC:$src2,
677 RC:$src3),
678 (OpVT (bitconvert
679 (v16i32 immAllZerosV))))))]>,
680 EVEX_4V, EVEX_KZ;
682 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
683 (ins RC:$src1, RC:$src2, x86memop:$src3),
684 !strconcat(OpcodeStr,
685 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
686 [(set RC:$dst,
687 (OpVT (OpNode RC:$src1, RC:$src2,
688 (mem_frag addr:$src3))))]>, EVEX_4V;
690 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
691 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
692 !strconcat(OpcodeStr,
693 " \t{$src3, $src2, $dst {${mask}}|"
694 "$dst {${mask}}, $src2, $src3}"),
695 [(set RC:$dst,
696 (OpVT (vselect KRC:$mask,
697 (OpNode RC:$src1, RC:$src2,
698 (mem_frag addr:$src3)),
699 RC:$src1)))]>,
700 EVEX_4V, EVEX_K;
702 let AddedComplexity = 10 in // Prefer over the rrkz variant
703 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
704 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
705 !strconcat(OpcodeStr,
706 " \t{$src3, $src2, $dst {${mask}} {z}|"
707 "$dst {${mask}} {z}, $src2, $src3}"),
708 [(set RC:$dst,
709 (OpVT (vselect KRC:$mask,
710 (OpNode RC:$src1, RC:$src2,
711 (mem_frag addr:$src3)),
712 (OpVT (bitconvert
713 (v16i32 immAllZerosV))))))]>,
714 EVEX_4V, EVEX_KZ;
715 }
716 }
717 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32,
718 i512mem, X86VPermiv3, v16i32, VK16WM>,
719 EVEX_V512, EVEX_CD8<32, CD8VF>;
720 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64,
721 i512mem, X86VPermiv3, v8i64, VK8WM>,
722 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
723 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32,
724 i512mem, X86VPermiv3, v16f32, VK16WM>,
725 EVEX_V512, EVEX_CD8<32, CD8VF>;
726 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64,
727 i512mem, X86VPermiv3, v8f64, VK8WM>,
728 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
730 multiclass avx512_perm_table_3src<bits<8> opc, string Suffix, RegisterClass RC,
731 PatFrag mem_frag, X86MemOperand x86memop,
732 SDNode OpNode, ValueType OpVT, RegisterClass KRC,
733 ValueType MaskVT, RegisterClass MRC> :
734 avx512_perm_3src<opc, "vpermt2"##Suffix, RC, mem_frag, x86memop, OpNode,
735 OpVT, KRC> {
736 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
737 VR512:$idx, VR512:$src1, VR512:$src2, -1)),
738 (!cast<Instruction>(NAME#rr) VR512:$src1, VR512:$idx, VR512:$src2)>;
740 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
741 VR512:$idx, VR512:$src1, VR512:$src2, MRC:$mask)),
742 (!cast<Instruction>(NAME#rrk) VR512:$src1,
743 (MaskVT (COPY_TO_REGCLASS MRC:$mask, KRC)), VR512:$idx, VR512:$src2)>;
744 }
746 defm VPERMT2D : avx512_perm_table_3src<0x7E, "d", VR512, memopv16i32, i512mem,
747 X86VPermv3, v16i32, VK16WM, v16i1, GR16>,
748 EVEX_V512, EVEX_CD8<32, CD8VF>;
749 defm VPERMT2Q : avx512_perm_table_3src<0x7E, "q", VR512, memopv8i64, i512mem,
750 X86VPermv3, v8i64, VK8WM, v8i1, GR8>,
751 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
752 defm VPERMT2PS : avx512_perm_table_3src<0x7F, "ps", VR512, memopv16f32, i512mem,
753 X86VPermv3, v16f32, VK16WM, v16i1, GR16>,
754 EVEX_V512, EVEX_CD8<32, CD8VF>;
755 defm VPERMT2PD : avx512_perm_table_3src<0x7F, "pd", VR512, memopv8f64, i512mem,
756 X86VPermv3, v8f64, VK8WM, v8i1, GR8>,
757 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
759 //===----------------------------------------------------------------------===//
760 // AVX-512 - BLEND using mask
761 //
762 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
763 RegisterClass KRC, RegisterClass RC,
764 X86MemOperand x86memop, PatFrag mem_frag,
765 SDNode OpNode, ValueType vt> {
766 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
767 (ins KRC:$mask, RC:$src1, RC:$src2),
768 !strconcat(OpcodeStr,
769 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
770 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
771 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
772 let mayLoad = 1 in
773 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
774 (ins KRC:$mask, RC:$src1, x86memop:$src2),
775 !strconcat(OpcodeStr,
776 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
777 []>, EVEX_4V, EVEX_K;
778 }
780 let ExeDomain = SSEPackedSingle in
781 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
782 VK16WM, VR512, f512mem,
783 memopv16f32, vselect, v16f32>,
784 EVEX_CD8<32, CD8VF>, EVEX_V512;
785 let ExeDomain = SSEPackedDouble in
786 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
787 VK8WM, VR512, f512mem,
788 memopv8f64, vselect, v8f64>,
789 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
791 def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
792 (v16f32 VR512:$src2), (i16 GR16:$mask))),
793 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16WM),
794 VR512:$src1, VR512:$src2)>;
796 def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
797 (v8f64 VR512:$src2), (i8 GR8:$mask))),
798 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8WM),
799 VR512:$src1, VR512:$src2)>;
801 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
802 VK16WM, VR512, f512mem,
803 memopv16i32, vselect, v16i32>,
804 EVEX_CD8<32, CD8VF>, EVEX_V512;
806 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
807 VK8WM, VR512, f512mem,
808 memopv8i64, vselect, v8i64>,
809 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
811 def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
812 (v16i32 VR512:$src2), (i16 GR16:$mask))),
813 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
814 VR512:$src1, VR512:$src2)>;
816 def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
817 (v8i64 VR512:$src2), (i8 GR8:$mask))),
818 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
819 VR512:$src1, VR512:$src2)>;
821 let Predicates = [HasAVX512] in {
822 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
823 (v8f32 VR256X:$src2))),
824 (EXTRACT_SUBREG
825 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
826 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
827 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
829 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
830 (v8i32 VR256X:$src2))),
831 (EXTRACT_SUBREG
832 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
833 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
834 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
835 }
836 //===----------------------------------------------------------------------===//
837 // Compare Instructions
838 //===----------------------------------------------------------------------===//
840 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
841 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
842 Operand CC, SDNode OpNode, ValueType VT,
843 PatFrag ld_frag, string asm, string asm_alt> {
844 def rr : AVX512Ii8<0xC2, MRMSrcReg,
845 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
846 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
847 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
848 def rm : AVX512Ii8<0xC2, MRMSrcMem,
849 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
850 [(set VK1:$dst, (OpNode (VT RC:$src1),
851 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
852 let isAsmParserOnly = 1, hasSideEffects = 0 in {
853 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
854 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
855 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
856 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
857 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
858 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
859 }
860 }
862 let Predicates = [HasAVX512] in {
863 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
864 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
865 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
866 XS;
867 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
868 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
869 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
870 XD, VEX_W;
871 }
873 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, RegisterClass KRC,
874 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
875 SDNode OpNode, ValueType vt> {
876 def rr : AVX512BI<opc, MRMSrcReg,
877 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
878 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
879 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
880 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
881 def rm : AVX512BI<opc, MRMSrcMem,
882 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
883 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
884 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2)))],
885 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
886 }
888 defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem,
889 memopv16i32, X86pcmpeqm, v16i32>, EVEX_V512,
890 EVEX_CD8<32, CD8VF>;
891 defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem,
892 memopv8i64, X86pcmpeqm, v8i64>, T8PD, EVEX_V512,
893 VEX_W, EVEX_CD8<64, CD8VF>;
895 defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem,
896 memopv16i32, X86pcmpgtm, v16i32>, EVEX_V512,
897 EVEX_CD8<32, CD8VF>;
898 defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem,
899 memopv8i64, X86pcmpgtm, v8i64>, T8PD, EVEX_V512,
900 VEX_W, EVEX_CD8<64, CD8VF>;
902 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
903 (COPY_TO_REGCLASS (VPCMPGTDZrr
904 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
905 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
907 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
908 (COPY_TO_REGCLASS (VPCMPEQDZrr
909 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
910 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
912 multiclass avx512_icmp_cc<bits<8> opc, RegisterClass WMRC, RegisterClass KRC,
913 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
914 SDNode OpNode, ValueType vt, Operand CC, string Suffix> {
915 def rri : AVX512AIi8<opc, MRMSrcReg,
916 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc),
917 !strconcat("vpcmp${cc}", Suffix,
918 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
919 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))],
920 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
921 def rmi : AVX512AIi8<opc, MRMSrcMem,
922 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc),
923 !strconcat("vpcmp${cc}", Suffix,
924 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
925 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2),
926 imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
927 // Accept explicit immediate argument form instead of comparison code.
928 let isAsmParserOnly = 1, hasSideEffects = 0 in {
929 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
930 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
931 !strconcat("vpcmp", Suffix,
932 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
933 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
934 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
935 (outs KRC:$dst), (ins WMRC:$mask, RC:$src1, RC:$src2, i8imm:$cc),
936 !strconcat("vpcmp", Suffix,
937 "\t{$cc, $src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2, $cc}"),
938 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
939 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
940 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
941 !strconcat("vpcmp", Suffix,
942 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
943 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
944 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
945 (outs KRC:$dst), (ins WMRC:$mask, RC:$src1, x86memop:$src2, i8imm:$cc),
946 !strconcat("vpcmp", Suffix,
947 "\t{$cc, $src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2, $cc}"),
948 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
949 }
950 }
952 defm VPCMPDZ : avx512_icmp_cc<0x1F, VK16WM, VK16, VR512, i512mem, memopv16i32,
953 X86cmpm, v16i32, AVXCC, "d">,
954 EVEX_V512, EVEX_CD8<32, CD8VF>;
955 defm VPCMPUDZ : avx512_icmp_cc<0x1E, VK16WM, VK16, VR512, i512mem, memopv16i32,
956 X86cmpmu, v16i32, AVXCC, "ud">,
957 EVEX_V512, EVEX_CD8<32, CD8VF>;
959 defm VPCMPQZ : avx512_icmp_cc<0x1F, VK8WM, VK8, VR512, i512mem, memopv8i64,
960 X86cmpm, v8i64, AVXCC, "q">,
961 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
962 defm VPCMPUQZ : avx512_icmp_cc<0x1E, VK8WM, VK8, VR512, i512mem, memopv8i64,
963 X86cmpmu, v8i64, AVXCC, "uq">,
964 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
966 // avx512_cmp_packed - compare packed instructions
967 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
968 X86MemOperand x86memop, ValueType vt,
969 string suffix, Domain d> {
970 def rri : AVX512PIi8<0xC2, MRMSrcReg,
971 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
972 !strconcat("vcmp${cc}", suffix,
973 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
974 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
975 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
976 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
977 !strconcat("vcmp${cc}", suffix,
978 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
979 [], d>, EVEX_B;
980 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
981 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
982 !strconcat("vcmp${cc}", suffix,
983 " \t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
984 [(set KRC:$dst,
985 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
987 // Accept explicit immediate argument form instead of comparison code.
988 let isAsmParserOnly = 1, hasSideEffects = 0 in {
989 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
990 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
991 !strconcat("vcmp", suffix,
992 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
993 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
994 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
995 !strconcat("vcmp", suffix,
996 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
997 }
998 }
1000 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
1001 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
1002 EVEX_CD8<32, CD8VF>;
1003 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
1004 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
1005 EVEX_CD8<64, CD8VF>;
1007 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1008 (COPY_TO_REGCLASS (VCMPPSZrri
1009 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1010 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1011 imm:$cc), VK8)>;
1012 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1013 (COPY_TO_REGCLASS (VPCMPDZrri
1014 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1015 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1016 imm:$cc), VK8)>;
1017 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1018 (COPY_TO_REGCLASS (VPCMPUDZrri
1019 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1020 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1021 imm:$cc), VK8)>;
1023 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1024 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1025 FROUND_NO_EXC)),
1026 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
1027 (I8Imm imm:$cc)), GR16)>;
1029 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1030 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1031 FROUND_NO_EXC)),
1032 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
1033 (I8Imm imm:$cc)), GR8)>;
1035 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1036 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1037 FROUND_CURRENT)),
1038 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
1039 (I8Imm imm:$cc)), GR16)>;
1041 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1042 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1043 FROUND_CURRENT)),
1044 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
1045 (I8Imm imm:$cc)), GR8)>;
1047 // Mask register copy, including
1048 // - copy between mask registers
1049 // - load/store mask registers
1050 // - copy from GPR to mask register and vice versa
1051 //
1052 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1053 string OpcodeStr, RegisterClass KRC,
1054 ValueType vvt, ValueType ivt, X86MemOperand x86memop> {
1055 let hasSideEffects = 0 in {
1056 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1057 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1058 let mayLoad = 1 in
1059 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1060 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
1061 [(set KRC:$dst, (vvt (bitconvert (ivt (load addr:$src)))))]>;
1062 let mayStore = 1 in
1063 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1064 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1065 }
1066 }
1068 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1069 string OpcodeStr,
1070 RegisterClass KRC, RegisterClass GRC> {
1071 let hasSideEffects = 0 in {
1072 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1073 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1074 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1075 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1076 }
1077 }
1079 let Predicates = [HasDQI] in
1080 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8,
1081 i8mem>,
1082 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1083 VEX, PD;
1085 let Predicates = [HasAVX512] in
1086 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16,
1087 i16mem>,
1088 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
1089 VEX, PS;
1091 let Predicates = [HasBWI] in {
1092 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1, i32,
1093 i32mem>, VEX, PD, VEX_W;
1094 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1095 VEX, XD;
1096 }
1098 let Predicates = [HasBWI] in {
1099 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64,
1100 i64mem>, VEX, PS, VEX_W;
1101 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1102 VEX, XD, VEX_W;
1103 }
1105 // GR from/to mask register
1106 let Predicates = [HasDQI] in {
1107 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1108 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1109 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1110 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1111 }
1112 let Predicates = [HasAVX512] in {
1113 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1114 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1115 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1116 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
1117 }
1118 let Predicates = [HasBWI] in {
1119 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1120 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1121 }
1122 let Predicates = [HasBWI] in {
1123 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1124 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1125 }
1127 // Load/store kreg
1128 let Predicates = [HasDQI] in {
1129 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1130 (KMOVBmk addr:$dst, VK8:$src)>;
1131 }
1132 let Predicates = [HasAVX512] in {
1133 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
1134 (KMOVWmk addr:$dst, VK16:$src)>;
1135 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1136 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
1137 def : Pat<(i1 (load addr:$src)),
1138 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
1139 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1140 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
1141 }
1142 let Predicates = [HasBWI] in {
1143 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1144 (KMOVDmk addr:$dst, VK32:$src)>;
1145 }
1146 let Predicates = [HasBWI] in {
1147 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1148 (KMOVQmk addr:$dst, VK64:$src)>;
1149 }
1151 let Predicates = [HasAVX512] in {
1152 def : Pat<(i1 (trunc (i32 GR32:$src))),
1153 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
1155 def : Pat<(i1 (trunc (i8 GR8:$src))),
1156 (COPY_TO_REGCLASS
1157 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1158 VK1)>;
1159 def : Pat<(i1 (trunc (i16 GR16:$src))),
1160 (COPY_TO_REGCLASS
1161 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1162 VK1)>;
1164 def : Pat<(i32 (zext VK1:$src)),
1165 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
1166 def : Pat<(i8 (zext VK1:$src)),
1167 (EXTRACT_SUBREG
1168 (AND32ri (KMOVWrk
1169 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
1170 def : Pat<(i64 (zext VK1:$src)),
1171 (AND64ri8 (SUBREG_TO_REG (i64 0),
1172 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
1173 def : Pat<(i16 (zext VK1:$src)),
1174 (EXTRACT_SUBREG
1175 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1176 sub_16bit)>;
1177 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1178 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1179 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1180 (COPY_TO_REGCLASS VK1:$src, VK8)>;
1181 }
1182 let Predicates = [HasBWI] in {
1183 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
1184 (COPY_TO_REGCLASS VK1:$src, VK32)>;
1185 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
1186 (COPY_TO_REGCLASS VK1:$src, VK64)>;
1187 }
1190 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1191 let Predicates = [HasAVX512] in {
1192 // GR from/to 8-bit mask without native support
1193 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1194 (COPY_TO_REGCLASS
1195 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
1196 VK8)>;
1197 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1198 (EXTRACT_SUBREG
1199 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1200 sub_8bit)>;
1202 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1203 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1204 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1205 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1206 }
1207 let Predicates = [HasBWI] in {
1208 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
1209 (COPY_TO_REGCLASS VK32:$src, VK1)>;
1210 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
1211 (COPY_TO_REGCLASS VK64:$src, VK1)>;
1212 }
1214 // Mask unary operation
1215 // - KNOT
1216 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1217 RegisterClass KRC, SDPatternOperator OpNode,
1218 Predicate prd> {
1219 let Predicates = [prd] in
1220 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1221 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
1222 [(set KRC:$dst, (OpNode KRC:$src))]>;
1223 }
1225 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
1226 SDPatternOperator OpNode> {
1227 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1228 HasDQI>, VEX, PD;
1229 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1230 HasAVX512>, VEX, PS;
1231 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1232 HasBWI>, VEX, PD, VEX_W;
1233 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1234 HasBWI>, VEX, PS, VEX_W;
1235 }
1237 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
1239 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1240 let Predicates = [HasAVX512] in
1241 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1242 (i16 GR16:$src)),
1243 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1244 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1245 }
1246 defm : avx512_mask_unop_int<"knot", "KNOT">;
1248 let Predicates = [HasDQI] in
1249 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
1250 let Predicates = [HasAVX512] in
1251 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1252 let Predicates = [HasBWI] in
1253 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
1254 let Predicates = [HasBWI] in
1255 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
1257 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
1258 let Predicates = [HasAVX512] in {
1259 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1260 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1262 def : Pat<(not VK8:$src),
1263 (COPY_TO_REGCLASS
1264 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1265 }
1267 // Mask binary operation
1268 // - KAND, KANDN, KOR, KXNOR, KXOR
1269 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1270 RegisterClass KRC, SDPatternOperator OpNode,
1271 Predicate prd> {
1272 let Predicates = [prd] in
1273 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1274 !strconcat(OpcodeStr,
1275 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1276 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1277 }
1279 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
1280 SDPatternOperator OpNode> {
1281 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1282 HasDQI>, VEX_4V, VEX_L, PD;
1283 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1284 HasAVX512>, VEX_4V, VEX_L, PS;
1285 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1286 HasBWI>, VEX_4V, VEX_L, VEX_W, PD;
1287 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1288 HasBWI>, VEX_4V, VEX_L, VEX_W, PS;
1289 }
1291 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1292 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1294 let isCommutable = 1 in {
1295 defm KAND : avx512_mask_binop_all<0x41, "kand", and>;
1296 defm KOR : avx512_mask_binop_all<0x45, "kor", or>;
1297 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor>;
1298 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor>;
1299 }
1300 let isCommutable = 0 in
1301 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn>;
1303 def : Pat<(xor VK1:$src1, VK1:$src2),
1304 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1305 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1307 def : Pat<(or VK1:$src1, VK1:$src2),
1308 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1309 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1311 def : Pat<(and VK1:$src1, VK1:$src2),
1312 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1313 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1315 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1316 let Predicates = [HasAVX512] in
1317 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1318 (i16 GR16:$src1), (i16 GR16:$src2)),
1319 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1320 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1321 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1322 }
1324 defm : avx512_mask_binop_int<"kand", "KAND">;
1325 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1326 defm : avx512_mask_binop_int<"kor", "KOR">;
1327 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1328 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1330 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1331 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1332 let Predicates = [HasAVX512] in
1333 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1334 (COPY_TO_REGCLASS
1335 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1336 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1337 }
1339 defm : avx512_binop_pat<and, KANDWrr>;
1340 defm : avx512_binop_pat<andn, KANDNWrr>;
1341 defm : avx512_binop_pat<or, KORWrr>;
1342 defm : avx512_binop_pat<xnor, KXNORWrr>;
1343 defm : avx512_binop_pat<xor, KXORWrr>;
1345 // Mask unpacking
1346 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1347 RegisterClass KRC> {
1348 let Predicates = [HasAVX512] in
1349 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1350 !strconcat(OpcodeStr,
1351 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1352 }
1354 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1355 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1356 VEX_4V, VEX_L, PD;
1357 }
1359 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1360 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1361 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1362 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1365 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1366 let Predicates = [HasAVX512] in
1367 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1368 (i16 GR16:$src1), (i16 GR16:$src2)),
1369 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1370 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1371 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1372 }
1373 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1375 // Mask bit testing
1376 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1377 SDNode OpNode> {
1378 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1379 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1380 !strconcat(OpcodeStr, " \t{$src2, $src1|$src1, $src2}"),
1381 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1382 }
1384 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1385 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1386 VEX, PS;
1387 }
1389 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1391 def : Pat<(X86cmp VK1:$src1, (i1 0)),
1392 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1393 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
1395 // Mask shift
1396 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1397 SDNode OpNode> {
1398 let Predicates = [HasAVX512] in
1399 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1400 !strconcat(OpcodeStr,
1401 " \t{$imm, $src, $dst|$dst, $src, $imm}"),
1402 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1403 }
1405 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1406 SDNode OpNode> {
1407 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1408 VEX, TAPD, VEX_W;
1409 }
1411 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1412 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1414 // Mask setting all 0s or 1s
1415 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1416 let Predicates = [HasAVX512] in
1417 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1418 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1419 [(set KRC:$dst, (VT Val))]>;
1420 }
1422 multiclass avx512_mask_setop_w<PatFrag Val> {
1423 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1424 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1425 }
1427 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1428 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1430 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1431 let Predicates = [HasAVX512] in {
1432 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1433 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1434 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1435 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1436 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1437 }
1438 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1439 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1441 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1442 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1444 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1445 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1447 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
1448 (v8i1 (COPY_TO_REGCLASS (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1450 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
1451 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1452 //===----------------------------------------------------------------------===//
1453 // AVX-512 - Aligned and unaligned load and store
1454 //
1456 multiclass avx512_load<bits<8> opc, string OpcodeStr, PatFrag ld_frag,
1457 RegisterClass KRC, RegisterClass RC,
1458 ValueType vt, ValueType zvt, X86MemOperand memop,
1459 Domain d, bit IsReMaterializable = 1> {
1460 let hasSideEffects = 0 in {
1461 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1462 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
1463 d>, EVEX;
1464 def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
1465 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1466 "${dst} {${mask}} {z}, $src}"), [], d>, EVEX, EVEX_KZ;
1467 }
1468 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
1469 SchedRW = [WriteLoad] in
1470 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins memop:$src),
1471 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1472 [(set RC:$dst, (vt (bitconvert (ld_frag addr:$src))))],
1473 d>, EVEX;
1475 let AddedComplexity = 20 in {
1476 let Constraints = "$src0 = $dst", hasSideEffects = 0 in {
1477 let hasSideEffects = 0 in
1478 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1479 (ins RC:$src0, KRC:$mask, RC:$src1),
1480 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1481 "${dst} {${mask}}, $src1}"),
1482 [(set RC:$dst, (vt (vselect KRC:$mask,
1483 (vt RC:$src1),
1484 (vt RC:$src0))))],
1485 d>, EVEX, EVEX_K;
1486 let mayLoad = 1, SchedRW = [WriteLoad] in
1487 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1488 (ins RC:$src0, KRC:$mask, memop:$src1),
1489 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1490 "${dst} {${mask}}, $src1}"),
1491 [(set RC:$dst, (vt
1492 (vselect KRC:$mask,
1493 (vt (bitconvert (ld_frag addr:$src1))),
1494 (vt RC:$src0))))],
1495 d>, EVEX, EVEX_K;
1496 }
1497 let mayLoad = 1, SchedRW = [WriteLoad] in
1498 def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1499 (ins KRC:$mask, memop:$src),
1500 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1501 "${dst} {${mask}} {z}, $src}"),
1502 [(set RC:$dst, (vt
1503 (vselect KRC:$mask,
1504 (vt (bitconvert (ld_frag addr:$src))),
1505 (vt (bitconvert (zvt immAllZerosV))))))],
1506 d>, EVEX, EVEX_KZ;
1507 }
1508 }
1510 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr, string ld_pat,
1511 string elty, string elsz, string vsz512,
1512 string vsz256, string vsz128, Domain d,
1513 Predicate prd, bit IsReMaterializable = 1> {
1514 let Predicates = [prd] in
1515 defm Z : avx512_load<opc, OpcodeStr,
1516 !cast<PatFrag>(ld_pat##"v"##vsz512##elty##elsz),
1517 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
1518 !cast<ValueType>("v"##vsz512##elty##elsz), v16i32,
1519 !cast<X86MemOperand>(elty##"512mem"), d,
1520 IsReMaterializable>, EVEX_V512;
1522 let Predicates = [prd, HasVLX] in {
1523 defm Z256 : avx512_load<opc, OpcodeStr,
1524 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
1525 "v"##vsz256##elty##elsz, "v4i64")),
1526 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
1527 !cast<ValueType>("v"##vsz256##elty##elsz), v8i32,
1528 !cast<X86MemOperand>(elty##"256mem"), d,
1529 IsReMaterializable>, EVEX_V256;
1531 defm Z128 : avx512_load<opc, OpcodeStr,
1532 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
1533 "v"##vsz128##elty##elsz, "v2i64")),
1534 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
1535 !cast<ValueType>("v"##vsz128##elty##elsz), v4i32,
1536 !cast<X86MemOperand>(elty##"128mem"), d,
1537 IsReMaterializable>, EVEX_V128;
1538 }
1539 }
1542 multiclass avx512_store<bits<8> opc, string OpcodeStr, PatFrag st_frag,
1543 ValueType OpVT, RegisterClass KRC, RegisterClass RC,
1544 X86MemOperand memop, Domain d> {
1545 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1546 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
1547 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [], d>,
1548 EVEX;
1549 let Constraints = "$src1 = $dst" in
1550 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1551 (ins RC:$src1, KRC:$mask, RC:$src2),
1552 !strconcat(OpcodeStr,
1553 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1554 EVEX, EVEX_K;
1555 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1556 (ins KRC:$mask, RC:$src),
1557 !strconcat(OpcodeStr,
1558 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1559 [], d>, EVEX, EVEX_KZ;
1560 }
1561 let mayStore = 1 in {
1562 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
1563 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1564 [(st_frag (OpVT RC:$src), addr:$dst)], d>, EVEX;
1565 def mrk : AVX512PI<opc, MRMDestMem, (outs),
1566 (ins memop:$dst, KRC:$mask, RC:$src),
1567 !strconcat(OpcodeStr,
1568 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
1569 [], d>, EVEX, EVEX_K;
1570 }
1571 }
1574 multiclass avx512_store_vl<bits<8> opc, string OpcodeStr, string st_pat,
1575 string st_suff_512, string st_suff_256,
1576 string st_suff_128, string elty, string elsz,
1577 string vsz512, string vsz256, string vsz128,
1578 Domain d, Predicate prd> {
1579 let Predicates = [prd] in
1580 defm Z : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_512),
1581 !cast<ValueType>("v"##vsz512##elty##elsz),
1582 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
1583 !cast<X86MemOperand>(elty##"512mem"), d>, EVEX_V512;
1585 let Predicates = [prd, HasVLX] in {
1586 defm Z256 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_256),
1587 !cast<ValueType>("v"##vsz256##elty##elsz),
1588 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
1589 !cast<X86MemOperand>(elty##"256mem"), d>, EVEX_V256;
1591 defm Z128 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_128),
1592 !cast<ValueType>("v"##vsz128##elty##elsz),
1593 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
1594 !cast<X86MemOperand>(elty##"128mem"), d>, EVEX_V128;
1595 }
1596 }
1598 defm VMOVAPS : avx512_load_vl<0x28, "vmovaps", "alignedload", "f", "32",
1599 "16", "8", "4", SSEPackedSingle, HasAVX512>,
1600 avx512_store_vl<0x29, "vmovaps", "alignedstore",
1601 "512", "256", "", "f", "32", "16", "8", "4",
1602 SSEPackedSingle, HasAVX512>,
1603 PS, EVEX_CD8<32, CD8VF>;
1605 defm VMOVAPD : avx512_load_vl<0x28, "vmovapd", "alignedload", "f", "64",
1606 "8", "4", "2", SSEPackedDouble, HasAVX512>,
1607 avx512_store_vl<0x29, "vmovapd", "alignedstore",
1608 "512", "256", "", "f", "64", "8", "4", "2",
1609 SSEPackedDouble, HasAVX512>,
1610 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1612 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", "load", "f", "32",
1613 "16", "8", "4", SSEPackedSingle, HasAVX512>,
1614 avx512_store_vl<0x11, "vmovups", "store", "", "", "", "f", "32",
1615 "16", "8", "4", SSEPackedSingle, HasAVX512>,
1616 PS, EVEX_CD8<32, CD8VF>;
1618 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", "load", "f", "64",
1619 "8", "4", "2", SSEPackedDouble, HasAVX512, 0>,
1620 avx512_store_vl<0x11, "vmovupd", "store", "", "", "", "f", "64",
1621 "8", "4", "2", SSEPackedDouble, HasAVX512>,
1622 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1624 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
1625 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
1626 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
1628 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
1629 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
1630 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
1632 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
1633 GR16:$mask),
1634 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
1635 VR512:$src)>;
1636 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
1637 GR8:$mask),
1638 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
1639 VR512:$src)>;
1641 defm VMOVDQA32 : avx512_load_vl<0x6F, "vmovdqa32", "alignedload", "i", "32",
1642 "16", "8", "4", SSEPackedInt, HasAVX512>,
1643 avx512_store_vl<0x7F, "vmovdqa32", "alignedstore",
1644 "512", "256", "", "i", "32", "16", "8", "4",
1645 SSEPackedInt, HasAVX512>,
1646 PD, EVEX_CD8<32, CD8VF>;
1648 defm VMOVDQA64 : avx512_load_vl<0x6F, "vmovdqa64", "alignedload", "i", "64",
1649 "8", "4", "2", SSEPackedInt, HasAVX512>,
1650 avx512_store_vl<0x7F, "vmovdqa64", "alignedstore",
1651 "512", "256", "", "i", "64", "8", "4", "2",
1652 SSEPackedInt, HasAVX512>,
1653 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1655 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", "load", "i", "8",
1656 "64", "32", "16", SSEPackedInt, HasBWI>,
1657 avx512_store_vl<0x7F, "vmovdqu8", "store", "", "", "",
1658 "i", "8", "64", "32", "16", SSEPackedInt,
1659 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
1661 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", "load", "i", "16",
1662 "32", "16", "8", SSEPackedInt, HasBWI>,
1663 avx512_store_vl<0x7F, "vmovdqu16", "store", "", "", "",
1664 "i", "16", "32", "16", "8", SSEPackedInt,
1665 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
1667 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", "load", "i", "32",
1668 "16", "8", "4", SSEPackedInt, HasAVX512>,
1669 avx512_store_vl<0x7F, "vmovdqu32", "store", "", "", "",
1670 "i", "32", "16", "8", "4", SSEPackedInt,
1671 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
1673 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", "load", "i", "64",
1674 "8", "4", "2", SSEPackedInt, HasAVX512>,
1675 avx512_store_vl<0x7F, "vmovdqu64", "store", "", "", "",
1676 "i", "64", "8", "4", "2", SSEPackedInt,
1677 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
1679 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
1680 (v16i32 immAllZerosV), GR16:$mask)),
1681 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
1683 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
1684 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
1685 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
1687 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
1688 GR16:$mask),
1689 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
1690 VR512:$src)>;
1691 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
1692 GR8:$mask),
1693 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
1694 VR512:$src)>;
1696 let AddedComplexity = 20 in {
1697 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
1698 (bc_v8i64 (v16i32 immAllZerosV)))),
1699 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
1701 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
1702 (v8i64 VR512:$src))),
1703 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
1704 VK8), VR512:$src)>;
1706 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
1707 (v16i32 immAllZerosV))),
1708 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
1710 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
1711 (v16i32 VR512:$src))),
1712 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
1713 }
1715 // Move Int Doubleword to Packed Double Int
1716 //
1717 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
1718 "vmovd\t{$src, $dst|$dst, $src}",
1719 [(set VR128X:$dst,
1720 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
1721 EVEX, VEX_LIG;
1722 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
1723 "vmovd\t{$src, $dst|$dst, $src}",
1724 [(set VR128X:$dst,
1725 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
1726 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1727 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
1728 "vmovq\t{$src, $dst|$dst, $src}",
1729 [(set VR128X:$dst,
1730 (v2i64 (scalar_to_vector GR64:$src)))],
1731 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
1732 let isCodeGenOnly = 1 in {
1733 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1734 "vmovq\t{$src, $dst|$dst, $src}",
1735 [(set FR64:$dst, (bitconvert GR64:$src))],
1736 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1737 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1738 "vmovq\t{$src, $dst|$dst, $src}",
1739 [(set GR64:$dst, (bitconvert FR64:$src))],
1740 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1741 }
1742 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1743 "vmovq\t{$src, $dst|$dst, $src}",
1744 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
1745 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
1746 EVEX_CD8<64, CD8VT1>;
1748 // Move Int Doubleword to Single Scalar
1749 //
1750 let isCodeGenOnly = 1 in {
1751 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
1752 "vmovd\t{$src, $dst|$dst, $src}",
1753 [(set FR32X:$dst, (bitconvert GR32:$src))],
1754 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
1756 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
1757 "vmovd\t{$src, $dst|$dst, $src}",
1758 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
1759 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1760 }
1762 // Move doubleword from xmm register to r/m32
1763 //
1764 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
1765 "vmovd\t{$src, $dst|$dst, $src}",
1766 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
1767 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
1768 EVEX, VEX_LIG;
1769 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
1770 (ins i32mem:$dst, VR128X:$src),
1771 "vmovd\t{$src, $dst|$dst, $src}",
1772 [(store (i32 (vector_extract (v4i32 VR128X:$src),
1773 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
1774 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1776 // Move quadword from xmm1 register to r/m64
1777 //
1778 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
1779 "vmovq\t{$src, $dst|$dst, $src}",
1780 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
1781 (iPTR 0)))],
1782 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
1783 Requires<[HasAVX512, In64BitMode]>;
1785 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
1786 (ins i64mem:$dst, VR128X:$src),
1787 "vmovq\t{$src, $dst|$dst, $src}",
1788 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
1789 addr:$dst)], IIC_SSE_MOVDQ>,
1790 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
1791 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
1793 // Move Scalar Single to Double Int
1794 //
1795 let isCodeGenOnly = 1 in {
1796 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
1797 (ins FR32X:$src),
1798 "vmovd\t{$src, $dst|$dst, $src}",
1799 [(set GR32:$dst, (bitconvert FR32X:$src))],
1800 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
1801 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
1802 (ins i32mem:$dst, FR32X:$src),
1803 "vmovd\t{$src, $dst|$dst, $src}",
1804 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
1805 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1806 }
1808 // Move Quadword Int to Packed Quadword Int
1809 //
1810 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
1811 (ins i64mem:$src),
1812 "vmovq\t{$src, $dst|$dst, $src}",
1813 [(set VR128X:$dst,
1814 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
1815 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
1817 //===----------------------------------------------------------------------===//
1818 // AVX-512 MOVSS, MOVSD
1819 //===----------------------------------------------------------------------===//
1821 multiclass avx512_move_scalar <string asm, RegisterClass RC,
1822 SDNode OpNode, ValueType vt,
1823 X86MemOperand x86memop, PatFrag mem_pat> {
1824 let hasSideEffects = 0 in {
1825 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
1826 !strconcat(asm, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1827 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
1828 (scalar_to_vector RC:$src2))))],
1829 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
1830 let Constraints = "$src1 = $dst" in
1831 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
1832 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
1833 !strconcat(asm,
1834 " \t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
1835 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
1836 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1837 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1838 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
1839 EVEX, VEX_LIG;
1840 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1841 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1842 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
1843 EVEX, VEX_LIG;
1844 } //hasSideEffects = 0
1845 }
1847 let ExeDomain = SSEPackedSingle in
1848 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
1849 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
1851 let ExeDomain = SSEPackedDouble in
1852 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
1853 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
1855 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
1856 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
1857 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
1859 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
1860 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
1861 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
1863 // For the disassembler
1864 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
1865 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1866 (ins VR128X:$src1, FR32X:$src2),
1867 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1868 IIC_SSE_MOV_S_RR>,
1869 XS, EVEX_4V, VEX_LIG;
1870 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1871 (ins VR128X:$src1, FR64X:$src2),
1872 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1873 IIC_SSE_MOV_S_RR>,
1874 XD, EVEX_4V, VEX_LIG, VEX_W;
1875 }
1877 let Predicates = [HasAVX512] in {
1878 let AddedComplexity = 15 in {
1879 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
1880 // MOVS{S,D} to the lower bits.
1881 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
1882 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
1883 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
1884 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1885 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
1886 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1887 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
1888 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
1890 // Move low f32 and clear high bits.
1891 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
1892 (SUBREG_TO_REG (i32 0),
1893 (VMOVSSZrr (v4f32 (V_SET0)),
1894 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
1895 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
1896 (SUBREG_TO_REG (i32 0),
1897 (VMOVSSZrr (v4i32 (V_SET0)),
1898 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
1899 }
1901 let AddedComplexity = 20 in {
1902 // MOVSSrm zeros the high parts of the register; represent this
1903 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1904 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
1905 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1906 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
1907 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1908 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1909 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1911 // MOVSDrm zeros the high parts of the register; represent this
1912 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1913 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1914 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1915 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1916 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1917 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1918 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1919 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1920 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1921 def : Pat<(v2f64 (X86vzload addr:$src)),
1922 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1924 // Represent the same patterns above but in the form they appear for
1925 // 256-bit types
1926 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1927 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
1928 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
1929 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1930 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
1931 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
1932 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1933 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
1934 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
1935 }
1936 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1937 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
1938 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
1939 FR32X:$src)), sub_xmm)>;
1940 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1941 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
1942 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
1943 FR64X:$src)), sub_xmm)>;
1944 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1945 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
1946 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
1948 // Move low f64 and clear high bits.
1949 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
1950 (SUBREG_TO_REG (i32 0),
1951 (VMOVSDZrr (v2f64 (V_SET0)),
1952 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
1954 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
1955 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
1956 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
1958 // Extract and store.
1959 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
1960 addr:$dst),
1961 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
1962 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
1963 addr:$dst),
1964 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
1966 // Shuffle with VMOVSS
1967 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
1968 (VMOVSSZrr (v4i32 VR128X:$src1),
1969 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
1970 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
1971 (VMOVSSZrr (v4f32 VR128X:$src1),
1972 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
1974 // 256-bit variants
1975 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
1976 (SUBREG_TO_REG (i32 0),
1977 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
1978 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
1979 sub_xmm)>;
1980 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
1981 (SUBREG_TO_REG (i32 0),
1982 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
1983 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
1984 sub_xmm)>;
1986 // Shuffle with VMOVSD
1987 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1988 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1989 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1990 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1991 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1992 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1993 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1994 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1996 // 256-bit variants
1997 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1998 (SUBREG_TO_REG (i32 0),
1999 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
2000 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
2001 sub_xmm)>;
2002 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2003 (SUBREG_TO_REG (i32 0),
2004 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
2005 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
2006 sub_xmm)>;
2008 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2009 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2010 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2011 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2012 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2013 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2014 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2015 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2016 }
2018 let AddedComplexity = 15 in
2019 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
2020 (ins VR128X:$src),
2021 "vmovq\t{$src, $dst|$dst, $src}",
2022 [(set VR128X:$dst, (v2i64 (X86vzmovl
2023 (v2i64 VR128X:$src))))],
2024 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
2026 let AddedComplexity = 20 in
2027 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
2028 (ins i128mem:$src),
2029 "vmovq\t{$src, $dst|$dst, $src}",
2030 [(set VR128X:$dst, (v2i64 (X86vzmovl
2031 (loadv2i64 addr:$src))))],
2032 IIC_SSE_MOVDQ>, EVEX, VEX_W,
2033 EVEX_CD8<8, CD8VT8>;
2035 let Predicates = [HasAVX512] in {
2036 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
2037 let AddedComplexity = 20 in {
2038 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
2039 (VMOVDI2PDIZrm addr:$src)>;
2040 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
2041 (VMOV64toPQIZrr GR64:$src)>;
2042 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
2043 (VMOVDI2PDIZrr GR32:$src)>;
2045 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2046 (VMOVDI2PDIZrm addr:$src)>;
2047 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2048 (VMOVDI2PDIZrm addr:$src)>;
2049 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2050 (VMOVZPQILo2PQIZrm addr:$src)>;
2051 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
2052 (VMOVZPQILo2PQIZrr VR128X:$src)>;
2053 def : Pat<(v2i64 (X86vzload addr:$src)),
2054 (VMOVZPQILo2PQIZrm addr:$src)>;
2055 }
2057 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
2058 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2059 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
2060 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
2061 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2062 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
2063 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
2064 }
2066 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
2067 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2069 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
2070 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2072 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
2073 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2075 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
2076 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2078 //===----------------------------------------------------------------------===//
2079 // AVX-512 - Non-temporals
2080 //===----------------------------------------------------------------------===//
2082 def VMOVNTDQAZrm : AVX5128I<0x2A, MRMSrcMem, (outs VR512:$dst),
2083 (ins i512mem:$src),
2084 "vmovntdqa\t{$src, $dst|$dst, $src}",
2085 [(set VR512:$dst,
2086 (int_x86_avx512_movntdqa addr:$src))]>,
2087 EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
2089 // Prefer non-temporal over temporal versions
2090 let AddedComplexity = 400, SchedRW = [WriteStore] in {
2092 def VMOVNTPSZmr : AVX512PSI<0x2B, MRMDestMem, (outs),
2093 (ins f512mem:$dst, VR512:$src),
2094 "vmovntps\t{$src, $dst|$dst, $src}",
2095 [(alignednontemporalstore (v16f32 VR512:$src),
2096 addr:$dst)],
2097 IIC_SSE_MOVNT>,
2098 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2100 def VMOVNTPDZmr : AVX512PDI<0x2B, MRMDestMem, (outs),
2101 (ins f512mem:$dst, VR512:$src),
2102 "vmovntpd\t{$src, $dst|$dst, $src}",
2103 [(alignednontemporalstore (v8f64 VR512:$src),
2104 addr:$dst)],
2105 IIC_SSE_MOVNT>,
2106 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2109 def VMOVNTDQZmr : AVX512BI<0xE7, MRMDestMem, (outs),
2110 (ins i512mem:$dst, VR512:$src),
2111 "vmovntdq\t{$src, $dst|$dst, $src}",
2112 [(alignednontemporalstore (v8i64 VR512:$src),
2113 addr:$dst)],
2114 IIC_SSE_MOVNT>,
2115 EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
2116 }
2118 //===----------------------------------------------------------------------===//
2119 // AVX-512 - Integer arithmetic
2120 //
2121 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2122 ValueType OpVT, RegisterClass KRC,
2123 RegisterClass RC, PatFrag memop_frag,
2124 X86MemOperand x86memop, PatFrag scalar_mfrag,
2125 X86MemOperand x86scalar_mop, string BrdcstStr,
2126 OpndItins itins, bit IsCommutable = 0> {
2127 let isCommutable = IsCommutable in
2128 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2129 (ins RC:$src1, RC:$src2),
2130 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2131 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
2132 itins.rr>, EVEX_4V;
2133 let AddedComplexity = 30 in {
2134 let Constraints = "$src0 = $dst" in
2135 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2136 (ins RC:$src0, KRC:$mask, RC:$src1, RC:$src2),
2137 !strconcat(OpcodeStr,
2138 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2139 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2140 (OpNode (OpVT RC:$src1), (OpVT RC:$src2)),
2141 RC:$src0)))],
2142 itins.rr>, EVEX_4V, EVEX_K;
2143 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2144 (ins KRC:$mask, RC:$src1, RC:$src2),
2145 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
2146 "|$dst {${mask}} {z}, $src1, $src2}"),
2147 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2148 (OpNode (OpVT RC:$src1), (OpVT RC:$src2)),
2149 (OpVT immAllZerosV))))],
2150 itins.rr>, EVEX_4V, EVEX_KZ;
2151 }
2153 let mayLoad = 1 in {
2154 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2155 (ins RC:$src1, x86memop:$src2),
2156 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2157 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
2158 itins.rm>, EVEX_4V;
2159 let AddedComplexity = 30 in {
2160 let Constraints = "$src0 = $dst" in
2161 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2162 (ins RC:$src0, KRC:$mask, RC:$src1, x86memop:$src2),
2163 !strconcat(OpcodeStr,
2164 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2165 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2166 (OpNode (OpVT RC:$src1), (memop_frag addr:$src2)),
2167 RC:$src0)))],
2168 itins.rm>, EVEX_4V, EVEX_K;
2169 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2170 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2171 !strconcat(OpcodeStr,
2172 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2173 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2174 (OpNode (OpVT RC:$src1), (memop_frag addr:$src2)),
2175 (OpVT immAllZerosV))))],
2176 itins.rm>, EVEX_4V, EVEX_KZ;
2177 }
2178 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2179 (ins RC:$src1, x86scalar_mop:$src2),
2180 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2181 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2182 [(set RC:$dst, (OpNode RC:$src1,
2183 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
2184 itins.rm>, EVEX_4V, EVEX_B;
2185 let AddedComplexity = 30 in {
2186 let Constraints = "$src0 = $dst" in
2187 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2188 (ins RC:$src0, KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2189 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2190 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
2191 BrdcstStr, "}"),
2192 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2193 (OpNode (OpVT RC:$src1),
2194 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))),
2195 RC:$src0)))],
2196 itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
2197 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2198 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2199 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2200 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2201 BrdcstStr, "}"),
2202 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2203 (OpNode (OpVT RC:$src1),
2204 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))),
2205 (OpVT immAllZerosV))))],
2206 itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
2207 }
2208 }
2209 }
2211 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT,
2212 ValueType SrcVT, RegisterClass KRC, RegisterClass RC,
2213 PatFrag memop_frag, X86MemOperand x86memop,
2214 PatFrag scalar_mfrag, X86MemOperand x86scalar_mop,
2215 string BrdcstStr, OpndItins itins, bit IsCommutable = 0> {
2216 let isCommutable = IsCommutable in
2217 {
2218 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2219 (ins RC:$src1, RC:$src2),
2220 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2221 []>, EVEX_4V;
2222 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2223 (ins KRC:$mask, RC:$src1, RC:$src2),
2224 !strconcat(OpcodeStr,
2225 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2226 [], itins.rr>, EVEX_4V, EVEX_K;
2227 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2228 (ins KRC:$mask, RC:$src1, RC:$src2),
2229 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
2230 "|$dst {${mask}} {z}, $src1, $src2}"),
2231 [], itins.rr>, EVEX_4V, EVEX_KZ;
2232 }
2233 let mayLoad = 1 in {
2234 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2235 (ins RC:$src1, x86memop:$src2),
2236 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2237 []>, EVEX_4V;
2238 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2239 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2240 !strconcat(OpcodeStr,
2241 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2242 [], itins.rm>, EVEX_4V, EVEX_K;
2243 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2244 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2245 !strconcat(OpcodeStr,
2246 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2247 [], itins.rm>, EVEX_4V, EVEX_KZ;
2248 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2249 (ins RC:$src1, x86scalar_mop:$src2),
2250 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2251 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2252 [], itins.rm>, EVEX_4V, EVEX_B;
2253 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2254 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2255 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2256 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
2257 BrdcstStr, "}"),
2258 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
2259 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2260 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2261 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2262 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2263 BrdcstStr, "}"),
2264 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
2265 }
2266 }
2268 defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VK16WM, VR512,
2269 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2270 SSE_INTALU_ITINS_P, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2272 defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VK16WM, VR512,
2273 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2274 SSE_INTALU_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2276 defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VK16WM, VR512,
2277 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2278 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2280 defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VK8WM, VR512,
2281 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2282 SSE_INTALU_ITINS_P, 1>, EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
2284 defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VK8WM, VR512,
2285 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2286 SSE_INTALU_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2288 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512,
2289 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2290 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512,
2291 EVEX_CD8<64, CD8VF>, VEX_W;
2293 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32, VK8WM, VR512,
2294 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2295 SSE_INTMUL_ITINS_P, 1>, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
2297 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
2298 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2300 def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
2301 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2302 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2303 def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
2304 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2305 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
2307 defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxud", X86umax, v16i32, VK16WM, VR512,
2308 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2309 SSE_INTALU_ITINS_P, 1>,
2310 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2311 defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxuq", X86umax, v8i64, VK8WM, VR512,
2312 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2313 SSE_INTALU_ITINS_P, 0>,
2314 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2316 defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxsd", X86smax, v16i32, VK16WM, VR512,
2317 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2318 SSE_INTALU_ITINS_P, 1>,
2319 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2320 defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxsq", X86smax, v8i64, VK8WM, VR512,
2321 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2322 SSE_INTALU_ITINS_P, 0>,
2323 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2325 defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminud", X86umin, v16i32, VK16WM, VR512,
2326 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2327 SSE_INTALU_ITINS_P, 1>,
2328 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2329 defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminuq", X86umin, v8i64, VK8WM, VR512,
2330 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2331 SSE_INTALU_ITINS_P, 0>,
2332 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2334 defm VPMINSDZ : avx512_binop_rm<0x39, "vpminsd", X86smin, v16i32, VK16WM, VR512,
2335 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2336 SSE_INTALU_ITINS_P, 1>,
2337 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2338 defm VPMINSQZ : avx512_binop_rm<0x39, "vpminsq", X86smin, v8i64, VK8WM, VR512,
2339 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2340 SSE_INTALU_ITINS_P, 0>,
2341 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2343 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
2344 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2345 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
2346 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
2347 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2348 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
2349 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
2350 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2351 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
2352 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
2353 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2354 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
2355 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
2356 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2357 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
2358 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
2359 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2360 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
2361 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
2362 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2363 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
2364 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
2365 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2366 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
2367 //===----------------------------------------------------------------------===//
2368 // AVX-512 - Unpack Instructions
2369 //===----------------------------------------------------------------------===//
2371 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
2372 PatFrag mem_frag, RegisterClass RC,
2373 X86MemOperand x86memop, string asm,
2374 Domain d> {
2375 def rr : AVX512PI<opc, MRMSrcReg,
2376 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2377 asm, [(set RC:$dst,
2378 (vt (OpNode RC:$src1, RC:$src2)))],
2379 d>, EVEX_4V;
2380 def rm : AVX512PI<opc, MRMSrcMem,
2381 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2382 asm, [(set RC:$dst,
2383 (vt (OpNode RC:$src1,
2384 (bitconvert (mem_frag addr:$src2)))))],
2385 d>, EVEX_4V;
2386 }
2388 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
2389 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2390 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
2391 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
2392 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2393 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2394 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
2395 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2396 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
2397 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
2398 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2399 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2401 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
2402 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2403 X86MemOperand x86memop> {
2404 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2405 (ins RC:$src1, RC:$src2),
2406 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2407 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
2408 IIC_SSE_UNPCK>, EVEX_4V;
2409 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2410 (ins RC:$src1, x86memop:$src2),
2411 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2412 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
2413 (bitconvert (memop_frag addr:$src2)))))],
2414 IIC_SSE_UNPCK>, EVEX_4V;
2415 }
2416 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
2417 VR512, memopv16i32, i512mem>, EVEX_V512,
2418 EVEX_CD8<32, CD8VF>;
2419 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
2420 VR512, memopv8i64, i512mem>, EVEX_V512,
2421 VEX_W, EVEX_CD8<64, CD8VF>;
2422 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
2423 VR512, memopv16i32, i512mem>, EVEX_V512,
2424 EVEX_CD8<32, CD8VF>;
2425 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
2426 VR512, memopv8i64, i512mem>, EVEX_V512,
2427 VEX_W, EVEX_CD8<64, CD8VF>;
2428 //===----------------------------------------------------------------------===//
2429 // AVX-512 - PSHUFD
2430 //
2432 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
2433 SDNode OpNode, PatFrag mem_frag,
2434 X86MemOperand x86memop, ValueType OpVT> {
2435 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
2436 (ins RC:$src1, i8imm:$src2),
2437 !strconcat(OpcodeStr,
2438 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2439 [(set RC:$dst,
2440 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
2441 EVEX;
2442 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
2443 (ins x86memop:$src1, i8imm:$src2),
2444 !strconcat(OpcodeStr,
2445 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2446 [(set RC:$dst,
2447 (OpVT (OpNode (mem_frag addr:$src1),
2448 (i8 imm:$src2))))]>, EVEX;
2449 }
2451 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
2452 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2454 let ExeDomain = SSEPackedSingle in
2455 defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilp,
2456 memopv16f32, i512mem, v16f32>, TAPD, EVEX_V512,
2457 EVEX_CD8<32, CD8VF>;
2458 let ExeDomain = SSEPackedDouble in
2459 defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilp,
2460 memopv8f64, i512mem, v8f64>, TAPD, EVEX_V512,
2461 VEX_W, EVEX_CD8<32, CD8VF>;
2463 def : Pat<(v16i32 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
2464 (VPERMILPSZri VR512:$src1, imm:$imm)>;
2465 def : Pat<(v8i64 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
2466 (VPERMILPDZri VR512:$src1, imm:$imm)>;
2468 //===----------------------------------------------------------------------===//
2469 // AVX-512 Logical Instructions
2470 //===----------------------------------------------------------------------===//
2472 defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VK16WM, VR512, memopv16i32,
2473 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2474 EVEX_V512, EVEX_CD8<32, CD8VF>;
2475 defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VK8WM, VR512, memopv8i64,
2476 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2477 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2478 defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VK16WM, VR512, memopv16i32,
2479 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2480 EVEX_V512, EVEX_CD8<32, CD8VF>;
2481 defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VK8WM, VR512, memopv8i64,
2482 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2483 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2484 defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VK16WM, VR512, memopv16i32,
2485 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2486 EVEX_V512, EVEX_CD8<32, CD8VF>;
2487 defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VK8WM, VR512, memopv8i64,
2488 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2489 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2490 defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VK16WM, VR512,
2491 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2492 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2493 defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VK8WM, VR512,
2494 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2495 SSE_BIT_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2497 //===----------------------------------------------------------------------===//
2498 // AVX-512 FP arithmetic
2499 //===----------------------------------------------------------------------===//
2501 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2502 SizeItins itins> {
2503 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
2504 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
2505 EVEX_CD8<32, CD8VT1>;
2506 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
2507 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
2508 EVEX_CD8<64, CD8VT1>;
2509 }
2511 let isCommutable = 1 in {
2512 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
2513 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
2514 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
2515 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
2516 }
2517 let isCommutable = 0 in {
2518 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
2519 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
2520 }
2522 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
2523 RegisterClass KRC,
2524 RegisterClass RC, ValueType vt,
2525 X86MemOperand x86memop, PatFrag mem_frag,
2526 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2527 string BrdcstStr,
2528 Domain d, OpndItins itins, bit commutable> {
2529 let isCommutable = commutable in {
2530 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2531 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2532 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
2533 EVEX_4V;
2535 def rrk: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2536 !strconcat(OpcodeStr,
2537 " \t{$src2, $src1, $dst {${mask}} |$dst {${mask}}, $src1, $src2}"),
2538 [], itins.rr, d>, EVEX_4V, EVEX_K;
2540 def rrkz: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2541 !strconcat(OpcodeStr,
2542 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2543 [], itins.rr, d>, EVEX_4V, EVEX_KZ;
2544 }
2546 let mayLoad = 1 in {
2547 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2548 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2549 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
2550 itins.rm, d>, EVEX_4V;
2552 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
2553 (ins RC:$src1, x86scalar_mop:$src2),
2554 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2555 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2556 [(set RC:$dst, (OpNode RC:$src1,
2557 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
2558 itins.rm, d>, EVEX_4V, EVEX_B;
2560 def rmk : PI<opc, MRMSrcMem, (outs RC:$dst),
2561 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2562 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2563 [], itins.rm, d>, EVEX_4V, EVEX_K;
2565 def rmkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2566 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2567 "\t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2568 [], itins.rm, d>, EVEX_4V, EVEX_KZ;
2570 def rmbk : PI<opc, MRMSrcMem, (outs RC:$dst),
2571 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2572 " \t{${src2}", BrdcstStr,
2573 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}", BrdcstStr, "}"),
2574 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_K;
2576 def rmbkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2577 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2578 " \t{${src2}", BrdcstStr,
2579 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2580 BrdcstStr, "}"),
2581 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_KZ;
2582 }
2583 }
2585 defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VK16WM, VR512, v16f32, f512mem,
2586 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2587 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2589 defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VK8WM, VR512, v8f64, f512mem,
2590 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2591 SSE_ALU_ITINS_P.d, 1>,
2592 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2594 defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VK16WM, VR512, v16f32, f512mem,
2595 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2596 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2597 defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VK8WM, VR512, v8f64, f512mem,
2598 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2599 SSE_ALU_ITINS_P.d, 1>,
2600 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2602 defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VK16WM, VR512, v16f32, f512mem,
2603 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2604 SSE_ALU_ITINS_P.s, 1>,
2605 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2606 defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VK16WM, VR512, v16f32, f512mem,
2607 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2608 SSE_ALU_ITINS_P.s, 1>,
2609 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2611 defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VK8WM, VR512, v8f64, f512mem,
2612 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2613 SSE_ALU_ITINS_P.d, 1>,
2614 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2615 defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VK8WM, VR512, v8f64, f512mem,
2616 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2617 SSE_ALU_ITINS_P.d, 1>,
2618 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2620 defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VK16WM, VR512, v16f32, f512mem,
2621 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2622 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2623 defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VK16WM, VR512, v16f32, f512mem,
2624 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2625 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2627 defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VK8WM, VR512, v8f64, f512mem,
2628 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2629 SSE_ALU_ITINS_P.d, 0>,
2630 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2631 defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VK8WM, VR512, v8f64, f512mem,
2632 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2633 SSE_ALU_ITINS_P.d, 0>,
2634 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2636 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
2637 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2638 (i16 -1), FROUND_CURRENT)),
2639 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
2641 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
2642 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2643 (i8 -1), FROUND_CURRENT)),
2644 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
2646 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
2647 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2648 (i16 -1), FROUND_CURRENT)),
2649 (VMINPSZrr VR512:$src1, VR512:$src2)>;
2651 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
2652 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2653 (i8 -1), FROUND_CURRENT)),
2654 (VMINPDZrr VR512:$src1, VR512:$src2)>;
2655 //===----------------------------------------------------------------------===//
2656 // AVX-512 VPTESTM instructions
2657 //===----------------------------------------------------------------------===//
2659 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2660 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
2661 SDNode OpNode, ValueType vt> {
2662 def rr : AVX512PI<opc, MRMSrcReg,
2663 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
2664 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2665 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
2666 SSEPackedInt>, EVEX_4V;
2667 def rm : AVX512PI<opc, MRMSrcMem,
2668 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
2669 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2670 [(set KRC:$dst, (OpNode (vt RC:$src1),
2671 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
2672 }
2674 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
2675 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
2676 EVEX_CD8<32, CD8VF>;
2677 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
2678 memopv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
2679 EVEX_CD8<64, CD8VF>;
2681 let Predicates = [HasCDI] in {
2682 defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
2683 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
2684 EVEX_CD8<32, CD8VF>;
2685 defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
2686 memopv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
2687 EVEX_CD8<64, CD8VF>;
2688 }
2690 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
2691 (v16i32 VR512:$src2), (i16 -1))),
2692 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
2694 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
2695 (v8i64 VR512:$src2), (i8 -1))),
2696 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
2697 //===----------------------------------------------------------------------===//
2698 // AVX-512 Shift instructions
2699 //===----------------------------------------------------------------------===//
2700 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
2701 string OpcodeStr, SDNode OpNode, RegisterClass RC,
2702 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
2703 RegisterClass KRC> {
2704 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2705 (ins RC:$src1, i8imm:$src2),
2706 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2707 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
2708 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2709 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2710 (ins KRC:$mask, RC:$src1, i8imm:$src2),
2711 !strconcat(OpcodeStr,
2712 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2713 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2714 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2715 (ins x86memop:$src1, i8imm:$src2),
2716 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2717 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
2718 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2719 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2720 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
2721 !strconcat(OpcodeStr,
2722 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2723 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2724 }
2726 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2727 RegisterClass RC, ValueType vt, ValueType SrcVT,
2728 PatFrag bc_frag, RegisterClass KRC> {
2729 // src2 is always 128-bit
2730 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2731 (ins RC:$src1, VR128X:$src2),
2732 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2733 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
2734 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2735 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2736 (ins KRC:$mask, RC:$src1, VR128X:$src2),
2737 !strconcat(OpcodeStr,
2738 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2739 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2740 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2741 (ins RC:$src1, i128mem:$src2),
2742 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2743 [(set RC:$dst, (vt (OpNode RC:$src1,
2744 (bc_frag (memopv2i64 addr:$src2)))))],
2745 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2746 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2747 (ins KRC:$mask, RC:$src1, i128mem:$src2),
2748 !strconcat(OpcodeStr,
2749 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2750 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2751 }
2753 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
2754 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2755 EVEX_V512, EVEX_CD8<32, CD8VF>;
2756 defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
2757 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2758 EVEX_CD8<32, CD8VQ>;
2760 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
2761 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2762 EVEX_CD8<64, CD8VF>, VEX_W;
2763 defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
2764 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2765 EVEX_CD8<64, CD8VQ>, VEX_W;
2767 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
2768 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
2769 EVEX_CD8<32, CD8VF>;
2770 defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
2771 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2772 EVEX_CD8<32, CD8VQ>;
2774 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
2775 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2776 EVEX_CD8<64, CD8VF>, VEX_W;
2777 defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
2778 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2779 EVEX_CD8<64, CD8VQ>, VEX_W;
2781 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
2782 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2783 EVEX_V512, EVEX_CD8<32, CD8VF>;
2784 defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
2785 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2786 EVEX_CD8<32, CD8VQ>;
2788 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
2789 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2790 EVEX_CD8<64, CD8VF>, VEX_W;
2791 defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
2792 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2793 EVEX_CD8<64, CD8VQ>, VEX_W;
2795 //===-------------------------------------------------------------------===//
2796 // Variable Bit Shifts
2797 //===-------------------------------------------------------------------===//
2798 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
2799 RegisterClass RC, ValueType vt,
2800 X86MemOperand x86memop, PatFrag mem_frag> {
2801 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
2802 (ins RC:$src1, RC:$src2),
2803 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2804 [(set RC:$dst,
2805 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
2806 EVEX_4V;
2807 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
2808 (ins RC:$src1, x86memop:$src2),
2809 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2810 [(set RC:$dst,
2811 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
2812 EVEX_4V;
2813 }
2815 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
2816 i512mem, memopv16i32>, EVEX_V512,
2817 EVEX_CD8<32, CD8VF>;
2818 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
2819 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2820 EVEX_CD8<64, CD8VF>;
2821 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
2822 i512mem, memopv16i32>, EVEX_V512,
2823 EVEX_CD8<32, CD8VF>;
2824 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
2825 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2826 EVEX_CD8<64, CD8VF>;
2827 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
2828 i512mem, memopv16i32>, EVEX_V512,
2829 EVEX_CD8<32, CD8VF>;
2830 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
2831 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2832 EVEX_CD8<64, CD8VF>;
2834 //===----------------------------------------------------------------------===//
2835 // AVX-512 - MOVDDUP
2836 //===----------------------------------------------------------------------===//
2838 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
2839 X86MemOperand x86memop, PatFrag memop_frag> {
2840 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2841 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2842 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
2843 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2844 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2845 [(set RC:$dst,
2846 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
2847 }
2849 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
2850 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
2851 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
2852 (VMOVDDUPZrm addr:$src)>;
2854 //===---------------------------------------------------------------------===//
2855 // Replicate Single FP - MOVSHDUP and MOVSLDUP
2856 //===---------------------------------------------------------------------===//
2857 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
2858 ValueType vt, RegisterClass RC, PatFrag mem_frag,
2859 X86MemOperand x86memop> {
2860 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2861 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2862 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
2863 let mayLoad = 1 in
2864 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2865 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2866 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
2867 }
2869 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
2870 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2871 EVEX_CD8<32, CD8VF>;
2872 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
2873 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2874 EVEX_CD8<32, CD8VF>;
2876 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
2877 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
2878 (VMOVSHDUPZrm addr:$src)>;
2879 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
2880 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
2881 (VMOVSLDUPZrm addr:$src)>;
2883 //===----------------------------------------------------------------------===//
2884 // Move Low to High and High to Low packed FP Instructions
2885 //===----------------------------------------------------------------------===//
2886 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
2887 (ins VR128X:$src1, VR128X:$src2),
2888 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2889 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
2890 IIC_SSE_MOV_LH>, EVEX_4V;
2891 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
2892 (ins VR128X:$src1, VR128X:$src2),
2893 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2894 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
2895 IIC_SSE_MOV_LH>, EVEX_4V;
2897 let Predicates = [HasAVX512] in {
2898 // MOVLHPS patterns
2899 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2900 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
2901 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2902 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
2904 // MOVHLPS patterns
2905 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
2906 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
2907 }
2909 //===----------------------------------------------------------------------===//
2910 // FMA - Fused Multiply Operations
2911 //
2912 let Constraints = "$src1 = $dst" in {
2913 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr,
2914 RegisterClass RC, X86MemOperand x86memop,
2915 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2916 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2917 def r: AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2918 (ins RC:$src1, RC:$src2, RC:$src3),
2919 !strconcat(OpcodeStr," \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2920 [(set RC:$dst, (OpVT(OpNode RC:$src1, RC:$src2, RC:$src3)))]>;
2922 let mayLoad = 1 in
2923 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2924 (ins RC:$src1, RC:$src2, x86memop:$src3),
2925 !strconcat(OpcodeStr, " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2926 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2,
2927 (mem_frag addr:$src3))))]>;
2928 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2929 (ins RC:$src1, RC:$src2, x86scalar_mop:$src3),
2930 !strconcat(OpcodeStr, " \t{${src3}", BrdcstStr,
2931 ", $src2, $dst|$dst, $src2, ${src3}", BrdcstStr, "}"),
2932 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
2933 (OpVT (X86VBroadcast (scalar_mfrag addr:$src3)))))]>, EVEX_B;
2934 }
2935 } // Constraints = "$src1 = $dst"
2937 let ExeDomain = SSEPackedSingle in {
2938 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", VR512, f512mem,
2939 memopv16f32, f32mem, loadf32, "{1to16}",
2940 X86Fmadd, v16f32>, EVEX_V512,
2941 EVEX_CD8<32, CD8VF>;
2942 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", VR512, f512mem,
2943 memopv16f32, f32mem, loadf32, "{1to16}",
2944 X86Fmsub, v16f32>, EVEX_V512,
2945 EVEX_CD8<32, CD8VF>;
2946 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", VR512, f512mem,
2947 memopv16f32, f32mem, loadf32, "{1to16}",
2948 X86Fmaddsub, v16f32>,
2949 EVEX_V512, EVEX_CD8<32, CD8VF>;
2950 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", VR512, f512mem,
2951 memopv16f32, f32mem, loadf32, "{1to16}",
2952 X86Fmsubadd, v16f32>,
2953 EVEX_V512, EVEX_CD8<32, CD8VF>;
2954 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", VR512, f512mem,
2955 memopv16f32, f32mem, loadf32, "{1to16}",
2956 X86Fnmadd, v16f32>, EVEX_V512,
2957 EVEX_CD8<32, CD8VF>;
2958 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", VR512, f512mem,
2959 memopv16f32, f32mem, loadf32, "{1to16}",
2960 X86Fnmsub, v16f32>, EVEX_V512,
2961 EVEX_CD8<32, CD8VF>;
2962 }
2963 let ExeDomain = SSEPackedDouble in {
2964 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", VR512, f512mem,
2965 memopv8f64, f64mem, loadf64, "{1to8}",
2966 X86Fmadd, v8f64>, EVEX_V512,
2967 VEX_W, EVEX_CD8<64, CD8VF>;
2968 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", VR512, f512mem,
2969 memopv8f64, f64mem, loadf64, "{1to8}",
2970 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2971 EVEX_CD8<64, CD8VF>;
2972 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", VR512, f512mem,
2973 memopv8f64, f64mem, loadf64, "{1to8}",
2974 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2975 EVEX_CD8<64, CD8VF>;
2976 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", VR512, f512mem,
2977 memopv8f64, f64mem, loadf64, "{1to8}",
2978 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2979 EVEX_CD8<64, CD8VF>;
2980 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", VR512, f512mem,
2981 memopv8f64, f64mem, loadf64, "{1to8}",
2982 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2983 EVEX_CD8<64, CD8VF>;
2984 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", VR512, f512mem,
2985 memopv8f64, f64mem, loadf64, "{1to8}",
2986 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2987 EVEX_CD8<64, CD8VF>;
2988 }
2990 let Constraints = "$src1 = $dst" in {
2991 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr,
2992 RegisterClass RC, X86MemOperand x86memop,
2993 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2994 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2995 let mayLoad = 1 in
2996 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2997 (ins RC:$src1, RC:$src3, x86memop:$src2),
2998 !strconcat(OpcodeStr, " \t{$src2, $src3, $dst|$dst, $src3, $src2}"),
2999 [(set RC:$dst, (OpVT (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3)))]>;
3000 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
3001 (ins RC:$src1, RC:$src3, x86scalar_mop:$src2),
3002 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
3003 ", $src3, $dst|$dst, $src3, ${src2}", BrdcstStr, "}"),
3004 [(set RC:$dst, (OpNode RC:$src1,
3005 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2))), RC:$src3))]>, EVEX_B;
3006 }
3007 } // Constraints = "$src1 = $dst"
3010 let ExeDomain = SSEPackedSingle in {
3011 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", VR512, f512mem,
3012 memopv16f32, f32mem, loadf32, "{1to16}",
3013 X86Fmadd, v16f32>, EVEX_V512,
3014 EVEX_CD8<32, CD8VF>;
3015 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", VR512, f512mem,
3016 memopv16f32, f32mem, loadf32, "{1to16}",
3017 X86Fmsub, v16f32>, EVEX_V512,
3018 EVEX_CD8<32, CD8VF>;
3019 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", VR512, f512mem,
3020 memopv16f32, f32mem, loadf32, "{1to16}",
3021 X86Fmaddsub, v16f32>,
3022 EVEX_V512, EVEX_CD8<32, CD8VF>;
3023 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", VR512, f512mem,
3024 memopv16f32, f32mem, loadf32, "{1to16}",
3025 X86Fmsubadd, v16f32>,
3026 EVEX_V512, EVEX_CD8<32, CD8VF>;
3027 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", VR512, f512mem,
3028 memopv16f32, f32mem, loadf32, "{1to16}",
3029 X86Fnmadd, v16f32>, EVEX_V512,
3030 EVEX_CD8<32, CD8VF>;
3031 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", VR512, f512mem,
3032 memopv16f32, f32mem, loadf32, "{1to16}",
3033 X86Fnmsub, v16f32>, EVEX_V512,
3034 EVEX_CD8<32, CD8VF>;
3035 }
3036 let ExeDomain = SSEPackedDouble in {
3037 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", VR512, f512mem,
3038 memopv8f64, f64mem, loadf64, "{1to8}",
3039 X86Fmadd, v8f64>, EVEX_V512,
3040 VEX_W, EVEX_CD8<64, CD8VF>;
3041 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", VR512, f512mem,
3042 memopv8f64, f64mem, loadf64, "{1to8}",
3043 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
3044 EVEX_CD8<64, CD8VF>;
3045 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", VR512, f512mem,
3046 memopv8f64, f64mem, loadf64, "{1to8}",
3047 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
3048 EVEX_CD8<64, CD8VF>;
3049 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", VR512, f512mem,
3050 memopv8f64, f64mem, loadf64, "{1to8}",
3051 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
3052 EVEX_CD8<64, CD8VF>;
3053 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", VR512, f512mem,
3054 memopv8f64, f64mem, loadf64, "{1to8}",
3055 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
3056 EVEX_CD8<64, CD8VF>;
3057 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", VR512, f512mem,
3058 memopv8f64, f64mem, loadf64, "{1to8}",
3059 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
3060 EVEX_CD8<64, CD8VF>;
3061 }
3063 // Scalar FMA
3064 let Constraints = "$src1 = $dst" in {
3065 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3066 RegisterClass RC, ValueType OpVT,
3067 X86MemOperand x86memop, Operand memop,
3068 PatFrag mem_frag> {
3069 let isCommutable = 1 in
3070 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
3071 (ins RC:$src1, RC:$src2, RC:$src3),
3072 !strconcat(OpcodeStr,
3073 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3074 [(set RC:$dst,
3075 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
3076 let mayLoad = 1 in
3077 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
3078 (ins RC:$src1, RC:$src2, f128mem:$src3),
3079 !strconcat(OpcodeStr,
3080 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3081 [(set RC:$dst,
3082 (OpVT (OpNode RC:$src2, RC:$src1,
3083 (mem_frag addr:$src3))))]>;
3084 }
3086 } // Constraints = "$src1 = $dst"
3088 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
3089 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3090 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
3091 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3092 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
3093 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3094 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
3095 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3096 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
3097 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3098 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
3099 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3100 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
3101 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3102 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
3103 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3105 //===----------------------------------------------------------------------===//
3106 // AVX-512 Scalar convert from sign integer to float/double
3107 //===----------------------------------------------------------------------===//
3109 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3110 X86MemOperand x86memop, string asm> {
3111 let hasSideEffects = 0 in {
3112 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
3113 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3114 EVEX_4V;
3115 let mayLoad = 1 in
3116 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
3117 (ins DstRC:$src1, x86memop:$src),
3118 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3119 EVEX_4V;
3120 } // hasSideEffects = 0
3121 }
3122 let Predicates = [HasAVX512] in {
3123 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
3124 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3125 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
3126 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3127 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
3128 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3129 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
3130 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3132 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
3133 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3134 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
3135 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3136 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
3137 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3138 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
3139 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3141 def : Pat<(f32 (sint_to_fp GR32:$src)),
3142 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3143 def : Pat<(f32 (sint_to_fp GR64:$src)),
3144 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3145 def : Pat<(f64 (sint_to_fp GR32:$src)),
3146 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3147 def : Pat<(f64 (sint_to_fp GR64:$src)),
3148 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3150 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
3151 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3152 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
3153 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3154 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
3155 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3156 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
3157 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3159 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
3160 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3161 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
3162 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3163 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
3164 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3165 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
3166 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3168 def : Pat<(f32 (uint_to_fp GR32:$src)),
3169 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3170 def : Pat<(f32 (uint_to_fp GR64:$src)),
3171 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3172 def : Pat<(f64 (uint_to_fp GR32:$src)),
3173 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3174 def : Pat<(f64 (uint_to_fp GR64:$src)),
3175 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3176 }
3178 //===----------------------------------------------------------------------===//
3179 // AVX-512 Scalar convert from float/double to integer
3180 //===----------------------------------------------------------------------===//
3181 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3182 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
3183 string asm> {
3184 let hasSideEffects = 0 in {
3185 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3186 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3187 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
3188 Requires<[HasAVX512]>;
3189 let mayLoad = 1 in
3190 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
3191 !strconcat(asm," \t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
3192 Requires<[HasAVX512]>;
3193 } // hasSideEffects = 0
3194 }
3195 let Predicates = [HasAVX512] in {
3196 // Convert float/double to signed/unsigned int 32/64
3197 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
3198 ssmem, sse_load_f32, "cvtss2si">,
3199 XS, EVEX_CD8<32, CD8VT1>;
3200 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
3201 ssmem, sse_load_f32, "cvtss2si">,
3202 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
3203 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
3204 ssmem, sse_load_f32, "cvtss2usi">,
3205 XS, EVEX_CD8<32, CD8VT1>;
3206 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3207 int_x86_avx512_cvtss2usi64, ssmem,
3208 sse_load_f32, "cvtss2usi">, XS, VEX_W,
3209 EVEX_CD8<32, CD8VT1>;
3210 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
3211 sdmem, sse_load_f64, "cvtsd2si">,
3212 XD, EVEX_CD8<64, CD8VT1>;
3213 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
3214 sdmem, sse_load_f64, "cvtsd2si">,
3215 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
3216 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
3217 sdmem, sse_load_f64, "cvtsd2usi">,
3218 XD, EVEX_CD8<64, CD8VT1>;
3219 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3220 int_x86_avx512_cvtsd2usi64, sdmem,
3221 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
3222 EVEX_CD8<64, CD8VT1>;
3224 let isCodeGenOnly = 1 in {
3225 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3226 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
3227 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3228 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3229 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
3230 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3231 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3232 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
3233 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3234 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3235 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
3236 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3238 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3239 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
3240 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3241 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3242 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
3243 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3244 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3245 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
3246 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3247 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3248 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
3249 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3250 } // isCodeGenOnly = 1
3252 // Convert float/double to signed/unsigned int 32/64 with truncation
3253 let isCodeGenOnly = 1 in {
3254 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
3255 ssmem, sse_load_f32, "cvttss2si">,
3256 XS, EVEX_CD8<32, CD8VT1>;
3257 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3258 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
3259 "cvttss2si">, XS, VEX_W,
3260 EVEX_CD8<32, CD8VT1>;
3261 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
3262 sdmem, sse_load_f64, "cvttsd2si">, XD,
3263 EVEX_CD8<64, CD8VT1>;
3264 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3265 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
3266 "cvttsd2si">, XD, VEX_W,
3267 EVEX_CD8<64, CD8VT1>;
3268 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3269 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
3270 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
3271 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3272 int_x86_avx512_cvttss2usi64, ssmem,
3273 sse_load_f32, "cvttss2usi">, XS, VEX_W,
3274 EVEX_CD8<32, CD8VT1>;
3275 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3276 int_x86_avx512_cvttsd2usi,
3277 sdmem, sse_load_f64, "cvttsd2usi">, XD,
3278 EVEX_CD8<64, CD8VT1>;
3279 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3280 int_x86_avx512_cvttsd2usi64, sdmem,
3281 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
3282 EVEX_CD8<64, CD8VT1>;
3283 } // isCodeGenOnly = 1
3285 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3286 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
3287 string asm> {
3288 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3289 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3290 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
3291 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3292 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3293 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
3294 }
3296 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
3297 loadf32, "cvttss2si">, XS,
3298 EVEX_CD8<32, CD8VT1>;
3299 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
3300 loadf32, "cvttss2usi">, XS,
3301 EVEX_CD8<32, CD8VT1>;
3302 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
3303 loadf32, "cvttss2si">, XS, VEX_W,
3304 EVEX_CD8<32, CD8VT1>;
3305 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
3306 loadf32, "cvttss2usi">, XS, VEX_W,
3307 EVEX_CD8<32, CD8VT1>;
3308 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
3309 loadf64, "cvttsd2si">, XD,
3310 EVEX_CD8<64, CD8VT1>;
3311 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
3312 loadf64, "cvttsd2usi">, XD,
3313 EVEX_CD8<64, CD8VT1>;
3314 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
3315 loadf64, "cvttsd2si">, XD, VEX_W,
3316 EVEX_CD8<64, CD8VT1>;
3317 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
3318 loadf64, "cvttsd2usi">, XD, VEX_W,
3319 EVEX_CD8<64, CD8VT1>;
3320 } // HasAVX512
3321 //===----------------------------------------------------------------------===//
3322 // AVX-512 Convert form float to double and back
3323 //===----------------------------------------------------------------------===//
3324 let hasSideEffects = 0 in {
3325 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
3326 (ins FR32X:$src1, FR32X:$src2),
3327 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3328 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
3329 let mayLoad = 1 in
3330 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
3331 (ins FR32X:$src1, f32mem:$src2),
3332 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3333 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
3334 EVEX_CD8<32, CD8VT1>;
3336 // Convert scalar double to scalar single
3337 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
3338 (ins FR64X:$src1, FR64X:$src2),
3339 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3340 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
3341 let mayLoad = 1 in
3342 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
3343 (ins FR64X:$src1, f64mem:$src2),
3344 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3345 []>, EVEX_4V, VEX_LIG, VEX_W,
3346 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
3347 }
3349 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
3350 Requires<[HasAVX512]>;
3351 def : Pat<(fextend (loadf32 addr:$src)),
3352 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
3354 def : Pat<(extloadf32 addr:$src),
3355 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3356 Requires<[HasAVX512, OptForSize]>;
3358 def : Pat<(extloadf32 addr:$src),
3359 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
3360 Requires<[HasAVX512, OptForSpeed]>;
3362 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
3363 Requires<[HasAVX512]>;
3365 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
3366 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3367 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3368 Domain d> {
3369 let hasSideEffects = 0 in {
3370 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3371 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3372 [(set DstRC:$dst,
3373 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3374 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3375 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
3376 [], d>, EVEX, EVEX_B, EVEX_RC;
3377 let mayLoad = 1 in
3378 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3379 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3380 [(set DstRC:$dst,
3381 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3382 } // hasSideEffects = 0
3383 }
3385 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
3386 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3387 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3388 Domain d> {
3389 let hasSideEffects = 0 in {
3390 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3391 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3392 [(set DstRC:$dst,
3393 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3394 let mayLoad = 1 in
3395 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3396 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3397 [(set DstRC:$dst,
3398 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3399 } // hasSideEffects = 0
3400 }
3402 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
3403 memopv8f64, f512mem, v8f32, v8f64,
3404 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
3405 EVEX_CD8<64, CD8VF>;
3407 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
3408 memopv4f64, f256mem, v8f64, v8f32,
3409 SSEPackedDouble>, EVEX_V512, PS,
3410 EVEX_CD8<32, CD8VH>;
3411 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3412 (VCVTPS2PDZrm addr:$src)>;
3414 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3415 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
3416 (VCVTPD2PSZrr VR512:$src)>;
3418 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3419 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
3420 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
3422 //===----------------------------------------------------------------------===//
3423 // AVX-512 Vector convert from sign integer to float/double
3424 //===----------------------------------------------------------------------===//
3426 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
3427 memopv8i64, i512mem, v16f32, v16i32,
3428 SSEPackedSingle>, EVEX_V512, PS,
3429 EVEX_CD8<32, CD8VF>;
3431 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
3432 memopv4i64, i256mem, v8f64, v8i32,
3433 SSEPackedDouble>, EVEX_V512, XS,
3434 EVEX_CD8<32, CD8VH>;
3436 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
3437 memopv16f32, f512mem, v16i32, v16f32,
3438 SSEPackedSingle>, EVEX_V512, XS,
3439 EVEX_CD8<32, CD8VF>;
3441 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
3442 memopv8f64, f512mem, v8i32, v8f64,
3443 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
3444 EVEX_CD8<64, CD8VF>;
3446 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
3447 memopv16f32, f512mem, v16i32, v16f32,
3448 SSEPackedSingle>, EVEX_V512, PS,
3449 EVEX_CD8<32, CD8VF>;
3451 // cvttps2udq (src, 0, mask-all-ones, sae-current)
3452 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
3453 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
3454 (VCVTTPS2UDQZrr VR512:$src)>;
3456 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
3457 memopv8f64, f512mem, v8i32, v8f64,
3458 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
3459 EVEX_CD8<64, CD8VF>;
3461 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
3462 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
3463 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
3464 (VCVTTPD2UDQZrr VR512:$src)>;
3466 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
3467 memopv4i64, f256mem, v8f64, v8i32,
3468 SSEPackedDouble>, EVEX_V512, XS,
3469 EVEX_CD8<32, CD8VH>;
3471 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
3472 memopv16i32, f512mem, v16f32, v16i32,
3473 SSEPackedSingle>, EVEX_V512, XD,
3474 EVEX_CD8<32, CD8VF>;
3476 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
3477 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3478 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3480 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
3481 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3482 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3484 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
3485 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3486 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3488 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
3489 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3490 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3492 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
3493 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
3494 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
3496 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
3497 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3498 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
3499 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
3500 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3501 (VCVTDQ2PDZrr VR256X:$src)>;
3502 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
3503 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3504 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
3505 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
3506 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3507 (VCVTUDQ2PDZrr VR256X:$src)>;
3509 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
3510 RegisterClass DstRC, PatFrag mem_frag,
3511 X86MemOperand x86memop, Domain d> {
3512 let hasSideEffects = 0 in {
3513 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3514 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3515 [], d>, EVEX;
3516 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3517 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
3518 [], d>, EVEX, EVEX_B, EVEX_RC;
3519 let mayLoad = 1 in
3520 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3521 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3522 [], d>, EVEX;
3523 } // hasSideEffects = 0
3524 }
3526 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
3527 memopv16f32, f512mem, SSEPackedSingle>, PD,
3528 EVEX_V512, EVEX_CD8<32, CD8VF>;
3529 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
3530 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
3531 EVEX_V512, EVEX_CD8<64, CD8VF>;
3533 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
3534 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3535 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
3537 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
3538 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3539 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
3541 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
3542 memopv16f32, f512mem, SSEPackedSingle>,
3543 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3544 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
3545 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
3546 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
3548 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
3549 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3550 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
3552 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
3553 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3554 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
3556 let Predicates = [HasAVX512] in {
3557 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
3558 (VCVTPD2PSZrm addr:$src)>;
3559 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3560 (VCVTPS2PDZrm addr:$src)>;
3561 }
3563 //===----------------------------------------------------------------------===//
3564 // Half precision conversion instructions
3565 //===----------------------------------------------------------------------===//
3566 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
3567 X86MemOperand x86memop> {
3568 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
3569 "vcvtph2ps\t{$src, $dst|$dst, $src}",
3570 []>, EVEX;
3571 let hasSideEffects = 0, mayLoad = 1 in
3572 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
3573 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
3574 }
3576 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
3577 X86MemOperand x86memop> {
3578 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
3579 (ins srcRC:$src1, i32i8imm:$src2),
3580 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}",
3581 []>, EVEX;
3582 let hasSideEffects = 0, mayStore = 1 in
3583 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
3584 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
3585 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
3586 }
3588 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
3589 EVEX_CD8<32, CD8VH>;
3590 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
3591 EVEX_CD8<32, CD8VH>;
3593 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
3594 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
3595 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
3597 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
3598 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
3599 (VCVTPH2PSZrr VR256X:$src)>;
3601 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
3602 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
3603 "ucomiss">, PS, EVEX, VEX_LIG,
3604 EVEX_CD8<32, CD8VT1>;
3605 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
3606 "ucomisd">, PD, EVEX,
3607 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3608 let Pattern = []<dag> in {
3609 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
3610 "comiss">, PS, EVEX, VEX_LIG,
3611 EVEX_CD8<32, CD8VT1>;
3612 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
3613 "comisd">, PD, EVEX,
3614 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3615 }
3616 let isCodeGenOnly = 1 in {
3617 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
3618 load, "ucomiss">, PS, EVEX, VEX_LIG,
3619 EVEX_CD8<32, CD8VT1>;
3620 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
3621 load, "ucomisd">, PD, EVEX,
3622 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3624 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
3625 load, "comiss">, PS, EVEX, VEX_LIG,
3626 EVEX_CD8<32, CD8VT1>;
3627 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
3628 load, "comisd">, PD, EVEX,
3629 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3630 }
3631 }
3633 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
3634 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3635 X86MemOperand x86memop> {
3636 let hasSideEffects = 0 in {
3637 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3638 (ins RC:$src1, RC:$src2),
3639 !strconcat(OpcodeStr,
3640 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3641 let mayLoad = 1 in {
3642 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3643 (ins RC:$src1, x86memop:$src2),
3644 !strconcat(OpcodeStr,
3645 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3646 }
3647 }
3648 }
3650 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
3651 EVEX_CD8<32, CD8VT1>;
3652 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
3653 VEX_W, EVEX_CD8<64, CD8VT1>;
3654 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
3655 EVEX_CD8<32, CD8VT1>;
3656 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
3657 VEX_W, EVEX_CD8<64, CD8VT1>;
3659 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
3660 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3661 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3662 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3664 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
3665 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3666 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3667 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3669 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
3670 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3671 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3672 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3674 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
3675 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3676 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3677 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3679 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
3680 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3681 RegisterClass RC, X86MemOperand x86memop,
3682 PatFrag mem_frag, ValueType OpVt> {
3683 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3684 !strconcat(OpcodeStr,
3685 " \t{$src, $dst|$dst, $src}"),
3686 [(set RC:$dst, (OpVt (OpNode RC:$src)))]>,
3687 EVEX;
3688 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3689 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3690 [(set RC:$dst, (OpVt (OpNode (mem_frag addr:$src))))]>,
3691 EVEX;
3692 }
3693 defm VRSQRT14PSZ : avx512_fp14_p<0x4E, "vrsqrt14ps", X86frsqrt, VR512, f512mem,
3694 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3695 defm VRSQRT14PDZ : avx512_fp14_p<0x4E, "vrsqrt14pd", X86frsqrt, VR512, f512mem,
3696 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3697 defm VRCP14PSZ : avx512_fp14_p<0x4C, "vrcp14ps", X86frcp, VR512, f512mem,
3698 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3699 defm VRCP14PDZ : avx512_fp14_p<0x4C, "vrcp14pd", X86frcp, VR512, f512mem,
3700 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3702 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
3703 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3704 (VRSQRT14PSZr VR512:$src)>;
3705 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
3706 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3707 (VRSQRT14PDZr VR512:$src)>;
3709 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
3710 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3711 (VRCP14PSZr VR512:$src)>;
3712 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
3713 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3714 (VRCP14PDZr VR512:$src)>;
3716 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
3717 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3718 X86MemOperand x86memop> {
3719 let hasSideEffects = 0, Predicates = [HasERI] in {
3720 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3721 (ins RC:$src1, RC:$src2),
3722 !strconcat(OpcodeStr,
3723 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3724 def rrb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3725 (ins RC:$src1, RC:$src2),
3726 !strconcat(OpcodeStr,
3727 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
3728 []>, EVEX_4V, EVEX_B;
3729 let mayLoad = 1 in {
3730 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3731 (ins RC:$src1, x86memop:$src2),
3732 !strconcat(OpcodeStr,
3733 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3734 }
3735 }
3736 }
3738 defm VRCP28SS : avx512_fp28_s<0xCB, "vrcp28ss", FR32X, f32mem>,
3739 EVEX_CD8<32, CD8VT1>;
3740 defm VRCP28SD : avx512_fp28_s<0xCB, "vrcp28sd", FR64X, f64mem>,
3741 VEX_W, EVEX_CD8<64, CD8VT1>;
3742 defm VRSQRT28SS : avx512_fp28_s<0xCD, "vrsqrt28ss", FR32X, f32mem>,
3743 EVEX_CD8<32, CD8VT1>;
3744 defm VRSQRT28SD : avx512_fp28_s<0xCD, "vrsqrt28sd", FR64X, f64mem>,
3745 VEX_W, EVEX_CD8<64, CD8VT1>;
3747 def : Pat <(v4f32 (int_x86_avx512_rcp28_ss (v4f32 VR128X:$src1),
3748 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3749 FROUND_NO_EXC)),
3750 (COPY_TO_REGCLASS (VRCP28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3751 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3753 def : Pat <(v2f64 (int_x86_avx512_rcp28_sd (v2f64 VR128X:$src1),
3754 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
3755 FROUND_NO_EXC)),
3756 (COPY_TO_REGCLASS (VRCP28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3757 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3759 def : Pat <(v4f32 (int_x86_avx512_rsqrt28_ss (v4f32 VR128X:$src1),
3760 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3761 FROUND_NO_EXC)),
3762 (COPY_TO_REGCLASS (VRSQRT28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3763 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3765 def : Pat <(v2f64 (int_x86_avx512_rsqrt28_sd (v2f64 VR128X:$src1),
3766 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
3767 FROUND_NO_EXC)),
3768 (COPY_TO_REGCLASS (VRSQRT28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3769 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3771 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
3772 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr,
3773 RegisterClass RC, X86MemOperand x86memop> {
3774 let hasSideEffects = 0, Predicates = [HasERI] in {
3775 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3776 !strconcat(OpcodeStr,
3777 " \t{$src, $dst|$dst, $src}"),
3778 []>, EVEX;
3779 def rb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3780 !strconcat(OpcodeStr,
3781 " \t{{sae}, $src, $dst|$dst, $src, {sae}}"),
3782 []>, EVEX, EVEX_B;
3783 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3784 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3785 []>, EVEX;
3786 }
3787 }
3788 defm VRSQRT28PSZ : avx512_fp28_p<0xCC, "vrsqrt28ps", VR512, f512mem>,
3789 EVEX_V512, EVEX_CD8<32, CD8VF>;
3790 defm VRSQRT28PDZ : avx512_fp28_p<0xCC, "vrsqrt28pd", VR512, f512mem>,
3791 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3792 defm VRCP28PSZ : avx512_fp28_p<0xCA, "vrcp28ps", VR512, f512mem>,
3793 EVEX_V512, EVEX_CD8<32, CD8VF>;
3794 defm VRCP28PDZ : avx512_fp28_p<0xCA, "vrcp28pd", VR512, f512mem>,
3795 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3797 def : Pat <(v16f32 (int_x86_avx512_rsqrt28_ps (v16f32 VR512:$src),
3798 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
3799 (VRSQRT28PSZrb VR512:$src)>;
3800 def : Pat <(v8f64 (int_x86_avx512_rsqrt28_pd (v8f64 VR512:$src),
3801 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
3802 (VRSQRT28PDZrb VR512:$src)>;
3804 def : Pat <(v16f32 (int_x86_avx512_rcp28_ps (v16f32 VR512:$src),
3805 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
3806 (VRCP28PSZrb VR512:$src)>;
3807 def : Pat <(v8f64 (int_x86_avx512_rcp28_pd (v8f64 VR512:$src),
3808 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
3809 (VRCP28PDZrb VR512:$src)>;
3811 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3812 OpndItins itins_s, OpndItins itins_d> {
3813 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3814 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3815 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
3816 EVEX, EVEX_V512;
3818 let mayLoad = 1 in
3819 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3820 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3821 [(set VR512:$dst,
3822 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
3823 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
3825 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3826 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3827 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
3828 EVEX, EVEX_V512;
3830 let mayLoad = 1 in
3831 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3832 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3833 [(set VR512:$dst, (OpNode
3834 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
3835 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
3837 }
3839 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
3840 Intrinsic F32Int, Intrinsic F64Int,
3841 OpndItins itins_s, OpndItins itins_d> {
3842 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
3843 (ins FR32X:$src1, FR32X:$src2),
3844 !strconcat(OpcodeStr,
3845 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3846 [], itins_s.rr>, XS, EVEX_4V;
3847 let isCodeGenOnly = 1 in
3848 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3849 (ins VR128X:$src1, VR128X:$src2),
3850 !strconcat(OpcodeStr,
3851 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3852 [(set VR128X:$dst,
3853 (F32Int VR128X:$src1, VR128X:$src2))],
3854 itins_s.rr>, XS, EVEX_4V;
3855 let mayLoad = 1 in {
3856 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
3857 (ins FR32X:$src1, f32mem:$src2),
3858 !strconcat(OpcodeStr,
3859 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3860 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3861 let isCodeGenOnly = 1 in
3862 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3863 (ins VR128X:$src1, ssmem:$src2),
3864 !strconcat(OpcodeStr,
3865 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3866 [(set VR128X:$dst,
3867 (F32Int VR128X:$src1, sse_load_f32:$src2))],
3868 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3869 }
3870 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
3871 (ins FR64X:$src1, FR64X:$src2),
3872 !strconcat(OpcodeStr,
3873 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3874 XD, EVEX_4V, VEX_W;
3875 let isCodeGenOnly = 1 in
3876 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3877 (ins VR128X:$src1, VR128X:$src2),
3878 !strconcat(OpcodeStr,
3879 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3880 [(set VR128X:$dst,
3881 (F64Int VR128X:$src1, VR128X:$src2))],
3882 itins_s.rr>, XD, EVEX_4V, VEX_W;
3883 let mayLoad = 1 in {
3884 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
3885 (ins FR64X:$src1, f64mem:$src2),
3886 !strconcat(OpcodeStr,
3887 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3888 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3889 let isCodeGenOnly = 1 in
3890 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3891 (ins VR128X:$src1, sdmem:$src2),
3892 !strconcat(OpcodeStr,
3893 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3894 [(set VR128X:$dst,
3895 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
3896 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3897 }
3898 }
3901 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
3902 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
3903 SSE_SQRTSS, SSE_SQRTSD>,
3904 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
3905 SSE_SQRTPS, SSE_SQRTPD>;
3907 let Predicates = [HasAVX512] in {
3908 def : Pat<(v16f32 (int_x86_avx512_sqrt_ps_512 (v16f32 VR512:$src1),
3909 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_CURRENT)),
3910 (VSQRTPSZrr VR512:$src1)>;
3911 def : Pat<(v8f64 (int_x86_avx512_sqrt_pd_512 (v8f64 VR512:$src1),
3912 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_CURRENT)),
3913 (VSQRTPDZrr VR512:$src1)>;
3915 def : Pat<(f32 (fsqrt FR32X:$src)),
3916 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3917 def : Pat<(f32 (fsqrt (load addr:$src))),
3918 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3919 Requires<[OptForSize]>;
3920 def : Pat<(f64 (fsqrt FR64X:$src)),
3921 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
3922 def : Pat<(f64 (fsqrt (load addr:$src))),
3923 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
3924 Requires<[OptForSize]>;
3926 def : Pat<(f32 (X86frsqrt FR32X:$src)),
3927 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3928 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3929 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3930 Requires<[OptForSize]>;
3932 def : Pat<(f32 (X86frcp FR32X:$src)),
3933 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3934 def : Pat<(f32 (X86frcp (load addr:$src))),
3935 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3936 Requires<[OptForSize]>;
3938 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
3939 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
3940 (COPY_TO_REGCLASS VR128X:$src, FR32)),
3941 VR128X)>;
3942 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3943 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3945 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
3946 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
3947 (COPY_TO_REGCLASS VR128X:$src, FR64)),
3948 VR128X)>;
3949 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3950 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3951 }
3954 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
3955 X86MemOperand x86memop, RegisterClass RC,
3956 PatFrag mem_frag32, PatFrag mem_frag64,
3957 Intrinsic V4F32Int, Intrinsic V2F64Int,
3958 CD8VForm VForm> {
3959 let ExeDomain = SSEPackedSingle in {
3960 // Intrinsic operation, reg.
3961 // Vector intrinsic operation, reg
3962 def PSr : AVX512AIi8<opcps, MRMSrcReg,
3963 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3964 !strconcat(OpcodeStr,
3965 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3966 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
3968 // Vector intrinsic operation, mem
3969 def PSm : AVX512AIi8<opcps, MRMSrcMem,
3970 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3971 !strconcat(OpcodeStr,
3972 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3973 [(set RC:$dst,
3974 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
3975 EVEX_CD8<32, VForm>;
3976 } // ExeDomain = SSEPackedSingle
3978 let ExeDomain = SSEPackedDouble in {
3979 // Vector intrinsic operation, reg
3980 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
3981 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3982 !strconcat(OpcodeStr,
3983 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3984 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
3986 // Vector intrinsic operation, mem
3987 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
3988 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3989 !strconcat(OpcodeStr,
3990 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3991 [(set RC:$dst,
3992 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
3993 EVEX_CD8<64, VForm>;
3994 } // ExeDomain = SSEPackedDouble
3995 }
3997 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3998 string OpcodeStr,
3999 Intrinsic F32Int,
4000 Intrinsic F64Int> {
4001 let ExeDomain = GenericDomain in {
4002 // Operation, reg.
4003 let hasSideEffects = 0 in
4004 def SSr : AVX512AIi8<opcss, MRMSrcReg,
4005 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
4006 !strconcat(OpcodeStr,
4007 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4008 []>;
4010 // Intrinsic operation, reg.
4011 let isCodeGenOnly = 1 in
4012 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
4013 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4014 !strconcat(OpcodeStr,
4015 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4016 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
4018 // Intrinsic operation, mem.
4019 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
4020 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
4021 !strconcat(OpcodeStr,
4022 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4023 [(set VR128X:$dst, (F32Int VR128X:$src1,
4024 sse_load_f32:$src2, imm:$src3))]>,
4025 EVEX_CD8<32, CD8VT1>;
4027 // Operation, reg.
4028 let hasSideEffects = 0 in
4029 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
4030 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
4031 !strconcat(OpcodeStr,
4032 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4033 []>, VEX_W;
4035 // Intrinsic operation, reg.
4036 let isCodeGenOnly = 1 in
4037 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
4038 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4039 !strconcat(OpcodeStr,
4040 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4041 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
4042 VEX_W;
4044 // Intrinsic operation, mem.
4045 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
4046 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
4047 !strconcat(OpcodeStr,
4048 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4049 [(set VR128X:$dst,
4050 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
4051 VEX_W, EVEX_CD8<64, CD8VT1>;
4052 } // ExeDomain = GenericDomain
4053 }
4055 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
4056 X86MemOperand x86memop, RegisterClass RC,
4057 PatFrag mem_frag, Domain d> {
4058 let ExeDomain = d in {
4059 // Intrinsic operation, reg.
4060 // Vector intrinsic operation, reg
4061 def r : AVX512AIi8<opc, MRMSrcReg,
4062 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4063 !strconcat(OpcodeStr,
4064 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4065 []>, EVEX;
4067 // Vector intrinsic operation, mem
4068 def m : AVX512AIi8<opc, MRMSrcMem,
4069 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4070 !strconcat(OpcodeStr,
4071 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4072 []>, EVEX;
4073 } // ExeDomain
4074 }
4077 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
4078 memopv16f32, SSEPackedSingle>, EVEX_V512,
4079 EVEX_CD8<32, CD8VF>;
4081 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
4082 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
4083 FROUND_CURRENT)),
4084 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
4087 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
4088 memopv8f64, SSEPackedDouble>, EVEX_V512,
4089 VEX_W, EVEX_CD8<64, CD8VF>;
4091 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
4092 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
4093 FROUND_CURRENT)),
4094 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
4096 multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
4097 Operand x86memop, RegisterClass RC, Domain d> {
4098 let ExeDomain = d in {
4099 def r : AVX512AIi8<opc, MRMSrcReg,
4100 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
4101 !strconcat(OpcodeStr,
4102 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4103 []>, EVEX_4V;
4105 def m : AVX512AIi8<opc, MRMSrcMem,
4106 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
4107 !strconcat(OpcodeStr,
4108 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4109 []>, EVEX_4V;
4110 } // ExeDomain
4111 }
4113 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
4114 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
4116 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
4117 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
4119 def : Pat<(ffloor FR32X:$src),
4120 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
4121 def : Pat<(f64 (ffloor FR64X:$src)),
4122 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
4123 def : Pat<(f32 (fnearbyint FR32X:$src)),
4124 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
4125 def : Pat<(f64 (fnearbyint FR64X:$src)),
4126 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
4127 def : Pat<(f32 (fceil FR32X:$src)),
4128 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
4129 def : Pat<(f64 (fceil FR64X:$src)),
4130 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
4131 def : Pat<(f32 (frint FR32X:$src)),
4132 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
4133 def : Pat<(f64 (frint FR64X:$src)),
4134 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
4135 def : Pat<(f32 (ftrunc FR32X:$src)),
4136 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
4137 def : Pat<(f64 (ftrunc FR64X:$src)),
4138 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
4140 def : Pat<(v16f32 (ffloor VR512:$src)),
4141 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
4142 def : Pat<(v16f32 (fnearbyint VR512:$src)),
4143 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
4144 def : Pat<(v16f32 (fceil VR512:$src)),
4145 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
4146 def : Pat<(v16f32 (frint VR512:$src)),
4147 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
4148 def : Pat<(v16f32 (ftrunc VR512:$src)),
4149 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
4151 def : Pat<(v8f64 (ffloor VR512:$src)),
4152 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
4153 def : Pat<(v8f64 (fnearbyint VR512:$src)),
4154 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
4155 def : Pat<(v8f64 (fceil VR512:$src)),
4156 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
4157 def : Pat<(v8f64 (frint VR512:$src)),
4158 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
4159 def : Pat<(v8f64 (ftrunc VR512:$src)),
4160 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
4162 //-------------------------------------------------
4163 // Integer truncate and extend operations
4164 //-------------------------------------------------
4166 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
4167 RegisterClass dstRC, RegisterClass srcRC,
4168 RegisterClass KRC, X86MemOperand x86memop> {
4169 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4170 (ins srcRC:$src),
4171 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
4172 []>, EVEX;
4174 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4175 (ins KRC:$mask, srcRC:$src),
4176 !strconcat(OpcodeStr,
4177 " \t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
4178 []>, EVEX, EVEX_K;
4180 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4181 (ins KRC:$mask, srcRC:$src),
4182 !strconcat(OpcodeStr,
4183 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4184 []>, EVEX, EVEX_KZ;
4186 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
4187 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4188 []>, EVEX;
4190 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
4191 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
4192 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
4193 []>, EVEX, EVEX_K;
4195 }
4196 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
4197 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4198 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
4199 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4200 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
4201 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4202 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
4203 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4204 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
4205 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4206 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
4207 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4208 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
4209 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4210 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
4211 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4212 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
4213 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4214 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
4215 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4216 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
4217 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4218 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
4219 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4220 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
4221 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4222 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
4223 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4224 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
4225 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4227 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
4228 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
4229 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
4230 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
4231 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
4233 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4234 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
4235 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4236 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
4237 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4238 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
4239 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4240 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
4243 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4244 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode,
4245 PatFrag mem_frag, X86MemOperand x86memop,
4246 ValueType OpVT, ValueType InVT> {
4248 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4249 (ins SrcRC:$src),
4250 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4251 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
4253 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4254 (ins KRC:$mask, SrcRC:$src),
4255 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4256 []>, EVEX, EVEX_K;
4258 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4259 (ins KRC:$mask, SrcRC:$src),
4260 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4261 []>, EVEX, EVEX_KZ;
4263 let mayLoad = 1 in {
4264 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4265 (ins x86memop:$src),
4266 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
4267 [(set DstRC:$dst,
4268 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
4269 EVEX;
4271 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4272 (ins KRC:$mask, x86memop:$src),
4273 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4274 []>,
4275 EVEX, EVEX_K;
4277 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4278 (ins KRC:$mask, x86memop:$src),
4279 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4280 []>,
4281 EVEX, EVEX_KZ;
4282 }
4283 }
4285 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext,
4286 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4287 EVEX_CD8<8, CD8VQ>;
4288 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext,
4289 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4290 EVEX_CD8<8, CD8VO>;
4291 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext,
4292 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4293 EVEX_CD8<16, CD8VH>;
4294 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext,
4295 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4296 EVEX_CD8<16, CD8VQ>;
4297 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext,
4298 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4299 EVEX_CD8<32, CD8VH>;
4301 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext,
4302 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4303 EVEX_CD8<8, CD8VQ>;
4304 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext,
4305 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4306 EVEX_CD8<8, CD8VO>;
4307 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext,
4308 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4309 EVEX_CD8<16, CD8VH>;
4310 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext,
4311 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4312 EVEX_CD8<16, CD8VQ>;
4313 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext,
4314 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4315 EVEX_CD8<32, CD8VH>;
4317 //===----------------------------------------------------------------------===//
4318 // GATHER - SCATTER Operations
4320 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4321 RegisterClass RC, X86MemOperand memop> {
4322 let mayLoad = 1,
4323 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
4324 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
4325 (ins RC:$src1, KRC:$mask, memop:$src2),
4326 !strconcat(OpcodeStr,
4327 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4328 []>, EVEX, EVEX_K;
4329 }
4331 let ExeDomain = SSEPackedDouble in {
4332 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
4333 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4334 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
4335 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4336 }
4338 let ExeDomain = SSEPackedSingle in {
4339 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
4340 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4341 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
4342 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4343 }
4345 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
4346 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4347 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
4348 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4350 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
4351 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4352 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
4353 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4355 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4356 RegisterClass RC, X86MemOperand memop> {
4357 let mayStore = 1, Constraints = "$mask = $mask_wb" in
4358 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
4359 (ins memop:$dst, KRC:$mask, RC:$src2),
4360 !strconcat(OpcodeStr,
4361 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4362 []>, EVEX, EVEX_K;
4363 }
4365 let ExeDomain = SSEPackedDouble in {
4366 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
4367 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4368 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
4369 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4370 }
4372 let ExeDomain = SSEPackedSingle in {
4373 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
4374 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4375 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
4376 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4377 }
4379 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
4380 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4381 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
4382 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4384 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
4385 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4386 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
4387 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4389 // prefetch
4390 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
4391 RegisterClass KRC, X86MemOperand memop> {
4392 let Predicates = [HasPFI], hasSideEffects = 1 in
4393 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
4394 !strconcat(OpcodeStr, " \t{$src {${mask}}|{${mask}}, $src}"),
4395 []>, EVEX, EVEX_K;
4396 }
4398 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
4399 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4401 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
4402 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4404 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
4405 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4407 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
4408 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4410 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
4411 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4413 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
4414 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4416 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
4417 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4419 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
4420 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4422 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
4423 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4425 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
4426 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4428 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
4429 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4431 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
4432 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4434 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
4435 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4437 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
4438 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4440 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
4441 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4443 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
4444 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4445 //===----------------------------------------------------------------------===//
4446 // VSHUFPS - VSHUFPD Operations
4448 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
4449 ValueType vt, string OpcodeStr, PatFrag mem_frag,
4450 Domain d> {
4451 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
4452 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4453 !strconcat(OpcodeStr,
4454 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4455 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
4456 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4457 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
4458 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
4459 (ins RC:$src1, RC:$src2, i8imm:$src3),
4460 !strconcat(OpcodeStr,
4461 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4462 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
4463 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4464 EVEX_4V, Sched<[WriteShuffle]>;
4465 }
4467 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
4468 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
4469 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
4470 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4472 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4473 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4474 def : Pat<(v16i32 (X86Shufp VR512:$src1,
4475 (memopv16i32 addr:$src2), (i8 imm:$imm))),
4476 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4478 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4479 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4480 def : Pat<(v8i64 (X86Shufp VR512:$src1,
4481 (memopv8i64 addr:$src2), (i8 imm:$imm))),
4482 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4484 multiclass avx512_valign<string Suffix, RegisterClass RC, RegisterClass KRC,
4485 RegisterClass MRC, X86MemOperand x86memop,
4486 ValueType IntVT, ValueType FloatVT> {
4487 defm rri : AVX512_masking<0x03, MRMSrcReg, (outs RC:$dst),
4488 (ins RC:$src1, RC:$src2, i8imm:$src3),
4489 "valign"##Suffix,
4490 "$src3, $src2, $src1", "$src1, $src2, $src3",
4491 (IntVT (X86VAlign RC:$src2, RC:$src1,
4492 (i8 imm:$src3))),
4493 RC, KRC>,
4494 AVX512AIi8Base, EVEX_4V;
4496 // Also match valign of packed floats.
4497 def : Pat<(FloatVT (X86VAlign RC:$src1, RC:$src2, (i8 imm:$imm))),
4498 (!cast<Instruction>(NAME##rri) RC:$src2, RC:$src1, imm:$imm)>;
4500 // Non-masking intrinsic call.
4501 def : Pat<(IntVT
4502 (!cast<Intrinsic>("int_x86_avx512_mask_valign_"##Suffix##"_512")
4503 RC:$src1, RC:$src2, imm:$src3,
4504 (IntVT (bitconvert (v16i32 immAllZerosV))), -1)),
4505 (!cast<Instruction>(NAME#rri) RC:$src1, RC:$src2, imm:$src3)>;
4507 // Masking intrinsic call.
4508 def : Pat<(IntVT
4509 (!cast<Intrinsic>("int_x86_avx512_mask_valign_"##Suffix##"_512")
4510 RC:$src1, RC:$src2, imm:$src3,
4511 RC:$src4, MRC:$mask)),
4512 (!cast<Instruction>(NAME#rrik) RC:$src4,
4513 (COPY_TO_REGCLASS MRC:$mask, KRC), RC:$src1,
4514 RC:$src2, imm:$src3)>;
4516 let mayLoad = 1 in
4517 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs RC:$dst),
4518 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4519 !strconcat("valign"##Suffix,
4520 " \t{$src3, $src2, $src1, $dst|"
4521 "$dst, $src1, $src2, $src3}"),
4522 []>, EVEX_4V;
4523 }
4524 defm VALIGND : avx512_valign<"d", VR512, VK16WM, GR16, i512mem, v16i32, v16f32>,
4525 EVEX_V512, EVEX_CD8<32, CD8VF>;
4526 defm VALIGNQ : avx512_valign<"q", VR512, VK8WM, GR8, i512mem, v8i64, v8f64>,
4527 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4529 // Helper fragments to match sext vXi1 to vXiY.
4530 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
4531 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
4533 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
4534 RegisterClass KRC, RegisterClass RC,
4535 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
4536 string BrdcstStr> {
4537 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4538 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4539 []>, EVEX;
4540 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4541 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4542 []>, EVEX, EVEX_K;
4543 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4544 !strconcat(OpcodeStr,
4545 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4546 []>, EVEX, EVEX_KZ;
4547 let mayLoad = 1 in {
4548 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4549 (ins x86memop:$src),
4550 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4551 []>, EVEX;
4552 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4553 (ins KRC:$mask, x86memop:$src),
4554 !strconcat(OpcodeStr,
4555 " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4556 []>, EVEX, EVEX_K;
4557 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4558 (ins KRC:$mask, x86memop:$src),
4559 !strconcat(OpcodeStr,
4560 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4561 []>, EVEX, EVEX_KZ;
4562 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4563 (ins x86scalar_mop:$src),
4564 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4565 ", $dst|$dst, ${src}", BrdcstStr, "}"),
4566 []>, EVEX, EVEX_B;
4567 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4568 (ins KRC:$mask, x86scalar_mop:$src),
4569 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4570 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
4571 []>, EVEX, EVEX_B, EVEX_K;
4572 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4573 (ins KRC:$mask, x86scalar_mop:$src),
4574 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4575 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
4576 BrdcstStr, "}"),
4577 []>, EVEX, EVEX_B, EVEX_KZ;
4578 }
4579 }
4581 defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
4582 i512mem, i32mem, "{1to16}">, EVEX_V512,
4583 EVEX_CD8<32, CD8VF>;
4584 defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
4585 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
4586 EVEX_CD8<64, CD8VF>;
4588 def : Pat<(xor
4589 (bc_v16i32 (v16i1sextv16i32)),
4590 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
4591 (VPABSDZrr VR512:$src)>;
4592 def : Pat<(xor
4593 (bc_v8i64 (v8i1sextv8i64)),
4594 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
4595 (VPABSQZrr VR512:$src)>;
4597 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
4598 (v16i32 immAllZerosV), (i16 -1))),
4599 (VPABSDZrr VR512:$src)>;
4600 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
4601 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
4602 (VPABSQZrr VR512:$src)>;
4604 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
4605 RegisterClass RC, RegisterClass KRC,
4606 X86MemOperand x86memop,
4607 X86MemOperand x86scalar_mop, string BrdcstStr> {
4608 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4609 (ins RC:$src),
4610 !strconcat(OpcodeStr, " \t{$src, ${dst} |${dst}, $src}"),
4611 []>, EVEX;
4612 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4613 (ins x86memop:$src),
4614 !strconcat(OpcodeStr, " \t{$src, ${dst}|${dst}, $src}"),
4615 []>, EVEX;
4616 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4617 (ins x86scalar_mop:$src),
4618 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4619 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
4620 []>, EVEX, EVEX_B;
4621 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4622 (ins KRC:$mask, RC:$src),
4623 !strconcat(OpcodeStr,
4624 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4625 []>, EVEX, EVEX_KZ;
4626 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4627 (ins KRC:$mask, x86memop:$src),
4628 !strconcat(OpcodeStr,
4629 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4630 []>, EVEX, EVEX_KZ;
4631 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4632 (ins KRC:$mask, x86scalar_mop:$src),
4633 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4634 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
4635 BrdcstStr, "}"),
4636 []>, EVEX, EVEX_KZ, EVEX_B;
4638 let Constraints = "$src1 = $dst" in {
4639 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4640 (ins RC:$src1, KRC:$mask, RC:$src2),
4641 !strconcat(OpcodeStr,
4642 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4643 []>, EVEX, EVEX_K;
4644 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4645 (ins RC:$src1, KRC:$mask, x86memop:$src2),
4646 !strconcat(OpcodeStr,
4647 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4648 []>, EVEX, EVEX_K;
4649 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4650 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
4651 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
4652 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
4653 []>, EVEX, EVEX_K, EVEX_B;
4654 }
4655 }
4657 let Predicates = [HasCDI] in {
4658 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
4659 i512mem, i32mem, "{1to16}">,
4660 EVEX_V512, EVEX_CD8<32, CD8VF>;
4663 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
4664 i512mem, i64mem, "{1to8}">,
4665 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4667 }
4669 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
4670 GR16:$mask),
4671 (VPCONFLICTDrrk VR512:$src1,
4672 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
4674 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
4675 GR8:$mask),
4676 (VPCONFLICTQrrk VR512:$src1,
4677 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
4679 let Predicates = [HasCDI] in {
4680 defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
4681 i512mem, i32mem, "{1to16}">,
4682 EVEX_V512, EVEX_CD8<32, CD8VF>;
4685 defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
4686 i512mem, i64mem, "{1to8}">,
4687 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4689 }
4691 def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
4692 GR16:$mask),
4693 (VPLZCNTDrrk VR512:$src1,
4694 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
4696 def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
4697 GR8:$mask),
4698 (VPLZCNTQrrk VR512:$src1,
4699 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
4701 def : Pat<(v16i32 (ctlz (memopv16i32 addr:$src))),
4702 (VPLZCNTDrm addr:$src)>;
4703 def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
4704 (VPLZCNTDrr VR512:$src)>;
4705 def : Pat<(v8i64 (ctlz (memopv8i64 addr:$src))),
4706 (VPLZCNTQrm addr:$src)>;
4707 def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
4708 (VPLZCNTQrr VR512:$src)>;
4710 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
4711 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
4712 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
4714 def : Pat<(store VK1:$src, addr:$dst),
4715 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK16))>;
4717 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
4718 (truncstore node:$val, node:$ptr), [{
4719 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
4720 }]>;
4722 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
4723 (MOV8mr addr:$dst, GR8:$src)>;