8a6684cef0c7966dad9a70835c6ede3a49b6acae
[opencl/llvm.git] / lib / Target / X86 / X86InstrInfo.cpp
1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the X86 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
14 #include "X86InstrInfo.h"
15 #include "X86.h"
16 #include "X86InstrBuilder.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/LiveVariables.h"
22 #include "llvm/CodeGen/MachineConstantPool.h"
23 #include "llvm/CodeGen/MachineDominators.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/StackMaps.h"
28 #include "llvm/IR/DerivedTypes.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/IR/LLVMContext.h"
31 #include "llvm/MC/MCAsmInfo.h"
32 #include "llvm/MC/MCExpr.h"
33 #include "llvm/MC/MCInst.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
38 #include "llvm/Target/TargetOptions.h"
39 #include <limits>
41 using namespace llvm;
43 #define DEBUG_TYPE "x86-instr-info"
45 #define GET_INSTRINFO_CTOR_DTOR
46 #include "X86GenInstrInfo.inc"
48 static cl::opt<bool>
49 NoFusing("disable-spill-fusing",
50          cl::desc("Disable fusing of spill code into instructions"));
51 static cl::opt<bool>
52 PrintFailedFusing("print-failed-fuse-candidates",
53                   cl::desc("Print instructions that the allocator wants to"
54                            " fuse, but the X86 backend currently can't"),
55                   cl::Hidden);
56 static cl::opt<bool>
57 ReMatPICStubLoad("remat-pic-stub-load",
58                  cl::desc("Re-materialize load from stub in PIC mode"),
59                  cl::init(false), cl::Hidden);
61 enum {
62   // Select which memory operand is being unfolded.
63   // (stored in bits 0 - 3)
64   TB_INDEX_0    = 0,
65   TB_INDEX_1    = 1,
66   TB_INDEX_2    = 2,
67   TB_INDEX_3    = 3,
68   TB_INDEX_4    = 4,
69   TB_INDEX_MASK = 0xf,
71   // Do not insert the reverse map (MemOp -> RegOp) into the table.
72   // This may be needed because there is a many -> one mapping.
73   TB_NO_REVERSE   = 1 << 4,
75   // Do not insert the forward map (RegOp -> MemOp) into the table.
76   // This is needed for Native Client, which prohibits branch
77   // instructions from using a memory operand.
78   TB_NO_FORWARD   = 1 << 5,
80   TB_FOLDED_LOAD  = 1 << 6,
81   TB_FOLDED_STORE = 1 << 7,
83   // Minimum alignment required for load/store.
84   // Used for RegOp->MemOp conversion.
85   // (stored in bits 8 - 15)
86   TB_ALIGN_SHIFT = 8,
87   TB_ALIGN_NONE  =    0 << TB_ALIGN_SHIFT,
88   TB_ALIGN_16    =   16 << TB_ALIGN_SHIFT,
89   TB_ALIGN_32    =   32 << TB_ALIGN_SHIFT,
90   TB_ALIGN_64    =   64 << TB_ALIGN_SHIFT,
91   TB_ALIGN_MASK  = 0xff << TB_ALIGN_SHIFT
92 };
94 struct X86OpTblEntry {
95   uint16_t RegOp;
96   uint16_t MemOp;
97   uint16_t Flags;
98 };
100 // Pin the vtable to this file.
101 void X86InstrInfo::anchor() {}
103 X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
104     : X86GenInstrInfo(
105           (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64 : X86::ADJCALLSTACKDOWN32),
106           (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64 : X86::ADJCALLSTACKUP32)),
107       Subtarget(STI), RI(STI) {
109   static const X86OpTblEntry OpTbl2Addr[] = {
110     { X86::ADC32ri,     X86::ADC32mi,    0 },
111     { X86::ADC32ri8,    X86::ADC32mi8,   0 },
112     { X86::ADC32rr,     X86::ADC32mr,    0 },
113     { X86::ADC64ri32,   X86::ADC64mi32,  0 },
114     { X86::ADC64ri8,    X86::ADC64mi8,   0 },
115     { X86::ADC64rr,     X86::ADC64mr,    0 },
116     { X86::ADD16ri,     X86::ADD16mi,    0 },
117     { X86::ADD16ri8,    X86::ADD16mi8,   0 },
118     { X86::ADD16ri_DB,  X86::ADD16mi,    TB_NO_REVERSE },
119     { X86::ADD16ri8_DB, X86::ADD16mi8,   TB_NO_REVERSE },
120     { X86::ADD16rr,     X86::ADD16mr,    0 },
121     { X86::ADD16rr_DB,  X86::ADD16mr,    TB_NO_REVERSE },
122     { X86::ADD32ri,     X86::ADD32mi,    0 },
123     { X86::ADD32ri8,    X86::ADD32mi8,   0 },
124     { X86::ADD32ri_DB,  X86::ADD32mi,    TB_NO_REVERSE },
125     { X86::ADD32ri8_DB, X86::ADD32mi8,   TB_NO_REVERSE },
126     { X86::ADD32rr,     X86::ADD32mr,    0 },
127     { X86::ADD32rr_DB,  X86::ADD32mr,    TB_NO_REVERSE },
128     { X86::ADD64ri32,   X86::ADD64mi32,  0 },
129     { X86::ADD64ri8,    X86::ADD64mi8,   0 },
130     { X86::ADD64ri32_DB,X86::ADD64mi32,  TB_NO_REVERSE },
131     { X86::ADD64ri8_DB, X86::ADD64mi8,   TB_NO_REVERSE },
132     { X86::ADD64rr,     X86::ADD64mr,    0 },
133     { X86::ADD64rr_DB,  X86::ADD64mr,    TB_NO_REVERSE },
134     { X86::ADD8ri,      X86::ADD8mi,     0 },
135     { X86::ADD8rr,      X86::ADD8mr,     0 },
136     { X86::AND16ri,     X86::AND16mi,    0 },
137     { X86::AND16ri8,    X86::AND16mi8,   0 },
138     { X86::AND16rr,     X86::AND16mr,    0 },
139     { X86::AND32ri,     X86::AND32mi,    0 },
140     { X86::AND32ri8,    X86::AND32mi8,   0 },
141     { X86::AND32rr,     X86::AND32mr,    0 },
142     { X86::AND64ri32,   X86::AND64mi32,  0 },
143     { X86::AND64ri8,    X86::AND64mi8,   0 },
144     { X86::AND64rr,     X86::AND64mr,    0 },
145     { X86::AND8ri,      X86::AND8mi,     0 },
146     { X86::AND8rr,      X86::AND8mr,     0 },
147     { X86::DEC16r,      X86::DEC16m,     0 },
148     { X86::DEC32r,      X86::DEC32m,     0 },
149     { X86::DEC64r,      X86::DEC64m,     0 },
150     { X86::DEC8r,       X86::DEC8m,      0 },
151     { X86::INC16r,      X86::INC16m,     0 },
152     { X86::INC32r,      X86::INC32m,     0 },
153     { X86::INC64r,      X86::INC64m,     0 },
154     { X86::INC8r,       X86::INC8m,      0 },
155     { X86::NEG16r,      X86::NEG16m,     0 },
156     { X86::NEG32r,      X86::NEG32m,     0 },
157     { X86::NEG64r,      X86::NEG64m,     0 },
158     { X86::NEG8r,       X86::NEG8m,      0 },
159     { X86::NOT16r,      X86::NOT16m,     0 },
160     { X86::NOT32r,      X86::NOT32m,     0 },
161     { X86::NOT64r,      X86::NOT64m,     0 },
162     { X86::NOT8r,       X86::NOT8m,      0 },
163     { X86::OR16ri,      X86::OR16mi,     0 },
164     { X86::OR16ri8,     X86::OR16mi8,    0 },
165     { X86::OR16rr,      X86::OR16mr,     0 },
166     { X86::OR32ri,      X86::OR32mi,     0 },
167     { X86::OR32ri8,     X86::OR32mi8,    0 },
168     { X86::OR32rr,      X86::OR32mr,     0 },
169     { X86::OR64ri32,    X86::OR64mi32,   0 },
170     { X86::OR64ri8,     X86::OR64mi8,    0 },
171     { X86::OR64rr,      X86::OR64mr,     0 },
172     { X86::OR8ri,       X86::OR8mi,      0 },
173     { X86::OR8rr,       X86::OR8mr,      0 },
174     { X86::ROL16r1,     X86::ROL16m1,    0 },
175     { X86::ROL16rCL,    X86::ROL16mCL,   0 },
176     { X86::ROL16ri,     X86::ROL16mi,    0 },
177     { X86::ROL32r1,     X86::ROL32m1,    0 },
178     { X86::ROL32rCL,    X86::ROL32mCL,   0 },
179     { X86::ROL32ri,     X86::ROL32mi,    0 },
180     { X86::ROL64r1,     X86::ROL64m1,    0 },
181     { X86::ROL64rCL,    X86::ROL64mCL,   0 },
182     { X86::ROL64ri,     X86::ROL64mi,    0 },
183     { X86::ROL8r1,      X86::ROL8m1,     0 },
184     { X86::ROL8rCL,     X86::ROL8mCL,    0 },
185     { X86::ROL8ri,      X86::ROL8mi,     0 },
186     { X86::ROR16r1,     X86::ROR16m1,    0 },
187     { X86::ROR16rCL,    X86::ROR16mCL,   0 },
188     { X86::ROR16ri,     X86::ROR16mi,    0 },
189     { X86::ROR32r1,     X86::ROR32m1,    0 },
190     { X86::ROR32rCL,    X86::ROR32mCL,   0 },
191     { X86::ROR32ri,     X86::ROR32mi,    0 },
192     { X86::ROR64r1,     X86::ROR64m1,    0 },
193     { X86::ROR64rCL,    X86::ROR64mCL,   0 },
194     { X86::ROR64ri,     X86::ROR64mi,    0 },
195     { X86::ROR8r1,      X86::ROR8m1,     0 },
196     { X86::ROR8rCL,     X86::ROR8mCL,    0 },
197     { X86::ROR8ri,      X86::ROR8mi,     0 },
198     { X86::SAR16r1,     X86::SAR16m1,    0 },
199     { X86::SAR16rCL,    X86::SAR16mCL,   0 },
200     { X86::SAR16ri,     X86::SAR16mi,    0 },
201     { X86::SAR32r1,     X86::SAR32m1,    0 },
202     { X86::SAR32rCL,    X86::SAR32mCL,   0 },
203     { X86::SAR32ri,     X86::SAR32mi,    0 },
204     { X86::SAR64r1,     X86::SAR64m1,    0 },
205     { X86::SAR64rCL,    X86::SAR64mCL,   0 },
206     { X86::SAR64ri,     X86::SAR64mi,    0 },
207     { X86::SAR8r1,      X86::SAR8m1,     0 },
208     { X86::SAR8rCL,     X86::SAR8mCL,    0 },
209     { X86::SAR8ri,      X86::SAR8mi,     0 },
210     { X86::SBB32ri,     X86::SBB32mi,    0 },
211     { X86::SBB32ri8,    X86::SBB32mi8,   0 },
212     { X86::SBB32rr,     X86::SBB32mr,    0 },
213     { X86::SBB64ri32,   X86::SBB64mi32,  0 },
214     { X86::SBB64ri8,    X86::SBB64mi8,   0 },
215     { X86::SBB64rr,     X86::SBB64mr,    0 },
216     { X86::SHL16rCL,    X86::SHL16mCL,   0 },
217     { X86::SHL16ri,     X86::SHL16mi,    0 },
218     { X86::SHL32rCL,    X86::SHL32mCL,   0 },
219     { X86::SHL32ri,     X86::SHL32mi,    0 },
220     { X86::SHL64rCL,    X86::SHL64mCL,   0 },
221     { X86::SHL64ri,     X86::SHL64mi,    0 },
222     { X86::SHL8rCL,     X86::SHL8mCL,    0 },
223     { X86::SHL8ri,      X86::SHL8mi,     0 },
224     { X86::SHLD16rrCL,  X86::SHLD16mrCL, 0 },
225     { X86::SHLD16rri8,  X86::SHLD16mri8, 0 },
226     { X86::SHLD32rrCL,  X86::SHLD32mrCL, 0 },
227     { X86::SHLD32rri8,  X86::SHLD32mri8, 0 },
228     { X86::SHLD64rrCL,  X86::SHLD64mrCL, 0 },
229     { X86::SHLD64rri8,  X86::SHLD64mri8, 0 },
230     { X86::SHR16r1,     X86::SHR16m1,    0 },
231     { X86::SHR16rCL,    X86::SHR16mCL,   0 },
232     { X86::SHR16ri,     X86::SHR16mi,    0 },
233     { X86::SHR32r1,     X86::SHR32m1,    0 },
234     { X86::SHR32rCL,    X86::SHR32mCL,   0 },
235     { X86::SHR32ri,     X86::SHR32mi,    0 },
236     { X86::SHR64r1,     X86::SHR64m1,    0 },
237     { X86::SHR64rCL,    X86::SHR64mCL,   0 },
238     { X86::SHR64ri,     X86::SHR64mi,    0 },
239     { X86::SHR8r1,      X86::SHR8m1,     0 },
240     { X86::SHR8rCL,     X86::SHR8mCL,    0 },
241     { X86::SHR8ri,      X86::SHR8mi,     0 },
242     { X86::SHRD16rrCL,  X86::SHRD16mrCL, 0 },
243     { X86::SHRD16rri8,  X86::SHRD16mri8, 0 },
244     { X86::SHRD32rrCL,  X86::SHRD32mrCL, 0 },
245     { X86::SHRD32rri8,  X86::SHRD32mri8, 0 },
246     { X86::SHRD64rrCL,  X86::SHRD64mrCL, 0 },
247     { X86::SHRD64rri8,  X86::SHRD64mri8, 0 },
248     { X86::SUB16ri,     X86::SUB16mi,    0 },
249     { X86::SUB16ri8,    X86::SUB16mi8,   0 },
250     { X86::SUB16rr,     X86::SUB16mr,    0 },
251     { X86::SUB32ri,     X86::SUB32mi,    0 },
252     { X86::SUB32ri8,    X86::SUB32mi8,   0 },
253     { X86::SUB32rr,     X86::SUB32mr,    0 },
254     { X86::SUB64ri32,   X86::SUB64mi32,  0 },
255     { X86::SUB64ri8,    X86::SUB64mi8,   0 },
256     { X86::SUB64rr,     X86::SUB64mr,    0 },
257     { X86::SUB8ri,      X86::SUB8mi,     0 },
258     { X86::SUB8rr,      X86::SUB8mr,     0 },
259     { X86::XOR16ri,     X86::XOR16mi,    0 },
260     { X86::XOR16ri8,    X86::XOR16mi8,   0 },
261     { X86::XOR16rr,     X86::XOR16mr,    0 },
262     { X86::XOR32ri,     X86::XOR32mi,    0 },
263     { X86::XOR32ri8,    X86::XOR32mi8,   0 },
264     { X86::XOR32rr,     X86::XOR32mr,    0 },
265     { X86::XOR64ri32,   X86::XOR64mi32,  0 },
266     { X86::XOR64ri8,    X86::XOR64mi8,   0 },
267     { X86::XOR64rr,     X86::XOR64mr,    0 },
268     { X86::XOR8ri,      X86::XOR8mi,     0 },
269     { X86::XOR8rr,      X86::XOR8mr,     0 }
270   };
272   for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
273     unsigned RegOp = OpTbl2Addr[i].RegOp;
274     unsigned MemOp = OpTbl2Addr[i].MemOp;
275     unsigned Flags = OpTbl2Addr[i].Flags;
276     AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
277                   RegOp, MemOp,
278                   // Index 0, folded load and store, no alignment requirement.
279                   Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
280   }
282   static const X86OpTblEntry OpTbl0[] = {
283     { X86::BT16ri8,     X86::BT16mi8,       TB_FOLDED_LOAD },
284     { X86::BT32ri8,     X86::BT32mi8,       TB_FOLDED_LOAD },
285     { X86::BT64ri8,     X86::BT64mi8,       TB_FOLDED_LOAD },
286     { X86::CALL32r,     X86::CALL32m,       TB_FOLDED_LOAD },
287     { X86::CALL64r,     X86::CALL64m,       TB_FOLDED_LOAD },
288     { X86::CMP16ri,     X86::CMP16mi,       TB_FOLDED_LOAD },
289     { X86::CMP16ri8,    X86::CMP16mi8,      TB_FOLDED_LOAD },
290     { X86::CMP16rr,     X86::CMP16mr,       TB_FOLDED_LOAD },
291     { X86::CMP32ri,     X86::CMP32mi,       TB_FOLDED_LOAD },
292     { X86::CMP32ri8,    X86::CMP32mi8,      TB_FOLDED_LOAD },
293     { X86::CMP32rr,     X86::CMP32mr,       TB_FOLDED_LOAD },
294     { X86::CMP64ri32,   X86::CMP64mi32,     TB_FOLDED_LOAD },
295     { X86::CMP64ri8,    X86::CMP64mi8,      TB_FOLDED_LOAD },
296     { X86::CMP64rr,     X86::CMP64mr,       TB_FOLDED_LOAD },
297     { X86::CMP8ri,      X86::CMP8mi,        TB_FOLDED_LOAD },
298     { X86::CMP8rr,      X86::CMP8mr,        TB_FOLDED_LOAD },
299     { X86::DIV16r,      X86::DIV16m,        TB_FOLDED_LOAD },
300     { X86::DIV32r,      X86::DIV32m,        TB_FOLDED_LOAD },
301     { X86::DIV64r,      X86::DIV64m,        TB_FOLDED_LOAD },
302     { X86::DIV8r,       X86::DIV8m,         TB_FOLDED_LOAD },
303     { X86::EXTRACTPSrr, X86::EXTRACTPSmr,   TB_FOLDED_STORE },
304     { X86::IDIV16r,     X86::IDIV16m,       TB_FOLDED_LOAD },
305     { X86::IDIV32r,     X86::IDIV32m,       TB_FOLDED_LOAD },
306     { X86::IDIV64r,     X86::IDIV64m,       TB_FOLDED_LOAD },
307     { X86::IDIV8r,      X86::IDIV8m,        TB_FOLDED_LOAD },
308     { X86::IMUL16r,     X86::IMUL16m,       TB_FOLDED_LOAD },
309     { X86::IMUL32r,     X86::IMUL32m,       TB_FOLDED_LOAD },
310     { X86::IMUL64r,     X86::IMUL64m,       TB_FOLDED_LOAD },
311     { X86::IMUL8r,      X86::IMUL8m,        TB_FOLDED_LOAD },
312     { X86::JMP32r,      X86::JMP32m,        TB_FOLDED_LOAD },
313     { X86::JMP64r,      X86::JMP64m,        TB_FOLDED_LOAD },
314     { X86::MOV16ri,     X86::MOV16mi,       TB_FOLDED_STORE },
315     { X86::MOV16rr,     X86::MOV16mr,       TB_FOLDED_STORE },
316     { X86::MOV32ri,     X86::MOV32mi,       TB_FOLDED_STORE },
317     { X86::MOV32rr,     X86::MOV32mr,       TB_FOLDED_STORE },
318     { X86::MOV64ri32,   X86::MOV64mi32,     TB_FOLDED_STORE },
319     { X86::MOV64rr,     X86::MOV64mr,       TB_FOLDED_STORE },
320     { X86::MOV8ri,      X86::MOV8mi,        TB_FOLDED_STORE },
321     { X86::MOV8rr,      X86::MOV8mr,        TB_FOLDED_STORE },
322     { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
323     { X86::MOVAPDrr,    X86::MOVAPDmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
324     { X86::MOVAPSrr,    X86::MOVAPSmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
325     { X86::MOVDQArr,    X86::MOVDQAmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
326     { X86::MOVPDI2DIrr, X86::MOVPDI2DImr,   TB_FOLDED_STORE },
327     { X86::MOVPQIto64rr,X86::MOVPQI2QImr,   TB_FOLDED_STORE },
328     { X86::MOVSDto64rr, X86::MOVSDto64mr,   TB_FOLDED_STORE },
329     { X86::MOVSS2DIrr,  X86::MOVSS2DImr,    TB_FOLDED_STORE },
330     { X86::MOVUPDrr,    X86::MOVUPDmr,      TB_FOLDED_STORE },
331     { X86::MOVUPSrr,    X86::MOVUPSmr,      TB_FOLDED_STORE },
332     { X86::MUL16r,      X86::MUL16m,        TB_FOLDED_LOAD },
333     { X86::MUL32r,      X86::MUL32m,        TB_FOLDED_LOAD },
334     { X86::MUL64r,      X86::MUL64m,        TB_FOLDED_LOAD },
335     { X86::MUL8r,       X86::MUL8m,         TB_FOLDED_LOAD },
336     { X86::PEXTRDrr,    X86::PEXTRDmr,      TB_FOLDED_STORE },
337     { X86::PEXTRQrr,    X86::PEXTRQmr,      TB_FOLDED_STORE },
338     { X86::SETAEr,      X86::SETAEm,        TB_FOLDED_STORE },
339     { X86::SETAr,       X86::SETAm,         TB_FOLDED_STORE },
340     { X86::SETBEr,      X86::SETBEm,        TB_FOLDED_STORE },
341     { X86::SETBr,       X86::SETBm,         TB_FOLDED_STORE },
342     { X86::SETEr,       X86::SETEm,         TB_FOLDED_STORE },
343     { X86::SETGEr,      X86::SETGEm,        TB_FOLDED_STORE },
344     { X86::SETGr,       X86::SETGm,         TB_FOLDED_STORE },
345     { X86::SETLEr,      X86::SETLEm,        TB_FOLDED_STORE },
346     { X86::SETLr,       X86::SETLm,         TB_FOLDED_STORE },
347     { X86::SETNEr,      X86::SETNEm,        TB_FOLDED_STORE },
348     { X86::SETNOr,      X86::SETNOm,        TB_FOLDED_STORE },
349     { X86::SETNPr,      X86::SETNPm,        TB_FOLDED_STORE },
350     { X86::SETNSr,      X86::SETNSm,        TB_FOLDED_STORE },
351     { X86::SETOr,       X86::SETOm,         TB_FOLDED_STORE },
352     { X86::SETPr,       X86::SETPm,         TB_FOLDED_STORE },
353     { X86::SETSr,       X86::SETSm,         TB_FOLDED_STORE },
354     { X86::TAILJMPr,    X86::TAILJMPm,      TB_FOLDED_LOAD },
355     { X86::TAILJMPr64,  X86::TAILJMPm64,    TB_FOLDED_LOAD },
356     { X86::TEST16ri,    X86::TEST16mi,      TB_FOLDED_LOAD },
357     { X86::TEST32ri,    X86::TEST32mi,      TB_FOLDED_LOAD },
358     { X86::TEST64ri32,  X86::TEST64mi32,    TB_FOLDED_LOAD },
359     { X86::TEST8ri,     X86::TEST8mi,       TB_FOLDED_LOAD },
360     // AVX 128-bit versions of foldable instructions
361     { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr,  TB_FOLDED_STORE  },
362     { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
363     { X86::VMOVAPDrr,   X86::VMOVAPDmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
364     { X86::VMOVAPSrr,   X86::VMOVAPSmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
365     { X86::VMOVDQArr,   X86::VMOVDQAmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
366     { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr,  TB_FOLDED_STORE },
367     { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
368     { X86::VMOVSDto64rr,X86::VMOVSDto64mr,  TB_FOLDED_STORE },
369     { X86::VMOVSS2DIrr, X86::VMOVSS2DImr,   TB_FOLDED_STORE },
370     { X86::VMOVUPDrr,   X86::VMOVUPDmr,     TB_FOLDED_STORE },
371     { X86::VMOVUPSrr,   X86::VMOVUPSmr,     TB_FOLDED_STORE },
372     { X86::VPEXTRDrr,   X86::VPEXTRDmr,     TB_FOLDED_STORE },
373     { X86::VPEXTRQrr,   X86::VPEXTRQmr,     TB_FOLDED_STORE },
374     // AVX 256-bit foldable instructions
375     { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
376     { X86::VMOVAPDYrr,  X86::VMOVAPDYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
377     { X86::VMOVAPSYrr,  X86::VMOVAPSYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
378     { X86::VMOVDQAYrr,  X86::VMOVDQAYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
379     { X86::VMOVUPDYrr,  X86::VMOVUPDYmr,    TB_FOLDED_STORE },
380     { X86::VMOVUPSYrr,  X86::VMOVUPSYmr,    TB_FOLDED_STORE },
381     // AVX-512 foldable instructions
382     { X86::VMOVPDI2DIZrr,   X86::VMOVPDI2DIZmr, TB_FOLDED_STORE },
383     { X86::VMOVAPDZrr,      X86::VMOVAPDZmr,    TB_FOLDED_STORE | TB_ALIGN_64 },
384     { X86::VMOVAPSZrr,      X86::VMOVAPSZmr,    TB_FOLDED_STORE | TB_ALIGN_64 },
385     { X86::VMOVDQA32Zrr,    X86::VMOVDQA32Zmr,  TB_FOLDED_STORE | TB_ALIGN_64 },
386     { X86::VMOVDQA64Zrr,    X86::VMOVDQA64Zmr,  TB_FOLDED_STORE | TB_ALIGN_64 },
387     { X86::VMOVUPDZrr,      X86::VMOVUPDZmr,    TB_FOLDED_STORE },
388     { X86::VMOVUPSZrr,      X86::VMOVUPSZmr,    TB_FOLDED_STORE },
389     { X86::VMOVDQU8Zrr,     X86::VMOVDQU8Zmr,   TB_FOLDED_STORE },
390     { X86::VMOVDQU16Zrr,    X86::VMOVDQU16Zmr,  TB_FOLDED_STORE },
391     { X86::VMOVDQU32Zrr,    X86::VMOVDQU32Zmr,  TB_FOLDED_STORE },
392     { X86::VMOVDQU64Zrr,    X86::VMOVDQU64Zmr,  TB_FOLDED_STORE },
393     // AVX-512 foldable instructions (256-bit versions)
394     { X86::VMOVAPDZ256rr,      X86::VMOVAPDZ256mr,    TB_FOLDED_STORE | TB_ALIGN_32 },
395     { X86::VMOVAPSZ256rr,      X86::VMOVAPSZ256mr,    TB_FOLDED_STORE | TB_ALIGN_32 },
396     { X86::VMOVDQA32Z256rr,    X86::VMOVDQA32Z256mr,  TB_FOLDED_STORE | TB_ALIGN_32 },
397     { X86::VMOVDQA64Z256rr,    X86::VMOVDQA64Z256mr,  TB_FOLDED_STORE | TB_ALIGN_32 },
398     { X86::VMOVUPDZ256rr,      X86::VMOVUPDZ256mr,    TB_FOLDED_STORE },
399     { X86::VMOVUPSZ256rr,      X86::VMOVUPSZ256mr,    TB_FOLDED_STORE },
400     { X86::VMOVDQU8Z256rr,     X86::VMOVDQU8Z256mr,   TB_FOLDED_STORE },
401     { X86::VMOVDQU16Z256rr,    X86::VMOVDQU16Z256mr,  TB_FOLDED_STORE },
402     { X86::VMOVDQU32Z256rr,    X86::VMOVDQU32Z256mr,  TB_FOLDED_STORE },
403     { X86::VMOVDQU64Z256rr,    X86::VMOVDQU64Z256mr,  TB_FOLDED_STORE },
404     // AVX-512 foldable instructions (128-bit versions)
405     { X86::VMOVAPDZ128rr,      X86::VMOVAPDZ128mr,    TB_FOLDED_STORE | TB_ALIGN_16 },
406     { X86::VMOVAPSZ128rr,      X86::VMOVAPSZ128mr,    TB_FOLDED_STORE | TB_ALIGN_16 },
407     { X86::VMOVDQA32Z128rr,    X86::VMOVDQA32Z128mr,  TB_FOLDED_STORE | TB_ALIGN_16 },
408     { X86::VMOVDQA64Z128rr,    X86::VMOVDQA64Z128mr,  TB_FOLDED_STORE | TB_ALIGN_16 },
409     { X86::VMOVUPDZ128rr,      X86::VMOVUPDZ128mr,    TB_FOLDED_STORE },
410     { X86::VMOVUPSZ128rr,      X86::VMOVUPSZ128mr,    TB_FOLDED_STORE },
411     { X86::VMOVDQU8Z128rr,     X86::VMOVDQU8Z128mr,   TB_FOLDED_STORE },
412     { X86::VMOVDQU16Z128rr,    X86::VMOVDQU16Z128mr,  TB_FOLDED_STORE },
413     { X86::VMOVDQU32Z128rr,    X86::VMOVDQU32Z128mr,  TB_FOLDED_STORE },
414     { X86::VMOVDQU64Z128rr,    X86::VMOVDQU64Z128mr,  TB_FOLDED_STORE },
415     // F16C foldable instructions
416     { X86::VCVTPS2PHrr,        X86::VCVTPS2PHmr,      TB_FOLDED_STORE },
417     { X86::VCVTPS2PHYrr,       X86::VCVTPS2PHYmr,     TB_FOLDED_STORE }
418   };
420   for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
421     unsigned RegOp      = OpTbl0[i].RegOp;
422     unsigned MemOp      = OpTbl0[i].MemOp;
423     unsigned Flags      = OpTbl0[i].Flags;
424     AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
425                   RegOp, MemOp, TB_INDEX_0 | Flags);
426   }
428   static const X86OpTblEntry OpTbl1[] = {
429     { X86::CMP16rr,         X86::CMP16rm,             0 },
430     { X86::CMP32rr,         X86::CMP32rm,             0 },
431     { X86::CMP64rr,         X86::CMP64rm,             0 },
432     { X86::CMP8rr,          X86::CMP8rm,              0 },
433     { X86::CVTSD2SSrr,      X86::CVTSD2SSrm,          0 },
434     { X86::CVTSI2SD64rr,    X86::CVTSI2SD64rm,        0 },
435     { X86::CVTSI2SDrr,      X86::CVTSI2SDrm,          0 },
436     { X86::CVTSI2SS64rr,    X86::CVTSI2SS64rm,        0 },
437     { X86::CVTSI2SSrr,      X86::CVTSI2SSrm,          0 },
438     { X86::CVTSS2SDrr,      X86::CVTSS2SDrm,          0 },
439     { X86::CVTTSD2SI64rr,   X86::CVTTSD2SI64rm,       0 },
440     { X86::CVTTSD2SIrr,     X86::CVTTSD2SIrm,         0 },
441     { X86::CVTTSS2SI64rr,   X86::CVTTSS2SI64rm,       0 },
442     { X86::CVTTSS2SIrr,     X86::CVTTSS2SIrm,         0 },
443     { X86::IMUL16rri,       X86::IMUL16rmi,           0 },
444     { X86::IMUL16rri8,      X86::IMUL16rmi8,          0 },
445     { X86::IMUL32rri,       X86::IMUL32rmi,           0 },
446     { X86::IMUL32rri8,      X86::IMUL32rmi8,          0 },
447     { X86::IMUL64rri32,     X86::IMUL64rmi32,         0 },
448     { X86::IMUL64rri8,      X86::IMUL64rmi8,          0 },
449     { X86::Int_COMISDrr,    X86::Int_COMISDrm,        0 },
450     { X86::Int_COMISSrr,    X86::Int_COMISSrm,        0 },
451     { X86::CVTSD2SI64rr,    X86::CVTSD2SI64rm,        0 },
452     { X86::CVTSD2SIrr,      X86::CVTSD2SIrm,          0 },
453     { X86::CVTSS2SI64rr,    X86::CVTSS2SI64rm,        0 },
454     { X86::CVTSS2SIrr,      X86::CVTSS2SIrm,          0 },
455     { X86::CVTDQ2PDrr,      X86::CVTDQ2PDrm,          TB_ALIGN_16 },
456     { X86::CVTDQ2PSrr,      X86::CVTDQ2PSrm,          TB_ALIGN_16 },
457     { X86::CVTPD2DQrr,      X86::CVTPD2DQrm,          TB_ALIGN_16 },
458     { X86::CVTPD2PSrr,      X86::CVTPD2PSrm,          TB_ALIGN_16 },
459     { X86::CVTPS2DQrr,      X86::CVTPS2DQrm,          TB_ALIGN_16 },
460     { X86::CVTPS2PDrr,      X86::CVTPS2PDrm,          TB_ALIGN_16 },
461     { X86::CVTTPD2DQrr,     X86::CVTTPD2DQrm,         TB_ALIGN_16 },
462     { X86::CVTTPS2DQrr,     X86::CVTTPS2DQrm,         TB_ALIGN_16 },
463     { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm,  0 },
464     { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm,     0 },
465     { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm,  0 },
466     { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm,     0 },
467     { X86::Int_UCOMISDrr,   X86::Int_UCOMISDrm,       0 },
468     { X86::Int_UCOMISSrr,   X86::Int_UCOMISSrm,       0 },
469     { X86::MOV16rr,         X86::MOV16rm,             0 },
470     { X86::MOV32rr,         X86::MOV32rm,             0 },
471     { X86::MOV64rr,         X86::MOV64rm,             0 },
472     { X86::MOV64toPQIrr,    X86::MOVQI2PQIrm,         0 },
473     { X86::MOV64toSDrr,     X86::MOV64toSDrm,         0 },
474     { X86::MOV8rr,          X86::MOV8rm,              0 },
475     { X86::MOVAPDrr,        X86::MOVAPDrm,            TB_ALIGN_16 },
476     { X86::MOVAPSrr,        X86::MOVAPSrm,            TB_ALIGN_16 },
477     { X86::MOVDDUPrr,       X86::MOVDDUPrm,           0 },
478     { X86::MOVDI2PDIrr,     X86::MOVDI2PDIrm,         0 },
479     { X86::MOVDI2SSrr,      X86::MOVDI2SSrm,          0 },
480     { X86::MOVDQArr,        X86::MOVDQArm,            TB_ALIGN_16 },
481     { X86::MOVSHDUPrr,      X86::MOVSHDUPrm,          TB_ALIGN_16 },
482     { X86::MOVSLDUPrr,      X86::MOVSLDUPrm,          TB_ALIGN_16 },
483     { X86::MOVSX16rr8,      X86::MOVSX16rm8,          0 },
484     { X86::MOVSX32rr16,     X86::MOVSX32rm16,         0 },
485     { X86::MOVSX32rr8,      X86::MOVSX32rm8,          0 },
486     { X86::MOVSX64rr16,     X86::MOVSX64rm16,         0 },
487     { X86::MOVSX64rr32,     X86::MOVSX64rm32,         0 },
488     { X86::MOVSX64rr8,      X86::MOVSX64rm8,          0 },
489     { X86::MOVUPDrr,        X86::MOVUPDrm,            TB_ALIGN_16 },
490     { X86::MOVUPSrr,        X86::MOVUPSrm,            0 },
491     { X86::MOVZQI2PQIrr,    X86::MOVZQI2PQIrm,        0 },
492     { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm,     TB_ALIGN_16 },
493     { X86::MOVZX16rr8,      X86::MOVZX16rm8,          0 },
494     { X86::MOVZX32rr16,     X86::MOVZX32rm16,         0 },
495     { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8,   0 },
496     { X86::MOVZX32rr8,      X86::MOVZX32rm8,          0 },
497     { X86::PABSBrr128,      X86::PABSBrm128,          TB_ALIGN_16 },
498     { X86::PABSDrr128,      X86::PABSDrm128,          TB_ALIGN_16 },
499     { X86::PABSWrr128,      X86::PABSWrm128,          TB_ALIGN_16 },
500     { X86::PCMPESTRIrr,     X86::PCMPESTRIrm,         TB_ALIGN_16 },
501     { X86::PCMPESTRM128rr,  X86::PCMPESTRM128rm,      TB_ALIGN_16 },
502     { X86::PCMPISTRIrr,     X86::PCMPISTRIrm,         TB_ALIGN_16 },
503     { X86::PCMPISTRM128rr,  X86::PCMPISTRM128rm,      TB_ALIGN_16 },
504     { X86::PHMINPOSUWrr128, X86::PHMINPOSUWrm128,     TB_ALIGN_16 },
505     { X86::PMOVSXBDrr,      X86::PMOVSXBDrm,          TB_ALIGN_16 },
506     { X86::PMOVSXBQrr,      X86::PMOVSXBQrm,          TB_ALIGN_16 },
507     { X86::PMOVSXBWrr,      X86::PMOVSXBWrm,          TB_ALIGN_16 },
508     { X86::PMOVSXDQrr,      X86::PMOVSXDQrm,          TB_ALIGN_16 },
509     { X86::PMOVSXWDrr,      X86::PMOVSXWDrm,          TB_ALIGN_16 },
510     { X86::PMOVSXWQrr,      X86::PMOVSXWQrm,          TB_ALIGN_16 },
511     { X86::PMOVZXBDrr,      X86::PMOVZXBDrm,          TB_ALIGN_16 },
512     { X86::PMOVZXBQrr,      X86::PMOVZXBQrm,          TB_ALIGN_16 },
513     { X86::PMOVZXBWrr,      X86::PMOVZXBWrm,          TB_ALIGN_16 },
514     { X86::PMOVZXDQrr,      X86::PMOVZXDQrm,          TB_ALIGN_16 },
515     { X86::PMOVZXWDrr,      X86::PMOVZXWDrm,          TB_ALIGN_16 },
516     { X86::PMOVZXWQrr,      X86::PMOVZXWQrm,          TB_ALIGN_16 },
517     { X86::PSHUFDri,        X86::PSHUFDmi,            TB_ALIGN_16 },
518     { X86::PSHUFHWri,       X86::PSHUFHWmi,           TB_ALIGN_16 },
519     { X86::PSHUFLWri,       X86::PSHUFLWmi,           TB_ALIGN_16 },
520     { X86::PTESTrr,         X86::PTESTrm,             TB_ALIGN_16 },
521     { X86::RCPPSr,          X86::RCPPSm,              TB_ALIGN_16 },
522     { X86::RCPPSr_Int,      X86::RCPPSm_Int,          TB_ALIGN_16 },
523     { X86::ROUNDPDr,        X86::ROUNDPDm,            TB_ALIGN_16 },
524     { X86::ROUNDPSr,        X86::ROUNDPSm,            TB_ALIGN_16 },
525     { X86::RSQRTPSr,        X86::RSQRTPSm,            TB_ALIGN_16 },
526     { X86::RSQRTPSr_Int,    X86::RSQRTPSm_Int,        TB_ALIGN_16 },
527     { X86::RSQRTSSr,        X86::RSQRTSSm,            0 },
528     { X86::RSQRTSSr_Int,    X86::RSQRTSSm_Int,        0 },
529     { X86::SQRTPDr,         X86::SQRTPDm,             TB_ALIGN_16 },
530     { X86::SQRTPSr,         X86::SQRTPSm,             TB_ALIGN_16 },
531     { X86::SQRTSDr,         X86::SQRTSDm,             0 },
532     { X86::SQRTSDr_Int,     X86::SQRTSDm_Int,         0 },
533     { X86::SQRTSSr,         X86::SQRTSSm,             0 },
534     { X86::SQRTSSr_Int,     X86::SQRTSSm_Int,         0 },
535     { X86::TEST16rr,        X86::TEST16rm,            0 },
536     { X86::TEST32rr,        X86::TEST32rm,            0 },
537     { X86::TEST64rr,        X86::TEST64rm,            0 },
538     { X86::TEST8rr,         X86::TEST8rm,             0 },
539     // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
540     { X86::UCOMISDrr,       X86::UCOMISDrm,           0 },
541     { X86::UCOMISSrr,       X86::UCOMISSrm,           0 },
542     // AVX 128-bit versions of foldable instructions
543     { X86::Int_VCOMISDrr,   X86::Int_VCOMISDrm,       0 },
544     { X86::Int_VCOMISSrr,   X86::Int_VCOMISSrm,       0 },
545     { X86::Int_VUCOMISDrr,  X86::Int_VUCOMISDrm,      0 },
546     { X86::Int_VUCOMISSrr,  X86::Int_VUCOMISSrm,      0 },
547     { X86::VCVTTSD2SI64rr,  X86::VCVTTSD2SI64rm,      0 },
548     { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 },
549     { X86::VCVTTSD2SIrr,    X86::VCVTTSD2SIrm,        0 },
550     { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm,    0 },
551     { X86::VCVTTSS2SI64rr,  X86::VCVTTSS2SI64rm,      0 },
552     { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 },
553     { X86::VCVTTSS2SIrr,    X86::VCVTTSS2SIrm,        0 },
554     { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm,    0 },
555     { X86::VCVTSD2SI64rr,   X86::VCVTSD2SI64rm,       0 },
556     { X86::VCVTSD2SIrr,     X86::VCVTSD2SIrm,         0 },
557     { X86::VCVTSS2SI64rr,   X86::VCVTSS2SI64rm,       0 },
558     { X86::VCVTSS2SIrr,     X86::VCVTSS2SIrm,         0 },
559     { X86::VCVTDQ2PDrr,     X86::VCVTDQ2PDrm,         0 },
560     { X86::VCVTDQ2PSrr,     X86::VCVTDQ2PSrm,         0 },
561     { X86::VCVTPD2DQrr,     X86::VCVTPD2DQXrm,        0 },
562     { X86::VCVTPD2PSrr,     X86::VCVTPD2PSXrm,        0 },
563     { X86::VCVTPS2DQrr,     X86::VCVTPS2DQrm,         0 },
564     { X86::VCVTPS2PDrr,     X86::VCVTPS2PDrm,         0 },
565     { X86::VCVTTPD2DQrr,    X86::VCVTTPD2DQXrm,       0 },
566     { X86::VCVTTPS2DQrr,    X86::VCVTTPS2DQrm,        0 },
567     { X86::VMOV64toPQIrr,   X86::VMOVQI2PQIrm,        0 },
568     { X86::VMOV64toSDrr,    X86::VMOV64toSDrm,        0 },
569     { X86::VMOVAPDrr,       X86::VMOVAPDrm,           TB_ALIGN_16 },
570     { X86::VMOVAPSrr,       X86::VMOVAPSrm,           TB_ALIGN_16 },
571     { X86::VMOVDDUPrr,      X86::VMOVDDUPrm,          0 },
572     { X86::VMOVDI2PDIrr,    X86::VMOVDI2PDIrm,        0 },
573     { X86::VMOVDI2SSrr,     X86::VMOVDI2SSrm,         0 },
574     { X86::VMOVDQArr,       X86::VMOVDQArm,           TB_ALIGN_16 },
575     { X86::VMOVSLDUPrr,     X86::VMOVSLDUPrm,         TB_ALIGN_16 },
576     { X86::VMOVSHDUPrr,     X86::VMOVSHDUPrm,         TB_ALIGN_16 },
577     { X86::VMOVUPDrr,       X86::VMOVUPDrm,           0 },
578     { X86::VMOVUPSrr,       X86::VMOVUPSrm,           0 },
579     { X86::VMOVZQI2PQIrr,   X86::VMOVZQI2PQIrm,       0 },
580     { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm,    TB_ALIGN_16 },
581     { X86::VPABSBrr128,     X86::VPABSBrm128,         0 },
582     { X86::VPABSDrr128,     X86::VPABSDrm128,         0 },
583     { X86::VPABSWrr128,     X86::VPABSWrm128,         0 },
584     { X86::VPCMPESTRIrr,    X86::VPCMPESTRIrm,        0 },
585     { X86::VPCMPESTRM128rr, X86::VPCMPESTRM128rm,     0 },
586     { X86::VPCMPISTRIrr,    X86::VPCMPISTRIrm,        0 },
587     { X86::VPCMPISTRM128rr, X86::VPCMPISTRM128rm,     0 },
588     { X86::VPHMINPOSUWrr128, X86::VPHMINPOSUWrm128,   0 },
589     { X86::VPERMILPDri,     X86::VPERMILPDmi,         0 },
590     { X86::VPERMILPSri,     X86::VPERMILPSmi,         0 },
591     { X86::VPMOVSXBDrr,     X86::VPMOVSXBDrm,         0 },
592     { X86::VPMOVSXBQrr,     X86::VPMOVSXBQrm,         0 },
593     { X86::VPMOVSXBWrr,     X86::VPMOVSXBWrm,         0 },
594     { X86::VPMOVSXDQrr,     X86::VPMOVSXDQrm,         0 },
595     { X86::VPMOVSXWDrr,     X86::VPMOVSXWDrm,         0 },
596     { X86::VPMOVSXWQrr,     X86::VPMOVSXWQrm,         0 },
597     { X86::VPMOVZXBDrr,     X86::VPMOVZXBDrm,         0 },
598     { X86::VPMOVZXBQrr,     X86::VPMOVZXBQrm,         0 },
599     { X86::VPMOVZXBWrr,     X86::VPMOVZXBWrm,         0 },
600     { X86::VPMOVZXDQrr,     X86::VPMOVZXDQrm,         0 },
601     { X86::VPMOVZXWDrr,     X86::VPMOVZXWDrm,         0 },
602     { X86::VPMOVZXWQrr,     X86::VPMOVZXWQrm,         0 },
603     { X86::VPSHUFDri,       X86::VPSHUFDmi,           0 },
604     { X86::VPSHUFHWri,      X86::VPSHUFHWmi,          0 },
605     { X86::VPSHUFLWri,      X86::VPSHUFLWmi,          0 },
606     { X86::VPTESTrr,        X86::VPTESTrm,            0 },
607     { X86::VRCPPSr,         X86::VRCPPSm,             0 },
608     { X86::VRCPPSr_Int,     X86::VRCPPSm_Int,         0 },
609     { X86::VROUNDPDr,       X86::VROUNDPDm,           0 },
610     { X86::VROUNDPSr,       X86::VROUNDPSm,           0 },
611     { X86::VRSQRTPSr,       X86::VRSQRTPSm,           0 },
612     { X86::VRSQRTPSr_Int,   X86::VRSQRTPSm_Int,       0 },
613     { X86::VSQRTPDr,        X86::VSQRTPDm,            0 },
614     { X86::VSQRTPSr,        X86::VSQRTPSm,            0 },
615     { X86::VTESTPDrr,       X86::VTESTPDrm,           0 },
616     { X86::VTESTPSrr,       X86::VTESTPSrm,           0 },
617     { X86::VUCOMISDrr,      X86::VUCOMISDrm,          0 },
618     { X86::VUCOMISSrr,      X86::VUCOMISSrm,          0 },
619     { X86::VBROADCASTSSrr,  X86::VBROADCASTSSrm,      TB_NO_REVERSE },
621     // AVX 256-bit foldable instructions
622     { X86::VCVTDQ2PDYrr,    X86::VCVTDQ2PDYrm,        0 },
623     { X86::VCVTDQ2PSYrr,    X86::VCVTDQ2PSYrm,        0 },
624     { X86::VCVTPD2DQYrr,    X86::VCVTPD2DQYrm,        0 },
625     { X86::VCVTPD2PSYrr,    X86::VCVTPD2PSYrm,        0 },
626     { X86::VCVTPS2DQYrr,    X86::VCVTPS2DQYrm,        0 },
627     { X86::VCVTPS2PDYrr,    X86::VCVTPS2PDYrm,        0 },
628     { X86::VCVTTPD2DQYrr,   X86::VCVTTPD2DQYrm,       0 },
629     { X86::VCVTTPS2DQYrr,   X86::VCVTTPS2DQYrm,       0 },
630     { X86::VMOVAPDYrr,      X86::VMOVAPDYrm,          TB_ALIGN_32 },
631     { X86::VMOVAPSYrr,      X86::VMOVAPSYrm,          TB_ALIGN_32 },
632     { X86::VMOVDQAYrr,      X86::VMOVDQAYrm,          TB_ALIGN_32 },
633     { X86::VMOVUPDYrr,      X86::VMOVUPDYrm,          0 },
634     { X86::VMOVUPSYrr,      X86::VMOVUPSYrm,          0 },
635     { X86::VPERMILPDYri,    X86::VPERMILPDYmi,        0 },
636     { X86::VPERMILPSYri,    X86::VPERMILPSYmi,        0 },
637     { X86::VRCPPSYr,        X86::VRCPPSYm,            0 },
638     { X86::VRCPPSYr_Int,    X86::VRCPPSYm_Int,        0 },
639     { X86::VROUNDYPDr,      X86::VROUNDYPDm,          0 },
640     { X86::VROUNDYPSr,      X86::VROUNDYPSm,          0 },
641     { X86::VRSQRTPSYr,      X86::VRSQRTPSYm,          0 },
642     { X86::VRSQRTPSYr_Int,  X86::VRSQRTPSYm_Int,      0 },
643     { X86::VSQRTPDYr,       X86::VSQRTPDYm,           0 },
644     { X86::VSQRTPSYr,       X86::VSQRTPSYm,           0 },
645     { X86::VTESTPDYrr,      X86::VTESTPDYrm,          0 },
646     { X86::VTESTPSYrr,      X86::VTESTPSYrm,          0 },
647     { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm,     TB_NO_REVERSE },
648     { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm,     TB_NO_REVERSE },
650     // AVX2 foldable instructions
651     { X86::VPABSBrr256,     X86::VPABSBrm256,         0 },
652     { X86::VPABSDrr256,     X86::VPABSDrm256,         0 },
653     { X86::VPABSWrr256,     X86::VPABSWrm256,         0 },
654     { X86::VPSHUFDYri,      X86::VPSHUFDYmi,          0 },
655     { X86::VPSHUFHWYri,     X86::VPSHUFHWYmi,         0 },
656     { X86::VPSHUFLWYri,     X86::VPSHUFLWYmi,         0 },
658     // BMI/BMI2/LZCNT/POPCNT/TBM foldable instructions
659     { X86::BEXTR32rr,       X86::BEXTR32rm,           0 },
660     { X86::BEXTR64rr,       X86::BEXTR64rm,           0 },
661     { X86::BEXTRI32ri,      X86::BEXTRI32mi,          0 },
662     { X86::BEXTRI64ri,      X86::BEXTRI64mi,          0 },
663     { X86::BLCFILL32rr,     X86::BLCFILL32rm,         0 },
664     { X86::BLCFILL64rr,     X86::BLCFILL64rm,         0 },
665     { X86::BLCI32rr,        X86::BLCI32rm,            0 },
666     { X86::BLCI64rr,        X86::BLCI64rm,            0 },
667     { X86::BLCIC32rr,       X86::BLCIC32rm,           0 },
668     { X86::BLCIC64rr,       X86::BLCIC64rm,           0 },
669     { X86::BLCMSK32rr,      X86::BLCMSK32rm,          0 },
670     { X86::BLCMSK64rr,      X86::BLCMSK64rm,          0 },
671     { X86::BLCS32rr,        X86::BLCS32rm,            0 },
672     { X86::BLCS64rr,        X86::BLCS64rm,            0 },
673     { X86::BLSFILL32rr,     X86::BLSFILL32rm,         0 },
674     { X86::BLSFILL64rr,     X86::BLSFILL64rm,         0 },
675     { X86::BLSI32rr,        X86::BLSI32rm,            0 },
676     { X86::BLSI64rr,        X86::BLSI64rm,            0 },
677     { X86::BLSIC32rr,       X86::BLSIC32rm,           0 },
678     { X86::BLSIC64rr,       X86::BLSIC64rm,           0 },
679     { X86::BLSMSK32rr,      X86::BLSMSK32rm,          0 },
680     { X86::BLSMSK64rr,      X86::BLSMSK64rm,          0 },
681     { X86::BLSR32rr,        X86::BLSR32rm,            0 },
682     { X86::BLSR64rr,        X86::BLSR64rm,            0 },
683     { X86::BZHI32rr,        X86::BZHI32rm,            0 },
684     { X86::BZHI64rr,        X86::BZHI64rm,            0 },
685     { X86::LZCNT16rr,       X86::LZCNT16rm,           0 },
686     { X86::LZCNT32rr,       X86::LZCNT32rm,           0 },
687     { X86::LZCNT64rr,       X86::LZCNT64rm,           0 },
688     { X86::POPCNT16rr,      X86::POPCNT16rm,          0 },
689     { X86::POPCNT32rr,      X86::POPCNT32rm,          0 },
690     { X86::POPCNT64rr,      X86::POPCNT64rm,          0 },
691     { X86::RORX32ri,        X86::RORX32mi,            0 },
692     { X86::RORX64ri,        X86::RORX64mi,            0 },
693     { X86::SARX32rr,        X86::SARX32rm,            0 },
694     { X86::SARX64rr,        X86::SARX64rm,            0 },
695     { X86::SHRX32rr,        X86::SHRX32rm,            0 },
696     { X86::SHRX64rr,        X86::SHRX64rm,            0 },
697     { X86::SHLX32rr,        X86::SHLX32rm,            0 },
698     { X86::SHLX64rr,        X86::SHLX64rm,            0 },
699     { X86::T1MSKC32rr,      X86::T1MSKC32rm,          0 },
700     { X86::T1MSKC64rr,      X86::T1MSKC64rm,          0 },
701     { X86::TZCNT16rr,       X86::TZCNT16rm,           0 },
702     { X86::TZCNT32rr,       X86::TZCNT32rm,           0 },
703     { X86::TZCNT64rr,       X86::TZCNT64rm,           0 },
704     { X86::TZMSK32rr,       X86::TZMSK32rm,           0 },
705     { X86::TZMSK64rr,       X86::TZMSK64rm,           0 },
707     // AVX-512 foldable instructions
708     { X86::VMOV64toPQIZrr,  X86::VMOVQI2PQIZrm,       0 },
709     { X86::VMOVDI2SSZrr,    X86::VMOVDI2SSZrm,        0 },
710     { X86::VMOVAPDZrr,      X86::VMOVAPDZrm,          TB_ALIGN_64 },
711     { X86::VMOVAPSZrr,      X86::VMOVAPSZrm,          TB_ALIGN_64 },
712     { X86::VMOVDQA32Zrr,    X86::VMOVDQA32Zrm,        TB_ALIGN_64 },
713     { X86::VMOVDQA64Zrr,    X86::VMOVDQA64Zrm,        TB_ALIGN_64 },
714     { X86::VMOVDQU8Zrr,     X86::VMOVDQU8Zrm,         0 },
715     { X86::VMOVDQU16Zrr,    X86::VMOVDQU16Zrm,        0 },
716     { X86::VMOVDQU32Zrr,    X86::VMOVDQU32Zrm,        0 },
717     { X86::VMOVDQU64Zrr,    X86::VMOVDQU64Zrm,        0 },
718     { X86::VMOVUPDZrr,      X86::VMOVUPDZrm,          0 },
719     { X86::VMOVUPSZrr,      X86::VMOVUPSZrm,          0 },
720     { X86::VPABSDZrr,       X86::VPABSDZrm,           0 },
721     { X86::VPABSQZrr,       X86::VPABSQZrm,           0 },
722     { X86::VBROADCASTSSZr,  X86::VBROADCASTSSZm,      TB_NO_REVERSE },
723     { X86::VBROADCASTSDZr,  X86::VBROADCASTSDZm,      TB_NO_REVERSE },
724     // AVX-512 foldable instructions (256-bit versions)
725     { X86::VMOVAPDZ256rr,      X86::VMOVAPDZ256rm,          TB_ALIGN_32 },
726     { X86::VMOVAPSZ256rr,      X86::VMOVAPSZ256rm,          TB_ALIGN_32 },
727     { X86::VMOVDQA32Z256rr,    X86::VMOVDQA32Z256rm,        TB_ALIGN_32 },
728     { X86::VMOVDQA64Z256rr,    X86::VMOVDQA64Z256rm,        TB_ALIGN_32 },
729     { X86::VMOVDQU8Z256rr,     X86::VMOVDQU8Z256rm,         0 },
730     { X86::VMOVDQU16Z256rr,    X86::VMOVDQU16Z256rm,        0 },
731     { X86::VMOVDQU32Z256rr,    X86::VMOVDQU32Z256rm,        0 },
732     { X86::VMOVDQU64Z256rr,    X86::VMOVDQU64Z256rm,        0 },
733     { X86::VMOVUPDZ256rr,      X86::VMOVUPDZ256rm,          0 },
734     { X86::VMOVUPSZ256rr,      X86::VMOVUPSZ256rm,          0 },
735     { X86::VBROADCASTSSZ256r,  X86::VBROADCASTSSZ256m,      TB_NO_REVERSE },
736     { X86::VBROADCASTSDZ256r,  X86::VBROADCASTSDZ256m,      TB_NO_REVERSE },
737     // AVX-512 foldable instructions (256-bit versions)
738     { X86::VMOVAPDZ128rr,      X86::VMOVAPDZ128rm,          TB_ALIGN_16 },
739     { X86::VMOVAPSZ128rr,      X86::VMOVAPSZ128rm,          TB_ALIGN_16 },
740     { X86::VMOVDQA32Z128rr,    X86::VMOVDQA32Z128rm,        TB_ALIGN_16 },
741     { X86::VMOVDQA64Z128rr,    X86::VMOVDQA64Z128rm,        TB_ALIGN_16 },
742     { X86::VMOVDQU8Z128rr,     X86::VMOVDQU8Z128rm,         0 },
743     { X86::VMOVDQU16Z128rr,    X86::VMOVDQU16Z128rm,        0 },
744     { X86::VMOVDQU32Z128rr,    X86::VMOVDQU32Z128rm,        0 },
745     { X86::VMOVDQU64Z128rr,    X86::VMOVDQU64Z128rm,        0 },
746     { X86::VMOVUPDZ128rr,      X86::VMOVUPDZ128rm,          0 },
747     { X86::VMOVUPSZ128rr,      X86::VMOVUPSZ128rm,          0 },
748     { X86::VBROADCASTSSZ128r,  X86::VBROADCASTSSZ128m,      TB_NO_REVERSE },
749     // F16C foldable instructions
750     { X86::VCVTPH2PSrr,        X86::VCVTPH2PSrm,            0 },
751     { X86::VCVTPH2PSYrr,       X86::VCVTPH2PSYrm,           0 },
752     // AES foldable instructions
753     { X86::AESIMCrr,              X86::AESIMCrm,              TB_ALIGN_16 },
754     { X86::AESKEYGENASSIST128rr,  X86::AESKEYGENASSIST128rm,  TB_ALIGN_16 },
755     { X86::VAESIMCrr,             X86::VAESIMCrm,             TB_ALIGN_16 },
756     { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, TB_ALIGN_16 }
757   };
759   for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
760     unsigned RegOp = OpTbl1[i].RegOp;
761     unsigned MemOp = OpTbl1[i].MemOp;
762     unsigned Flags = OpTbl1[i].Flags;
763     AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
764                   RegOp, MemOp,
765                   // Index 1, folded load
766                   Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
767   }
769   static const X86OpTblEntry OpTbl2[] = {
770     { X86::ADC32rr,         X86::ADC32rm,       0 },
771     { X86::ADC64rr,         X86::ADC64rm,       0 },
772     { X86::ADD16rr,         X86::ADD16rm,       0 },
773     { X86::ADD16rr_DB,      X86::ADD16rm,       TB_NO_REVERSE },
774     { X86::ADD32rr,         X86::ADD32rm,       0 },
775     { X86::ADD32rr_DB,      X86::ADD32rm,       TB_NO_REVERSE },
776     { X86::ADD64rr,         X86::ADD64rm,       0 },
777     { X86::ADD64rr_DB,      X86::ADD64rm,       TB_NO_REVERSE },
778     { X86::ADD8rr,          X86::ADD8rm,        0 },
779     { X86::ADDPDrr,         X86::ADDPDrm,       TB_ALIGN_16 },
780     { X86::ADDPSrr,         X86::ADDPSrm,       TB_ALIGN_16 },
781     { X86::ADDSDrr,         X86::ADDSDrm,       0 },
782     { X86::ADDSDrr_Int,     X86::ADDSDrm_Int,   0 },
783     { X86::ADDSSrr,         X86::ADDSSrm,       0 },
784     { X86::ADDSSrr_Int,     X86::ADDSSrm_Int,   0 },
785     { X86::ADDSUBPDrr,      X86::ADDSUBPDrm,    TB_ALIGN_16 },
786     { X86::ADDSUBPSrr,      X86::ADDSUBPSrm,    TB_ALIGN_16 },
787     { X86::AND16rr,         X86::AND16rm,       0 },
788     { X86::AND32rr,         X86::AND32rm,       0 },
789     { X86::AND64rr,         X86::AND64rm,       0 },
790     { X86::AND8rr,          X86::AND8rm,        0 },
791     { X86::ANDNPDrr,        X86::ANDNPDrm,      TB_ALIGN_16 },
792     { X86::ANDNPSrr,        X86::ANDNPSrm,      TB_ALIGN_16 },
793     { X86::ANDPDrr,         X86::ANDPDrm,       TB_ALIGN_16 },
794     { X86::ANDPSrr,         X86::ANDPSrm,       TB_ALIGN_16 },
795     { X86::BLENDPDrri,      X86::BLENDPDrmi,    TB_ALIGN_16 },
796     { X86::BLENDPSrri,      X86::BLENDPSrmi,    TB_ALIGN_16 },
797     { X86::BLENDVPDrr0,     X86::BLENDVPDrm0,   TB_ALIGN_16 },
798     { X86::BLENDVPSrr0,     X86::BLENDVPSrm0,   TB_ALIGN_16 },
799     { X86::CMOVA16rr,       X86::CMOVA16rm,     0 },
800     { X86::CMOVA32rr,       X86::CMOVA32rm,     0 },
801     { X86::CMOVA64rr,       X86::CMOVA64rm,     0 },
802     { X86::CMOVAE16rr,      X86::CMOVAE16rm,    0 },
803     { X86::CMOVAE32rr,      X86::CMOVAE32rm,    0 },
804     { X86::CMOVAE64rr,      X86::CMOVAE64rm,    0 },
805     { X86::CMOVB16rr,       X86::CMOVB16rm,     0 },
806     { X86::CMOVB32rr,       X86::CMOVB32rm,     0 },
807     { X86::CMOVB64rr,       X86::CMOVB64rm,     0 },
808     { X86::CMOVBE16rr,      X86::CMOVBE16rm,    0 },
809     { X86::CMOVBE32rr,      X86::CMOVBE32rm,    0 },
810     { X86::CMOVBE64rr,      X86::CMOVBE64rm,    0 },
811     { X86::CMOVE16rr,       X86::CMOVE16rm,     0 },
812     { X86::CMOVE32rr,       X86::CMOVE32rm,     0 },
813     { X86::CMOVE64rr,       X86::CMOVE64rm,     0 },
814     { X86::CMOVG16rr,       X86::CMOVG16rm,     0 },
815     { X86::CMOVG32rr,       X86::CMOVG32rm,     0 },
816     { X86::CMOVG64rr,       X86::CMOVG64rm,     0 },
817     { X86::CMOVGE16rr,      X86::CMOVGE16rm,    0 },
818     { X86::CMOVGE32rr,      X86::CMOVGE32rm,    0 },
819     { X86::CMOVGE64rr,      X86::CMOVGE64rm,    0 },
820     { X86::CMOVL16rr,       X86::CMOVL16rm,     0 },
821     { X86::CMOVL32rr,       X86::CMOVL32rm,     0 },
822     { X86::CMOVL64rr,       X86::CMOVL64rm,     0 },
823     { X86::CMOVLE16rr,      X86::CMOVLE16rm,    0 },
824     { X86::CMOVLE32rr,      X86::CMOVLE32rm,    0 },
825     { X86::CMOVLE64rr,      X86::CMOVLE64rm,    0 },
826     { X86::CMOVNE16rr,      X86::CMOVNE16rm,    0 },
827     { X86::CMOVNE32rr,      X86::CMOVNE32rm,    0 },
828     { X86::CMOVNE64rr,      X86::CMOVNE64rm,    0 },
829     { X86::CMOVNO16rr,      X86::CMOVNO16rm,    0 },
830     { X86::CMOVNO32rr,      X86::CMOVNO32rm,    0 },
831     { X86::CMOVNO64rr,      X86::CMOVNO64rm,    0 },
832     { X86::CMOVNP16rr,      X86::CMOVNP16rm,    0 },
833     { X86::CMOVNP32rr,      X86::CMOVNP32rm,    0 },
834     { X86::CMOVNP64rr,      X86::CMOVNP64rm,    0 },
835     { X86::CMOVNS16rr,      X86::CMOVNS16rm,    0 },
836     { X86::CMOVNS32rr,      X86::CMOVNS32rm,    0 },
837     { X86::CMOVNS64rr,      X86::CMOVNS64rm,    0 },
838     { X86::CMOVO16rr,       X86::CMOVO16rm,     0 },
839     { X86::CMOVO32rr,       X86::CMOVO32rm,     0 },
840     { X86::CMOVO64rr,       X86::CMOVO64rm,     0 },
841     { X86::CMOVP16rr,       X86::CMOVP16rm,     0 },
842     { X86::CMOVP32rr,       X86::CMOVP32rm,     0 },
843     { X86::CMOVP64rr,       X86::CMOVP64rm,     0 },
844     { X86::CMOVS16rr,       X86::CMOVS16rm,     0 },
845     { X86::CMOVS32rr,       X86::CMOVS32rm,     0 },
846     { X86::CMOVS64rr,       X86::CMOVS64rm,     0 },
847     { X86::CMPPDrri,        X86::CMPPDrmi,      TB_ALIGN_16 },
848     { X86::CMPPSrri,        X86::CMPPSrmi,      TB_ALIGN_16 },
849     { X86::CMPSDrr,         X86::CMPSDrm,       0 },
850     { X86::CMPSSrr,         X86::CMPSSrm,       0 },
851     { X86::DIVPDrr,         X86::DIVPDrm,       TB_ALIGN_16 },
852     { X86::DIVPSrr,         X86::DIVPSrm,       TB_ALIGN_16 },
853     { X86::DIVSDrr,         X86::DIVSDrm,       0 },
854     { X86::DIVSDrr_Int,     X86::DIVSDrm_Int,   0 },
855     { X86::DIVSSrr,         X86::DIVSSrm,       0 },
856     { X86::DIVSSrr_Int,     X86::DIVSSrm_Int,   0 },
857     { X86::DPPDrri,         X86::DPPDrmi,       TB_ALIGN_16 },
858     { X86::DPPSrri,         X86::DPPSrmi,       TB_ALIGN_16 },
859     { X86::FsANDNPDrr,      X86::FsANDNPDrm,    TB_ALIGN_16 },
860     { X86::FsANDNPSrr,      X86::FsANDNPSrm,    TB_ALIGN_16 },
861     { X86::FsANDPDrr,       X86::FsANDPDrm,     TB_ALIGN_16 },
862     { X86::FsANDPSrr,       X86::FsANDPSrm,     TB_ALIGN_16 },
863     { X86::FsORPDrr,        X86::FsORPDrm,      TB_ALIGN_16 },
864     { X86::FsORPSrr,        X86::FsORPSrm,      TB_ALIGN_16 },
865     { X86::FsXORPDrr,       X86::FsXORPDrm,     TB_ALIGN_16 },
866     { X86::FsXORPSrr,       X86::FsXORPSrm,     TB_ALIGN_16 },
867     { X86::HADDPDrr,        X86::HADDPDrm,      TB_ALIGN_16 },
868     { X86::HADDPSrr,        X86::HADDPSrm,      TB_ALIGN_16 },
869     { X86::HSUBPDrr,        X86::HSUBPDrm,      TB_ALIGN_16 },
870     { X86::HSUBPSrr,        X86::HSUBPSrm,      TB_ALIGN_16 },
871     { X86::IMUL16rr,        X86::IMUL16rm,      0 },
872     { X86::IMUL32rr,        X86::IMUL32rm,      0 },
873     { X86::IMUL64rr,        X86::IMUL64rm,      0 },
874     { X86::Int_CMPSDrr,     X86::Int_CMPSDrm,   0 },
875     { X86::Int_CMPSSrr,     X86::Int_CMPSSrm,   0 },
876     { X86::Int_CVTSD2SSrr,  X86::Int_CVTSD2SSrm,      0 },
877     { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm,    0 },
878     { X86::Int_CVTSI2SDrr,  X86::Int_CVTSI2SDrm,      0 },
879     { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm,    0 },
880     { X86::Int_CVTSI2SSrr,  X86::Int_CVTSI2SSrm,      0 },
881     { X86::Int_CVTSS2SDrr,  X86::Int_CVTSS2SDrm,      0 },
882     { X86::MAXPDrr,         X86::MAXPDrm,       TB_ALIGN_16 },
883     { X86::MAXPSrr,         X86::MAXPSrm,       TB_ALIGN_16 },
884     { X86::MAXSDrr,         X86::MAXSDrm,       0 },
885     { X86::MAXSDrr_Int,     X86::MAXSDrm_Int,   0 },
886     { X86::MAXSSrr,         X86::MAXSSrm,       0 },
887     { X86::MAXSSrr_Int,     X86::MAXSSrm_Int,   0 },
888     { X86::MINPDrr,         X86::MINPDrm,       TB_ALIGN_16 },
889     { X86::MINPSrr,         X86::MINPSrm,       TB_ALIGN_16 },
890     { X86::MINSDrr,         X86::MINSDrm,       0 },
891     { X86::MINSDrr_Int,     X86::MINSDrm_Int,   0 },
892     { X86::MINSSrr,         X86::MINSSrm,       0 },
893     { X86::MINSSrr_Int,     X86::MINSSrm_Int,   0 },
894     { X86::MPSADBWrri,      X86::MPSADBWrmi,    TB_ALIGN_16 },
895     { X86::MULPDrr,         X86::MULPDrm,       TB_ALIGN_16 },
896     { X86::MULPSrr,         X86::MULPSrm,       TB_ALIGN_16 },
897     { X86::MULSDrr,         X86::MULSDrm,       0 },
898     { X86::MULSDrr_Int,     X86::MULSDrm_Int,   0 },
899     { X86::MULSSrr,         X86::MULSSrm,       0 },
900     { X86::MULSSrr_Int,     X86::MULSSrm_Int,   0 },
901     { X86::OR16rr,          X86::OR16rm,        0 },
902     { X86::OR32rr,          X86::OR32rm,        0 },
903     { X86::OR64rr,          X86::OR64rm,        0 },
904     { X86::OR8rr,           X86::OR8rm,         0 },
905     { X86::ORPDrr,          X86::ORPDrm,        TB_ALIGN_16 },
906     { X86::ORPSrr,          X86::ORPSrm,        TB_ALIGN_16 },
907     { X86::PACKSSDWrr,      X86::PACKSSDWrm,    TB_ALIGN_16 },
908     { X86::PACKSSWBrr,      X86::PACKSSWBrm,    TB_ALIGN_16 },
909     { X86::PACKUSDWrr,      X86::PACKUSDWrm,    TB_ALIGN_16 },
910     { X86::PACKUSWBrr,      X86::PACKUSWBrm,    TB_ALIGN_16 },
911     { X86::PADDBrr,         X86::PADDBrm,       TB_ALIGN_16 },
912     { X86::PADDDrr,         X86::PADDDrm,       TB_ALIGN_16 },
913     { X86::PADDQrr,         X86::PADDQrm,       TB_ALIGN_16 },
914     { X86::PADDSBrr,        X86::PADDSBrm,      TB_ALIGN_16 },
915     { X86::PADDSWrr,        X86::PADDSWrm,      TB_ALIGN_16 },
916     { X86::PADDUSBrr,       X86::PADDUSBrm,     TB_ALIGN_16 },
917     { X86::PADDUSWrr,       X86::PADDUSWrm,     TB_ALIGN_16 },
918     { X86::PADDWrr,         X86::PADDWrm,       TB_ALIGN_16 },
919     { X86::PALIGNR128rr,    X86::PALIGNR128rm,  TB_ALIGN_16 },
920     { X86::PANDNrr,         X86::PANDNrm,       TB_ALIGN_16 },
921     { X86::PANDrr,          X86::PANDrm,        TB_ALIGN_16 },
922     { X86::PAVGBrr,         X86::PAVGBrm,       TB_ALIGN_16 },
923     { X86::PAVGWrr,         X86::PAVGWrm,       TB_ALIGN_16 },
924     { X86::PBLENDVBrr0,     X86::PBLENDVBrm0,   TB_ALIGN_16 },
925     { X86::PBLENDWrri,      X86::PBLENDWrmi,    TB_ALIGN_16 },
926     { X86::PCLMULQDQrr,     X86::PCLMULQDQrm,   TB_ALIGN_16 },
927     { X86::PCMPEQBrr,       X86::PCMPEQBrm,     TB_ALIGN_16 },
928     { X86::PCMPEQDrr,       X86::PCMPEQDrm,     TB_ALIGN_16 },
929     { X86::PCMPEQQrr,       X86::PCMPEQQrm,     TB_ALIGN_16 },
930     { X86::PCMPEQWrr,       X86::PCMPEQWrm,     TB_ALIGN_16 },
931     { X86::PCMPGTBrr,       X86::PCMPGTBrm,     TB_ALIGN_16 },
932     { X86::PCMPGTDrr,       X86::PCMPGTDrm,     TB_ALIGN_16 },
933     { X86::PCMPGTQrr,       X86::PCMPGTQrm,     TB_ALIGN_16 },
934     { X86::PCMPGTWrr,       X86::PCMPGTWrm,     TB_ALIGN_16 },
935     { X86::PHADDDrr,        X86::PHADDDrm,      TB_ALIGN_16 },
936     { X86::PHADDWrr,        X86::PHADDWrm,      TB_ALIGN_16 },
937     { X86::PHADDSWrr128,    X86::PHADDSWrm128,  TB_ALIGN_16 },
938     { X86::PHSUBDrr,        X86::PHSUBDrm,      TB_ALIGN_16 },
939     { X86::PHSUBSWrr128,    X86::PHSUBSWrm128,  TB_ALIGN_16 },
940     { X86::PHSUBWrr,        X86::PHSUBWrm,      TB_ALIGN_16 },
941     { X86::PINSRBrr,        X86::PINSRBrm,      0 },
942     { X86::PINSRDrr,        X86::PINSRDrm,      0 },
943     { X86::PINSRQrr,        X86::PINSRQrm,      0 },
944     { X86::PINSRWrri,       X86::PINSRWrmi,     0 },
945     { X86::PMADDUBSWrr128,  X86::PMADDUBSWrm128, TB_ALIGN_16 },
946     { X86::PMADDWDrr,       X86::PMADDWDrm,     TB_ALIGN_16 },
947     { X86::PMAXSWrr,        X86::PMAXSWrm,      TB_ALIGN_16 },
948     { X86::PMAXUBrr,        X86::PMAXUBrm,      TB_ALIGN_16 },
949     { X86::PMINSWrr,        X86::PMINSWrm,      TB_ALIGN_16 },
950     { X86::PMINUBrr,        X86::PMINUBrm,      TB_ALIGN_16 },
951     { X86::PMINSBrr,        X86::PMINSBrm,      TB_ALIGN_16 },
952     { X86::PMINSDrr,        X86::PMINSDrm,      TB_ALIGN_16 },
953     { X86::PMINUDrr,        X86::PMINUDrm,      TB_ALIGN_16 },
954     { X86::PMINUWrr,        X86::PMINUWrm,      TB_ALIGN_16 },
955     { X86::PMAXSBrr,        X86::PMAXSBrm,      TB_ALIGN_16 },
956     { X86::PMAXSDrr,        X86::PMAXSDrm,      TB_ALIGN_16 },
957     { X86::PMAXUDrr,        X86::PMAXUDrm,      TB_ALIGN_16 },
958     { X86::PMAXUWrr,        X86::PMAXUWrm,      TB_ALIGN_16 },
959     { X86::PMULDQrr,        X86::PMULDQrm,      TB_ALIGN_16 },
960     { X86::PMULHRSWrr128,   X86::PMULHRSWrm128, TB_ALIGN_16 },
961     { X86::PMULHUWrr,       X86::PMULHUWrm,     TB_ALIGN_16 },
962     { X86::PMULHWrr,        X86::PMULHWrm,      TB_ALIGN_16 },
963     { X86::PMULLDrr,        X86::PMULLDrm,      TB_ALIGN_16 },
964     { X86::PMULLWrr,        X86::PMULLWrm,      TB_ALIGN_16 },
965     { X86::PMULUDQrr,       X86::PMULUDQrm,     TB_ALIGN_16 },
966     { X86::PORrr,           X86::PORrm,         TB_ALIGN_16 },
967     { X86::PSADBWrr,        X86::PSADBWrm,      TB_ALIGN_16 },
968     { X86::PSHUFBrr,        X86::PSHUFBrm,      TB_ALIGN_16 },
969     { X86::PSIGNBrr,        X86::PSIGNBrm,      TB_ALIGN_16 },
970     { X86::PSIGNWrr,        X86::PSIGNWrm,      TB_ALIGN_16 },
971     { X86::PSIGNDrr,        X86::PSIGNDrm,      TB_ALIGN_16 },
972     { X86::PSLLDrr,         X86::PSLLDrm,       TB_ALIGN_16 },
973     { X86::PSLLQrr,         X86::PSLLQrm,       TB_ALIGN_16 },
974     { X86::PSLLWrr,         X86::PSLLWrm,       TB_ALIGN_16 },
975     { X86::PSRADrr,         X86::PSRADrm,       TB_ALIGN_16 },
976     { X86::PSRAWrr,         X86::PSRAWrm,       TB_ALIGN_16 },
977     { X86::PSRLDrr,         X86::PSRLDrm,       TB_ALIGN_16 },
978     { X86::PSRLQrr,         X86::PSRLQrm,       TB_ALIGN_16 },
979     { X86::PSRLWrr,         X86::PSRLWrm,       TB_ALIGN_16 },
980     { X86::PSUBBrr,         X86::PSUBBrm,       TB_ALIGN_16 },
981     { X86::PSUBDrr,         X86::PSUBDrm,       TB_ALIGN_16 },
982     { X86::PSUBQrr,         X86::PSUBQrm,       TB_ALIGN_16 },
983     { X86::PSUBSBrr,        X86::PSUBSBrm,      TB_ALIGN_16 },
984     { X86::PSUBSWrr,        X86::PSUBSWrm,      TB_ALIGN_16 },
985     { X86::PSUBUSBrr,       X86::PSUBUSBrm,     TB_ALIGN_16 },
986     { X86::PSUBUSWrr,       X86::PSUBUSWrm,     TB_ALIGN_16 },
987     { X86::PSUBWrr,         X86::PSUBWrm,       TB_ALIGN_16 },
988     { X86::PUNPCKHBWrr,     X86::PUNPCKHBWrm,   TB_ALIGN_16 },
989     { X86::PUNPCKHDQrr,     X86::PUNPCKHDQrm,   TB_ALIGN_16 },
990     { X86::PUNPCKHQDQrr,    X86::PUNPCKHQDQrm,  TB_ALIGN_16 },
991     { X86::PUNPCKHWDrr,     X86::PUNPCKHWDrm,   TB_ALIGN_16 },
992     { X86::PUNPCKLBWrr,     X86::PUNPCKLBWrm,   TB_ALIGN_16 },
993     { X86::PUNPCKLDQrr,     X86::PUNPCKLDQrm,   TB_ALIGN_16 },
994     { X86::PUNPCKLQDQrr,    X86::PUNPCKLQDQrm,  TB_ALIGN_16 },
995     { X86::PUNPCKLWDrr,     X86::PUNPCKLWDrm,   TB_ALIGN_16 },
996     { X86::PXORrr,          X86::PXORrm,        TB_ALIGN_16 },
997     { X86::SBB32rr,         X86::SBB32rm,       0 },
998     { X86::SBB64rr,         X86::SBB64rm,       0 },
999     { X86::SHUFPDrri,       X86::SHUFPDrmi,     TB_ALIGN_16 },
1000     { X86::SHUFPSrri,       X86::SHUFPSrmi,     TB_ALIGN_16 },
1001     { X86::SUB16rr,         X86::SUB16rm,       0 },
1002     { X86::SUB32rr,         X86::SUB32rm,       0 },
1003     { X86::SUB64rr,         X86::SUB64rm,       0 },
1004     { X86::SUB8rr,          X86::SUB8rm,        0 },
1005     { X86::SUBPDrr,         X86::SUBPDrm,       TB_ALIGN_16 },
1006     { X86::SUBPSrr,         X86::SUBPSrm,       TB_ALIGN_16 },
1007     { X86::SUBSDrr,         X86::SUBSDrm,       0 },
1008     { X86::SUBSDrr_Int,     X86::SUBSDrm_Int,   0 },
1009     { X86::SUBSSrr,         X86::SUBSSrm,       0 },
1010     { X86::SUBSSrr_Int,     X86::SUBSSrm_Int,   0 },
1011     // FIXME: TEST*rr -> swapped operand of TEST*mr.
1012     { X86::UNPCKHPDrr,      X86::UNPCKHPDrm,    TB_ALIGN_16 },
1013     { X86::UNPCKHPSrr,      X86::UNPCKHPSrm,    TB_ALIGN_16 },
1014     { X86::UNPCKLPDrr,      X86::UNPCKLPDrm,    TB_ALIGN_16 },
1015     { X86::UNPCKLPSrr,      X86::UNPCKLPSrm,    TB_ALIGN_16 },
1016     { X86::XOR16rr,         X86::XOR16rm,       0 },
1017     { X86::XOR32rr,         X86::XOR32rm,       0 },
1018     { X86::XOR64rr,         X86::XOR64rm,       0 },
1019     { X86::XOR8rr,          X86::XOR8rm,        0 },
1020     { X86::XORPDrr,         X86::XORPDrm,       TB_ALIGN_16 },
1021     { X86::XORPSrr,         X86::XORPSrm,       TB_ALIGN_16 },
1022     // AVX 128-bit versions of foldable instructions
1023     { X86::VCVTSD2SSrr,       X86::VCVTSD2SSrm,        0 },
1024     { X86::Int_VCVTSD2SSrr,   X86::Int_VCVTSD2SSrm,    0 },
1025     { X86::VCVTSI2SD64rr,     X86::VCVTSI2SD64rm,      0 },
1026     { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm,  0 },
1027     { X86::VCVTSI2SDrr,       X86::VCVTSI2SDrm,        0 },
1028     { X86::Int_VCVTSI2SDrr,   X86::Int_VCVTSI2SDrm,    0 },
1029     { X86::VCVTSI2SS64rr,     X86::VCVTSI2SS64rm,      0 },
1030     { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm,  0 },
1031     { X86::VCVTSI2SSrr,       X86::VCVTSI2SSrm,        0 },
1032     { X86::Int_VCVTSI2SSrr,   X86::Int_VCVTSI2SSrm,    0 },
1033     { X86::VCVTSS2SDrr,       X86::VCVTSS2SDrm,        0 },
1034     { X86::Int_VCVTSS2SDrr,   X86::Int_VCVTSS2SDrm,    0 },
1035     { X86::VRCPSSr,           X86::VRCPSSm,            0 },
1036     { X86::VRSQRTSSr,         X86::VRSQRTSSm,          0 },
1037     { X86::VSQRTSDr,          X86::VSQRTSDm,           0 },
1038     { X86::VSQRTSSr,          X86::VSQRTSSm,           0 },
1039     { X86::VADDPDrr,          X86::VADDPDrm,           0 },
1040     { X86::VADDPSrr,          X86::VADDPSrm,           0 },
1041     { X86::VADDSDrr,          X86::VADDSDrm,           0 },
1042     { X86::VADDSDrr_Int,      X86::VADDSDrm_Int,       0 },
1043     { X86::VADDSSrr,          X86::VADDSSrm,           0 },
1044     { X86::VADDSSrr_Int,      X86::VADDSSrm_Int,       0 },
1045     { X86::VADDSUBPDrr,       X86::VADDSUBPDrm,        0 },
1046     { X86::VADDSUBPSrr,       X86::VADDSUBPSrm,        0 },
1047     { X86::VANDNPDrr,         X86::VANDNPDrm,          0 },
1048     { X86::VANDNPSrr,         X86::VANDNPSrm,          0 },
1049     { X86::VANDPDrr,          X86::VANDPDrm,           0 },
1050     { X86::VANDPSrr,          X86::VANDPSrm,           0 },
1051     { X86::VBLENDPDrri,       X86::VBLENDPDrmi,        0 },
1052     { X86::VBLENDPSrri,       X86::VBLENDPSrmi,        0 },
1053     { X86::VBLENDVPDrr,       X86::VBLENDVPDrm,        0 },
1054     { X86::VBLENDVPSrr,       X86::VBLENDVPSrm,        0 },
1055     { X86::VCMPPDrri,         X86::VCMPPDrmi,          0 },
1056     { X86::VCMPPSrri,         X86::VCMPPSrmi,          0 },
1057     { X86::VCMPSDrr,          X86::VCMPSDrm,           0 },
1058     { X86::VCMPSSrr,          X86::VCMPSSrm,           0 },
1059     { X86::VDIVPDrr,          X86::VDIVPDrm,           0 },
1060     { X86::VDIVPSrr,          X86::VDIVPSrm,           0 },
1061     { X86::VDIVSDrr,          X86::VDIVSDrm,           0 },
1062     { X86::VDIVSDrr_Int,      X86::VDIVSDrm_Int,       0 },
1063     { X86::VDIVSSrr,          X86::VDIVSSrm,           0 },
1064     { X86::VDIVSSrr_Int,      X86::VDIVSSrm_Int,       0 },
1065     { X86::VDPPDrri,          X86::VDPPDrmi,           0 },
1066     { X86::VDPPSrri,          X86::VDPPSrmi,           0 },
1067     { X86::VFsANDNPDrr,       X86::VFsANDNPDrm,        TB_ALIGN_16 },
1068     { X86::VFsANDNPSrr,       X86::VFsANDNPSrm,        TB_ALIGN_16 },
1069     { X86::VFsANDPDrr,        X86::VFsANDPDrm,         TB_ALIGN_16 },
1070     { X86::VFsANDPSrr,        X86::VFsANDPSrm,         TB_ALIGN_16 },
1071     { X86::VFsORPDrr,         X86::VFsORPDrm,          TB_ALIGN_16 },
1072     { X86::VFsORPSrr,         X86::VFsORPSrm,          TB_ALIGN_16 },
1073     { X86::VFsXORPDrr,        X86::VFsXORPDrm,         TB_ALIGN_16 },
1074     { X86::VFsXORPSrr,        X86::VFsXORPSrm,         TB_ALIGN_16 },
1075     { X86::VHADDPDrr,         X86::VHADDPDrm,          0 },
1076     { X86::VHADDPSrr,         X86::VHADDPSrm,          0 },
1077     { X86::VHSUBPDrr,         X86::VHSUBPDrm,          0 },
1078     { X86::VHSUBPSrr,         X86::VHSUBPSrm,          0 },
1079     { X86::Int_VCMPSDrr,      X86::Int_VCMPSDrm,       0 },
1080     { X86::Int_VCMPSSrr,      X86::Int_VCMPSSrm,       0 },
1081     { X86::VMAXPDrr,          X86::VMAXPDrm,           0 },
1082     { X86::VMAXPSrr,          X86::VMAXPSrm,           0 },
1083     { X86::VMAXSDrr,          X86::VMAXSDrm,           0 },
1084     { X86::VMAXSDrr_Int,      X86::VMAXSDrm_Int,       0 },
1085     { X86::VMAXSSrr,          X86::VMAXSSrm,           0 },
1086     { X86::VMAXSSrr_Int,      X86::VMAXSSrm_Int,       0 },
1087     { X86::VMINPDrr,          X86::VMINPDrm,           0 },
1088     { X86::VMINPSrr,          X86::VMINPSrm,           0 },
1089     { X86::VMINSDrr,          X86::VMINSDrm,           0 },
1090     { X86::VMINSDrr_Int,      X86::VMINSDrm_Int,       0 },
1091     { X86::VMINSSrr,          X86::VMINSSrm,           0 },
1092     { X86::VMINSSrr_Int,      X86::VMINSSrm_Int,       0 },
1093     { X86::VMPSADBWrri,       X86::VMPSADBWrmi,        0 },
1094     { X86::VMULPDrr,          X86::VMULPDrm,           0 },
1095     { X86::VMULPSrr,          X86::VMULPSrm,           0 },
1096     { X86::VMULSDrr,          X86::VMULSDrm,           0 },
1097     { X86::VMULSDrr_Int,      X86::VMULSDrm_Int,       0 },
1098     { X86::VMULSSrr,          X86::VMULSSrm,           0 },
1099     { X86::VMULSSrr_Int,      X86::VMULSSrm_Int,       0 },
1100     { X86::VORPDrr,           X86::VORPDrm,            0 },
1101     { X86::VORPSrr,           X86::VORPSrm,            0 },
1102     { X86::VPACKSSDWrr,       X86::VPACKSSDWrm,        0 },
1103     { X86::VPACKSSWBrr,       X86::VPACKSSWBrm,        0 },
1104     { X86::VPACKUSDWrr,       X86::VPACKUSDWrm,        0 },
1105     { X86::VPACKUSWBrr,       X86::VPACKUSWBrm,        0 },
1106     { X86::VPADDBrr,          X86::VPADDBrm,           0 },
1107     { X86::VPADDDrr,          X86::VPADDDrm,           0 },
1108     { X86::VPADDQrr,          X86::VPADDQrm,           0 },
1109     { X86::VPADDSBrr,         X86::VPADDSBrm,          0 },
1110     { X86::VPADDSWrr,         X86::VPADDSWrm,          0 },
1111     { X86::VPADDUSBrr,        X86::VPADDUSBrm,         0 },
1112     { X86::VPADDUSWrr,        X86::VPADDUSWrm,         0 },
1113     { X86::VPADDWrr,          X86::VPADDWrm,           0 },
1114     { X86::VPALIGNR128rr,     X86::VPALIGNR128rm,      0 },
1115     { X86::VPANDNrr,          X86::VPANDNrm,           0 },
1116     { X86::VPANDrr,           X86::VPANDrm,            0 },
1117     { X86::VPAVGBrr,          X86::VPAVGBrm,           0 },
1118     { X86::VPAVGWrr,          X86::VPAVGWrm,           0 },
1119     { X86::VPBLENDVBrr,       X86::VPBLENDVBrm,        0 },
1120     { X86::VPBLENDWrri,       X86::VPBLENDWrmi,        0 },
1121     { X86::VPCLMULQDQrr,      X86::VPCLMULQDQrm,       0 },
1122     { X86::VPCMPEQBrr,        X86::VPCMPEQBrm,         0 },
1123     { X86::VPCMPEQDrr,        X86::VPCMPEQDrm,         0 },
1124     { X86::VPCMPEQQrr,        X86::VPCMPEQQrm,         0 },
1125     { X86::VPCMPEQWrr,        X86::VPCMPEQWrm,         0 },
1126     { X86::VPCMPGTBrr,        X86::VPCMPGTBrm,         0 },
1127     { X86::VPCMPGTDrr,        X86::VPCMPGTDrm,         0 },
1128     { X86::VPCMPGTQrr,        X86::VPCMPGTQrm,         0 },
1129     { X86::VPCMPGTWrr,        X86::VPCMPGTWrm,         0 },
1130     { X86::VPHADDDrr,         X86::VPHADDDrm,          0 },
1131     { X86::VPHADDSWrr128,     X86::VPHADDSWrm128,      0 },
1132     { X86::VPHADDWrr,         X86::VPHADDWrm,          0 },
1133     { X86::VPHSUBDrr,         X86::VPHSUBDrm,          0 },
1134     { X86::VPHSUBSWrr128,     X86::VPHSUBSWrm128,      0 },
1135     { X86::VPHSUBWrr,         X86::VPHSUBWrm,          0 },
1136     { X86::VPERMILPDrr,       X86::VPERMILPDrm,        0 },
1137     { X86::VPERMILPSrr,       X86::VPERMILPSrm,        0 },
1138     { X86::VPINSRBrr,         X86::VPINSRBrm,          0 },
1139     { X86::VPINSRDrr,         X86::VPINSRDrm,          0 },
1140     { X86::VPINSRQrr,         X86::VPINSRQrm,          0 },
1141     { X86::VPINSRWrri,        X86::VPINSRWrmi,         0 },
1142     { X86::VPMADDUBSWrr128,   X86::VPMADDUBSWrm128,    0 },
1143     { X86::VPMADDWDrr,        X86::VPMADDWDrm,         0 },
1144     { X86::VPMAXSWrr,         X86::VPMAXSWrm,          0 },
1145     { X86::VPMAXUBrr,         X86::VPMAXUBrm,          0 },
1146     { X86::VPMINSWrr,         X86::VPMINSWrm,          0 },
1147     { X86::VPMINUBrr,         X86::VPMINUBrm,          0 },
1148     { X86::VPMINSBrr,         X86::VPMINSBrm,          0 },
1149     { X86::VPMINSDrr,         X86::VPMINSDrm,          0 },
1150     { X86::VPMINUDrr,         X86::VPMINUDrm,          0 },
1151     { X86::VPMINUWrr,         X86::VPMINUWrm,          0 },
1152     { X86::VPMAXSBrr,         X86::VPMAXSBrm,          0 },
1153     { X86::VPMAXSDrr,         X86::VPMAXSDrm,          0 },
1154     { X86::VPMAXUDrr,         X86::VPMAXUDrm,          0 },
1155     { X86::VPMAXUWrr,         X86::VPMAXUWrm,          0 },
1156     { X86::VPMULDQrr,         X86::VPMULDQrm,          0 },
1157     { X86::VPMULHRSWrr128,    X86::VPMULHRSWrm128,     0 },
1158     { X86::VPMULHUWrr,        X86::VPMULHUWrm,         0 },
1159     { X86::VPMULHWrr,         X86::VPMULHWrm,          0 },
1160     { X86::VPMULLDrr,         X86::VPMULLDrm,          0 },
1161     { X86::VPMULLWrr,         X86::VPMULLWrm,          0 },
1162     { X86::VPMULUDQrr,        X86::VPMULUDQrm,         0 },
1163     { X86::VPORrr,            X86::VPORrm,             0 },
1164     { X86::VPSADBWrr,         X86::VPSADBWrm,          0 },
1165     { X86::VPSHUFBrr,         X86::VPSHUFBrm,          0 },
1166     { X86::VPSIGNBrr,         X86::VPSIGNBrm,          0 },
1167     { X86::VPSIGNWrr,         X86::VPSIGNWrm,          0 },
1168     { X86::VPSIGNDrr,         X86::VPSIGNDrm,          0 },
1169     { X86::VPSLLDrr,          X86::VPSLLDrm,           0 },
1170     { X86::VPSLLQrr,          X86::VPSLLQrm,           0 },
1171     { X86::VPSLLWrr,          X86::VPSLLWrm,           0 },
1172     { X86::VPSRADrr,          X86::VPSRADrm,           0 },
1173     { X86::VPSRAWrr,          X86::VPSRAWrm,           0 },
1174     { X86::VPSRLDrr,          X86::VPSRLDrm,           0 },
1175     { X86::VPSRLQrr,          X86::VPSRLQrm,           0 },
1176     { X86::VPSRLWrr,          X86::VPSRLWrm,           0 },
1177     { X86::VPSUBBrr,          X86::VPSUBBrm,           0 },
1178     { X86::VPSUBDrr,          X86::VPSUBDrm,           0 },
1179     { X86::VPSUBQrr,          X86::VPSUBQrm,           0 },
1180     { X86::VPSUBSBrr,         X86::VPSUBSBrm,          0 },
1181     { X86::VPSUBSWrr,         X86::VPSUBSWrm,          0 },
1182     { X86::VPSUBUSBrr,        X86::VPSUBUSBrm,         0 },
1183     { X86::VPSUBUSWrr,        X86::VPSUBUSWrm,         0 },
1184     { X86::VPSUBWrr,          X86::VPSUBWrm,           0 },
1185     { X86::VPUNPCKHBWrr,      X86::VPUNPCKHBWrm,       0 },
1186     { X86::VPUNPCKHDQrr,      X86::VPUNPCKHDQrm,       0 },
1187     { X86::VPUNPCKHQDQrr,     X86::VPUNPCKHQDQrm,      0 },
1188     { X86::VPUNPCKHWDrr,      X86::VPUNPCKHWDrm,       0 },
1189     { X86::VPUNPCKLBWrr,      X86::VPUNPCKLBWrm,       0 },
1190     { X86::VPUNPCKLDQrr,      X86::VPUNPCKLDQrm,       0 },
1191     { X86::VPUNPCKLQDQrr,     X86::VPUNPCKLQDQrm,      0 },
1192     { X86::VPUNPCKLWDrr,      X86::VPUNPCKLWDrm,       0 },
1193     { X86::VPXORrr,           X86::VPXORrm,            0 },
1194     { X86::VSHUFPDrri,        X86::VSHUFPDrmi,         0 },
1195     { X86::VSHUFPSrri,        X86::VSHUFPSrmi,         0 },
1196     { X86::VSUBPDrr,          X86::VSUBPDrm,           0 },
1197     { X86::VSUBPSrr,          X86::VSUBPSrm,           0 },
1198     { X86::VSUBSDrr,          X86::VSUBSDrm,           0 },
1199     { X86::VSUBSDrr_Int,      X86::VSUBSDrm_Int,       0 },
1200     { X86::VSUBSSrr,          X86::VSUBSSrm,           0 },
1201     { X86::VSUBSSrr_Int,      X86::VSUBSSrm_Int,       0 },
1202     { X86::VUNPCKHPDrr,       X86::VUNPCKHPDrm,        0 },
1203     { X86::VUNPCKHPSrr,       X86::VUNPCKHPSrm,        0 },
1204     { X86::VUNPCKLPDrr,       X86::VUNPCKLPDrm,        0 },
1205     { X86::VUNPCKLPSrr,       X86::VUNPCKLPSrm,        0 },
1206     { X86::VXORPDrr,          X86::VXORPDrm,           0 },
1207     { X86::VXORPSrr,          X86::VXORPSrm,           0 },
1208     // AVX 256-bit foldable instructions
1209     { X86::VADDPDYrr,         X86::VADDPDYrm,          0 },
1210     { X86::VADDPSYrr,         X86::VADDPSYrm,          0 },
1211     { X86::VADDSUBPDYrr,      X86::VADDSUBPDYrm,       0 },
1212     { X86::VADDSUBPSYrr,      X86::VADDSUBPSYrm,       0 },
1213     { X86::VANDNPDYrr,        X86::VANDNPDYrm,         0 },
1214     { X86::VANDNPSYrr,        X86::VANDNPSYrm,         0 },
1215     { X86::VANDPDYrr,         X86::VANDPDYrm,          0 },
1216     { X86::VANDPSYrr,         X86::VANDPSYrm,          0 },
1217     { X86::VBLENDPDYrri,      X86::VBLENDPDYrmi,       0 },
1218     { X86::VBLENDPSYrri,      X86::VBLENDPSYrmi,       0 },
1219     { X86::VBLENDVPDYrr,      X86::VBLENDVPDYrm,       0 },
1220     { X86::VBLENDVPSYrr,      X86::VBLENDVPSYrm,       0 },
1221     { X86::VCMPPDYrri,        X86::VCMPPDYrmi,         0 },
1222     { X86::VCMPPSYrri,        X86::VCMPPSYrmi,         0 },
1223     { X86::VDIVPDYrr,         X86::VDIVPDYrm,          0 },
1224     { X86::VDIVPSYrr,         X86::VDIVPSYrm,          0 },
1225     { X86::VDPPSYrri,         X86::VDPPSYrmi,          0 },
1226     { X86::VHADDPDYrr,        X86::VHADDPDYrm,         0 },
1227     { X86::VHADDPSYrr,        X86::VHADDPSYrm,         0 },
1228     { X86::VHSUBPDYrr,        X86::VHSUBPDYrm,         0 },
1229     { X86::VHSUBPSYrr,        X86::VHSUBPSYrm,         0 },
1230     { X86::VINSERTF128rr,     X86::VINSERTF128rm,      0 },
1231     { X86::VMAXPDYrr,         X86::VMAXPDYrm,          0 },
1232     { X86::VMAXPSYrr,         X86::VMAXPSYrm,          0 },
1233     { X86::VMINPDYrr,         X86::VMINPDYrm,          0 },
1234     { X86::VMINPSYrr,         X86::VMINPSYrm,          0 },
1235     { X86::VMULPDYrr,         X86::VMULPDYrm,          0 },
1236     { X86::VMULPSYrr,         X86::VMULPSYrm,          0 },
1237     { X86::VORPDYrr,          X86::VORPDYrm,           0 },
1238     { X86::VORPSYrr,          X86::VORPSYrm,           0 },
1239     { X86::VPERM2F128rr,      X86::VPERM2F128rm,       0 },
1240     { X86::VPERMILPDYrr,      X86::VPERMILPDYrm,       0 },
1241     { X86::VPERMILPSYrr,      X86::VPERMILPSYrm,       0 },
1242     { X86::VSHUFPDYrri,       X86::VSHUFPDYrmi,        0 },
1243     { X86::VSHUFPSYrri,       X86::VSHUFPSYrmi,        0 },
1244     { X86::VSUBPDYrr,         X86::VSUBPDYrm,          0 },
1245     { X86::VSUBPSYrr,         X86::VSUBPSYrm,          0 },
1246     { X86::VUNPCKHPDYrr,      X86::VUNPCKHPDYrm,       0 },
1247     { X86::VUNPCKHPSYrr,      X86::VUNPCKHPSYrm,       0 },
1248     { X86::VUNPCKLPDYrr,      X86::VUNPCKLPDYrm,       0 },
1249     { X86::VUNPCKLPSYrr,      X86::VUNPCKLPSYrm,       0 },
1250     { X86::VXORPDYrr,         X86::VXORPDYrm,          0 },
1251     { X86::VXORPSYrr,         X86::VXORPSYrm,          0 },
1252     // AVX2 foldable instructions
1253     { X86::VINSERTI128rr,     X86::VINSERTI128rm,      0 },
1254     { X86::VPACKSSDWYrr,      X86::VPACKSSDWYrm,       0 },
1255     { X86::VPACKSSWBYrr,      X86::VPACKSSWBYrm,       0 },
1256     { X86::VPACKUSDWYrr,      X86::VPACKUSDWYrm,       0 },
1257     { X86::VPACKUSWBYrr,      X86::VPACKUSWBYrm,       0 },
1258     { X86::VPADDBYrr,         X86::VPADDBYrm,          0 },
1259     { X86::VPADDDYrr,         X86::VPADDDYrm,          0 },
1260     { X86::VPADDQYrr,         X86::VPADDQYrm,          0 },
1261     { X86::VPADDSBYrr,        X86::VPADDSBYrm,         0 },
1262     { X86::VPADDSWYrr,        X86::VPADDSWYrm,         0 },
1263     { X86::VPADDUSBYrr,       X86::VPADDUSBYrm,        0 },
1264     { X86::VPADDUSWYrr,       X86::VPADDUSWYrm,        0 },
1265     { X86::VPADDWYrr,         X86::VPADDWYrm,          0 },
1266     { X86::VPALIGNR256rr,     X86::VPALIGNR256rm,      0 },
1267     { X86::VPANDNYrr,         X86::VPANDNYrm,          0 },
1268     { X86::VPANDYrr,          X86::VPANDYrm,           0 },
1269     { X86::VPAVGBYrr,         X86::VPAVGBYrm,          0 },
1270     { X86::VPAVGWYrr,         X86::VPAVGWYrm,          0 },
1271     { X86::VPBLENDDrri,       X86::VPBLENDDrmi,        0 },
1272     { X86::VPBLENDDYrri,      X86::VPBLENDDYrmi,       0 },
1273     { X86::VPBLENDWYrri,      X86::VPBLENDWYrmi,       0 },
1274     { X86::VPCMPEQBYrr,       X86::VPCMPEQBYrm,        0 },
1275     { X86::VPCMPEQDYrr,       X86::VPCMPEQDYrm,        0 },
1276     { X86::VPCMPEQQYrr,       X86::VPCMPEQQYrm,        0 },
1277     { X86::VPCMPEQWYrr,       X86::VPCMPEQWYrm,        0 },
1278     { X86::VPCMPGTBYrr,       X86::VPCMPGTBYrm,        0 },
1279     { X86::VPCMPGTDYrr,       X86::VPCMPGTDYrm,        0 },
1280     { X86::VPCMPGTQYrr,       X86::VPCMPGTQYrm,        0 },
1281     { X86::VPCMPGTWYrr,       X86::VPCMPGTWYrm,        0 },
1282     { X86::VPERM2I128rr,      X86::VPERM2I128rm,       0 },
1283     { X86::VPERMDYrr,         X86::VPERMDYrm,          0 },
1284     { X86::VPERMPDYri,        X86::VPERMPDYmi,         0 },
1285     { X86::VPERMPSYrr,        X86::VPERMPSYrm,         0 },
1286     { X86::VPERMQYri,         X86::VPERMQYmi,          0 },
1287     { X86::VPHADDDYrr,        X86::VPHADDDYrm,         0 },
1288     { X86::VPHADDSWrr256,     X86::VPHADDSWrm256,      0 },
1289     { X86::VPHADDWYrr,        X86::VPHADDWYrm,         0 },
1290     { X86::VPHSUBDYrr,        X86::VPHSUBDYrm,         0 },
1291     { X86::VPHSUBSWrr256,     X86::VPHSUBSWrm256,      0 },
1292     { X86::VPHSUBWYrr,        X86::VPHSUBWYrm,         0 },
1293     { X86::VPMADDUBSWrr256,   X86::VPMADDUBSWrm256,    0 },
1294     { X86::VPMADDWDYrr,       X86::VPMADDWDYrm,        0 },
1295     { X86::VPMAXSWYrr,        X86::VPMAXSWYrm,         0 },
1296     { X86::VPMAXUBYrr,        X86::VPMAXUBYrm,         0 },
1297     { X86::VPMINSWYrr,        X86::VPMINSWYrm,         0 },
1298     { X86::VPMINUBYrr,        X86::VPMINUBYrm,         0 },
1299     { X86::VPMINSBYrr,        X86::VPMINSBYrm,         0 },
1300     { X86::VPMINSDYrr,        X86::VPMINSDYrm,         0 },
1301     { X86::VPMINUDYrr,        X86::VPMINUDYrm,         0 },
1302     { X86::VPMINUWYrr,        X86::VPMINUWYrm,         0 },
1303     { X86::VPMAXSBYrr,        X86::VPMAXSBYrm,         0 },
1304     { X86::VPMAXSDYrr,        X86::VPMAXSDYrm,         0 },
1305     { X86::VPMAXUDYrr,        X86::VPMAXUDYrm,         0 },
1306     { X86::VPMAXUWYrr,        X86::VPMAXUWYrm,         0 },
1307     { X86::VMPSADBWYrri,      X86::VMPSADBWYrmi,       0 },
1308     { X86::VPMULDQYrr,        X86::VPMULDQYrm,         0 },
1309     { X86::VPMULHRSWrr256,    X86::VPMULHRSWrm256,     0 },
1310     { X86::VPMULHUWYrr,       X86::VPMULHUWYrm,        0 },
1311     { X86::VPMULHWYrr,        X86::VPMULHWYrm,         0 },
1312     { X86::VPMULLDYrr,        X86::VPMULLDYrm,         0 },
1313     { X86::VPMULLWYrr,        X86::VPMULLWYrm,         0 },
1314     { X86::VPMULUDQYrr,       X86::VPMULUDQYrm,        0 },
1315     { X86::VPORYrr,           X86::VPORYrm,            0 },
1316     { X86::VPSADBWYrr,        X86::VPSADBWYrm,         0 },
1317     { X86::VPSHUFBYrr,        X86::VPSHUFBYrm,         0 },
1318     { X86::VPSIGNBYrr,        X86::VPSIGNBYrm,         0 },
1319     { X86::VPSIGNWYrr,        X86::VPSIGNWYrm,         0 },
1320     { X86::VPSIGNDYrr,        X86::VPSIGNDYrm,         0 },
1321     { X86::VPSLLDYrr,         X86::VPSLLDYrm,          0 },
1322     { X86::VPSLLQYrr,         X86::VPSLLQYrm,          0 },
1323     { X86::VPSLLWYrr,         X86::VPSLLWYrm,          0 },
1324     { X86::VPSLLVDrr,         X86::VPSLLVDrm,          0 },
1325     { X86::VPSLLVDYrr,        X86::VPSLLVDYrm,         0 },
1326     { X86::VPSLLVQrr,         X86::VPSLLVQrm,          0 },
1327     { X86::VPSLLVQYrr,        X86::VPSLLVQYrm,         0 },
1328     { X86::VPSRADYrr,         X86::VPSRADYrm,          0 },
1329     { X86::VPSRAWYrr,         X86::VPSRAWYrm,          0 },
1330     { X86::VPSRAVDrr,         X86::VPSRAVDrm,          0 },
1331     { X86::VPSRAVDYrr,        X86::VPSRAVDYrm,         0 },
1332     { X86::VPSRLDYrr,         X86::VPSRLDYrm,          0 },
1333     { X86::VPSRLQYrr,         X86::VPSRLQYrm,          0 },
1334     { X86::VPSRLWYrr,         X86::VPSRLWYrm,          0 },
1335     { X86::VPSRLVDrr,         X86::VPSRLVDrm,          0 },
1336     { X86::VPSRLVDYrr,        X86::VPSRLVDYrm,         0 },
1337     { X86::VPSRLVQrr,         X86::VPSRLVQrm,          0 },
1338     { X86::VPSRLVQYrr,        X86::VPSRLVQYrm,         0 },
1339     { X86::VPSUBBYrr,         X86::VPSUBBYrm,          0 },
1340     { X86::VPSUBDYrr,         X86::VPSUBDYrm,          0 },
1341     { X86::VPSUBSBYrr,        X86::VPSUBSBYrm,         0 },
1342     { X86::VPSUBSWYrr,        X86::VPSUBSWYrm,         0 },
1343     { X86::VPSUBWYrr,         X86::VPSUBWYrm,          0 },
1344     { X86::VPUNPCKHBWYrr,     X86::VPUNPCKHBWYrm,      0 },
1345     { X86::VPUNPCKHDQYrr,     X86::VPUNPCKHDQYrm,      0 },
1346     { X86::VPUNPCKHQDQYrr,    X86::VPUNPCKHQDQYrm,     0 },
1347     { X86::VPUNPCKHWDYrr,     X86::VPUNPCKHWDYrm,      0 },
1348     { X86::VPUNPCKLBWYrr,     X86::VPUNPCKLBWYrm,      0 },
1349     { X86::VPUNPCKLDQYrr,     X86::VPUNPCKLDQYrm,      0 },
1350     { X86::VPUNPCKLQDQYrr,    X86::VPUNPCKLQDQYrm,     0 },
1351     { X86::VPUNPCKLWDYrr,     X86::VPUNPCKLWDYrm,      0 },
1352     { X86::VPXORYrr,          X86::VPXORYrm,           0 },
1353     // FIXME: add AVX 256-bit foldable instructions
1355     // FMA4 foldable patterns
1356     { X86::VFMADDSS4rr,       X86::VFMADDSS4mr,        0           },
1357     { X86::VFMADDSD4rr,       X86::VFMADDSD4mr,        0           },
1358     { X86::VFMADDPS4rr,       X86::VFMADDPS4mr,        TB_ALIGN_16 },
1359     { X86::VFMADDPD4rr,       X86::VFMADDPD4mr,        TB_ALIGN_16 },
1360     { X86::VFMADDPS4rrY,      X86::VFMADDPS4mrY,       TB_ALIGN_32 },
1361     { X86::VFMADDPD4rrY,      X86::VFMADDPD4mrY,       TB_ALIGN_32 },
1362     { X86::VFNMADDSS4rr,      X86::VFNMADDSS4mr,       0           },
1363     { X86::VFNMADDSD4rr,      X86::VFNMADDSD4mr,       0           },
1364     { X86::VFNMADDPS4rr,      X86::VFNMADDPS4mr,       TB_ALIGN_16 },
1365     { X86::VFNMADDPD4rr,      X86::VFNMADDPD4mr,       TB_ALIGN_16 },
1366     { X86::VFNMADDPS4rrY,     X86::VFNMADDPS4mrY,      TB_ALIGN_32 },
1367     { X86::VFNMADDPD4rrY,     X86::VFNMADDPD4mrY,      TB_ALIGN_32 },
1368     { X86::VFMSUBSS4rr,       X86::VFMSUBSS4mr,        0           },
1369     { X86::VFMSUBSD4rr,       X86::VFMSUBSD4mr,        0           },
1370     { X86::VFMSUBPS4rr,       X86::VFMSUBPS4mr,        TB_ALIGN_16 },
1371     { X86::VFMSUBPD4rr,       X86::VFMSUBPD4mr,        TB_ALIGN_16 },
1372     { X86::VFMSUBPS4rrY,      X86::VFMSUBPS4mrY,       TB_ALIGN_32 },
1373     { X86::VFMSUBPD4rrY,      X86::VFMSUBPD4mrY,       TB_ALIGN_32 },
1374     { X86::VFNMSUBSS4rr,      X86::VFNMSUBSS4mr,       0           },
1375     { X86::VFNMSUBSD4rr,      X86::VFNMSUBSD4mr,       0           },
1376     { X86::VFNMSUBPS4rr,      X86::VFNMSUBPS4mr,       TB_ALIGN_16 },
1377     { X86::VFNMSUBPD4rr,      X86::VFNMSUBPD4mr,       TB_ALIGN_16 },
1378     { X86::VFNMSUBPS4rrY,     X86::VFNMSUBPS4mrY,      TB_ALIGN_32 },
1379     { X86::VFNMSUBPD4rrY,     X86::VFNMSUBPD4mrY,      TB_ALIGN_32 },
1380     { X86::VFMADDSUBPS4rr,    X86::VFMADDSUBPS4mr,     TB_ALIGN_16 },
1381     { X86::VFMADDSUBPD4rr,    X86::VFMADDSUBPD4mr,     TB_ALIGN_16 },
1382     { X86::VFMADDSUBPS4rrY,   X86::VFMADDSUBPS4mrY,    TB_ALIGN_32 },
1383     { X86::VFMADDSUBPD4rrY,   X86::VFMADDSUBPD4mrY,    TB_ALIGN_32 },
1384     { X86::VFMSUBADDPS4rr,    X86::VFMSUBADDPS4mr,     TB_ALIGN_16 },
1385     { X86::VFMSUBADDPD4rr,    X86::VFMSUBADDPD4mr,     TB_ALIGN_16 },
1386     { X86::VFMSUBADDPS4rrY,   X86::VFMSUBADDPS4mrY,    TB_ALIGN_32 },
1387     { X86::VFMSUBADDPD4rrY,   X86::VFMSUBADDPD4mrY,    TB_ALIGN_32 },
1389     // BMI/BMI2 foldable instructions
1390     { X86::ANDN32rr,          X86::ANDN32rm,            0 },
1391     { X86::ANDN64rr,          X86::ANDN64rm,            0 },
1392     { X86::MULX32rr,          X86::MULX32rm,            0 },
1393     { X86::MULX64rr,          X86::MULX64rm,            0 },
1394     { X86::PDEP32rr,          X86::PDEP32rm,            0 },
1395     { X86::PDEP64rr,          X86::PDEP64rm,            0 },
1396     { X86::PEXT32rr,          X86::PEXT32rm,            0 },
1397     { X86::PEXT64rr,          X86::PEXT64rm,            0 },
1399     // AVX-512 foldable instructions
1400     { X86::VADDPSZrr,         X86::VADDPSZrm,           0 },
1401     { X86::VADDPDZrr,         X86::VADDPDZrm,           0 },
1402     { X86::VSUBPSZrr,         X86::VSUBPSZrm,           0 },
1403     { X86::VSUBPDZrr,         X86::VSUBPDZrm,           0 },
1404     { X86::VMULPSZrr,         X86::VMULPSZrm,           0 },
1405     { X86::VMULPDZrr,         X86::VMULPDZrm,           0 },
1406     { X86::VDIVPSZrr,         X86::VDIVPSZrm,           0 },
1407     { X86::VDIVPDZrr,         X86::VDIVPDZrm,           0 },
1408     { X86::VMINPSZrr,         X86::VMINPSZrm,           0 },
1409     { X86::VMINPDZrr,         X86::VMINPDZrm,           0 },
1410     { X86::VMAXPSZrr,         X86::VMAXPSZrm,           0 },
1411     { X86::VMAXPDZrr,         X86::VMAXPDZrm,           0 },
1412     { X86::VPADDDZrr,         X86::VPADDDZrm,           0 },
1413     { X86::VPADDQZrr,         X86::VPADDQZrm,           0 },
1414     { X86::VPERMPDZri,        X86::VPERMPDZmi,          0 },
1415     { X86::VPERMPSZrr,        X86::VPERMPSZrm,          0 },
1416     { X86::VPMAXSDZrr,        X86::VPMAXSDZrm,          0 },
1417     { X86::VPMAXSQZrr,        X86::VPMAXSQZrm,          0 },
1418     { X86::VPMAXUDZrr,        X86::VPMAXUDZrm,          0 },
1419     { X86::VPMAXUQZrr,        X86::VPMAXUQZrm,          0 },
1420     { X86::VPMINSDZrr,        X86::VPMINSDZrm,          0 },
1421     { X86::VPMINSQZrr,        X86::VPMINSQZrm,          0 },
1422     { X86::VPMINUDZrr,        X86::VPMINUDZrm,          0 },
1423     { X86::VPMINUQZrr,        X86::VPMINUQZrm,          0 },
1424     { X86::VPMULDQZrr,        X86::VPMULDQZrm,          0 },
1425     { X86::VPSLLVDZrr,        X86::VPSLLVDZrm,          0 },
1426     { X86::VPSLLVQZrr,        X86::VPSLLVQZrm,          0 },
1427     { X86::VPSRAVDZrr,        X86::VPSRAVDZrm,          0 },
1428     { X86::VPSRLVDZrr,        X86::VPSRLVDZrm,          0 },
1429     { X86::VPSRLVQZrr,        X86::VPSRLVQZrm,          0 },
1430     { X86::VPSUBDZrr,         X86::VPSUBDZrm,           0 },
1431     { X86::VPSUBQZrr,         X86::VPSUBQZrm,           0 },
1432     { X86::VSHUFPDZrri,       X86::VSHUFPDZrmi,         0 },
1433     { X86::VSHUFPSZrri,       X86::VSHUFPSZrmi,         0 },
1434     { X86::VALIGNQrri,        X86::VALIGNQrmi,          0 },
1435     { X86::VALIGNDrri,        X86::VALIGNDrmi,          0 },
1436     { X86::VPMULUDQZrr,       X86::VPMULUDQZrm,         0 },
1437     { X86::VBROADCASTSSZrkz,  X86::VBROADCASTSSZmkz,    TB_NO_REVERSE },
1438     { X86::VBROADCASTSDZrkz,  X86::VBROADCASTSDZmkz,    TB_NO_REVERSE },
1440     // AVX-512{F,VL} foldable instructions
1441     { X86::VBROADCASTSSZ256rkz,  X86::VBROADCASTSSZ256mkz,      TB_NO_REVERSE },
1442     { X86::VBROADCASTSDZ256rkz,  X86::VBROADCASTSDZ256mkz,      TB_NO_REVERSE },
1443     { X86::VBROADCASTSSZ128rkz,  X86::VBROADCASTSSZ128mkz,      TB_NO_REVERSE },
1445     // AVX-512{F,VL} foldable instructions
1446     { X86::VADDPDZ128rr,      X86::VADDPDZ128rm,        0 },
1447     { X86::VADDPDZ256rr,      X86::VADDPDZ256rm,        0 },
1448     { X86::VADDPSZ128rr,      X86::VADDPSZ128rm,        0 },
1449     { X86::VADDPSZ256rr,      X86::VADDPSZ256rm,        0 },
1451     // AES foldable instructions
1452     { X86::AESDECLASTrr,      X86::AESDECLASTrm,        TB_ALIGN_16 },
1453     { X86::AESDECrr,          X86::AESDECrm,            TB_ALIGN_16 },
1454     { X86::AESENCLASTrr,      X86::AESENCLASTrm,        TB_ALIGN_16 },
1455     { X86::AESENCrr,          X86::AESENCrm,            TB_ALIGN_16 },
1456     { X86::VAESDECLASTrr,     X86::VAESDECLASTrm,       TB_ALIGN_16 },
1457     { X86::VAESDECrr,         X86::VAESDECrm,           TB_ALIGN_16 },
1458     { X86::VAESENCLASTrr,     X86::VAESENCLASTrm,       TB_ALIGN_16 },
1459     { X86::VAESENCrr,         X86::VAESENCrm,           TB_ALIGN_16 },
1461     // SHA foldable instructions
1462     { X86::SHA1MSG1rr,        X86::SHA1MSG1rm,          TB_ALIGN_16 },
1463     { X86::SHA1MSG2rr,        X86::SHA1MSG2rm,          TB_ALIGN_16 },
1464     { X86::SHA1NEXTErr,       X86::SHA1NEXTErm,         TB_ALIGN_16 },
1465     { X86::SHA1RNDS4rri,      X86::SHA1RNDS4rmi,        TB_ALIGN_16 },
1466     { X86::SHA256MSG1rr,      X86::SHA256MSG1rm,        TB_ALIGN_16 },
1467     { X86::SHA256MSG2rr,      X86::SHA256MSG2rm,        TB_ALIGN_16 },
1468     { X86::SHA256RNDS2rr,     X86::SHA256RNDS2rm,       TB_ALIGN_16 },
1469   };
1471   for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
1472     unsigned RegOp = OpTbl2[i].RegOp;
1473     unsigned MemOp = OpTbl2[i].MemOp;
1474     unsigned Flags = OpTbl2[i].Flags;
1475     AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
1476                   RegOp, MemOp,
1477                   // Index 2, folded load
1478                   Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
1479   }
1481   static const X86OpTblEntry OpTbl3[] = {
1482     // FMA foldable instructions
1483     { X86::VFMADDSSr231r,         X86::VFMADDSSr231m,         TB_ALIGN_NONE },
1484     { X86::VFMADDSDr231r,         X86::VFMADDSDr231m,         TB_ALIGN_NONE },
1485     { X86::VFMADDSSr132r,         X86::VFMADDSSr132m,         TB_ALIGN_NONE },
1486     { X86::VFMADDSDr132r,         X86::VFMADDSDr132m,         TB_ALIGN_NONE },
1487     { X86::VFMADDSSr213r,         X86::VFMADDSSr213m,         TB_ALIGN_NONE },
1488     { X86::VFMADDSDr213r,         X86::VFMADDSDr213m,         TB_ALIGN_NONE },
1490     { X86::VFMADDPSr231r,         X86::VFMADDPSr231m,         TB_ALIGN_NONE },
1491     { X86::VFMADDPDr231r,         X86::VFMADDPDr231m,         TB_ALIGN_NONE },
1492     { X86::VFMADDPSr132r,         X86::VFMADDPSr132m,         TB_ALIGN_NONE },
1493     { X86::VFMADDPDr132r,         X86::VFMADDPDr132m,         TB_ALIGN_NONE },
1494     { X86::VFMADDPSr213r,         X86::VFMADDPSr213m,         TB_ALIGN_NONE },
1495     { X86::VFMADDPDr213r,         X86::VFMADDPDr213m,         TB_ALIGN_NONE },
1496     { X86::VFMADDPSr231rY,        X86::VFMADDPSr231mY,        TB_ALIGN_NONE },
1497     { X86::VFMADDPDr231rY,        X86::VFMADDPDr231mY,        TB_ALIGN_NONE },
1498     { X86::VFMADDPSr132rY,        X86::VFMADDPSr132mY,        TB_ALIGN_NONE },
1499     { X86::VFMADDPDr132rY,        X86::VFMADDPDr132mY,        TB_ALIGN_NONE },
1500     { X86::VFMADDPSr213rY,        X86::VFMADDPSr213mY,        TB_ALIGN_NONE },
1501     { X86::VFMADDPDr213rY,        X86::VFMADDPDr213mY,        TB_ALIGN_NONE },
1503     { X86::VFNMADDSSr231r,        X86::VFNMADDSSr231m,        TB_ALIGN_NONE },
1504     { X86::VFNMADDSDr231r,        X86::VFNMADDSDr231m,        TB_ALIGN_NONE },
1505     { X86::VFNMADDSSr132r,        X86::VFNMADDSSr132m,        TB_ALIGN_NONE },
1506     { X86::VFNMADDSDr132r,        X86::VFNMADDSDr132m,        TB_ALIGN_NONE },
1507     { X86::VFNMADDSSr213r,        X86::VFNMADDSSr213m,        TB_ALIGN_NONE },
1508     { X86::VFNMADDSDr213r,        X86::VFNMADDSDr213m,        TB_ALIGN_NONE },
1510     { X86::VFNMADDPSr231r,        X86::VFNMADDPSr231m,        TB_ALIGN_NONE },
1511     { X86::VFNMADDPDr231r,        X86::VFNMADDPDr231m,        TB_ALIGN_NONE },
1512     { X86::VFNMADDPSr132r,        X86::VFNMADDPSr132m,        TB_ALIGN_NONE },
1513     { X86::VFNMADDPDr132r,        X86::VFNMADDPDr132m,        TB_ALIGN_NONE },
1514     { X86::VFNMADDPSr213r,        X86::VFNMADDPSr213m,        TB_ALIGN_NONE },
1515     { X86::VFNMADDPDr213r,        X86::VFNMADDPDr213m,        TB_ALIGN_NONE },
1516     { X86::VFNMADDPSr231rY,       X86::VFNMADDPSr231mY,       TB_ALIGN_NONE },
1517     { X86::VFNMADDPDr231rY,       X86::VFNMADDPDr231mY,       TB_ALIGN_NONE },
1518     { X86::VFNMADDPSr132rY,       X86::VFNMADDPSr132mY,       TB_ALIGN_NONE },
1519     { X86::VFNMADDPDr132rY,       X86::VFNMADDPDr132mY,       TB_ALIGN_NONE },
1520     { X86::VFNMADDPSr213rY,       X86::VFNMADDPSr213mY,       TB_ALIGN_NONE },
1521     { X86::VFNMADDPDr213rY,       X86::VFNMADDPDr213mY,       TB_ALIGN_NONE },
1523     { X86::VFMSUBSSr231r,         X86::VFMSUBSSr231m,         TB_ALIGN_NONE },
1524     { X86::VFMSUBSDr231r,         X86::VFMSUBSDr231m,         TB_ALIGN_NONE },
1525     { X86::VFMSUBSSr132r,         X86::VFMSUBSSr132m,         TB_ALIGN_NONE },
1526     { X86::VFMSUBSDr132r,         X86::VFMSUBSDr132m,         TB_ALIGN_NONE },
1527     { X86::VFMSUBSSr213r,         X86::VFMSUBSSr213m,         TB_ALIGN_NONE },
1528     { X86::VFMSUBSDr213r,         X86::VFMSUBSDr213m,         TB_ALIGN_NONE },
1530     { X86::VFMSUBPSr231r,         X86::VFMSUBPSr231m,         TB_ALIGN_NONE },
1531     { X86::VFMSUBPDr231r,         X86::VFMSUBPDr231m,         TB_ALIGN_NONE },
1532     { X86::VFMSUBPSr132r,         X86::VFMSUBPSr132m,         TB_ALIGN_NONE },
1533     { X86::VFMSUBPDr132r,         X86::VFMSUBPDr132m,         TB_ALIGN_NONE },
1534     { X86::VFMSUBPSr213r,         X86::VFMSUBPSr213m,         TB_ALIGN_NONE },
1535     { X86::VFMSUBPDr213r,         X86::VFMSUBPDr213m,         TB_ALIGN_NONE },
1536     { X86::VFMSUBPSr231rY,        X86::VFMSUBPSr231mY,        TB_ALIGN_NONE },
1537     { X86::VFMSUBPDr231rY,        X86::VFMSUBPDr231mY,        TB_ALIGN_NONE },
1538     { X86::VFMSUBPSr132rY,        X86::VFMSUBPSr132mY,        TB_ALIGN_NONE },
1539     { X86::VFMSUBPDr132rY,        X86::VFMSUBPDr132mY,        TB_ALIGN_NONE },
1540     { X86::VFMSUBPSr213rY,        X86::VFMSUBPSr213mY,        TB_ALIGN_NONE },
1541     { X86::VFMSUBPDr213rY,        X86::VFMSUBPDr213mY,        TB_ALIGN_NONE },
1543     { X86::VFNMSUBSSr231r,        X86::VFNMSUBSSr231m,        TB_ALIGN_NONE },
1544     { X86::VFNMSUBSDr231r,        X86::VFNMSUBSDr231m,        TB_ALIGN_NONE },
1545     { X86::VFNMSUBSSr132r,        X86::VFNMSUBSSr132m,        TB_ALIGN_NONE },
1546     { X86::VFNMSUBSDr132r,        X86::VFNMSUBSDr132m,        TB_ALIGN_NONE },
1547     { X86::VFNMSUBSSr213r,        X86::VFNMSUBSSr213m,        TB_ALIGN_NONE },
1548     { X86::VFNMSUBSDr213r,        X86::VFNMSUBSDr213m,        TB_ALIGN_NONE },
1550     { X86::VFNMSUBPSr231r,        X86::VFNMSUBPSr231m,        TB_ALIGN_NONE },
1551     { X86::VFNMSUBPDr231r,        X86::VFNMSUBPDr231m,        TB_ALIGN_NONE },
1552     { X86::VFNMSUBPSr132r,        X86::VFNMSUBPSr132m,        TB_ALIGN_NONE },
1553     { X86::VFNMSUBPDr132r,        X86::VFNMSUBPDr132m,        TB_ALIGN_NONE },
1554     { X86::VFNMSUBPSr213r,        X86::VFNMSUBPSr213m,        TB_ALIGN_NONE },
1555     { X86::VFNMSUBPDr213r,        X86::VFNMSUBPDr213m,        TB_ALIGN_NONE },
1556     { X86::VFNMSUBPSr231rY,       X86::VFNMSUBPSr231mY,       TB_ALIGN_NONE },
1557     { X86::VFNMSUBPDr231rY,       X86::VFNMSUBPDr231mY,       TB_ALIGN_NONE },
1558     { X86::VFNMSUBPSr132rY,       X86::VFNMSUBPSr132mY,       TB_ALIGN_NONE },
1559     { X86::VFNMSUBPDr132rY,       X86::VFNMSUBPDr132mY,       TB_ALIGN_NONE },
1560     { X86::VFNMSUBPSr213rY,       X86::VFNMSUBPSr213mY,       TB_ALIGN_NONE },
1561     { X86::VFNMSUBPDr213rY,       X86::VFNMSUBPDr213mY,       TB_ALIGN_NONE },
1563     { X86::VFMADDSUBPSr231r,      X86::VFMADDSUBPSr231m,      TB_ALIGN_NONE },
1564     { X86::VFMADDSUBPDr231r,      X86::VFMADDSUBPDr231m,      TB_ALIGN_NONE },
1565     { X86::VFMADDSUBPSr132r,      X86::VFMADDSUBPSr132m,      TB_ALIGN_NONE },
1566     { X86::VFMADDSUBPDr132r,      X86::VFMADDSUBPDr132m,      TB_ALIGN_NONE },
1567     { X86::VFMADDSUBPSr213r,      X86::VFMADDSUBPSr213m,      TB_ALIGN_NONE },
1568     { X86::VFMADDSUBPDr213r,      X86::VFMADDSUBPDr213m,      TB_ALIGN_NONE },
1569     { X86::VFMADDSUBPSr231rY,     X86::VFMADDSUBPSr231mY,     TB_ALIGN_NONE },
1570     { X86::VFMADDSUBPDr231rY,     X86::VFMADDSUBPDr231mY,     TB_ALIGN_NONE },
1571     { X86::VFMADDSUBPSr132rY,     X86::VFMADDSUBPSr132mY,     TB_ALIGN_NONE },
1572     { X86::VFMADDSUBPDr132rY,     X86::VFMADDSUBPDr132mY,     TB_ALIGN_NONE },
1573     { X86::VFMADDSUBPSr213rY,     X86::VFMADDSUBPSr213mY,     TB_ALIGN_NONE },
1574     { X86::VFMADDSUBPDr213rY,     X86::VFMADDSUBPDr213mY,     TB_ALIGN_NONE },
1576     { X86::VFMSUBADDPSr231r,      X86::VFMSUBADDPSr231m,      TB_ALIGN_NONE },
1577     { X86::VFMSUBADDPDr231r,      X86::VFMSUBADDPDr231m,      TB_ALIGN_NONE },
1578     { X86::VFMSUBADDPSr132r,      X86::VFMSUBADDPSr132m,      TB_ALIGN_NONE },
1579     { X86::VFMSUBADDPDr132r,      X86::VFMSUBADDPDr132m,      TB_ALIGN_NONE },
1580     { X86::VFMSUBADDPSr213r,      X86::VFMSUBADDPSr213m,      TB_ALIGN_NONE },
1581     { X86::VFMSUBADDPDr213r,      X86::VFMSUBADDPDr213m,      TB_ALIGN_NONE },
1582     { X86::VFMSUBADDPSr231rY,     X86::VFMSUBADDPSr231mY,     TB_ALIGN_NONE },
1583     { X86::VFMSUBADDPDr231rY,     X86::VFMSUBADDPDr231mY,     TB_ALIGN_NONE },
1584     { X86::VFMSUBADDPSr132rY,     X86::VFMSUBADDPSr132mY,     TB_ALIGN_NONE },
1585     { X86::VFMSUBADDPDr132rY,     X86::VFMSUBADDPDr132mY,     TB_ALIGN_NONE },
1586     { X86::VFMSUBADDPSr213rY,     X86::VFMSUBADDPSr213mY,     TB_ALIGN_NONE },
1587     { X86::VFMSUBADDPDr213rY,     X86::VFMSUBADDPDr213mY,     TB_ALIGN_NONE },
1589     // FMA4 foldable patterns
1590     { X86::VFMADDSS4rr,           X86::VFMADDSS4rm,           0           },
1591     { X86::VFMADDSD4rr,           X86::VFMADDSD4rm,           0           },
1592     { X86::VFMADDPS4rr,           X86::VFMADDPS4rm,           TB_ALIGN_16 },
1593     { X86::VFMADDPD4rr,           X86::VFMADDPD4rm,           TB_ALIGN_16 },
1594     { X86::VFMADDPS4rrY,          X86::VFMADDPS4rmY,          TB_ALIGN_32 },
1595     { X86::VFMADDPD4rrY,          X86::VFMADDPD4rmY,          TB_ALIGN_32 },
1596     { X86::VFNMADDSS4rr,          X86::VFNMADDSS4rm,          0           },
1597     { X86::VFNMADDSD4rr,          X86::VFNMADDSD4rm,          0           },
1598     { X86::VFNMADDPS4rr,          X86::VFNMADDPS4rm,          TB_ALIGN_16 },
1599     { X86::VFNMADDPD4rr,          X86::VFNMADDPD4rm,          TB_ALIGN_16 },
1600     { X86::VFNMADDPS4rrY,         X86::VFNMADDPS4rmY,         TB_ALIGN_32 },
1601     { X86::VFNMADDPD4rrY,         X86::VFNMADDPD4rmY,         TB_ALIGN_32 },
1602     { X86::VFMSUBSS4rr,           X86::VFMSUBSS4rm,           0           },
1603     { X86::VFMSUBSD4rr,           X86::VFMSUBSD4rm,           0           },
1604     { X86::VFMSUBPS4rr,           X86::VFMSUBPS4rm,           TB_ALIGN_16 },
1605     { X86::VFMSUBPD4rr,           X86::VFMSUBPD4rm,           TB_ALIGN_16 },
1606     { X86::VFMSUBPS4rrY,          X86::VFMSUBPS4rmY,          TB_ALIGN_32 },
1607     { X86::VFMSUBPD4rrY,          X86::VFMSUBPD4rmY,          TB_ALIGN_32 },
1608     { X86::VFNMSUBSS4rr,          X86::VFNMSUBSS4rm,          0           },
1609     { X86::VFNMSUBSD4rr,          X86::VFNMSUBSD4rm,          0           },
1610     { X86::VFNMSUBPS4rr,          X86::VFNMSUBPS4rm,          TB_ALIGN_16 },
1611     { X86::VFNMSUBPD4rr,          X86::VFNMSUBPD4rm,          TB_ALIGN_16 },
1612     { X86::VFNMSUBPS4rrY,         X86::VFNMSUBPS4rmY,         TB_ALIGN_32 },
1613     { X86::VFNMSUBPD4rrY,         X86::VFNMSUBPD4rmY,         TB_ALIGN_32 },
1614     { X86::VFMADDSUBPS4rr,        X86::VFMADDSUBPS4rm,        TB_ALIGN_16 },
1615     { X86::VFMADDSUBPD4rr,        X86::VFMADDSUBPD4rm,        TB_ALIGN_16 },
1616     { X86::VFMADDSUBPS4rrY,       X86::VFMADDSUBPS4rmY,       TB_ALIGN_32 },
1617     { X86::VFMADDSUBPD4rrY,       X86::VFMADDSUBPD4rmY,       TB_ALIGN_32 },
1618     { X86::VFMSUBADDPS4rr,        X86::VFMSUBADDPS4rm,        TB_ALIGN_16 },
1619     { X86::VFMSUBADDPD4rr,        X86::VFMSUBADDPD4rm,        TB_ALIGN_16 },
1620     { X86::VFMSUBADDPS4rrY,       X86::VFMSUBADDPS4rmY,       TB_ALIGN_32 },
1621     { X86::VFMSUBADDPD4rrY,       X86::VFMSUBADDPD4rmY,       TB_ALIGN_32 },
1622     // AVX-512 VPERMI instructions with 3 source operands.
1623     { X86::VPERMI2Drr,            X86::VPERMI2Drm,            0 },
1624     { X86::VPERMI2Qrr,            X86::VPERMI2Qrm,            0 },
1625     { X86::VPERMI2PSrr,           X86::VPERMI2PSrm,           0 },
1626     { X86::VPERMI2PDrr,           X86::VPERMI2PDrm,           0 },
1627     { X86::VBLENDMPDZrr,          X86::VBLENDMPDZrm,          0 },
1628     { X86::VBLENDMPSZrr,          X86::VBLENDMPSZrm,          0 },
1629     { X86::VPBLENDMDZrr,          X86::VPBLENDMDZrm,          0 },
1630     { X86::VPBLENDMQZrr,          X86::VPBLENDMQZrm,          0 },
1631     { X86::VBROADCASTSSZrk,       X86::VBROADCASTSSZmk,       TB_NO_REVERSE },
1632     { X86::VBROADCASTSDZrk,       X86::VBROADCASTSDZmk,       TB_NO_REVERSE },
1633     { X86::VBROADCASTSSZ256rk,    X86::VBROADCASTSSZ256mk,    TB_NO_REVERSE },
1634     { X86::VBROADCASTSDZ256rk,    X86::VBROADCASTSDZ256mk,    TB_NO_REVERSE },
1635     { X86::VBROADCASTSSZ128rk,    X86::VBROADCASTSSZ128mk,    TB_NO_REVERSE },
1636      // AVX-512 arithmetic instructions
1637     { X86::VADDPSZrrkz,           X86::VADDPSZrmkz,           0 },
1638     { X86::VADDPDZrrkz,           X86::VADDPDZrmkz,           0 },
1639     { X86::VSUBPSZrrkz,           X86::VSUBPSZrmkz,           0 },
1640     { X86::VSUBPDZrrkz,           X86::VSUBPDZrmkz,           0 },
1641     { X86::VMULPSZrrkz,           X86::VMULPSZrmkz,           0 },
1642     { X86::VMULPDZrrkz,           X86::VMULPDZrmkz,           0 },
1643     { X86::VDIVPSZrrkz,           X86::VDIVPSZrmkz,           0 },
1644     { X86::VDIVPDZrrkz,           X86::VDIVPDZrmkz,           0 },
1645     { X86::VMINPSZrrkz,           X86::VMINPSZrmkz,           0 },
1646     { X86::VMINPDZrrkz,           X86::VMINPDZrmkz,           0 },
1647     { X86::VMAXPSZrrkz,           X86::VMAXPSZrmkz,           0 },
1648     { X86::VMAXPDZrrkz,           X86::VMAXPDZrmkz,           0 },
1649     // AVX-512{F,VL} arithmetic instructions 256-bit
1650     { X86::VADDPSZ256rrkz,        X86::VADDPSZ256rmkz,        0 },
1651     { X86::VADDPDZ256rrkz,        X86::VADDPDZ256rmkz,        0 },
1652     { X86::VSUBPSZ256rrkz,        X86::VSUBPSZ256rmkz,        0 },
1653     { X86::VSUBPDZ256rrkz,        X86::VSUBPDZ256rmkz,        0 },
1654     { X86::VMULPSZ256rrkz,        X86::VMULPSZ256rmkz,        0 },
1655     { X86::VMULPDZ256rrkz,        X86::VMULPDZ256rmkz,        0 },
1656     { X86::VDIVPSZ256rrkz,        X86::VDIVPSZ256rmkz,        0 },
1657     { X86::VDIVPDZ256rrkz,        X86::VDIVPDZ256rmkz,        0 },
1658     { X86::VMINPSZ256rrkz,        X86::VMINPSZ256rmkz,        0 },
1659     { X86::VMINPDZ256rrkz,        X86::VMINPDZ256rmkz,        0 },
1660     { X86::VMAXPSZ256rrkz,        X86::VMAXPSZ256rmkz,        0 },
1661     { X86::VMAXPDZ256rrkz,        X86::VMAXPDZ256rmkz,        0 },
1662     // AVX-512{F,VL} arithmetic instructions 128-bit
1663     { X86::VADDPSZ128rrkz,        X86::VADDPSZ128rmkz,        0 },
1664     { X86::VADDPDZ128rrkz,        X86::VADDPDZ128rmkz,        0 },
1665     { X86::VSUBPSZ128rrkz,        X86::VSUBPSZ128rmkz,        0 },
1666     { X86::VSUBPDZ128rrkz,        X86::VSUBPDZ128rmkz,        0 },
1667     { X86::VMULPSZ128rrkz,        X86::VMULPSZ128rmkz,        0 },
1668     { X86::VMULPDZ128rrkz,        X86::VMULPDZ128rmkz,        0 },
1669     { X86::VDIVPSZ128rrkz,        X86::VDIVPSZ128rmkz,        0 },
1670     { X86::VDIVPDZ128rrkz,        X86::VDIVPDZ128rmkz,        0 },
1671     { X86::VMINPSZ128rrkz,        X86::VMINPSZ128rmkz,        0 },
1672     { X86::VMINPDZ128rrkz,        X86::VMINPDZ128rmkz,        0 },
1673     { X86::VMAXPSZ128rrkz,        X86::VMAXPSZ128rmkz,        0 },
1674     { X86::VMAXPDZ128rrkz,        X86::VMAXPDZ128rmkz,        0 }
1675   };
1677   for (unsigned i = 0, e = array_lengthof(OpTbl3); i != e; ++i) {
1678     unsigned RegOp = OpTbl3[i].RegOp;
1679     unsigned MemOp = OpTbl3[i].MemOp;
1680     unsigned Flags = OpTbl3[i].Flags;
1681     AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
1682                   RegOp, MemOp,
1683                   // Index 3, folded load
1684                   Flags | TB_INDEX_3 | TB_FOLDED_LOAD);
1685   }
1687   static const X86OpTblEntry OpTbl4[] = {
1688      // AVX-512 foldable instructions
1689     { X86::VADDPSZrrk,         X86::VADDPSZrmk,           0 },
1690     { X86::VADDPDZrrk,         X86::VADDPDZrmk,           0 },
1691     { X86::VSUBPSZrrk,         X86::VSUBPSZrmk,           0 },
1692     { X86::VSUBPDZrrk,         X86::VSUBPDZrmk,           0 },
1693     { X86::VMULPSZrrk,         X86::VMULPSZrmk,           0 },
1694     { X86::VMULPDZrrk,         X86::VMULPDZrmk,           0 },
1695     { X86::VDIVPSZrrk,         X86::VDIVPSZrmk,           0 },
1696     { X86::VDIVPDZrrk,         X86::VDIVPDZrmk,           0 },
1697     { X86::VMINPSZrrk,         X86::VMINPSZrmk,           0 },
1698     { X86::VMINPDZrrk,         X86::VMINPDZrmk,           0 },
1699     { X86::VMAXPSZrrk,         X86::VMAXPSZrmk,           0 },
1700     { X86::VMAXPDZrrk,         X86::VMAXPDZrmk,           0 },
1701     // AVX-512{F,VL} foldable instructions 256-bit
1702     { X86::VADDPSZ256rrk,      X86::VADDPSZ256rmk,        0 },
1703     { X86::VADDPDZ256rrk,      X86::VADDPDZ256rmk,        0 },
1704     { X86::VSUBPSZ256rrk,      X86::VSUBPSZ256rmk,        0 },
1705     { X86::VSUBPDZ256rrk,      X86::VSUBPDZ256rmk,        0 },
1706     { X86::VMULPSZ256rrk,      X86::VMULPSZ256rmk,        0 },
1707     { X86::VMULPDZ256rrk,      X86::VMULPDZ256rmk,        0 },
1708     { X86::VDIVPSZ256rrk,      X86::VDIVPSZ256rmk,        0 },
1709     { X86::VDIVPDZ256rrk,      X86::VDIVPDZ256rmk,        0 },
1710     { X86::VMINPSZ256rrk,      X86::VMINPSZ256rmk,        0 },
1711     { X86::VMINPDZ256rrk,      X86::VMINPDZ256rmk,        0 },
1712     { X86::VMAXPSZ256rrk,      X86::VMAXPSZ256rmk,        0 },
1713     { X86::VMAXPDZ256rrk,      X86::VMAXPDZ256rmk,        0 },
1714     // AVX-512{F,VL} foldable instructions 128-bit
1715     { X86::VADDPSZ128rrk,      X86::VADDPSZ128rmk,        0 },
1716     { X86::VADDPDZ128rrk,      X86::VADDPDZ128rmk,        0 },
1717     { X86::VSUBPSZ128rrk,      X86::VSUBPSZ128rmk,        0 },
1718     { X86::VSUBPDZ128rrk,      X86::VSUBPDZ128rmk,        0 },
1719     { X86::VMULPSZ128rrk,      X86::VMULPSZ128rmk,        0 },
1720     { X86::VMULPDZ128rrk,      X86::VMULPDZ128rmk,        0 },
1721     { X86::VDIVPSZ128rrk,      X86::VDIVPSZ128rmk,        0 },
1722     { X86::VDIVPDZ128rrk,      X86::VDIVPDZ128rmk,        0 },
1723     { X86::VMINPSZ128rrk,      X86::VMINPSZ128rmk,        0 },
1724     { X86::VMINPDZ128rrk,      X86::VMINPDZ128rmk,        0 },
1725     { X86::VMAXPSZ128rrk,      X86::VMAXPSZ128rmk,        0 },
1726     { X86::VMAXPDZ128rrk,      X86::VMAXPDZ128rmk,        0 }
1727   };
1729   for (unsigned i = 0, e = array_lengthof(OpTbl4); i != e; ++i) {
1730     unsigned RegOp = OpTbl4[i].RegOp;
1731     unsigned MemOp = OpTbl4[i].MemOp;
1732     unsigned Flags = OpTbl4[i].Flags;
1733     AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
1734                   RegOp, MemOp,
1735                   // Index 4, folded load
1736                   Flags | TB_INDEX_4 | TB_FOLDED_LOAD);
1737   }
1740 void
1741 X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
1742                             MemOp2RegOpTableType &M2RTable,
1743                             unsigned RegOp, unsigned MemOp, unsigned Flags) {
1744     if ((Flags & TB_NO_FORWARD) == 0) {
1745       assert(!R2MTable.count(RegOp) && "Duplicate entry!");
1746       R2MTable[RegOp] = std::make_pair(MemOp, Flags);
1747     }
1748     if ((Flags & TB_NO_REVERSE) == 0) {
1749       assert(!M2RTable.count(MemOp) &&
1750            "Duplicated entries in unfolding maps?");
1751       M2RTable[MemOp] = std::make_pair(RegOp, Flags);
1752     }
1755 bool
1756 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
1757                                     unsigned &SrcReg, unsigned &DstReg,
1758                                     unsigned &SubIdx) const {
1759   switch (MI.getOpcode()) {
1760   default: break;
1761   case X86::MOVSX16rr8:
1762   case X86::MOVZX16rr8:
1763   case X86::MOVSX32rr8:
1764   case X86::MOVZX32rr8:
1765   case X86::MOVSX64rr8:
1766     if (!Subtarget.is64Bit())
1767       // It's not always legal to reference the low 8-bit of the larger
1768       // register in 32-bit mode.
1769       return false;
1770   case X86::MOVSX32rr16:
1771   case X86::MOVZX32rr16:
1772   case X86::MOVSX64rr16:
1773   case X86::MOVSX64rr32: {
1774     if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
1775       // Be conservative.
1776       return false;
1777     SrcReg = MI.getOperand(1).getReg();
1778     DstReg = MI.getOperand(0).getReg();
1779     switch (MI.getOpcode()) {
1780     default: llvm_unreachable("Unreachable!");
1781     case X86::MOVSX16rr8:
1782     case X86::MOVZX16rr8:
1783     case X86::MOVSX32rr8:
1784     case X86::MOVZX32rr8:
1785     case X86::MOVSX64rr8:
1786       SubIdx = X86::sub_8bit;
1787       break;
1788     case X86::MOVSX32rr16:
1789     case X86::MOVZX32rr16:
1790     case X86::MOVSX64rr16:
1791       SubIdx = X86::sub_16bit;
1792       break;
1793     case X86::MOVSX64rr32:
1794       SubIdx = X86::sub_32bit;
1795       break;
1796     }
1797     return true;
1798   }
1799   }
1800   return false;
1803 /// isFrameOperand - Return true and the FrameIndex if the specified
1804 /// operand and follow operands form a reference to the stack frame.
1805 bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
1806                                   int &FrameIndex) const {
1807   if (MI->getOperand(Op+X86::AddrBaseReg).isFI() &&
1808       MI->getOperand(Op+X86::AddrScaleAmt).isImm() &&
1809       MI->getOperand(Op+X86::AddrIndexReg).isReg() &&
1810       MI->getOperand(Op+X86::AddrDisp).isImm() &&
1811       MI->getOperand(Op+X86::AddrScaleAmt).getImm() == 1 &&
1812       MI->getOperand(Op+X86::AddrIndexReg).getReg() == 0 &&
1813       MI->getOperand(Op+X86::AddrDisp).getImm() == 0) {
1814     FrameIndex = MI->getOperand(Op+X86::AddrBaseReg).getIndex();
1815     return true;
1816   }
1817   return false;
1820 static bool isFrameLoadOpcode(int Opcode) {
1821   switch (Opcode) {
1822   default:
1823     return false;
1824   case X86::MOV8rm:
1825   case X86::MOV16rm:
1826   case X86::MOV32rm:
1827   case X86::MOV64rm:
1828   case X86::LD_Fp64m:
1829   case X86::MOVSSrm:
1830   case X86::MOVSDrm:
1831   case X86::MOVAPSrm:
1832   case X86::MOVAPDrm:
1833   case X86::MOVDQArm:
1834   case X86::VMOVSSrm:
1835   case X86::VMOVSDrm:
1836   case X86::VMOVAPSrm:
1837   case X86::VMOVAPDrm:
1838   case X86::VMOVDQArm:
1839   case X86::VMOVUPSYrm:
1840   case X86::VMOVAPSYrm:
1841   case X86::VMOVUPDYrm:
1842   case X86::VMOVAPDYrm:
1843   case X86::VMOVDQUYrm:
1844   case X86::VMOVDQAYrm:
1845   case X86::MMX_MOVD64rm:
1846   case X86::MMX_MOVQ64rm:
1847   case X86::VMOVAPSZrm:
1848   case X86::VMOVUPSZrm:
1849     return true;
1850   }
1853 static bool isFrameStoreOpcode(int Opcode) {
1854   switch (Opcode) {
1855   default: break;
1856   case X86::MOV8mr:
1857   case X86::MOV16mr:
1858   case X86::MOV32mr:
1859   case X86::MOV64mr:
1860   case X86::ST_FpP64m:
1861   case X86::MOVSSmr:
1862   case X86::MOVSDmr:
1863   case X86::MOVAPSmr:
1864   case X86::MOVAPDmr:
1865   case X86::MOVDQAmr:
1866   case X86::VMOVSSmr:
1867   case X86::VMOVSDmr:
1868   case X86::VMOVAPSmr:
1869   case X86::VMOVAPDmr:
1870   case X86::VMOVDQAmr:
1871   case X86::VMOVUPSYmr:
1872   case X86::VMOVAPSYmr:
1873   case X86::VMOVUPDYmr:
1874   case X86::VMOVAPDYmr:
1875   case X86::VMOVDQUYmr:
1876   case X86::VMOVDQAYmr:
1877   case X86::VMOVUPSZmr:
1878   case X86::VMOVAPSZmr:
1879   case X86::MMX_MOVD64mr:
1880   case X86::MMX_MOVQ64mr:
1881   case X86::MMX_MOVNTQmr:
1882     return true;
1883   }
1884   return false;
1887 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
1888                                            int &FrameIndex) const {
1889   if (isFrameLoadOpcode(MI->getOpcode()))
1890     if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
1891       return MI->getOperand(0).getReg();
1892   return 0;
1895 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
1896                                                  int &FrameIndex) const {
1897   if (isFrameLoadOpcode(MI->getOpcode())) {
1898     unsigned Reg;
1899     if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
1900       return Reg;
1901     // Check for post-frame index elimination operations
1902     const MachineMemOperand *Dummy;
1903     return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
1904   }
1905   return 0;
1908 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
1909                                           int &FrameIndex) const {
1910   if (isFrameStoreOpcode(MI->getOpcode()))
1911     if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
1912         isFrameOperand(MI, 0, FrameIndex))
1913       return MI->getOperand(X86::AddrNumOperands).getReg();
1914   return 0;
1917 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
1918                                                 int &FrameIndex) const {
1919   if (isFrameStoreOpcode(MI->getOpcode())) {
1920     unsigned Reg;
1921     if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
1922       return Reg;
1923     // Check for post-frame index elimination operations
1924     const MachineMemOperand *Dummy;
1925     return hasStoreToStackSlot(MI, Dummy, FrameIndex);
1926   }
1927   return 0;
1930 /// regIsPICBase - Return true if register is PIC base (i.e.g defined by
1931 /// X86::MOVPC32r.
1932 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
1933   // Don't waste compile time scanning use-def chains of physregs.
1934   if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
1935     return false;
1936   bool isPICBase = false;
1937   for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
1938          E = MRI.def_instr_end(); I != E; ++I) {
1939     MachineInstr *DefMI = &*I;
1940     if (DefMI->getOpcode() != X86::MOVPC32r)
1941       return false;
1942     assert(!isPICBase && "More than one PIC base?");
1943     isPICBase = true;
1944   }
1945   return isPICBase;
1948 bool
1949 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
1950                                                 AliasAnalysis *AA) const {
1951   switch (MI->getOpcode()) {
1952   default: break;
1953   case X86::MOV8rm:
1954   case X86::MOV16rm:
1955   case X86::MOV32rm:
1956   case X86::MOV64rm:
1957   case X86::LD_Fp64m:
1958   case X86::MOVSSrm:
1959   case X86::MOVSDrm:
1960   case X86::MOVAPSrm:
1961   case X86::MOVUPSrm:
1962   case X86::MOVAPDrm:
1963   case X86::MOVDQArm:
1964   case X86::MOVDQUrm:
1965   case X86::VMOVSSrm:
1966   case X86::VMOVSDrm:
1967   case X86::VMOVAPSrm:
1968   case X86::VMOVUPSrm:
1969   case X86::VMOVAPDrm:
1970   case X86::VMOVDQArm:
1971   case X86::VMOVDQUrm:
1972   case X86::VMOVAPSYrm:
1973   case X86::VMOVUPSYrm:
1974   case X86::VMOVAPDYrm:
1975   case X86::VMOVDQAYrm:
1976   case X86::VMOVDQUYrm:
1977   case X86::MMX_MOVD64rm:
1978   case X86::MMX_MOVQ64rm:
1979   case X86::FsVMOVAPSrm:
1980   case X86::FsVMOVAPDrm:
1981   case X86::FsMOVAPSrm:
1982   case X86::FsMOVAPDrm: {
1983     // Loads from constant pools are trivially rematerializable.
1984     if (MI->getOperand(1+X86::AddrBaseReg).isReg() &&
1985         MI->getOperand(1+X86::AddrScaleAmt).isImm() &&
1986         MI->getOperand(1+X86::AddrIndexReg).isReg() &&
1987         MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 &&
1988         MI->isInvariantLoad(AA)) {
1989       unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg();
1990       if (BaseReg == 0 || BaseReg == X86::RIP)
1991         return true;
1992       // Allow re-materialization of PIC load.
1993       if (!ReMatPICStubLoad && MI->getOperand(1+X86::AddrDisp).isGlobal())
1994         return false;
1995       const MachineFunction &MF = *MI->getParent()->getParent();
1996       const MachineRegisterInfo &MRI = MF.getRegInfo();
1997       return regIsPICBase(BaseReg, MRI);
1998     }
1999     return false;
2000   }
2002   case X86::LEA32r:
2003   case X86::LEA64r: {
2004     if (MI->getOperand(1+X86::AddrScaleAmt).isImm() &&
2005         MI->getOperand(1+X86::AddrIndexReg).isReg() &&
2006         MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 &&
2007         !MI->getOperand(1+X86::AddrDisp).isReg()) {
2008       // lea fi#, lea GV, etc. are all rematerializable.
2009       if (!MI->getOperand(1+X86::AddrBaseReg).isReg())
2010         return true;
2011       unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg();
2012       if (BaseReg == 0)
2013         return true;
2014       // Allow re-materialization of lea PICBase + x.
2015       const MachineFunction &MF = *MI->getParent()->getParent();
2016       const MachineRegisterInfo &MRI = MF.getRegInfo();
2017       return regIsPICBase(BaseReg, MRI);
2018     }
2019     return false;
2020   }
2021   }
2023   // All other instructions marked M_REMATERIALIZABLE are always trivially
2024   // rematerializable.
2025   return true;
2028 bool X86InstrInfo::isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
2029                                          MachineBasicBlock::iterator I) const {
2030   MachineBasicBlock::iterator E = MBB.end();
2032   // For compile time consideration, if we are not able to determine the
2033   // safety after visiting 4 instructions in each direction, we will assume
2034   // it's not safe.
2035   MachineBasicBlock::iterator Iter = I;
2036   for (unsigned i = 0; Iter != E && i < 4; ++i) {
2037     bool SeenDef = false;
2038     for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2039       MachineOperand &MO = Iter->getOperand(j);
2040       if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2041         SeenDef = true;
2042       if (!MO.isReg())
2043         continue;
2044       if (MO.getReg() == X86::EFLAGS) {
2045         if (MO.isUse())
2046           return false;
2047         SeenDef = true;
2048       }
2049     }
2051     if (SeenDef)
2052       // This instruction defines EFLAGS, no need to look any further.
2053       return true;
2054     ++Iter;
2055     // Skip over DBG_VALUE.
2056     while (Iter != E && Iter->isDebugValue())
2057       ++Iter;
2058   }
2060   // It is safe to clobber EFLAGS at the end of a block of no successor has it
2061   // live in.
2062   if (Iter == E) {
2063     for (MachineBasicBlock::succ_iterator SI = MBB.succ_begin(),
2064            SE = MBB.succ_end(); SI != SE; ++SI)
2065       if ((*SI)->isLiveIn(X86::EFLAGS))
2066         return false;
2067     return true;
2068   }
2070   MachineBasicBlock::iterator B = MBB.begin();
2071   Iter = I;
2072   for (unsigned i = 0; i < 4; ++i) {
2073     // If we make it to the beginning of the block, it's safe to clobber
2074     // EFLAGS iff EFLAGS is not live-in.
2075     if (Iter == B)
2076       return !MBB.isLiveIn(X86::EFLAGS);
2078     --Iter;
2079     // Skip over DBG_VALUE.
2080     while (Iter != B && Iter->isDebugValue())
2081       --Iter;
2083     bool SawKill = false;
2084     for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2085       MachineOperand &MO = Iter->getOperand(j);
2086       // A register mask may clobber EFLAGS, but we should still look for a
2087       // live EFLAGS def.
2088       if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2089         SawKill = true;
2090       if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
2091         if (MO.isDef()) return MO.isDead();
2092         if (MO.isKill()) SawKill = true;
2093       }
2094     }
2096     if (SawKill)
2097       // This instruction kills EFLAGS and doesn't redefine it, so
2098       // there's no need to look further.
2099       return true;
2100   }
2102   // Conservative answer.
2103   return false;
2106 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
2107                                  MachineBasicBlock::iterator I,
2108                                  unsigned DestReg, unsigned SubIdx,
2109                                  const MachineInstr *Orig,
2110                                  const TargetRegisterInfo &TRI) const {
2111   // MOV32r0 is implemented with a xor which clobbers condition code.
2112   // Re-materialize it as movri instructions to avoid side effects.
2113   unsigned Opc = Orig->getOpcode();
2114   if (Opc == X86::MOV32r0 && !isSafeToClobberEFLAGS(MBB, I)) {
2115     DebugLoc DL = Orig->getDebugLoc();
2116     BuildMI(MBB, I, DL, get(X86::MOV32ri)).addOperand(Orig->getOperand(0))
2117       .addImm(0);
2118   } else {
2119     MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
2120     MBB.insert(I, MI);
2121   }
2123   MachineInstr *NewMI = std::prev(I);
2124   NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
2127 /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
2128 /// is not marked dead.
2129 static bool hasLiveCondCodeDef(MachineInstr *MI) {
2130   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2131     MachineOperand &MO = MI->getOperand(i);
2132     if (MO.isReg() && MO.isDef() &&
2133         MO.getReg() == X86::EFLAGS && !MO.isDead()) {
2134       return true;
2135     }
2136   }
2137   return false;
2140 /// getTruncatedShiftCount - check whether the shift count for a machine operand
2141 /// is non-zero.
2142 inline static unsigned getTruncatedShiftCount(MachineInstr *MI,
2143                                               unsigned ShiftAmtOperandIdx) {
2144   // The shift count is six bits with the REX.W prefix and five bits without.
2145   unsigned ShiftCountMask = (MI->getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
2146   unsigned Imm = MI->getOperand(ShiftAmtOperandIdx).getImm();
2147   return Imm & ShiftCountMask;
2150 /// isTruncatedShiftCountForLEA - check whether the given shift count is appropriate
2151 /// can be represented by a LEA instruction.
2152 inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
2153   // Left shift instructions can be transformed into load-effective-address
2154   // instructions if we can encode them appropriately.
2155   // A LEA instruction utilizes a SIB byte to encode it's scale factor.
2156   // The SIB.scale field is two bits wide which means that we can encode any
2157   // shift amount less than 4.
2158   return ShAmt < 4 && ShAmt > 0;
2161 bool X86InstrInfo::classifyLEAReg(MachineInstr *MI, const MachineOperand &Src,
2162                                   unsigned Opc, bool AllowSP,
2163                                   unsigned &NewSrc, bool &isKill, bool &isUndef,
2164                                   MachineOperand &ImplicitOp) const {
2165   MachineFunction &MF = *MI->getParent()->getParent();
2166   const TargetRegisterClass *RC;
2167   if (AllowSP) {
2168     RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
2169   } else {
2170     RC = Opc != X86::LEA32r ?
2171       &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
2172   }
2173   unsigned SrcReg = Src.getReg();
2175   // For both LEA64 and LEA32 the register already has essentially the right
2176   // type (32-bit or 64-bit) we may just need to forbid SP.
2177   if (Opc != X86::LEA64_32r) {
2178     NewSrc = SrcReg;
2179     isKill = Src.isKill();
2180     isUndef = Src.isUndef();
2182     if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
2183         !MF.getRegInfo().constrainRegClass(NewSrc, RC))
2184       return false;
2186     return true;
2187   }
2189   // This is for an LEA64_32r and incoming registers are 32-bit. One way or
2190   // another we need to add 64-bit registers to the final MI.
2191   if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
2192     ImplicitOp = Src;
2193     ImplicitOp.setImplicit();
2195     NewSrc = getX86SubSuperRegister(Src.getReg(), MVT::i64);
2196     MachineBasicBlock::LivenessQueryResult LQR =
2197       MI->getParent()->computeRegisterLiveness(&getRegisterInfo(), NewSrc, MI);
2199     switch (LQR) {
2200     case MachineBasicBlock::LQR_Unknown:
2201       // We can't give sane liveness flags to the instruction, abandon LEA
2202       // formation.
2203       return false;
2204     case MachineBasicBlock::LQR_Live:
2205       isKill = MI->killsRegister(SrcReg);
2206       isUndef = false;
2207       break;
2208     default:
2209       // The physreg itself is dead, so we have to use it as an <undef>.
2210       isKill = false;
2211       isUndef = true;
2212       break;
2213     }
2214   } else {
2215     // Virtual register of the wrong class, we have to create a temporary 64-bit
2216     // vreg to feed into the LEA.
2217     NewSrc = MF.getRegInfo().createVirtualRegister(RC);
2218     BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
2219             get(TargetOpcode::COPY))
2220       .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
2221         .addOperand(Src);
2223     // Which is obviously going to be dead after we're done with it.
2224     isKill = true;
2225     isUndef = false;
2226   }
2228   // We've set all the parameters without issue.
2229   return true;
2232 /// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when
2233 /// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting
2234 /// to a 32-bit superregister and then truncating back down to a 16-bit
2235 /// subregister.
2236 MachineInstr *
2237 X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
2238                                            MachineFunction::iterator &MFI,
2239                                            MachineBasicBlock::iterator &MBBI,
2240                                            LiveVariables *LV) const {
2241   MachineInstr *MI = MBBI;
2242   unsigned Dest = MI->getOperand(0).getReg();
2243   unsigned Src = MI->getOperand(1).getReg();
2244   bool isDead = MI->getOperand(0).isDead();
2245   bool isKill = MI->getOperand(1).isKill();
2247   MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
2248   unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
2249   unsigned Opc, leaInReg;
2250   if (Subtarget.is64Bit()) {
2251     Opc = X86::LEA64_32r;
2252     leaInReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2253   } else {
2254     Opc = X86::LEA32r;
2255     leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2256   }
2258   // Build and insert into an implicit UNDEF value. This is OK because
2259   // well be shifting and then extracting the lower 16-bits.
2260   // This has the potential to cause partial register stall. e.g.
2261   //   movw    (%rbp,%rcx,2), %dx
2262   //   leal    -65(%rdx), %esi
2263   // But testing has shown this *does* help performance in 64-bit mode (at
2264   // least on modern x86 machines).
2265   BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
2266   MachineInstr *InsMI =
2267     BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
2268     .addReg(leaInReg, RegState::Define, X86::sub_16bit)
2269     .addReg(Src, getKillRegState(isKill));
2271   MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
2272                                     get(Opc), leaOutReg);
2273   switch (MIOpc) {
2274   default: llvm_unreachable("Unreachable!");
2275   case X86::SHL16ri: {
2276     unsigned ShAmt = MI->getOperand(2).getImm();
2277     MIB.addReg(0).addImm(1 << ShAmt)
2278        .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
2279     break;
2280   }
2281   case X86::INC16r:
2282     addRegOffset(MIB, leaInReg, true, 1);
2283     break;
2284   case X86::DEC16r:
2285     addRegOffset(MIB, leaInReg, true, -1);
2286     break;
2287   case X86::ADD16ri:
2288   case X86::ADD16ri8:
2289   case X86::ADD16ri_DB:
2290   case X86::ADD16ri8_DB:
2291     addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
2292     break;
2293   case X86::ADD16rr:
2294   case X86::ADD16rr_DB: {
2295     unsigned Src2 = MI->getOperand(2).getReg();
2296     bool isKill2 = MI->getOperand(2).isKill();
2297     unsigned leaInReg2 = 0;
2298     MachineInstr *InsMI2 = nullptr;
2299     if (Src == Src2) {
2300       // ADD16rr %reg1028<kill>, %reg1028
2301       // just a single insert_subreg.
2302       addRegReg(MIB, leaInReg, true, leaInReg, false);
2303     } else {
2304       if (Subtarget.is64Bit())
2305         leaInReg2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2306       else
2307         leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2308       // Build and insert into an implicit UNDEF value. This is OK because
2309       // well be shifting and then extracting the lower 16-bits.
2310       BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2);
2311       InsMI2 =
2312         BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
2313         .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
2314         .addReg(Src2, getKillRegState(isKill2));
2315       addRegReg(MIB, leaInReg, true, leaInReg2, true);
2316     }
2317     if (LV && isKill2 && InsMI2)
2318       LV->replaceKillInstruction(Src2, MI, InsMI2);
2319     break;
2320   }
2321   }
2323   MachineInstr *NewMI = MIB;
2324   MachineInstr *ExtMI =
2325     BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
2326     .addReg(Dest, RegState::Define | getDeadRegState(isDead))
2327     .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
2329   if (LV) {
2330     // Update live variables
2331     LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
2332     LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
2333     if (isKill)
2334       LV->replaceKillInstruction(Src, MI, InsMI);
2335     if (isDead)
2336       LV->replaceKillInstruction(Dest, MI, ExtMI);
2337   }
2339   return ExtMI;
2342 /// convertToThreeAddress - This method must be implemented by targets that
2343 /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
2344 /// may be able to convert a two-address instruction into a true
2345 /// three-address instruction on demand.  This allows the X86 target (for
2346 /// example) to convert ADD and SHL instructions into LEA instructions if they
2347 /// would require register copies due to two-addressness.
2348 ///
2349 /// This method returns a null pointer if the transformation cannot be
2350 /// performed, otherwise it returns the new instruction.
2351 ///
2352 MachineInstr *
2353 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
2354                                     MachineBasicBlock::iterator &MBBI,
2355                                     LiveVariables *LV) const {
2356   MachineInstr *MI = MBBI;
2358   // The following opcodes also sets the condition code register(s). Only
2359   // convert them to equivalent lea if the condition code register def's
2360   // are dead!
2361   if (hasLiveCondCodeDef(MI))
2362     return nullptr;
2364   MachineFunction &MF = *MI->getParent()->getParent();
2365   // All instructions input are two-addr instructions.  Get the known operands.
2366   const MachineOperand &Dest = MI->getOperand(0);
2367   const MachineOperand &Src = MI->getOperand(1);
2369   MachineInstr *NewMI = nullptr;
2370   // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's.  When
2371   // we have better subtarget support, enable the 16-bit LEA generation here.
2372   // 16-bit LEA is also slow on Core2.
2373   bool DisableLEA16 = true;
2374   bool is64Bit = Subtarget.is64Bit();
2376   unsigned MIOpc = MI->getOpcode();
2377   switch (MIOpc) {
2378   default: return nullptr;
2379   case X86::SHL64ri: {
2380     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2381     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2382     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2384     // LEA can't handle RSP.
2385     if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
2386         !MF.getRegInfo().constrainRegClass(Src.getReg(),
2387                                            &X86::GR64_NOSPRegClass))
2388       return nullptr;
2390     NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2391       .addOperand(Dest)
2392       .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
2393     break;
2394   }
2395   case X86::SHL32ri: {
2396     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2397     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2398     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2400     unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2402     // LEA can't handle ESP.
2403     bool isKill, isUndef;
2404     unsigned SrcReg;
2405     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2406     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2407                         SrcReg, isKill, isUndef, ImplicitOp))
2408       return nullptr;
2410     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2411       .addOperand(Dest)
2412       .addReg(0).addImm(1 << ShAmt)
2413       .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
2414       .addImm(0).addReg(0);
2415     if (ImplicitOp.getReg() != 0)
2416       MIB.addOperand(ImplicitOp);
2417     NewMI = MIB;
2419     break;
2420   }
2421   case X86::SHL16ri: {
2422     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2423     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2424     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2426     if (DisableLEA16)
2427       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : nullptr;
2428     NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2429       .addOperand(Dest)
2430       .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
2431     break;
2432   }
2433   case X86::INC64r:
2434   case X86::INC32r: {
2435     assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2436     unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
2437       : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2438     bool isKill, isUndef;
2439     unsigned SrcReg;
2440     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2441     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2442                         SrcReg, isKill, isUndef, ImplicitOp))
2443       return nullptr;
2445     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2446         .addOperand(Dest)
2447         .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef));
2448     if (ImplicitOp.getReg() != 0)
2449       MIB.addOperand(ImplicitOp);
2451     NewMI = addOffset(MIB, 1);
2452     break;
2453   }
2454   case X86::INC16r:
2455     if (DisableLEA16)
2456       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2457                      : nullptr;
2458     assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2459     NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2460                       .addOperand(Dest).addOperand(Src), 1);
2461     break;
2462   case X86::DEC64r:
2463   case X86::DEC32r: {
2464     assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2465     unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
2466       : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2468     bool isKill, isUndef;
2469     unsigned SrcReg;
2470     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2471     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2472                         SrcReg, isKill, isUndef, ImplicitOp))
2473       return nullptr;
2475     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2476         .addOperand(Dest)
2477         .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2478     if (ImplicitOp.getReg() != 0)
2479       MIB.addOperand(ImplicitOp);
2481     NewMI = addOffset(MIB, -1);
2483     break;
2484   }
2485   case X86::DEC16r:
2486     if (DisableLEA16)
2487       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2488                      : nullptr;
2489     assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2490     NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2491                       .addOperand(Dest).addOperand(Src), -1);
2492     break;
2493   case X86::ADD64rr:
2494   case X86::ADD64rr_DB:
2495   case X86::ADD32rr:
2496   case X86::ADD32rr_DB: {
2497     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2498     unsigned Opc;
2499     if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
2500       Opc = X86::LEA64r;
2501     else
2502       Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2504     bool isKill, isUndef;
2505     unsigned SrcReg;
2506     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2507     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2508                         SrcReg, isKill, isUndef, ImplicitOp))
2509       return nullptr;
2511     const MachineOperand &Src2 = MI->getOperand(2);
2512     bool isKill2, isUndef2;
2513     unsigned SrcReg2;
2514     MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
2515     if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
2516                         SrcReg2, isKill2, isUndef2, ImplicitOp2))
2517       return nullptr;
2519     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2520       .addOperand(Dest);
2521     if (ImplicitOp.getReg() != 0)
2522       MIB.addOperand(ImplicitOp);
2523     if (ImplicitOp2.getReg() != 0)
2524       MIB.addOperand(ImplicitOp2);
2526     NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
2528     // Preserve undefness of the operands.
2529     NewMI->getOperand(1).setIsUndef(isUndef);
2530     NewMI->getOperand(3).setIsUndef(isUndef2);
2532     if (LV && Src2.isKill())
2533       LV->replaceKillInstruction(SrcReg2, MI, NewMI);
2534     break;
2535   }
2536   case X86::ADD16rr:
2537   case X86::ADD16rr_DB: {
2538     if (DisableLEA16)
2539       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2540                      : nullptr;
2541     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2542     unsigned Src2 = MI->getOperand(2).getReg();
2543     bool isKill2 = MI->getOperand(2).isKill();
2544     NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2545                       .addOperand(Dest),
2546                       Src.getReg(), Src.isKill(), Src2, isKill2);
2548     // Preserve undefness of the operands.
2549     bool isUndef = MI->getOperand(1).isUndef();
2550     bool isUndef2 = MI->getOperand(2).isUndef();
2551     NewMI->getOperand(1).setIsUndef(isUndef);
2552     NewMI->getOperand(3).setIsUndef(isUndef2);
2554     if (LV && isKill2)
2555       LV->replaceKillInstruction(Src2, MI, NewMI);
2556     break;
2557   }
2558   case X86::ADD64ri32:
2559   case X86::ADD64ri8:
2560   case X86::ADD64ri32_DB:
2561   case X86::ADD64ri8_DB:
2562     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2563     NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2564                       .addOperand(Dest).addOperand(Src),
2565                       MI->getOperand(2).getImm());
2566     break;
2567   case X86::ADD32ri:
2568   case X86::ADD32ri8:
2569   case X86::ADD32ri_DB:
2570   case X86::ADD32ri8_DB: {
2571     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2572     unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2574     bool isKill, isUndef;
2575     unsigned SrcReg;
2576     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2577     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2578                         SrcReg, isKill, isUndef, ImplicitOp))
2579       return nullptr;
2581     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2582         .addOperand(Dest)
2583         .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2584     if (ImplicitOp.getReg() != 0)
2585       MIB.addOperand(ImplicitOp);
2587     NewMI = addOffset(MIB, MI->getOperand(2).getImm());
2588     break;
2589   }
2590   case X86::ADD16ri:
2591   case X86::ADD16ri8:
2592   case X86::ADD16ri_DB:
2593   case X86::ADD16ri8_DB:
2594     if (DisableLEA16)
2595       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2596                      : nullptr;
2597     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2598     NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2599                       .addOperand(Dest).addOperand(Src),
2600                       MI->getOperand(2).getImm());
2601     break;
2602   }
2604   if (!NewMI) return nullptr;
2606   if (LV) {  // Update live variables
2607     if (Src.isKill())
2608       LV->replaceKillInstruction(Src.getReg(), MI, NewMI);
2609     if (Dest.isDead())
2610       LV->replaceKillInstruction(Dest.getReg(), MI, NewMI);
2611   }
2613   MFI->insert(MBBI, NewMI);          // Insert the new inst
2614   return NewMI;
2617 /// commuteInstruction - We have a few instructions that must be hacked on to
2618 /// commute them.
2619 ///
2620 MachineInstr *
2621 X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
2622   switch (MI->getOpcode()) {
2623   case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
2624   case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
2625   case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
2626   case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
2627   case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
2628   case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
2629     unsigned Opc;
2630     unsigned Size;
2631     switch (MI->getOpcode()) {
2632     default: llvm_unreachable("Unreachable!");
2633     case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
2634     case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
2635     case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
2636     case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
2637     case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
2638     case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
2639     }
2640     unsigned Amt = MI->getOperand(3).getImm();
2641     if (NewMI) {
2642       MachineFunction &MF = *MI->getParent()->getParent();
2643       MI = MF.CloneMachineInstr(MI);
2644       NewMI = false;
2645     }
2646     MI->setDesc(get(Opc));
2647     MI->getOperand(3).setImm(Size-Amt);
2648     return TargetInstrInfo::commuteInstruction(MI, NewMI);
2649   }
2650   case X86::BLENDPDrri:
2651   case X86::BLENDPSrri:
2652   case X86::PBLENDWrri:
2653   case X86::VBLENDPDrri:
2654   case X86::VBLENDPSrri:
2655   case X86::VBLENDPDYrri:
2656   case X86::VBLENDPSYrri:
2657   case X86::VPBLENDDrri:
2658   case X86::VPBLENDWrri:
2659   case X86::VPBLENDDYrri:
2660   case X86::VPBLENDWYrri:{
2661     unsigned Mask;
2662     switch (MI->getOpcode()) {
2663     default: llvm_unreachable("Unreachable!");
2664     case X86::BLENDPDrri:    Mask = 0x03; break;
2665     case X86::BLENDPSrri:    Mask = 0x0F; break;
2666     case X86::PBLENDWrri:    Mask = 0xFF; break;
2667     case X86::VBLENDPDrri:   Mask = 0x03; break;
2668     case X86::VBLENDPSrri:   Mask = 0x0F; break;
2669     case X86::VBLENDPDYrri:  Mask = 0x0F; break;
2670     case X86::VBLENDPSYrri:  Mask = 0xFF; break;
2671     case X86::VPBLENDDrri:   Mask = 0x0F; break;
2672     case X86::VPBLENDWrri:   Mask = 0xFF; break;
2673     case X86::VPBLENDDYrri:  Mask = 0xFF; break;
2674     case X86::VPBLENDWYrri:  Mask = 0xFF; break;
2675     }
2676     // Only the least significant bits of Imm are used.
2677     unsigned Imm = MI->getOperand(3).getImm() & Mask;
2678     if (NewMI) {
2679       MachineFunction &MF = *MI->getParent()->getParent();
2680       MI = MF.CloneMachineInstr(MI);
2681       NewMI = false;
2682     }
2683     MI->getOperand(3).setImm(Mask ^ Imm);
2684     return TargetInstrInfo::commuteInstruction(MI, NewMI);
2685   }
2686   case X86::CMOVB16rr:  case X86::CMOVB32rr:  case X86::CMOVB64rr:
2687   case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
2688   case X86::CMOVE16rr:  case X86::CMOVE32rr:  case X86::CMOVE64rr:
2689   case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
2690   case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
2691   case X86::CMOVA16rr:  case X86::CMOVA32rr:  case X86::CMOVA64rr:
2692   case X86::CMOVL16rr:  case X86::CMOVL32rr:  case X86::CMOVL64rr:
2693   case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
2694   case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
2695   case X86::CMOVG16rr:  case X86::CMOVG32rr:  case X86::CMOVG64rr:
2696   case X86::CMOVS16rr:  case X86::CMOVS32rr:  case X86::CMOVS64rr:
2697   case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
2698   case X86::CMOVP16rr:  case X86::CMOVP32rr:  case X86::CMOVP64rr:
2699   case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
2700   case X86::CMOVO16rr:  case X86::CMOVO32rr:  case X86::CMOVO64rr:
2701   case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
2702     unsigned Opc;
2703     switch (MI->getOpcode()) {
2704     default: llvm_unreachable("Unreachable!");
2705     case X86::CMOVB16rr:  Opc = X86::CMOVAE16rr; break;
2706     case X86::CMOVB32rr:  Opc = X86::CMOVAE32rr; break;
2707     case X86::CMOVB64rr:  Opc = X86::CMOVAE64rr; break;
2708     case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
2709     case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
2710     case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
2711     case X86::CMOVE16rr:  Opc = X86::CMOVNE16rr; break;
2712     case X86::CMOVE32rr:  Opc = X86::CMOVNE32rr; break;
2713     case X86::CMOVE64rr:  Opc = X86::CMOVNE64rr; break;
2714     case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
2715     case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
2716     case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
2717     case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
2718     case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
2719     case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
2720     case X86::CMOVA16rr:  Opc = X86::CMOVBE16rr; break;
2721     case X86::CMOVA32rr:  Opc = X86::CMOVBE32rr; break;
2722     case X86::CMOVA64rr:  Opc = X86::CMOVBE64rr; break;
2723     case X86::CMOVL16rr:  Opc = X86::CMOVGE16rr; break;
2724     case X86::CMOVL32rr:  Opc = X86::CMOVGE32rr; break;
2725     case X86::CMOVL64rr:  Opc = X86::CMOVGE64rr; break;
2726     case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
2727     case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
2728     case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
2729     case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
2730     case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
2731     case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
2732     case X86::CMOVG16rr:  Opc = X86::CMOVLE16rr; break;
2733     case X86::CMOVG32rr:  Opc = X86::CMOVLE32rr; break;
2734     case X86::CMOVG64rr:  Opc = X86::CMOVLE64rr; break;
2735     case X86::CMOVS16rr:  Opc = X86::CMOVNS16rr; break;
2736     case X86::CMOVS32rr:  Opc = X86::CMOVNS32rr; break;
2737     case X86::CMOVS64rr:  Opc = X86::CMOVNS64rr; break;
2738     case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
2739     case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
2740     case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
2741     case X86::CMOVP16rr:  Opc = X86::CMOVNP16rr; break;
2742     case X86::CMOVP32rr:  Opc = X86::CMOVNP32rr; break;
2743     case X86::CMOVP64rr:  Opc = X86::CMOVNP64rr; break;
2744     case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
2745     case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
2746     case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
2747     case X86::CMOVO16rr:  Opc = X86::CMOVNO16rr; break;
2748     case X86::CMOVO32rr:  Opc = X86::CMOVNO32rr; break;
2749     case X86::CMOVO64rr:  Opc = X86::CMOVNO64rr; break;
2750     case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
2751     case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
2752     case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
2753     }
2754     if (NewMI) {
2755       MachineFunction &MF = *MI->getParent()->getParent();
2756       MI = MF.CloneMachineInstr(MI);
2757       NewMI = false;
2758     }
2759     MI->setDesc(get(Opc));
2760     // Fallthrough intended.
2761   }
2762   default:
2763     return TargetInstrInfo::commuteInstruction(MI, NewMI);
2764   }
2767 bool X86InstrInfo::findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
2768                                          unsigned &SrcOpIdx2) const {
2769   switch (MI->getOpcode()) {
2770     case X86::BLENDPDrri:
2771     case X86::BLENDPSrri:
2772     case X86::PBLENDWrri:
2773     case X86::VBLENDPDrri:
2774     case X86::VBLENDPSrri:
2775     case X86::VBLENDPDYrri:
2776     case X86::VBLENDPSYrri:
2777     case X86::VPBLENDDrri:
2778     case X86::VPBLENDDYrri:
2779     case X86::VPBLENDWrri:
2780     case X86::VPBLENDWYrri:
2781       SrcOpIdx1 = 1;
2782       SrcOpIdx2 = 2;
2783       return true;
2784     case X86::VFMADDPDr231r:
2785     case X86::VFMADDPSr231r:
2786     case X86::VFMADDSDr231r:
2787     case X86::VFMADDSSr231r:
2788     case X86::VFMSUBPDr231r:
2789     case X86::VFMSUBPSr231r:
2790     case X86::VFMSUBSDr231r:
2791     case X86::VFMSUBSSr231r:
2792     case X86::VFNMADDPDr231r:
2793     case X86::VFNMADDPSr231r:
2794     case X86::VFNMADDSDr231r:
2795     case X86::VFNMADDSSr231r:
2796     case X86::VFNMSUBPDr231r:
2797     case X86::VFNMSUBPSr231r:
2798     case X86::VFNMSUBSDr231r:
2799     case X86::VFNMSUBSSr231r:
2800     case X86::VFMADDPDr231rY:
2801     case X86::VFMADDPSr231rY:
2802     case X86::VFMSUBPDr231rY:
2803     case X86::VFMSUBPSr231rY:
2804     case X86::VFNMADDPDr231rY:
2805     case X86::VFNMADDPSr231rY:
2806     case X86::VFNMSUBPDr231rY:
2807     case X86::VFNMSUBPSr231rY:
2808       SrcOpIdx1 = 2;
2809       SrcOpIdx2 = 3;
2810       return true;
2811     default:
2812       return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2813   }
2816 static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) {
2817   switch (BrOpc) {
2818   default: return X86::COND_INVALID;
2819   case X86::JE_1:  return X86::COND_E;
2820   case X86::JNE_1: return X86::COND_NE;
2821   case X86::JL_1:  return X86::COND_L;
2822   case X86::JLE_1: return X86::COND_LE;
2823   case X86::JG_1:  return X86::COND_G;
2824   case X86::JGE_1: return X86::COND_GE;
2825   case X86::JB_1:  return X86::COND_B;
2826   case X86::JBE_1: return X86::COND_BE;
2827   case X86::JA_1:  return X86::COND_A;
2828   case X86::JAE_1: return X86::COND_AE;
2829   case X86::JS_1:  return X86::COND_S;
2830   case X86::JNS_1: return X86::COND_NS;
2831   case X86::JP_1:  return X86::COND_P;
2832   case X86::JNP_1: return X86::COND_NP;
2833   case X86::JO_1:  return X86::COND_O;
2834   case X86::JNO_1: return X86::COND_NO;
2835   }
2838 /// getCondFromSETOpc - return condition code of a SET opcode.
2839 static X86::CondCode getCondFromSETOpc(unsigned Opc) {
2840   switch (Opc) {
2841   default: return X86::COND_INVALID;
2842   case X86::SETAr:  case X86::SETAm:  return X86::COND_A;
2843   case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
2844   case X86::SETBr:  case X86::SETBm:  return X86::COND_B;
2845   case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
2846   case X86::SETEr:  case X86::SETEm:  return X86::COND_E;
2847   case X86::SETGr:  case X86::SETGm:  return X86::COND_G;
2848   case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
2849   case X86::SETLr:  case X86::SETLm:  return X86::COND_L;
2850   case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
2851   case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
2852   case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
2853   case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
2854   case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
2855   case X86::SETOr:  case X86::SETOm:  return X86::COND_O;
2856   case X86::SETPr:  case X86::SETPm:  return X86::COND_P;
2857   case X86::SETSr:  case X86::SETSm:  return X86::COND_S;
2858   }
2861 /// getCondFromCmovOpc - return condition code of a CMov opcode.
2862 X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) {
2863   switch (Opc) {
2864   default: return X86::COND_INVALID;
2865   case X86::CMOVA16rm:  case X86::CMOVA16rr:  case X86::CMOVA32rm:
2866   case X86::CMOVA32rr:  case X86::CMOVA64rm:  case X86::CMOVA64rr:
2867     return X86::COND_A;
2868   case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
2869   case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
2870     return X86::COND_AE;
2871   case X86::CMOVB16rm:  case X86::CMOVB16rr:  case X86::CMOVB32rm:
2872   case X86::CMOVB32rr:  case X86::CMOVB64rm:  case X86::CMOVB64rr:
2873     return X86::COND_B;
2874   case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
2875   case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
2876     return X86::COND_BE;
2877   case X86::CMOVE16rm:  case X86::CMOVE16rr:  case X86::CMOVE32rm:
2878   case X86::CMOVE32rr:  case X86::CMOVE64rm:  case X86::CMOVE64rr:
2879     return X86::COND_E;
2880   case X86::CMOVG16rm:  case X86::CMOVG16rr:  case X86::CMOVG32rm:
2881   case X86::CMOVG32rr:  case X86::CMOVG64rm:  case X86::CMOVG64rr:
2882     return X86::COND_G;
2883   case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
2884   case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
2885     return X86::COND_GE;
2886   case X86::CMOVL16rm:  case X86::CMOVL16rr:  case X86::CMOVL32rm:
2887   case X86::CMOVL32rr:  case X86::CMOVL64rm:  case X86::CMOVL64rr:
2888     return X86::COND_L;
2889   case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
2890   case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
2891     return X86::COND_LE;
2892   case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
2893   case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
2894     return X86::COND_NE;
2895   case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
2896   case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
2897     return X86::COND_NO;
2898   case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
2899   case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
2900     return X86::COND_NP;
2901   case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
2902   case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
2903     return X86::COND_NS;
2904   case X86::CMOVO16rm:  case X86::CMOVO16rr:  case X86::CMOVO32rm:
2905   case X86::CMOVO32rr:  case X86::CMOVO64rm:  case X86::CMOVO64rr:
2906     return X86::COND_O;
2907   case X86::CMOVP16rm:  case X86::CMOVP16rr:  case X86::CMOVP32rm:
2908   case X86::CMOVP32rr:  case X86::CMOVP64rm:  case X86::CMOVP64rr:
2909     return X86::COND_P;
2910   case X86::CMOVS16rm:  case X86::CMOVS16rr:  case X86::CMOVS32rm:
2911   case X86::CMOVS32rr:  case X86::CMOVS64rm:  case X86::CMOVS64rr:
2912     return X86::COND_S;
2913   }
2916 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
2917   switch (CC) {
2918   default: llvm_unreachable("Illegal condition code!");
2919   case X86::COND_E:  return X86::JE_1;
2920   case X86::COND_NE: return X86::JNE_1;
2921   case X86::COND_L:  return X86::JL_1;
2922   case X86::COND_LE: return X86::JLE_1;
2923   case X86::COND_G:  return X86::JG_1;
2924   case X86::COND_GE: return X86::JGE_1;
2925   case X86::COND_B:  return X86::JB_1;
2926   case X86::COND_BE: return X86::JBE_1;
2927   case X86::COND_A:  return X86::JA_1;
2928   case X86::COND_AE: return X86::JAE_1;
2929   case X86::COND_S:  return X86::JS_1;
2930   case X86::COND_NS: return X86::JNS_1;
2931   case X86::COND_P:  return X86::JP_1;
2932   case X86::COND_NP: return X86::JNP_1;
2933   case X86::COND_O:  return X86::JO_1;
2934   case X86::COND_NO: return X86::JNO_1;
2935   }
2938 /// GetOppositeBranchCondition - Return the inverse of the specified condition,
2939 /// e.g. turning COND_E to COND_NE.
2940 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
2941   switch (CC) {
2942   default: llvm_unreachable("Illegal condition code!");
2943   case X86::COND_E:  return X86::COND_NE;
2944   case X86::COND_NE: return X86::COND_E;
2945   case X86::COND_L:  return X86::COND_GE;
2946   case X86::COND_LE: return X86::COND_G;
2947   case X86::COND_G:  return X86::COND_LE;
2948   case X86::COND_GE: return X86::COND_L;
2949   case X86::COND_B:  return X86::COND_AE;
2950   case X86::COND_BE: return X86::COND_A;
2951   case X86::COND_A:  return X86::COND_BE;
2952   case X86::COND_AE: return X86::COND_B;
2953   case X86::COND_S:  return X86::COND_NS;
2954   case X86::COND_NS: return X86::COND_S;
2955   case X86::COND_P:  return X86::COND_NP;
2956   case X86::COND_NP: return X86::COND_P;
2957   case X86::COND_O:  return X86::COND_NO;
2958   case X86::COND_NO: return X86::COND_O;
2959   }
2962 /// getSwappedCondition - assume the flags are set by MI(a,b), return
2963 /// the condition code if we modify the instructions such that flags are
2964 /// set by MI(b,a).
2965 static X86::CondCode getSwappedCondition(X86::CondCode CC) {
2966   switch (CC) {
2967   default: return X86::COND_INVALID;
2968   case X86::COND_E:  return X86::COND_E;
2969   case X86::COND_NE: return X86::COND_NE;
2970   case X86::COND_L:  return X86::COND_G;
2971   case X86::COND_LE: return X86::COND_GE;
2972   case X86::COND_G:  return X86::COND_L;
2973   case X86::COND_GE: return X86::COND_LE;
2974   case X86::COND_B:  return X86::COND_A;
2975   case X86::COND_BE: return X86::COND_AE;
2976   case X86::COND_A:  return X86::COND_B;
2977   case X86::COND_AE: return X86::COND_BE;
2978   }
2981 /// getSETFromCond - Return a set opcode for the given condition and
2982 /// whether it has memory operand.
2983 unsigned X86::getSETFromCond(CondCode CC, bool HasMemoryOperand) {
2984   static const uint16_t Opc[16][2] = {
2985     { X86::SETAr,  X86::SETAm  },
2986     { X86::SETAEr, X86::SETAEm },
2987     { X86::SETBr,  X86::SETBm  },
2988     { X86::SETBEr, X86::SETBEm },
2989     { X86::SETEr,  X86::SETEm  },
2990     { X86::SETGr,  X86::SETGm  },
2991     { X86::SETGEr, X86::SETGEm },
2992     { X86::SETLr,  X86::SETLm  },
2993     { X86::SETLEr, X86::SETLEm },
2994     { X86::SETNEr, X86::SETNEm },
2995     { X86::SETNOr, X86::SETNOm },
2996     { X86::SETNPr, X86::SETNPm },
2997     { X86::SETNSr, X86::SETNSm },
2998     { X86::SETOr,  X86::SETOm  },
2999     { X86::SETPr,  X86::SETPm  },
3000     { X86::SETSr,  X86::SETSm  }
3001   };
3003   assert(CC <= LAST_VALID_COND && "Can only handle standard cond codes");
3004   return Opc[CC][HasMemoryOperand ? 1 : 0];
3007 /// getCMovFromCond - Return a cmov opcode for the given condition,
3008 /// register size in bytes, and operand type.
3009 unsigned X86::getCMovFromCond(CondCode CC, unsigned RegBytes,
3010                               bool HasMemoryOperand) {
3011   static const uint16_t Opc[32][3] = {
3012     { X86::CMOVA16rr,  X86::CMOVA32rr,  X86::CMOVA64rr  },
3013     { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
3014     { X86::CMOVB16rr,  X86::CMOVB32rr,  X86::CMOVB64rr  },
3015     { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
3016     { X86::CMOVE16rr,  X86::CMOVE32rr,  X86::CMOVE64rr  },
3017     { X86::CMOVG16rr,  X86::CMOVG32rr,  X86::CMOVG64rr  },
3018     { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
3019     { X86::CMOVL16rr,  X86::CMOVL32rr,  X86::CMOVL64rr  },
3020     { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
3021     { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
3022     { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
3023     { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
3024     { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
3025     { X86::CMOVO16rr,  X86::CMOVO32rr,  X86::CMOVO64rr  },
3026     { X86::CMOVP16rr,  X86::CMOVP32rr,  X86::CMOVP64rr  },
3027     { X86::CMOVS16rr,  X86::CMOVS32rr,  X86::CMOVS64rr  },
3028     { X86::CMOVA16rm,  X86::CMOVA32rm,  X86::CMOVA64rm  },
3029     { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
3030     { X86::CMOVB16rm,  X86::CMOVB32rm,  X86::CMOVB64rm  },
3031     { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
3032     { X86::CMOVE16rm,  X86::CMOVE32rm,  X86::CMOVE64rm  },
3033     { X86::CMOVG16rm,  X86::CMOVG32rm,  X86::CMOVG64rm  },
3034     { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
3035     { X86::CMOVL16rm,  X86::CMOVL32rm,  X86::CMOVL64rm  },
3036     { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
3037     { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
3038     { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
3039     { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
3040     { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
3041     { X86::CMOVO16rm,  X86::CMOVO32rm,  X86::CMOVO64rm  },
3042     { X86::CMOVP16rm,  X86::CMOVP32rm,  X86::CMOVP64rm  },
3043     { X86::CMOVS16rm,  X86::CMOVS32rm,  X86::CMOVS64rm  }
3044   };
3046   assert(CC < 16 && "Can only handle standard cond codes");
3047   unsigned Idx = HasMemoryOperand ? 16+CC : CC;
3048   switch(RegBytes) {
3049   default: llvm_unreachable("Illegal register size!");
3050   case 2: return Opc[Idx][0];
3051   case 4: return Opc[Idx][1];
3052   case 8: return Opc[Idx][2];
3053   }
3056 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
3057   if (!MI->isTerminator()) return false;
3059   // Conditional branch is a special case.
3060   if (MI->isBranch() && !MI->isBarrier())
3061     return true;
3062   if (!MI->isPredicable())
3063     return true;
3064   return !isPredicated(MI);
3067 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
3068                                  MachineBasicBlock *&TBB,
3069                                  MachineBasicBlock *&FBB,
3070                                  SmallVectorImpl<MachineOperand> &Cond,
3071                                  bool AllowModify) const {
3072   // Start from the bottom of the block and work up, examining the
3073   // terminator instructions.
3074   MachineBasicBlock::iterator I = MBB.end();
3075   MachineBasicBlock::iterator UnCondBrIter = MBB.end();
3076   while (I != MBB.begin()) {
3077     --I;
3078     if (I->isDebugValue())
3079       continue;
3081     // Working from the bottom, when we see a non-terminator instruction, we're
3082     // done.
3083     if (!isUnpredicatedTerminator(I))
3084       break;
3086     // A terminator that isn't a branch can't easily be handled by this
3087     // analysis.
3088     if (!I->isBranch())
3089       return true;
3091     // Handle unconditional branches.
3092     if (I->getOpcode() == X86::JMP_1) {
3093       UnCondBrIter = I;
3095       if (!AllowModify) {
3096         TBB = I->getOperand(0).getMBB();
3097         continue;
3098       }
3100       // If the block has any instructions after a JMP, delete them.
3101       while (std::next(I) != MBB.end())
3102         std::next(I)->eraseFromParent();
3104       Cond.clear();
3105       FBB = nullptr;
3107       // Delete the JMP if it's equivalent to a fall-through.
3108       if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
3109         TBB = nullptr;
3110         I->eraseFromParent();
3111         I = MBB.end();
3112         UnCondBrIter = MBB.end();
3113         continue;
3114       }
3116       // TBB is used to indicate the unconditional destination.
3117       TBB = I->getOperand(0).getMBB();
3118       continue;
3119     }
3121     // Handle conditional branches.
3122     X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode());
3123     if (BranchCode == X86::COND_INVALID)
3124       return true;  // Can't handle indirect branch.
3126     // Working from the bottom, handle the first conditional branch.
3127     if (Cond.empty()) {
3128       MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
3129       if (AllowModify && UnCondBrIter != MBB.end() &&
3130           MBB.isLayoutSuccessor(TargetBB)) {
3131         // If we can modify the code and it ends in something like:
3132         //
3133         //     jCC L1
3134         //     jmp L2
3135         //   L1:
3136         //     ...
3137         //   L2:
3138         //
3139         // Then we can change this to:
3140         //
3141         //     jnCC L2
3142         //   L1:
3143         //     ...
3144         //   L2:
3145         //
3146         // Which is a bit more efficient.
3147         // We conditionally jump to the fall-through block.
3148         BranchCode = GetOppositeBranchCondition(BranchCode);
3149         unsigned JNCC = GetCondBranchFromCond(BranchCode);
3150         MachineBasicBlock::iterator OldInst = I;
3152         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
3153           .addMBB(UnCondBrIter->getOperand(0).getMBB());
3154         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
3155           .addMBB(TargetBB);
3157         OldInst->eraseFromParent();
3158         UnCondBrIter->eraseFromParent();
3160         // Restart the analysis.
3161         UnCondBrIter = MBB.end();
3162         I = MBB.end();
3163         continue;
3164       }
3166       FBB = TBB;
3167       TBB = I->getOperand(0).getMBB();
3168       Cond.push_back(MachineOperand::CreateImm(BranchCode));
3169       continue;
3170     }
3172     // Handle subsequent conditional branches. Only handle the case where all
3173     // conditional branches branch to the same destination and their condition
3174     // opcodes fit one of the special multi-branch idioms.
3175     assert(Cond.size() == 1);
3176     assert(TBB);
3178     // Only handle the case where all conditional branches branch to the same
3179     // destination.
3180     if (TBB != I->getOperand(0).getMBB())
3181       return true;
3183     // If the conditions are the same, we can leave them alone.
3184     X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
3185     if (OldBranchCode == BranchCode)
3186       continue;
3188     // If they differ, see if they fit one of the known patterns. Theoretically,
3189     // we could handle more patterns here, but we shouldn't expect to see them
3190     // if instruction selection has done a reasonable job.
3191     if ((OldBranchCode == X86::COND_NP &&
3192          BranchCode == X86::COND_E) ||
3193         (OldBranchCode == X86::COND_E &&
3194          BranchCode == X86::COND_NP))
3195       BranchCode = X86::COND_NP_OR_E;
3196     else if ((OldBranchCode == X86::COND_P &&
3197               BranchCode == X86::COND_NE) ||
3198              (OldBranchCode == X86::COND_NE &&
3199               BranchCode == X86::COND_P))
3200       BranchCode = X86::COND_NE_OR_P;
3201     else
3202       return true;
3204     // Update the MachineOperand.
3205     Cond[0].setImm(BranchCode);
3206   }
3208   return false;
3211 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
3212   MachineBasicBlock::iterator I = MBB.end();
3213   unsigned Count = 0;
3215   while (I != MBB.begin()) {
3216     --I;
3217     if (I->isDebugValue())
3218       continue;
3219     if (I->getOpcode() != X86::JMP_1 &&
3220         getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
3221       break;
3222     // Remove the branch.
3223     I->eraseFromParent();
3224     I = MBB.end();
3225     ++Count;
3226   }
3228   return Count;
3231 unsigned
3232 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
3233                            MachineBasicBlock *FBB,
3234                            const SmallVectorImpl<MachineOperand> &Cond,
3235                            DebugLoc DL) const {
3236   // Shouldn't be a fall through.
3237   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
3238   assert((Cond.size() == 1 || Cond.size() == 0) &&
3239          "X86 branch conditions have one component!");
3241   if (Cond.empty()) {
3242     // Unconditional branch?
3243     assert(!FBB && "Unconditional branch with multiple successors!");
3244     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
3245     return 1;
3246   }
3248   // Conditional branch.
3249   unsigned Count = 0;
3250   X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
3251   switch (CC) {
3252   case X86::COND_NP_OR_E:
3253     // Synthesize NP_OR_E with two branches.
3254     BuildMI(&MBB, DL, get(X86::JNP_1)).addMBB(TBB);
3255     ++Count;
3256     BuildMI(&MBB, DL, get(X86::JE_1)).addMBB(TBB);
3257     ++Count;
3258     break;
3259   case X86::COND_NE_OR_P:
3260     // Synthesize NE_OR_P with two branches.
3261     BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(TBB);
3262     ++Count;
3263     BuildMI(&MBB, DL, get(X86::JP_1)).addMBB(TBB);
3264     ++Count;
3265     break;
3266   default: {
3267     unsigned Opc = GetCondBranchFromCond(CC);
3268     BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
3269     ++Count;
3270   }
3271   }
3272   if (FBB) {
3273     // Two-way Conditional branch. Insert the second branch.
3274     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
3275     ++Count;
3276   }
3277   return Count;
3280 bool X86InstrInfo::
3281 canInsertSelect(const MachineBasicBlock &MBB,
3282                 const SmallVectorImpl<MachineOperand> &Cond,
3283                 unsigned TrueReg, unsigned FalseReg,
3284                 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
3285   // Not all subtargets have cmov instructions.
3286   if (!Subtarget.hasCMov())
3287     return false;
3288   if (Cond.size() != 1)
3289     return false;
3290   // We cannot do the composite conditions, at least not in SSA form.
3291   if ((X86::CondCode)Cond[0].getImm() > X86::COND_S)
3292     return false;
3294   // Check register classes.
3295   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3296   const TargetRegisterClass *RC =
3297     RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
3298   if (!RC)
3299     return false;
3301   // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
3302   if (X86::GR16RegClass.hasSubClassEq(RC) ||
3303       X86::GR32RegClass.hasSubClassEq(RC) ||
3304       X86::GR64RegClass.hasSubClassEq(RC)) {
3305     // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
3306     // Bridge. Probably Ivy Bridge as well.
3307     CondCycles = 2;
3308     TrueCycles = 2;
3309     FalseCycles = 2;
3310     return true;
3311   }
3313   // Can't do vectors.
3314   return false;
3317 void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
3318                                 MachineBasicBlock::iterator I, DebugLoc DL,
3319                                 unsigned DstReg,
3320                                 const SmallVectorImpl<MachineOperand> &Cond,
3321                                 unsigned TrueReg, unsigned FalseReg) const {
3322    MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3323    assert(Cond.size() == 1 && "Invalid Cond array");
3324    unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
3325                                   MRI.getRegClass(DstReg)->getSize(),
3326                                   false/*HasMemoryOperand*/);
3327    BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
3330 /// isHReg - Test if the given register is a physical h register.
3331 static bool isHReg(unsigned Reg) {
3332   return X86::GR8_ABCD_HRegClass.contains(Reg);
3335 // Try and copy between VR128/VR64 and GR64 registers.
3336 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
3337                                         const X86Subtarget &Subtarget) {
3339   // SrcReg(VR128) -> DestReg(GR64)
3340   // SrcReg(VR64)  -> DestReg(GR64)
3341   // SrcReg(GR64)  -> DestReg(VR128)
3342   // SrcReg(GR64)  -> DestReg(VR64)
3344   bool HasAVX = Subtarget.hasAVX();
3345   bool HasAVX512 = Subtarget.hasAVX512();
3346   if (X86::GR64RegClass.contains(DestReg)) {
3347     if (X86::VR128XRegClass.contains(SrcReg))
3348       // Copy from a VR128 register to a GR64 register.
3349       return HasAVX512 ? X86::VMOVPQIto64Zrr: (HasAVX ? X86::VMOVPQIto64rr :
3350                                                X86::MOVPQIto64rr);
3351     if (X86::VR64RegClass.contains(SrcReg))
3352       // Copy from a VR64 register to a GR64 register.
3353       return X86::MOVSDto64rr;
3354   } else if (X86::GR64RegClass.contains(SrcReg)) {
3355     // Copy from a GR64 register to a VR128 register.
3356     if (X86::VR128XRegClass.contains(DestReg))
3357       return HasAVX512 ? X86::VMOV64toPQIZrr: (HasAVX ? X86::VMOV64toPQIrr :
3358                                                X86::MOV64toPQIrr);
3359     // Copy from a GR64 register to a VR64 register.
3360     if (X86::VR64RegClass.contains(DestReg))
3361       return X86::MOV64toSDrr;
3362   }
3364   // SrcReg(FR32) -> DestReg(GR32)
3365   // SrcReg(GR32) -> DestReg(FR32)
3367   if (X86::GR32RegClass.contains(DestReg) && X86::FR32XRegClass.contains(SrcReg))
3368     // Copy from a FR32 register to a GR32 register.
3369     return HasAVX512 ? X86::VMOVSS2DIZrr : (HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr);
3371   if (X86::FR32XRegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg))
3372     // Copy from a GR32 register to a FR32 register.
3373     return HasAVX512 ? X86::VMOVDI2SSZrr : (HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr);
3374   return 0;
3377 inline static bool MaskRegClassContains(unsigned Reg) {
3378   return X86::VK8RegClass.contains(Reg) ||
3379          X86::VK16RegClass.contains(Reg) ||
3380          X86::VK32RegClass.contains(Reg) ||
3381          X86::VK64RegClass.contains(Reg) ||
3382          X86::VK1RegClass.contains(Reg);
3384 static
3385 unsigned copyPhysRegOpcode_AVX512(unsigned& DestReg, unsigned& SrcReg) {
3386   if (X86::VR128XRegClass.contains(DestReg, SrcReg) ||
3387       X86::VR256XRegClass.contains(DestReg, SrcReg) ||
3388       X86::VR512RegClass.contains(DestReg, SrcReg)) {
3389      DestReg = get512BitSuperRegister(DestReg);
3390      SrcReg = get512BitSuperRegister(SrcReg);
3391      return X86::VMOVAPSZrr;
3392   }
3393   if (MaskRegClassContains(DestReg) &&
3394       MaskRegClassContains(SrcReg))
3395     return X86::KMOVWkk;
3396   if (MaskRegClassContains(DestReg) &&
3397       (X86::GR32RegClass.contains(SrcReg) ||
3398        X86::GR16RegClass.contains(SrcReg) ||
3399        X86::GR8RegClass.contains(SrcReg))) {
3400     SrcReg = getX86SubSuperRegister(SrcReg, MVT::i32);
3401     return X86::KMOVWkr;
3402   }
3403   if ((X86::GR32RegClass.contains(DestReg) ||
3404        X86::GR16RegClass.contains(DestReg) ||
3405        X86::GR8RegClass.contains(DestReg)) &&
3406        MaskRegClassContains(SrcReg)) {
3407     DestReg = getX86SubSuperRegister(DestReg, MVT::i32);
3408     return X86::KMOVWrk;
3409   }
3410   return 0;
3413 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
3414                                MachineBasicBlock::iterator MI, DebugLoc DL,
3415                                unsigned DestReg, unsigned SrcReg,
3416                                bool KillSrc) const {
3417   // First deal with the normal symmetric copies.
3418   bool HasAVX = Subtarget.hasAVX();
3419   bool HasAVX512 = Subtarget.hasAVX512();
3420   unsigned Opc = 0;
3421   if (X86::GR64RegClass.contains(DestReg, SrcReg))
3422     Opc = X86::MOV64rr;
3423   else if (X86::GR32RegClass.contains(DestReg, SrcReg))
3424     Opc = X86::MOV32rr;
3425   else if (X86::GR16RegClass.contains(DestReg, SrcReg))
3426     Opc = X86::MOV16rr;
3427   else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
3428     // Copying to or from a physical H register on x86-64 requires a NOREX
3429     // move.  Otherwise use a normal move.
3430     if ((isHReg(DestReg) || isHReg(SrcReg)) &&
3431         Subtarget.is64Bit()) {
3432       Opc = X86::MOV8rr_NOREX;
3433       // Both operands must be encodable without an REX prefix.
3434       assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
3435              "8-bit H register can not be copied outside GR8_NOREX");
3436     } else
3437       Opc = X86::MOV8rr;
3438   }
3439   else if (X86::VR64RegClass.contains(DestReg, SrcReg))
3440     Opc = X86::MMX_MOVQ64rr;
3441   else if (HasAVX512)
3442     Opc = copyPhysRegOpcode_AVX512(DestReg, SrcReg);
3443   else if (X86::VR128RegClass.contains(DestReg, SrcReg))
3444     Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
3445   else if (X86::VR256RegClass.contains(DestReg, SrcReg))
3446     Opc = X86::VMOVAPSYrr;
3447   if (!Opc)
3448     Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
3450   if (Opc) {
3451     BuildMI(MBB, MI, DL, get(Opc), DestReg)
3452       .addReg(SrcReg, getKillRegState(KillSrc));
3453     return;
3454   }
3456   // Moving EFLAGS to / from another register requires a push and a pop.
3457   // Notice that we have to adjust the stack if we don't want to clobber the
3458   // first frame index. See X86FrameLowering.cpp - clobbersTheStack.
3459   if (SrcReg == X86::EFLAGS) {
3460     if (X86::GR64RegClass.contains(DestReg)) {
3461       BuildMI(MBB, MI, DL, get(X86::PUSHF64));
3462       BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
3463       return;
3464     }
3465     if (X86::GR32RegClass.contains(DestReg)) {
3466       BuildMI(MBB, MI, DL, get(X86::PUSHF32));
3467       BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
3468       return;
3469     }
3470   }
3471   if (DestReg == X86::EFLAGS) {
3472     if (X86::GR64RegClass.contains(SrcReg)) {
3473       BuildMI(MBB, MI, DL, get(X86::PUSH64r))
3474         .addReg(SrcReg, getKillRegState(KillSrc));
3475       BuildMI(MBB, MI, DL, get(X86::POPF64));
3476       return;
3477     }
3478     if (X86::GR32RegClass.contains(SrcReg)) {
3479       BuildMI(MBB, MI, DL, get(X86::PUSH32r))
3480         .addReg(SrcReg, getKillRegState(KillSrc));
3481       BuildMI(MBB, MI, DL, get(X86::POPF32));
3482       return;
3483     }
3484   }
3486   DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
3487                << " to " << RI.getName(DestReg) << '\n');
3488   llvm_unreachable("Cannot emit physreg copy instruction");
3491 static unsigned getLoadStoreRegOpcode(unsigned Reg,
3492                                       const TargetRegisterClass *RC,
3493                                       bool isStackAligned,
3494                                       const X86Subtarget &STI,
3495                                       bool load) {
3496   if (STI.hasAVX512()) {
3497     if (X86::VK8RegClass.hasSubClassEq(RC)  ||
3498       X86::VK16RegClass.hasSubClassEq(RC))
3499       return load ? X86::KMOVWkm : X86::KMOVWmk;
3500     if (RC->getSize() == 4 && X86::FR32XRegClass.hasSubClassEq(RC))
3501       return load ? X86::VMOVSSZrm : X86::VMOVSSZmr;
3502     if (RC->getSize() == 8 && X86::FR64XRegClass.hasSubClassEq(RC))
3503       return load ? X86::VMOVSDZrm : X86::VMOVSDZmr;
3504     if (X86::VR512RegClass.hasSubClassEq(RC))
3505       return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3506   }
3508   bool HasAVX = STI.hasAVX();
3509   switch (RC->getSize()) {
3510   default:
3511     llvm_unreachable("Unknown spill size");
3512   case 1:
3513     assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
3514     if (STI.is64Bit())
3515       // Copying to or from a physical H register on x86-64 requires a NOREX
3516       // move.  Otherwise use a normal move.
3517       if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
3518         return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
3519     return load ? X86::MOV8rm : X86::MOV8mr;
3520   case 2:
3521     assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
3522     return load ? X86::MOV16rm : X86::MOV16mr;
3523   case 4:
3524     if (X86::GR32RegClass.hasSubClassEq(RC))
3525       return load ? X86::MOV32rm : X86::MOV32mr;
3526     if (X86::FR32RegClass.hasSubClassEq(RC))
3527       return load ?
3528         (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
3529         (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
3530     if (X86::RFP32RegClass.hasSubClassEq(RC))
3531       return load ? X86::LD_Fp32m : X86::ST_Fp32m;
3532     llvm_unreachable("Unknown 4-byte regclass");
3533   case 8:
3534     if (X86::GR64RegClass.hasSubClassEq(RC))
3535       return load ? X86::MOV64rm : X86::MOV64mr;
3536     if (X86::FR64RegClass.hasSubClassEq(RC))
3537       return load ?
3538         (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
3539         (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
3540     if (X86::VR64RegClass.hasSubClassEq(RC))
3541       return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
3542     if (X86::RFP64RegClass.hasSubClassEq(RC))
3543       return load ? X86::LD_Fp64m : X86::ST_Fp64m;
3544     llvm_unreachable("Unknown 8-byte regclass");
3545   case 10:
3546     assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
3547     return load ? X86::LD_Fp80m : X86::ST_FpP80m;
3548   case 16: {