1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the X86 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
14 #include "X86InstrInfo.h"
15 #include "X86.h"
16 #include "X86InstrBuilder.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/LiveVariables.h"
22 #include "llvm/CodeGen/MachineConstantPool.h"
23 #include "llvm/CodeGen/MachineDominators.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/StackMaps.h"
28 #include "llvm/IR/DerivedTypes.h"
29 #include "llvm/IR/LLVMContext.h"
30 #include "llvm/MC/MCAsmInfo.h"
31 #include "llvm/MC/MCInst.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetOptions.h"
37 #include <limits>
39 using namespace llvm;
41 #define DEBUG_TYPE "x86-instr-info"
43 #define GET_INSTRINFO_CTOR_DTOR
44 #include "X86GenInstrInfo.inc"
46 static cl::opt<bool>
47 NoFusing("disable-spill-fusing",
48 cl::desc("Disable fusing of spill code into instructions"));
49 static cl::opt<bool>
50 PrintFailedFusing("print-failed-fuse-candidates",
51 cl::desc("Print instructions that the allocator wants to"
52 " fuse, but the X86 backend currently can't"),
53 cl::Hidden);
54 static cl::opt<bool>
55 ReMatPICStubLoad("remat-pic-stub-load",
56 cl::desc("Re-materialize load from stub in PIC mode"),
57 cl::init(false), cl::Hidden);
59 enum {
60 // Select which memory operand is being unfolded.
61 // (stored in bits 0 - 3)
62 TB_INDEX_0 = 0,
63 TB_INDEX_1 = 1,
64 TB_INDEX_2 = 2,
65 TB_INDEX_3 = 3,
66 TB_INDEX_MASK = 0xf,
68 // Do not insert the reverse map (MemOp -> RegOp) into the table.
69 // This may be needed because there is a many -> one mapping.
70 TB_NO_REVERSE = 1 << 4,
72 // Do not insert the forward map (RegOp -> MemOp) into the table.
73 // This is needed for Native Client, which prohibits branch
74 // instructions from using a memory operand.
75 TB_NO_FORWARD = 1 << 5,
77 TB_FOLDED_LOAD = 1 << 6,
78 TB_FOLDED_STORE = 1 << 7,
80 // Minimum alignment required for load/store.
81 // Used for RegOp->MemOp conversion.
82 // (stored in bits 8 - 15)
83 TB_ALIGN_SHIFT = 8,
84 TB_ALIGN_NONE = 0 << TB_ALIGN_SHIFT,
85 TB_ALIGN_16 = 16 << TB_ALIGN_SHIFT,
86 TB_ALIGN_32 = 32 << TB_ALIGN_SHIFT,
87 TB_ALIGN_64 = 64 << TB_ALIGN_SHIFT,
88 TB_ALIGN_MASK = 0xff << TB_ALIGN_SHIFT
89 };
91 struct X86OpTblEntry {
92 uint16_t RegOp;
93 uint16_t MemOp;
94 uint16_t Flags;
95 };
97 // Pin the vtable to this file.
98 void X86InstrInfo::anchor() {}
100 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
101 : X86GenInstrInfo((tm.getSubtarget<X86Subtarget>().is64Bit()
102 ? X86::ADJCALLSTACKDOWN64
103 : X86::ADJCALLSTACKDOWN32),
104 (tm.getSubtarget<X86Subtarget>().is64Bit()
105 ? X86::ADJCALLSTACKUP64
106 : X86::ADJCALLSTACKUP32)),
107 TM(tm), RI(tm) {
109 static const X86OpTblEntry OpTbl2Addr[] = {
110 { X86::ADC32ri, X86::ADC32mi, 0 },
111 { X86::ADC32ri8, X86::ADC32mi8, 0 },
112 { X86::ADC32rr, X86::ADC32mr, 0 },
113 { X86::ADC64ri32, X86::ADC64mi32, 0 },
114 { X86::ADC64ri8, X86::ADC64mi8, 0 },
115 { X86::ADC64rr, X86::ADC64mr, 0 },
116 { X86::ADD16ri, X86::ADD16mi, 0 },
117 { X86::ADD16ri8, X86::ADD16mi8, 0 },
118 { X86::ADD16ri_DB, X86::ADD16mi, TB_NO_REVERSE },
119 { X86::ADD16ri8_DB, X86::ADD16mi8, TB_NO_REVERSE },
120 { X86::ADD16rr, X86::ADD16mr, 0 },
121 { X86::ADD16rr_DB, X86::ADD16mr, TB_NO_REVERSE },
122 { X86::ADD32ri, X86::ADD32mi, 0 },
123 { X86::ADD32ri8, X86::ADD32mi8, 0 },
124 { X86::ADD32ri_DB, X86::ADD32mi, TB_NO_REVERSE },
125 { X86::ADD32ri8_DB, X86::ADD32mi8, TB_NO_REVERSE },
126 { X86::ADD32rr, X86::ADD32mr, 0 },
127 { X86::ADD32rr_DB, X86::ADD32mr, TB_NO_REVERSE },
128 { X86::ADD64ri32, X86::ADD64mi32, 0 },
129 { X86::ADD64ri8, X86::ADD64mi8, 0 },
130 { X86::ADD64ri32_DB,X86::ADD64mi32, TB_NO_REVERSE },
131 { X86::ADD64ri8_DB, X86::ADD64mi8, TB_NO_REVERSE },
132 { X86::ADD64rr, X86::ADD64mr, 0 },
133 { X86::ADD64rr_DB, X86::ADD64mr, TB_NO_REVERSE },
134 { X86::ADD8ri, X86::ADD8mi, 0 },
135 { X86::ADD8rr, X86::ADD8mr, 0 },
136 { X86::AND16ri, X86::AND16mi, 0 },
137 { X86::AND16ri8, X86::AND16mi8, 0 },
138 { X86::AND16rr, X86::AND16mr, 0 },
139 { X86::AND32ri, X86::AND32mi, 0 },
140 { X86::AND32ri8, X86::AND32mi8, 0 },
141 { X86::AND32rr, X86::AND32mr, 0 },
142 { X86::AND64ri32, X86::AND64mi32, 0 },
143 { X86::AND64ri8, X86::AND64mi8, 0 },
144 { X86::AND64rr, X86::AND64mr, 0 },
145 { X86::AND8ri, X86::AND8mi, 0 },
146 { X86::AND8rr, X86::AND8mr, 0 },
147 { X86::DEC16r, X86::DEC16m, 0 },
148 { X86::DEC32r, X86::DEC32m, 0 },
149 { X86::DEC64_16r, X86::DEC64_16m, 0 },
150 { X86::DEC64_32r, X86::DEC64_32m, 0 },
151 { X86::DEC64r, X86::DEC64m, 0 },
152 { X86::DEC8r, X86::DEC8m, 0 },
153 { X86::INC16r, X86::INC16m, 0 },
154 { X86::INC32r, X86::INC32m, 0 },
155 { X86::INC64_16r, X86::INC64_16m, 0 },
156 { X86::INC64_32r, X86::INC64_32m, 0 },
157 { X86::INC64r, X86::INC64m, 0 },
158 { X86::INC8r, X86::INC8m, 0 },
159 { X86::NEG16r, X86::NEG16m, 0 },
160 { X86::NEG32r, X86::NEG32m, 0 },
161 { X86::NEG64r, X86::NEG64m, 0 },
162 { X86::NEG8r, X86::NEG8m, 0 },
163 { X86::NOT16r, X86::NOT16m, 0 },
164 { X86::NOT32r, X86::NOT32m, 0 },
165 { X86::NOT64r, X86::NOT64m, 0 },
166 { X86::NOT8r, X86::NOT8m, 0 },
167 { X86::OR16ri, X86::OR16mi, 0 },
168 { X86::OR16ri8, X86::OR16mi8, 0 },
169 { X86::OR16rr, X86::OR16mr, 0 },
170 { X86::OR32ri, X86::OR32mi, 0 },
171 { X86::OR32ri8, X86::OR32mi8, 0 },
172 { X86::OR32rr, X86::OR32mr, 0 },
173 { X86::OR64ri32, X86::OR64mi32, 0 },
174 { X86::OR64ri8, X86::OR64mi8, 0 },
175 { X86::OR64rr, X86::OR64mr, 0 },
176 { X86::OR8ri, X86::OR8mi, 0 },
177 { X86::OR8rr, X86::OR8mr, 0 },
178 { X86::ROL16r1, X86::ROL16m1, 0 },
179 { X86::ROL16rCL, X86::ROL16mCL, 0 },
180 { X86::ROL16ri, X86::ROL16mi, 0 },
181 { X86::ROL32r1, X86::ROL32m1, 0 },
182 { X86::ROL32rCL, X86::ROL32mCL, 0 },
183 { X86::ROL32ri, X86::ROL32mi, 0 },
184 { X86::ROL64r1, X86::ROL64m1, 0 },
185 { X86::ROL64rCL, X86::ROL64mCL, 0 },
186 { X86::ROL64ri, X86::ROL64mi, 0 },
187 { X86::ROL8r1, X86::ROL8m1, 0 },
188 { X86::ROL8rCL, X86::ROL8mCL, 0 },
189 { X86::ROL8ri, X86::ROL8mi, 0 },
190 { X86::ROR16r1, X86::ROR16m1, 0 },
191 { X86::ROR16rCL, X86::ROR16mCL, 0 },
192 { X86::ROR16ri, X86::ROR16mi, 0 },
193 { X86::ROR32r1, X86::ROR32m1, 0 },
194 { X86::ROR32rCL, X86::ROR32mCL, 0 },
195 { X86::ROR32ri, X86::ROR32mi, 0 },
196 { X86::ROR64r1, X86::ROR64m1, 0 },
197 { X86::ROR64rCL, X86::ROR64mCL, 0 },
198 { X86::ROR64ri, X86::ROR64mi, 0 },
199 { X86::ROR8r1, X86::ROR8m1, 0 },
200 { X86::ROR8rCL, X86::ROR8mCL, 0 },
201 { X86::ROR8ri, X86::ROR8mi, 0 },
202 { X86::SAR16r1, X86::SAR16m1, 0 },
203 { X86::SAR16rCL, X86::SAR16mCL, 0 },
204 { X86::SAR16ri, X86::SAR16mi, 0 },
205 { X86::SAR32r1, X86::SAR32m1, 0 },
206 { X86::SAR32rCL, X86::SAR32mCL, 0 },
207 { X86::SAR32ri, X86::SAR32mi, 0 },
208 { X86::SAR64r1, X86::SAR64m1, 0 },
209 { X86::SAR64rCL, X86::SAR64mCL, 0 },
210 { X86::SAR64ri, X86::SAR64mi, 0 },
211 { X86::SAR8r1, X86::SAR8m1, 0 },
212 { X86::SAR8rCL, X86::SAR8mCL, 0 },
213 { X86::SAR8ri, X86::SAR8mi, 0 },
214 { X86::SBB32ri, X86::SBB32mi, 0 },
215 { X86::SBB32ri8, X86::SBB32mi8, 0 },
216 { X86::SBB32rr, X86::SBB32mr, 0 },
217 { X86::SBB64ri32, X86::SBB64mi32, 0 },
218 { X86::SBB64ri8, X86::SBB64mi8, 0 },
219 { X86::SBB64rr, X86::SBB64mr, 0 },
220 { X86::SHL16rCL, X86::SHL16mCL, 0 },
221 { X86::SHL16ri, X86::SHL16mi, 0 },
222 { X86::SHL32rCL, X86::SHL32mCL, 0 },
223 { X86::SHL32ri, X86::SHL32mi, 0 },
224 { X86::SHL64rCL, X86::SHL64mCL, 0 },
225 { X86::SHL64ri, X86::SHL64mi, 0 },
226 { X86::SHL8rCL, X86::SHL8mCL, 0 },
227 { X86::SHL8ri, X86::SHL8mi, 0 },
228 { X86::SHLD16rrCL, X86::SHLD16mrCL, 0 },
229 { X86::SHLD16rri8, X86::SHLD16mri8, 0 },
230 { X86::SHLD32rrCL, X86::SHLD32mrCL, 0 },
231 { X86::SHLD32rri8, X86::SHLD32mri8, 0 },
232 { X86::SHLD64rrCL, X86::SHLD64mrCL, 0 },
233 { X86::SHLD64rri8, X86::SHLD64mri8, 0 },
234 { X86::SHR16r1, X86::SHR16m1, 0 },
235 { X86::SHR16rCL, X86::SHR16mCL, 0 },
236 { X86::SHR16ri, X86::SHR16mi, 0 },
237 { X86::SHR32r1, X86::SHR32m1, 0 },
238 { X86::SHR32rCL, X86::SHR32mCL, 0 },
239 { X86::SHR32ri, X86::SHR32mi, 0 },
240 { X86::SHR64r1, X86::SHR64m1, 0 },
241 { X86::SHR64rCL, X86::SHR64mCL, 0 },
242 { X86::SHR64ri, X86::SHR64mi, 0 },
243 { X86::SHR8r1, X86::SHR8m1, 0 },
244 { X86::SHR8rCL, X86::SHR8mCL, 0 },
245 { X86::SHR8ri, X86::SHR8mi, 0 },
246 { X86::SHRD16rrCL, X86::SHRD16mrCL, 0 },
247 { X86::SHRD16rri8, X86::SHRD16mri8, 0 },
248 { X86::SHRD32rrCL, X86::SHRD32mrCL, 0 },
249 { X86::SHRD32rri8, X86::SHRD32mri8, 0 },
250 { X86::SHRD64rrCL, X86::SHRD64mrCL, 0 },
251 { X86::SHRD64rri8, X86::SHRD64mri8, 0 },
252 { X86::SUB16ri, X86::SUB16mi, 0 },
253 { X86::SUB16ri8, X86::SUB16mi8, 0 },
254 { X86::SUB16rr, X86::SUB16mr, 0 },
255 { X86::SUB32ri, X86::SUB32mi, 0 },
256 { X86::SUB32ri8, X86::SUB32mi8, 0 },
257 { X86::SUB32rr, X86::SUB32mr, 0 },
258 { X86::SUB64ri32, X86::SUB64mi32, 0 },
259 { X86::SUB64ri8, X86::SUB64mi8, 0 },
260 { X86::SUB64rr, X86::SUB64mr, 0 },
261 { X86::SUB8ri, X86::SUB8mi, 0 },
262 { X86::SUB8rr, X86::SUB8mr, 0 },
263 { X86::XOR16ri, X86::XOR16mi, 0 },
264 { X86::XOR16ri8, X86::XOR16mi8, 0 },
265 { X86::XOR16rr, X86::XOR16mr, 0 },
266 { X86::XOR32ri, X86::XOR32mi, 0 },
267 { X86::XOR32ri8, X86::XOR32mi8, 0 },
268 { X86::XOR32rr, X86::XOR32mr, 0 },
269 { X86::XOR64ri32, X86::XOR64mi32, 0 },
270 { X86::XOR64ri8, X86::XOR64mi8, 0 },
271 { X86::XOR64rr, X86::XOR64mr, 0 },
272 { X86::XOR8ri, X86::XOR8mi, 0 },
273 { X86::XOR8rr, X86::XOR8mr, 0 }
274 };
276 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
277 unsigned RegOp = OpTbl2Addr[i].RegOp;
278 unsigned MemOp = OpTbl2Addr[i].MemOp;
279 unsigned Flags = OpTbl2Addr[i].Flags;
280 AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
281 RegOp, MemOp,
282 // Index 0, folded load and store, no alignment requirement.
283 Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
284 }
286 static const X86OpTblEntry OpTbl0[] = {
287 { X86::BT16ri8, X86::BT16mi8, TB_FOLDED_LOAD },
288 { X86::BT32ri8, X86::BT32mi8, TB_FOLDED_LOAD },
289 { X86::BT64ri8, X86::BT64mi8, TB_FOLDED_LOAD },
290 { X86::CALL32r, X86::CALL32m, TB_FOLDED_LOAD },
291 { X86::CALL64r, X86::CALL64m, TB_FOLDED_LOAD },
292 { X86::CMP16ri, X86::CMP16mi, TB_FOLDED_LOAD },
293 { X86::CMP16ri8, X86::CMP16mi8, TB_FOLDED_LOAD },
294 { X86::CMP16rr, X86::CMP16mr, TB_FOLDED_LOAD },
295 { X86::CMP32ri, X86::CMP32mi, TB_FOLDED_LOAD },
296 { X86::CMP32ri8, X86::CMP32mi8, TB_FOLDED_LOAD },
297 { X86::CMP32rr, X86::CMP32mr, TB_FOLDED_LOAD },
298 { X86::CMP64ri32, X86::CMP64mi32, TB_FOLDED_LOAD },
299 { X86::CMP64ri8, X86::CMP64mi8, TB_FOLDED_LOAD },
300 { X86::CMP64rr, X86::CMP64mr, TB_FOLDED_LOAD },
301 { X86::CMP8ri, X86::CMP8mi, TB_FOLDED_LOAD },
302 { X86::CMP8rr, X86::CMP8mr, TB_FOLDED_LOAD },
303 { X86::DIV16r, X86::DIV16m, TB_FOLDED_LOAD },
304 { X86::DIV32r, X86::DIV32m, TB_FOLDED_LOAD },
305 { X86::DIV64r, X86::DIV64m, TB_FOLDED_LOAD },
306 { X86::DIV8r, X86::DIV8m, TB_FOLDED_LOAD },
307 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, TB_FOLDED_STORE },
308 { X86::IDIV16r, X86::IDIV16m, TB_FOLDED_LOAD },
309 { X86::IDIV32r, X86::IDIV32m, TB_FOLDED_LOAD },
310 { X86::IDIV64r, X86::IDIV64m, TB_FOLDED_LOAD },
311 { X86::IDIV8r, X86::IDIV8m, TB_FOLDED_LOAD },
312 { X86::IMUL16r, X86::IMUL16m, TB_FOLDED_LOAD },
313 { X86::IMUL32r, X86::IMUL32m, TB_FOLDED_LOAD },
314 { X86::IMUL64r, X86::IMUL64m, TB_FOLDED_LOAD },
315 { X86::IMUL8r, X86::IMUL8m, TB_FOLDED_LOAD },
316 { X86::JMP32r, X86::JMP32m, TB_FOLDED_LOAD },
317 { X86::JMP64r, X86::JMP64m, TB_FOLDED_LOAD },
318 { X86::MOV16ri, X86::MOV16mi, TB_FOLDED_STORE },
319 { X86::MOV16rr, X86::MOV16mr, TB_FOLDED_STORE },
320 { X86::MOV32ri, X86::MOV32mi, TB_FOLDED_STORE },
321 { X86::MOV32rr, X86::MOV32mr, TB_FOLDED_STORE },
322 { X86::MOV64ri32, X86::MOV64mi32, TB_FOLDED_STORE },
323 { X86::MOV64rr, X86::MOV64mr, TB_FOLDED_STORE },
324 { X86::MOV8ri, X86::MOV8mi, TB_FOLDED_STORE },
325 { X86::MOV8rr, X86::MOV8mr, TB_FOLDED_STORE },
326 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
327 { X86::MOVAPDrr, X86::MOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
328 { X86::MOVAPSrr, X86::MOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
329 { X86::MOVDQArr, X86::MOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
330 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, TB_FOLDED_STORE },
331 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, TB_FOLDED_STORE },
332 { X86::MOVSDto64rr, X86::MOVSDto64mr, TB_FOLDED_STORE },
333 { X86::MOVSS2DIrr, X86::MOVSS2DImr, TB_FOLDED_STORE },
334 { X86::MOVUPDrr, X86::MOVUPDmr, TB_FOLDED_STORE },
335 { X86::MOVUPSrr, X86::MOVUPSmr, TB_FOLDED_STORE },
336 { X86::MUL16r, X86::MUL16m, TB_FOLDED_LOAD },
337 { X86::MUL32r, X86::MUL32m, TB_FOLDED_LOAD },
338 { X86::MUL64r, X86::MUL64m, TB_FOLDED_LOAD },
339 { X86::MUL8r, X86::MUL8m, TB_FOLDED_LOAD },
340 { X86::SETAEr, X86::SETAEm, TB_FOLDED_STORE },
341 { X86::SETAr, X86::SETAm, TB_FOLDED_STORE },
342 { X86::SETBEr, X86::SETBEm, TB_FOLDED_STORE },
343 { X86::SETBr, X86::SETBm, TB_FOLDED_STORE },
344 { X86::SETEr, X86::SETEm, TB_FOLDED_STORE },
345 { X86::SETGEr, X86::SETGEm, TB_FOLDED_STORE },
346 { X86::SETGr, X86::SETGm, TB_FOLDED_STORE },
347 { X86::SETLEr, X86::SETLEm, TB_FOLDED_STORE },
348 { X86::SETLr, X86::SETLm, TB_FOLDED_STORE },
349 { X86::SETNEr, X86::SETNEm, TB_FOLDED_STORE },
350 { X86::SETNOr, X86::SETNOm, TB_FOLDED_STORE },
351 { X86::SETNPr, X86::SETNPm, TB_FOLDED_STORE },
352 { X86::SETNSr, X86::SETNSm, TB_FOLDED_STORE },
353 { X86::SETOr, X86::SETOm, TB_FOLDED_STORE },
354 { X86::SETPr, X86::SETPm, TB_FOLDED_STORE },
355 { X86::SETSr, X86::SETSm, TB_FOLDED_STORE },
356 { X86::TAILJMPr, X86::TAILJMPm, TB_FOLDED_LOAD },
357 { X86::TAILJMPr64, X86::TAILJMPm64, TB_FOLDED_LOAD },
358 { X86::TEST16ri, X86::TEST16mi, TB_FOLDED_LOAD },
359 { X86::TEST32ri, X86::TEST32mi, TB_FOLDED_LOAD },
360 { X86::TEST64ri32, X86::TEST64mi32, TB_FOLDED_LOAD },
361 { X86::TEST8ri, X86::TEST8mi, TB_FOLDED_LOAD },
362 // AVX 128-bit versions of foldable instructions
363 { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr, TB_FOLDED_STORE },
364 { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
365 { X86::VMOVAPDrr, X86::VMOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
366 { X86::VMOVAPSrr, X86::VMOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
367 { X86::VMOVDQArr, X86::VMOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
368 { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr, TB_FOLDED_STORE },
369 { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
370 { X86::VMOVSDto64rr,X86::VMOVSDto64mr, TB_FOLDED_STORE },
371 { X86::VMOVSS2DIrr, X86::VMOVSS2DImr, TB_FOLDED_STORE },
372 { X86::VMOVUPDrr, X86::VMOVUPDmr, TB_FOLDED_STORE },
373 { X86::VMOVUPSrr, X86::VMOVUPSmr, TB_FOLDED_STORE },
374 // AVX 256-bit foldable instructions
375 { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
376 { X86::VMOVAPDYrr, X86::VMOVAPDYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
377 { X86::VMOVAPSYrr, X86::VMOVAPSYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
378 { X86::VMOVDQAYrr, X86::VMOVDQAYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
379 { X86::VMOVUPDYrr, X86::VMOVUPDYmr, TB_FOLDED_STORE },
380 { X86::VMOVUPSYrr, X86::VMOVUPSYmr, TB_FOLDED_STORE },
381 // AVX-512 foldable instructions
382 { X86::VMOVPDI2DIZrr,X86::VMOVPDI2DIZmr, TB_FOLDED_STORE }
383 };
385 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
386 unsigned RegOp = OpTbl0[i].RegOp;
387 unsigned MemOp = OpTbl0[i].MemOp;
388 unsigned Flags = OpTbl0[i].Flags;
389 AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
390 RegOp, MemOp, TB_INDEX_0 | Flags);
391 }
393 static const X86OpTblEntry OpTbl1[] = {
394 { X86::CMP16rr, X86::CMP16rm, 0 },
395 { X86::CMP32rr, X86::CMP32rm, 0 },
396 { X86::CMP64rr, X86::CMP64rm, 0 },
397 { X86::CMP8rr, X86::CMP8rm, 0 },
398 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 },
399 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 },
400 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 },
401 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 },
402 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 },
403 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 },
404 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 },
405 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 },
406 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 },
407 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 },
408 { X86::IMUL16rri, X86::IMUL16rmi, 0 },
409 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 },
410 { X86::IMUL32rri, X86::IMUL32rmi, 0 },
411 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 },
412 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 },
413 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
414 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 },
415 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 },
416 { X86::CVTSD2SI64rr, X86::CVTSD2SI64rm, 0 },
417 { X86::CVTSD2SIrr, X86::CVTSD2SIrm, 0 },
418 { X86::CVTSS2SI64rr, X86::CVTSS2SI64rm, 0 },
419 { X86::CVTSS2SIrr, X86::CVTSS2SIrm, 0 },
420 { X86::CVTTPD2DQrr, X86::CVTTPD2DQrm, TB_ALIGN_16 },
421 { X86::CVTTPS2DQrr, X86::CVTTPS2DQrm, TB_ALIGN_16 },
422 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 },
423 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 },
424 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 },
425 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 },
426 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 },
427 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 },
428 { X86::MOV16rr, X86::MOV16rm, 0 },
429 { X86::MOV32rr, X86::MOV32rm, 0 },
430 { X86::MOV64rr, X86::MOV64rm, 0 },
431 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 },
432 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 },
433 { X86::MOV8rr, X86::MOV8rm, 0 },
434 { X86::MOVAPDrr, X86::MOVAPDrm, TB_ALIGN_16 },
435 { X86::MOVAPSrr, X86::MOVAPSrm, TB_ALIGN_16 },
436 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 },
437 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 },
438 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 },
439 { X86::MOVDQArr, X86::MOVDQArm, TB_ALIGN_16 },
440 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, TB_ALIGN_16 },
441 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, TB_ALIGN_16 },
442 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 },
443 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 },
444 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 },
445 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 },
446 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 },
447 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 },
448 { X86::MOVUPDrr, X86::MOVUPDrm, TB_ALIGN_16 },
449 { X86::MOVUPSrr, X86::MOVUPSrm, 0 },
450 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 },
451 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, TB_ALIGN_16 },
452 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 },
453 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 },
454 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
455 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 },
456 { X86::PABSBrr128, X86::PABSBrm128, TB_ALIGN_16 },
457 { X86::PABSDrr128, X86::PABSDrm128, TB_ALIGN_16 },
458 { X86::PABSWrr128, X86::PABSWrm128, TB_ALIGN_16 },
459 { X86::PSHUFDri, X86::PSHUFDmi, TB_ALIGN_16 },
460 { X86::PSHUFHWri, X86::PSHUFHWmi, TB_ALIGN_16 },
461 { X86::PSHUFLWri, X86::PSHUFLWmi, TB_ALIGN_16 },
462 { X86::RCPPSr, X86::RCPPSm, TB_ALIGN_16 },
463 { X86::RCPPSr_Int, X86::RCPPSm_Int, TB_ALIGN_16 },
464 { X86::RSQRTPSr, X86::RSQRTPSm, TB_ALIGN_16 },
465 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int, TB_ALIGN_16 },
466 { X86::RSQRTSSr, X86::RSQRTSSm, 0 },
467 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 },
468 { X86::SQRTPDr, X86::SQRTPDm, TB_ALIGN_16 },
469 { X86::SQRTPSr, X86::SQRTPSm, TB_ALIGN_16 },
470 { X86::SQRTSDr, X86::SQRTSDm, 0 },
471 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 },
472 { X86::SQRTSSr, X86::SQRTSSm, 0 },
473 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 },
474 { X86::TEST16rr, X86::TEST16rm, 0 },
475 { X86::TEST32rr, X86::TEST32rm, 0 },
476 { X86::TEST64rr, X86::TEST64rm, 0 },
477 { X86::TEST8rr, X86::TEST8rm, 0 },
478 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
479 { X86::UCOMISDrr, X86::UCOMISDrm, 0 },
480 { X86::UCOMISSrr, X86::UCOMISSrm, 0 },
481 // AVX 128-bit versions of foldable instructions
482 { X86::Int_VCOMISDrr, X86::Int_VCOMISDrm, 0 },
483 { X86::Int_VCOMISSrr, X86::Int_VCOMISSrm, 0 },
484 { X86::Int_VUCOMISDrr, X86::Int_VUCOMISDrm, 0 },
485 { X86::Int_VUCOMISSrr, X86::Int_VUCOMISSrm, 0 },
486 { X86::VCVTTSD2SI64rr, X86::VCVTTSD2SI64rm, 0 },
487 { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 },
488 { X86::VCVTTSD2SIrr, X86::VCVTTSD2SIrm, 0 },
489 { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm, 0 },
490 { X86::VCVTTSS2SI64rr, X86::VCVTTSS2SI64rm, 0 },
491 { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 },
492 { X86::VCVTTSS2SIrr, X86::VCVTTSS2SIrm, 0 },
493 { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm, 0 },
494 { X86::VCVTSD2SI64rr, X86::VCVTSD2SI64rm, 0 },
495 { X86::VCVTSD2SIrr, X86::VCVTSD2SIrm, 0 },
496 { X86::VCVTSS2SI64rr, X86::VCVTSS2SI64rm, 0 },
497 { X86::VCVTSS2SIrr, X86::VCVTSS2SIrm, 0 },
498 { X86::VMOV64toPQIrr, X86::VMOVQI2PQIrm, 0 },
499 { X86::VMOV64toSDrr, X86::VMOV64toSDrm, 0 },
500 { X86::VMOVAPDrr, X86::VMOVAPDrm, TB_ALIGN_16 },
501 { X86::VMOVAPSrr, X86::VMOVAPSrm, TB_ALIGN_16 },
502 { X86::VMOVDDUPrr, X86::VMOVDDUPrm, 0 },
503 { X86::VMOVDI2PDIrr, X86::VMOVDI2PDIrm, 0 },
504 { X86::VMOVDI2SSrr, X86::VMOVDI2SSrm, 0 },
505 { X86::VMOVDQArr, X86::VMOVDQArm, TB_ALIGN_16 },
506 { X86::VMOVSLDUPrr, X86::VMOVSLDUPrm, TB_ALIGN_16 },
507 { X86::VMOVSHDUPrr, X86::VMOVSHDUPrm, TB_ALIGN_16 },
508 { X86::VMOVUPDrr, X86::VMOVUPDrm, 0 },
509 { X86::VMOVUPSrr, X86::VMOVUPSrm, 0 },
510 { X86::VMOVZQI2PQIrr, X86::VMOVZQI2PQIrm, 0 },
511 { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm, TB_ALIGN_16 },
512 { X86::VPABSBrr128, X86::VPABSBrm128, 0 },
513 { X86::VPABSDrr128, X86::VPABSDrm128, 0 },
514 { X86::VPABSWrr128, X86::VPABSWrm128, 0 },
515 { X86::VPERMILPDri, X86::VPERMILPDmi, 0 },
516 { X86::VPERMILPSri, X86::VPERMILPSmi, 0 },
517 { X86::VPSHUFDri, X86::VPSHUFDmi, 0 },
518 { X86::VPSHUFHWri, X86::VPSHUFHWmi, 0 },
519 { X86::VPSHUFLWri, X86::VPSHUFLWmi, 0 },
520 { X86::VRCPPSr, X86::VRCPPSm, 0 },
521 { X86::VRCPPSr_Int, X86::VRCPPSm_Int, 0 },
522 { X86::VRSQRTPSr, X86::VRSQRTPSm, 0 },
523 { X86::VRSQRTPSr_Int, X86::VRSQRTPSm_Int, 0 },
524 { X86::VSQRTPDr, X86::VSQRTPDm, 0 },
525 { X86::VSQRTPSr, X86::VSQRTPSm, 0 },
526 { X86::VUCOMISDrr, X86::VUCOMISDrm, 0 },
527 { X86::VUCOMISSrr, X86::VUCOMISSrm, 0 },
528 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrm, TB_NO_REVERSE },
530 // AVX 256-bit foldable instructions
531 { X86::VMOVAPDYrr, X86::VMOVAPDYrm, TB_ALIGN_32 },
532 { X86::VMOVAPSYrr, X86::VMOVAPSYrm, TB_ALIGN_32 },
533 { X86::VMOVDQAYrr, X86::VMOVDQAYrm, TB_ALIGN_32 },
534 { X86::VMOVUPDYrr, X86::VMOVUPDYrm, 0 },
535 { X86::VMOVUPSYrr, X86::VMOVUPSYrm, 0 },
536 { X86::VPERMILPDYri, X86::VPERMILPDYmi, 0 },
537 { X86::VPERMILPSYri, X86::VPERMILPSYmi, 0 },
539 // AVX2 foldable instructions
540 { X86::VPABSBrr256, X86::VPABSBrm256, 0 },
541 { X86::VPABSDrr256, X86::VPABSDrm256, 0 },
542 { X86::VPABSWrr256, X86::VPABSWrm256, 0 },
543 { X86::VPSHUFDYri, X86::VPSHUFDYmi, 0 },
544 { X86::VPSHUFHWYri, X86::VPSHUFHWYmi, 0 },
545 { X86::VPSHUFLWYri, X86::VPSHUFLWYmi, 0 },
546 { X86::VRCPPSYr, X86::VRCPPSYm, 0 },
547 { X86::VRCPPSYr_Int, X86::VRCPPSYm_Int, 0 },
548 { X86::VRSQRTPSYr, X86::VRSQRTPSYm, 0 },
549 { X86::VSQRTPDYr, X86::VSQRTPDYm, 0 },
550 { X86::VSQRTPSYr, X86::VSQRTPSYm, 0 },
551 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm, TB_NO_REVERSE },
552 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm, TB_NO_REVERSE },
554 // BMI/BMI2/LZCNT/POPCNT/TBM foldable instructions
555 { X86::BEXTR32rr, X86::BEXTR32rm, 0 },
556 { X86::BEXTR64rr, X86::BEXTR64rm, 0 },
557 { X86::BEXTRI32ri, X86::BEXTRI32mi, 0 },
558 { X86::BEXTRI64ri, X86::BEXTRI64mi, 0 },
559 { X86::BLCFILL32rr, X86::BLCFILL32rm, 0 },
560 { X86::BLCFILL64rr, X86::BLCFILL64rm, 0 },
561 { X86::BLCI32rr, X86::BLCI32rm, 0 },
562 { X86::BLCI64rr, X86::BLCI64rm, 0 },
563 { X86::BLCIC32rr, X86::BLCIC32rm, 0 },
564 { X86::BLCIC64rr, X86::BLCIC64rm, 0 },
565 { X86::BLCMSK32rr, X86::BLCMSK32rm, 0 },
566 { X86::BLCMSK64rr, X86::BLCMSK64rm, 0 },
567 { X86::BLCS32rr, X86::BLCS32rm, 0 },
568 { X86::BLCS64rr, X86::BLCS64rm, 0 },
569 { X86::BLSFILL32rr, X86::BLSFILL32rm, 0 },
570 { X86::BLSFILL64rr, X86::BLSFILL64rm, 0 },
571 { X86::BLSI32rr, X86::BLSI32rm, 0 },
572 { X86::BLSI64rr, X86::BLSI64rm, 0 },
573 { X86::BLSIC32rr, X86::BLSIC32rm, 0 },
574 { X86::BLSIC64rr, X86::BLSIC64rm, 0 },
575 { X86::BLSMSK32rr, X86::BLSMSK32rm, 0 },
576 { X86::BLSMSK64rr, X86::BLSMSK64rm, 0 },
577 { X86::BLSR32rr, X86::BLSR32rm, 0 },
578 { X86::BLSR64rr, X86::BLSR64rm, 0 },
579 { X86::BZHI32rr, X86::BZHI32rm, 0 },
580 { X86::BZHI64rr, X86::BZHI64rm, 0 },
581 { X86::LZCNT16rr, X86::LZCNT16rm, 0 },
582 { X86::LZCNT32rr, X86::LZCNT32rm, 0 },
583 { X86::LZCNT64rr, X86::LZCNT64rm, 0 },
584 { X86::POPCNT16rr, X86::POPCNT16rm, 0 },
585 { X86::POPCNT32rr, X86::POPCNT32rm, 0 },
586 { X86::POPCNT64rr, X86::POPCNT64rm, 0 },
587 { X86::RORX32ri, X86::RORX32mi, 0 },
588 { X86::RORX64ri, X86::RORX64mi, 0 },
589 { X86::SARX32rr, X86::SARX32rm, 0 },
590 { X86::SARX64rr, X86::SARX64rm, 0 },
591 { X86::SHRX32rr, X86::SHRX32rm, 0 },
592 { X86::SHRX64rr, X86::SHRX64rm, 0 },
593 { X86::SHLX32rr, X86::SHLX32rm, 0 },
594 { X86::SHLX64rr, X86::SHLX64rm, 0 },
595 { X86::T1MSKC32rr, X86::T1MSKC32rm, 0 },
596 { X86::T1MSKC64rr, X86::T1MSKC64rm, 0 },
597 { X86::TZCNT16rr, X86::TZCNT16rm, 0 },
598 { X86::TZCNT32rr, X86::TZCNT32rm, 0 },
599 { X86::TZCNT64rr, X86::TZCNT64rm, 0 },
600 { X86::TZMSK32rr, X86::TZMSK32rm, 0 },
601 { X86::TZMSK64rr, X86::TZMSK64rm, 0 },
603 // AVX-512 foldable instructions
604 { X86::VMOV64toPQIZrr, X86::VMOVQI2PQIZrm, 0 },
605 { X86::VMOVDI2SSZrr, X86::VMOVDI2SSZrm, 0 },
606 { X86::VMOVDQA32rr, X86::VMOVDQA32rm, TB_ALIGN_64 },
607 { X86::VMOVDQA64rr, X86::VMOVDQA64rm, TB_ALIGN_64 },
608 { X86::VMOVDQU32rr, X86::VMOVDQU32rm, 0 },
609 { X86::VMOVDQU64rr, X86::VMOVDQU64rm, 0 },
610 { X86::VPABSDZrr, X86::VPABSDZrm, 0 },
611 { X86::VPABSQZrr, X86::VPABSQZrm, 0 },
613 // AES foldable instructions
614 { X86::AESIMCrr, X86::AESIMCrm, TB_ALIGN_16 },
615 { X86::AESKEYGENASSIST128rr, X86::AESKEYGENASSIST128rm, TB_ALIGN_16 },
616 { X86::VAESIMCrr, X86::VAESIMCrm, TB_ALIGN_16 },
617 { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, TB_ALIGN_16 },
618 };
620 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
621 unsigned RegOp = OpTbl1[i].RegOp;
622 unsigned MemOp = OpTbl1[i].MemOp;
623 unsigned Flags = OpTbl1[i].Flags;
624 AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
625 RegOp, MemOp,
626 // Index 1, folded load
627 Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
628 }
630 static const X86OpTblEntry OpTbl2[] = {
631 { X86::ADC32rr, X86::ADC32rm, 0 },
632 { X86::ADC64rr, X86::ADC64rm, 0 },
633 { X86::ADD16rr, X86::ADD16rm, 0 },
634 { X86::ADD16rr_DB, X86::ADD16rm, TB_NO_REVERSE },
635 { X86::ADD32rr, X86::ADD32rm, 0 },
636 { X86::ADD32rr_DB, X86::ADD32rm, TB_NO_REVERSE },
637 { X86::ADD64rr, X86::ADD64rm, 0 },
638 { X86::ADD64rr_DB, X86::ADD64rm, TB_NO_REVERSE },
639 { X86::ADD8rr, X86::ADD8rm, 0 },
640 { X86::ADDPDrr, X86::ADDPDrm, TB_ALIGN_16 },
641 { X86::ADDPSrr, X86::ADDPSrm, TB_ALIGN_16 },
642 { X86::ADDSDrr, X86::ADDSDrm, 0 },
643 { X86::ADDSSrr, X86::ADDSSrm, 0 },
644 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, TB_ALIGN_16 },
645 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, TB_ALIGN_16 },
646 { X86::AND16rr, X86::AND16rm, 0 },
647 { X86::AND32rr, X86::AND32rm, 0 },
648 { X86::AND64rr, X86::AND64rm, 0 },
649 { X86::AND8rr, X86::AND8rm, 0 },
650 { X86::ANDNPDrr, X86::ANDNPDrm, TB_ALIGN_16 },
651 { X86::ANDNPSrr, X86::ANDNPSrm, TB_ALIGN_16 },
652 { X86::ANDPDrr, X86::ANDPDrm, TB_ALIGN_16 },
653 { X86::ANDPSrr, X86::ANDPSrm, TB_ALIGN_16 },
654 { X86::BLENDPDrri, X86::BLENDPDrmi, TB_ALIGN_16 },
655 { X86::BLENDPSrri, X86::BLENDPSrmi, TB_ALIGN_16 },
656 { X86::BLENDVPDrr0, X86::BLENDVPDrm0, TB_ALIGN_16 },
657 { X86::BLENDVPSrr0, X86::BLENDVPSrm0, TB_ALIGN_16 },
658 { X86::CMOVA16rr, X86::CMOVA16rm, 0 },
659 { X86::CMOVA32rr, X86::CMOVA32rm, 0 },
660 { X86::CMOVA64rr, X86::CMOVA64rm, 0 },
661 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 },
662 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 },
663 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 },
664 { X86::CMOVB16rr, X86::CMOVB16rm, 0 },
665 { X86::CMOVB32rr, X86::CMOVB32rm, 0 },
666 { X86::CMOVB64rr, X86::CMOVB64rm, 0 },
667 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
668 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
669 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
670 { X86::CMOVE16rr, X86::CMOVE16rm, 0 },
671 { X86::CMOVE32rr, X86::CMOVE32rm, 0 },
672 { X86::CMOVE64rr, X86::CMOVE64rm, 0 },
673 { X86::CMOVG16rr, X86::CMOVG16rm, 0 },
674 { X86::CMOVG32rr, X86::CMOVG32rm, 0 },
675 { X86::CMOVG64rr, X86::CMOVG64rm, 0 },
676 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 },
677 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 },
678 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 },
679 { X86::CMOVL16rr, X86::CMOVL16rm, 0 },
680 { X86::CMOVL32rr, X86::CMOVL32rm, 0 },
681 { X86::CMOVL64rr, X86::CMOVL64rm, 0 },
682 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 },
683 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 },
684 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 },
685 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 },
686 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 },
687 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 },
688 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 },
689 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 },
690 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 },
691 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 },
692 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 },
693 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 },
694 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 },
695 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 },
696 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 },
697 { X86::CMOVO16rr, X86::CMOVO16rm, 0 },
698 { X86::CMOVO32rr, X86::CMOVO32rm, 0 },
699 { X86::CMOVO64rr, X86::CMOVO64rm, 0 },
700 { X86::CMOVP16rr, X86::CMOVP16rm, 0 },
701 { X86::CMOVP32rr, X86::CMOVP32rm, 0 },
702 { X86::CMOVP64rr, X86::CMOVP64rm, 0 },
703 { X86::CMOVS16rr, X86::CMOVS16rm, 0 },
704 { X86::CMOVS32rr, X86::CMOVS32rm, 0 },
705 { X86::CMOVS64rr, X86::CMOVS64rm, 0 },
706 { X86::CMPPDrri, X86::CMPPDrmi, TB_ALIGN_16 },
707 { X86::CMPPSrri, X86::CMPPSrmi, TB_ALIGN_16 },
708 { X86::CMPSDrr, X86::CMPSDrm, 0 },
709 { X86::CMPSSrr, X86::CMPSSrm, 0 },
710 { X86::DIVPDrr, X86::DIVPDrm, TB_ALIGN_16 },
711 { X86::DIVPSrr, X86::DIVPSrm, TB_ALIGN_16 },
712 { X86::DIVSDrr, X86::DIVSDrm, 0 },
713 { X86::DIVSSrr, X86::DIVSSrm, 0 },
714 { X86::FsANDNPDrr, X86::FsANDNPDrm, TB_ALIGN_16 },
715 { X86::FsANDNPSrr, X86::FsANDNPSrm, TB_ALIGN_16 },
716 { X86::FsANDPDrr, X86::FsANDPDrm, TB_ALIGN_16 },
717 { X86::FsANDPSrr, X86::FsANDPSrm, TB_ALIGN_16 },
718 { X86::FsORPDrr, X86::FsORPDrm, TB_ALIGN_16 },
719 { X86::FsORPSrr, X86::FsORPSrm, TB_ALIGN_16 },
720 { X86::FsXORPDrr, X86::FsXORPDrm, TB_ALIGN_16 },
721 { X86::FsXORPSrr, X86::FsXORPSrm, TB_ALIGN_16 },
722 { X86::HADDPDrr, X86::HADDPDrm, TB_ALIGN_16 },
723 { X86::HADDPSrr, X86::HADDPSrm, TB_ALIGN_16 },
724 { X86::HSUBPDrr, X86::HSUBPDrm, TB_ALIGN_16 },
725 { X86::HSUBPSrr, X86::HSUBPSrm, TB_ALIGN_16 },
726 { X86::IMUL16rr, X86::IMUL16rm, 0 },
727 { X86::IMUL32rr, X86::IMUL32rm, 0 },
728 { X86::IMUL64rr, X86::IMUL64rm, 0 },
729 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 },
730 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 },
731 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 },
732 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
733 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 },
734 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
735 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 },
736 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 },
737 { X86::MAXPDrr, X86::MAXPDrm, TB_ALIGN_16 },
738 { X86::MAXPSrr, X86::MAXPSrm, TB_ALIGN_16 },
739 { X86::MAXSDrr, X86::MAXSDrm, 0 },
740 { X86::MAXSSrr, X86::MAXSSrm, 0 },
741 { X86::MINPDrr, X86::MINPDrm, TB_ALIGN_16 },
742 { X86::MINPSrr, X86::MINPSrm, TB_ALIGN_16 },
743 { X86::MINSDrr, X86::MINSDrm, 0 },
744 { X86::MINSSrr, X86::MINSSrm, 0 },
745 { X86::MPSADBWrri, X86::MPSADBWrmi, TB_ALIGN_16 },
746 { X86::MULPDrr, X86::MULPDrm, TB_ALIGN_16 },
747 { X86::MULPSrr, X86::MULPSrm, TB_ALIGN_16 },
748 { X86::MULSDrr, X86::MULSDrm, 0 },
749 { X86::MULSSrr, X86::MULSSrm, 0 },
750 { X86::OR16rr, X86::OR16rm, 0 },
751 { X86::OR32rr, X86::OR32rm, 0 },
752 { X86::OR64rr, X86::OR64rm, 0 },
753 { X86::OR8rr, X86::OR8rm, 0 },
754 { X86::ORPDrr, X86::ORPDrm, TB_ALIGN_16 },
755 { X86::ORPSrr, X86::ORPSrm, TB_ALIGN_16 },
756 { X86::PACKSSDWrr, X86::PACKSSDWrm, TB_ALIGN_16 },
757 { X86::PACKSSWBrr, X86::PACKSSWBrm, TB_ALIGN_16 },
758 { X86::PACKUSDWrr, X86::PACKUSDWrm, TB_ALIGN_16 },
759 { X86::PACKUSWBrr, X86::PACKUSWBrm, TB_ALIGN_16 },
760 { X86::PADDBrr, X86::PADDBrm, TB_ALIGN_16 },
761 { X86::PADDDrr, X86::PADDDrm, TB_ALIGN_16 },
762 { X86::PADDQrr, X86::PADDQrm, TB_ALIGN_16 },
763 { X86::PADDSBrr, X86::PADDSBrm, TB_ALIGN_16 },
764 { X86::PADDSWrr, X86::PADDSWrm, TB_ALIGN_16 },
765 { X86::PADDUSBrr, X86::PADDUSBrm, TB_ALIGN_16 },
766 { X86::PADDUSWrr, X86::PADDUSWrm, TB_ALIGN_16 },
767 { X86::PADDWrr, X86::PADDWrm, TB_ALIGN_16 },
768 { X86::PALIGNR128rr, X86::PALIGNR128rm, TB_ALIGN_16 },
769 { X86::PANDNrr, X86::PANDNrm, TB_ALIGN_16 },
770 { X86::PANDrr, X86::PANDrm, TB_ALIGN_16 },
771 { X86::PAVGBrr, X86::PAVGBrm, TB_ALIGN_16 },
772 { X86::PAVGWrr, X86::PAVGWrm, TB_ALIGN_16 },
773 { X86::PBLENDWrri, X86::PBLENDWrmi, TB_ALIGN_16 },
774 { X86::PCMPEQBrr, X86::PCMPEQBrm, TB_ALIGN_16 },
775 { X86::PCMPEQDrr, X86::PCMPEQDrm, TB_ALIGN_16 },
776 { X86::PCMPEQQrr, X86::PCMPEQQrm, TB_ALIGN_16 },
777 { X86::PCMPEQWrr, X86::PCMPEQWrm, TB_ALIGN_16 },
778 { X86::PCMPGTBrr, X86::PCMPGTBrm, TB_ALIGN_16 },
779 { X86::PCMPGTDrr, X86::PCMPGTDrm, TB_ALIGN_16 },
780 { X86::PCMPGTQrr, X86::PCMPGTQrm, TB_ALIGN_16 },
781 { X86::PCMPGTWrr, X86::PCMPGTWrm, TB_ALIGN_16 },
782 { X86::PHADDDrr, X86::PHADDDrm, TB_ALIGN_16 },
783 { X86::PHADDWrr, X86::PHADDWrm, TB_ALIGN_16 },
784 { X86::PHADDSWrr128, X86::PHADDSWrm128, TB_ALIGN_16 },
785 { X86::PHSUBDrr, X86::PHSUBDrm, TB_ALIGN_16 },
786 { X86::PHSUBSWrr128, X86::PHSUBSWrm128, TB_ALIGN_16 },
787 { X86::PHSUBWrr, X86::PHSUBWrm, TB_ALIGN_16 },
788 { X86::PINSRWrri, X86::PINSRWrmi, TB_ALIGN_16 },
789 { X86::PMADDUBSWrr128, X86::PMADDUBSWrm128, TB_ALIGN_16 },
790 { X86::PMADDWDrr, X86::PMADDWDrm, TB_ALIGN_16 },
791 { X86::PMAXSWrr, X86::PMAXSWrm, TB_ALIGN_16 },
792 { X86::PMAXUBrr, X86::PMAXUBrm, TB_ALIGN_16 },
793 { X86::PMINSWrr, X86::PMINSWrm, TB_ALIGN_16 },
794 { X86::PMINUBrr, X86::PMINUBrm, TB_ALIGN_16 },
795 { X86::PMINSBrr, X86::PMINSBrm, TB_ALIGN_16 },
796 { X86::PMINSDrr, X86::PMINSDrm, TB_ALIGN_16 },
797 { X86::PMINUDrr, X86::PMINUDrm, TB_ALIGN_16 },
798 { X86::PMINUWrr, X86::PMINUWrm, TB_ALIGN_16 },
799 { X86::PMAXSBrr, X86::PMAXSBrm, TB_ALIGN_16 },
800 { X86::PMAXSDrr, X86::PMAXSDrm, TB_ALIGN_16 },
801 { X86::PMAXUDrr, X86::PMAXUDrm, TB_ALIGN_16 },
802 { X86::PMAXUWrr, X86::PMAXUWrm, TB_ALIGN_16 },
803 { X86::PMULDQrr, X86::PMULDQrm, TB_ALIGN_16 },
804 { X86::PMULHRSWrr128, X86::PMULHRSWrm128, TB_ALIGN_16 },
805 { X86::PMULHUWrr, X86::PMULHUWrm, TB_ALIGN_16 },
806 { X86::PMULHWrr, X86::PMULHWrm, TB_ALIGN_16 },
807 { X86::PMULLDrr, X86::PMULLDrm, TB_ALIGN_16 },
808 { X86::PMULLWrr, X86::PMULLWrm, TB_ALIGN_16 },
809 { X86::PMULUDQrr, X86::PMULUDQrm, TB_ALIGN_16 },
810 { X86::PORrr, X86::PORrm, TB_ALIGN_16 },
811 { X86::PSADBWrr, X86::PSADBWrm, TB_ALIGN_16 },
812 { X86::PSHUFBrr, X86::PSHUFBrm, TB_ALIGN_16 },
813 { X86::PSIGNBrr, X86::PSIGNBrm, TB_ALIGN_16 },
814 { X86::PSIGNWrr, X86::PSIGNWrm, TB_ALIGN_16 },
815 { X86::PSIGNDrr, X86::PSIGNDrm, TB_ALIGN_16 },
816 { X86::PSLLDrr, X86::PSLLDrm, TB_ALIGN_16 },
817 { X86::PSLLQrr, X86::PSLLQrm, TB_ALIGN_16 },
818 { X86::PSLLWrr, X86::PSLLWrm, TB_ALIGN_16 },
819 { X86::PSRADrr, X86::PSRADrm, TB_ALIGN_16 },
820 { X86::PSRAWrr, X86::PSRAWrm, TB_ALIGN_16 },
821 { X86::PSRLDrr, X86::PSRLDrm, TB_ALIGN_16 },
822 { X86::PSRLQrr, X86::PSRLQrm, TB_ALIGN_16 },
823 { X86::PSRLWrr, X86::PSRLWrm, TB_ALIGN_16 },
824 { X86::PSUBBrr, X86::PSUBBrm, TB_ALIGN_16 },
825 { X86::PSUBDrr, X86::PSUBDrm, TB_ALIGN_16 },
826 { X86::PSUBSBrr, X86::PSUBSBrm, TB_ALIGN_16 },
827 { X86::PSUBSWrr, X86::PSUBSWrm, TB_ALIGN_16 },
828 { X86::PSUBWrr, X86::PSUBWrm, TB_ALIGN_16 },
829 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, TB_ALIGN_16 },
830 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, TB_ALIGN_16 },
831 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, TB_ALIGN_16 },
832 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, TB_ALIGN_16 },
833 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, TB_ALIGN_16 },
834 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, TB_ALIGN_16 },
835 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, TB_ALIGN_16 },
836 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, TB_ALIGN_16 },
837 { X86::PXORrr, X86::PXORrm, TB_ALIGN_16 },
838 { X86::SBB32rr, X86::SBB32rm, 0 },
839 { X86::SBB64rr, X86::SBB64rm, 0 },
840 { X86::SHUFPDrri, X86::SHUFPDrmi, TB_ALIGN_16 },
841 { X86::SHUFPSrri, X86::SHUFPSrmi, TB_ALIGN_16 },
842 { X86::SUB16rr, X86::SUB16rm, 0 },
843 { X86::SUB32rr, X86::SUB32rm, 0 },
844 { X86::SUB64rr, X86::SUB64rm, 0 },
845 { X86::SUB8rr, X86::SUB8rm, 0 },
846 { X86::SUBPDrr, X86::SUBPDrm, TB_ALIGN_16 },
847 { X86::SUBPSrr, X86::SUBPSrm, TB_ALIGN_16 },
848 { X86::SUBSDrr, X86::SUBSDrm, 0 },
849 { X86::SUBSSrr, X86::SUBSSrm, 0 },
850 // FIXME: TEST*rr -> swapped operand of TEST*mr.
851 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, TB_ALIGN_16 },
852 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, TB_ALIGN_16 },
853 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, TB_ALIGN_16 },
854 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, TB_ALIGN_16 },
855 { X86::XOR16rr, X86::XOR16rm, 0 },
856 { X86::XOR32rr, X86::XOR32rm, 0 },
857 { X86::XOR64rr, X86::XOR64rm, 0 },
858 { X86::XOR8rr, X86::XOR8rm, 0 },
859 { X86::XORPDrr, X86::XORPDrm, TB_ALIGN_16 },
860 { X86::XORPSrr, X86::XORPSrm, TB_ALIGN_16 },
861 // AVX 128-bit versions of foldable instructions
862 { X86::VCVTSD2SSrr, X86::VCVTSD2SSrm, 0 },
863 { X86::Int_VCVTSD2SSrr, X86::Int_VCVTSD2SSrm, 0 },
864 { X86::VCVTSI2SD64rr, X86::VCVTSI2SD64rm, 0 },
865 { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm, 0 },
866 { X86::VCVTSI2SDrr, X86::VCVTSI2SDrm, 0 },
867 { X86::Int_VCVTSI2SDrr, X86::Int_VCVTSI2SDrm, 0 },
868 { X86::VCVTSI2SS64rr, X86::VCVTSI2SS64rm, 0 },
869 { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm, 0 },
870 { X86::VCVTSI2SSrr, X86::VCVTSI2SSrm, 0 },
871 { X86::Int_VCVTSI2SSrr, X86::Int_VCVTSI2SSrm, 0 },
872 { X86::VCVTSS2SDrr, X86::VCVTSS2SDrm, 0 },
873 { X86::Int_VCVTSS2SDrr, X86::Int_VCVTSS2SDrm, 0 },
874 { X86::VCVTTPD2DQrr, X86::VCVTTPD2DQXrm, 0 },
875 { X86::VCVTTPS2DQrr, X86::VCVTTPS2DQrm, 0 },
876 { X86::VRSQRTSSr, X86::VRSQRTSSm, 0 },
877 { X86::VSQRTSDr, X86::VSQRTSDm, 0 },
878 { X86::VSQRTSSr, X86::VSQRTSSm, 0 },
879 { X86::VADDPDrr, X86::VADDPDrm, 0 },
880 { X86::VADDPSrr, X86::VADDPSrm, 0 },
881 { X86::VADDSDrr, X86::VADDSDrm, 0 },
882 { X86::VADDSSrr, X86::VADDSSrm, 0 },
883 { X86::VADDSUBPDrr, X86::VADDSUBPDrm, 0 },
884 { X86::VADDSUBPSrr, X86::VADDSUBPSrm, 0 },
885 { X86::VANDNPDrr, X86::VANDNPDrm, 0 },
886 { X86::VANDNPSrr, X86::VANDNPSrm, 0 },
887 { X86::VANDPDrr, X86::VANDPDrm, 0 },
888 { X86::VANDPSrr, X86::VANDPSrm, 0 },
889 { X86::VBLENDPDrri, X86::VBLENDPDrmi, 0 },
890 { X86::VBLENDPSrri, X86::VBLENDPSrmi, 0 },
891 { X86::VBLENDVPDrr, X86::VBLENDVPDrm, 0 },
892 { X86::VBLENDVPSrr, X86::VBLENDVPSrm, 0 },
893 { X86::VCMPPDrri, X86::VCMPPDrmi, 0 },
894 { X86::VCMPPSrri, X86::VCMPPSrmi, 0 },
895 { X86::VCMPSDrr, X86::VCMPSDrm, 0 },
896 { X86::VCMPSSrr, X86::VCMPSSrm, 0 },
897 { X86::VDIVPDrr, X86::VDIVPDrm, 0 },
898 { X86::VDIVPSrr, X86::VDIVPSrm, 0 },
899 { X86::VDIVSDrr, X86::VDIVSDrm, 0 },
900 { X86::VDIVSSrr, X86::VDIVSSrm, 0 },
901 { X86::VFsANDNPDrr, X86::VFsANDNPDrm, TB_ALIGN_16 },
902 { X86::VFsANDNPSrr, X86::VFsANDNPSrm, TB_ALIGN_16 },
903 { X86::VFsANDPDrr, X86::VFsANDPDrm, TB_ALIGN_16 },
904 { X86::VFsANDPSrr, X86::VFsANDPSrm, TB_ALIGN_16 },
905 { X86::VFsORPDrr, X86::VFsORPDrm, TB_ALIGN_16 },
906 { X86::VFsORPSrr, X86::VFsORPSrm, TB_ALIGN_16 },
907 { X86::VFsXORPDrr, X86::VFsXORPDrm, TB_ALIGN_16 },
908 { X86::VFsXORPSrr, X86::VFsXORPSrm, TB_ALIGN_16 },
909 { X86::VHADDPDrr, X86::VHADDPDrm, 0 },
910 { X86::VHADDPSrr, X86::VHADDPSrm, 0 },
911 { X86::VHSUBPDrr, X86::VHSUBPDrm, 0 },
912 { X86::VHSUBPSrr, X86::VHSUBPSrm, 0 },
913 { X86::Int_VCMPSDrr, X86::Int_VCMPSDrm, 0 },
914 { X86::Int_VCMPSSrr, X86::Int_VCMPSSrm, 0 },
915 { X86::VMAXPDrr, X86::VMAXPDrm, 0 },
916 { X86::VMAXPSrr, X86::VMAXPSrm, 0 },
917 { X86::VMAXSDrr, X86::VMAXSDrm, 0 },
918 { X86::VMAXSSrr, X86::VMAXSSrm, 0 },
919 { X86::VMINPDrr, X86::VMINPDrm, 0 },
920 { X86::VMINPSrr, X86::VMINPSrm, 0 },
921 { X86::VMINSDrr, X86::VMINSDrm, 0 },
922 { X86::VMINSSrr, X86::VMINSSrm, 0 },
923 { X86::VMPSADBWrri, X86::VMPSADBWrmi, 0 },
924 { X86::VMULPDrr, X86::VMULPDrm, 0 },
925 { X86::VMULPSrr, X86::VMULPSrm, 0 },
926 { X86::VMULSDrr, X86::VMULSDrm, 0 },
927 { X86::VMULSSrr, X86::VMULSSrm, 0 },
928 { X86::VORPDrr, X86::VORPDrm, 0 },
929 { X86::VORPSrr, X86::VORPSrm, 0 },
930 { X86::VPACKSSDWrr, X86::VPACKSSDWrm, 0 },
931 { X86::VPACKSSWBrr, X86::VPACKSSWBrm, 0 },
932 { X86::VPACKUSDWrr, X86::VPACKUSDWrm, 0 },
933 { X86::VPACKUSWBrr, X86::VPACKUSWBrm, 0 },
934 { X86::VPADDBrr, X86::VPADDBrm, 0 },
935 { X86::VPADDDrr, X86::VPADDDrm, 0 },
936 { X86::VPADDQrr, X86::VPADDQrm, 0 },
937 { X86::VPADDSBrr, X86::VPADDSBrm, 0 },
938 { X86::VPADDSWrr, X86::VPADDSWrm, 0 },
939 { X86::VPADDUSBrr, X86::VPADDUSBrm, 0 },
940 { X86::VPADDUSWrr, X86::VPADDUSWrm, 0 },
941 { X86::VPADDWrr, X86::VPADDWrm, 0 },
942 { X86::VPALIGNR128rr, X86::VPALIGNR128rm, 0 },
943 { X86::VPANDNrr, X86::VPANDNrm, 0 },
944 { X86::VPANDrr, X86::VPANDrm, 0 },
945 { X86::VPAVGBrr, X86::VPAVGBrm, 0 },
946 { X86::VPAVGWrr, X86::VPAVGWrm, 0 },
947 { X86::VPBLENDWrri, X86::VPBLENDWrmi, 0 },
948 { X86::VPCMPEQBrr, X86::VPCMPEQBrm, 0 },
949 { X86::VPCMPEQDrr, X86::VPCMPEQDrm, 0 },
950 { X86::VPCMPEQQrr, X86::VPCMPEQQrm, 0 },
951 { X86::VPCMPEQWrr, X86::VPCMPEQWrm, 0 },
952 { X86::VPCMPGTBrr, X86::VPCMPGTBrm, 0 },
953 { X86::VPCMPGTDrr, X86::VPCMPGTDrm, 0 },
954 { X86::VPCMPGTQrr, X86::VPCMPGTQrm, 0 },
955 { X86::VPCMPGTWrr, X86::VPCMPGTWrm, 0 },
956 { X86::VPHADDDrr, X86::VPHADDDrm, 0 },
957 { X86::VPHADDSWrr128, X86::VPHADDSWrm128, 0 },
958 { X86::VPHADDWrr, X86::VPHADDWrm, 0 },
959 { X86::VPHSUBDrr, X86::VPHSUBDrm, 0 },
960 { X86::VPHSUBSWrr128, X86::VPHSUBSWrm128, 0 },
961 { X86::VPHSUBWrr, X86::VPHSUBWrm, 0 },
962 { X86::VPERMILPDrr, X86::VPERMILPDrm, 0 },
963 { X86::VPERMILPSrr, X86::VPERMILPSrm, 0 },
964 { X86::VPINSRWrri, X86::VPINSRWrmi, 0 },
965 { X86::VPMADDUBSWrr128, X86::VPMADDUBSWrm128, 0 },
966 { X86::VPMADDWDrr, X86::VPMADDWDrm, 0 },
967 { X86::VPMAXSWrr, X86::VPMAXSWrm, 0 },
968 { X86::VPMAXUBrr, X86::VPMAXUBrm, 0 },
969 { X86::VPMINSWrr, X86::VPMINSWrm, 0 },
970 { X86::VPMINUBrr, X86::VPMINUBrm, 0 },
971 { X86::VPMINSBrr, X86::VPMINSBrm, 0 },
972 { X86::VPMINSDrr, X86::VPMINSDrm, 0 },
973 { X86::VPMINUDrr, X86::VPMINUDrm, 0 },
974 { X86::VPMINUWrr, X86::VPMINUWrm, 0 },
975 { X86::VPMAXSBrr, X86::VPMAXSBrm, 0 },
976 { X86::VPMAXSDrr, X86::VPMAXSDrm, 0 },
977 { X86::VPMAXUDrr, X86::VPMAXUDrm, 0 },
978 { X86::VPMAXUWrr, X86::VPMAXUWrm, 0 },
979 { X86::VPMULDQrr, X86::VPMULDQrm, 0 },
980 { X86::VPMULHRSWrr128, X86::VPMULHRSWrm128, 0 },
981 { X86::VPMULHUWrr, X86::VPMULHUWrm, 0 },
982 { X86::VPMULHWrr, X86::VPMULHWrm, 0 },
983 { X86::VPMULLDrr, X86::VPMULLDrm, 0 },
984 { X86::VPMULLWrr, X86::VPMULLWrm, 0 },
985 { X86::VPMULUDQrr, X86::VPMULUDQrm, 0 },
986 { X86::VPORrr, X86::VPORrm, 0 },
987 { X86::VPSADBWrr, X86::VPSADBWrm, 0 },
988 { X86::VPSHUFBrr, X86::VPSHUFBrm, 0 },
989 { X86::VPSIGNBrr, X86::VPSIGNBrm, 0 },
990 { X86::VPSIGNWrr, X86::VPSIGNWrm, 0 },
991 { X86::VPSIGNDrr, X86::VPSIGNDrm, 0 },
992 { X86::VPSLLDrr, X86::VPSLLDrm, 0 },
993 { X86::VPSLLQrr, X86::VPSLLQrm, 0 },
994 { X86::VPSLLWrr, X86::VPSLLWrm, 0 },
995 { X86::VPSRADrr, X86::VPSRADrm, 0 },
996 { X86::VPSRAWrr, X86::VPSRAWrm, 0 },
997 { X86::VPSRLDrr, X86::VPSRLDrm, 0 },
998 { X86::VPSRLQrr, X86::VPSRLQrm, 0 },
999 { X86::VPSRLWrr, X86::VPSRLWrm, 0 },
1000 { X86::VPSUBBrr, X86::VPSUBBrm, 0 },
1001 { X86::VPSUBDrr, X86::VPSUBDrm, 0 },
1002 { X86::VPSUBSBrr, X86::VPSUBSBrm, 0 },
1003 { X86::VPSUBSWrr, X86::VPSUBSWrm, 0 },
1004 { X86::VPSUBWrr, X86::VPSUBWrm, 0 },
1005 { X86::VPUNPCKHBWrr, X86::VPUNPCKHBWrm, 0 },
1006 { X86::VPUNPCKHDQrr, X86::VPUNPCKHDQrm, 0 },
1007 { X86::VPUNPCKHQDQrr, X86::VPUNPCKHQDQrm, 0 },
1008 { X86::VPUNPCKHWDrr, X86::VPUNPCKHWDrm, 0 },
1009 { X86::VPUNPCKLBWrr, X86::VPUNPCKLBWrm, 0 },
1010 { X86::VPUNPCKLDQrr, X86::VPUNPCKLDQrm, 0 },
1011 { X86::VPUNPCKLQDQrr, X86::VPUNPCKLQDQrm, 0 },
1012 { X86::VPUNPCKLWDrr, X86::VPUNPCKLWDrm, 0 },
1013 { X86::VPXORrr, X86::VPXORrm, 0 },
1014 { X86::VSHUFPDrri, X86::VSHUFPDrmi, 0 },
1015 { X86::VSHUFPSrri, X86::VSHUFPSrmi, 0 },
1016 { X86::VSUBPDrr, X86::VSUBPDrm, 0 },
1017 { X86::VSUBPSrr, X86::VSUBPSrm, 0 },
1018 { X86::VSUBSDrr, X86::VSUBSDrm, 0 },
1019 { X86::VSUBSSrr, X86::VSUBSSrm, 0 },
1020 { X86::VUNPCKHPDrr, X86::VUNPCKHPDrm, 0 },
1021 { X86::VUNPCKHPSrr, X86::VUNPCKHPSrm, 0 },
1022 { X86::VUNPCKLPDrr, X86::VUNPCKLPDrm, 0 },
1023 { X86::VUNPCKLPSrr, X86::VUNPCKLPSrm, 0 },
1024 { X86::VXORPDrr, X86::VXORPDrm, 0 },
1025 { X86::VXORPSrr, X86::VXORPSrm, 0 },
1026 // AVX 256-bit foldable instructions
1027 { X86::VADDPDYrr, X86::VADDPDYrm, 0 },
1028 { X86::VADDPSYrr, X86::VADDPSYrm, 0 },
1029 { X86::VADDSUBPDYrr, X86::VADDSUBPDYrm, 0 },
1030 { X86::VADDSUBPSYrr, X86::VADDSUBPSYrm, 0 },
1031 { X86::VANDNPDYrr, X86::VANDNPDYrm, 0 },
1032 { X86::VANDNPSYrr, X86::VANDNPSYrm, 0 },
1033 { X86::VANDPDYrr, X86::VANDPDYrm, 0 },
1034 { X86::VANDPSYrr, X86::VANDPSYrm, 0 },
1035 { X86::VBLENDPDYrri, X86::VBLENDPDYrmi, 0 },
1036 { X86::VBLENDPSYrri, X86::VBLENDPSYrmi, 0 },
1037 { X86::VBLENDVPDYrr, X86::VBLENDVPDYrm, 0 },
1038 { X86::VBLENDVPSYrr, X86::VBLENDVPSYrm, 0 },
1039 { X86::VCMPPDYrri, X86::VCMPPDYrmi, 0 },
1040 { X86::VCMPPSYrri, X86::VCMPPSYrmi, 0 },
1041 { X86::VDIVPDYrr, X86::VDIVPDYrm, 0 },
1042 { X86::VDIVPSYrr, X86::VDIVPSYrm, 0 },
1043 { X86::VHADDPDYrr, X86::VHADDPDYrm, 0 },
1044 { X86::VHADDPSYrr, X86::VHADDPSYrm, 0 },
1045 { X86::VHSUBPDYrr, X86::VHSUBPDYrm, 0 },
1046 { X86::VHSUBPSYrr, X86::VHSUBPSYrm, 0 },
1047 { X86::VINSERTF128rr, X86::VINSERTF128rm, 0 },
1048 { X86::VMAXPDYrr, X86::VMAXPDYrm, 0 },
1049 { X86::VMAXPSYrr, X86::VMAXPSYrm, 0 },
1050 { X86::VMINPDYrr, X86::VMINPDYrm, 0 },
1051 { X86::VMINPSYrr, X86::VMINPSYrm, 0 },
1052 { X86::VMULPDYrr, X86::VMULPDYrm, 0 },
1053 { X86::VMULPSYrr, X86::VMULPSYrm, 0 },
1054 { X86::VORPDYrr, X86::VORPDYrm, 0 },
1055 { X86::VORPSYrr, X86::VORPSYrm, 0 },
1056 { X86::VPERM2F128rr, X86::VPERM2F128rm, 0 },
1057 { X86::VPERMILPDYrr, X86::VPERMILPDYrm, 0 },
1058 { X86::VPERMILPSYrr, X86::VPERMILPSYrm, 0 },
1059 { X86::VSHUFPDYrri, X86::VSHUFPDYrmi, 0 },
1060 { X86::VSHUFPSYrri, X86::VSHUFPSYrmi, 0 },
1061 { X86::VSUBPDYrr, X86::VSUBPDYrm, 0 },
1062 { X86::VSUBPSYrr, X86::VSUBPSYrm, 0 },
1063 { X86::VUNPCKHPDYrr, X86::VUNPCKHPDYrm, 0 },
1064 { X86::VUNPCKHPSYrr, X86::VUNPCKHPSYrm, 0 },
1065 { X86::VUNPCKLPDYrr, X86::VUNPCKLPDYrm, 0 },
1066 { X86::VUNPCKLPSYrr, X86::VUNPCKLPSYrm, 0 },
1067 { X86::VXORPDYrr, X86::VXORPDYrm, 0 },
1068 { X86::VXORPSYrr, X86::VXORPSYrm, 0 },
1069 // AVX2 foldable instructions
1070 { X86::VINSERTI128rr, X86::VINSERTI128rm, 0 },
1071 { X86::VPACKSSDWYrr, X86::VPACKSSDWYrm, 0 },
1072 { X86::VPACKSSWBYrr, X86::VPACKSSWBYrm, 0 },
1073 { X86::VPACKUSDWYrr, X86::VPACKUSDWYrm, 0 },
1074 { X86::VPACKUSWBYrr, X86::VPACKUSWBYrm, 0 },
1075 { X86::VPADDBYrr, X86::VPADDBYrm, 0 },
1076 { X86::VPADDDYrr, X86::VPADDDYrm, 0 },
1077 { X86::VPADDQYrr, X86::VPADDQYrm, 0 },
1078 { X86::VPADDSBYrr, X86::VPADDSBYrm, 0 },
1079 { X86::VPADDSWYrr, X86::VPADDSWYrm, 0 },
1080 { X86::VPADDUSBYrr, X86::VPADDUSBYrm, 0 },
1081 { X86::VPADDUSWYrr, X86::VPADDUSWYrm, 0 },
1082 { X86::VPADDWYrr, X86::VPADDWYrm, 0 },
1083 { X86::VPALIGNR256rr, X86::VPALIGNR256rm, 0 },
1084 { X86::VPANDNYrr, X86::VPANDNYrm, 0 },
1085 { X86::VPANDYrr, X86::VPANDYrm, 0 },
1086 { X86::VPAVGBYrr, X86::VPAVGBYrm, 0 },
1087 { X86::VPAVGWYrr, X86::VPAVGWYrm, 0 },
1088 { X86::VPBLENDDrri, X86::VPBLENDDrmi, 0 },
1089 { X86::VPBLENDDYrri, X86::VPBLENDDYrmi, 0 },
1090 { X86::VPBLENDWYrri, X86::VPBLENDWYrmi, 0 },
1091 { X86::VPCMPEQBYrr, X86::VPCMPEQBYrm, 0 },
1092 { X86::VPCMPEQDYrr, X86::VPCMPEQDYrm, 0 },
1093 { X86::VPCMPEQQYrr, X86::VPCMPEQQYrm, 0 },
1094 { X86::VPCMPEQWYrr, X86::VPCMPEQWYrm, 0 },
1095 { X86::VPCMPGTBYrr, X86::VPCMPGTBYrm, 0 },
1096 { X86::VPCMPGTDYrr, X86::VPCMPGTDYrm, 0 },
1097 { X86::VPCMPGTQYrr, X86::VPCMPGTQYrm, 0 },
1098 { X86::VPCMPGTWYrr, X86::VPCMPGTWYrm, 0 },
1099 { X86::VPERM2I128rr, X86::VPERM2I128rm, 0 },
1100 { X86::VPERMDYrr, X86::VPERMDYrm, 0 },
1101 { X86::VPERMPDYri, X86::VPERMPDYmi, 0 },
1102 { X86::VPERMPSYrr, X86::VPERMPSYrm, 0 },
1103 { X86::VPERMQYri, X86::VPERMQYmi, 0 },
1104 { X86::VPHADDDYrr, X86::VPHADDDYrm, 0 },
1105 { X86::VPHADDSWrr256, X86::VPHADDSWrm256, 0 },
1106 { X86::VPHADDWYrr, X86::VPHADDWYrm, 0 },
1107 { X86::VPHSUBDYrr, X86::VPHSUBDYrm, 0 },
1108 { X86::VPHSUBSWrr256, X86::VPHSUBSWrm256, 0 },
1109 { X86::VPHSUBWYrr, X86::VPHSUBWYrm, 0 },
1110 { X86::VPMADDUBSWrr256, X86::VPMADDUBSWrm256, 0 },
1111 { X86::VPMADDWDYrr, X86::VPMADDWDYrm, 0 },
1112 { X86::VPMAXSWYrr, X86::VPMAXSWYrm, 0 },
1113 { X86::VPMAXUBYrr, X86::VPMAXUBYrm, 0 },
1114 { X86::VPMINSWYrr, X86::VPMINSWYrm, 0 },
1115 { X86::VPMINUBYrr, X86::VPMINUBYrm, 0 },
1116 { X86::VPMINSBYrr, X86::VPMINSBYrm, 0 },
1117 { X86::VPMINSDYrr, X86::VPMINSDYrm, 0 },
1118 { X86::VPMINUDYrr, X86::VPMINUDYrm, 0 },
1119 { X86::VPMINUWYrr, X86::VPMINUWYrm, 0 },
1120 { X86::VPMAXSBYrr, X86::VPMAXSBYrm, 0 },
1121 { X86::VPMAXSDYrr, X86::VPMAXSDYrm, 0 },
1122 { X86::VPMAXUDYrr, X86::VPMAXUDYrm, 0 },
1123 { X86::VPMAXUWYrr, X86::VPMAXUWYrm, 0 },
1124 { X86::VMPSADBWYrri, X86::VMPSADBWYrmi, 0 },
1125 { X86::VPMULDQYrr, X86::VPMULDQYrm, 0 },
1126 { X86::VPMULHRSWrr256, X86::VPMULHRSWrm256, 0 },
1127 { X86::VPMULHUWYrr, X86::VPMULHUWYrm, 0 },
1128 { X86::VPMULHWYrr, X86::VPMULHWYrm, 0 },
1129 { X86::VPMULLDYrr, X86::VPMULLDYrm, 0 },
1130 { X86::VPMULLWYrr, X86::VPMULLWYrm, 0 },
1131 { X86::VPMULUDQYrr, X86::VPMULUDQYrm, 0 },
1132 { X86::VPORYrr, X86::VPORYrm, 0 },
1133 { X86::VPSADBWYrr, X86::VPSADBWYrm, 0 },
1134 { X86::VPSHUFBYrr, X86::VPSHUFBYrm, 0 },
1135 { X86::VPSIGNBYrr, X86::VPSIGNBYrm, 0 },
1136 { X86::VPSIGNWYrr, X86::VPSIGNWYrm, 0 },
1137 { X86::VPSIGNDYrr, X86::VPSIGNDYrm, 0 },
1138 { X86::VPSLLDYrr, X86::VPSLLDYrm, 0 },
1139 { X86::VPSLLQYrr, X86::VPSLLQYrm, 0 },
1140 { X86::VPSLLWYrr, X86::VPSLLWYrm, 0 },
1141 { X86::VPSLLVDrr, X86::VPSLLVDrm, 0 },
1142 { X86::VPSLLVDYrr, X86::VPSLLVDYrm, 0 },
1143 { X86::VPSLLVQrr, X86::VPSLLVQrm, 0 },
1144 { X86::VPSLLVQYrr, X86::VPSLLVQYrm, 0 },
1145 { X86::VPSRADYrr, X86::VPSRADYrm, 0 },
1146 { X86::VPSRAWYrr, X86::VPSRAWYrm, 0 },
1147 { X86::VPSRAVDrr, X86::VPSRAVDrm, 0 },
1148 { X86::VPSRAVDYrr, X86::VPSRAVDYrm, 0 },
1149 { X86::VPSRLDYrr, X86::VPSRLDYrm, 0 },
1150 { X86::VPSRLQYrr, X86::VPSRLQYrm, 0 },
1151 { X86::VPSRLWYrr, X86::VPSRLWYrm, 0 },
1152 { X86::VPSRLVDrr, X86::VPSRLVDrm, 0 },
1153 { X86::VPSRLVDYrr, X86::VPSRLVDYrm, 0 },
1154 { X86::VPSRLVQrr, X86::VPSRLVQrm, 0 },
1155 { X86::VPSRLVQYrr, X86::VPSRLVQYrm, 0 },
1156 { X86::VPSUBBYrr, X86::VPSUBBYrm, 0 },
1157 { X86::VPSUBDYrr, X86::VPSUBDYrm, 0 },
1158 { X86::VPSUBSBYrr, X86::VPSUBSBYrm, 0 },
1159 { X86::VPSUBSWYrr, X86::VPSUBSWYrm, 0 },
1160 { X86::VPSUBWYrr, X86::VPSUBWYrm, 0 },
1161 { X86::VPUNPCKHBWYrr, X86::VPUNPCKHBWYrm, 0 },
1162 { X86::VPUNPCKHDQYrr, X86::VPUNPCKHDQYrm, 0 },
1163 { X86::VPUNPCKHQDQYrr, X86::VPUNPCKHQDQYrm, 0 },
1164 { X86::VPUNPCKHWDYrr, X86::VPUNPCKHWDYrm, 0 },
1165 { X86::VPUNPCKLBWYrr, X86::VPUNPCKLBWYrm, 0 },
1166 { X86::VPUNPCKLDQYrr, X86::VPUNPCKLDQYrm, 0 },
1167 { X86::VPUNPCKLQDQYrr, X86::VPUNPCKLQDQYrm, 0 },
1168 { X86::VPUNPCKLWDYrr, X86::VPUNPCKLWDYrm, 0 },
1169 { X86::VPXORYrr, X86::VPXORYrm, 0 },
1170 // FIXME: add AVX 256-bit foldable instructions
1172 // FMA4 foldable patterns
1173 { X86::VFMADDSS4rr, X86::VFMADDSS4mr, 0 },
1174 { X86::VFMADDSD4rr, X86::VFMADDSD4mr, 0 },
1175 { X86::VFMADDPS4rr, X86::VFMADDPS4mr, TB_ALIGN_16 },
1176 { X86::VFMADDPD4rr, X86::VFMADDPD4mr, TB_ALIGN_16 },
1177 { X86::VFMADDPS4rrY, X86::VFMADDPS4mrY, TB_ALIGN_32 },
1178 { X86::VFMADDPD4rrY, X86::VFMADDPD4mrY, TB_ALIGN_32 },
1179 { X86::VFNMADDSS4rr, X86::VFNMADDSS4mr, 0 },
1180 { X86::VFNMADDSD4rr, X86::VFNMADDSD4mr, 0 },
1181 { X86::VFNMADDPS4rr, X86::VFNMADDPS4mr, TB_ALIGN_16 },
1182 { X86::VFNMADDPD4rr, X86::VFNMADDPD4mr, TB_ALIGN_16 },
1183 { X86::VFNMADDPS4rrY, X86::VFNMADDPS4mrY, TB_ALIGN_32 },
1184 { X86::VFNMADDPD4rrY, X86::VFNMADDPD4mrY, TB_ALIGN_32 },
1185 { X86::VFMSUBSS4rr, X86::VFMSUBSS4mr, 0 },
1186 { X86::VFMSUBSD4rr, X86::VFMSUBSD4mr, 0 },
1187 { X86::VFMSUBPS4rr, X86::VFMSUBPS4mr, TB_ALIGN_16 },
1188 { X86::VFMSUBPD4rr, X86::VFMSUBPD4mr, TB_ALIGN_16 },
1189 { X86::VFMSUBPS4rrY, X86::VFMSUBPS4mrY, TB_ALIGN_32 },
1190 { X86::VFMSUBPD4rrY, X86::VFMSUBPD4mrY, TB_ALIGN_32 },
1191 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4mr, 0 },
1192 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4mr, 0 },
1193 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4mr, TB_ALIGN_16 },
1194 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4mr, TB_ALIGN_16 },
1195 { X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4mrY, TB_ALIGN_32 },
1196 { X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4mrY, TB_ALIGN_32 },
1197 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4mr, TB_ALIGN_16 },
1198 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4mr, TB_ALIGN_16 },
1199 { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4mrY, TB_ALIGN_32 },
1200 { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4mrY, TB_ALIGN_32 },
1201 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4mr, TB_ALIGN_16 },
1202 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4mr, TB_ALIGN_16 },
1203 { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4mrY, TB_ALIGN_32 },
1204 { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4mrY, TB_ALIGN_32 },
1206 // BMI/BMI2 foldable instructions
1207 { X86::ANDN32rr, X86::ANDN32rm, 0 },
1208 { X86::ANDN64rr, X86::ANDN64rm, 0 },
1209 { X86::MULX32rr, X86::MULX32rm, 0 },
1210 { X86::MULX64rr, X86::MULX64rm, 0 },
1211 { X86::PDEP32rr, X86::PDEP32rm, 0 },
1212 { X86::PDEP64rr, X86::PDEP64rm, 0 },
1213 { X86::PEXT32rr, X86::PEXT32rm, 0 },
1214 { X86::PEXT64rr, X86::PEXT64rm, 0 },
1216 // AVX-512 foldable instructions
1217 { X86::VADDPSZrr, X86::VADDPSZrm, 0 },
1218 { X86::VADDPDZrr, X86::VADDPDZrm, 0 },
1219 { X86::VSUBPSZrr, X86::VSUBPSZrm, 0 },
1220 { X86::VSUBPDZrr, X86::VSUBPDZrm, 0 },
1221 { X86::VMULPSZrr, X86::VMULPSZrm, 0 },
1222 { X86::VMULPDZrr, X86::VMULPDZrm, 0 },
1223 { X86::VDIVPSZrr, X86::VDIVPSZrm, 0 },
1224 { X86::VDIVPDZrr, X86::VDIVPDZrm, 0 },
1225 { X86::VMINPSZrr, X86::VMINPSZrm, 0 },
1226 { X86::VMINPDZrr, X86::VMINPDZrm, 0 },
1227 { X86::VMAXPSZrr, X86::VMAXPSZrm, 0 },
1228 { X86::VMAXPDZrr, X86::VMAXPDZrm, 0 },
1229 { X86::VPADDDZrr, X86::VPADDDZrm, 0 },
1230 { X86::VPADDQZrr, X86::VPADDQZrm, 0 },
1231 { X86::VPERMPDZri, X86::VPERMPDZmi, 0 },
1232 { X86::VPERMPSZrr, X86::VPERMPSZrm, 0 },
1233 { X86::VPMAXSDZrr, X86::VPMAXSDZrm, 0 },
1234 { X86::VPMAXSQZrr, X86::VPMAXSQZrm, 0 },
1235 { X86::VPMAXUDZrr, X86::VPMAXUDZrm, 0 },
1236 { X86::VPMAXUQZrr, X86::VPMAXUQZrm, 0 },
1237 { X86::VPMINSDZrr, X86::VPMINSDZrm, 0 },
1238 { X86::VPMINSQZrr, X86::VPMINSQZrm, 0 },
1239 { X86::VPMINUDZrr, X86::VPMINUDZrm, 0 },
1240 { X86::VPMINUQZrr, X86::VPMINUQZrm, 0 },
1241 { X86::VPMULDQZrr, X86::VPMULDQZrm, 0 },
1242 { X86::VPSLLVDZrr, X86::VPSLLVDZrm, 0 },
1243 { X86::VPSLLVQZrr, X86::VPSLLVQZrm, 0 },
1244 { X86::VPSRAVDZrr, X86::VPSRAVDZrm, 0 },
1245 { X86::VPSRLVDZrr, X86::VPSRLVDZrm, 0 },
1246 { X86::VPSRLVQZrr, X86::VPSRLVQZrm, 0 },
1247 { X86::VPSUBDZrr, X86::VPSUBDZrm, 0 },
1248 { X86::VPSUBQZrr, X86::VPSUBQZrm, 0 },
1249 { X86::VSHUFPDZrri, X86::VSHUFPDZrmi, 0 },
1250 { X86::VSHUFPSZrri, X86::VSHUFPSZrmi, 0 },
1251 { X86::VALIGNQrri, X86::VALIGNQrmi, 0 },
1252 { X86::VALIGNDrri, X86::VALIGNDrmi, 0 },
1253 { X86::VPMULUDQZrr, X86::VPMULUDQZrm, 0 },
1255 // AES foldable instructions
1256 { X86::AESDECLASTrr, X86::AESDECLASTrm, TB_ALIGN_16 },
1257 { X86::AESDECrr, X86::AESDECrm, TB_ALIGN_16 },
1258 { X86::AESENCLASTrr, X86::AESENCLASTrm, TB_ALIGN_16 },
1259 { X86::AESENCrr, X86::AESENCrm, TB_ALIGN_16 },
1260 { X86::VAESDECLASTrr, X86::VAESDECLASTrm, TB_ALIGN_16 },
1261 { X86::VAESDECrr, X86::VAESDECrm, TB_ALIGN_16 },
1262 { X86::VAESENCLASTrr, X86::VAESENCLASTrm, TB_ALIGN_16 },
1263 { X86::VAESENCrr, X86::VAESENCrm, TB_ALIGN_16 },
1265 // SHA foldable instructions
1266 { X86::SHA1MSG1rr, X86::SHA1MSG1rm, TB_ALIGN_16 },
1267 { X86::SHA1MSG2rr, X86::SHA1MSG2rm, TB_ALIGN_16 },
1268 { X86::SHA1NEXTErr, X86::SHA1NEXTErm, TB_ALIGN_16 },
1269 { X86::SHA1RNDS4rri, X86::SHA1RNDS4rmi, TB_ALIGN_16 },
1270 { X86::SHA256MSG1rr, X86::SHA256MSG1rm, TB_ALIGN_16 },
1271 { X86::SHA256MSG2rr, X86::SHA256MSG2rm, TB_ALIGN_16 },
1272 { X86::SHA256RNDS2rr, X86::SHA256RNDS2rm, TB_ALIGN_16 },
1273 };
1275 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
1276 unsigned RegOp = OpTbl2[i].RegOp;
1277 unsigned MemOp = OpTbl2[i].MemOp;
1278 unsigned Flags = OpTbl2[i].Flags;
1279 AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
1280 RegOp, MemOp,
1281 // Index 2, folded load
1282 Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
1283 }
1285 static const X86OpTblEntry OpTbl3[] = {
1286 // FMA foldable instructions
1287 { X86::VFMADDSSr231r, X86::VFMADDSSr231m, TB_ALIGN_NONE },
1288 { X86::VFMADDSDr231r, X86::VFMADDSDr231m, TB_ALIGN_NONE },
1289 { X86::VFMADDSSr132r, X86::VFMADDSSr132m, TB_ALIGN_NONE },
1290 { X86::VFMADDSDr132r, X86::VFMADDSDr132m, TB_ALIGN_NONE },
1291 { X86::VFMADDSSr213r, X86::VFMADDSSr213m, TB_ALIGN_NONE },
1292 { X86::VFMADDSDr213r, X86::VFMADDSDr213m, TB_ALIGN_NONE },
1294 { X86::VFMADDPSr231r, X86::VFMADDPSr231m, TB_ALIGN_NONE },
1295 { X86::VFMADDPDr231r, X86::VFMADDPDr231m, TB_ALIGN_NONE },
1296 { X86::VFMADDPSr132r, X86::VFMADDPSr132m, TB_ALIGN_NONE },
1297 { X86::VFMADDPDr132r, X86::VFMADDPDr132m, TB_ALIGN_NONE },
1298 { X86::VFMADDPSr213r, X86::VFMADDPSr213m, TB_ALIGN_NONE },
1299 { X86::VFMADDPDr213r, X86::VFMADDPDr213m, TB_ALIGN_NONE },
1300 { X86::VFMADDPSr231rY, X86::VFMADDPSr231mY, TB_ALIGN_NONE },
1301 { X86::VFMADDPDr231rY, X86::VFMADDPDr231mY, TB_ALIGN_NONE },
1302 { X86::VFMADDPSr132rY, X86::VFMADDPSr132mY, TB_ALIGN_NONE },
1303 { X86::VFMADDPDr132rY, X86::VFMADDPDr132mY, TB_ALIGN_NONE },
1304 { X86::VFMADDPSr213rY, X86::VFMADDPSr213mY, TB_ALIGN_NONE },
1305 { X86::VFMADDPDr213rY, X86::VFMADDPDr213mY, TB_ALIGN_NONE },
1307 { X86::VFNMADDSSr231r, X86::VFNMADDSSr231m, TB_ALIGN_NONE },
1308 { X86::VFNMADDSDr231r, X86::VFNMADDSDr231m, TB_ALIGN_NONE },
1309 { X86::VFNMADDSSr132r, X86::VFNMADDSSr132m, TB_ALIGN_NONE },
1310 { X86::VFNMADDSDr132r, X86::VFNMADDSDr132m, TB_ALIGN_NONE },
1311 { X86::VFNMADDSSr213r, X86::VFNMADDSSr213m, TB_ALIGN_NONE },
1312 { X86::VFNMADDSDr213r, X86::VFNMADDSDr213m, TB_ALIGN_NONE },
1314 { X86::VFNMADDPSr231r, X86::VFNMADDPSr231m, TB_ALIGN_NONE },
1315 { X86::VFNMADDPDr231r, X86::VFNMADDPDr231m, TB_ALIGN_NONE },
1316 { X86::VFNMADDPSr132r, X86::VFNMADDPSr132m, TB_ALIGN_NONE },
1317 { X86::VFNMADDPDr132r, X86::VFNMADDPDr132m, TB_ALIGN_NONE },
1318 { X86::VFNMADDPSr213r, X86::VFNMADDPSr213m, TB_ALIGN_NONE },
1319 { X86::VFNMADDPDr213r, X86::VFNMADDPDr213m, TB_ALIGN_NONE },
1320 { X86::VFNMADDPSr231rY, X86::VFNMADDPSr231mY, TB_ALIGN_NONE },
1321 { X86::VFNMADDPDr231rY, X86::VFNMADDPDr231mY, TB_ALIGN_NONE },
1322 { X86::VFNMADDPSr132rY, X86::VFNMADDPSr132mY, TB_ALIGN_NONE },
1323 { X86::VFNMADDPDr132rY, X86::VFNMADDPDr132mY, TB_ALIGN_NONE },
1324 { X86::VFNMADDPSr213rY, X86::VFNMADDPSr213mY, TB_ALIGN_NONE },
1325 { X86::VFNMADDPDr213rY, X86::VFNMADDPDr213mY, TB_ALIGN_NONE },
1327 { X86::VFMSUBSSr231r, X86::VFMSUBSSr231m, TB_ALIGN_NONE },
1328 { X86::VFMSUBSDr231r, X86::VFMSUBSDr231m, TB_ALIGN_NONE },
1329 { X86::VFMSUBSSr132r, X86::VFMSUBSSr132m, TB_ALIGN_NONE },
1330 { X86::VFMSUBSDr132r, X86::VFMSUBSDr132m, TB_ALIGN_NONE },
1331 { X86::VFMSUBSSr213r, X86::VFMSUBSSr213m, TB_ALIGN_NONE },
1332 { X86::VFMSUBSDr213r, X86::VFMSUBSDr213m, TB_ALIGN_NONE },
1334 { X86::VFMSUBPSr231r, X86::VFMSUBPSr231m, TB_ALIGN_NONE },
1335 { X86::VFMSUBPDr231r, X86::VFMSUBPDr231m, TB_ALIGN_NONE },
1336 { X86::VFMSUBPSr132r, X86::VFMSUBPSr132m, TB_ALIGN_NONE },
1337 { X86::VFMSUBPDr132r, X86::VFMSUBPDr132m, TB_ALIGN_NONE },
1338 { X86::VFMSUBPSr213r, X86::VFMSUBPSr213m, TB_ALIGN_NONE },
1339 { X86::VFMSUBPDr213r, X86::VFMSUBPDr213m, TB_ALIGN_NONE },
1340 { X86::VFMSUBPSr231rY, X86::VFMSUBPSr231mY, TB_ALIGN_NONE },
1341 { X86::VFMSUBPDr231rY, X86::VFMSUBPDr231mY, TB_ALIGN_NONE },
1342 { X86::VFMSUBPSr132rY, X86::VFMSUBPSr132mY, TB_ALIGN_NONE },
1343 { X86::VFMSUBPDr132rY, X86::VFMSUBPDr132mY, TB_ALIGN_NONE },
1344 { X86::VFMSUBPSr213rY, X86::VFMSUBPSr213mY, TB_ALIGN_NONE },
1345 { X86::VFMSUBPDr213rY, X86::VFMSUBPDr213mY, TB_ALIGN_NONE },
1347 { X86::VFNMSUBSSr231r, X86::VFNMSUBSSr231m, TB_ALIGN_NONE },
1348 { X86::VFNMSUBSDr231r, X86::VFNMSUBSDr231m, TB_ALIGN_NONE },
1349 { X86::VFNMSUBSSr132r, X86::VFNMSUBSSr132m, TB_ALIGN_NONE },
1350 { X86::VFNMSUBSDr132r, X86::VFNMSUBSDr132m, TB_ALIGN_NONE },
1351 { X86::VFNMSUBSSr213r, X86::VFNMSUBSSr213m, TB_ALIGN_NONE },
1352 { X86::VFNMSUBSDr213r, X86::VFNMSUBSDr213m, TB_ALIGN_NONE },
1354 { X86::VFNMSUBPSr231r, X86::VFNMSUBPSr231m, TB_ALIGN_NONE },
1355 { X86::VFNMSUBPDr231r, X86::VFNMSUBPDr231m, TB_ALIGN_NONE },
1356 { X86::VFNMSUBPSr132r, X86::VFNMSUBPSr132m, TB_ALIGN_NONE },
1357 { X86::VFNMSUBPDr132r, X86::VFNMSUBPDr132m, TB_ALIGN_NONE },
1358 { X86::VFNMSUBPSr213r, X86::VFNMSUBPSr213m, TB_ALIGN_NONE },
1359 { X86::VFNMSUBPDr213r, X86::VFNMSUBPDr213m, TB_ALIGN_NONE },
1360 { X86::VFNMSUBPSr231rY, X86::VFNMSUBPSr231mY, TB_ALIGN_NONE },
1361 { X86::VFNMSUBPDr231rY, X86::VFNMSUBPDr231mY, TB_ALIGN_NONE },
1362 { X86::VFNMSUBPSr132rY, X86::VFNMSUBPSr132mY, TB_ALIGN_NONE },
1363 { X86::VFNMSUBPDr132rY, X86::VFNMSUBPDr132mY, TB_ALIGN_NONE },
1364 { X86::VFNMSUBPSr213rY, X86::VFNMSUBPSr213mY, TB_ALIGN_NONE },
1365 { X86::VFNMSUBPDr213rY, X86::VFNMSUBPDr213mY, TB_ALIGN_NONE },
1367 { X86::VFMADDSUBPSr231r, X86::VFMADDSUBPSr231m, TB_ALIGN_NONE },
1368 { X86::VFMADDSUBPDr231r, X86::VFMADDSUBPDr231m, TB_ALIGN_NONE },
1369 { X86::VFMADDSUBPSr132r, X86::VFMADDSUBPSr132m, TB_ALIGN_NONE },
1370 { X86::VFMADDSUBPDr132r, X86::VFMADDSUBPDr132m, TB_ALIGN_NONE },
1371 { X86::VFMADDSUBPSr213r, X86::VFMADDSUBPSr213m, TB_ALIGN_NONE },
1372 { X86::VFMADDSUBPDr213r, X86::VFMADDSUBPDr213m, TB_ALIGN_NONE },
1373 { X86::VFMADDSUBPSr231rY, X86::VFMADDSUBPSr231mY, TB_ALIGN_NONE },
1374 { X86::VFMADDSUBPDr231rY, X86::VFMADDSUBPDr231mY, TB_ALIGN_NONE },
1375 { X86::VFMADDSUBPSr132rY, X86::VFMADDSUBPSr132mY, TB_ALIGN_NONE },
1376 { X86::VFMADDSUBPDr132rY, X86::VFMADDSUBPDr132mY, TB_ALIGN_NONE },
1377 { X86::VFMADDSUBPSr213rY, X86::VFMADDSUBPSr213mY, TB_ALIGN_NONE },
1378 { X86::VFMADDSUBPDr213rY, X86::VFMADDSUBPDr213mY, TB_ALIGN_NONE },
1380 { X86::VFMSUBADDPSr231r, X86::VFMSUBADDPSr231m, TB_ALIGN_NONE },
1381 { X86::VFMSUBADDPDr231r, X86::VFMSUBADDPDr231m, TB_ALIGN_NONE },
1382 { X86::VFMSUBADDPSr132r, X86::VFMSUBADDPSr132m, TB_ALIGN_NONE },
1383 { X86::VFMSUBADDPDr132r, X86::VFMSUBADDPDr132m, TB_ALIGN_NONE },
1384 { X86::VFMSUBADDPSr213r, X86::VFMSUBADDPSr213m, TB_ALIGN_NONE },
1385 { X86::VFMSUBADDPDr213r, X86::VFMSUBADDPDr213m, TB_ALIGN_NONE },
1386 { X86::VFMSUBADDPSr231rY, X86::VFMSUBADDPSr231mY, TB_ALIGN_NONE },
1387 { X86::VFMSUBADDPDr231rY, X86::VFMSUBADDPDr231mY, TB_ALIGN_NONE },
1388 { X86::VFMSUBADDPSr132rY, X86::VFMSUBADDPSr132mY, TB_ALIGN_NONE },
1389 { X86::VFMSUBADDPDr132rY, X86::VFMSUBADDPDr132mY, TB_ALIGN_NONE },
1390 { X86::VFMSUBADDPSr213rY, X86::VFMSUBADDPSr213mY, TB_ALIGN_NONE },
1391 { X86::VFMSUBADDPDr213rY, X86::VFMSUBADDPDr213mY, TB_ALIGN_NONE },
1393 // FMA4 foldable patterns
1394 { X86::VFMADDSS4rr, X86::VFMADDSS4rm, 0 },
1395 { X86::VFMADDSD4rr, X86::VFMADDSD4rm, 0 },
1396 { X86::VFMADDPS4rr, X86::VFMADDPS4rm, TB_ALIGN_16 },
1397 { X86::VFMADDPD4rr, X86::VFMADDPD4rm, TB_ALIGN_16 },
1398 { X86::VFMADDPS4rrY, X86::VFMADDPS4rmY, TB_ALIGN_32 },
1399 { X86::VFMADDPD4rrY, X86::VFMADDPD4rmY, TB_ALIGN_32 },
1400 { X86::VFNMADDSS4rr, X86::VFNMADDSS4rm, 0 },
1401 { X86::VFNMADDSD4rr, X86::VFNMADDSD4rm, 0 },
1402 { X86::VFNMADDPS4rr, X86::VFNMADDPS4rm, TB_ALIGN_16 },
1403 { X86::VFNMADDPD4rr, X86::VFNMADDPD4rm, TB_ALIGN_16 },
1404 { X86::VFNMADDPS4rrY, X86::VFNMADDPS4rmY, TB_ALIGN_32 },
1405 { X86::VFNMADDPD4rrY, X86::VFNMADDPD4rmY, TB_ALIGN_32 },
1406 { X86::VFMSUBSS4rr, X86::VFMSUBSS4rm, 0 },
1407 { X86::VFMSUBSD4rr, X86::VFMSUBSD4rm, 0 },
1408 { X86::VFMSUBPS4rr, X86::VFMSUBPS4rm, TB_ALIGN_16 },
1409 { X86::VFMSUBPD4rr, X86::VFMSUBPD4rm, TB_ALIGN_16 },
1410 { X86::VFMSUBPS4rrY, X86::VFMSUBPS4rmY, TB_ALIGN_32 },
1411 { X86::VFMSUBPD4rrY, X86::VFMSUBPD4rmY, TB_ALIGN_32 },
1412 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4rm, 0 },
1413 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4rm, 0 },
1414 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4rm, TB_ALIGN_16 },
1415 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4rm, TB_ALIGN_16 },
1416 { X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4rmY, TB_ALIGN_32 },
1417 { X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4rmY, TB_ALIGN_32 },
1418 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4rm, TB_ALIGN_16 },
1419 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4rm, TB_ALIGN_16 },
1420 { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4rmY, TB_ALIGN_32 },
1421 { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4rmY, TB_ALIGN_32 },
1422 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4rm, TB_ALIGN_16 },
1423 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4rm, TB_ALIGN_16 },
1424 { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4rmY, TB_ALIGN_32 },
1425 { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4rmY, TB_ALIGN_32 },
1426 // AVX-512 VPERMI instructions with 3 source operands.
1427 { X86::VPERMI2Drr, X86::VPERMI2Drm, 0 },
1428 { X86::VPERMI2Qrr, X86::VPERMI2Qrm, 0 },
1429 { X86::VPERMI2PSrr, X86::VPERMI2PSrm, 0 },
1430 { X86::VPERMI2PDrr, X86::VPERMI2PDrm, 0 },
1431 { X86::VBLENDMPDZrr, X86::VBLENDMPDZrm, 0 },
1432 { X86::VBLENDMPSZrr, X86::VBLENDMPSZrm, 0 },
1433 { X86::VPBLENDMDZrr, X86::VPBLENDMDZrm, 0 },
1434 { X86::VPBLENDMQZrr, X86::VPBLENDMQZrm, 0 }
1435 };
1437 for (unsigned i = 0, e = array_lengthof(OpTbl3); i != e; ++i) {
1438 unsigned RegOp = OpTbl3[i].RegOp;
1439 unsigned MemOp = OpTbl3[i].MemOp;
1440 unsigned Flags = OpTbl3[i].Flags;
1441 AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
1442 RegOp, MemOp,
1443 // Index 3, folded load
1444 Flags | TB_INDEX_3 | TB_FOLDED_LOAD);
1445 }
1447 }
1449 void
1450 X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
1451 MemOp2RegOpTableType &M2RTable,
1452 unsigned RegOp, unsigned MemOp, unsigned Flags) {
1453 if ((Flags & TB_NO_FORWARD) == 0) {
1454 assert(!R2MTable.count(RegOp) && "Duplicate entry!");
1455 R2MTable[RegOp] = std::make_pair(MemOp, Flags);
1456 }
1457 if ((Flags & TB_NO_REVERSE) == 0) {
1458 assert(!M2RTable.count(MemOp) &&
1459 "Duplicated entries in unfolding maps?");
1460 M2RTable[MemOp] = std::make_pair(RegOp, Flags);
1461 }
1462 }
1464 bool
1465 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
1466 unsigned &SrcReg, unsigned &DstReg,
1467 unsigned &SubIdx) const {
1468 switch (MI.getOpcode()) {
1469 default: break;
1470 case X86::MOVSX16rr8:
1471 case X86::MOVZX16rr8:
1472 case X86::MOVSX32rr8:
1473 case X86::MOVZX32rr8:
1474 case X86::MOVSX64rr8:
1475 if (!TM.getSubtarget<X86Subtarget>().is64Bit())
1476 // It's not always legal to reference the low 8-bit of the larger
1477 // register in 32-bit mode.
1478 return false;
1479 case X86::MOVSX32rr16:
1480 case X86::MOVZX32rr16:
1481 case X86::MOVSX64rr16:
1482 case X86::MOVSX64rr32: {
1483 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
1484 // Be conservative.
1485 return false;
1486 SrcReg = MI.getOperand(1).getReg();
1487 DstReg = MI.getOperand(0).getReg();
1488 switch (MI.getOpcode()) {
1489 default: llvm_unreachable("Unreachable!");
1490 case X86::MOVSX16rr8:
1491 case X86::MOVZX16rr8:
1492 case X86::MOVSX32rr8:
1493 case X86::MOVZX32rr8:
1494 case X86::MOVSX64rr8:
1495 SubIdx = X86::sub_8bit;
1496 break;
1497 case X86::MOVSX32rr16:
1498 case X86::MOVZX32rr16:
1499 case X86::MOVSX64rr16:
1500 SubIdx = X86::sub_16bit;
1501 break;
1502 case X86::MOVSX64rr32:
1503 SubIdx = X86::sub_32bit;
1504 break;
1505 }
1506 return true;
1507 }
1508 }
1509 return false;
1510 }
1512 /// isFrameOperand - Return true and the FrameIndex if the specified
1513 /// operand and follow operands form a reference to the stack frame.
1514 bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
1515 int &FrameIndex) const {
1516 if (MI->getOperand(Op).isFI() && MI->getOperand(Op+1).isImm() &&
1517 MI->getOperand(Op+2).isReg() && MI->getOperand(Op+3).isImm() &&
1518 MI->getOperand(Op+1).getImm() == 1 &&
1519 MI->getOperand(Op+2).getReg() == 0 &&
1520 MI->getOperand(Op+3).getImm() == 0) {
1521 FrameIndex = MI->getOperand(Op).getIndex();
1522 return true;
1523 }
1524 return false;
1525 }
1527 static bool isFrameLoadOpcode(int Opcode) {
1528 switch (Opcode) {
1529 default:
1530 return false;
1531 case X86::MOV8rm:
1532 case X86::MOV16rm:
1533 case X86::MOV32rm:
1534 case X86::MOV64rm:
1535 case X86::LD_Fp64m:
1536 case X86::MOVSSrm:
1537 case X86::MOVSDrm:
1538 case X86::MOVAPSrm:
1539 case X86::MOVAPDrm:
1540 case X86::MOVDQArm:
1541 case X86::VMOVSSrm:
1542 case X86::VMOVSDrm:
1543 case X86::VMOVAPSrm:
1544 case X86::VMOVAPDrm:
1545 case X86::VMOVDQArm:
1546 case X86::VMOVAPSYrm:
1547 case X86::VMOVAPDYrm:
1548 case X86::VMOVDQAYrm:
1549 case X86::MMX_MOVD64rm:
1550 case X86::MMX_MOVQ64rm:
1551 case X86::VMOVAPSZrm:
1552 case X86::VMOVUPSZrm:
1553 return true;
1554 }
1555 }
1557 static bool isFrameStoreOpcode(int Opcode) {
1558 switch (Opcode) {
1559 default: break;
1560 case X86::MOV8mr:
1561 case X86::MOV16mr:
1562 case X86::MOV32mr:
1563 case X86::MOV64mr:
1564 case X86::ST_FpP64m:
1565 case X86::MOVSSmr:
1566 case X86::MOVSDmr:
1567 case X86::MOVAPSmr:
1568 case X86::MOVAPDmr:
1569 case X86::MOVDQAmr:
1570 case X86::VMOVSSmr:
1571 case X86::VMOVSDmr:
1572 case X86::VMOVAPSmr:
1573 case X86::VMOVAPDmr:
1574 case X86::VMOVDQAmr:
1575 case X86::VMOVAPSYmr:
1576 case X86::VMOVAPDYmr:
1577 case X86::VMOVDQAYmr:
1578 case X86::VMOVUPSZmr:
1579 case X86::VMOVAPSZmr:
1580 case X86::MMX_MOVD64mr:
1581 case X86::MMX_MOVQ64mr:
1582 case X86::MMX_MOVNTQmr:
1583 return true;
1584 }
1585 return false;
1586 }
1588 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
1589 int &FrameIndex) const {
1590 if (isFrameLoadOpcode(MI->getOpcode()))
1591 if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
1592 return MI->getOperand(0).getReg();
1593 return 0;
1594 }
1596 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
1597 int &FrameIndex) const {
1598 if (isFrameLoadOpcode(MI->getOpcode())) {
1599 unsigned Reg;
1600 if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
1601 return Reg;
1602 // Check for post-frame index elimination operations
1603 const MachineMemOperand *Dummy;
1604 return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
1605 }
1606 return 0;
1607 }
1609 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
1610 int &FrameIndex) const {
1611 if (isFrameStoreOpcode(MI->getOpcode()))
1612 if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
1613 isFrameOperand(MI, 0, FrameIndex))
1614 return MI->getOperand(X86::AddrNumOperands).getReg();
1615 return 0;
1616 }
1618 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
1619 int &FrameIndex) const {
1620 if (isFrameStoreOpcode(MI->getOpcode())) {
1621 unsigned Reg;
1622 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
1623 return Reg;
1624 // Check for post-frame index elimination operations
1625 const MachineMemOperand *Dummy;
1626 return hasStoreToStackSlot(MI, Dummy, FrameIndex);
1627 }
1628 return 0;
1629 }
1631 /// regIsPICBase - Return true if register is PIC base (i.e.g defined by
1632 /// X86::MOVPC32r.
1633 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
1634 // Don't waste compile time scanning use-def chains of physregs.
1635 if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
1636 return false;
1637 bool isPICBase = false;
1638 for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
1639 E = MRI.def_instr_end(); I != E; ++I) {
1640 MachineInstr *DefMI = &*I;
1641 if (DefMI->getOpcode() != X86::MOVPC32r)
1642 return false;
1643 assert(!isPICBase && "More than one PIC base?");
1644 isPICBase = true;
1645 }
1646 return isPICBase;
1647 }
1649 bool
1650 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
1651 AliasAnalysis *AA) const {
1652 switch (MI->getOpcode()) {
1653 default: break;
1654 case X86::MOV8rm:
1655 case X86::MOV16rm:
1656 case X86::MOV32rm:
1657 case X86::MOV64rm:
1658 case X86::LD_Fp64m:
1659 case X86::MOVSSrm:
1660 case X86::MOVSDrm:
1661 case X86::MOVAPSrm:
1662 case X86::MOVUPSrm:
1663 case X86::MOVAPDrm:
1664 case X86::MOVDQArm:
1665 case X86::MOVDQUrm:
1666 case X86::VMOVSSrm:
1667 case X86::VMOVSDrm:
1668 case X86::VMOVAPSrm:
1669 case X86::VMOVUPSrm:
1670 case X86::VMOVAPDrm:
1671 case X86::VMOVDQArm:
1672 case X86::VMOVDQUrm:
1673 case X86::VMOVAPSYrm:
1674 case X86::VMOVUPSYrm:
1675 case X86::VMOVAPDYrm:
1676 case X86::VMOVDQAYrm:
1677 case X86::VMOVDQUYrm:
1678 case X86::MMX_MOVD64rm:
1679 case X86::MMX_MOVQ64rm:
1680 case X86::FsVMOVAPSrm:
1681 case X86::FsVMOVAPDrm:
1682 case X86::FsMOVAPSrm:
1683 case X86::FsMOVAPDrm: {
1684 // Loads from constant pools are trivially rematerializable.
1685 if (MI->getOperand(1).isReg() &&
1686 MI->getOperand(2).isImm() &&
1687 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
1688 MI->isInvariantLoad(AA)) {
1689 unsigned BaseReg = MI->getOperand(1).getReg();
1690 if (BaseReg == 0 || BaseReg == X86::RIP)
1691 return true;
1692 // Allow re-materialization of PIC load.
1693 if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal())
1694 return false;
1695 const MachineFunction &MF = *MI->getParent()->getParent();
1696 const MachineRegisterInfo &MRI = MF.getRegInfo();
1697 return regIsPICBase(BaseReg, MRI);
1698 }
1699 return false;
1700 }
1702 case X86::LEA32r:
1703 case X86::LEA64r: {
1704 if (MI->getOperand(2).isImm() &&
1705 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
1706 !MI->getOperand(4).isReg()) {
1707 // lea fi#, lea GV, etc. are all rematerializable.
1708 if (!MI->getOperand(1).isReg())
1709 return true;
1710 unsigned BaseReg = MI->getOperand(1).getReg();
1711 if (BaseReg == 0)
1712 return true;
1713 // Allow re-materialization of lea PICBase + x.
1714 const MachineFunction &MF = *MI->getParent()->getParent();
1715 const MachineRegisterInfo &MRI = MF.getRegInfo();
1716 return regIsPICBase(BaseReg, MRI);
1717 }
1718 return false;
1719 }
1720 }
1722 // All other instructions marked M_REMATERIALIZABLE are always trivially
1723 // rematerializable.
1724 return true;
1725 }
1727 /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that
1728 /// would clobber the EFLAGS condition register. Note the result may be
1729 /// conservative. If it cannot definitely determine the safety after visiting
1730 /// a few instructions in each direction it assumes it's not safe.
1731 static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
1732 MachineBasicBlock::iterator I) {
1733 MachineBasicBlock::iterator E = MBB.end();
1735 // For compile time consideration, if we are not able to determine the
1736 // safety after visiting 4 instructions in each direction, we will assume
1737 // it's not safe.
1738 MachineBasicBlock::iterator Iter = I;
1739 for (unsigned i = 0; Iter != E && i < 4; ++i) {
1740 bool SeenDef = false;
1741 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1742 MachineOperand &MO = Iter->getOperand(j);
1743 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
1744 SeenDef = true;
1745 if (!MO.isReg())
1746 continue;
1747 if (MO.getReg() == X86::EFLAGS) {
1748 if (MO.isUse())
1749 return false;
1750 SeenDef = true;
1751 }
1752 }
1754 if (SeenDef)
1755 // This instruction defines EFLAGS, no need to look any further.
1756 return true;
1757 ++Iter;
1758 // Skip over DBG_VALUE.
1759 while (Iter != E && Iter->isDebugValue())
1760 ++Iter;
1761 }
1763 // It is safe to clobber EFLAGS at the end of a block of no successor has it
1764 // live in.
1765 if (Iter == E) {
1766 for (MachineBasicBlock::succ_iterator SI = MBB.succ_begin(),
1767 SE = MBB.succ_end(); SI != SE; ++SI)
1768 if ((*SI)->isLiveIn(X86::EFLAGS))
1769 return false;
1770 return true;
1771 }
1773 MachineBasicBlock::iterator B = MBB.begin();
1774 Iter = I;
1775 for (unsigned i = 0; i < 4; ++i) {
1776 // If we make it to the beginning of the block, it's safe to clobber
1777 // EFLAGS iff EFLAGS is not live-in.
1778 if (Iter == B)
1779 return !MBB.isLiveIn(X86::EFLAGS);
1781 --Iter;
1782 // Skip over DBG_VALUE.
1783 while (Iter != B && Iter->isDebugValue())
1784 --Iter;
1786 bool SawKill = false;
1787 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1788 MachineOperand &MO = Iter->getOperand(j);
1789 // A register mask may clobber EFLAGS, but we should still look for a
1790 // live EFLAGS def.
1791 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
1792 SawKill = true;
1793 if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
1794 if (MO.isDef()) return MO.isDead();
1795 if (MO.isKill()) SawKill = true;
1796 }
1797 }
1799 if (SawKill)
1800 // This instruction kills EFLAGS and doesn't redefine it, so
1801 // there's no need to look further.
1802 return true;
1803 }
1805 // Conservative answer.
1806 return false;
1807 }
1809 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
1810 MachineBasicBlock::iterator I,
1811 unsigned DestReg, unsigned SubIdx,
1812 const MachineInstr *Orig,
1813 const TargetRegisterInfo &TRI) const {
1814 // MOV32r0 is implemented with a xor which clobbers condition code.
1815 // Re-materialize it as movri instructions to avoid side effects.
1816 unsigned Opc = Orig->getOpcode();
1817 if (Opc == X86::MOV32r0 && !isSafeToClobberEFLAGS(MBB, I)) {
1818 DebugLoc DL = Orig->getDebugLoc();
1819 BuildMI(MBB, I, DL, get(X86::MOV32ri)).addOperand(Orig->getOperand(0))
1820 .addImm(0);
1821 } else {
1822 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1823 MBB.insert(I, MI);
1824 }
1826 MachineInstr *NewMI = std::prev(I);
1827 NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1828 }
1830 /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
1831 /// is not marked dead.
1832 static bool hasLiveCondCodeDef(MachineInstr *MI) {
1833 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1834 MachineOperand &MO = MI->getOperand(i);
1835 if (MO.isReg() && MO.isDef() &&
1836 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1837 return true;
1838 }
1839 }
1840 return false;
1841 }
1843 /// getTruncatedShiftCount - check whether the shift count for a machine operand
1844 /// is non-zero.
1845 inline static unsigned getTruncatedShiftCount(MachineInstr *MI,
1846 unsigned ShiftAmtOperandIdx) {
1847 // The shift count is six bits with the REX.W prefix and five bits without.
1848 unsigned ShiftCountMask = (MI->getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
1849 unsigned Imm = MI->getOperand(ShiftAmtOperandIdx).getImm();
1850 return Imm & ShiftCountMask;
1851 }
1853 /// isTruncatedShiftCountForLEA - check whether the given shift count is appropriate
1854 /// can be represented by a LEA instruction.
1855 inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
1856 // Left shift instructions can be transformed into load-effective-address
1857 // instructions if we can encode them appropriately.
1858 // A LEA instruction utilizes a SIB byte to encode it's scale factor.
1859 // The SIB.scale field is two bits wide which means that we can encode any
1860 // shift amount less than 4.
1861 return ShAmt < 4 && ShAmt > 0;
1862 }
1864 bool X86InstrInfo::classifyLEAReg(MachineInstr *MI, const MachineOperand &Src,
1865 unsigned Opc, bool AllowSP,
1866 unsigned &NewSrc, bool &isKill, bool &isUndef,
1867 MachineOperand &ImplicitOp) const {
1868 MachineFunction &MF = *MI->getParent()->getParent();
1869 const TargetRegisterClass *RC;
1870 if (AllowSP) {
1871 RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
1872 } else {
1873 RC = Opc != X86::LEA32r ?
1874 &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
1875 }
1876 unsigned SrcReg = Src.getReg();
1878 // For both LEA64 and LEA32 the register already has essentially the right
1879 // type (32-bit or 64-bit) we may just need to forbid SP.
1880 if (Opc != X86::LEA64_32r) {
1881 NewSrc = SrcReg;
1882 isKill = Src.isKill();
1883 isUndef = Src.isUndef();
1885 if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
1886 !MF.getRegInfo().constrainRegClass(NewSrc, RC))
1887 return false;
1889 return true;
1890 }
1892 // This is for an LEA64_32r and incoming registers are 32-bit. One way or
1893 // another we need to add 64-bit registers to the final MI.
1894 if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
1895 ImplicitOp = Src;
1896 ImplicitOp.setImplicit();
1898 NewSrc = getX86SubSuperRegister(Src.getReg(), MVT::i64);
1899 MachineBasicBlock::LivenessQueryResult LQR =
1900 MI->getParent()->computeRegisterLiveness(&getRegisterInfo(), NewSrc, MI);
1902 switch (LQR) {
1903 case MachineBasicBlock::LQR_Unknown:
1904 // We can't give sane liveness flags to the instruction, abandon LEA
1905 // formation.
1906 return false;
1907 case MachineBasicBlock::LQR_Live:
1908 isKill = MI->killsRegister(SrcReg);
1909 isUndef = false;
1910 break;
1911 default:
1912 // The physreg itself is dead, so we have to use it as an <undef>.
1913 isKill = false;
1914 isUndef = true;
1915 break;
1916 }
1917 } else {
1918 // Virtual register of the wrong class, we have to create a temporary 64-bit
1919 // vreg to feed into the LEA.
1920 NewSrc = MF.getRegInfo().createVirtualRegister(RC);
1921 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
1922 get(TargetOpcode::COPY))
1923 .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
1924 .addOperand(Src);
1926 // Which is obviously going to be dead after we're done with it.
1927 isKill = true;
1928 isUndef = false;
1929 }
1931 // We've set all the parameters without issue.
1932 return true;
1933 }
1935 /// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when
1936 /// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting
1937 /// to a 32-bit superregister and then truncating back down to a 16-bit
1938 /// subregister.
1939 MachineInstr *
1940 X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
1941 MachineFunction::iterator &MFI,
1942 MachineBasicBlock::iterator &MBBI,
1943 LiveVariables *LV) const {
1944 MachineInstr *MI = MBBI;
1945 unsigned Dest = MI->getOperand(0).getReg();
1946 unsigned Src = MI->getOperand(1).getReg();
1947 bool isDead = MI->getOperand(0).isDead();
1948 bool isKill = MI->getOperand(1).isKill();
1950 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
1951 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1952 unsigned Opc, leaInReg;
1953 if (TM.getSubtarget<X86Subtarget>().is64Bit()) {
1954 Opc = X86::LEA64_32r;
1955 leaInReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
1956 } else {
1957 Opc = X86::LEA32r;
1958 leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1959 }
1961 // Build and insert into an implicit UNDEF value. This is OK because
1962 // well be shifting and then extracting the lower 16-bits.
1963 // This has the potential to cause partial register stall. e.g.
1964 // movw (%rbp,%rcx,2), %dx
1965 // leal -65(%rdx), %esi
1966 // But testing has shown this *does* help performance in 64-bit mode (at
1967 // least on modern x86 machines).
1968 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
1969 MachineInstr *InsMI =
1970 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
1971 .addReg(leaInReg, RegState::Define, X86::sub_16bit)
1972 .addReg(Src, getKillRegState(isKill));
1974 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
1975 get(Opc), leaOutReg);
1976 switch (MIOpc) {
1977 default: llvm_unreachable("Unreachable!");
1978 case X86::SHL16ri: {
1979 unsigned ShAmt = MI->getOperand(2).getImm();
1980 MIB.addReg(0).addImm(1 << ShAmt)
1981 .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
1982 break;
1983 }
1984 case X86::INC16r:
1985 case X86::INC64_16r:
1986 addRegOffset(MIB, leaInReg, true, 1);
1987 break;
1988 case X86::DEC16r:
1989 case X86::DEC64_16r:
1990 addRegOffset(MIB, leaInReg, true, -1);
1991 break;
1992 case X86::ADD16ri:
1993 case X86::ADD16ri8:
1994 case X86::ADD16ri_DB:
1995 case X86::ADD16ri8_DB:
1996 addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
1997 break;
1998 case X86::ADD16rr:
1999 case X86::ADD16rr_DB: {
2000 unsigned Src2 = MI->getOperand(2).getReg();
2001 bool isKill2 = MI->getOperand(2).isKill();
2002 unsigned leaInReg2 = 0;
2003 MachineInstr *InsMI2 = 0;
2004 if (Src == Src2) {
2005 // ADD16rr %reg1028<kill>, %reg1028
2006 // just a single insert_subreg.
2007 addRegReg(MIB, leaInReg, true, leaInReg, false);
2008 } else {
2009 if (TM.getSubtarget<X86Subtarget>().is64Bit())
2010 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2011 else
2012 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2013 // Build and insert into an implicit UNDEF value. This is OK because
2014 // well be shifting and then extracting the lower 16-bits.
2015 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2);
2016 InsMI2 =
2017 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
2018 .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
2019 .addReg(Src2, getKillRegState(isKill2));
2020 addRegReg(MIB, leaInReg, true, leaInReg2, true);
2021 }
2022 if (LV && isKill2 && InsMI2)
2023 LV->replaceKillInstruction(Src2, MI, InsMI2);
2024 break;
2025 }
2026 }
2028 MachineInstr *NewMI = MIB;
2029 MachineInstr *ExtMI =
2030 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
2031 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
2032 .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
2034 if (LV) {
2035 // Update live variables
2036 LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
2037 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
2038 if (isKill)
2039 LV->replaceKillInstruction(Src, MI, InsMI);
2040 if (isDead)
2041 LV->replaceKillInstruction(Dest, MI, ExtMI);
2042 }
2044 return ExtMI;
2045 }
2047 /// convertToThreeAddress - This method must be implemented by targets that
2048 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
2049 /// may be able to convert a two-address instruction into a true
2050 /// three-address instruction on demand. This allows the X86 target (for
2051 /// example) to convert ADD and SHL instructions into LEA instructions if they
2052 /// would require register copies due to two-addressness.
2053 ///
2054 /// This method returns a null pointer if the transformation cannot be
2055 /// performed, otherwise it returns the new instruction.
2056 ///
2057 MachineInstr *
2058 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
2059 MachineBasicBlock::iterator &MBBI,
2060 LiveVariables *LV) const {
2061 MachineInstr *MI = MBBI;
2063 // The following opcodes also sets the condition code register(s). Only
2064 // convert them to equivalent lea if the condition code register def's
2065 // are dead!
2066 if (hasLiveCondCodeDef(MI))
2067 return 0;
2069 MachineFunction &MF = *MI->getParent()->getParent();
2070 // All instructions input are two-addr instructions. Get the known operands.
2071 const MachineOperand &Dest = MI->getOperand(0);
2072 const MachineOperand &Src = MI->getOperand(1);
2074 MachineInstr *NewMI = NULL;
2075 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
2076 // we have better subtarget support, enable the 16-bit LEA generation here.
2077 // 16-bit LEA is also slow on Core2.
2078 bool DisableLEA16 = true;
2079 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
2081 unsigned MIOpc = MI->getOpcode();
2082 switch (MIOpc) {
2083 case X86::SHUFPSrri: {
2084 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
2085 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
2087 unsigned B = MI->getOperand(1).getReg();
2088 unsigned C = MI->getOperand(2).getReg();
2089 if (B != C) return 0;
2090 unsigned M = MI->getOperand(3).getImm();
2091 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
2092 .addOperand(Dest).addOperand(Src).addImm(M);
2093 break;
2094 }
2095 case X86::SHUFPDrri: {
2096 assert(MI->getNumOperands() == 4 && "Unknown shufpd instruction!");
2097 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
2099 unsigned B = MI->getOperand(1).getReg();
2100 unsigned C = MI->getOperand(2).getReg();
2101 if (B != C) return 0;
2102 unsigned M = MI->getOperand(3).getImm();
2104 // Convert to PSHUFD mask.
2105 M = ((M & 1) << 1) | ((M & 1) << 3) | ((M & 2) << 4) | ((M & 2) << 6)| 0x44;
2107 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
2108 .addOperand(Dest).addOperand(Src).addImm(M);
2109 break;
2110 }
2111 case X86::SHL64ri: {
2112 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2113 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2114 if (!isTruncatedShiftCountForLEA(ShAmt)) return 0;
2116 // LEA can't handle RSP.
2117 if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
2118 !MF.getRegInfo().constrainRegClass(Src.getReg(),
2119 &X86::GR64_NOSPRegClass))
2120 return 0;
2122 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2123 .addOperand(Dest)
2124 .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
2125 break;
2126 }
2127 case X86::SHL32ri: {
2128 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2129 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2130 if (!isTruncatedShiftCountForLEA(ShAmt)) return 0;
2132 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2134 // LEA can't handle ESP.
2135 bool isKill, isUndef;
2136 unsigned SrcReg;
2137 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2138 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2139 SrcReg, isKill, isUndef, ImplicitOp))
2140 return 0;
2142 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2143 .addOperand(Dest)
2144 .addReg(0).addImm(1 << ShAmt)
2145 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
2146 .addImm(0).addReg(0);
2147 if (ImplicitOp.getReg() != 0)
2148 MIB.addOperand(ImplicitOp);
2149 NewMI = MIB;
2151 break;
2152 }
2153 case X86::SHL16ri: {
2154 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2155 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2156 if (!isTruncatedShiftCountForLEA(ShAmt)) return 0;
2158 if (DisableLEA16)
2159 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
2160 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2161 .addOperand(Dest)
2162 .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
2163 break;
2164 }
2165 default: {
2167 switch (MIOpc) {
2168 default: return 0;
2169 case X86::INC64r:
2170 case X86::INC32r:
2171 case X86::INC64_32r: {
2172 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2173 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
2174 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2175 bool isKill, isUndef;
2176 unsigned SrcReg;
2177 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2178 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2179 SrcReg, isKill, isUndef, ImplicitOp))
2180 return 0;
2182 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2183 .addOperand(Dest)
2184 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef));
2185 if (ImplicitOp.getReg() != 0)
2186 MIB.addOperand(ImplicitOp);
2188 NewMI = addOffset(MIB, 1);
2189 break;
2190 }
2191 case X86::INC16r:
2192 case X86::INC64_16r:
2193 if (DisableLEA16)
2194 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
2195 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2196 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2197 .addOperand(Dest).addOperand(Src), 1);
2198 break;
2199 case X86::DEC64r:
2200 case X86::DEC32r:
2201 case X86::DEC64_32r: {
2202 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2203 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
2204 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2206 bool isKill, isUndef;
2207 unsigned SrcReg;
2208 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2209 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2210 SrcReg, isKill, isUndef, ImplicitOp))
2211 return 0;
2213 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2214 .addOperand(Dest)
2215 .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2216 if (ImplicitOp.getReg() != 0)
2217 MIB.addOperand(ImplicitOp);
2219 NewMI = addOffset(MIB, -1);
2221 break;
2222 }
2223 case X86::DEC16r:
2224 case X86::DEC64_16r:
2225 if (DisableLEA16)
2226 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
2227 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2228 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2229 .addOperand(Dest).addOperand(Src), -1);
2230 break;
2231 case X86::ADD64rr:
2232 case X86::ADD64rr_DB:
2233 case X86::ADD32rr:
2234 case X86::ADD32rr_DB: {
2235 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2236 unsigned Opc;
2237 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
2238 Opc = X86::LEA64r;
2239 else
2240 Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2242 bool isKill, isUndef;
2243 unsigned SrcReg;
2244 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2245 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2246 SrcReg, isKill, isUndef, ImplicitOp))
2247 return 0;
2249 const MachineOperand &Src2 = MI->getOperand(2);
2250 bool isKill2, isUndef2;
2251 unsigned SrcReg2;
2252 MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
2253 if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
2254 SrcReg2, isKill2, isUndef2, ImplicitOp2))
2255 return 0;
2257 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2258 .addOperand(Dest);
2259 if (ImplicitOp.getReg() != 0)
2260 MIB.addOperand(ImplicitOp);
2261 if (ImplicitOp2.getReg() != 0)
2262 MIB.addOperand(ImplicitOp2);
2264 NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
2266 // Preserve undefness of the operands.
2267 NewMI->getOperand(1).setIsUndef(isUndef);
2268 NewMI->getOperand(3).setIsUndef(isUndef2);
2270 if (LV && Src2.isKill())
2271 LV->replaceKillInstruction(SrcReg2, MI, NewMI);
2272 break;
2273 }
2274 case X86::ADD16rr:
2275 case X86::ADD16rr_DB: {
2276 if (DisableLEA16)
2277 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
2278 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2279 unsigned Src2 = MI->getOperand(2).getReg();
2280 bool isKill2 = MI->getOperand(2).isKill();
2281 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2282 .addOperand(Dest),
2283 Src.getReg(), Src.isKill(), Src2, isKill2);
2285 // Preserve undefness of the operands.
2286 bool isUndef = MI->getOperand(1).isUndef();
2287 bool isUndef2 = MI->getOperand(2).isUndef();
2288 NewMI->getOperand(1).setIsUndef(isUndef);
2289 NewMI->getOperand(3).setIsUndef(isUndef2);
2291 if (LV && isKill2)
2292 LV->replaceKillInstruction(Src2, MI, NewMI);
2293 break;
2294 }
2295 case X86::ADD64ri32:
2296 case X86::ADD64ri8:
2297 case X86::ADD64ri32_DB:
2298 case X86::ADD64ri8_DB:
2299 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2300 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2301 .addOperand(Dest).addOperand(Src),
2302 MI->getOperand(2).getImm());
2303 break;
2304 case X86::ADD32ri:
2305 case X86::ADD32ri8:
2306 case X86::ADD32ri_DB:
2307 case X86::ADD32ri8_DB: {
2308 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2309 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2311 bool isKill, isUndef;
2312 unsigned SrcReg;
2313 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2314 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2315 SrcReg, isKill, isUndef, ImplicitOp))
2316 return 0;
2318 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2319 .addOperand(Dest)
2320 .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2321 if (ImplicitOp.getReg() != 0)
2322 MIB.addOperand(ImplicitOp);
2324 NewMI = addOffset(MIB, MI->getOperand(2).getImm());
2325 break;
2326 }
2327 case X86::ADD16ri:
2328 case X86::ADD16ri8:
2329 case X86::ADD16ri_DB:
2330 case X86::ADD16ri8_DB:
2331 if (DisableLEA16)
2332 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
2333 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2334 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2335 .addOperand(Dest).addOperand(Src),
2336 MI->getOperand(2).getImm());
2337 break;
2338 }
2339 }
2340 }
2342 if (!NewMI) return 0;
2344 if (LV) { // Update live variables
2345 if (Src.isKill())
2346 LV->replaceKillInstruction(Src.getReg(), MI, NewMI);
2347 if (Dest.isDead())
2348 LV->replaceKillInstruction(Dest.getReg(), MI, NewMI);
2349 }
2351 MFI->insert(MBBI, NewMI); // Insert the new inst
2352 return NewMI;
2353 }
2355 /// commuteInstruction - We have a few instructions that must be hacked on to
2356 /// commute them.
2357 ///
2358 MachineInstr *
2359 X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
2360 switch (MI->getOpcode()) {
2361 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
2362 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
2363 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
2364 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
2365 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
2366 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
2367 unsigned Opc;
2368 unsigned Size;
2369 switch (MI->getOpcode()) {
2370 default: llvm_unreachable("Unreachable!");
2371 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
2372 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
2373 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
2374 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
2375 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
2376 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
2377 }
2378 unsigned Amt = MI->getOperand(3).getImm();
2379 if (NewMI) {
2380 MachineFunction &MF = *MI->getParent()->getParent();
2381 MI = MF.CloneMachineInstr(MI);
2382 NewMI = false;
2383 }
2384 MI->setDesc(get(Opc));
2385 MI->getOperand(3).setImm(Size-Amt);
2386 return TargetInstrInfo::commuteInstruction(MI, NewMI);
2387 }
2388 case X86::CMOVB16rr: case X86::CMOVB32rr: case X86::CMOVB64rr:
2389 case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
2390 case X86::CMOVE16rr: case X86::CMOVE32rr: case X86::CMOVE64rr:
2391 case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
2392 case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
2393 case X86::CMOVA16rr: case X86::CMOVA32rr: case X86::CMOVA64rr:
2394 case X86::CMOVL16rr: case X86::CMOVL32rr: case X86::CMOVL64rr:
2395 case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
2396 case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
2397 case X86::CMOVG16rr: case X86::CMOVG32rr: case X86::CMOVG64rr:
2398 case X86::CMOVS16rr: case X86::CMOVS32rr: case X86::CMOVS64rr:
2399 case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
2400 case X86::CMOVP16rr: case X86::CMOVP32rr: case X86::CMOVP64rr:
2401 case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
2402 case X86::CMOVO16rr: case X86::CMOVO32rr: case X86::CMOVO64rr:
2403 case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
2404 unsigned Opc;
2405 switch (MI->getOpcode()) {
2406 default: llvm_unreachable("Unreachable!");
2407 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
2408 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
2409 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
2410 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
2411 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
2412 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
2413 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
2414 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
2415 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
2416 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
2417 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
2418 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
2419 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
2420 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
2421 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
2422 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
2423 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
2424 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
2425 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
2426 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
2427 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
2428 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
2429 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
2430 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
2431 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
2432 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
2433 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
2434 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
2435 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
2436 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
2437 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
2438 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
2439 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break;
2440 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
2441 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
2442 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
2443 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
2444 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
2445 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break;
2446 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
2447 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
2448 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
2449 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
2450 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
2451 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break;
2452 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
2453 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
2454 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
2455 }
2456 if (NewMI) {
2457 MachineFunction &MF = *MI->getParent()->getParent();
2458 MI = MF.CloneMachineInstr(MI);
2459 NewMI = false;
2460 }
2461 MI->setDesc(get(Opc));
2462 // Fallthrough intended.
2463 }
2464 default:
2465 return TargetInstrInfo::commuteInstruction(MI, NewMI);
2466 }
2467 }
2469 bool X86InstrInfo::findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
2470 unsigned &SrcOpIdx2) const {
2471 switch (MI->getOpcode()) {
2472 case X86::VFMADDPDr231r:
2473 case X86::VFMADDPSr231r:
2474 case X86::VFMADDSDr231r:
2475 case X86::VFMADDSSr231r:
2476 case X86::VFMSUBPDr231r:
2477 case X86::VFMSUBPSr231r:
2478 case X86::VFMSUBSDr231r:
2479 case X86::VFMSUBSSr231r:
2480 case X86::VFNMADDPDr231r:
2481 case X86::VFNMADDPSr231r:
2482 case X86::VFNMADDSDr231r:
2483 case X86::VFNMADDSSr231r:
2484 case X86::VFNMSUBPDr231r:
2485 case X86::VFNMSUBPSr231r:
2486 case X86::VFNMSUBSDr231r:
2487 case X86::VFNMSUBSSr231r:
2488 case X86::VFMADDPDr231rY:
2489 case X86::VFMADDPSr231rY:
2490 case X86::VFMSUBPDr231rY:
2491 case X86::VFMSUBPSr231rY:
2492 case X86::VFNMADDPDr231rY:
2493 case X86::VFNMADDPSr231rY:
2494 case X86::VFNMSUBPDr231rY:
2495 case X86::VFNMSUBPSr231rY:
2496 SrcOpIdx1 = 2;
2497 SrcOpIdx2 = 3;
2498 return true;
2499 default:
2500 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2501 }
2502 }
2504 static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) {
2505 switch (BrOpc) {
2506 default: return X86::COND_INVALID;
2507 case X86::JE_4: return X86::COND_E;
2508 case X86::JNE_4: return X86::COND_NE;
2509 case X86::JL_4: return X86::COND_L;
2510 case X86::JLE_4: return X86::COND_LE;
2511 case X86::JG_4: return X86::COND_G;
2512 case X86::JGE_4: return X86::COND_GE;
2513 case X86::JB_4: return X86::COND_B;
2514 case X86::JBE_4: return X86::COND_BE;
2515 case X86::JA_4: return X86::COND_A;
2516 case X86::JAE_4: return X86::COND_AE;
2517 case X86::JS_4: return X86::COND_S;
2518 case X86::JNS_4: return X86::COND_NS;
2519 case X86::JP_4: return X86::COND_P;
2520 case X86::JNP_4: return X86::COND_NP;
2521 case X86::JO_4: return X86::COND_O;
2522 case X86::JNO_4: return X86::COND_NO;
2523 }
2524 }
2526 /// getCondFromSETOpc - return condition code of a SET opcode.
2527 static X86::CondCode getCondFromSETOpc(unsigned Opc) {
2528 switch (Opc) {
2529 default: return X86::COND_INVALID;
2530 case X86::SETAr: case X86::SETAm: return X86::COND_A;
2531 case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
2532 case X86::SETBr: case X86::SETBm: return X86::COND_B;
2533 case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
2534 case X86::SETEr: case X86::SETEm: return X86::COND_E;
2535 case X86::SETGr: case X86::SETGm: return X86::COND_G;
2536 case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
2537 case X86::SETLr: case X86::SETLm: return X86::COND_L;
2538 case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
2539 case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
2540 case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
2541 case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
2542 case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
2543 case X86::SETOr: case X86::SETOm: return X86::COND_O;
2544 case X86::SETPr: case X86::SETPm: return X86::COND_P;
2545 case X86::SETSr: case X86::SETSm: return X86::COND_S;
2546 }
2547 }
2549 /// getCondFromCmovOpc - return condition code of a CMov opcode.
2550 X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) {
2551 switch (Opc) {
2552 default: return X86::COND_INVALID;
2553 case X86::CMOVA16rm: case X86::CMOVA16rr: case X86::CMOVA32rm:
2554 case X86::CMOVA32rr: case X86::CMOVA64rm: case X86::CMOVA64rr:
2555 return X86::COND_A;
2556 case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
2557 case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
2558 return X86::COND_AE;
2559 case X86::CMOVB16rm: case X86::CMOVB16rr: case X86::CMOVB32rm:
2560 case X86::CMOVB32rr: case X86::CMOVB64rm: case X86::CMOVB64rr:
2561 return X86::COND_B;
2562 case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
2563 case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
2564 return X86::COND_BE;
2565 case X86::CMOVE16rm: case X86::CMOVE16rr: case X86::CMOVE32rm:
2566 case X86::CMOVE32rr: case X86::CMOVE64rm: case X86::CMOVE64rr:
2567 return X86::COND_E;
2568 case X86::CMOVG16rm: case X86::CMOVG16rr: case X86::CMOVG32rm:
2569 case X86::CMOVG32rr: case X86::CMOVG64rm: case X86::CMOVG64rr:
2570 return X86::COND_G;
2571 case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
2572 case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
2573 return X86::COND_GE;
2574 case X86::CMOVL16rm: case X86::CMOVL16rr: case X86::CMOVL32rm:
2575 case X86::CMOVL32rr: case X86::CMOVL64rm: case X86::CMOVL64rr:
2576 return X86::COND_L;
2577 case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
2578 case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
2579 return X86::COND_LE;
2580 case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
2581 case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
2582 return X86::COND_NE;
2583 case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
2584 case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
2585 return X86::COND_NO;
2586 case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
2587 case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
2588 return X86::COND_NP;
2589 case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
2590 case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
2591 return X86::COND_NS;
2592 case X86::CMOVO16rm: case X86::CMOVO16rr: case X86::CMOVO32rm:
2593 case X86::CMOVO32rr: case X86::CMOVO64rm: case X86::CMOVO64rr:
2594 return X86::COND_O;
2595 case X86::CMOVP16rm: case X86::CMOVP16rr: case X86::CMOVP32rm:
2596 case X86::CMOVP32rr: case X86::CMOVP64rm: case X86::CMOVP64rr:
2597 return X86::COND_P;
2598 case X86::CMOVS16rm: case X86::CMOVS16rr: case X86::CMOVS32rm:
2599 case X86::CMOVS32rr: case X86::CMOVS64rm: case X86::CMOVS64rr:
2600 return X86::COND_S;
2601 }
2602 }
2604 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
2605 switch (CC) {
2606 default: llvm_unreachable("Illegal condition code!");
2607 case X86::COND_E: return X86::JE_4;
2608 case X86::COND_NE: return X86::JNE_4;
2609 case X86::COND_L: return X86::JL_4;
2610 case X86::COND_LE: return X86::JLE_4;
2611 case X86::COND_G: return X86::JG_4;
2612 case X86::COND_GE: return X86::JGE_4;
2613 case X86::COND_B: return X86::JB_4;
2614 case X86::COND_BE: return X86::JBE_4;
2615 case X86::COND_A: return X86::JA_4;
2616 case X86::COND_AE: return X86::JAE_4;
2617 case X86::COND_S: return X86::JS_4;
2618 case X86::COND_NS: return X86::JNS_4;
2619 case X86::COND_P: return X86::JP_4;
2620 case X86::COND_NP: return X86::JNP_4;
2621 case X86::COND_O: return X86::JO_4;
2622 case X86::COND_NO: return X86::JNO_4;
2623 }
2624 }
2626 /// GetOppositeBranchCondition - Return the inverse of the specified condition,
2627 /// e.g. turning COND_E to COND_NE.
2628 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
2629 switch (CC) {
2630 default: llvm_unreachable("Illegal condition code!");
2631 case X86::COND_E: return X86::COND_NE;
2632 case X86::COND_NE: return X86::COND_E;
2633 case X86::COND_L: return X86::COND_GE;
2634 case X86::COND_LE: return X86::COND_G;
2635 case X86::COND_G: return X86::COND_LE;
2636 case X86::COND_GE: return X86::COND_L;
2637 case X86::COND_B: return X86::COND_AE;
2638 case X86::COND_BE: return X86::COND_A;
2639 case X86::COND_A: return X86::COND_BE;
2640 case X86::COND_AE: return X86::COND_B;
2641 case X86::COND_S: return X86::COND_NS;
2642 case X86::COND_NS: return X86::COND_S;
2643 case X86::COND_P: return X86::COND_NP;
2644 case X86::COND_NP: return X86::COND_P;
2645 case X86::COND_O: return X86::COND_NO;
2646 case X86::COND_NO: return X86::COND_O;
2647 }
2648 }
2650 /// getSwappedCondition - assume the flags are set by MI(a,b), return
2651 /// the condition code if we modify the instructions such that flags are
2652 /// set by MI(b,a).
2653 static X86::CondCode getSwappedCondition(X86::CondCode CC) {
2654 switch (CC) {
2655 default: return X86::COND_INVALID;
2656 case X86::COND_E: return X86::COND_E;
2657 case X86::COND_NE: return X86::COND_NE;
2658 case X86::COND_L: return X86::COND_G;
2659 case X86::COND_LE: return X86::COND_GE;
2660 case X86::COND_G: return X86::COND_L;
2661 case X86::COND_GE: return X86::COND_LE;
2662 case X86::COND_B: return X86::COND_A;
2663 case X86::COND_BE: return X86::COND_AE;
2664 case X86::COND_A: return X86::COND_B;
2665 case X86::COND_AE: return X86::COND_BE;
2666 }
2667 }
2669 /// getSETFromCond - Return a set opcode for the given condition and
2670 /// whether it has memory operand.
2671 static unsigned getSETFromCond(X86::CondCode CC,
2672 bool HasMemoryOperand) {
2673 static const uint16_t Opc[16][2] = {
2674 { X86::SETAr, X86::SETAm },
2675 { X86::SETAEr, X86::SETAEm },
2676 { X86::SETBr, X86::SETBm },
2677 { X86::SETBEr, X86::SETBEm },
2678 { X86::SETEr, X86::SETEm },
2679 { X86::SETGr, X86::SETGm },
2680 { X86::SETGEr, X86::SETGEm },
2681 { X86::SETLr, X86::SETLm },
2682 { X86::SETLEr, X86::SETLEm },
2683 { X86::SETNEr, X86::SETNEm },
2684 { X86::SETNOr, X86::SETNOm },
2685 { X86::SETNPr, X86::SETNPm },
2686 { X86::SETNSr, X86::SETNSm },
2687 { X86::SETOr, X86::SETOm },
2688 { X86::SETPr, X86::SETPm },
2689 { X86::SETSr, X86::SETSm }
2690 };
2692 assert(CC < 16 && "Can only handle standard cond codes");
2693 return Opc[CC][HasMemoryOperand ? 1 : 0];
2694 }
2696 /// getCMovFromCond - Return a cmov opcode for the given condition,
2697 /// register size in bytes, and operand type.
2698 static unsigned getCMovFromCond(X86::CondCode CC, unsigned RegBytes,
2699 bool HasMemoryOperand) {
2700 static const uint16_t Opc[32][3] = {
2701 { X86::CMOVA16rr, X86::CMOVA32rr, X86::CMOVA64rr },
2702 { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
2703 { X86::CMOVB16rr, X86::CMOVB32rr, X86::CMOVB64rr },
2704 { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
2705 { X86::CMOVE16rr, X86::CMOVE32rr, X86::CMOVE64rr },
2706 { X86::CMOVG16rr, X86::CMOVG32rr, X86::CMOVG64rr },
2707 { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
2708 { X86::CMOVL16rr, X86::CMOVL32rr, X86::CMOVL64rr },
2709 { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
2710 { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
2711 { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
2712 { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
2713 { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
2714 { X86::CMOVO16rr, X86::CMOVO32rr, X86::CMOVO64rr },
2715 { X86::CMOVP16rr, X86::CMOVP32rr, X86::CMOVP64rr },
2716 { X86::CMOVS16rr, X86::CMOVS32rr, X86::CMOVS64rr },
2717 { X86::CMOVA16rm, X86::CMOVA32rm, X86::CMOVA64rm },
2718 { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
2719 { X86::CMOVB16rm, X86::CMOVB32rm, X86::CMOVB64rm },
2720 { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
2721 { X86::CMOVE16rm, X86::CMOVE32rm, X86::CMOVE64rm },
2722 { X86::CMOVG16rm, X86::CMOVG32rm, X86::CMOVG64rm },
2723 { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
2724 { X86::CMOVL16rm, X86::CMOVL32rm, X86::CMOVL64rm },
2725 { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
2726 { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
2727 { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
2728 { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
2729 { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
2730 { X86::CMOVO16rm, X86::CMOVO32rm, X86::CMOVO64rm },
2731 { X86::CMOVP16rm, X86::CMOVP32rm, X86::CMOVP64rm },
2732 { X86::CMOVS16rm, X86::CMOVS32rm, X86::CMOVS64rm }
2733 };
2735 assert(CC < 16 && "Can only handle standard cond codes");
2736 unsigned Idx = HasMemoryOperand ? 16+CC : CC;
2737 switch(RegBytes) {
2738 default: llvm_unreachable("Illegal register size!");
2739 case 2: return Opc[Idx][0];
2740 case 4: return Opc[Idx][1];
2741 case 8: return Opc[Idx][2];
2742 }
2743 }
2745 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
2746 if (!MI->isTerminator()) return false;
2748 // Conditional branch is a special case.
2749 if (MI->isBranch() && !MI->isBarrier())
2750 return true;
2751 if (!MI->isPredicable())
2752 return true;
2753 return !isPredicated(MI);
2754 }
2756 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
2757 MachineBasicBlock *&TBB,
2758 MachineBasicBlock *&FBB,
2759 SmallVectorImpl<MachineOperand> &Cond,
2760 bool AllowModify) const {
2761 // Start from the bottom of the block and work up, examining the
2762 // terminator instructions.
2763 MachineBasicBlock::iterator I = MBB.end();
2764 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
2765 while (I != MBB.begin()) {
2766 --I;
2767 if (I->isDebugValue())
2768 continue;
2770 // Working from the bottom, when we see a non-terminator instruction, we're
2771 // done.
2772 if (!isUnpredicatedTerminator(I))
2773 break;
2775 // A terminator that isn't a branch can't easily be handled by this
2776 // analysis.
2777 if (!I->isBranch())
2778 return true;
2780 // Handle unconditional branches.
2781 if (I->getOpcode() == X86::JMP_4) {
2782 UnCondBrIter = I;
2784 if (!AllowModify) {
2785 TBB = I->getOperand(0).getMBB();
2786 continue;
2787 }
2789 // If the block has any instructions after a JMP, delete them.
2790 while (std::next(I) != MBB.end())
2791 std::next(I)->eraseFromParent();
2793 Cond.clear();
2794 FBB = 0;
2796 // Delete the JMP if it's equivalent to a fall-through.
2797 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
2798 TBB = 0;
2799 I->eraseFromParent();
2800 I = MBB.end();
2801 UnCondBrIter = MBB.end();
2802 continue;
2803 }
2805 // TBB is used to indicate the unconditional destination.
2806 TBB = I->getOperand(0).getMBB();
2807 continue;
2808 }
2810 // Handle conditional branches.
2811 X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode());
2812 if (BranchCode == X86::COND_INVALID)
2813 return true; // Can't handle indirect branch.
2815 // Working from the bottom, handle the first conditional branch.
2816 if (Cond.empty()) {
2817 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
2818 if (AllowModify && UnCondBrIter != MBB.end() &&
2819 MBB.isLayoutSuccessor(TargetBB)) {
2820 // If we can modify the code and it ends in something like:
2821 //
2822 // jCC L1
2823 // jmp L2
2824 // L1:
2825 // ...
2826 // L2:
2827 //
2828 // Then we can change this to:
2829 //
2830 // jnCC L2
2831 // L1:
2832 // ...
2833 // L2:
2834 //
2835 // Which is a bit more efficient.
2836 // We conditionally jump to the fall-through block.
2837 BranchCode = GetOppositeBranchCondition(BranchCode);
2838 unsigned JNCC = GetCondBranchFromCond(BranchCode);
2839 MachineBasicBlock::iterator OldInst = I;
2841 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
2842 .addMBB(UnCondBrIter->getOperand(0).getMBB());
2843 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_4))
2844 .addMBB(TargetBB);
2846 OldInst->eraseFromParent();
2847 UnCondBrIter->eraseFromParent();
2849 // Restart the analysis.
2850 UnCondBrIter = MBB.end();
2851 I = MBB.end();
2852 continue;
2853 }
2855 FBB = TBB;
2856 TBB = I->getOperand(0).getMBB();
2857 Cond.push_back(MachineOperand::CreateImm(BranchCode));
2858 continue;
2859 }
2861 // Handle subsequent conditional branches. Only handle the case where all
2862 // conditional branches branch to the same destination and their condition
2863 // opcodes fit one of the special multi-branch idioms.
2864 assert(Cond.size() == 1);
2865 assert(TBB);
2867 // Only handle the case where all conditional branches branch to the same
2868 // destination.
2869 if (TBB != I->getOperand(0).getMBB())
2870 return true;
2872 // If the conditions are the same, we can leave them alone.
2873 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
2874 if (OldBranchCode == BranchCode)
2875 continue;
2877 // If they differ, see if they fit one of the known patterns. Theoretically,
2878 // we could handle more patterns here, but we shouldn't expect to see them
2879 // if instruction selection has done a reasonable job.
2880 if ((OldBranchCode == X86::COND_NP &&
2881 BranchCode == X86::COND_E) ||
2882 (OldBranchCode == X86::COND_E &&
2883 BranchCode == X86::COND_NP))
2884 BranchCode = X86::COND_NP_OR_E;
2885 else if ((OldBranchCode == X86::COND_P &&
2886 BranchCode == X86::COND_NE) ||
2887 (OldBranchCode == X86::COND_NE &&
2888 BranchCode == X86::COND_P))
2889 BranchCode = X86::COND_NE_OR_P;
2890 else
2891 return true;
2893 // Update the MachineOperand.
2894 Cond[0].setImm(BranchCode);
2895 }
2897 return false;
2898 }
2900 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
2901 MachineBasicBlock::iterator I = MBB.end();
2902 unsigned Count = 0;
2904 while (I != MBB.begin()) {
2905 --I;
2906 if (I->isDebugValue())
2907 continue;
2908 if (I->getOpcode() != X86::JMP_4 &&
2909 getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
2910 break;
2911 // Remove the branch.
2912 I->eraseFromParent();
2913 I = MBB.end();
2914 ++Count;
2915 }
2917 return Count;
2918 }
2920 unsigned
2921 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
2922 MachineBasicBlock *FBB,
2923 const SmallVectorImpl<MachineOperand> &Cond,
2924 DebugLoc DL) const {
2925 // Shouldn't be a fall through.
2926 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
2927 assert((Cond.size() == 1 || Cond.size() == 0) &&
2928 "X86 branch conditions have one component!");
2930 if (Cond.empty()) {
2931 // Unconditional branch?
2932 assert(!FBB && "Unconditional branch with multiple successors!");
2933 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(TBB);
2934 return 1;
2935 }
2937 // Conditional branch.
2938 unsigned Count = 0;
2939 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
2940 switch (CC) {
2941 case X86::COND_NP_OR_E:
2942 // Synthesize NP_OR_E with two branches.
2943 BuildMI(&MBB, DL, get(X86::JNP_4)).addMBB(TBB);
2944 ++Count;
2945 BuildMI(&MBB, DL, get(X86::JE_4)).addMBB(TBB);
2946 ++Count;
2947 break;
2948 case X86::COND_NE_OR_P:
2949 // Synthesize NE_OR_P with two branches.
2950 BuildMI(&MBB, DL, get(X86::JNE_4)).addMBB(TBB);
2951 ++Count;
2952 BuildMI(&MBB, DL, get(X86::JP_4)).addMBB(TBB);
2953 ++Count;
2954 break;
2955 default: {
2956 unsigned Opc = GetCondBranchFromCond(CC);
2957 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
2958 ++Count;
2959 }
2960 }
2961 if (FBB) {
2962 // Two-way Conditional branch. Insert the second branch.
2963 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(FBB);
2964 ++Count;
2965 }
2966 return Count;
2967 }
2969 bool X86InstrInfo::
2970 canInsertSelect(const MachineBasicBlock &MBB,
2971 const SmallVectorImpl<MachineOperand> &Cond,
2972 unsigned TrueReg, unsigned FalseReg,
2973 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
2974 // Not all subtargets have cmov instructions.
2975 if (!TM.getSubtarget<X86Subtarget>().hasCMov())
2976 return false;
2977 if (Cond.size() != 1)
2978 return false;
2979 // We cannot do the composite conditions, at least not in SSA form.
2980 if ((X86::CondCode)Cond[0].getImm() > X86::COND_S)
2981 return false;
2983 // Check register classes.
2984 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2985 const TargetRegisterClass *RC =
2986 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
2987 if (!RC)
2988 return false;
2990 // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
2991 if (X86::GR16RegClass.hasSubClassEq(RC) ||
2992 X86::GR32RegClass.hasSubClassEq(RC) ||
2993 X86::GR64RegClass.hasSubClassEq(RC)) {
2994 // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
2995 // Bridge. Probably Ivy Bridge as well.
2996 CondCycles = 2;
2997 TrueCycles = 2;
2998 FalseCycles = 2;
2999 return true;
3000 }
3002 // Can't do vectors.
3003 return false;
3004 }
3006 void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
3007 MachineBasicBlock::iterator I, DebugLoc DL,
3008 unsigned DstReg,
3009 const SmallVectorImpl<MachineOperand> &Cond,
3010 unsigned TrueReg, unsigned FalseReg) const {
3011 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3012 assert(Cond.size() == 1 && "Invalid Cond array");
3013 unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
3014 MRI.getRegClass(DstReg)->getSize(),
3015 false/*HasMemoryOperand*/);
3016 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
3017 }
3019 /// isHReg - Test if the given register is a physical h register.
3020 static bool isHReg(unsigned Reg) {
3021 return X86::GR8_ABCD_HRegClass.contains(Reg);
3022 }
3024 // Try and copy between VR128/VR64 and GR64 registers.
3025 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
3026 const X86Subtarget& Subtarget) {
3029 // SrcReg(VR128) -> DestReg(GR64)
3030 // SrcReg(VR64) -> DestReg(GR64)
3031 // SrcReg(GR64) -> DestReg(VR128)
3032 // SrcReg(GR64) -> DestReg(VR64)
3034 bool HasAVX = Subtarget.hasAVX();
3035 bool HasAVX512 = Subtarget.hasAVX512();
3036 if (X86::GR64RegClass.contains(DestReg)) {
3037 if (X86::VR128XRegClass.contains(SrcReg))
3038 // Copy from a VR128 register to a GR64 register.
3039 return HasAVX512 ? X86::VMOVPQIto64Zrr: (HasAVX ? X86::VMOVPQIto64rr :
3040 X86::MOVPQIto64rr);
3041 if (X86::VR64RegClass.contains(SrcReg))
3042 // Copy from a VR64 register to a GR64 register.
3043 return X86::MOVSDto64rr;
3044 } else if (X86::GR64RegClass.contains(SrcReg)) {
3045 // Copy from a GR64 register to a VR128 register.
3046 if (X86::VR128XRegClass.contains(DestReg))
3047 return HasAVX512 ? X86::VMOV64toPQIZrr: (HasAVX ? X86::VMOV64toPQIrr :
3048 X86::MOV64toPQIrr);
3049 // Copy from a GR64 register to a VR64 register.
3050 if (X86::VR64RegClass.contains(DestReg))
3051 return X86::MOV64toSDrr;
3052 }
3054 // SrcReg(FR32) -> DestReg(GR32)
3055 // SrcReg(GR32) -> DestReg(FR32)
3057 if (X86::GR32RegClass.contains(DestReg) && X86::FR32XRegClass.contains(SrcReg))
3058 // Copy from a FR32 register to a GR32 register.
3059 return HasAVX512 ? X86::VMOVSS2DIZrr : (HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr);
3061 if (X86::FR32XRegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg))
3062 // Copy from a GR32 register to a FR32 register.
3063 return HasAVX512 ? X86::VMOVDI2SSZrr : (HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr);
3064 return 0;
3065 }
3067 inline static bool MaskRegClassContains(unsigned Reg) {
3068 return X86::VK8RegClass.contains(Reg) ||
3069 X86::VK16RegClass.contains(Reg) ||
3070 X86::VK1RegClass.contains(Reg);
3071 }
3072 static
3073 unsigned copyPhysRegOpcode_AVX512(unsigned& DestReg, unsigned& SrcReg) {
3074 if (X86::VR128XRegClass.contains(DestReg, SrcReg) ||
3075 X86::VR256XRegClass.contains(DestReg, SrcReg) ||
3076 X86::VR512RegClass.contains(DestReg, SrcReg)) {
3077 DestReg = get512BitSuperRegister(DestReg);
3078 SrcReg = get512BitSuperRegister(SrcReg);
3079 return X86::VMOVAPSZrr;
3080 }
3081 if (MaskRegClassContains(DestReg) &&
3082 MaskRegClassContains(SrcReg))
3083 return X86::KMOVWkk;
3084 if (MaskRegClassContains(DestReg) &&
3085 (X86::GR32RegClass.contains(SrcReg) ||
3086 X86::GR16RegClass.contains(SrcReg) ||
3087 X86::GR8RegClass.contains(SrcReg))) {
3088 SrcReg = getX86SubSuperRegister(SrcReg, MVT::i32);
3089 return X86::KMOVWkr;
3090 }
3091 if ((X86::GR32RegClass.contains(DestReg) ||
3092 X86::GR16RegClass.contains(DestReg) ||
3093 X86::GR8RegClass.contains(DestReg)) &&
3094 MaskRegClassContains(SrcReg)) {
3095 DestReg = getX86SubSuperRegister(DestReg, MVT::i32);
3096 return X86::KMOVWrk;
3097 }
3098 return 0;
3099 }
3101 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
3102 MachineBasicBlock::iterator MI, DebugLoc DL,
3103 unsigned DestReg, unsigned SrcReg,
3104 bool KillSrc) const {
3105 // First deal with the normal symmetric copies.
3106 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
3107 bool HasAVX512 = TM.getSubtarget<X86Subtarget>().hasAVX512();
3108 unsigned Opc = 0;
3109 if (X86::GR64RegClass.contains(DestReg, SrcReg))
3110 Opc = X86::MOV64rr;
3111 else if (X86::GR32RegClass.contains(DestReg, SrcReg))
3112 Opc = X86::MOV32rr;
3113 else if (X86::GR16RegClass.contains(DestReg, SrcReg))
3114 Opc = X86::MOV16rr;
3115 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
3116 // Copying to or from a physical H register on x86-64 requires a NOREX
3117 // move. Otherwise use a normal move.
3118 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
3119 TM.getSubtarget<X86Subtarget>().is64Bit()) {
3120 Opc = X86::MOV8rr_NOREX;
3121 // Both operands must be encodable without an REX prefix.
3122 assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
3123 "8-bit H register can not be copied outside GR8_NOREX");
3124 } else
3125 Opc = X86::MOV8rr;
3126 }
3127 else if (X86::VR64RegClass.contains(DestReg, SrcReg))
3128 Opc = X86::MMX_MOVQ64rr;
3129 else if (HasAVX512)
3130 Opc = copyPhysRegOpcode_AVX512(DestReg, SrcReg);
3131 else if (X86::VR128RegClass.contains(DestReg, SrcReg))
3132 Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
3133 else if (X86::VR256RegClass.contains(DestReg, SrcReg))
3134 Opc = X86::VMOVAPSYrr;
3135 if (!Opc)
3136 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, TM.getSubtarget<X86Subtarget>());
3138 if (Opc) {
3139 BuildMI(MBB, MI, DL, get(Opc), DestReg)
3140 .addReg(SrcReg, getKillRegState(KillSrc));
3141 return;
3142 }
3144 // Moving EFLAGS to / from another register requires a push and a pop.
3145 // Notice that we have to adjust the stack if we don't want to clobber the
3146 // first frame index. See X86FrameLowering.cpp - colobbersTheStack.
3147 if (SrcReg == X86::EFLAGS) {
3148 if (X86::GR64RegClass.contains(DestReg)) {
3149 BuildMI(MBB, MI, DL, get(X86::PUSHF64));
3150 BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
3151 return;
3152 }
3153 if (X86::GR32RegClass.contains(DestReg)) {
3154 BuildMI(MBB, MI, DL, get(X86::PUSHF32));
3155 BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
3156 return;
3157 }
3158 }
3159 if (DestReg == X86::EFLAGS) {
3160 if (X86::GR64RegClass.contains(SrcReg)) {
3161 BuildMI(MBB, MI, DL, get(X86::PUSH64r))
3162 .addReg(SrcReg, getKillRegState(KillSrc));
3163 BuildMI(MBB, MI, DL, get(X86::POPF64));
3164 return;
3165 }
3166 if (X86::GR32RegClass.contains(SrcReg)) {
3167 BuildMI(MBB, MI, DL, get(X86::PUSH32r))
3168 .addReg(SrcReg, getKillRegState(KillSrc));
3169 BuildMI(MBB, MI, DL, get(X86::POPF32));
3170 return;
3171 }
3172 }
3174 DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
3175 << " to " << RI.getName(DestReg) << '\n');
3176 llvm_unreachable("Cannot emit physreg copy instruction");
3177 }
3179 static unsigned getLoadStoreRegOpcode(unsigned Reg,
3180 const TargetRegisterClass *RC,
3181 bool isStackAligned,
3182 const TargetMachine &TM,
3183 bool load) {
3184 if (TM.getSubtarget<X86Subtarget>().hasAVX512()) {
3185 if (X86::VK8RegClass.hasSubClassEq(RC) ||
3186 X86::VK16RegClass.hasSubClassEq(RC))
3187 return load ? X86::KMOVWkm : X86::KMOVWmk;
3188 if (RC->getSize() == 4 && X86::FR32XRegClass.hasSubClassEq(RC))
3189 return load ? X86::VMOVSSZrm : X86::VMOVSSZmr;
3190 if (RC->getSize() == 8 && X86::FR64XRegClass.hasSubClassEq(RC))
3191 return load ? X86::VMOVSDZrm : X86::VMOVSDZmr;
3192 if (X86::VR512RegClass.hasSubClassEq(RC))
3193 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3194 }
3196 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
3197 switch (RC->getSize()) {
3198 default:
3199 llvm_unreachable("Unknown spill size");
3200 case 1:
3201 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
3202 if (TM.getSubtarget<X86Subtarget>().is64Bit())
3203 // Copying to or from a physical H register on x86-64 requires a NOREX
3204 // move. Otherwise use a normal move.
3205 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
3206 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
3207 return load ? X86::MOV8rm : X86::MOV8mr;
3208 case 2:
3209 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
3210 return load ? X86::MOV16rm : X86::MOV16mr;
3211 case 4:
3212 if (X86::GR32RegClass.hasSubClassEq(RC))
3213 return load ? X86::MOV32rm : X86::MOV32mr;
3214 if (X86::FR32RegClass.hasSubClassEq(RC))
3215 return load ?
3216 (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
3217 (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
3218 if (X86::RFP32RegClass.hasSubClassEq(RC))
3219 return load ? X86::LD_Fp32m : X86::ST_Fp32m;
3220 llvm_unreachable("Unknown 4-byte regclass");
3221 case 8:
3222 if (X86::GR64RegClass.hasSubClassEq(RC))
3223 return load ? X86::MOV64rm : X86::MOV64mr;
3224 if (X86::FR64RegClass.hasSubClassEq(RC))
3225 return load ?
3226 (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
3227 (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
3228 if (X86::VR64RegClass.hasSubClassEq(RC))
3229 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
3230 if (X86::RFP64RegClass.hasSubClassEq(RC))
3231 return load ? X86::LD_Fp64m : X86::ST_Fp64m;
3232 llvm_unreachable("Unknown 8-byte regclass");
3233 case 10:
3234 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
3235 return load ? X86::LD_Fp80m : X86::ST_FpP80m;
3236 case 16: {
3237 assert((X86::VR128RegClass.hasSubClassEq(RC) ||
3238 X86::VR128XRegClass.hasSubClassEq(RC))&& "Unknown 16-byte regclass");
3239 // If stack is realigned we can use aligned stores.
3240 if (isStackAligned)
3241 return load ?
3242 (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) :
3243 (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
3244 else
3245 return load ?
3246 (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) :
3247 (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
3248 }
3249 case 32:
3250 assert((X86::VR256RegClass.hasSubClassEq(RC) ||
3251 X86::VR256XRegClass.hasSubClassEq(RC)) && "Unknown 32-byte regclass");
3252 // If stack is realigned we can use aligned stores.
3253 if (isStackAligned)
3254 return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr;
3255 else
3256 return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr;
3257 case 64:
3258 assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
3259 if (isStackAligned)
3260 return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
3261 else
3262 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3263 }
3264 }
3266 static unsigned getStoreRegOpcode(unsigned SrcReg,
3267 const TargetRegisterClass *RC,
3268 bool isStackAligned,
3269 TargetMachine &TM) {
3270 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, TM, false);
3271 }
3274 static unsigned getLoadRegOpcode(unsigned DestReg,
3275 const TargetRegisterClass *RC,
3276 bool isStackAligned,
3277 const TargetMachine &TM) {
3278 return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, TM, true);
3279 }
3281 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
3282 MachineBasicBlock::iterator MI,
3283 unsigned SrcReg, bool isKill, int FrameIdx,
3284 const TargetRegisterClass *RC,
3285 const TargetRegisterInfo *TRI) const {
3286 const MachineFunction &MF = *MBB.getParent();
3287 assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() &&
3288 "Stack slot too small for store");
3289 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
3290 bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= Alignment) ||
3291 RI.canRealignStack(MF);
3292 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
3293 DebugLoc DL = MBB.findDebugLoc(MI);
3294 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
3295 .addReg(SrcReg, getKillRegState(isKill));
3296 }
3298 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
3299 bool isKill,
3300 SmallVectorImpl<MachineOperand> &Addr,
3301 const TargetRegisterClass *RC,
3302 MachineInstr::mmo_iterator MMOBegin,
3303 MachineInstr::mmo_iterator MMOEnd,
3304 SmallVectorImpl<MachineInstr*> &NewMIs) const {
3305 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
3306 bool isAligned = MMOBegin != MMOEnd &&
3307 (*MMOBegin)->getAlignment() >= Alignment;
3308 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
3309 DebugLoc DL;
3310 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
3311 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
3312 MIB.addOperand(Addr[i]);
3313 MIB.addReg(SrcReg, getKillRegState(isKill));
3314 (*MIB).setMemRefs(MMOBegin, MMOEnd);
3315 NewMIs.push_back(MIB);
3316 }
3319 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
3320 MachineBasicBlock::iterator MI,
3321 unsigned DestReg, int FrameIdx,
3322 const TargetRegisterClass *RC,
3323 const TargetRegisterInfo *TRI) const {
3324 const MachineFunction &MF = *MBB.getParent();
3325 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
3326 bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= Alignment) ||
3327 RI.canRealignStack(MF);
3328 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
3329 DebugLoc DL = MBB.findDebugLoc(MI);
3330 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
3331 }
3333 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
3334 SmallVectorImpl<MachineOperand> &Addr,
3335 const TargetRegisterClass *RC,
3336 MachineInstr::mmo_iterator MMOBegin,
3337 MachineInstr::mmo_iterator MMOEnd,
3338 SmallVectorImpl<MachineInstr*> &NewMIs) const {
3339 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
3340 bool isAligned = MMOBegin != MMOEnd &&
3341 (*MMOBegin)->getAlignment() >= Alignment;
3342 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
3343 DebugLoc DL;
3344 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
3345 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
3346 MIB.addOperand(Addr[i]);
3347 (*MIB).setMemRefs(MMOBegin, MMOEnd);
3348 NewMIs.push_back(MIB);
3349 }
3351 bool X86InstrInfo::
3352 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
3353 int &CmpMask, int &CmpValue) const {
3354 switch (MI->getOpcode()) {
3355 default: break;
3356 case X86::CMP64ri32:
3357 case X86::CMP64ri8:
3358 case X86::CMP32ri:
3359 case X86::CMP32ri8:
3360 case X86::CMP16ri:
3361 case X86::CMP16ri8:
3362 case X86::CMP8ri:
3363 SrcReg = MI->getOperand(0).getReg();
3364 SrcReg2 = 0;
3365 CmpMask = ~0;
3366 CmpValue = MI->getOperand(1).getImm();
3367 return true;
3368 // A SUB can be used to perform comparison.
3369 case X86::SUB64rm:
3370 case X86::SUB32rm:
3371 case X86::SUB16rm:
3372 case X86::SUB8rm:
3373 SrcReg = MI->getOperand(1).getReg();
3374 SrcReg2 = 0;
3375 CmpMask = ~0;
3376 CmpValue = 0;
3377 return true;
3378 case X86::SUB64rr:
3379 case X86::SUB32rr:
3380 case X86::SUB16rr:
3381 case X86::SUB8rr:
3382 SrcReg = MI->getOperand(1).getReg();
3383 SrcReg2 = MI->getOperand(2).getReg();
3384 CmpMask = ~0;
3385 CmpValue = 0;
3386 return true;
3387 case X86::SUB64ri32:
3388 case X86::SUB64ri8:
3389 case X86::SUB32ri:
3390 case X86::SUB32ri8:
3391 case X86::SUB16ri:
3392 case X86::SUB16ri8:
3393 case X86::SUB8ri:
3394 SrcReg = MI->getOperand(1).getReg();
3395 SrcReg2 = 0;
3396 CmpMask = ~0;
3397 CmpValue = MI->getOperand(2).getImm();
3398 return true;
3399 case X86::CMP64rr:
3400 case X86::CMP32rr:
3401 case X86::CMP16rr:
3402 case X86::CMP8rr:
3403 SrcReg = MI->getOperand(0).getReg();
3404 SrcReg2 = MI->getOperand(1).getReg();
3405 CmpMask = ~0;
3406 CmpValue = 0;
3407 return true;
3408 case X86::TEST8rr:
3409 case X86::TEST16rr:
3410 case X86::TEST32rr:
3411 case X86::TEST64rr:
3412 SrcReg = MI->getOperand(0).getReg();
3413 if (MI->getOperand(1).getReg() != SrcReg) return false;
3414 // Compare against zero.
3415 SrcReg2 = 0;
3416 CmpMask = ~0;
3417 CmpValue = 0;
3418 return true;
3419 }
3420 return false;
3421 }
3423 /// isRedundantFlagInstr - check whether the first instruction, whose only
3424 /// purpose is to update flags, can be made redundant.
3425 /// CMPrr can be made redundant by SUBrr if the operands are the same.
3426 /// This function can be extended later on.
3427 /// SrcReg, SrcRegs: register operands for FlagI.
3428 /// ImmValue: immediate for FlagI if it takes an immediate.
3429 inline static bool isRedundantFlagInstr(MachineInstr *FlagI, unsigned SrcReg,
3430 unsigned SrcReg2, int ImmValue,
3431 MachineInstr *OI) {
3432 if (((FlagI->getOpcode() == X86::CMP64rr &&
3433 OI->getOpcode() == X86::SUB64rr) ||
3434 (FlagI->getOpcode() == X86::CMP32rr &&
3435 OI->getOpcode() == X86::SUB32rr)||
3436 (FlagI->getOpcode() == X86::CMP16rr &&
3437 OI->getOpcode() == X86::SUB16rr)||
3438 (FlagI->getOpcode() == X86::CMP8rr &&
3439 OI->getOpcode() == X86::SUB8rr)) &&
3440 ((OI->getOperand(1).getReg() == SrcReg &&
3441 OI->getOperand(2).getReg() == SrcReg2) ||
3442 (OI->getOperand(1).getReg() == SrcReg2 &&
3443 OI->getOperand(2).getReg() == SrcReg)))
3444 return true;
3446 if (((FlagI->getOpcode() == X86::CMP64ri32 &&
3447 OI->getOpcode() == X86::SUB64ri32) ||
3448 (FlagI->getOpcode() == X86::CMP64ri8 &&
3449 OI->getOpcode() == X86::SUB64ri8) ||
3450 (FlagI->getOpcode() == X86::CMP32ri &&
3451 OI->getOpcode() == X86::SUB32ri) ||
3452 (FlagI->getOpcode() == X86::CMP32ri8 &&
3453 OI->getOpcode() == X86::SUB32ri8) ||
3454 (FlagI->getOpcode() == X86::CMP16ri &&
3455 OI->getOpcode() == X86::SUB16ri) ||
3456 (FlagI->getOpcode() == X86::CMP16ri8 &&
3457 OI->getOpcode() == X86::SUB16ri8) ||
3458 (FlagI->getOpcode() == X86::CMP8ri &&
3459 OI->getOpcode() == X86::SUB8ri)) &&
3460 OI->getOperand(1).getReg() == SrcReg &&
3461 OI->getOperand(2).getImm() == ImmValue)
3462 return true;
3463 return false;
3464 }
3466 /// isDefConvertible - check whether the definition can be converted
3467 /// to remove a comparison against zero.
3468 inline static bool isDefConvertible(MachineInstr *MI) {
3469 switch (MI->getOpcode()) {
3470 default: return false;
3472 // The shift instructions only modify ZF if their shift count is non-zero.
3473 // N.B.: The processor truncates the shift count depending on the encoding.
3474 case X86::SAR8ri: case X86::SAR16ri: case X86::SAR32ri:case X86::SAR64ri:
3475 case X86::SHR8ri: case X86::SHR16ri: case X86::SHR32ri:case X86::SHR64ri:
3476 return getTruncatedShiftCount(MI, 2) != 0;
3478 // Some left shift instructions can be turned into LEA instructions but only
3479 // if their flags aren't used. Avoid transforming such instructions.
3480 case X86::SHL8ri: case X86::SHL16ri: case X86::SHL32ri:case X86::SHL64ri:{
3481 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
3482 if (isTruncatedShiftCountForLEA(ShAmt)) return false;
3483 return ShAmt != 0;
3484 }
3486 case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
3487 case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
3488 return getTruncatedShiftCount(MI, 3) != 0;
3490 case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
3491 case X86::SUB32ri8: case X86::SUB16ri: case X86::SUB16ri8:
3492 case X86::SUB8ri: case X86::SUB64rr: case X86::SUB32rr:
3493 case X86::SUB16rr: case X86::SUB8rr: case X86::SUB64rm:
3494 case X86::SUB32rm: case X86::SUB16rm: case X86::SUB8rm:
3495 case X86::DEC64r: case X86::DEC32r: case X86::DEC16r: case X86::DEC8r:
3496 case X86::DEC64_32r: case X86::DEC64_16r:
3497 case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
3498 case X86::ADD32ri8: case X86::ADD16ri: case X86::ADD16ri8:
3499 case X86::ADD8ri: case X86::ADD64rr: case X86::ADD32rr:
3500 case X86::ADD16rr: case X86::ADD8rr: case X86::ADD64rm:
3501 case X86::ADD32rm: case X86::ADD16rm: case X86::ADD8rm:
3502 case X86::INC64r: case X86::INC32r: case X86::INC16r: case X86::INC8r:
3503 case X86::INC64_32r: case X86::INC64_16r:
3504 case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
3505 case X86::AND32ri8: case X86::AND16ri: case X86::AND16ri8:
3506 case X86::AND8ri: case X86::AND64rr: case X86::AND32rr:
3507 case X86::AND16rr: case X86::AND8rr: case X86::AND64rm:
3508 case X86::AND32rm: case X86::AND16rm: case X86::AND8rm:
3509 case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
3510 case X86::XOR32ri8: case X86::XOR16ri: case X86::XOR16ri8:
3511 case X86::XOR8ri: case X86::XOR64rr: case X86::XOR32rr:
3512 case X86::XOR16rr: case X86::XOR8rr: case X86::XOR64rm:
3513 case X86::XOR32rm: case X86::XOR16rm: case X86::XOR8rm:
3514 case X86::OR64ri32: case X86::OR64ri8: case X86::OR32ri:
3515 case X86::OR32ri8: case X86::OR16ri: case X86::OR16ri8:
3516 case X86::OR8ri: case X86::OR64rr: case X86::OR32rr:
3517 case X86::OR16rr: case X86::OR8rr: case X86::OR64rm:
3518 case X86::OR32rm: case X86::OR16rm: case X86::OR8rm:
3519 case X86::NEG8r: case X86::NEG16r: case X86::NEG32r: case X86::NEG64r:
3520 case X86::SAR8r1: case X86::SAR16r1: case X86::SAR32r1:case X86::SAR64r1:
3521 case X86::SHR8r1: case X86::SHR16r1: case X86::SHR32r1:case X86::SHR64r1:
3522 case X86::SHL8r1: case X86::SHL16r1: case X86::SHL32r1:case X86::SHL64r1:
3523 case X86::ADC32ri: case X86::ADC32ri8:
3524 case X86::ADC32rr: case X86::ADC64ri32:
3525 case X86::ADC64ri8: case X86::ADC64rr:
3526 case X86::SBB32ri: case X86::SBB32ri8:
3527 case X86::SBB32rr: case X86::SBB64ri32:
3528 case X86::SBB64ri8: case X86::SBB64rr:
3529 case X86::ANDN32rr: case X86::ANDN32rm:
3530 case X86::ANDN64rr: case X86::ANDN64rm:
3531 case X86::BEXTR32rr: case X86::BEXTR64rr:
3532 case X86::BEXTR32rm: case X86::BEXTR64rm:
3533 case X86::BLSI32rr: case X86::BLSI32rm:
3534 case X86::BLSI64rr: case X86::BLSI64rm:
3535 case X86::BLSMSK32rr:case X86::BLSMSK32rm:
3536 case X86::BLSMSK64rr:case X86::BLSMSK64rm:
3537 case X86::BLSR32rr: case X86::BLSR32rm:
3538 case X86::BLSR64rr: case X86::BLSR64rm:
3539 case X86::BZHI32rr: case X86::BZHI32rm:
3540 case X86::BZHI64rr: case X86::BZHI64rm:
3541 case X86::LZCNT16rr: case X86::LZCNT16rm:
3542 case X86::LZCNT32rr: case X86::LZCNT32rm:
3543 case X86::LZCNT64rr: case X86::LZCNT64rm:
3544 case X86::POPCNT16rr:case X86::POPCNT16rm:
3545 case X86::POPCNT32rr:case X86::POPCNT32rm:
3546 case X86::POPCNT64rr:case X86::POPCNT64rm:
3547 case X86::TZCNT16rr: case X86::TZCNT16rm:
3548 case X86::TZCNT32rr: case X86::TZCNT32rm:
3549 case X86::TZCNT64rr: case X86::TZCNT64rm:
3550 return true;
3551 }
3552 }
3554 /// optimizeCompareInstr - Check if there exists an earlier instruction that
3555 /// operates on the same source operands and sets flags in the same way as
3556 /// Compare; remove Compare if possible.
3557 bool X86InstrInfo::
3558 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
3559 int CmpMask, int CmpValue,
3560 const MachineRegisterInfo *MRI) const {
3561 // Check whether we can replace SUB with CMP.
3562 unsigned NewOpcode = 0;
3563 switch (CmpInstr->getOpcode()) {
3564 default: break;
3565 case X86::SUB64ri32:
3566 case X86::SUB64ri8:
3567 case X86::SUB32ri:
3568 case X86::SUB32ri8:
3569 case X86::SUB16ri:
3570 case X86::SUB16ri8:
3571 case X86::SUB8ri:
3572 case X86::SUB64rm:
3573 case X86::SUB32rm:
3574 case X86::SUB16rm:
3575 case X86::SUB8rm:
3576 case X86::SUB64rr:
3577 case X86::SUB32rr:
3578 case X86::SUB16rr:
3579 case X86::SUB8rr: {
3580 if (!MRI->use_nodbg_empty(CmpInstr->getOperand(0).getReg()))
3581 return false;
3582 // There is no use of the destination register, we can replace SUB with CMP.
3583 switch (CmpInstr->getOpcode()) {
3584 default: llvm_unreachable("Unreachable!");
3585 case X86::SUB64rm: NewOpcode = X86::CMP64rm; break;
3586 case X86::SUB32rm: NewOpcode = X86::CMP32rm; break;
3587 case X86::SUB16rm: NewOpcode = X86::CMP16rm; break;
3588 case X86::SUB8rm: NewOpcode = X86::CMP8rm; break;
3589 case X86::SUB64rr: NewOpcode = X86::CMP64rr; break;
3590 case X86::SUB32rr: NewOpcode = X86::CMP32rr; break;
3591 case X86::SUB16rr: NewOpcode = X86::CMP16rr; break;
3592 case X86::SUB8rr: NewOpcode = X86::CMP8rr; break;
3593 case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
3594 case X86::SUB64ri8: NewOpcode = X86::CMP64ri8; break;
3595 case X86::SUB32ri: NewOpcode = X86::CMP32ri; break;
3596 case X86::SUB32ri8: NewOpcode = X86::CMP32ri8; break;
3597 case X86::SUB16ri: NewOpcode = X86::CMP16ri; break;
3598 case X86::SUB16ri8: NewOpcode = X86::CMP16ri8; break;
3599 case X86::SUB8ri: NewOpcode = X86::CMP8ri; break;
3600 }
3601 CmpInstr->setDesc(get(NewOpcode));
3602 CmpInstr->RemoveOperand(0);
3603 // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
3604 if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
3605 NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
3606 return false;
3607 }
3608 }
3610 // Get the unique definition of SrcReg.
3611 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
3612 if (!MI) return false;
3614 // CmpInstr is the first instruction of the BB.
3615 MachineBasicBlock::iterator I = CmpInstr, Def = MI;
3617 // If we are comparing against zero, check whether we can use MI to update
3618 // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
3619 bool IsCmpZero = (SrcReg2 == 0 && CmpValue == 0);
3620 if (IsCmpZero && (MI->getParent() != CmpInstr->getParent() ||
3621 !isDefConvertible(MI)))
3622 return false;
3624 // We are searching for an earlier instruction that can make CmpInstr
3625 // redundant and that instruction will be saved in Sub.
3626 MachineInstr *Sub = NULL;
3627 const TargetRegisterInfo *TRI = &getRegisterInfo();
3629 // We iterate backward, starting from the instruction before CmpInstr and
3630 // stop when reaching the definition of a source register or done with the BB.
3631 // RI points to the instruction before CmpInstr.
3632 // If the definition is in this basic block, RE points to the definition;
3633 // otherwise, RE is the rend of the basic block.
3634 MachineBasicBlock::reverse_iterator
3635 RI = MachineBasicBlock::reverse_iterator(I),
3636 RE = CmpInstr->getParent() == MI->getParent() ?
3637 MachineBasicBlock::reverse_iterator(++Def) /* points to MI */ :
3638 CmpInstr->getParent()->rend();
3639 MachineInstr *Movr0Inst = 0;
3640 for (; RI != RE; ++RI) {
3641 MachineInstr *Instr = &*RI;
3642 // Check whether CmpInstr can be made redundant by the current instruction.
3643 if (!IsCmpZero &&
3644 isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) {
3645 Sub = Instr;
3646 break;
3647 }
3649 if (Instr->modifiesRegister(X86::EFLAGS, TRI) ||
3650 Instr->readsRegister(X86::EFLAGS, TRI)) {
3651 // This instruction modifies or uses EFLAGS.
3653 // MOV32r0 etc. are implemented with xor which clobbers condition code.
3654 // They are safe to move up, if the definition to EFLAGS is dead and
3655 // earlier instructions do not read or write EFLAGS.
3656 if (!Movr0Inst && Instr->getOpcode() == X86::MOV32r0 &&
3657 Instr->registerDefIsDead(X86::EFLAGS, TRI)) {
3658 Movr0Inst = Instr;
3659 continue;
3660 }
3662 // We can't remove CmpInstr.
3663 return false;
3664 }
3665 }
3667 // Return false if no candidates exist.
3668 if (!IsCmpZero && !Sub)
3669 return false;
3671 bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
3672 Sub->getOperand(2).getReg() == SrcReg);
3674 // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
3675 // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
3676 // If we are done with the basic block, we need to check whether EFLAGS is
3677 // live-out.
3678 bool IsSafe = false;
3679 SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
3680 MachineBasicBlock::iterator E = CmpInstr->getParent()->end();
3681 for (++I; I != E; ++I) {
3682 const MachineInstr &Instr = *I;
3683 bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
3684 bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
3685 // We should check the usage if this instruction uses and updates EFLAGS.
3686 if (!UseEFLAGS && ModifyEFLAGS) {
3687 // It is safe to remove CmpInstr if EFLAGS is updated again.
3688 IsSafe = true;
3689 break;
3690 }
3691 if (!UseEFLAGS && !ModifyEFLAGS)
3692 continue;
3694 // EFLAGS is used by this instruction.
3695 X86::CondCode OldCC;
3696 bool OpcIsSET = false;
3697 if (IsCmpZero || IsSwapped) {
3698 // We decode the condition code from opcode.
3699 if (Instr.isBranch())
3700 OldCC = getCondFromBranchOpc(Instr.getOpcode());
3701 else {
3702 OldCC = getCondFromSETOpc(Instr.getOpcode());
3703 if (OldCC != X86::COND_INVALID)
3704 OpcIsSET = true;
3705 else
3706 OldCC = X86::getCondFromCMovOpc(Instr.getOpcode());
3707 }
3708 if (OldCC == X86::COND_INVALID) return false;
3709 }
3710 if (IsCmpZero) {
3711 switch (OldCC) {
3712 default: break;
3713 case X86::COND_A: case X86::COND_AE:
3714 case X86::COND_B: case X86::COND_BE:
3715 case X86::COND_G: case X86::COND_GE:
3716 case X86::COND_L: case X86::COND_LE:
3717 case X86::COND_O: case X86::COND_NO:
3718 // CF and OF are used, we can't perform this optimization.
3719 return false;
3720 }
3721 } else if (IsSwapped) {
3722 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
3723 // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
3724 // We swap the condition code and synthesize the new opcode.
3725 X86::CondCode NewCC = getSwappedCondition(OldCC);
3726 if (NewCC == X86::COND_INVALID) return false;
3728 // Synthesize the new opcode.
3729 bool HasMemoryOperand = Instr.hasOneMemOperand();
3730 unsigned NewOpc;
3731 if (Instr.isBranch())
3732 NewOpc = GetCondBranchFromCond(NewCC);
3733 else if(OpcIsSET)
3734 NewOpc = getSETFromCond(NewCC, HasMemoryOperand);
3735 else {
3736 unsigned DstReg = Instr.getOperand(0).getReg();
3737 NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(),
3738 HasMemoryOperand);
3739 }
3741 // Push the MachineInstr to OpsToUpdate.
3742 // If it is safe to remove CmpInstr, the condition code of these
3743 // instructions will be modified.
3744 OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
3745 }
3746 if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
3747 // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
3748 IsSafe = true;
3749 break;
3750 }
3751 }
3753 // If EFLAGS is not killed nor re-defined, we should check whether it is
3754 // live-out. If it is live-out, do not optimize.
3755 if ((IsCmpZero || IsSwapped) && !IsSafe) {
3756 MachineBasicBlock *MBB = CmpInstr->getParent();
3757 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
3758 SE = MBB->succ_end(); SI != SE; ++SI)
3759 if ((*SI)->isLiveIn(X86::EFLAGS))
3760 return false;
3761 }
3763 // The instruction to be updated is either Sub or MI.
3764 Sub = IsCmpZero ? MI : Sub;
3765 // Move Movr0Inst to the appropriate place before Sub.
3766 if (Movr0Inst) {
3767 // Look backwards until we find a def that doesn't use the current EFLAGS.
3768 Def = Sub;
3769 MachineBasicBlock::reverse_iterator
3770 InsertI = MachineBasicBlock::reverse_iterator(++Def),
3771 InsertE = Sub->getParent()->rend();
3772 for (; InsertI != InsertE; ++InsertI) {
3773 MachineInstr *Instr = &*InsertI;
3774 if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
3775 Instr->modifiesRegister(X86::EFLAGS, TRI)) {
3776 Sub->getParent()->remove(Movr0Inst);
3777 Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
3778 Movr0Inst);
3779 break;
3780 }
3781 }
3782 if (InsertI == InsertE)
3783 return false;
3784 }
3786 // Make sure Sub instruction defines EFLAGS and mark the def live.
3787 unsigned i = 0, e = Sub->getNumOperands();
3788 for (; i != e; ++i) {
3789 MachineOperand &MO = Sub->getOperand(i);
3790 if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
3791 MO.setIsDead(false);
3792 break;
3793 }
3794 }
3795 assert(i != e && "Unable to locate a def EFLAGS operand");
3797 CmpInstr->eraseFromParent();
3799 // Modify the condition code of instructions in OpsToUpdate.
3800 for (unsigned i = 0, e = OpsToUpdate.size(); i < e; i++)
3801 OpsToUpdate[i].first->setDesc(get(OpsToUpdate[i].second));
3802 return true;
3803 }
3805 /// optimizeLoadInstr - Try to remove the load by folding it to a register
3806 /// operand at the use. We fold the load instructions if load defines a virtual
3807 /// register, the virtual register is used once in the same BB, and the
3808 /// instructions in-between do not load or store, and have no side effects.
3809 MachineInstr* X86InstrInfo::
3810 optimizeLoadInstr(MachineInstr *MI, const MachineRegisterInfo *MRI,
3811 unsigned &FoldAsLoadDefReg,
3812 MachineInstr *&DefMI) const {
3813 if (FoldAsLoadDefReg == 0)
3814 return 0;
3815 // To be conservative, if there exists another load, clear the load candidate.
3816 if (MI->mayLoad()) {
3817 FoldAsLoadDefReg = 0;
3818 return 0;
3819 }
3821 // Check whether we can move DefMI here.
3822 DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
3823 assert(DefMI);
3824 bool SawStore = false;
3825 if (!DefMI->isSafeToMove(this, 0, SawStore))
3826 return 0;
3828 // We try to commute MI if possible.
3829 unsigned IdxEnd = (MI->isCommutable()) ? 2 : 1;
3830 for (unsigned Idx = 0; Idx < IdxEnd; Idx++) {
3831 // Collect information about virtual register operands of MI.
3832 unsigned SrcOperandId = 0;
3833 bool FoundSrcOperand = false;
3834 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
3835 MachineOperand &MO = MI->getOperand(i);
3836 if (!MO.isReg())
3837 continue;
3838 unsigned Reg = MO.getReg();
3839 if (Reg != FoldAsLoadDefReg)
3840 continue;
3841 // Do not fold if we have a subreg use or a def or multiple uses.
3842 if (MO.getSubReg() || MO.isDef() || FoundSrcOperand)
3843 return 0;
3845 SrcOperandId = i;
3846 FoundSrcOperand = true;
3847 }
3848 if (!FoundSrcOperand) return 0;
3850 // Check whether we can fold the def into SrcOperandId.
3851 SmallVector<unsigned, 8> Ops;
3852 Ops.push_back(SrcOperandId);
3853 MachineInstr *FoldMI = foldMemoryOperand(MI, Ops, DefMI);
3854 if (FoldMI) {
3855 FoldAsLoadDefReg = 0;
3856 return FoldMI;
3857 }
3859 if (Idx == 1) {
3860 // MI was changed but it didn't help, commute it back!
3861 commuteInstruction(MI, false);
3862 return 0;
3863 }
3865 // Check whether we can commute MI and enable folding.
3866 if (MI->isCommutable()) {
3867 MachineInstr *NewMI = commuteInstruction(MI, false);
3868 // Unable to commute.
3869 if (!NewMI) return 0;
3870 if (NewMI != MI) {
3871 // New instruction. It doesn't need to be kept.
3872 NewMI->eraseFromParent();
3873 return 0;
3874 }
3875 }
3876 }
3877 return 0;
3878 }
3880 /// Expand2AddrUndef - Expand a single-def pseudo instruction to a two-addr
3881 /// instruction with two undef reads of the register being defined. This is
3882 /// used for mapping:
3883 /// %xmm4 = V_SET0
3884 /// to:
3885 /// %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
3886 ///
3887 static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
3888 const MCInstrDesc &Desc) {
3889 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
3890 unsigned Reg = MIB->getOperand(0).getReg();
3891 MIB->setDesc(Desc);
3893 // MachineInstr::addOperand() will insert explicit operands before any
3894 // implicit operands.
3895 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
3896 // But we don't trust that.
3897 assert(MIB->getOperand(1).getReg() == Reg &&
3898 MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
3899 return true;
3900 }
3902 bool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
3903 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
3904 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
3905 switch (MI->getOpcode()) {
3906 case X86::MOV32r0:
3907 return Expand2AddrUndef(MIB, get(X86::XOR32rr));
3908 case X86::SETB_C8r:
3909 return Expand2AddrUndef(MIB, get(X86::SBB8rr));
3910 case X86::SETB_C16r:
3911 return Expand2AddrUndef(MIB, get(X86::SBB16rr));
3912 case X86::SETB_C32r:
3913 return Expand2AddrUndef(MIB, get(X86::SBB32rr));
3914 case X86::SETB_C64r:
3915 return Expand2AddrUndef(MIB, get(X86::SBB64rr));
3916 case X86::V_SET0:
3917 case X86::FsFLD0SS:
3918 case X86::FsFLD0SD:
3919 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
3920 case X86::AVX_SET0:
3921 assert(HasAVX && "AVX not supported");
3922 return Expand2AddrUndef(MIB, get(X86::VXORPSYrr));
3923 case X86::AVX512_512_SET0:
3924 return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
3925 case X86::V_SETALLONES:
3926 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
3927 case X86::AVX2_SETALLONES:
3928 return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
3929 case X86::TEST8ri_NOREX:
3930 MI->setDesc(get(X86::TEST8ri));
3931 return true;
3932 case X86::KSET0B:
3933 case X86::KSET0W: return Expand2AddrUndef(MIB, get(X86::KXORWrr));
3934 case X86::KSET1B:
3935 case X86::KSET1W: return Expand2AddrUndef(MIB, get(X86::KXNORWrr));
3936 }
3937 return false;
3938 }
3940 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
3941 const SmallVectorImpl<MachineOperand> &MOs,
3942 MachineInstr *MI,
3943 const TargetInstrInfo &TII) {
3944 // Create the base instruction with the memory operand as the first part.
3945 // Omit the implicit operands, something BuildMI can't do.
3946 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
3947 MI->getDebugLoc(), true);
3948 MachineInstrBuilder MIB(MF, NewMI);
3949 unsigned NumAddrOps = MOs.size();
3950 for (unsigned i = 0; i != NumAddrOps; ++i)
3951 MIB.addOperand(MOs[i]);
3952 if (NumAddrOps < 4) // FrameIndex only
3953 addOffset(MIB, 0);
3955 // Loop over the rest of the ri operands, converting them over.
3956 unsigned NumOps = MI->getDesc().getNumOperands()-2;
3957 for (unsigned i = 0; i != NumOps; ++i) {
3958 MachineOperand &MO = MI->getOperand(i+2);
3959 MIB.addOperand(MO);
3960 }
3961 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
3962 MachineOperand &MO = MI->getOperand(i);
3963 MIB.addOperand(MO);
3964 }
3965 return MIB;
3966 }
3968 static MachineInstr *FuseInst(MachineFunction &MF,
3969 unsigned Opcode, unsigned OpNo,
3970 const SmallVectorImpl<MachineOperand> &MOs,
3971 MachineInstr *MI, const TargetInstrInfo &TII) {
3972 // Omit the implicit operands, something BuildMI can't do.
3973 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
3974 MI->getDebugLoc(), true);
3975 MachineInstrBuilder MIB(MF, NewMI);
3977 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
3978 MachineOperand &MO = MI->getOperand(i);
3979 if (i == OpNo) {
3980 assert(MO.isReg() && "Expected to fold into reg operand!");
3981 unsigned NumAddrOps = MOs.size();
3982 for (unsigned i = 0; i != NumAddrOps; ++i)
3983 MIB.addOperand(MOs[i]);
3984 if (NumAddrOps < 4) // FrameIndex only
3985 addOffset(MIB, 0);
3986 } else {
3987 MIB.addOperand(MO);
3988 }
3989 }
3990 return MIB;
3991 }
3993 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
3994 const SmallVectorImpl<MachineOperand> &MOs,
3995 MachineInstr *MI) {
3996 MachineFunction &MF = *MI->getParent()->getParent();
3997 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
3999 unsigned NumAddrOps = MOs.size();
4000 for (unsigned i = 0; i != NumAddrOps; ++i)
4001 MIB.addOperand(MOs[i]);
4002 if (NumAddrOps < 4) // FrameIndex only
4003 addOffset(MIB, 0);
4004 return MIB.addImm(0);
4005 }
4007 MachineInstr*
4008 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
4009 MachineInstr *MI, unsigned i,
4010 const SmallVectorImpl<MachineOperand> &MOs,
4011 unsigned Size, unsigned Align) const {
4012 const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0;
4013 bool isCallRegIndirect = TM.getSubtarget<X86Subtarget>().callRegIndirect();
4014 bool isTwoAddrFold = false;
4016 // Atom favors register form of call. So, we do not fold loads into calls
4017 // when X86Subtarget is Atom.
4018 if (isCallRegIndirect &&
4019 (MI->getOpcode() == X86::CALL32r || MI->getOpcode() == X86::CALL64r)) {
4020 return NULL;
4021 }
4023 unsigned NumOps = MI->getDesc().getNumOperands();
4024 bool isTwoAddr = NumOps > 1 &&
4025 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
4027 // FIXME: AsmPrinter doesn't know how to handle
4028 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
4029 if (MI->getOpcode() == X86::ADD32ri &&
4030 MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
4031 return NULL;
4033 MachineInstr *NewMI = NULL;
4034 // Folding a memory location into the two-address part of a two-address
4035 // instruction is different than folding it other places. It requires
4036 // replacing the *two* registers with the memory location.
4037 if (isTwoAddr && NumOps >= 2 && i < 2 &&
4038 MI->getOperand(0).isReg() &&
4039 MI->getOperand(1).isReg() &&
4040 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
4041 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
4042 isTwoAddrFold = true;
4043 } else if (i == 0) { // If operand 0
4044 if (MI->getOpcode() == X86::MOV32r0) {
4045 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
4046 if (NewMI)
4047 return NewMI;
4048 }
4050 OpcodeTablePtr = &RegOp2MemOpTable0;
4051 } else if (i == 1) {
4052 OpcodeTablePtr = &RegOp2MemOpTable1;
4053 } else if (i == 2) {
4054 OpcodeTablePtr = &RegOp2MemOpTable2;
4055 } else if (i == 3) {
4056 OpcodeTablePtr = &RegOp2MemOpTable3;
4057 }
4059 // If table selected...
4060 if (OpcodeTablePtr) {
4061 // Find the Opcode to fuse
4062 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
4063 OpcodeTablePtr->find(MI->getOpcode());
4064 if (I != OpcodeTablePtr->end()) {
4065 unsigned Opcode = I->second.first;
4066 unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
4067 if (Align < MinAlign)
4068 return NULL;
4069 bool NarrowToMOV32rm = false;
4070 if (Size) {
4071 unsigned RCSize = getRegClass(MI->getDesc(), i, &RI, MF)->getSize();
4072 if (Size < RCSize) {
4073 // Check if it's safe to fold the load. If the size of the object is
4074 // narrower than the load width, then it's not.
4075 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
4076 return NULL;
4077 // If this is a 64-bit load, but the spill slot is 32, then we can do
4078 // a 32-bit load which is implicitly zero-extended. This likely is due
4079 // to liveintervalanalysis remat'ing a load from stack slot.
4080 if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
4081 return NULL;
4082 Opcode = X86::MOV32rm;
4083 NarrowToMOV32rm = true;
4084 }
4085 }
4087 if (isTwoAddrFold)
4088 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this);
4089 else
4090 NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this);
4092 if (NarrowToMOV32rm) {
4093 // If this is the special case where we use a MOV32rm to load a 32-bit
4094 // value and zero-extend the top bits. Change the destination register
4095 // to a 32-bit one.
4096 unsigned DstReg = NewMI->getOperand(0).getReg();
4097 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
4098 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg,
4099 X86::sub_32bit));
4100 else
4101 NewMI->getOperand(0).setSubReg(X86::sub_32bit);
4102 }
4103 return NewMI;
4104 }
4105 }
4107 // No fusion
4108 if (PrintFailedFusing && !MI->isCopy())
4109 dbgs() << "We failed to fuse operand " << i << " in " << *MI;
4110 return NULL;
4111 }
4113 /// hasPartialRegUpdate - Return true for all instructions that only update
4114 /// the first 32 or 64-bits of the destination register and leave the rest
4115 /// unmodified. This can be used to avoid folding loads if the instructions
4116 /// only update part of the destination register, and the non-updated part is
4117 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
4118 /// instructions breaks the partial register dependency and it can improve
4119 /// performance. e.g.:
4120 ///
4121 /// movss (%rdi), %xmm0
4122 /// cvtss2sd %xmm0, %xmm0
4123 ///
4124 /// Instead of
4125 /// cvtss2sd (%rdi), %xmm0
4126 ///
4127 /// FIXME: This should be turned into a TSFlags.
4128 ///
4129 static bool hasPartialRegUpdate(unsigned Opcode) {
4130 switch (Opcode) {
4131 case X86::CVTSI2SSrr:
4132 case X86::CVTSI2SS64rr:
4133 case X86::CVTSI2SDrr:
4134 case X86::CVTSI2SD64rr:
4135 case X86::CVTSD2SSrr:
4136 case X86::Int_CVTSD2SSrr:
4137 case X86::CVTSS2SDrr:
4138 case X86::Int_CVTSS2SDrr:
4139 case X86::RCPSSr:
4140 case X86::RCPSSr_Int:
4141 case X86::ROUNDSDr:
4142 case X86::ROUNDSDr_Int:
4143 case X86::ROUNDSSr:
4144 case X86::ROUNDSSr_Int:
4145 case X86::RSQRTSSr:
4146 case X86::RSQRTSSr_Int:
4147 case X86::SQRTSSr:
4148 case X86::SQRTSSr_Int:
4149 return true;
4150 }
4152 return false;
4153 }
4155 /// getPartialRegUpdateClearance - Inform the ExeDepsFix pass how many idle
4156 /// instructions we would like before a partial register update.
4157 unsigned X86InstrInfo::
4158 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
4159 const TargetRegisterInfo *TRI) const {
4160 if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode()))
4161 return 0;
4163 // If MI is marked as reading Reg, the partial register update is wanted.
4164 const MachineOperand &MO = MI->getOperand(0);
4165 unsigned Reg = MO.getReg();
4166 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
4167 if (MO.readsReg() || MI->readsVirtualRegister(Reg))
4168 return 0;
4169 } else {
4170 if (MI->readsRegister(Reg, TRI))
4171 return 0;
4172 }
4174 // If any of the preceding 16 instructions are reading Reg, insert a
4175 // dependency breaking instruction. The magic number is based on a few
4176 // Nehalem experiments.
4177 return 16;
4178 }
4180 // Return true for any instruction the copies the high bits of the first source
4181 // operand into the unused high bits of the destination operand.
4182 static bool hasUndefRegUpdate(unsigned Opcode) {
4183 switch (Opcode) {
4184 case X86::VCVTSI2SSrr:
4185 case X86::Int_VCVTSI2SSrr:
4186 case X86::VCVTSI2SS64rr:
4187 case X86::Int_VCVTSI2SS64rr:
4188 case X86::VCVTSI2SDrr:
4189 case X86::Int_VCVTSI2SDrr:
4190 case X86::VCVTSI2SD64rr:
4191 case X86::Int_VCVTSI2SD64rr:
4192 case X86::VCVTSD2SSrr:
4193 case X86::Int_VCVTSD2SSrr:
4194 case X86::VCVTSS2SDrr:
4195 case X86::Int_VCVTSS2SDrr:
4196 case X86::VRCPSSr:
4197 case X86::VROUNDSDr:
4198 case X86::VROUNDSDr_Int:
4199 case X86::VROUNDSSr:
4200 case X86::VROUNDSSr_Int:
4201 case X86::VRSQRTSSr:
4202 case X86::VSQRTSSr:
4204 // AVX-512
4205 case X86::VCVTSD2SSZrr:
4206 case X86::VCVTSS2SDZrr:
4207 return true;
4208 }
4210 return false;
4211 }
4213 /// Inform the ExeDepsFix pass how many idle instructions we would like before
4214 /// certain undef register reads.
4215 ///
4216 /// This catches the VCVTSI2SD family of instructions:
4217 ///
4218 /// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14
4219 ///
4220 /// We should to be careful *not* to catch VXOR idioms which are presumably
4221 /// handled specially in the pipeline:
4222 ///
4223 /// vxorps %xmm1<undef>, %xmm1<undef>, %xmm1
4224 ///
4225 /// Like getPartialRegUpdateClearance, this makes a strong assumption that the
4226 /// high bits that are passed-through are not live.
4227 unsigned X86InstrInfo::
4228 getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum,
4229 const TargetRegisterInfo *TRI) const {
4230 if (!hasUndefRegUpdate(MI->getOpcode()))
4231 return 0;
4233 // Set the OpNum parameter to the first source operand.
4234 OpNum = 1;
4236 const MachineOperand &MO = MI->getOperand(OpNum);
4237 if (MO.isUndef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
4238 // Use the same magic number as getPartialRegUpdateClearance.
4239 return 16;
4240 }
4241 return 0;
4242 }
4244 void X86InstrInfo::
4245 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
4246 const TargetRegisterInfo *TRI) const {
4247 unsigned Reg = MI->getOperand(OpNum).getReg();
4248 // If MI kills this register, the false dependence is already broken.
4249 if (MI->killsRegister(Reg, TRI))
4250 return;
4251 if (X86::VR128RegClass.contains(Reg)) {
4252 // These instructions are all floating point domain, so xorps is the best
4253 // choice.
4254 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
4255 unsigned Opc = HasAVX ? X86::VXORPSrr : X86::XORPSrr;
4256 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(Opc), Reg)
4257 .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
4258 } else if (X86::VR256RegClass.contains(Reg)) {
4259 // Use vxorps to clear the full ymm register.
4260 // It wants to read and write the xmm sub-register.
4261 unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
4262 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(X86::VXORPSrr), XReg)
4263 .addReg(XReg, RegState::Undef).addReg(XReg, RegState::Undef)
4264 .addReg(Reg, RegState::ImplicitDefine);
4265 } else
4266 return;
4267 MI->addRegisterKilled(Reg, TRI, true);
4268 }
4270 MachineInstr*
4271 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
4272 const SmallVectorImpl<unsigned> &Ops,
4273 int FrameIndex) const {
4274 // Check switch flag
4275 if (NoFusing) return NULL;
4277 // Unless optimizing for size, don't fold to avoid partial
4278 // register update stalls
4279 if (!MF.getFunction()->getAttributes().
4280 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize) &&
4281 hasPartialRegUpdate(MI->getOpcode()))
4282 return 0;
4284 const MachineFrameInfo *MFI = MF.getFrameInfo();
4285 unsigned Size = MFI->getObjectSize(FrameIndex);
4286 unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
4287 // If the function stack isn't realigned we don't want to fold instructions
4288 // that need increased alignment.
4289 if (!RI.needsStackRealignment(MF))
4290 Alignment = std::min(Alignment, TM.getFrameLowering()->getStackAlignment());
4291 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
4292 unsigned NewOpc = 0;
4293 unsigned RCSize = 0;
4294 switch (MI->getOpcode()) {
4295 default: return NULL;
4296 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
4297 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
4298 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
4299 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
4300 }
4301 // Check if it's safe to fold the load. If the size of the object is
4302 // narrower than the load width, then it's not.
4303 if (Size < RCSize)
4304 return NULL;
4305 // Change to CMPXXri r, 0 first.
4306 MI->setDesc(get(NewOpc));
4307 MI->getOperand(1).ChangeToImmediate(0);
4308 } else if (Ops.size() != 1)
4309 return NULL;
4311 SmallVector<MachineOperand,4> MOs;
4312 MOs.push_back(MachineOperand::CreateFI(FrameIndex));
4313 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Size, Alignment);
4314 }
4316 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
4317 MachineInstr *MI,
4318 const SmallVectorImpl<unsigned> &Ops,
4319 MachineInstr *LoadMI) const {
4320 // If loading from a FrameIndex, fold directly from the FrameIndex.
4321 unsigned NumOps = LoadMI->getDesc().getNumOperands();
4322 int FrameIndex;
4323 if (isLoadFromStackSlot(LoadMI, FrameIndex))
4324 return foldMemoryOperandImpl(MF, MI, Ops, FrameIndex);
4326 // Check switch flag
4327 if (NoFusing) return NULL;
4329 // Unless optimizing for size, don't fold to avoid partial
4330 // register update stalls
4331 if (!MF.getFunction()->getAttributes().
4332 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize) &&
4333 hasPartialRegUpdate(MI->getOpcode()))
4334 return 0;
4336 // Determine the alignment of the load.
4337 unsigned Alignment = 0;
4338 if (LoadMI->hasOneMemOperand())
4339 Alignment = (*LoadMI->memoperands_begin())->getAlignment();
4340 else
4341 switch (LoadMI->getOpcode()) {
4342 case X86::AVX2_SETALLONES:
4343 case X86::AVX_SET0:
4344 Alignment = 32;
4345 break;
4346 case X86::V_SET0:
4347 case X86::V_SETALLONES:
4348 Alignment = 16;
4349 break;
4350 case X86::FsFLD0SD:
4351 Alignment = 8;
4352 break;
4353 case X86::FsFLD0SS:
4354 Alignment = 4;
4355 break;
4356 default:
4357 return 0;
4358 }
4359 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
4360 unsigned NewOpc = 0;
4361 switch (MI->getOpcode()) {
4362 default: return NULL;
4363 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
4364 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
4365 case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
4366 case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
4367 }
4368 // Change to CMPXXri r, 0 first.
4369 MI->setDesc(get(NewOpc));
4370 MI->getOperand(1).ChangeToImmediate(0);
4371 } else if (Ops.size() != 1)
4372 return NULL;
4374 // Make sure the subregisters match.
4375 // Otherwise we risk changing the size of the load.
4376 if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg())
4377 return NULL;
4379 SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
4380 switch (LoadMI->getOpcode()) {
4381 case X86::V_SET0:
4382 case X86::V_SETALLONES:
4383 case X86::AVX2_SETALLONES:
4384 case X86::AVX_SET0:
4385 case X86::FsFLD0SD:
4386 case X86::FsFLD0SS: {
4387 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
4388 // Create a constant-pool entry and operands to load from it.
4390 // Medium and large mode can't fold loads this way.
4391 if (TM.getCodeModel() != CodeModel::Small &&
4392 TM.getCodeModel() != CodeModel::Kernel)
4393 return NULL;
4395 // x86-32 PIC requires a PIC base register for constant pools.
4396 unsigned PICBase = 0;
4397 if (TM.getRelocationModel() == Reloc::PIC_) {
4398 if (TM.getSubtarget<X86Subtarget>().is64Bit())
4399 PICBase = X86::RIP;
4400 else
4401 // FIXME: PICBase = getGlobalBaseReg(&MF);
4402 // This doesn't work for several reasons.
4403 // 1. GlobalBaseReg may have been spilled.
4404 // 2. It may not be live at MI.
4405 return NULL;
4406 }
4408 // Create a constant-pool entry.
4409 MachineConstantPool &MCP = *MF.getConstantPool();
4410 Type *Ty;
4411 unsigned Opc = LoadMI->getOpcode();
4412 if (Opc == X86::FsFLD0SS)
4413 Ty = Type::getFloatTy(MF.getFunction()->getContext());
4414 else if (Opc == X86::FsFLD0SD)
4415 Ty = Type::getDoubleTy(MF.getFunction()->getContext());
4416 else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0)
4417 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8);
4418 else
4419 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
4421 bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES);
4422 const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
4423 Constant::getNullValue(Ty);
4424 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
4426 // Create operands to load from the constant pool entry.
4427 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
4428 MOs.push_back(MachineOperand::CreateImm(1));
4429 MOs.push_back(MachineOperand::CreateReg(0, false));
4430 MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
4431 MOs.push_back(MachineOperand::CreateReg(0, false));
4432 break;
4433 }
4434 default: {
4435 if ((LoadMI->getOpcode() == X86::MOVSSrm ||
4436 LoadMI->getOpcode() == X86::VMOVSSrm) &&
4437 MF.getRegInfo().getRegClass(LoadMI->getOperand(0).getReg())->getSize()
4438 > 4)
4439 // These instructions only load 32 bits, we can't fold them if the
4440 // destination register is wider than 32 bits (4 bytes).
4441 return NULL;
4442 if ((LoadMI->getOpcode() == X86::MOVSDrm ||
4443 LoadMI->getOpcode() == X86::VMOVSDrm) &&
4444 MF.getRegInfo().getRegClass(LoadMI->getOperand(0).getReg())->getSize()
4445 > 8)
4446 // These instructions only load 64 bits, we can't fold them if the
4447 // destination register is wider than 64 bits (8 bytes).
4448 return NULL;
4450 // Folding a normal load. Just copy the load's address operands.
4451 for (unsigned i = NumOps - X86::AddrNumOperands; i != NumOps; ++i)
4452 MOs.push_back(LoadMI->getOperand(i));
4453 break;
4454 }
4455 }
4456 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 0, Alignment);
4457 }
4460 bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
4461 const SmallVectorImpl<unsigned> &Ops) const {
4462 // Check switch flag
4463 if (NoFusing) return 0;
4465 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
4466 switch (MI->getOpcode()) {
4467 default: return false;
4468 case X86::TEST8rr:
4469 case X86::TEST16rr:
4470 case X86::TEST32rr:
4471 case X86::TEST64rr:
4472 return true;
4473 case X86::ADD32ri:
4474 // FIXME: AsmPrinter doesn't know how to handle
4475 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
4476 if (MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
4477 return false;
4478 break;
4479 }
4480 }
4482 if (Ops.size() != 1)
4483 return false;
4485 unsigned OpNum = Ops[0];
4486 unsigned Opc = MI->getOpcode();
4487 unsigned NumOps = MI->getDesc().getNumOperands();
4488 bool isTwoAddr = NumOps > 1 &&
4489 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
4491 // Folding a memory location into the two-address part of a two-address
4492 // instruction is different than folding it other places. It requires
4493 // replacing the *two* registers with the memory location.
4494 const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0;
4495 if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
4496 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
4497 } else if (OpNum == 0) { // If operand 0
4498 if (Opc == X86::MOV32r0)
4499 return true;
4501 OpcodeTablePtr = &RegOp2MemOpTable0;
4502 } else if (OpNum == 1) {
4503 OpcodeTablePtr = &RegOp2MemOpTable1;
4504 } else if (OpNum == 2) {
4505 OpcodeTablePtr = &RegOp2MemOpTable2;
4506 } else if (OpNum == 3) {
4507 OpcodeTablePtr = &RegOp2MemOpTable3;
4508 }
4510 if (OpcodeTablePtr && OpcodeTablePtr->count(Opc))
4511 return true;
4512 return TargetInstrInfo::canFoldMemoryOperand(MI, Ops);
4513 }
4515 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
4516 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
4517 SmallVectorImpl<MachineInstr*> &NewMIs) const {
4518 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
4519 MemOp2RegOpTable.find(MI->getOpcode());
4520 if (I == MemOp2RegOpTable.end())
4521 return false;
4522 unsigned Opc = I->second.first;
4523 unsigned Index = I->second.second & TB_INDEX_MASK;
4524 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
4525 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
4526 if (UnfoldLoad && !FoldedLoad)
4527 return false;
4528 UnfoldLoad &= FoldedLoad;
4529 if (UnfoldStore && !FoldedStore)
4530 return false;
4531 UnfoldStore &= FoldedStore;
4533 const MCInstrDesc &MCID = get(Opc);
4534 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
4535 if (!MI->hasOneMemOperand() &&
4536 RC == &X86::VR128RegClass &&
4537 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
4538 // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
4539 // conservatively assume the address is unaligned. That's bad for
4540 // performance.
4541 return false;
4542 SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
4543 SmallVector<MachineOperand,2> BeforeOps;
4544 SmallVector<MachineOperand,2> AfterOps;
4545 SmallVector<MachineOperand,4> ImpOps;
4546 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
4547 MachineOperand &Op = MI->getOperand(i);
4548 if (i >= Index && i < Index + X86::AddrNumOperands)
4549 AddrOps.push_back(Op);
4550 else if (Op.isReg() && Op.isImplicit())
4551 ImpOps.push_back(Op);
4552 else if (i < Index)
4553 BeforeOps.push_back(Op);
4554 else if (i > Index)
4555 AfterOps.push_back(Op);
4556 }
4558 // Emit the load instruction.
4559 if (UnfoldLoad) {
4560 std::pair<MachineInstr::mmo_iterator,
4561 MachineInstr::mmo_iterator> MMOs =
4562 MF.extractLoadMemRefs(MI->memoperands_begin(),
4563 MI->memoperands_end());
4564 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
4565 if (UnfoldStore) {
4566 // Address operands cannot be marked isKill.
4567 for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
4568 MachineOperand &MO = NewMIs[0]->getOperand(i);
4569 if (MO.isReg())
4570 MO.setIsKill(false);
4571 }
4572 }
4573 }
4575 // Emit the data processing instruction.
4576 MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI->getDebugLoc(), true);
4577 MachineInstrBuilder MIB(MF, DataMI);
4579 if (FoldedStore)
4580 MIB.addReg(Reg, RegState::Define);
4581 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
4582 MIB.addOperand(BeforeOps[i]);
4583 if (FoldedLoad)
4584 MIB.addReg(Reg);
4585 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
4586 MIB.addOperand(AfterOps[i]);
4587 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
4588 MachineOperand &MO = ImpOps[i];
4589 MIB.addReg(MO.getReg(),
4590 getDefRegState(MO.isDef()) |
4591 RegState::Implicit |
4592 getKillRegState(MO.isKill()) |
4593 getDeadRegState(MO.isDead()) |
4594 getUndefRegState(MO.isUndef()));
4595 }
4596 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
4597 switch (DataMI->getOpcode()) {
4598 default: break;
4599 case X86::CMP64ri32:
4600 case X86::CMP64ri8:
4601 case X86::CMP32ri:
4602 case X86::CMP32ri8:
4603 case X86::CMP16ri:
4604 case X86::CMP16ri8:
4605 case X86::CMP8ri: {
4606 MachineOperand &MO0 = DataMI->getOperand(0);
4607 MachineOperand &MO1 = DataMI->getOperand(1);
4608 if (MO1.getImm() == 0) {
4609 unsigned NewOpc;
4610 switch (DataMI->getOpcode()) {
4611 default: llvm_unreachable("Unreachable!");
4612 case X86::CMP64ri8:
4613 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
4614 case X86::CMP32ri8:
4615 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
4616 case X86::CMP16ri8:
4617 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
4618 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
4619 }
4620 DataMI->setDesc(get(NewOpc));
4621 MO1.ChangeToRegister(MO0.getReg(), false);
4622 }
4623 }
4624 }
4625 NewMIs.push_back(DataMI);
4627 // Emit the store instruction.
4628 if (UnfoldStore) {
4629 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
4630 std::pair<MachineInstr::mmo_iterator,
4631 MachineInstr::mmo_iterator> MMOs =
4632 MF.extractStoreMemRefs(MI->memoperands_begin(),
4633 MI->memoperands_end());
4634 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
4635 }
4637 return true;
4638 }
4640 bool
4641 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
4642 SmallVectorImpl<SDNode*> &NewNodes) const {
4643 if (!N->isMachineOpcode())
4644 return false;
4646 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
4647 MemOp2RegOpTable.find(N->getMachineOpcode());
4648 if (I == MemOp2RegOpTable.end())
4649 return false;
4650 unsigned Opc = I->second.first;
4651 unsigned Index = I->second.second & TB_INDEX_MASK;
4652 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
4653 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
4654 const MCInstrDesc &MCID = get(Opc);
4655 MachineFunction &MF = DAG.getMachineFunction();
4656 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
4657 unsigned NumDefs = MCID.NumDefs;
4658 std::vector<SDValue> AddrOps;
4659 std::vector<SDValue> BeforeOps;
4660 std::vector<SDValue> AfterOps;
4661 SDLoc dl(N);
4662 unsigned NumOps = N->getNumOperands();
4663 for (unsigned i = 0; i != NumOps-1; ++i) {
4664 SDValue Op = N->getOperand(i);
4665 if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
4666 AddrOps.push_back(Op);
4667 else if (i < Index-NumDefs)
4668 BeforeOps.push_back(Op);
4669 else if (i > Index-NumDefs)
4670 AfterOps.push_back(Op);
4671 }
4672 SDValue Chain = N->getOperand(NumOps-1);
4673 AddrOps.push_back(Chain);
4675 // Emit the load instruction.
4676 SDNode *Load = 0;
4677 if (FoldedLoad) {
4678 EVT VT = *RC->vt_begin();
4679 std::pair<MachineInstr::mmo_iterator,
4680 MachineInstr::mmo_iterator> MMOs =
4681 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
4682 cast<MachineSDNode>(N)->memoperands_end());
4683 if (!(*MMOs.first) &&
4684 RC == &X86::VR128RegClass &&
4685 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
4686 // Do not introduce a slow unaligned load.
4687 return false;
4688 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
4689 bool isAligned = (*MMOs.first) &&
4690 (*MMOs.first)->getAlignment() >= Alignment;
4691 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl,
4692 VT, MVT::Other, AddrOps);
4693 NewNodes.push_back(Load);
4695 // Preserve memory reference information.
4696 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
4697 }
4699 // Emit the data processing instruction.
4700 std::vector<EVT> VTs;
4701 const TargetRegisterClass *DstRC = 0;
4702 if (MCID.getNumDefs() > 0) {
4703 DstRC = getRegClass(MCID, 0, &RI, MF);
4704 VTs.push_back(*DstRC->vt_begin());
4705 }
4706 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
4707 EVT VT = N->getValueType(i);
4708 if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
4709 VTs.push_back(VT);
4710 }
4711 if (Load)
4712 BeforeOps.push_back(SDValue(Load, 0));
4713 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
4714 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
4715 NewNodes.push_back(NewNode);
4717 // Emit the store instruction.
4718 if (FoldedStore) {
4719 AddrOps.pop_back();
4720 AddrOps.push_back(SDValue(NewNode, 0));
4721 AddrOps.push_back(Chain);
4722 std::pair<MachineInstr::mmo_iterator,
4723 MachineInstr::mmo_iterator> MMOs =
4724 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
4725 cast<MachineSDNode>(N)->memoperands_end());
4726 if (!(*MMOs.first) &&
4727 RC == &X86::VR128RegClass &&
4728 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
4729 // Do not introduce a slow unaligned store.
4730 return false;
4731 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
4732 bool isAligned = (*MMOs.first) &&
4733 (*MMOs.first)->getAlignment() >= Alignment;
4734 SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC,
4735 isAligned, TM),
4736 dl, MVT::Other, AddrOps);
4737 NewNodes.push_back(Store);
4739 // Preserve memory reference information.
4740 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
4741 }
4743 return true;
4744 }
4746 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
4747 bool UnfoldLoad, bool UnfoldStore,
4748 unsigned *LoadRegIndex) const {
4749 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
4750 MemOp2RegOpTable.find(Opc);
4751 if (I == MemOp2RegOpTable.end())
4752 return 0;
4753 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
4754 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
4755 if (UnfoldLoad && !FoldedLoad)
4756 return 0;
4757 if (UnfoldStore && !FoldedStore)
4758 return 0;
4759 if (LoadRegIndex)
4760 *LoadRegIndex = I->second.second & TB_INDEX_MASK;
4761 return I->second.first;
4762 }
4764 bool
4765 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
4766 int64_t &Offset1, int64_t &Offset2) const {
4767 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
4768 return false;
4769 unsigned Opc1 = Load1->getMachineOpcode();
4770 unsigned Opc2 = Load2->getMachineOpcode();
4771 switch (Opc1) {
4772 default: return false;
4773 case X86::MOV8rm:
4774 case X86::MOV16rm:
4775 case X86::MOV32rm:
4776 case X86::MOV64rm:
4777 case X86::LD_Fp32m:
4778 case X86::LD_Fp64m:
4779 case X86::LD_Fp80m:
4780 case X86::MOVSSrm:
4781 case X86::MOVSDrm:
4782 case X86::MMX_MOVD64rm:
4783 case X86::MMX_MOVQ64rm:
4784 case X86::FsMOVAPSrm:
4785 case X86::FsMOVAPDrm:
4786 case X86::MOVAPSrm:
4787 case X86::MOVUPSrm:
4788 case X86::MOVAPDrm:
4789 case X86::MOVDQArm:
4790 case X86::MOVDQUrm:
4791 // AVX load instructions
4792 case X86::VMOVSSrm:
4793 case X86::VMOVSDrm:
4794 case X86::FsVMOVAPSrm:
4795 case X86::FsVMOVAPDrm:
4796 case X86::VMOVAPSrm:
4797 case X86::VMOVUPSrm:
4798 case X86::VMOVAPDrm:
4799 case X86::VMOVDQArm:
4800 case X86::VMOVDQUrm:
4801 case X86::VMOVAPSYrm:
4802 case X86::VMOVUPSYrm:
4803 case X86::VMOVAPDYrm:
4804 case X86::VMOVDQAYrm:
4805 case X86::VMOVDQUYrm:
4806 break;
4807 }
4808 switch (Opc2) {
4809 default: return false;
4810 case X86::MOV8rm:
4811 case X86::MOV16rm:
4812 case X86::MOV32rm:
4813 case X86::MOV64rm:
4814 case X86::LD_Fp32m:
4815 case X86::LD_Fp64m:
4816 case X86::LD_Fp80m:
4817 case X86::MOVSSrm:
4818 case X86::MOVSDrm:
4819 case X86::MMX_MOVD64rm:
4820 case X86::MMX_MOVQ64rm:
4821 case X86::FsMOVAPSrm:
4822 case X86::FsMOVAPDrm:
4823 case X86::MOVAPSrm:
4824 case X86::MOVUPSrm:
4825 case X86::MOVAPDrm:
4826 case X86::MOVDQArm:
4827 case X86::MOVDQUrm:
4828 // AVX load instructions
4829 case X86::VMOVSSrm:
4830 case X86::VMOVSDrm:
4831 case X86::FsVMOVAPSrm:
4832 case X86::FsVMOVAPDrm:
4833 case X86::VMOVAPSrm:
4834 case X86::VMOVUPSrm:
4835 case X86::VMOVAPDrm:
4836 case X86::VMOVDQArm:
4837 case X86::VMOVDQUrm:
4838 case X86::VMOVAPSYrm:
4839 case X86::VMOVUPSYrm:
4840 case X86::VMOVAPDYrm:
4841 case X86::VMOVDQAYrm:
4842 case X86::VMOVDQUYrm:
4843 break;
4844 }
4846 // Check if chain operands and base addresses match.
4847 if (Load1->getOperand(0) != Load2->getOperand(0) ||
4848 Load1->getOperand(5) != Load2->getOperand(5))
4849 return false;
4850 // Segment operands should match as well.
4851 if (Load1->getOperand(4) != Load2->getOperand(4))
4852 return false;
4853 // Scale should be 1, Index should be Reg0.
4854 if (Load1->getOperand(1) == Load2->getOperand(1) &&
4855 Load1->getOperand(2) == Load2->getOperand(2)) {
4856 if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
4857 return false;
4859 // Now let's examine the displacements.
4860 if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
4861 isa<ConstantSDNode>(Load2->getOperand(3))) {
4862 Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
4863 Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
4864 return true;
4865 }
4866 }
4867 return false;
4868 }
4870 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
4871 int64_t Offset1, int64_t Offset2,
4872 unsigned NumLoads) const {
4873 assert(Offset2 > Offset1);
4874 if ((Offset2 - Offset1) / 8 > 64)
4875 return false;
4877 unsigned Opc1 = Load1->getMachineOpcode();
4878 unsigned Opc2 = Load2->getMachineOpcode();
4879 if (Opc1 != Opc2)
4880 return false; // FIXME: overly conservative?
4882 switch (Opc1) {
4883 default: break;
4884 case X86::LD_Fp32m:
4885 case X86::LD_Fp64m:
4886 case X86::LD_Fp80m:
4887 case X86::MMX_MOVD64rm:
4888 case X86::MMX_MOVQ64rm:
4889 return false;
4890 }
4892 EVT VT = Load1->getValueType(0);
4893 switch (VT.getSimpleVT().SimpleTy) {
4894 default:
4895 // XMM registers. In 64-bit mode we can be a bit more aggressive since we
4896 // have 16 of them to play with.
4897 if (TM.getSubtargetImpl()->is64Bit()) {
4898 if (NumLoads >= 3)
4899 return false;
4900 } else if (NumLoads) {
4901 return false;
4902 }
4903 break;
4904 case MVT::i8:
4905 case MVT::i16:
4906 case MVT::i32:
4907 case MVT::i64:
4908 case MVT::f32:
4909 case MVT::f64:
4910 if (NumLoads)
4911 return false;
4912 break;
4913 }
4915 return true;
4916 }
4918 bool X86InstrInfo::shouldScheduleAdjacent(MachineInstr* First,
4919 MachineInstr *Second) const {
4920 // Check if this processor supports macro-fusion. Since this is a minor
4921 // heuristic, we haven't specifically reserved a feature. hasAVX is a decent
4922 // proxy for SandyBridge+.
4923 if (!TM.getSubtarget<X86Subtarget>().hasAVX())
4924 return false;
4926 enum {
4927 FuseTest,
4928 FuseCmp,
4929 FuseInc
4930 } FuseKind;
4932 switch(Second->getOpcode()) {
4933 default:
4934 return false;
4935 case X86::JE_4:
4936 case X86::JNE_4:
4937 case X86::JL_4:
4938 case X86::JLE_4:
4939 case X86::JG_4:
4940 case X86::JGE_4:
4941 FuseKind = FuseInc;
4942 break;
4943 case X86::JB_4:
4944 case X86::JBE_4:
4945 case X86::JA_4:
4946 case X86::JAE_4:
4947 FuseKind = FuseCmp;
4948 break;
4949 case X86::JS_4:
4950 case X86::JNS_4:
4951 case X86::JP_4:
4952 case X86::JNP_4:
4953 case X86::JO_4:
4954 case X86::JNO_4:
4955 FuseKind = FuseTest;
4956 break;
4957 }
4958 switch (First->getOpcode()) {
4959 default:
4960 return false;
4961 case X86::TEST8rr:
4962 case X86::TEST16rr:
4963 case X86::TEST32rr:
4964 case X86::TEST64rr:
4965 case X86::TEST8ri:
4966 case X86::TEST16ri:
4967 case X86::TEST32ri:
4968 case X86::TEST32i32:
4969 case X86::TEST64i32:
4970 case X86::TEST64ri32:
4971 case X86::TEST8rm:
4972 case X86::TEST16rm:
4973 case X86::TEST32rm:
4974 case X86::TEST64rm:
4975 case X86::AND16i16:
4976 case X86::AND16ri:
4977 case X86::AND16ri8:
4978 case X86::AND16rm:
4979 case X86::AND16rr:
4980 case X86::AND32i32:
4981 case X86::AND32ri:
4982 case X86::AND32ri8:
4983 case X86::AND32rm:
4984 case X86::AND32rr:
4985 case X86::AND64i32:
4986 case X86::AND64ri32:
4987 case X86::AND64ri8:
4988 case X86::AND64rm:
4989 case X86::AND64rr:
4990 case X86::AND8i8:
4991 case X86::AND8ri:
4992 case X86::AND8rm:
4993 case X86::AND8rr:
4994 return true;
4995 case X86::CMP16i16:
4996 case X86::CMP16ri:
4997 case X86::CMP16ri8:
4998 case X86::CMP16rm:
4999 case X86::CMP16rr:
5000 case X86::CMP32i32:
5001 case X86::CMP32ri:
5002 case X86::CMP32ri8:
5003 case X86::CMP32rm:
5004 case X86::CMP32rr:
5005 case X86::CMP64i32:
5006 case X86::CMP64ri32:
5007 case X86::CMP64ri8:
5008 case X86::CMP64rm:
5009 case X86::CMP64rr:
5010 case X86::CMP8i8:
5011 case X86::CMP8ri:
5012 case X86::CMP8rm:
5013 case X86::CMP8rr:
5014 case X86::ADD16i16:
5015 case X86::ADD16ri:
5016 case X86::ADD16ri8:
5017 case X86::ADD16ri8_DB:
5018 case X86::ADD16ri_DB:
5019 case X86::ADD16rm:
5020 case X86::ADD16rr:
5021 case X86::ADD16rr_DB:
5022 case X86::ADD32i32:
5023 case X86::ADD32ri:
5024 case X86::ADD32ri8:
5025 case X86::ADD32ri8_DB:
5026 case X86::ADD32ri_DB:
5027 case X86::ADD32rm:
5028 case X86::ADD32rr:
5029 case X86::ADD32rr_DB:
5030 case X86::ADD64i32:
5031 case X86::ADD64ri32:
5032 case X86::ADD64ri32_DB:
5033 case X86::ADD64ri8:
5034 case X86::ADD64ri8_DB:
5035 case X86::ADD64rm:
5036 case X86::ADD64rr:
5037 case X86::ADD64rr_DB:
5038 case X86::ADD8i8:
5039 case X86::ADD8mi:
5040 case X86::ADD8mr:
5041 case X86::ADD8ri:
5042 case X86::ADD8rm:
5043 case X86::ADD8rr:
5044 case X86::SUB16i16:
5045 case X86::SUB16ri:
5046 case X86::SUB16ri8:
5047 case X86::SUB16rm:
5048 case X86::SUB16rr:
5049 case X86::SUB32i32:
5050 case X86::SUB32ri:
5051 case X86::SUB32ri8:
5052 case X86::SUB32rm:
5053 case X86::SUB32rr:
5054 case X86::SUB64i32:
5055 case X86::SUB64ri32:
5056 case X86::SUB64ri8:
5057 case X86::SUB64rm:
5058 case X86::SUB64rr:
5059 case X86::SUB8i8:
5060 case X86::SUB8ri:
5061 case X86::SUB8rm:
5062 case X86::SUB8rr:
5063 return FuseKind == FuseCmp || FuseKind == FuseInc;
5064 case X86::INC16r:
5065 case X86::INC32r:
5066 case X86::INC64_16r:
5067 case X86::INC64_32r:
5068 case X86::INC64r:
5069 case X86::INC8r:
5070 case X86::DEC16r:
5071 case X86::DEC32r:
5072 case X86::DEC64_16r:
5073 case X86::DEC64_32r:
5074 case X86::DEC64r:
5075 case X86::DEC8r:
5076 return FuseKind == FuseInc;
5077 }
5078 }
5080 bool X86InstrInfo::
5081 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
5082 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
5083 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
5084 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
5085 return true;
5086 Cond[0].setImm(GetOppositeBranchCondition(CC));
5087 return false;
5088 }
5090 bool X86InstrInfo::
5091 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
5092 // FIXME: Return false for x87 stack register classes for now. We can't
5093 // allow any loads of these registers before FpGet_ST0_80.
5094 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
5095 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
5096 }
5098 /// getGlobalBaseReg - Return a virtual register initialized with the
5099 /// the global base register value. Output instructions required to
5100 /// initialize the register in the function entry block, if necessary.
5101 ///
5102 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
5103 ///
5104 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
5105 assert(!TM.getSubtarget<X86Subtarget>().is64Bit() &&
5106 "X86-64 PIC uses RIP relative addressing");
5108 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
5109 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
5110 if (GlobalBaseReg != 0)
5111 return GlobalBaseReg;
5113 // Create the register. The code to initialize it is inserted
5114 // later, by the CGBR pass (below).
5115 MachineRegisterInfo &RegInfo = MF->getRegInfo();
5116 GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
5117 X86FI->setGlobalBaseReg(GlobalBaseReg);
5118 return GlobalBaseReg;
5119 }
5121 // These are the replaceable SSE instructions. Some of these have Int variants
5122 // that we don't include here. We don't want to replace instructions selected
5123 // by intrinsics.
5124 static const uint16_t ReplaceableInstrs[][3] = {
5125 //PackedSingle PackedDouble PackedInt
5126 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr },
5127 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm },
5128 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr },
5129 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr },
5130 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm },
5131 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr },
5132 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm },
5133 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr },
5134 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm },
5135 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr },
5136 { X86::ORPSrm, X86::ORPDrm, X86::PORrm },
5137 { X86::ORPSrr, X86::ORPDrr, X86::PORrr },
5138 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm },
5139 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr },
5140 // AVX 128-bit support
5141 { X86::VMOVAPSmr, X86::VMOVAPDmr, X86::VMOVDQAmr },
5142 { X86::VMOVAPSrm, X86::VMOVAPDrm, X86::VMOVDQArm },
5143 { X86::VMOVAPSrr, X86::VMOVAPDrr, X86::VMOVDQArr },
5144 { X86::VMOVUPSmr, X86::VMOVUPDmr, X86::VMOVDQUmr },
5145 { X86::VMOVUPSrm, X86::VMOVUPDrm, X86::VMOVDQUrm },
5146 { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
5147 { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm },
5148 { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr },
5149 { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDrm },
5150 { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr },
5151 { X86::VORPSrm, X86::VORPDrm, X86::VPORrm },
5152 { X86::VORPSrr, X86::VORPDrr, X86::VPORrr },
5153 { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm },
5154 { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr },
5155 // AVX 256-bit support
5156 { X86::VMOVAPSYmr, X86::VMOVAPDYmr, X86::VMOVDQAYmr },
5157 { X86::VMOVAPSYrm, X86::VMOVAPDYrm, X86::VMOVDQAYrm },
5158 { X86::VMOVAPSYrr, X86::VMOVAPDYrr, X86::VMOVDQAYrr },
5159 { X86::VMOVUPSYmr, X86::VMOVUPDYmr, X86::VMOVDQUYmr },
5160 { X86::VMOVUPSYrm, X86::VMOVUPDYrm, X86::VMOVDQUYrm },
5161 { X86::VMOVNTPSYmr, X86::VMOVNTPDYmr, X86::VMOVNTDQYmr }
5162 };
5164 static const uint16_t ReplaceableInstrsAVX2[][3] = {
5165 //PackedSingle PackedDouble PackedInt
5166 { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNYrm },
5167 { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNYrr },
5168 { X86::VANDPSYrm, X86::VANDPDYrm, X86::VPANDYrm },
5169 { X86::VANDPSYrr, X86::VANDPDYrr, X86::VPANDYrr },
5170 { X86::VORPSYrm, X86::VORPDYrm, X86::VPORYrm },
5171 { X86::VORPSYrr, X86::VORPDYrr, X86::VPORYrr },
5172 { X86::VXORPSYrm, X86::VXORPDYrm, X86::VPXORYrm },
5173 { X86::VXORPSYrr, X86::VXORPDYrr, X86::VPXORYrr },
5174 { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
5175 { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
5176 { X86::VINSERTF128rm, X86::VINSERTF128rm, X86::VINSERTI128rm },
5177 { X86::VINSERTF128rr, X86::VINSERTF128rr, X86::VINSERTI128rr },
5178 { X86::VPERM2F128rm, X86::VPERM2F128rm, X86::VPERM2I128rm },
5179 { X86::VPERM2F128rr, X86::VPERM2F128rr, X86::VPERM2I128rr },
5180 { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
5181 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
5182 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
5183 { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
5184 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
5185 { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm}
5186 };
5188 // FIXME: Some shuffle and unpack instructions have equivalents in different
5189 // domains, but they require a bit more work than just switching opcodes.
5191 static const uint16_t *lookup(unsigned opcode, unsigned domain) {
5192 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i)
5193 if (ReplaceableInstrs[i][domain-1] == opcode)
5194 return ReplaceableInstrs[i];
5195 return 0;
5196 }
5198 static const uint16_t *lookupAVX2(unsigned opcode, unsigned domain) {
5199 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrsAVX2); i != e; ++i)
5200 if (ReplaceableInstrsAVX2[i][domain-1] == opcode)
5201 return ReplaceableInstrsAVX2[i];
5202 return 0;
5203 }
5205 std::pair<uint16_t, uint16_t>
5206 X86InstrInfo::getExecutionDomain(const MachineInstr *MI) const {
5207 uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
5208 bool hasAVX2 = TM.getSubtarget<X86Subtarget>().hasAVX2();
5209 uint16_t validDomains = 0;
5210 if (domain && lookup(MI->getOpcode(), domain))
5211 validDomains = 0xe;
5212 else if (domain && lookupAVX2(MI->getOpcode(), domain))
5213 validDomains = hasAVX2 ? 0xe : 0x6;
5214 return std::make_pair(domain, validDomains);
5215 }
5217 void X86InstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
5218 assert(Domain>0 && Domain<4 && "Invalid execution domain");
5219 uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
5220 assert(dom && "Not an SSE instruction");
5221 const uint16_t *table = lookup(MI->getOpcode(), dom);
5222 if (!table) { // try the other table
5223 assert((TM.getSubtarget<X86Subtarget>().hasAVX2() || Domain < 3) &&
5224 "256-bit vector operations only available in AVX2");
5225 table = lookupAVX2(MI->getOpcode(), dom);
5226 }
5227 assert(table && "Cannot change domain");
5228 MI->setDesc(get(table[Domain-1]));
5229 }
5231 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
5232 void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
5233 NopInst.setOpcode(X86::NOOP);
5234 }
5236 bool X86InstrInfo::isHighLatencyDef(int opc) const {
5237 switch (opc) {
5238 default: return false;
5239 case X86::DIVSDrm:
5240 case X86::DIVSDrm_Int:
5241 case X86::DIVSDrr:
5242 case X86::DIVSDrr_Int:
5243 case X86::DIVSSrm:
5244 case X86::DIVSSrm_Int:
5245 case X86::DIVSSrr:
5246 case X86::DIVSSrr_Int:
5247 case X86::SQRTPDm:
5248 case X86::SQRTPDr:
5249 case X86::SQRTPSm:
5250 case X86::SQRTPSr:
5251 case X86::SQRTSDm:
5252 case X86::SQRTSDm_Int:
5253 case X86::SQRTSDr:
5254 case X86::SQRTSDr_Int:
5255 case X86::SQRTSSm:
5256 case X86::SQRTSSm_Int:
5257 case X86::SQRTSSr:
5258 case X86::SQRTSSr_Int:
5259 // AVX instructions with high latency
5260 case X86::VDIVSDrm:
5261 case X86::VDIVSDrm_Int:
5262 case X86::VDIVSDrr:
5263 case X86::VDIVSDrr_Int:
5264 case X86::VDIVSSrm:
5265 case X86::VDIVSSrm_Int:
5266 case X86::VDIVSSrr:
5267 case X86::VDIVSSrr_Int:
5268 case X86::VSQRTPDm:
5269 case X86::VSQRTPDr:
5270 case X86::VSQRTPSm:
5271 case X86::VSQRTPSr:
5272 case X86::VSQRTSDm:
5273 case X86::VSQRTSDm_Int:
5274 case X86::VSQRTSDr:
5275 case X86::VSQRTSSm:
5276 case X86::VSQRTSSm_Int:
5277 case X86::VSQRTSSr:
5278 case X86::VSQRTPDZrm:
5279 case X86::VSQRTPDZrr:
5280 case X86::VSQRTPSZrm:
5281 case X86::VSQRTPSZrr:
5282 case X86::VSQRTSDZm:
5283 case X86::VSQRTSDZm_Int:
5284 case X86::VSQRTSDZr:
5285 case X86::VSQRTSSZm_Int:
5286 case X86::VSQRTSSZr:
5287 case X86::VSQRTSSZm:
5288 case X86::VDIVSDZrm:
5289 case X86::VDIVSDZrr:
5290 case X86::VDIVSSZrm:
5291 case X86::VDIVSSZrr:
5293 case X86::VGATHERQPSZrm:
5294 case X86::VGATHERQPDZrm:
5295 case X86::VGATHERDPDZrm:
5296 case X86::VGATHERDPSZrm:
5297 case X86::VPGATHERQDZrm:
5298 case X86::VPGATHERQQZrm:
5299 case X86::VPGATHERDDZrm:
5300 case X86::VPGATHERDQZrm:
5301 case X86::VSCATTERQPDZmr:
5302 case X86::VSCATTERQPSZmr:
5303 case X86::VSCATTERDPDZmr:
5304 case X86::VSCATTERDPSZmr:
5305 case X86::VPSCATTERQDZmr:
5306 case X86::VPSCATTERQQZmr:
5307 case X86::VPSCATTERDDZmr:
5308 case X86::VPSCATTERDQZmr:
5309 return true;
5310 }
5311 }
5313 bool X86InstrInfo::
5314 hasHighOperandLatency(const InstrItineraryData *ItinData,
5315 const MachineRegisterInfo *MRI,
5316 const MachineInstr *DefMI, unsigned DefIdx,
5317 const MachineInstr *UseMI, unsigned UseIdx) const {
5318 return isHighLatencyDef(DefMI->getOpcode());
5319 }
5321 namespace {
5322 /// CGBR - Create Global Base Reg pass. This initializes the PIC
5323 /// global base register for x86-32.
5324 struct CGBR : public MachineFunctionPass {
5325 static char ID;
5326 CGBR() : MachineFunctionPass(ID) {}
5328 bool runOnMachineFunction(MachineFunction &MF) override {
5329 const X86TargetMachine *TM =
5330 static_cast<const X86TargetMachine *>(&MF.getTarget());
5332 assert(!TM->getSubtarget<X86Subtarget>().is64Bit() &&
5333 "X86-64 PIC uses RIP relative addressing");
5335 // Only emit a global base reg in PIC mode.
5336 if (TM->getRelocationModel() != Reloc::PIC_)
5337 return false;
5339 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
5340 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
5342 // If we didn't need a GlobalBaseReg, don't insert code.
5343 if (GlobalBaseReg == 0)
5344 return false;
5346 // Insert the set of GlobalBaseReg into the first MBB of the function
5347 MachineBasicBlock &FirstMBB = MF.front();
5348 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
5349 DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
5350 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5351 const X86InstrInfo *TII = TM->getInstrInfo();
5353 unsigned PC;
5354 if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT())
5355 PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
5356 else
5357 PC = GlobalBaseReg;
5359 // Operand of MovePCtoStack is completely ignored by asm printer. It's
5360 // only used in JIT code emission as displacement to pc.
5361 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
5363 // If we're using vanilla 'GOT' PIC style, we should use relative addressing
5364 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
5365 if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT()) {
5366 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
5367 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
5368 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
5369 X86II::MO_GOT_ABSOLUTE_ADDRESS);
5370 }
5372 return true;
5373 }
5375 const char *getPassName() const override {
5376 return "X86 PIC Global Base Reg Initialization";
5377 }
5379 void getAnalysisUsage(AnalysisUsage &AU) const override {
5380 AU.setPreservesCFG();
5381 MachineFunctionPass::getAnalysisUsage(AU);
5382 }
5383 };
5384 }
5386 char CGBR::ID = 0;
5387 FunctionPass*
5388 llvm::createGlobalBaseRegPass() { return new CGBR(); }
5390 namespace {
5391 struct LDTLSCleanup : public MachineFunctionPass {
5392 static char ID;
5393 LDTLSCleanup() : MachineFunctionPass(ID) {}
5395 bool runOnMachineFunction(MachineFunction &MF) override {
5396 X86MachineFunctionInfo* MFI = MF.getInfo<X86MachineFunctionInfo>();
5397 if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
5398 // No point folding accesses if there isn't at least two.
5399 return false;
5400 }
5402 MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
5403 return VisitNode(DT->getRootNode(), 0);
5404 }
5406 // Visit the dominator subtree rooted at Node in pre-order.
5407 // If TLSBaseAddrReg is non-null, then use that to replace any
5408 // TLS_base_addr instructions. Otherwise, create the register
5409 // when the first such instruction is seen, and then use it
5410 // as we encounter more instructions.
5411 bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
5412 MachineBasicBlock *BB = Node->getBlock();
5413 bool Changed = false;
5415 // Traverse the current block.
5416 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
5417 ++I) {
5418 switch (I->getOpcode()) {
5419 case X86::TLS_base_addr32:
5420 case X86::TLS_base_addr64:
5421 if (TLSBaseAddrReg)
5422 I = ReplaceTLSBaseAddrCall(I, TLSBaseAddrReg);
5423 else
5424 I = SetRegister(I, &TLSBaseAddrReg);
5425 Changed = true;
5426 break;
5427 default:
5428 break;
5429 }
5430 }
5432 // Visit the children of this block in the dominator tree.
5433 for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
5434 I != E; ++I) {
5435 Changed |= VisitNode(*I, TLSBaseAddrReg);
5436 }
5438 return Changed;
5439 }
5441 // Replace the TLS_base_addr instruction I with a copy from
5442 // TLSBaseAddrReg, returning the new instruction.
5443 MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr *I,
5444 unsigned TLSBaseAddrReg) {
5445 MachineFunction *MF = I->getParent()->getParent();
5446 const X86TargetMachine *TM =
5447 static_cast<const X86TargetMachine *>(&MF->getTarget());
5448 const bool is64Bit = TM->getSubtarget<X86Subtarget>().is64Bit();
5449 const X86InstrInfo *TII = TM->getInstrInfo();
5451 // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
5452 MachineInstr *Copy = BuildMI(*I->getParent(), I, I->getDebugLoc(),
5453 TII->get(TargetOpcode::COPY),
5454 is64Bit ? X86::RAX : X86::EAX)
5455 .addReg(TLSBaseAddrReg);
5457 // Erase the TLS_base_addr instruction.
5458 I->eraseFromParent();
5460 return Copy;
5461 }
5463 // Create a virtal register in *TLSBaseAddrReg, and populate it by
5464 // inserting a copy instruction after I. Returns the new instruction.
5465 MachineInstr *SetRegister(MachineInstr *I, unsigned *TLSBaseAddrReg) {
5466 MachineFunction *MF = I->getParent()->getParent();
5467 const X86TargetMachine *TM =
5468 static_cast<const X86TargetMachine *>(&MF->getTarget());
5469 const bool is64Bit = TM->getSubtarget<X86Subtarget>().is64Bit();
5470 const X86InstrInfo *TII = TM->getInstrInfo();
5472 // Create a virtual register for the TLS base address.
5473 MachineRegisterInfo &RegInfo = MF->getRegInfo();
5474 *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
5475 ? &X86::GR64RegClass
5476 : &X86::GR32RegClass);
5478 // Insert a copy from RAX/EAX to TLSBaseAddrReg.
5479 MachineInstr *Next = I->getNextNode();
5480 MachineInstr *Copy = BuildMI(*I->getParent(), Next, I->getDebugLoc(),
5481 TII->get(TargetOpcode::COPY),
5482 *TLSBaseAddrReg)
5483 .addReg(is64Bit ? X86::RAX : X86::EAX);
5485 return Copy;
5486 }
5488 const char *getPassName() const override {
5489 return "Local Dynamic TLS Access Clean-up";
5490 }
5492 void getAnalysisUsage(AnalysisUsage &AU) const override {
5493 AU.setPreservesCFG();
5494 AU.addRequired<MachineDominatorTree>();
5495 MachineFunctionPass::getAnalysisUsage(AU);
5496 }
5497 };
5498 }
5500 char LDTLSCleanup::ID = 0;
5501 FunctionPass*
5502 llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }