1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the X86 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
14 #include "X86InstrInfo.h"
15 #include "X86.h"
16 #include "X86InstrBuilder.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/LiveVariables.h"
22 #include "llvm/CodeGen/MachineConstantPool.h"
23 #include "llvm/CodeGen/MachineDominators.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/StackMaps.h"
28 #include "llvm/IR/DerivedTypes.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/IR/LLVMContext.h"
31 #include "llvm/MC/MCAsmInfo.h"
32 #include "llvm/MC/MCExpr.h"
33 #include "llvm/MC/MCInst.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
38 #include "llvm/Target/TargetOptions.h"
39 #include <limits>
41 using namespace llvm;
43 #define DEBUG_TYPE "x86-instr-info"
45 #define GET_INSTRINFO_CTOR_DTOR
46 #include "X86GenInstrInfo.inc"
48 static cl::opt<bool>
49 NoFusing("disable-spill-fusing",
50 cl::desc("Disable fusing of spill code into instructions"));
51 static cl::opt<bool>
52 PrintFailedFusing("print-failed-fuse-candidates",
53 cl::desc("Print instructions that the allocator wants to"
54 " fuse, but the X86 backend currently can't"),
55 cl::Hidden);
56 static cl::opt<bool>
57 ReMatPICStubLoad("remat-pic-stub-load",
58 cl::desc("Re-materialize load from stub in PIC mode"),
59 cl::init(false), cl::Hidden);
61 enum {
62 // Select which memory operand is being unfolded.
63 // (stored in bits 0 - 3)
64 TB_INDEX_0 = 0,
65 TB_INDEX_1 = 1,
66 TB_INDEX_2 = 2,
67 TB_INDEX_3 = 3,
68 TB_INDEX_4 = 4,
69 TB_INDEX_MASK = 0xf,
71 // Do not insert the reverse map (MemOp -> RegOp) into the table.
72 // This may be needed because there is a many -> one mapping.
73 TB_NO_REVERSE = 1 << 4,
75 // Do not insert the forward map (RegOp -> MemOp) into the table.
76 // This is needed for Native Client, which prohibits branch
77 // instructions from using a memory operand.
78 TB_NO_FORWARD = 1 << 5,
80 TB_FOLDED_LOAD = 1 << 6,
81 TB_FOLDED_STORE = 1 << 7,
83 // Minimum alignment required for load/store.
84 // Used for RegOp->MemOp conversion.
85 // (stored in bits 8 - 15)
86 TB_ALIGN_SHIFT = 8,
87 TB_ALIGN_NONE = 0 << TB_ALIGN_SHIFT,
88 TB_ALIGN_16 = 16 << TB_ALIGN_SHIFT,
89 TB_ALIGN_32 = 32 << TB_ALIGN_SHIFT,
90 TB_ALIGN_64 = 64 << TB_ALIGN_SHIFT,
91 TB_ALIGN_MASK = 0xff << TB_ALIGN_SHIFT
92 };
94 struct X86OpTblEntry {
95 uint16_t RegOp;
96 uint16_t MemOp;
97 uint16_t Flags;
98 };
100 // Pin the vtable to this file.
101 void X86InstrInfo::anchor() {}
103 X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
104 : X86GenInstrInfo(
105 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64 : X86::ADJCALLSTACKDOWN32),
106 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64 : X86::ADJCALLSTACKUP32)),
107 Subtarget(STI), RI(STI) {
109 static const X86OpTblEntry OpTbl2Addr[] = {
110 { X86::ADC32ri, X86::ADC32mi, 0 },
111 { X86::ADC32ri8, X86::ADC32mi8, 0 },
112 { X86::ADC32rr, X86::ADC32mr, 0 },
113 { X86::ADC64ri32, X86::ADC64mi32, 0 },
114 { X86::ADC64ri8, X86::ADC64mi8, 0 },
115 { X86::ADC64rr, X86::ADC64mr, 0 },
116 { X86::ADD16ri, X86::ADD16mi, 0 },
117 { X86::ADD16ri8, X86::ADD16mi8, 0 },
118 { X86::ADD16ri_DB, X86::ADD16mi, TB_NO_REVERSE },
119 { X86::ADD16ri8_DB, X86::ADD16mi8, TB_NO_REVERSE },
120 { X86::ADD16rr, X86::ADD16mr, 0 },
121 { X86::ADD16rr_DB, X86::ADD16mr, TB_NO_REVERSE },
122 { X86::ADD32ri, X86::ADD32mi, 0 },
123 { X86::ADD32ri8, X86::ADD32mi8, 0 },
124 { X86::ADD32ri_DB, X86::ADD32mi, TB_NO_REVERSE },
125 { X86::ADD32ri8_DB, X86::ADD32mi8, TB_NO_REVERSE },
126 { X86::ADD32rr, X86::ADD32mr, 0 },
127 { X86::ADD32rr_DB, X86::ADD32mr, TB_NO_REVERSE },
128 { X86::ADD64ri32, X86::ADD64mi32, 0 },
129 { X86::ADD64ri8, X86::ADD64mi8, 0 },
130 { X86::ADD64ri32_DB,X86::ADD64mi32, TB_NO_REVERSE },
131 { X86::ADD64ri8_DB, X86::ADD64mi8, TB_NO_REVERSE },
132 { X86::ADD64rr, X86::ADD64mr, 0 },
133 { X86::ADD64rr_DB, X86::ADD64mr, TB_NO_REVERSE },
134 { X86::ADD8ri, X86::ADD8mi, 0 },
135 { X86::ADD8rr, X86::ADD8mr, 0 },
136 { X86::AND16ri, X86::AND16mi, 0 },
137 { X86::AND16ri8, X86::AND16mi8, 0 },
138 { X86::AND16rr, X86::AND16mr, 0 },
139 { X86::AND32ri, X86::AND32mi, 0 },
140 { X86::AND32ri8, X86::AND32mi8, 0 },
141 { X86::AND32rr, X86::AND32mr, 0 },
142 { X86::AND64ri32, X86::AND64mi32, 0 },
143 { X86::AND64ri8, X86::AND64mi8, 0 },
144 { X86::AND64rr, X86::AND64mr, 0 },
145 { X86::AND8ri, X86::AND8mi, 0 },
146 { X86::AND8rr, X86::AND8mr, 0 },
147 { X86::DEC16r, X86::DEC16m, 0 },
148 { X86::DEC32r, X86::DEC32m, 0 },
149 { X86::DEC64_16r, X86::DEC64_16m, 0 },
150 { X86::DEC64_32r, X86::DEC64_32m, 0 },
151 { X86::DEC64r, X86::DEC64m, 0 },
152 { X86::DEC8r, X86::DEC8m, 0 },
153 { X86::INC16r, X86::INC16m, 0 },
154 { X86::INC32r, X86::INC32m, 0 },
155 { X86::INC64_16r, X86::INC64_16m, 0 },
156 { X86::INC64_32r, X86::INC64_32m, 0 },
157 { X86::INC64r, X86::INC64m, 0 },
158 { X86::INC8r, X86::INC8m, 0 },
159 { X86::NEG16r, X86::NEG16m, 0 },
160 { X86::NEG32r, X86::NEG32m, 0 },
161 { X86::NEG64r, X86::NEG64m, 0 },
162 { X86::NEG8r, X86::NEG8m, 0 },
163 { X86::NOT16r, X86::NOT16m, 0 },
164 { X86::NOT32r, X86::NOT32m, 0 },
165 { X86::NOT64r, X86::NOT64m, 0 },
166 { X86::NOT8r, X86::NOT8m, 0 },
167 { X86::OR16ri, X86::OR16mi, 0 },
168 { X86::OR16ri8, X86::OR16mi8, 0 },
169 { X86::OR16rr, X86::OR16mr, 0 },
170 { X86::OR32ri, X86::OR32mi, 0 },
171 { X86::OR32ri8, X86::OR32mi8, 0 },
172 { X86::OR32rr, X86::OR32mr, 0 },
173 { X86::OR64ri32, X86::OR64mi32, 0 },
174 { X86::OR64ri8, X86::OR64mi8, 0 },
175 { X86::OR64rr, X86::OR64mr, 0 },
176 { X86::OR8ri, X86::OR8mi, 0 },
177 { X86::OR8rr, X86::OR8mr, 0 },
178 { X86::ROL16r1, X86::ROL16m1, 0 },
179 { X86::ROL16rCL, X86::ROL16mCL, 0 },
180 { X86::ROL16ri, X86::ROL16mi, 0 },
181 { X86::ROL32r1, X86::ROL32m1, 0 },
182 { X86::ROL32rCL, X86::ROL32mCL, 0 },
183 { X86::ROL32ri, X86::ROL32mi, 0 },
184 { X86::ROL64r1, X86::ROL64m1, 0 },
185 { X86::ROL64rCL, X86::ROL64mCL, 0 },
186 { X86::ROL64ri, X86::ROL64mi, 0 },
187 { X86::ROL8r1, X86::ROL8m1, 0 },
188 { X86::ROL8rCL, X86::ROL8mCL, 0 },
189 { X86::ROL8ri, X86::ROL8mi, 0 },
190 { X86::ROR16r1, X86::ROR16m1, 0 },
191 { X86::ROR16rCL, X86::ROR16mCL, 0 },
192 { X86::ROR16ri, X86::ROR16mi, 0 },
193 { X86::ROR32r1, X86::ROR32m1, 0 },
194 { X86::ROR32rCL, X86::ROR32mCL, 0 },
195 { X86::ROR32ri, X86::ROR32mi, 0 },
196 { X86::ROR64r1, X86::ROR64m1, 0 },
197 { X86::ROR64rCL, X86::ROR64mCL, 0 },
198 { X86::ROR64ri, X86::ROR64mi, 0 },
199 { X86::ROR8r1, X86::ROR8m1, 0 },
200 { X86::ROR8rCL, X86::ROR8mCL, 0 },
201 { X86::ROR8ri, X86::ROR8mi, 0 },
202 { X86::SAR16r1, X86::SAR16m1, 0 },
203 { X86::SAR16rCL, X86::SAR16mCL, 0 },
204 { X86::SAR16ri, X86::SAR16mi, 0 },
205 { X86::SAR32r1, X86::SAR32m1, 0 },
206 { X86::SAR32rCL, X86::SAR32mCL, 0 },
207 { X86::SAR32ri, X86::SAR32mi, 0 },
208 { X86::SAR64r1, X86::SAR64m1, 0 },
209 { X86::SAR64rCL, X86::SAR64mCL, 0 },
210 { X86::SAR64ri, X86::SAR64mi, 0 },
211 { X86::SAR8r1, X86::SAR8m1, 0 },
212 { X86::SAR8rCL, X86::SAR8mCL, 0 },
213 { X86::SAR8ri, X86::SAR8mi, 0 },
214 { X86::SBB32ri, X86::SBB32mi, 0 },
215 { X86::SBB32ri8, X86::SBB32mi8, 0 },
216 { X86::SBB32rr, X86::SBB32mr, 0 },
217 { X86::SBB64ri32, X86::SBB64mi32, 0 },
218 { X86::SBB64ri8, X86::SBB64mi8, 0 },
219 { X86::SBB64rr, X86::SBB64mr, 0 },
220 { X86::SHL16rCL, X86::SHL16mCL, 0 },
221 { X86::SHL16ri, X86::SHL16mi, 0 },
222 { X86::SHL32rCL, X86::SHL32mCL, 0 },
223 { X86::SHL32ri, X86::SHL32mi, 0 },
224 { X86::SHL64rCL, X86::SHL64mCL, 0 },
225 { X86::SHL64ri, X86::SHL64mi, 0 },
226 { X86::SHL8rCL, X86::SHL8mCL, 0 },
227 { X86::SHL8ri, X86::SHL8mi, 0 },
228 { X86::SHLD16rrCL, X86::SHLD16mrCL, 0 },
229 { X86::SHLD16rri8, X86::SHLD16mri8, 0 },
230 { X86::SHLD32rrCL, X86::SHLD32mrCL, 0 },
231 { X86::SHLD32rri8, X86::SHLD32mri8, 0 },
232 { X86::SHLD64rrCL, X86::SHLD64mrCL, 0 },
233 { X86::SHLD64rri8, X86::SHLD64mri8, 0 },
234 { X86::SHR16r1, X86::SHR16m1, 0 },
235 { X86::SHR16rCL, X86::SHR16mCL, 0 },
236 { X86::SHR16ri, X86::SHR16mi, 0 },
237 { X86::SHR32r1, X86::SHR32m1, 0 },
238 { X86::SHR32rCL, X86::SHR32mCL, 0 },
239 { X86::SHR32ri, X86::SHR32mi, 0 },
240 { X86::SHR64r1, X86::SHR64m1, 0 },
241 { X86::SHR64rCL, X86::SHR64mCL, 0 },
242 { X86::SHR64ri, X86::SHR64mi, 0 },
243 { X86::SHR8r1, X86::SHR8m1, 0 },
244 { X86::SHR8rCL, X86::SHR8mCL, 0 },
245 { X86::SHR8ri, X86::SHR8mi, 0 },
246 { X86::SHRD16rrCL, X86::SHRD16mrCL, 0 },
247 { X86::SHRD16rri8, X86::SHRD16mri8, 0 },
248 { X86::SHRD32rrCL, X86::SHRD32mrCL, 0 },
249 { X86::SHRD32rri8, X86::SHRD32mri8, 0 },
250 { X86::SHRD64rrCL, X86::SHRD64mrCL, 0 },
251 { X86::SHRD64rri8, X86::SHRD64mri8, 0 },
252 { X86::SUB16ri, X86::SUB16mi, 0 },
253 { X86::SUB16ri8, X86::SUB16mi8, 0 },
254 { X86::SUB16rr, X86::SUB16mr, 0 },
255 { X86::SUB32ri, X86::SUB32mi, 0 },
256 { X86::SUB32ri8, X86::SUB32mi8, 0 },
257 { X86::SUB32rr, X86::SUB32mr, 0 },
258 { X86::SUB64ri32, X86::SUB64mi32, 0 },
259 { X86::SUB64ri8, X86::SUB64mi8, 0 },
260 { X86::SUB64rr, X86::SUB64mr, 0 },
261 { X86::SUB8ri, X86::SUB8mi, 0 },
262 { X86::SUB8rr, X86::SUB8mr, 0 },
263 { X86::XOR16ri, X86::XOR16mi, 0 },
264 { X86::XOR16ri8, X86::XOR16mi8, 0 },
265 { X86::XOR16rr, X86::XOR16mr, 0 },
266 { X86::XOR32ri, X86::XOR32mi, 0 },
267 { X86::XOR32ri8, X86::XOR32mi8, 0 },
268 { X86::XOR32rr, X86::XOR32mr, 0 },
269 { X86::XOR64ri32, X86::XOR64mi32, 0 },
270 { X86::XOR64ri8, X86::XOR64mi8, 0 },
271 { X86::XOR64rr, X86::XOR64mr, 0 },
272 { X86::XOR8ri, X86::XOR8mi, 0 },
273 { X86::XOR8rr, X86::XOR8mr, 0 }
274 };
276 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
277 unsigned RegOp = OpTbl2Addr[i].RegOp;
278 unsigned MemOp = OpTbl2Addr[i].MemOp;
279 unsigned Flags = OpTbl2Addr[i].Flags;
280 AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
281 RegOp, MemOp,
282 // Index 0, folded load and store, no alignment requirement.
283 Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
284 }
286 static const X86OpTblEntry OpTbl0[] = {
287 { X86::BT16ri8, X86::BT16mi8, TB_FOLDED_LOAD },
288 { X86::BT32ri8, X86::BT32mi8, TB_FOLDED_LOAD },
289 { X86::BT64ri8, X86::BT64mi8, TB_FOLDED_LOAD },
290 { X86::CALL32r, X86::CALL32m, TB_FOLDED_LOAD },
291 { X86::CALL64r, X86::CALL64m, TB_FOLDED_LOAD },
292 { X86::CMP16ri, X86::CMP16mi, TB_FOLDED_LOAD },
293 { X86::CMP16ri8, X86::CMP16mi8, TB_FOLDED_LOAD },
294 { X86::CMP16rr, X86::CMP16mr, TB_FOLDED_LOAD },
295 { X86::CMP32ri, X86::CMP32mi, TB_FOLDED_LOAD },
296 { X86::CMP32ri8, X86::CMP32mi8, TB_FOLDED_LOAD },
297 { X86::CMP32rr, X86::CMP32mr, TB_FOLDED_LOAD },
298 { X86::CMP64ri32, X86::CMP64mi32, TB_FOLDED_LOAD },
299 { X86::CMP64ri8, X86::CMP64mi8, TB_FOLDED_LOAD },
300 { X86::CMP64rr, X86::CMP64mr, TB_FOLDED_LOAD },
301 { X86::CMP8ri, X86::CMP8mi, TB_FOLDED_LOAD },
302 { X86::CMP8rr, X86::CMP8mr, TB_FOLDED_LOAD },
303 { X86::DIV16r, X86::DIV16m, TB_FOLDED_LOAD },
304 { X86::DIV32r, X86::DIV32m, TB_FOLDED_LOAD },
305 { X86::DIV64r, X86::DIV64m, TB_FOLDED_LOAD },
306 { X86::DIV8r, X86::DIV8m, TB_FOLDED_LOAD },
307 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, TB_FOLDED_STORE },
308 { X86::IDIV16r, X86::IDIV16m, TB_FOLDED_LOAD },
309 { X86::IDIV32r, X86::IDIV32m, TB_FOLDED_LOAD },
310 { X86::IDIV64r, X86::IDIV64m, TB_FOLDED_LOAD },
311 { X86::IDIV8r, X86::IDIV8m, TB_FOLDED_LOAD },
312 { X86::IMUL16r, X86::IMUL16m, TB_FOLDED_LOAD },
313 { X86::IMUL32r, X86::IMUL32m, TB_FOLDED_LOAD },
314 { X86::IMUL64r, X86::IMUL64m, TB_FOLDED_LOAD },
315 { X86::IMUL8r, X86::IMUL8m, TB_FOLDED_LOAD },
316 { X86::JMP32r, X86::JMP32m, TB_FOLDED_LOAD },
317 { X86::JMP64r, X86::JMP64m, TB_FOLDED_LOAD },
318 { X86::MOV16ri, X86::MOV16mi, TB_FOLDED_STORE },
319 { X86::MOV16rr, X86::MOV16mr, TB_FOLDED_STORE },
320 { X86::MOV32ri, X86::MOV32mi, TB_FOLDED_STORE },
321 { X86::MOV32rr, X86::MOV32mr, TB_FOLDED_STORE },
322 { X86::MOV64ri32, X86::MOV64mi32, TB_FOLDED_STORE },
323 { X86::MOV64rr, X86::MOV64mr, TB_FOLDED_STORE },
324 { X86::MOV8ri, X86::MOV8mi, TB_FOLDED_STORE },
325 { X86::MOV8rr, X86::MOV8mr, TB_FOLDED_STORE },
326 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
327 { X86::MOVAPDrr, X86::MOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
328 { X86::MOVAPSrr, X86::MOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
329 { X86::MOVDQArr, X86::MOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
330 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, TB_FOLDED_STORE },
331 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, TB_FOLDED_STORE },
332 { X86::MOVSDto64rr, X86::MOVSDto64mr, TB_FOLDED_STORE },
333 { X86::MOVSS2DIrr, X86::MOVSS2DImr, TB_FOLDED_STORE },
334 { X86::MOVUPDrr, X86::MOVUPDmr, TB_FOLDED_STORE },
335 { X86::MOVUPSrr, X86::MOVUPSmr, TB_FOLDED_STORE },
336 { X86::MUL16r, X86::MUL16m, TB_FOLDED_LOAD },
337 { X86::MUL32r, X86::MUL32m, TB_FOLDED_LOAD },
338 { X86::MUL64r, X86::MUL64m, TB_FOLDED_LOAD },
339 { X86::MUL8r, X86::MUL8m, TB_FOLDED_LOAD },
340 { X86::SETAEr, X86::SETAEm, TB_FOLDED_STORE },
341 { X86::SETAr, X86::SETAm, TB_FOLDED_STORE },
342 { X86::SETBEr, X86::SETBEm, TB_FOLDED_STORE },
343 { X86::SETBr, X86::SETBm, TB_FOLDED_STORE },
344 { X86::SETEr, X86::SETEm, TB_FOLDED_STORE },
345 { X86::SETGEr, X86::SETGEm, TB_FOLDED_STORE },
346 { X86::SETGr, X86::SETGm, TB_FOLDED_STORE },
347 { X86::SETLEr, X86::SETLEm, TB_FOLDED_STORE },
348 { X86::SETLr, X86::SETLm, TB_FOLDED_STORE },
349 { X86::SETNEr, X86::SETNEm, TB_FOLDED_STORE },
350 { X86::SETNOr, X86::SETNOm, TB_FOLDED_STORE },
351 { X86::SETNPr, X86::SETNPm, TB_FOLDED_STORE },
352 { X86::SETNSr, X86::SETNSm, TB_FOLDED_STORE },
353 { X86::SETOr, X86::SETOm, TB_FOLDED_STORE },
354 { X86::SETPr, X86::SETPm, TB_FOLDED_STORE },
355 { X86::SETSr, X86::SETSm, TB_FOLDED_STORE },
356 { X86::TAILJMPr, X86::TAILJMPm, TB_FOLDED_LOAD },
357 { X86::TAILJMPr64, X86::TAILJMPm64, TB_FOLDED_LOAD },
358 { X86::TEST16ri, X86::TEST16mi, TB_FOLDED_LOAD },
359 { X86::TEST32ri, X86::TEST32mi, TB_FOLDED_LOAD },
360 { X86::TEST64ri32, X86::TEST64mi32, TB_FOLDED_LOAD },
361 { X86::TEST8ri, X86::TEST8mi, TB_FOLDED_LOAD },
362 // AVX 128-bit versions of foldable instructions
363 { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr, TB_FOLDED_STORE },
364 { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
365 { X86::VMOVAPDrr, X86::VMOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
366 { X86::VMOVAPSrr, X86::VMOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
367 { X86::VMOVDQArr, X86::VMOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
368 { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr, TB_FOLDED_STORE },
369 { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
370 { X86::VMOVSDto64rr,X86::VMOVSDto64mr, TB_FOLDED_STORE },
371 { X86::VMOVSS2DIrr, X86::VMOVSS2DImr, TB_FOLDED_STORE },
372 { X86::VMOVUPDrr, X86::VMOVUPDmr, TB_FOLDED_STORE },
373 { X86::VMOVUPSrr, X86::VMOVUPSmr, TB_FOLDED_STORE },
374 // AVX 256-bit foldable instructions
375 { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
376 { X86::VMOVAPDYrr, X86::VMOVAPDYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
377 { X86::VMOVAPSYrr, X86::VMOVAPSYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
378 { X86::VMOVDQAYrr, X86::VMOVDQAYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
379 { X86::VMOVUPDYrr, X86::VMOVUPDYmr, TB_FOLDED_STORE },
380 { X86::VMOVUPSYrr, X86::VMOVUPSYmr, TB_FOLDED_STORE },
381 // AVX-512 foldable instructions
382 { X86::VMOVPDI2DIZrr, X86::VMOVPDI2DIZmr, TB_FOLDED_STORE },
383 { X86::VMOVAPDZrr, X86::VMOVAPDZmr, TB_FOLDED_STORE | TB_ALIGN_64 },
384 { X86::VMOVAPSZrr, X86::VMOVAPSZmr, TB_FOLDED_STORE | TB_ALIGN_64 },
385 { X86::VMOVDQA32Zrr, X86::VMOVDQA32Zmr, TB_FOLDED_STORE | TB_ALIGN_64 },
386 { X86::VMOVDQA64Zrr, X86::VMOVDQA64Zmr, TB_FOLDED_STORE | TB_ALIGN_64 },
387 { X86::VMOVUPDZrr, X86::VMOVUPDZmr, TB_FOLDED_STORE },
388 { X86::VMOVUPSZrr, X86::VMOVUPSZmr, TB_FOLDED_STORE },
389 { X86::VMOVDQU8Zrr, X86::VMOVDQU8Zmr, TB_FOLDED_STORE },
390 { X86::VMOVDQU16Zrr, X86::VMOVDQU16Zmr, TB_FOLDED_STORE },
391 { X86::VMOVDQU32Zrr, X86::VMOVDQU32Zmr, TB_FOLDED_STORE },
392 { X86::VMOVDQU64Zrr, X86::VMOVDQU64Zmr, TB_FOLDED_STORE },
393 // AVX-512 foldable instructions (256-bit versions)
394 { X86::VMOVAPDZ256rr, X86::VMOVAPDZ256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
395 { X86::VMOVAPSZ256rr, X86::VMOVAPSZ256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
396 { X86::VMOVDQA32Z256rr, X86::VMOVDQA32Z256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
397 { X86::VMOVDQA64Z256rr, X86::VMOVDQA64Z256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
398 { X86::VMOVUPDZ256rr, X86::VMOVUPDZ256mr, TB_FOLDED_STORE },
399 { X86::VMOVUPSZ256rr, X86::VMOVUPSZ256mr, TB_FOLDED_STORE },
400 { X86::VMOVDQU8Z256rr, X86::VMOVDQU8Z256mr, TB_FOLDED_STORE },
401 { X86::VMOVDQU16Z256rr, X86::VMOVDQU16Z256mr, TB_FOLDED_STORE },
402 { X86::VMOVDQU32Z256rr, X86::VMOVDQU32Z256mr, TB_FOLDED_STORE },
403 { X86::VMOVDQU64Z256rr, X86::VMOVDQU64Z256mr, TB_FOLDED_STORE },
404 // AVX-512 foldable instructions (128-bit versions)
405 { X86::VMOVAPDZ128rr, X86::VMOVAPDZ128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
406 { X86::VMOVAPSZ128rr, X86::VMOVAPSZ128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
407 { X86::VMOVDQA32Z128rr, X86::VMOVDQA32Z128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
408 { X86::VMOVDQA64Z128rr, X86::VMOVDQA64Z128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
409 { X86::VMOVUPDZ128rr, X86::VMOVUPDZ128mr, TB_FOLDED_STORE },
410 { X86::VMOVUPSZ128rr, X86::VMOVUPSZ128mr, TB_FOLDED_STORE },
411 { X86::VMOVDQU8Z128rr, X86::VMOVDQU8Z128mr, TB_FOLDED_STORE },
412 { X86::VMOVDQU16Z128rr, X86::VMOVDQU16Z128mr, TB_FOLDED_STORE },
413 { X86::VMOVDQU32Z128rr, X86::VMOVDQU32Z128mr, TB_FOLDED_STORE },
414 { X86::VMOVDQU64Z128rr, X86::VMOVDQU64Z128mr, TB_FOLDED_STORE }
415 };
417 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
418 unsigned RegOp = OpTbl0[i].RegOp;
419 unsigned MemOp = OpTbl0[i].MemOp;
420 unsigned Flags = OpTbl0[i].Flags;
421 AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
422 RegOp, MemOp, TB_INDEX_0 | Flags);
423 }
425 static const X86OpTblEntry OpTbl1[] = {
426 { X86::CMP16rr, X86::CMP16rm, 0 },
427 { X86::CMP32rr, X86::CMP32rm, 0 },
428 { X86::CMP64rr, X86::CMP64rm, 0 },
429 { X86::CMP8rr, X86::CMP8rm, 0 },
430 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 },
431 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 },
432 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 },
433 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 },
434 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 },
435 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 },
436 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 },
437 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 },
438 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 },
439 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 },
440 { X86::IMUL16rri, X86::IMUL16rmi, 0 },
441 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 },
442 { X86::IMUL32rri, X86::IMUL32rmi, 0 },
443 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 },
444 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 },
445 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
446 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 },
447 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 },
448 { X86::CVTSD2SI64rr, X86::CVTSD2SI64rm, 0 },
449 { X86::CVTSD2SIrr, X86::CVTSD2SIrm, 0 },
450 { X86::CVTSS2SI64rr, X86::CVTSS2SI64rm, 0 },
451 { X86::CVTSS2SIrr, X86::CVTSS2SIrm, 0 },
452 { X86::CVTDQ2PSrr, X86::CVTDQ2PSrm, TB_ALIGN_16 },
453 { X86::CVTPD2DQrr, X86::CVTPD2DQrm, TB_ALIGN_16 },
454 { X86::CVTPD2PSrr, X86::CVTPD2PSrm, TB_ALIGN_16 },
455 { X86::CVTPS2DQrr, X86::CVTPS2DQrm, TB_ALIGN_16 },
456 { X86::CVTTPD2DQrr, X86::CVTTPD2DQrm, TB_ALIGN_16 },
457 { X86::CVTTPS2DQrr, X86::CVTTPS2DQrm, TB_ALIGN_16 },
458 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 },
459 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 },
460 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 },
461 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 },
462 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 },
463 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 },
464 { X86::MOV16rr, X86::MOV16rm, 0 },
465 { X86::MOV32rr, X86::MOV32rm, 0 },
466 { X86::MOV64rr, X86::MOV64rm, 0 },
467 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 },
468 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 },
469 { X86::MOV8rr, X86::MOV8rm, 0 },
470 { X86::MOVAPDrr, X86::MOVAPDrm, TB_ALIGN_16 },
471 { X86::MOVAPSrr, X86::MOVAPSrm, TB_ALIGN_16 },
472 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 },
473 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 },
474 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 },
475 { X86::MOVDQArr, X86::MOVDQArm, TB_ALIGN_16 },
476 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, TB_ALIGN_16 },
477 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, TB_ALIGN_16 },
478 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 },
479 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 },
480 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 },
481 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 },
482 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 },
483 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 },
484 { X86::MOVUPDrr, X86::MOVUPDrm, TB_ALIGN_16 },
485 { X86::MOVUPSrr, X86::MOVUPSrm, 0 },
486 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 },
487 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, TB_ALIGN_16 },
488 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 },
489 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 },
490 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
491 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 },
492 { X86::PABSBrr128, X86::PABSBrm128, TB_ALIGN_16 },
493 { X86::PABSDrr128, X86::PABSDrm128, TB_ALIGN_16 },
494 { X86::PABSWrr128, X86::PABSWrm128, TB_ALIGN_16 },
495 { X86::PSHUFDri, X86::PSHUFDmi, TB_ALIGN_16 },
496 { X86::PSHUFHWri, X86::PSHUFHWmi, TB_ALIGN_16 },
497 { X86::PSHUFLWri, X86::PSHUFLWmi, TB_ALIGN_16 },
498 { X86::RCPPSr, X86::RCPPSm, TB_ALIGN_16 },
499 { X86::RCPPSr_Int, X86::RCPPSm_Int, TB_ALIGN_16 },
500 { X86::RSQRTPSr, X86::RSQRTPSm, TB_ALIGN_16 },
501 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int, TB_ALIGN_16 },
502 { X86::RSQRTSSr, X86::RSQRTSSm, 0 },
503 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 },
504 { X86::SQRTPDr, X86::SQRTPDm, TB_ALIGN_16 },
505 { X86::SQRTPSr, X86::SQRTPSm, TB_ALIGN_16 },
506 { X86::SQRTSDr, X86::SQRTSDm, 0 },
507 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 },
508 { X86::SQRTSSr, X86::SQRTSSm, 0 },
509 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 },
510 { X86::TEST16rr, X86::TEST16rm, 0 },
511 { X86::TEST32rr, X86::TEST32rm, 0 },
512 { X86::TEST64rr, X86::TEST64rm, 0 },
513 { X86::TEST8rr, X86::TEST8rm, 0 },
514 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
515 { X86::UCOMISDrr, X86::UCOMISDrm, 0 },
516 { X86::UCOMISSrr, X86::UCOMISSrm, 0 },
517 // AVX 128-bit versions of foldable instructions
518 { X86::Int_VCOMISDrr, X86::Int_VCOMISDrm, 0 },
519 { X86::Int_VCOMISSrr, X86::Int_VCOMISSrm, 0 },
520 { X86::Int_VUCOMISDrr, X86::Int_VUCOMISDrm, 0 },
521 { X86::Int_VUCOMISSrr, X86::Int_VUCOMISSrm, 0 },
522 { X86::VCVTTSD2SI64rr, X86::VCVTTSD2SI64rm, 0 },
523 { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 },
524 { X86::VCVTTSD2SIrr, X86::VCVTTSD2SIrm, 0 },
525 { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm, 0 },
526 { X86::VCVTTSS2SI64rr, X86::VCVTTSS2SI64rm, 0 },
527 { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 },
528 { X86::VCVTTSS2SIrr, X86::VCVTTSS2SIrm, 0 },
529 { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm, 0 },
530 { X86::VCVTSD2SI64rr, X86::VCVTSD2SI64rm, 0 },
531 { X86::VCVTSD2SIrr, X86::VCVTSD2SIrm, 0 },
532 { X86::VCVTSS2SI64rr, X86::VCVTSS2SI64rm, 0 },
533 { X86::VCVTSS2SIrr, X86::VCVTSS2SIrm, 0 },
534 { X86::VCVTDQ2PSrr, X86::VCVTDQ2PSrm, 0 },
535 { X86::VCVTPD2DQrr, X86::VCVTPD2DQXrm, 0 },
536 { X86::VCVTPD2PSrr, X86::VCVTPD2PSXrm, 0 },
537 { X86::VCVTPS2DQrr, X86::VCVTPS2DQrm, 0 },
538 { X86::VCVTTPD2DQrr, X86::VCVTTPD2DQXrm, 0 },
539 { X86::VCVTTPS2DQrr, X86::VCVTTPS2DQrm, 0 },
540 { X86::VMOV64toPQIrr, X86::VMOVQI2PQIrm, 0 },
541 { X86::VMOV64toSDrr, X86::VMOV64toSDrm, 0 },
542 { X86::VMOVAPDrr, X86::VMOVAPDrm, TB_ALIGN_16 },
543 { X86::VMOVAPSrr, X86::VMOVAPSrm, TB_ALIGN_16 },
544 { X86::VMOVDDUPrr, X86::VMOVDDUPrm, 0 },
545 { X86::VMOVDI2PDIrr, X86::VMOVDI2PDIrm, 0 },
546 { X86::VMOVDI2SSrr, X86::VMOVDI2SSrm, 0 },
547 { X86::VMOVDQArr, X86::VMOVDQArm, TB_ALIGN_16 },
548 { X86::VMOVSLDUPrr, X86::VMOVSLDUPrm, TB_ALIGN_16 },
549 { X86::VMOVSHDUPrr, X86::VMOVSHDUPrm, TB_ALIGN_16 },
550 { X86::VMOVUPDrr, X86::VMOVUPDrm, 0 },
551 { X86::VMOVUPSrr, X86::VMOVUPSrm, 0 },
552 { X86::VMOVZQI2PQIrr, X86::VMOVZQI2PQIrm, 0 },
553 { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm, TB_ALIGN_16 },
554 { X86::VPABSBrr128, X86::VPABSBrm128, 0 },
555 { X86::VPABSDrr128, X86::VPABSDrm128, 0 },
556 { X86::VPABSWrr128, X86::VPABSWrm128, 0 },
557 { X86::VPERMILPDri, X86::VPERMILPDmi, 0 },
558 { X86::VPERMILPSri, X86::VPERMILPSmi, 0 },
559 { X86::VPSHUFDri, X86::VPSHUFDmi, 0 },
560 { X86::VPSHUFHWri, X86::VPSHUFHWmi, 0 },
561 { X86::VPSHUFLWri, X86::VPSHUFLWmi, 0 },
562 { X86::VRCPPSr, X86::VRCPPSm, 0 },
563 { X86::VRCPPSr_Int, X86::VRCPPSm_Int, 0 },
564 { X86::VRSQRTPSr, X86::VRSQRTPSm, 0 },
565 { X86::VRSQRTPSr_Int, X86::VRSQRTPSm_Int, 0 },
566 { X86::VSQRTPDr, X86::VSQRTPDm, 0 },
567 { X86::VSQRTPSr, X86::VSQRTPSm, 0 },
568 { X86::VUCOMISDrr, X86::VUCOMISDrm, 0 },
569 { X86::VUCOMISSrr, X86::VUCOMISSrm, 0 },
570 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrm, TB_NO_REVERSE },
572 // AVX 256-bit foldable instructions
573 { X86::VCVTDQ2PSYrr, X86::VCVTDQ2PSYrm, 0 },
574 { X86::VCVTPD2DQYrr, X86::VCVTPD2DQYrm, 0 },
575 { X86::VCVTPD2PSYrr, X86::VCVTPD2PSYrm, 0 },
576 { X86::VCVTPS2DQYrr, X86::VCVTPS2DQYrm, 0 },
577 { X86::VCVTTPD2DQYrr, X86::VCVTTPD2DQYrm, 0 },
578 { X86::VCVTTPS2DQYrr, X86::VCVTTPS2DQYrm, 0 },
579 { X86::VMOVAPDYrr, X86::VMOVAPDYrm, TB_ALIGN_32 },
580 { X86::VMOVAPSYrr, X86::VMOVAPSYrm, TB_ALIGN_32 },
581 { X86::VMOVDQAYrr, X86::VMOVDQAYrm, TB_ALIGN_32 },
582 { X86::VMOVUPDYrr, X86::VMOVUPDYrm, 0 },
583 { X86::VMOVUPSYrr, X86::VMOVUPSYrm, 0 },
584 { X86::VPERMILPDYri, X86::VPERMILPDYmi, 0 },
585 { X86::VPERMILPSYri, X86::VPERMILPSYmi, 0 },
586 { X86::VRCPPSYr, X86::VRCPPSYm, 0 },
587 { X86::VRCPPSYr_Int, X86::VRCPPSYm_Int, 0 },
588 { X86::VRSQRTPSYr, X86::VRSQRTPSYm, 0 },
589 { X86::VSQRTPDYr, X86::VSQRTPDYm, 0 },
590 { X86::VSQRTPSYr, X86::VSQRTPSYm, 0 },
591 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm, TB_NO_REVERSE },
592 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm, TB_NO_REVERSE },
594 // AVX2 foldable instructions
595 { X86::VPABSBrr256, X86::VPABSBrm256, 0 },
596 { X86::VPABSDrr256, X86::VPABSDrm256, 0 },
597 { X86::VPABSWrr256, X86::VPABSWrm256, 0 },
598 { X86::VPSHUFDYri, X86::VPSHUFDYmi, 0 },
599 { X86::VPSHUFHWYri, X86::VPSHUFHWYmi, 0 },
600 { X86::VPSHUFLWYri, X86::VPSHUFLWYmi, 0 },
602 // BMI/BMI2/LZCNT/POPCNT/TBM foldable instructions
603 { X86::BEXTR32rr, X86::BEXTR32rm, 0 },
604 { X86::BEXTR64rr, X86::BEXTR64rm, 0 },
605 { X86::BEXTRI32ri, X86::BEXTRI32mi, 0 },
606 { X86::BEXTRI64ri, X86::BEXTRI64mi, 0 },
607 { X86::BLCFILL32rr, X86::BLCFILL32rm, 0 },
608 { X86::BLCFILL64rr, X86::BLCFILL64rm, 0 },
609 { X86::BLCI32rr, X86::BLCI32rm, 0 },
610 { X86::BLCI64rr, X86::BLCI64rm, 0 },
611 { X86::BLCIC32rr, X86::BLCIC32rm, 0 },
612 { X86::BLCIC64rr, X86::BLCIC64rm, 0 },
613 { X86::BLCMSK32rr, X86::BLCMSK32rm, 0 },
614 { X86::BLCMSK64rr, X86::BLCMSK64rm, 0 },
615 { X86::BLCS32rr, X86::BLCS32rm, 0 },
616 { X86::BLCS64rr, X86::BLCS64rm, 0 },
617 { X86::BLSFILL32rr, X86::BLSFILL32rm, 0 },
618 { X86::BLSFILL64rr, X86::BLSFILL64rm, 0 },
619 { X86::BLSI32rr, X86::BLSI32rm, 0 },
620 { X86::BLSI64rr, X86::BLSI64rm, 0 },
621 { X86::BLSIC32rr, X86::BLSIC32rm, 0 },
622 { X86::BLSIC64rr, X86::BLSIC64rm, 0 },
623 { X86::BLSMSK32rr, X86::BLSMSK32rm, 0 },
624 { X86::BLSMSK64rr, X86::BLSMSK64rm, 0 },
625 { X86::BLSR32rr, X86::BLSR32rm, 0 },
626 { X86::BLSR64rr, X86::BLSR64rm, 0 },
627 { X86::BZHI32rr, X86::BZHI32rm, 0 },
628 { X86::BZHI64rr, X86::BZHI64rm, 0 },
629 { X86::LZCNT16rr, X86::LZCNT16rm, 0 },
630 { X86::LZCNT32rr, X86::LZCNT32rm, 0 },
631 { X86::LZCNT64rr, X86::LZCNT64rm, 0 },
632 { X86::POPCNT16rr, X86::POPCNT16rm, 0 },
633 { X86::POPCNT32rr, X86::POPCNT32rm, 0 },
634 { X86::POPCNT64rr, X86::POPCNT64rm, 0 },
635 { X86::RORX32ri, X86::RORX32mi, 0 },
636 { X86::RORX64ri, X86::RORX64mi, 0 },
637 { X86::SARX32rr, X86::SARX32rm, 0 },
638 { X86::SARX64rr, X86::SARX64rm, 0 },
639 { X86::SHRX32rr, X86::SHRX32rm, 0 },
640 { X86::SHRX64rr, X86::SHRX64rm, 0 },
641 { X86::SHLX32rr, X86::SHLX32rm, 0 },
642 { X86::SHLX64rr, X86::SHLX64rm, 0 },
643 { X86::T1MSKC32rr, X86::T1MSKC32rm, 0 },
644 { X86::T1MSKC64rr, X86::T1MSKC64rm, 0 },
645 { X86::TZCNT16rr, X86::TZCNT16rm, 0 },
646 { X86::TZCNT32rr, X86::TZCNT32rm, 0 },
647 { X86::TZCNT64rr, X86::TZCNT64rm, 0 },
648 { X86::TZMSK32rr, X86::TZMSK32rm, 0 },
649 { X86::TZMSK64rr, X86::TZMSK64rm, 0 },
651 // AVX-512 foldable instructions
652 { X86::VMOV64toPQIZrr, X86::VMOVQI2PQIZrm, 0 },
653 { X86::VMOVDI2SSZrr, X86::VMOVDI2SSZrm, 0 },
654 { X86::VMOVAPDZrr, X86::VMOVAPDZrm, TB_ALIGN_64 },
655 { X86::VMOVAPSZrr, X86::VMOVAPSZrm, TB_ALIGN_64 },
656 { X86::VMOVDQA32Zrr, X86::VMOVDQA32Zrm, TB_ALIGN_64 },
657 { X86::VMOVDQA64Zrr, X86::VMOVDQA64Zrm, TB_ALIGN_64 },
658 { X86::VMOVDQU8Zrr, X86::VMOVDQU8Zrm, 0 },
659 { X86::VMOVDQU16Zrr, X86::VMOVDQU16Zrm, 0 },
660 { X86::VMOVDQU32Zrr, X86::VMOVDQU32Zrm, 0 },
661 { X86::VMOVDQU64Zrr, X86::VMOVDQU64Zrm, 0 },
662 { X86::VMOVUPDZrr, X86::VMOVUPDZrm, 0 },
663 { X86::VMOVUPSZrr, X86::VMOVUPSZrm, 0 },
664 { X86::VPABSDZrr, X86::VPABSDZrm, 0 },
665 { X86::VPABSQZrr, X86::VPABSQZrm, 0 },
666 { X86::VBROADCASTSSZr, X86::VBROADCASTSSZm, TB_NO_REVERSE },
667 { X86::VBROADCASTSDZr, X86::VBROADCASTSDZm, TB_NO_REVERSE },
668 // AVX-512 foldable instructions (256-bit versions)
669 { X86::VMOVAPDZ256rr, X86::VMOVAPDZ256rm, TB_ALIGN_32 },
670 { X86::VMOVAPSZ256rr, X86::VMOVAPSZ256rm, TB_ALIGN_32 },
671 { X86::VMOVDQA32Z256rr, X86::VMOVDQA32Z256rm, TB_ALIGN_32 },
672 { X86::VMOVDQA64Z256rr, X86::VMOVDQA64Z256rm, TB_ALIGN_32 },
673 { X86::VMOVDQU8Z256rr, X86::VMOVDQU8Z256rm, 0 },
674 { X86::VMOVDQU16Z256rr, X86::VMOVDQU16Z256rm, 0 },
675 { X86::VMOVDQU32Z256rr, X86::VMOVDQU32Z256rm, 0 },
676 { X86::VMOVDQU64Z256rr, X86::VMOVDQU64Z256rm, 0 },
677 { X86::VMOVUPDZ256rr, X86::VMOVUPDZ256rm, 0 },
678 { X86::VMOVUPSZ256rr, X86::VMOVUPSZ256rm, 0 },
679 { X86::VBROADCASTSSZ256r, X86::VBROADCASTSSZ256m, TB_NO_REVERSE },
680 { X86::VBROADCASTSDZ256r, X86::VBROADCASTSDZ256m, TB_NO_REVERSE },
681 // AVX-512 foldable instructions (256-bit versions)
682 { X86::VMOVAPDZ128rr, X86::VMOVAPDZ128rm, TB_ALIGN_16 },
683 { X86::VMOVAPSZ128rr, X86::VMOVAPSZ128rm, TB_ALIGN_16 },
684 { X86::VMOVDQA32Z128rr, X86::VMOVDQA32Z128rm, TB_ALIGN_16 },
685 { X86::VMOVDQA64Z128rr, X86::VMOVDQA64Z128rm, TB_ALIGN_16 },
686 { X86::VMOVDQU8Z128rr, X86::VMOVDQU8Z128rm, 0 },
687 { X86::VMOVDQU16Z128rr, X86::VMOVDQU16Z128rm, 0 },
688 { X86::VMOVDQU32Z128rr, X86::VMOVDQU32Z128rm, 0 },
689 { X86::VMOVDQU64Z128rr, X86::VMOVDQU64Z128rm, 0 },
690 { X86::VMOVUPDZ128rr, X86::VMOVUPDZ128rm, 0 },
691 { X86::VMOVUPSZ128rr, X86::VMOVUPSZ128rm, 0 },
692 { X86::VBROADCASTSSZ128r, X86::VBROADCASTSSZ128m, TB_NO_REVERSE },
694 // AES foldable instructions
695 { X86::AESIMCrr, X86::AESIMCrm, TB_ALIGN_16 },
696 { X86::AESKEYGENASSIST128rr, X86::AESKEYGENASSIST128rm, TB_ALIGN_16 },
697 { X86::VAESIMCrr, X86::VAESIMCrm, TB_ALIGN_16 },
698 { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, TB_ALIGN_16 }
699 };
701 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
702 unsigned RegOp = OpTbl1[i].RegOp;
703 unsigned MemOp = OpTbl1[i].MemOp;
704 unsigned Flags = OpTbl1[i].Flags;
705 AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
706 RegOp, MemOp,
707 // Index 1, folded load
708 Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
709 }
711 static const X86OpTblEntry OpTbl2[] = {
712 { X86::ADC32rr, X86::ADC32rm, 0 },
713 { X86::ADC64rr, X86::ADC64rm, 0 },
714 { X86::ADD16rr, X86::ADD16rm, 0 },
715 { X86::ADD16rr_DB, X86::ADD16rm, TB_NO_REVERSE },
716 { X86::ADD32rr, X86::ADD32rm, 0 },
717 { X86::ADD32rr_DB, X86::ADD32rm, TB_NO_REVERSE },
718 { X86::ADD64rr, X86::ADD64rm, 0 },
719 { X86::ADD64rr_DB, X86::ADD64rm, TB_NO_REVERSE },
720 { X86::ADD8rr, X86::ADD8rm, 0 },
721 { X86::ADDPDrr, X86::ADDPDrm, TB_ALIGN_16 },
722 { X86::ADDPSrr, X86::ADDPSrm, TB_ALIGN_16 },
723 { X86::ADDSDrr, X86::ADDSDrm, 0 },
724 { X86::ADDSSrr, X86::ADDSSrm, 0 },
725 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, TB_ALIGN_16 },
726 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, TB_ALIGN_16 },
727 { X86::AND16rr, X86::AND16rm, 0 },
728 { X86::AND32rr, X86::AND32rm, 0 },
729 { X86::AND64rr, X86::AND64rm, 0 },
730 { X86::AND8rr, X86::AND8rm, 0 },
731 { X86::ANDNPDrr, X86::ANDNPDrm, TB_ALIGN_16 },
732 { X86::ANDNPSrr, X86::ANDNPSrm, TB_ALIGN_16 },
733 { X86::ANDPDrr, X86::ANDPDrm, TB_ALIGN_16 },
734 { X86::ANDPSrr, X86::ANDPSrm, TB_ALIGN_16 },
735 { X86::BLENDPDrri, X86::BLENDPDrmi, TB_ALIGN_16 },
736 { X86::BLENDPSrri, X86::BLENDPSrmi, TB_ALIGN_16 },
737 { X86::BLENDVPDrr0, X86::BLENDVPDrm0, TB_ALIGN_16 },
738 { X86::BLENDVPSrr0, X86::BLENDVPSrm0, TB_ALIGN_16 },
739 { X86::CMOVA16rr, X86::CMOVA16rm, 0 },
740 { X86::CMOVA32rr, X86::CMOVA32rm, 0 },
741 { X86::CMOVA64rr, X86::CMOVA64rm, 0 },
742 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 },
743 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 },
744 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 },
745 { X86::CMOVB16rr, X86::CMOVB16rm, 0 },
746 { X86::CMOVB32rr, X86::CMOVB32rm, 0 },
747 { X86::CMOVB64rr, X86::CMOVB64rm, 0 },
748 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
749 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
750 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
751 { X86::CMOVE16rr, X86::CMOVE16rm, 0 },
752 { X86::CMOVE32rr, X86::CMOVE32rm, 0 },
753 { X86::CMOVE64rr, X86::CMOVE64rm, 0 },
754 { X86::CMOVG16rr, X86::CMOVG16rm, 0 },
755 { X86::CMOVG32rr, X86::CMOVG32rm, 0 },
756 { X86::CMOVG64rr, X86::CMOVG64rm, 0 },
757 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 },
758 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 },
759 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 },
760 { X86::CMOVL16rr, X86::CMOVL16rm, 0 },
761 { X86::CMOVL32rr, X86::CMOVL32rm, 0 },
762 { X86::CMOVL64rr, X86::CMOVL64rm, 0 },
763 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 },
764 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 },
765 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 },
766 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 },
767 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 },
768 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 },
769 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 },
770 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 },
771 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 },
772 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 },
773 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 },
774 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 },
775 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 },
776 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 },
777 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 },
778 { X86::CMOVO16rr, X86::CMOVO16rm, 0 },
779 { X86::CMOVO32rr, X86::CMOVO32rm, 0 },
780 { X86::CMOVO64rr, X86::CMOVO64rm, 0 },
781 { X86::CMOVP16rr, X86::CMOVP16rm, 0 },
782 { X86::CMOVP32rr, X86::CMOVP32rm, 0 },
783 { X86::CMOVP64rr, X86::CMOVP64rm, 0 },
784 { X86::CMOVS16rr, X86::CMOVS16rm, 0 },
785 { X86::CMOVS32rr, X86::CMOVS32rm, 0 },
786 { X86::CMOVS64rr, X86::CMOVS64rm, 0 },
787 { X86::CMPPDrri, X86::CMPPDrmi, TB_ALIGN_16 },
788 { X86::CMPPSrri, X86::CMPPSrmi, TB_ALIGN_16 },
789 { X86::CMPSDrr, X86::CMPSDrm, 0 },
790 { X86::CMPSSrr, X86::CMPSSrm, 0 },
791 { X86::DIVPDrr, X86::DIVPDrm, TB_ALIGN_16 },
792 { X86::DIVPSrr, X86::DIVPSrm, TB_ALIGN_16 },
793 { X86::DIVSDrr, X86::DIVSDrm, 0 },
794 { X86::DIVSSrr, X86::DIVSSrm, 0 },
795 { X86::FsANDNPDrr, X86::FsANDNPDrm, TB_ALIGN_16 },
796 { X86::FsANDNPSrr, X86::FsANDNPSrm, TB_ALIGN_16 },
797 { X86::FsANDPDrr, X86::FsANDPDrm, TB_ALIGN_16 },
798 { X86::FsANDPSrr, X86::FsANDPSrm, TB_ALIGN_16 },
799 { X86::FsORPDrr, X86::FsORPDrm, TB_ALIGN_16 },
800 { X86::FsORPSrr, X86::FsORPSrm, TB_ALIGN_16 },
801 { X86::FsXORPDrr, X86::FsXORPDrm, TB_ALIGN_16 },
802 { X86::FsXORPSrr, X86::FsXORPSrm, TB_ALIGN_16 },
803 { X86::HADDPDrr, X86::HADDPDrm, TB_ALIGN_16 },
804 { X86::HADDPSrr, X86::HADDPSrm, TB_ALIGN_16 },
805 { X86::HSUBPDrr, X86::HSUBPDrm, TB_ALIGN_16 },
806 { X86::HSUBPSrr, X86::HSUBPSrm, TB_ALIGN_16 },
807 { X86::IMUL16rr, X86::IMUL16rm, 0 },
808 { X86::IMUL32rr, X86::IMUL32rm, 0 },
809 { X86::IMUL64rr, X86::IMUL64rm, 0 },
810 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 },
811 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 },
812 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 },
813 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
814 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 },
815 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
816 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 },
817 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 },
818 { X86::MAXPDrr, X86::MAXPDrm, TB_ALIGN_16 },
819 { X86::MAXPSrr, X86::MAXPSrm, TB_ALIGN_16 },
820 { X86::MAXSDrr, X86::MAXSDrm, 0 },
821 { X86::MAXSSrr, X86::MAXSSrm, 0 },
822 { X86::MINPDrr, X86::MINPDrm, TB_ALIGN_16 },
823 { X86::MINPSrr, X86::MINPSrm, TB_ALIGN_16 },
824 { X86::MINSDrr, X86::MINSDrm, 0 },
825 { X86::MINSSrr, X86::MINSSrm, 0 },
826 { X86::MPSADBWrri, X86::MPSADBWrmi, TB_ALIGN_16 },
827 { X86::MULPDrr, X86::MULPDrm, TB_ALIGN_16 },
828 { X86::MULPSrr, X86::MULPSrm, TB_ALIGN_16 },
829 { X86::MULSDrr, X86::MULSDrm, 0 },
830 { X86::MULSSrr, X86::MULSSrm, 0 },
831 { X86::OR16rr, X86::OR16rm, 0 },
832 { X86::OR32rr, X86::OR32rm, 0 },
833 { X86::OR64rr, X86::OR64rm, 0 },
834 { X86::OR8rr, X86::OR8rm, 0 },
835 { X86::ORPDrr, X86::ORPDrm, TB_ALIGN_16 },
836 { X86::ORPSrr, X86::ORPSrm, TB_ALIGN_16 },
837 { X86::PACKSSDWrr, X86::PACKSSDWrm, TB_ALIGN_16 },
838 { X86::PACKSSWBrr, X86::PACKSSWBrm, TB_ALIGN_16 },
839 { X86::PACKUSDWrr, X86::PACKUSDWrm, TB_ALIGN_16 },
840 { X86::PACKUSWBrr, X86::PACKUSWBrm, TB_ALIGN_16 },
841 { X86::PADDBrr, X86::PADDBrm, TB_ALIGN_16 },
842 { X86::PADDDrr, X86::PADDDrm, TB_ALIGN_16 },
843 { X86::PADDQrr, X86::PADDQrm, TB_ALIGN_16 },
844 { X86::PADDSBrr, X86::PADDSBrm, TB_ALIGN_16 },
845 { X86::PADDSWrr, X86::PADDSWrm, TB_ALIGN_16 },
846 { X86::PADDUSBrr, X86::PADDUSBrm, TB_ALIGN_16 },
847 { X86::PADDUSWrr, X86::PADDUSWrm, TB_ALIGN_16 },
848 { X86::PADDWrr, X86::PADDWrm, TB_ALIGN_16 },
849 { X86::PALIGNR128rr, X86::PALIGNR128rm, TB_ALIGN_16 },
850 { X86::PANDNrr, X86::PANDNrm, TB_ALIGN_16 },
851 { X86::PANDrr, X86::PANDrm, TB_ALIGN_16 },
852 { X86::PAVGBrr, X86::PAVGBrm, TB_ALIGN_16 },
853 { X86::PAVGWrr, X86::PAVGWrm, TB_ALIGN_16 },
854 { X86::PBLENDWrri, X86::PBLENDWrmi, TB_ALIGN_16 },
855 { X86::PCMPEQBrr, X86::PCMPEQBrm, TB_ALIGN_16 },
856 { X86::PCMPEQDrr, X86::PCMPEQDrm, TB_ALIGN_16 },
857 { X86::PCMPEQQrr, X86::PCMPEQQrm, TB_ALIGN_16 },
858 { X86::PCMPEQWrr, X86::PCMPEQWrm, TB_ALIGN_16 },
859 { X86::PCMPGTBrr, X86::PCMPGTBrm, TB_ALIGN_16 },
860 { X86::PCMPGTDrr, X86::PCMPGTDrm, TB_ALIGN_16 },
861 { X86::PCMPGTQrr, X86::PCMPGTQrm, TB_ALIGN_16 },
862 { X86::PCMPGTWrr, X86::PCMPGTWrm, TB_ALIGN_16 },
863 { X86::PHADDDrr, X86::PHADDDrm, TB_ALIGN_16 },
864 { X86::PHADDWrr, X86::PHADDWrm, TB_ALIGN_16 },
865 { X86::PHADDSWrr128, X86::PHADDSWrm128, TB_ALIGN_16 },
866 { X86::PHSUBDrr, X86::PHSUBDrm, TB_ALIGN_16 },
867 { X86::PHSUBSWrr128, X86::PHSUBSWrm128, TB_ALIGN_16 },
868 { X86::PHSUBWrr, X86::PHSUBWrm, TB_ALIGN_16 },
869 { X86::PINSRWrri, X86::PINSRWrmi, TB_ALIGN_16 },
870 { X86::PMADDUBSWrr128, X86::PMADDUBSWrm128, TB_ALIGN_16 },
871 { X86::PMADDWDrr, X86::PMADDWDrm, TB_ALIGN_16 },
872 { X86::PMAXSWrr, X86::PMAXSWrm, TB_ALIGN_16 },
873 { X86::PMAXUBrr, X86::PMAXUBrm, TB_ALIGN_16 },
874 { X86::PMINSWrr, X86::PMINSWrm, TB_ALIGN_16 },
875 { X86::PMINUBrr, X86::PMINUBrm, TB_ALIGN_16 },
876 { X86::PMINSBrr, X86::PMINSBrm, TB_ALIGN_16 },
877 { X86::PMINSDrr, X86::PMINSDrm, TB_ALIGN_16 },
878 { X86::PMINUDrr, X86::PMINUDrm, TB_ALIGN_16 },
879 { X86::PMINUWrr, X86::PMINUWrm, TB_ALIGN_16 },
880 { X86::PMAXSBrr, X86::PMAXSBrm, TB_ALIGN_16 },
881 { X86::PMAXSDrr, X86::PMAXSDrm, TB_ALIGN_16 },
882 { X86::PMAXUDrr, X86::PMAXUDrm, TB_ALIGN_16 },
883 { X86::PMAXUWrr, X86::PMAXUWrm, TB_ALIGN_16 },
884 { X86::PMULDQrr, X86::PMULDQrm, TB_ALIGN_16 },
885 { X86::PMULHRSWrr128, X86::PMULHRSWrm128, TB_ALIGN_16 },
886 { X86::PMULHUWrr, X86::PMULHUWrm, TB_ALIGN_16 },
887 { X86::PMULHWrr, X86::PMULHWrm, TB_ALIGN_16 },
888 { X86::PMULLDrr, X86::PMULLDrm, TB_ALIGN_16 },
889 { X86::PMULLWrr, X86::PMULLWrm, TB_ALIGN_16 },
890 { X86::PMULUDQrr, X86::PMULUDQrm, TB_ALIGN_16 },
891 { X86::PORrr, X86::PORrm, TB_ALIGN_16 },
892 { X86::PSADBWrr, X86::PSADBWrm, TB_ALIGN_16 },
893 { X86::PSHUFBrr, X86::PSHUFBrm, TB_ALIGN_16 },
894 { X86::PSIGNBrr, X86::PSIGNBrm, TB_ALIGN_16 },
895 { X86::PSIGNWrr, X86::PSIGNWrm, TB_ALIGN_16 },
896 { X86::PSIGNDrr, X86::PSIGNDrm, TB_ALIGN_16 },
897 { X86::PSLLDrr, X86::PSLLDrm, TB_ALIGN_16 },
898 { X86::PSLLQrr, X86::PSLLQrm, TB_ALIGN_16 },
899 { X86::PSLLWrr, X86::PSLLWrm, TB_ALIGN_16 },
900 { X86::PSRADrr, X86::PSRADrm, TB_ALIGN_16 },
901 { X86::PSRAWrr, X86::PSRAWrm, TB_ALIGN_16 },
902 { X86::PSRLDrr, X86::PSRLDrm, TB_ALIGN_16 },
903 { X86::PSRLQrr, X86::PSRLQrm, TB_ALIGN_16 },
904 { X86::PSRLWrr, X86::PSRLWrm, TB_ALIGN_16 },
905 { X86::PSUBBrr, X86::PSUBBrm, TB_ALIGN_16 },
906 { X86::PSUBDrr, X86::PSUBDrm, TB_ALIGN_16 },
907 { X86::PSUBSBrr, X86::PSUBSBrm, TB_ALIGN_16 },
908 { X86::PSUBSWrr, X86::PSUBSWrm, TB_ALIGN_16 },
909 { X86::PSUBWrr, X86::PSUBWrm, TB_ALIGN_16 },
910 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, TB_ALIGN_16 },
911 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, TB_ALIGN_16 },
912 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, TB_ALIGN_16 },
913 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, TB_ALIGN_16 },
914 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, TB_ALIGN_16 },
915 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, TB_ALIGN_16 },
916 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, TB_ALIGN_16 },
917 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, TB_ALIGN_16 },
918 { X86::PXORrr, X86::PXORrm, TB_ALIGN_16 },
919 { X86::SBB32rr, X86::SBB32rm, 0 },
920 { X86::SBB64rr, X86::SBB64rm, 0 },
921 { X86::SHUFPDrri, X86::SHUFPDrmi, TB_ALIGN_16 },
922 { X86::SHUFPSrri, X86::SHUFPSrmi, TB_ALIGN_16 },
923 { X86::SUB16rr, X86::SUB16rm, 0 },
924 { X86::SUB32rr, X86::SUB32rm, 0 },
925 { X86::SUB64rr, X86::SUB64rm, 0 },
926 { X86::SUB8rr, X86::SUB8rm, 0 },
927 { X86::SUBPDrr, X86::SUBPDrm, TB_ALIGN_16 },
928 { X86::SUBPSrr, X86::SUBPSrm, TB_ALIGN_16 },
929 { X86::SUBSDrr, X86::SUBSDrm, 0 },
930 { X86::SUBSSrr, X86::SUBSSrm, 0 },
931 // FIXME: TEST*rr -> swapped operand of TEST*mr.
932 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, TB_ALIGN_16 },
933 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, TB_ALIGN_16 },
934 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, TB_ALIGN_16 },
935 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, TB_ALIGN_16 },
936 { X86::XOR16rr, X86::XOR16rm, 0 },
937 { X86::XOR32rr, X86::XOR32rm, 0 },
938 { X86::XOR64rr, X86::XOR64rm, 0 },
939 { X86::XOR8rr, X86::XOR8rm, 0 },
940 { X86::XORPDrr, X86::XORPDrm, TB_ALIGN_16 },
941 { X86::XORPSrr, X86::XORPSrm, TB_ALIGN_16 },
942 // AVX 128-bit versions of foldable instructions
943 { X86::VCVTSD2SSrr, X86::VCVTSD2SSrm, 0 },
944 { X86::Int_VCVTSD2SSrr, X86::Int_VCVTSD2SSrm, 0 },
945 { X86::VCVTSI2SD64rr, X86::VCVTSI2SD64rm, 0 },
946 { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm, 0 },
947 { X86::VCVTSI2SDrr, X86::VCVTSI2SDrm, 0 },
948 { X86::Int_VCVTSI2SDrr, X86::Int_VCVTSI2SDrm, 0 },
949 { X86::VCVTSI2SS64rr, X86::VCVTSI2SS64rm, 0 },
950 { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm, 0 },
951 { X86::VCVTSI2SSrr, X86::VCVTSI2SSrm, 0 },
952 { X86::Int_VCVTSI2SSrr, X86::Int_VCVTSI2SSrm, 0 },
953 { X86::VCVTSS2SDrr, X86::VCVTSS2SDrm, 0 },
954 { X86::Int_VCVTSS2SDrr, X86::Int_VCVTSS2SDrm, 0 },
955 { X86::VRSQRTSSr, X86::VRSQRTSSm, 0 },
956 { X86::VSQRTSDr, X86::VSQRTSDm, 0 },
957 { X86::VSQRTSSr, X86::VSQRTSSm, 0 },
958 { X86::VADDPDrr, X86::VADDPDrm, 0 },
959 { X86::VADDPSrr, X86::VADDPSrm, 0 },
960 { X86::VADDSDrr, X86::VADDSDrm, 0 },
961 { X86::VADDSSrr, X86::VADDSSrm, 0 },
962 { X86::VADDSUBPDrr, X86::VADDSUBPDrm, 0 },
963 { X86::VADDSUBPSrr, X86::VADDSUBPSrm, 0 },
964 { X86::VANDNPDrr, X86::VANDNPDrm, 0 },
965 { X86::VANDNPSrr, X86::VANDNPSrm, 0 },
966 { X86::VANDPDrr, X86::VANDPDrm, 0 },
967 { X86::VANDPSrr, X86::VANDPSrm, 0 },
968 { X86::VBLENDPDrri, X86::VBLENDPDrmi, 0 },
969 { X86::VBLENDPSrri, X86::VBLENDPSrmi, 0 },
970 { X86::VBLENDVPDrr, X86::VBLENDVPDrm, 0 },
971 { X86::VBLENDVPSrr, X86::VBLENDVPSrm, 0 },
972 { X86::VCMPPDrri, X86::VCMPPDrmi, 0 },
973 { X86::VCMPPSrri, X86::VCMPPSrmi, 0 },
974 { X86::VCMPSDrr, X86::VCMPSDrm, 0 },
975 { X86::VCMPSSrr, X86::VCMPSSrm, 0 },
976 { X86::VDIVPDrr, X86::VDIVPDrm, 0 },
977 { X86::VDIVPSrr, X86::VDIVPSrm, 0 },
978 { X86::VDIVSDrr, X86::VDIVSDrm, 0 },
979 { X86::VDIVSSrr, X86::VDIVSSrm, 0 },
980 { X86::VFsANDNPDrr, X86::VFsANDNPDrm, TB_ALIGN_16 },
981 { X86::VFsANDNPSrr, X86::VFsANDNPSrm, TB_ALIGN_16 },
982 { X86::VFsANDPDrr, X86::VFsANDPDrm, TB_ALIGN_16 },
983 { X86::VFsANDPSrr, X86::VFsANDPSrm, TB_ALIGN_16 },
984 { X86::VFsORPDrr, X86::VFsORPDrm, TB_ALIGN_16 },
985 { X86::VFsORPSrr, X86::VFsORPSrm, TB_ALIGN_16 },
986 { X86::VFsXORPDrr, X86::VFsXORPDrm, TB_ALIGN_16 },
987 { X86::VFsXORPSrr, X86::VFsXORPSrm, TB_ALIGN_16 },
988 { X86::VHADDPDrr, X86::VHADDPDrm, 0 },
989 { X86::VHADDPSrr, X86::VHADDPSrm, 0 },
990 { X86::VHSUBPDrr, X86::VHSUBPDrm, 0 },
991 { X86::VHSUBPSrr, X86::VHSUBPSrm, 0 },
992 { X86::Int_VCMPSDrr, X86::Int_VCMPSDrm, 0 },
993 { X86::Int_VCMPSSrr, X86::Int_VCMPSSrm, 0 },
994 { X86::VMAXPDrr, X86::VMAXPDrm, 0 },
995 { X86::VMAXPSrr, X86::VMAXPSrm, 0 },
996 { X86::VMAXSDrr, X86::VMAXSDrm, 0 },
997 { X86::VMAXSSrr, X86::VMAXSSrm, 0 },
998 { X86::VMINPDrr, X86::VMINPDrm, 0 },
999 { X86::VMINPSrr, X86::VMINPSrm, 0 },
1000 { X86::VMINSDrr, X86::VMINSDrm, 0 },
1001 { X86::VMINSSrr, X86::VMINSSrm, 0 },
1002 { X86::VMPSADBWrri, X86::VMPSADBWrmi, 0 },
1003 { X86::VMULPDrr, X86::VMULPDrm, 0 },
1004 { X86::VMULPSrr, X86::VMULPSrm, 0 },
1005 { X86::VMULSDrr, X86::VMULSDrm, 0 },
1006 { X86::VMULSSrr, X86::VMULSSrm, 0 },
1007 { X86::VORPDrr, X86::VORPDrm, 0 },
1008 { X86::VORPSrr, X86::VORPSrm, 0 },
1009 { X86::VPACKSSDWrr, X86::VPACKSSDWrm, 0 },
1010 { X86::VPACKSSWBrr, X86::VPACKSSWBrm, 0 },
1011 { X86::VPACKUSDWrr, X86::VPACKUSDWrm, 0 },
1012 { X86::VPACKUSWBrr, X86::VPACKUSWBrm, 0 },
1013 { X86::VPADDBrr, X86::VPADDBrm, 0 },
1014 { X86::VPADDDrr, X86::VPADDDrm, 0 },
1015 { X86::VPADDQrr, X86::VPADDQrm, 0 },
1016 { X86::VPADDSBrr, X86::VPADDSBrm, 0 },
1017 { X86::VPADDSWrr, X86::VPADDSWrm, 0 },
1018 { X86::VPADDUSBrr, X86::VPADDUSBrm, 0 },
1019 { X86::VPADDUSWrr, X86::VPADDUSWrm, 0 },
1020 { X86::VPADDWrr, X86::VPADDWrm, 0 },
1021 { X86::VPALIGNR128rr, X86::VPALIGNR128rm, 0 },
1022 { X86::VPANDNrr, X86::VPANDNrm, 0 },
1023 { X86::VPANDrr, X86::VPANDrm, 0 },
1024 { X86::VPAVGBrr, X86::VPAVGBrm, 0 },
1025 { X86::VPAVGWrr, X86::VPAVGWrm, 0 },
1026 { X86::VPBLENDWrri, X86::VPBLENDWrmi, 0 },
1027 { X86::VPCMPEQBrr, X86::VPCMPEQBrm, 0 },
1028 { X86::VPCMPEQDrr, X86::VPCMPEQDrm, 0 },
1029 { X86::VPCMPEQQrr, X86::VPCMPEQQrm, 0 },
1030 { X86::VPCMPEQWrr, X86::VPCMPEQWrm, 0 },
1031 { X86::VPCMPGTBrr, X86::VPCMPGTBrm, 0 },
1032 { X86::VPCMPGTDrr, X86::VPCMPGTDrm, 0 },
1033 { X86::VPCMPGTQrr, X86::VPCMPGTQrm, 0 },
1034 { X86::VPCMPGTWrr, X86::VPCMPGTWrm, 0 },
1035 { X86::VPHADDDrr, X86::VPHADDDrm, 0 },
1036 { X86::VPHADDSWrr128, X86::VPHADDSWrm128, 0 },
1037 { X86::VPHADDWrr, X86::VPHADDWrm, 0 },
1038 { X86::VPHSUBDrr, X86::VPHSUBDrm, 0 },
1039 { X86::VPHSUBSWrr128, X86::VPHSUBSWrm128, 0 },
1040 { X86::VPHSUBWrr, X86::VPHSUBWrm, 0 },
1041 { X86::VPERMILPDrr, X86::VPERMILPDrm, 0 },
1042 { X86::VPERMILPSrr, X86::VPERMILPSrm, 0 },
1043 { X86::VPINSRWrri, X86::VPINSRWrmi, 0 },
1044 { X86::VPMADDUBSWrr128, X86::VPMADDUBSWrm128, 0 },
1045 { X86::VPMADDWDrr, X86::VPMADDWDrm, 0 },
1046 { X86::VPMAXSWrr, X86::VPMAXSWrm, 0 },
1047 { X86::VPMAXUBrr, X86::VPMAXUBrm, 0 },
1048 { X86::VPMINSWrr, X86::VPMINSWrm, 0 },
1049 { X86::VPMINUBrr, X86::VPMINUBrm, 0 },
1050 { X86::VPMINSBrr, X86::VPMINSBrm, 0 },
1051 { X86::VPMINSDrr, X86::VPMINSDrm, 0 },
1052 { X86::VPMINUDrr, X86::VPMINUDrm, 0 },
1053 { X86::VPMINUWrr, X86::VPMINUWrm, 0 },
1054 { X86::VPMAXSBrr, X86::VPMAXSBrm, 0 },
1055 { X86::VPMAXSDrr, X86::VPMAXSDrm, 0 },
1056 { X86::VPMAXUDrr, X86::VPMAXUDrm, 0 },
1057 { X86::VPMAXUWrr, X86::VPMAXUWrm, 0 },
1058 { X86::VPMULDQrr, X86::VPMULDQrm, 0 },
1059 { X86::VPMULHRSWrr128, X86::VPMULHRSWrm128, 0 },
1060 { X86::VPMULHUWrr, X86::VPMULHUWrm, 0 },
1061 { X86::VPMULHWrr, X86::VPMULHWrm, 0 },
1062 { X86::VPMULLDrr, X86::VPMULLDrm, 0 },
1063 { X86::VPMULLWrr, X86::VPMULLWrm, 0 },
1064 { X86::VPMULUDQrr, X86::VPMULUDQrm, 0 },
1065 { X86::VPORrr, X86::VPORrm, 0 },
1066 { X86::VPSADBWrr, X86::VPSADBWrm, 0 },
1067 { X86::VPSHUFBrr, X86::VPSHUFBrm, 0 },
1068 { X86::VPSIGNBrr, X86::VPSIGNBrm, 0 },
1069 { X86::VPSIGNWrr, X86::VPSIGNWrm, 0 },
1070 { X86::VPSIGNDrr, X86::VPSIGNDrm, 0 },
1071 { X86::VPSLLDrr, X86::VPSLLDrm, 0 },
1072 { X86::VPSLLQrr, X86::VPSLLQrm, 0 },
1073 { X86::VPSLLWrr, X86::VPSLLWrm, 0 },
1074 { X86::VPSRADrr, X86::VPSRADrm, 0 },
1075 { X86::VPSRAWrr, X86::VPSRAWrm, 0 },
1076 { X86::VPSRLDrr, X86::VPSRLDrm, 0 },
1077 { X86::VPSRLQrr, X86::VPSRLQrm, 0 },
1078 { X86::VPSRLWrr, X86::VPSRLWrm, 0 },
1079 { X86::VPSUBBrr, X86::VPSUBBrm, 0 },
1080 { X86::VPSUBDrr, X86::VPSUBDrm, 0 },
1081 { X86::VPSUBSBrr, X86::VPSUBSBrm, 0 },
1082 { X86::VPSUBSWrr, X86::VPSUBSWrm, 0 },
1083 { X86::VPSUBWrr, X86::VPSUBWrm, 0 },
1084 { X86::VPUNPCKHBWrr, X86::VPUNPCKHBWrm, 0 },
1085 { X86::VPUNPCKHDQrr, X86::VPUNPCKHDQrm, 0 },
1086 { X86::VPUNPCKHQDQrr, X86::VPUNPCKHQDQrm, 0 },
1087 { X86::VPUNPCKHWDrr, X86::VPUNPCKHWDrm, 0 },
1088 { X86::VPUNPCKLBWrr, X86::VPUNPCKLBWrm, 0 },
1089 { X86::VPUNPCKLDQrr, X86::VPUNPCKLDQrm, 0 },
1090 { X86::VPUNPCKLQDQrr, X86::VPUNPCKLQDQrm, 0 },
1091 { X86::VPUNPCKLWDrr, X86::VPUNPCKLWDrm, 0 },
1092 { X86::VPXORrr, X86::VPXORrm, 0 },
1093 { X86::VSHUFPDrri, X86::VSHUFPDrmi, 0 },
1094 { X86::VSHUFPSrri, X86::VSHUFPSrmi, 0 },
1095 { X86::VSUBPDrr, X86::VSUBPDrm, 0 },
1096 { X86::VSUBPSrr, X86::VSUBPSrm, 0 },
1097 { X86::VSUBSDrr, X86::VSUBSDrm, 0 },
1098 { X86::VSUBSSrr, X86::VSUBSSrm, 0 },
1099 { X86::VUNPCKHPDrr, X86::VUNPCKHPDrm, 0 },
1100 { X86::VUNPCKHPSrr, X86::VUNPCKHPSrm, 0 },
1101 { X86::VUNPCKLPDrr, X86::VUNPCKLPDrm, 0 },
1102 { X86::VUNPCKLPSrr, X86::VUNPCKLPSrm, 0 },
1103 { X86::VXORPDrr, X86::VXORPDrm, 0 },
1104 { X86::VXORPSrr, X86::VXORPSrm, 0 },
1105 // AVX 256-bit foldable instructions
1106 { X86::VADDPDYrr, X86::VADDPDYrm, 0 },
1107 { X86::VADDPSYrr, X86::VADDPSYrm, 0 },
1108 { X86::VADDSUBPDYrr, X86::VADDSUBPDYrm, 0 },
1109 { X86::VADDSUBPSYrr, X86::VADDSUBPSYrm, 0 },
1110 { X86::VANDNPDYrr, X86::VANDNPDYrm, 0 },
1111 { X86::VANDNPSYrr, X86::VANDNPSYrm, 0 },
1112 { X86::VANDPDYrr, X86::VANDPDYrm, 0 },
1113 { X86::VANDPSYrr, X86::VANDPSYrm, 0 },
1114 { X86::VBLENDPDYrri, X86::VBLENDPDYrmi, 0 },
1115 { X86::VBLENDPSYrri, X86::VBLENDPSYrmi, 0 },
1116 { X86::VBLENDVPDYrr, X86::VBLENDVPDYrm, 0 },
1117 { X86::VBLENDVPSYrr, X86::VBLENDVPSYrm, 0 },
1118 { X86::VCMPPDYrri, X86::VCMPPDYrmi, 0 },
1119 { X86::VCMPPSYrri, X86::VCMPPSYrmi, 0 },
1120 { X86::VDIVPDYrr, X86::VDIVPDYrm, 0 },
1121 { X86::VDIVPSYrr, X86::VDIVPSYrm, 0 },
1122 { X86::VHADDPDYrr, X86::VHADDPDYrm, 0 },
1123 { X86::VHADDPSYrr, X86::VHADDPSYrm, 0 },
1124 { X86::VHSUBPDYrr, X86::VHSUBPDYrm, 0 },
1125 { X86::VHSUBPSYrr, X86::VHSUBPSYrm, 0 },
1126 { X86::VINSERTF128rr, X86::VINSERTF128rm, 0 },
1127 { X86::VMAXPDYrr, X86::VMAXPDYrm, 0 },
1128 { X86::VMAXPSYrr, X86::VMAXPSYrm, 0 },
1129 { X86::VMINPDYrr, X86::VMINPDYrm, 0 },
1130 { X86::VMINPSYrr, X86::VMINPSYrm, 0 },
1131 { X86::VMULPDYrr, X86::VMULPDYrm, 0 },
1132 { X86::VMULPSYrr, X86::VMULPSYrm, 0 },
1133 { X86::VORPDYrr, X86::VORPDYrm, 0 },
1134 { X86::VORPSYrr, X86::VORPSYrm, 0 },
1135 { X86::VPERM2F128rr, X86::VPERM2F128rm, 0 },
1136 { X86::VPERMILPDYrr, X86::VPERMILPDYrm, 0 },
1137 { X86::VPERMILPSYrr, X86::VPERMILPSYrm, 0 },
1138 { X86::VSHUFPDYrri, X86::VSHUFPDYrmi, 0 },
1139 { X86::VSHUFPSYrri, X86::VSHUFPSYrmi, 0 },
1140 { X86::VSUBPDYrr, X86::VSUBPDYrm, 0 },
1141 { X86::VSUBPSYrr, X86::VSUBPSYrm, 0 },
1142 { X86::VUNPCKHPDYrr, X86::VUNPCKHPDYrm, 0 },
1143 { X86::VUNPCKHPSYrr, X86::VUNPCKHPSYrm, 0 },
1144 { X86::VUNPCKLPDYrr, X86::VUNPCKLPDYrm, 0 },
1145 { X86::VUNPCKLPSYrr, X86::VUNPCKLPSYrm, 0 },
1146 { X86::VXORPDYrr, X86::VXORPDYrm, 0 },
1147 { X86::VXORPSYrr, X86::VXORPSYrm, 0 },
1148 // AVX2 foldable instructions
1149 { X86::VINSERTI128rr, X86::VINSERTI128rm, 0 },
1150 { X86::VPACKSSDWYrr, X86::VPACKSSDWYrm, 0 },
1151 { X86::VPACKSSWBYrr, X86::VPACKSSWBYrm, 0 },
1152 { X86::VPACKUSDWYrr, X86::VPACKUSDWYrm, 0 },
1153 { X86::VPACKUSWBYrr, X86::VPACKUSWBYrm, 0 },
1154 { X86::VPADDBYrr, X86::VPADDBYrm, 0 },
1155 { X86::VPADDDYrr, X86::VPADDDYrm, 0 },
1156 { X86::VPADDQYrr, X86::VPADDQYrm, 0 },
1157 { X86::VPADDSBYrr, X86::VPADDSBYrm, 0 },
1158 { X86::VPADDSWYrr, X86::VPADDSWYrm, 0 },
1159 { X86::VPADDUSBYrr, X86::VPADDUSBYrm, 0 },
1160 { X86::VPADDUSWYrr, X86::VPADDUSWYrm, 0 },
1161 { X86::VPADDWYrr, X86::VPADDWYrm, 0 },
1162 { X86::VPALIGNR256rr, X86::VPALIGNR256rm, 0 },
1163 { X86::VPANDNYrr, X86::VPANDNYrm, 0 },
1164 { X86::VPANDYrr, X86::VPANDYrm, 0 },
1165 { X86::VPAVGBYrr, X86::VPAVGBYrm, 0 },
1166 { X86::VPAVGWYrr, X86::VPAVGWYrm, 0 },
1167 { X86::VPBLENDDrri, X86::VPBLENDDrmi, 0 },
1168 { X86::VPBLENDDYrri, X86::VPBLENDDYrmi, 0 },
1169 { X86::VPBLENDWYrri, X86::VPBLENDWYrmi, 0 },
1170 { X86::VPCMPEQBYrr, X86::VPCMPEQBYrm, 0 },
1171 { X86::VPCMPEQDYrr, X86::VPCMPEQDYrm, 0 },
1172 { X86::VPCMPEQQYrr, X86::VPCMPEQQYrm, 0 },
1173 { X86::VPCMPEQWYrr, X86::VPCMPEQWYrm, 0 },
1174 { X86::VPCMPGTBYrr, X86::VPCMPGTBYrm, 0 },
1175 { X86::VPCMPGTDYrr, X86::VPCMPGTDYrm, 0 },
1176 { X86::VPCMPGTQYrr, X86::VPCMPGTQYrm, 0 },
1177 { X86::VPCMPGTWYrr, X86::VPCMPGTWYrm, 0 },
1178 { X86::VPERM2I128rr, X86::VPERM2I128rm, 0 },
1179 { X86::VPERMDYrr, X86::VPERMDYrm, 0 },
1180 { X86::VPERMPDYri, X86::VPERMPDYmi, 0 },
1181 { X86::VPERMPSYrr, X86::VPERMPSYrm, 0 },
1182 { X86::VPERMQYri, X86::VPERMQYmi, 0 },
1183 { X86::VPHADDDYrr, X86::VPHADDDYrm, 0 },
1184 { X86::VPHADDSWrr256, X86::VPHADDSWrm256, 0 },
1185 { X86::VPHADDWYrr, X86::VPHADDWYrm, 0 },
1186 { X86::VPHSUBDYrr, X86::VPHSUBDYrm, 0 },
1187 { X86::VPHSUBSWrr256, X86::VPHSUBSWrm256, 0 },
1188 { X86::VPHSUBWYrr, X86::VPHSUBWYrm, 0 },
1189 { X86::VPMADDUBSWrr256, X86::VPMADDUBSWrm256, 0 },
1190 { X86::VPMADDWDYrr, X86::VPMADDWDYrm, 0 },
1191 { X86::VPMAXSWYrr, X86::VPMAXSWYrm, 0 },
1192 { X86::VPMAXUBYrr, X86::VPMAXUBYrm, 0 },
1193 { X86::VPMINSWYrr, X86::VPMINSWYrm, 0 },
1194 { X86::VPMINUBYrr, X86::VPMINUBYrm, 0 },
1195 { X86::VPMINSBYrr, X86::VPMINSBYrm, 0 },
1196 { X86::VPMINSDYrr, X86::VPMINSDYrm, 0 },
1197 { X86::VPMINUDYrr, X86::VPMINUDYrm, 0 },
1198 { X86::VPMINUWYrr, X86::VPMINUWYrm, 0 },
1199 { X86::VPMAXSBYrr, X86::VPMAXSBYrm, 0 },
1200 { X86::VPMAXSDYrr, X86::VPMAXSDYrm, 0 },
1201 { X86::VPMAXUDYrr, X86::VPMAXUDYrm, 0 },
1202 { X86::VPMAXUWYrr, X86::VPMAXUWYrm, 0 },
1203 { X86::VMPSADBWYrri, X86::VMPSADBWYrmi, 0 },
1204 { X86::VPMULDQYrr, X86::VPMULDQYrm, 0 },
1205 { X86::VPMULHRSWrr256, X86::VPMULHRSWrm256, 0 },
1206 { X86::VPMULHUWYrr, X86::VPMULHUWYrm, 0 },
1207 { X86::VPMULHWYrr, X86::VPMULHWYrm, 0 },
1208 { X86::VPMULLDYrr, X86::VPMULLDYrm, 0 },
1209 { X86::VPMULLWYrr, X86::VPMULLWYrm, 0 },
1210 { X86::VPMULUDQYrr, X86::VPMULUDQYrm, 0 },
1211 { X86::VPORYrr, X86::VPORYrm, 0 },
1212 { X86::VPSADBWYrr, X86::VPSADBWYrm, 0 },
1213 { X86::VPSHUFBYrr, X86::VPSHUFBYrm, 0 },
1214 { X86::VPSIGNBYrr, X86::VPSIGNBYrm, 0 },
1215 { X86::VPSIGNWYrr, X86::VPSIGNWYrm, 0 },
1216 { X86::VPSIGNDYrr, X86::VPSIGNDYrm, 0 },
1217 { X86::VPSLLDYrr, X86::VPSLLDYrm, 0 },
1218 { X86::VPSLLQYrr, X86::VPSLLQYrm, 0 },
1219 { X86::VPSLLWYrr, X86::VPSLLWYrm, 0 },
1220 { X86::VPSLLVDrr, X86::VPSLLVDrm, 0 },
1221 { X86::VPSLLVDYrr, X86::VPSLLVDYrm, 0 },
1222 { X86::VPSLLVQrr, X86::VPSLLVQrm, 0 },
1223 { X86::VPSLLVQYrr, X86::VPSLLVQYrm, 0 },
1224 { X86::VPSRADYrr, X86::VPSRADYrm, 0 },
1225 { X86::VPSRAWYrr, X86::VPSRAWYrm, 0 },
1226 { X86::VPSRAVDrr, X86::VPSRAVDrm, 0 },
1227 { X86::VPSRAVDYrr, X86::VPSRAVDYrm, 0 },
1228 { X86::VPSRLDYrr, X86::VPSRLDYrm, 0 },
1229 { X86::VPSRLQYrr, X86::VPSRLQYrm, 0 },
1230 { X86::VPSRLWYrr, X86::VPSRLWYrm, 0 },
1231 { X86::VPSRLVDrr, X86::VPSRLVDrm, 0 },
1232 { X86::VPSRLVDYrr, X86::VPSRLVDYrm, 0 },
1233 { X86::VPSRLVQrr, X86::VPSRLVQrm, 0 },
1234 { X86::VPSRLVQYrr, X86::VPSRLVQYrm, 0 },
1235 { X86::VPSUBBYrr, X86::VPSUBBYrm, 0 },
1236 { X86::VPSUBDYrr, X86::VPSUBDYrm, 0 },
1237 { X86::VPSUBSBYrr, X86::VPSUBSBYrm, 0 },
1238 { X86::VPSUBSWYrr, X86::VPSUBSWYrm, 0 },
1239 { X86::VPSUBWYrr, X86::VPSUBWYrm, 0 },
1240 { X86::VPUNPCKHBWYrr, X86::VPUNPCKHBWYrm, 0 },
1241 { X86::VPUNPCKHDQYrr, X86::VPUNPCKHDQYrm, 0 },
1242 { X86::VPUNPCKHQDQYrr, X86::VPUNPCKHQDQYrm, 0 },
1243 { X86::VPUNPCKHWDYrr, X86::VPUNPCKHWDYrm, 0 },
1244 { X86::VPUNPCKLBWYrr, X86::VPUNPCKLBWYrm, 0 },
1245 { X86::VPUNPCKLDQYrr, X86::VPUNPCKLDQYrm, 0 },
1246 { X86::VPUNPCKLQDQYrr, X86::VPUNPCKLQDQYrm, 0 },
1247 { X86::VPUNPCKLWDYrr, X86::VPUNPCKLWDYrm, 0 },
1248 { X86::VPXORYrr, X86::VPXORYrm, 0 },
1249 // FIXME: add AVX 256-bit foldable instructions
1251 // FMA4 foldable patterns
1252 { X86::VFMADDSS4rr, X86::VFMADDSS4mr, 0 },
1253 { X86::VFMADDSD4rr, X86::VFMADDSD4mr, 0 },
1254 { X86::VFMADDPS4rr, X86::VFMADDPS4mr, TB_ALIGN_16 },
1255 { X86::VFMADDPD4rr, X86::VFMADDPD4mr, TB_ALIGN_16 },
1256 { X86::VFMADDPS4rrY, X86::VFMADDPS4mrY, TB_ALIGN_32 },
1257 { X86::VFMADDPD4rrY, X86::VFMADDPD4mrY, TB_ALIGN_32 },
1258 { X86::VFNMADDSS4rr, X86::VFNMADDSS4mr, 0 },
1259 { X86::VFNMADDSD4rr, X86::VFNMADDSD4mr, 0 },
1260 { X86::VFNMADDPS4rr, X86::VFNMADDPS4mr, TB_ALIGN_16 },
1261 { X86::VFNMADDPD4rr, X86::VFNMADDPD4mr, TB_ALIGN_16 },
1262 { X86::VFNMADDPS4rrY, X86::VFNMADDPS4mrY, TB_ALIGN_32 },
1263 { X86::VFNMADDPD4rrY, X86::VFNMADDPD4mrY, TB_ALIGN_32 },
1264 { X86::VFMSUBSS4rr, X86::VFMSUBSS4mr, 0 },
1265 { X86::VFMSUBSD4rr, X86::VFMSUBSD4mr, 0 },
1266 { X86::VFMSUBPS4rr, X86::VFMSUBPS4mr, TB_ALIGN_16 },
1267 { X86::VFMSUBPD4rr, X86::VFMSUBPD4mr, TB_ALIGN_16 },
1268 { X86::VFMSUBPS4rrY, X86::VFMSUBPS4mrY, TB_ALIGN_32 },
1269 { X86::VFMSUBPD4rrY, X86::VFMSUBPD4mrY, TB_ALIGN_32 },
1270 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4mr, 0 },
1271 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4mr, 0 },
1272 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4mr, TB_ALIGN_16 },
1273 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4mr, TB_ALIGN_16 },
1274 { X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4mrY, TB_ALIGN_32 },
1275 { X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4mrY, TB_ALIGN_32 },
1276 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4mr, TB_ALIGN_16 },
1277 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4mr, TB_ALIGN_16 },
1278 { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4mrY, TB_ALIGN_32 },
1279 { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4mrY, TB_ALIGN_32 },
1280 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4mr, TB_ALIGN_16 },
1281 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4mr, TB_ALIGN_16 },
1282 { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4mrY, TB_ALIGN_32 },
1283 { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4mrY, TB_ALIGN_32 },
1285 // BMI/BMI2 foldable instructions
1286 { X86::ANDN32rr, X86::ANDN32rm, 0 },
1287 { X86::ANDN64rr, X86::ANDN64rm, 0 },
1288 { X86::MULX32rr, X86::MULX32rm, 0 },
1289 { X86::MULX64rr, X86::MULX64rm, 0 },
1290 { X86::PDEP32rr, X86::PDEP32rm, 0 },
1291 { X86::PDEP64rr, X86::PDEP64rm, 0 },
1292 { X86::PEXT32rr, X86::PEXT32rm, 0 },
1293 { X86::PEXT64rr, X86::PEXT64rm, 0 },
1295 // AVX-512 foldable instructions
1296 { X86::VADDPSZrr, X86::VADDPSZrm, 0 },
1297 { X86::VADDPDZrr, X86::VADDPDZrm, 0 },
1298 { X86::VSUBPSZrr, X86::VSUBPSZrm, 0 },
1299 { X86::VSUBPDZrr, X86::VSUBPDZrm, 0 },
1300 { X86::VMULPSZrr, X86::VMULPSZrm, 0 },
1301 { X86::VMULPDZrr, X86::VMULPDZrm, 0 },
1302 { X86::VDIVPSZrr, X86::VDIVPSZrm, 0 },
1303 { X86::VDIVPDZrr, X86::VDIVPDZrm, 0 },
1304 { X86::VMINPSZrr, X86::VMINPSZrm, 0 },
1305 { X86::VMINPDZrr, X86::VMINPDZrm, 0 },
1306 { X86::VMAXPSZrr, X86::VMAXPSZrm, 0 },
1307 { X86::VMAXPDZrr, X86::VMAXPDZrm, 0 },
1308 { X86::VPADDDZrr, X86::VPADDDZrm, 0 },
1309 { X86::VPADDQZrr, X86::VPADDQZrm, 0 },
1310 { X86::VPERMPDZri, X86::VPERMPDZmi, 0 },
1311 { X86::VPERMPSZrr, X86::VPERMPSZrm, 0 },
1312 { X86::VPMAXSDZrr, X86::VPMAXSDZrm, 0 },
1313 { X86::VPMAXSQZrr, X86::VPMAXSQZrm, 0 },
1314 { X86::VPMAXUDZrr, X86::VPMAXUDZrm, 0 },
1315 { X86::VPMAXUQZrr, X86::VPMAXUQZrm, 0 },
1316 { X86::VPMINSDZrr, X86::VPMINSDZrm, 0 },
1317 { X86::VPMINSQZrr, X86::VPMINSQZrm, 0 },
1318 { X86::VPMINUDZrr, X86::VPMINUDZrm, 0 },
1319 { X86::VPMINUQZrr, X86::VPMINUQZrm, 0 },
1320 { X86::VPMULDQZrr, X86::VPMULDQZrm, 0 },
1321 { X86::VPSLLVDZrr, X86::VPSLLVDZrm, 0 },
1322 { X86::VPSLLVQZrr, X86::VPSLLVQZrm, 0 },
1323 { X86::VPSRAVDZrr, X86::VPSRAVDZrm, 0 },
1324 { X86::VPSRLVDZrr, X86::VPSRLVDZrm, 0 },
1325 { X86::VPSRLVQZrr, X86::VPSRLVQZrm, 0 },
1326 { X86::VPSUBDZrr, X86::VPSUBDZrm, 0 },
1327 { X86::VPSUBQZrr, X86::VPSUBQZrm, 0 },
1328 { X86::VSHUFPDZrri, X86::VSHUFPDZrmi, 0 },
1329 { X86::VSHUFPSZrri, X86::VSHUFPSZrmi, 0 },
1330 { X86::VALIGNQrri, X86::VALIGNQrmi, 0 },
1331 { X86::VALIGNDrri, X86::VALIGNDrmi, 0 },
1332 { X86::VPMULUDQZrr, X86::VPMULUDQZrm, 0 },
1333 { X86::VBROADCASTSSZrkz, X86::VBROADCASTSSZmkz, TB_NO_REVERSE },
1334 { X86::VBROADCASTSDZrkz, X86::VBROADCASTSDZmkz, TB_NO_REVERSE },
1336 // AVX-512{F,VL} foldable instructions
1337 { X86::VBROADCASTSSZ256rkz, X86::VBROADCASTSSZ256mkz, TB_NO_REVERSE },
1338 { X86::VBROADCASTSDZ256rkz, X86::VBROADCASTSDZ256mkz, TB_NO_REVERSE },
1339 { X86::VBROADCASTSSZ128rkz, X86::VBROADCASTSSZ128mkz, TB_NO_REVERSE },
1341 // AVX-512{F,VL} foldable instructions
1342 { X86::VADDPDZ128rr, X86::VADDPDZ128rm, 0 },
1343 { X86::VADDPDZ256rr, X86::VADDPDZ256rm, 0 },
1344 { X86::VADDPSZ128rr, X86::VADDPSZ128rm, 0 },
1345 { X86::VADDPSZ256rr, X86::VADDPSZ256rm, 0 },
1347 // AES foldable instructions
1348 { X86::AESDECLASTrr, X86::AESDECLASTrm, TB_ALIGN_16 },
1349 { X86::AESDECrr, X86::AESDECrm, TB_ALIGN_16 },
1350 { X86::AESENCLASTrr, X86::AESENCLASTrm, TB_ALIGN_16 },
1351 { X86::AESENCrr, X86::AESENCrm, TB_ALIGN_16 },
1352 { X86::VAESDECLASTrr, X86::VAESDECLASTrm, TB_ALIGN_16 },
1353 { X86::VAESDECrr, X86::VAESDECrm, TB_ALIGN_16 },
1354 { X86::VAESENCLASTrr, X86::VAESENCLASTrm, TB_ALIGN_16 },
1355 { X86::VAESENCrr, X86::VAESENCrm, TB_ALIGN_16 },
1357 // SHA foldable instructions
1358 { X86::SHA1MSG1rr, X86::SHA1MSG1rm, TB_ALIGN_16 },
1359 { X86::SHA1MSG2rr, X86::SHA1MSG2rm, TB_ALIGN_16 },
1360 { X86::SHA1NEXTErr, X86::SHA1NEXTErm, TB_ALIGN_16 },
1361 { X86::SHA1RNDS4rri, X86::SHA1RNDS4rmi, TB_ALIGN_16 },
1362 { X86::SHA256MSG1rr, X86::SHA256MSG1rm, TB_ALIGN_16 },
1363 { X86::SHA256MSG2rr, X86::SHA256MSG2rm, TB_ALIGN_16 },
1364 { X86::SHA256RNDS2rr, X86::SHA256RNDS2rm, TB_ALIGN_16 },
1365 };
1367 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
1368 unsigned RegOp = OpTbl2[i].RegOp;
1369 unsigned MemOp = OpTbl2[i].MemOp;
1370 unsigned Flags = OpTbl2[i].Flags;
1371 AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
1372 RegOp, MemOp,
1373 // Index 2, folded load
1374 Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
1375 }
1377 static const X86OpTblEntry OpTbl3[] = {
1378 // FMA foldable instructions
1379 { X86::VFMADDSSr231r, X86::VFMADDSSr231m, TB_ALIGN_NONE },
1380 { X86::VFMADDSDr231r, X86::VFMADDSDr231m, TB_ALIGN_NONE },
1381 { X86::VFMADDSSr132r, X86::VFMADDSSr132m, TB_ALIGN_NONE },
1382 { X86::VFMADDSDr132r, X86::VFMADDSDr132m, TB_ALIGN_NONE },
1383 { X86::VFMADDSSr213r, X86::VFMADDSSr213m, TB_ALIGN_NONE },
1384 { X86::VFMADDSDr213r, X86::VFMADDSDr213m, TB_ALIGN_NONE },
1386 { X86::VFMADDPSr231r, X86::VFMADDPSr231m, TB_ALIGN_NONE },
1387 { X86::VFMADDPDr231r, X86::VFMADDPDr231m, TB_ALIGN_NONE },
1388 { X86::VFMADDPSr132r, X86::VFMADDPSr132m, TB_ALIGN_NONE },
1389 { X86::VFMADDPDr132r, X86::VFMADDPDr132m, TB_ALIGN_NONE },
1390 { X86::VFMADDPSr213r, X86::VFMADDPSr213m, TB_ALIGN_NONE },
1391 { X86::VFMADDPDr213r, X86::VFMADDPDr213m, TB_ALIGN_NONE },
1392 { X86::VFMADDPSr231rY, X86::VFMADDPSr231mY, TB_ALIGN_NONE },
1393 { X86::VFMADDPDr231rY, X86::VFMADDPDr231mY, TB_ALIGN_NONE },
1394 { X86::VFMADDPSr132rY, X86::VFMADDPSr132mY, TB_ALIGN_NONE },
1395 { X86::VFMADDPDr132rY, X86::VFMADDPDr132mY, TB_ALIGN_NONE },
1396 { X86::VFMADDPSr213rY, X86::VFMADDPSr213mY, TB_ALIGN_NONE },
1397 { X86::VFMADDPDr213rY, X86::VFMADDPDr213mY, TB_ALIGN_NONE },
1399 { X86::VFNMADDSSr231r, X86::VFNMADDSSr231m, TB_ALIGN_NONE },
1400 { X86::VFNMADDSDr231r, X86::VFNMADDSDr231m, TB_ALIGN_NONE },
1401 { X86::VFNMADDSSr132r, X86::VFNMADDSSr132m, TB_ALIGN_NONE },
1402 { X86::VFNMADDSDr132r, X86::VFNMADDSDr132m, TB_ALIGN_NONE },
1403 { X86::VFNMADDSSr213r, X86::VFNMADDSSr213m, TB_ALIGN_NONE },
1404 { X86::VFNMADDSDr213r, X86::VFNMADDSDr213m, TB_ALIGN_NONE },
1406 { X86::VFNMADDPSr231r, X86::VFNMADDPSr231m, TB_ALIGN_NONE },
1407 { X86::VFNMADDPDr231r, X86::VFNMADDPDr231m, TB_ALIGN_NONE },
1408 { X86::VFNMADDPSr132r, X86::VFNMADDPSr132m, TB_ALIGN_NONE },
1409 { X86::VFNMADDPDr132r, X86::VFNMADDPDr132m, TB_ALIGN_NONE },
1410 { X86::VFNMADDPSr213r, X86::VFNMADDPSr213m, TB_ALIGN_NONE },
1411 { X86::VFNMADDPDr213r, X86::VFNMADDPDr213m, TB_ALIGN_NONE },
1412 { X86::VFNMADDPSr231rY, X86::VFNMADDPSr231mY, TB_ALIGN_NONE },
1413 { X86::VFNMADDPDr231rY, X86::VFNMADDPDr231mY, TB_ALIGN_NONE },
1414 { X86::VFNMADDPSr132rY, X86::VFNMADDPSr132mY, TB_ALIGN_NONE },
1415 { X86::VFNMADDPDr132rY, X86::VFNMADDPDr132mY, TB_ALIGN_NONE },
1416 { X86::VFNMADDPSr213rY, X86::VFNMADDPSr213mY, TB_ALIGN_NONE },
1417 { X86::VFNMADDPDr213rY, X86::VFNMADDPDr213mY, TB_ALIGN_NONE },
1419 { X86::VFMSUBSSr231r, X86::VFMSUBSSr231m, TB_ALIGN_NONE },
1420 { X86::VFMSUBSDr231r, X86::VFMSUBSDr231m, TB_ALIGN_NONE },
1421 { X86::VFMSUBSSr132r, X86::VFMSUBSSr132m, TB_ALIGN_NONE },
1422 { X86::VFMSUBSDr132r, X86::VFMSUBSDr132m, TB_ALIGN_NONE },
1423 { X86::VFMSUBSSr213r, X86::VFMSUBSSr213m, TB_ALIGN_NONE },
1424 { X86::VFMSUBSDr213r, X86::VFMSUBSDr213m, TB_ALIGN_NONE },
1426 { X86::VFMSUBPSr231r, X86::VFMSUBPSr231m, TB_ALIGN_NONE },
1427 { X86::VFMSUBPDr231r, X86::VFMSUBPDr231m, TB_ALIGN_NONE },
1428 { X86::VFMSUBPSr132r, X86::VFMSUBPSr132m, TB_ALIGN_NONE },
1429 { X86::VFMSUBPDr132r, X86::VFMSUBPDr132m, TB_ALIGN_NONE },
1430 { X86::VFMSUBPSr213r, X86::VFMSUBPSr213m, TB_ALIGN_NONE },
1431 { X86::VFMSUBPDr213r, X86::VFMSUBPDr213m, TB_ALIGN_NONE },
1432 { X86::VFMSUBPSr231rY, X86::VFMSUBPSr231mY, TB_ALIGN_NONE },
1433 { X86::VFMSUBPDr231rY, X86::VFMSUBPDr231mY, TB_ALIGN_NONE },
1434 { X86::VFMSUBPSr132rY, X86::VFMSUBPSr132mY, TB_ALIGN_NONE },
1435 { X86::VFMSUBPDr132rY, X86::VFMSUBPDr132mY, TB_ALIGN_NONE },
1436 { X86::VFMSUBPSr213rY, X86::VFMSUBPSr213mY, TB_ALIGN_NONE },
1437 { X86::VFMSUBPDr213rY, X86::VFMSUBPDr213mY, TB_ALIGN_NONE },
1439 { X86::VFNMSUBSSr231r, X86::VFNMSUBSSr231m, TB_ALIGN_NONE },
1440 { X86::VFNMSUBSDr231r, X86::VFNMSUBSDr231m, TB_ALIGN_NONE },
1441 { X86::VFNMSUBSSr132r, X86::VFNMSUBSSr132m, TB_ALIGN_NONE },
1442 { X86::VFNMSUBSDr132r, X86::VFNMSUBSDr132m, TB_ALIGN_NONE },
1443 { X86::VFNMSUBSSr213r, X86::VFNMSUBSSr213m, TB_ALIGN_NONE },
1444 { X86::VFNMSUBSDr213r, X86::VFNMSUBSDr213m, TB_ALIGN_NONE },
1446 { X86::VFNMSUBPSr231r, X86::VFNMSUBPSr231m, TB_ALIGN_NONE },
1447 { X86::VFNMSUBPDr231r, X86::VFNMSUBPDr231m, TB_ALIGN_NONE },
1448 { X86::VFNMSUBPSr132r, X86::VFNMSUBPSr132m, TB_ALIGN_NONE },
1449 { X86::VFNMSUBPDr132r, X86::VFNMSUBPDr132m, TB_ALIGN_NONE },
1450 { X86::VFNMSUBPSr213r, X86::VFNMSUBPSr213m, TB_ALIGN_NONE },
1451 { X86::VFNMSUBPDr213r, X86::VFNMSUBPDr213m, TB_ALIGN_NONE },
1452 { X86::VFNMSUBPSr231rY, X86::VFNMSUBPSr231mY, TB_ALIGN_NONE },
1453 { X86::VFNMSUBPDr231rY, X86::VFNMSUBPDr231mY, TB_ALIGN_NONE },
1454 { X86::VFNMSUBPSr132rY, X86::VFNMSUBPSr132mY, TB_ALIGN_NONE },
1455 { X86::VFNMSUBPDr132rY, X86::VFNMSUBPDr132mY, TB_ALIGN_NONE },
1456 { X86::VFNMSUBPSr213rY, X86::VFNMSUBPSr213mY, TB_ALIGN_NONE },
1457 { X86::VFNMSUBPDr213rY, X86::VFNMSUBPDr213mY, TB_ALIGN_NONE },
1459 { X86::VFMADDSUBPSr231r, X86::VFMADDSUBPSr231m, TB_ALIGN_NONE },
1460 { X86::VFMADDSUBPDr231r, X86::VFMADDSUBPDr231m, TB_ALIGN_NONE },
1461 { X86::VFMADDSUBPSr132r, X86::VFMADDSUBPSr132m, TB_ALIGN_NONE },
1462 { X86::VFMADDSUBPDr132r, X86::VFMADDSUBPDr132m, TB_ALIGN_NONE },
1463 { X86::VFMADDSUBPSr213r, X86::VFMADDSUBPSr213m, TB_ALIGN_NONE },
1464 { X86::VFMADDSUBPDr213r, X86::VFMADDSUBPDr213m, TB_ALIGN_NONE },
1465 { X86::VFMADDSUBPSr231rY, X86::VFMADDSUBPSr231mY, TB_ALIGN_NONE },
1466 { X86::VFMADDSUBPDr231rY, X86::VFMADDSUBPDr231mY, TB_ALIGN_NONE },
1467 { X86::VFMADDSUBPSr132rY, X86::VFMADDSUBPSr132mY, TB_ALIGN_NONE },
1468 { X86::VFMADDSUBPDr132rY, X86::VFMADDSUBPDr132mY, TB_ALIGN_NONE },
1469 { X86::VFMADDSUBPSr213rY, X86::VFMADDSUBPSr213mY, TB_ALIGN_NONE },
1470 { X86::VFMADDSUBPDr213rY, X86::VFMADDSUBPDr213mY, TB_ALIGN_NONE },
1472 { X86::VFMSUBADDPSr231r, X86::VFMSUBADDPSr231m, TB_ALIGN_NONE },
1473 { X86::VFMSUBADDPDr231r, X86::VFMSUBADDPDr231m, TB_ALIGN_NONE },
1474 { X86::VFMSUBADDPSr132r, X86::VFMSUBADDPSr132m, TB_ALIGN_NONE },
1475 { X86::VFMSUBADDPDr132r, X86::VFMSUBADDPDr132m, TB_ALIGN_NONE },
1476 { X86::VFMSUBADDPSr213r, X86::VFMSUBADDPSr213m, TB_ALIGN_NONE },
1477 { X86::VFMSUBADDPDr213r, X86::VFMSUBADDPDr213m, TB_ALIGN_NONE },
1478 { X86::VFMSUBADDPSr231rY, X86::VFMSUBADDPSr231mY, TB_ALIGN_NONE },
1479 { X86::VFMSUBADDPDr231rY, X86::VFMSUBADDPDr231mY, TB_ALIGN_NONE },
1480 { X86::VFMSUBADDPSr132rY, X86::VFMSUBADDPSr132mY, TB_ALIGN_NONE },
1481 { X86::VFMSUBADDPDr132rY, X86::VFMSUBADDPDr132mY, TB_ALIGN_NONE },
1482 { X86::VFMSUBADDPSr213rY, X86::VFMSUBADDPSr213mY, TB_ALIGN_NONE },
1483 { X86::VFMSUBADDPDr213rY, X86::VFMSUBADDPDr213mY, TB_ALIGN_NONE },
1485 // FMA4 foldable patterns
1486 { X86::VFMADDSS4rr, X86::VFMADDSS4rm, 0 },
1487 { X86::VFMADDSD4rr, X86::VFMADDSD4rm, 0 },
1488 { X86::VFMADDPS4rr, X86::VFMADDPS4rm, TB_ALIGN_16 },
1489 { X86::VFMADDPD4rr, X86::VFMADDPD4rm, TB_ALIGN_16 },
1490 { X86::VFMADDPS4rrY, X86::VFMADDPS4rmY, TB_ALIGN_32 },
1491 { X86::VFMADDPD4rrY, X86::VFMADDPD4rmY, TB_ALIGN_32 },
1492 { X86::VFNMADDSS4rr, X86::VFNMADDSS4rm, 0 },
1493 { X86::VFNMADDSD4rr, X86::VFNMADDSD4rm, 0 },
1494 { X86::VFNMADDPS4rr, X86::VFNMADDPS4rm, TB_ALIGN_16 },
1495 { X86::VFNMADDPD4rr, X86::VFNMADDPD4rm, TB_ALIGN_16 },
1496 { X86::VFNMADDPS4rrY, X86::VFNMADDPS4rmY, TB_ALIGN_32 },
1497 { X86::VFNMADDPD4rrY, X86::VFNMADDPD4rmY, TB_ALIGN_32 },
1498 { X86::VFMSUBSS4rr, X86::VFMSUBSS4rm, 0 },
1499 { X86::VFMSUBSD4rr, X86::VFMSUBSD4rm, 0 },
1500 { X86::VFMSUBPS4rr, X86::VFMSUBPS4rm, TB_ALIGN_16 },
1501 { X86::VFMSUBPD4rr, X86::VFMSUBPD4rm, TB_ALIGN_16 },
1502 { X86::VFMSUBPS4rrY, X86::VFMSUBPS4rmY, TB_ALIGN_32 },
1503 { X86::VFMSUBPD4rrY, X86::VFMSUBPD4rmY, TB_ALIGN_32 },
1504 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4rm, 0 },
1505 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4rm, 0 },
1506 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4rm, TB_ALIGN_16 },
1507 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4rm, TB_ALIGN_16 },
1508 { X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4rmY, TB_ALIGN_32 },
1509 { X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4rmY, TB_ALIGN_32 },
1510 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4rm, TB_ALIGN_16 },
1511 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4rm, TB_ALIGN_16 },
1512 { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4rmY, TB_ALIGN_32 },
1513 { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4rmY, TB_ALIGN_32 },
1514 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4rm, TB_ALIGN_16 },
1515 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4rm, TB_ALIGN_16 },
1516 { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4rmY, TB_ALIGN_32 },
1517 { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4rmY, TB_ALIGN_32 },
1518 // AVX-512 VPERMI instructions with 3 source operands.
1519 { X86::VPERMI2Drr, X86::VPERMI2Drm, 0 },
1520 { X86::VPERMI2Qrr, X86::VPERMI2Qrm, 0 },
1521 { X86::VPERMI2PSrr, X86::VPERMI2PSrm, 0 },
1522 { X86::VPERMI2PDrr, X86::VPERMI2PDrm, 0 },
1523 { X86::VBLENDMPDZrr, X86::VBLENDMPDZrm, 0 },
1524 { X86::VBLENDMPSZrr, X86::VBLENDMPSZrm, 0 },
1525 { X86::VPBLENDMDZrr, X86::VPBLENDMDZrm, 0 },
1526 { X86::VPBLENDMQZrr, X86::VPBLENDMQZrm, 0 },
1527 { X86::VBROADCASTSSZrk, X86::VBROADCASTSSZmk, TB_NO_REVERSE },
1528 { X86::VBROADCASTSDZrk, X86::VBROADCASTSDZmk, TB_NO_REVERSE },
1529 { X86::VBROADCASTSSZ256rk, X86::VBROADCASTSSZ256mk, TB_NO_REVERSE },
1530 { X86::VBROADCASTSDZ256rk, X86::VBROADCASTSDZ256mk, TB_NO_REVERSE },
1531 { X86::VBROADCASTSSZ128rk, X86::VBROADCASTSSZ128mk, TB_NO_REVERSE },
1532 // AVX-512 arithmetic instructions
1533 { X86::VADDPSZrrkz, X86::VADDPSZrmkz, 0 },
1534 { X86::VADDPDZrrkz, X86::VADDPDZrmkz, 0 },
1535 { X86::VSUBPSZrrkz, X86::VSUBPSZrmkz, 0 },
1536 { X86::VSUBPDZrrkz, X86::VSUBPDZrmkz, 0 },
1537 { X86::VMULPSZrrkz, X86::VMULPSZrmkz, 0 },
1538 { X86::VMULPDZrrkz, X86::VMULPDZrmkz, 0 },
1539 { X86::VDIVPSZrrkz, X86::VDIVPSZrmkz, 0 },
1540 { X86::VDIVPDZrrkz, X86::VDIVPDZrmkz, 0 },
1541 { X86::VMINPSZrrkz, X86::VMINPSZrmkz, 0 },
1542 { X86::VMINPDZrrkz, X86::VMINPDZrmkz, 0 },
1543 { X86::VMAXPSZrrkz, X86::VMAXPSZrmkz, 0 },
1544 { X86::VMAXPDZrrkz, X86::VMAXPDZrmkz, 0 },
1545 // AVX-512{F,VL} arithmetic instructions 256-bit
1546 { X86::VADDPSZ256rrkz, X86::VADDPSZ256rmkz, 0 },
1547 { X86::VADDPDZ256rrkz, X86::VADDPDZ256rmkz, 0 },
1548 { X86::VSUBPSZ256rrkz, X86::VSUBPSZ256rmkz, 0 },
1549 { X86::VSUBPDZ256rrkz, X86::VSUBPDZ256rmkz, 0 },
1550 { X86::VMULPSZ256rrkz, X86::VMULPSZ256rmkz, 0 },
1551 { X86::VMULPDZ256rrkz, X86::VMULPDZ256rmkz, 0 },
1552 { X86::VDIVPSZ256rrkz, X86::VDIVPSZ256rmkz, 0 },
1553 { X86::VDIVPDZ256rrkz, X86::VDIVPDZ256rmkz, 0 },
1554 { X86::VMINPSZ256rrkz, X86::VMINPSZ256rmkz, 0 },
1555 { X86::VMINPDZ256rrkz, X86::VMINPDZ256rmkz, 0 },
1556 { X86::VMAXPSZ256rrkz, X86::VMAXPSZ256rmkz, 0 },
1557 { X86::VMAXPDZ256rrkz, X86::VMAXPDZ256rmkz, 0 },
1558 // AVX-512{F,VL} arithmetic instructions 128-bit
1559 { X86::VADDPSZ128rrkz, X86::VADDPSZ128rmkz, 0 },
1560 { X86::VADDPDZ128rrkz, X86::VADDPDZ128rmkz, 0 },
1561 { X86::VSUBPSZ128rrkz, X86::VSUBPSZ128rmkz, 0 },
1562 { X86::VSUBPDZ128rrkz, X86::VSUBPDZ128rmkz, 0 },
1563 { X86::VMULPSZ128rrkz, X86::VMULPSZ128rmkz, 0 },
1564 { X86::VMULPDZ128rrkz, X86::VMULPDZ128rmkz, 0 },
1565 { X86::VDIVPSZ128rrkz, X86::VDIVPSZ128rmkz, 0 },
1566 { X86::VDIVPDZ128rrkz, X86::VDIVPDZ128rmkz, 0 },
1567 { X86::VMINPSZ128rrkz, X86::VMINPSZ128rmkz, 0 },
1568 { X86::VMINPDZ128rrkz, X86::VMINPDZ128rmkz, 0 },
1569 { X86::VMAXPSZ128rrkz, X86::VMAXPSZ128rmkz, 0 },
1570 { X86::VMAXPDZ128rrkz, X86::VMAXPDZ128rmkz, 0 }
1571 };
1573 for (unsigned i = 0, e = array_lengthof(OpTbl3); i != e; ++i) {
1574 unsigned RegOp = OpTbl3[i].RegOp;
1575 unsigned MemOp = OpTbl3[i].MemOp;
1576 unsigned Flags = OpTbl3[i].Flags;
1577 AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
1578 RegOp, MemOp,
1579 // Index 3, folded load
1580 Flags | TB_INDEX_3 | TB_FOLDED_LOAD);
1581 }
1583 static const X86OpTblEntry OpTbl4[] = {
1584 // AVX-512 foldable instructions
1585 { X86::VADDPSZrrk, X86::VADDPSZrmk, 0 },
1586 { X86::VADDPDZrrk, X86::VADDPDZrmk, 0 },
1587 { X86::VSUBPSZrrk, X86::VSUBPSZrmk, 0 },
1588 { X86::VSUBPDZrrk, X86::VSUBPDZrmk, 0 },
1589 { X86::VMULPSZrrk, X86::VMULPSZrmk, 0 },
1590 { X86::VMULPDZrrk, X86::VMULPDZrmk, 0 },
1591 { X86::VDIVPSZrrk, X86::VDIVPSZrmk, 0 },
1592 { X86::VDIVPDZrrk, X86::VDIVPDZrmk, 0 },
1593 { X86::VMINPSZrrk, X86::VMINPSZrmk, 0 },
1594 { X86::VMINPDZrrk, X86::VMINPDZrmk, 0 },
1595 { X86::VMAXPSZrrk, X86::VMAXPSZrmk, 0 },
1596 { X86::VMAXPDZrrk, X86::VMAXPDZrmk, 0 },
1597 // AVX-512{F,VL} foldable instructions 256-bit
1598 { X86::VADDPSZ256rrk, X86::VADDPSZ256rmk, 0 },
1599 { X86::VADDPDZ256rrk, X86::VADDPDZ256rmk, 0 },
1600 { X86::VSUBPSZ256rrk, X86::VSUBPSZ256rmk, 0 },
1601 { X86::VSUBPDZ256rrk, X86::VSUBPDZ256rmk, 0 },
1602 { X86::VMULPSZ256rrk, X86::VMULPSZ256rmk, 0 },
1603 { X86::VMULPDZ256rrk, X86::VMULPDZ256rmk, 0 },
1604 { X86::VDIVPSZ256rrk, X86::VDIVPSZ256rmk, 0 },
1605 { X86::VDIVPDZ256rrk, X86::VDIVPDZ256rmk, 0 },
1606 { X86::VMINPSZ256rrk, X86::VMINPSZ256rmk, 0 },
1607 { X86::VMINPDZ256rrk, X86::VMINPDZ256rmk, 0 },
1608 { X86::VMAXPSZ256rrk, X86::VMAXPSZ256rmk, 0 },
1609 { X86::VMAXPDZ256rrk, X86::VMAXPDZ256rmk, 0 },
1610 // AVX-512{F,VL} foldable instructions 128-bit
1611 { X86::VADDPSZ128rrk, X86::VADDPSZ128rmk, 0 },
1612 { X86::VADDPDZ128rrk, X86::VADDPDZ128rmk, 0 },
1613 { X86::VSUBPSZ128rrk, X86::VSUBPSZ128rmk, 0 },
1614 { X86::VSUBPDZ128rrk, X86::VSUBPDZ128rmk, 0 },
1615 { X86::VMULPSZ128rrk, X86::VMULPSZ128rmk, 0 },
1616 { X86::VMULPDZ128rrk, X86::VMULPDZ128rmk, 0 },
1617 { X86::VDIVPSZ128rrk, X86::VDIVPSZ128rmk, 0 },
1618 { X86::VDIVPDZ128rrk, X86::VDIVPDZ128rmk, 0 },
1619 { X86::VMINPSZ128rrk, X86::VMINPSZ128rmk, 0 },
1620 { X86::VMINPDZ128rrk, X86::VMINPDZ128rmk, 0 },
1621 { X86::VMAXPSZ128rrk, X86::VMAXPSZ128rmk, 0 },
1622 { X86::VMAXPDZ128rrk, X86::VMAXPDZ128rmk, 0 }
1623 };
1625 for (unsigned i = 0, e = array_lengthof(OpTbl4); i != e; ++i) {
1626 unsigned RegOp = OpTbl4[i].RegOp;
1627 unsigned MemOp = OpTbl4[i].MemOp;
1628 unsigned Flags = OpTbl4[i].Flags;
1629 AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
1630 RegOp, MemOp,
1631 // Index 4, folded load
1632 Flags | TB_INDEX_4 | TB_FOLDED_LOAD);
1633 }
1634 }
1636 void
1637 X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
1638 MemOp2RegOpTableType &M2RTable,
1639 unsigned RegOp, unsigned MemOp, unsigned Flags) {
1640 if ((Flags & TB_NO_FORWARD) == 0) {
1641 assert(!R2MTable.count(RegOp) && "Duplicate entry!");
1642 R2MTable[RegOp] = std::make_pair(MemOp, Flags);
1643 }
1644 if ((Flags & TB_NO_REVERSE) == 0) {
1645 assert(!M2RTable.count(MemOp) &&
1646 "Duplicated entries in unfolding maps?");
1647 M2RTable[MemOp] = std::make_pair(RegOp, Flags);
1648 }
1649 }
1651 bool
1652 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
1653 unsigned &SrcReg, unsigned &DstReg,
1654 unsigned &SubIdx) const {
1655 switch (MI.getOpcode()) {
1656 default: break;
1657 case X86::MOVSX16rr8:
1658 case X86::MOVZX16rr8:
1659 case X86::MOVSX32rr8:
1660 case X86::MOVZX32rr8:
1661 case X86::MOVSX64rr8:
1662 if (!Subtarget.is64Bit())
1663 // It's not always legal to reference the low 8-bit of the larger
1664 // register in 32-bit mode.
1665 return false;
1666 case X86::MOVSX32rr16:
1667 case X86::MOVZX32rr16:
1668 case X86::MOVSX64rr16:
1669 case X86::MOVSX64rr32: {
1670 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
1671 // Be conservative.
1672 return false;
1673 SrcReg = MI.getOperand(1).getReg();
1674 DstReg = MI.getOperand(0).getReg();
1675 switch (MI.getOpcode()) {
1676 default: llvm_unreachable("Unreachable!");
1677 case X86::MOVSX16rr8:
1678 case X86::MOVZX16rr8:
1679 case X86::MOVSX32rr8:
1680 case X86::MOVZX32rr8:
1681 case X86::MOVSX64rr8:
1682 SubIdx = X86::sub_8bit;
1683 break;
1684 case X86::MOVSX32rr16:
1685 case X86::MOVZX32rr16:
1686 case X86::MOVSX64rr16:
1687 SubIdx = X86::sub_16bit;
1688 break;
1689 case X86::MOVSX64rr32:
1690 SubIdx = X86::sub_32bit;
1691 break;
1692 }
1693 return true;
1694 }
1695 }
1696 return false;
1697 }
1699 /// isFrameOperand - Return true and the FrameIndex if the specified
1700 /// operand and follow operands form a reference to the stack frame.
1701 bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
1702 int &FrameIndex) const {
1703 if (MI->getOperand(Op+X86::AddrBaseReg).isFI() &&
1704 MI->getOperand(Op+X86::AddrScaleAmt).isImm() &&
1705 MI->getOperand(Op+X86::AddrIndexReg).isReg() &&
1706 MI->getOperand(Op+X86::AddrDisp).isImm() &&
1707 MI->getOperand(Op+X86::AddrScaleAmt).getImm() == 1 &&
1708 MI->getOperand(Op+X86::AddrIndexReg).getReg() == 0 &&
1709 MI->getOperand(Op+X86::AddrDisp).getImm() == 0) {
1710 FrameIndex = MI->getOperand(Op+X86::AddrBaseReg).getIndex();
1711 return true;
1712 }
1713 return false;
1714 }
1716 static bool isFrameLoadOpcode(int Opcode) {
1717 switch (Opcode) {
1718 default:
1719 return false;
1720 case X86::MOV8rm:
1721 case X86::MOV16rm:
1722 case X86::MOV32rm:
1723 case X86::MOV64rm:
1724 case X86::LD_Fp64m:
1725 case X86::MOVSSrm:
1726 case X86::MOVSDrm:
1727 case X86::MOVAPSrm:
1728 case X86::MOVAPDrm:
1729 case X86::MOVDQArm:
1730 case X86::VMOVSSrm:
1731 case X86::VMOVSDrm:
1732 case X86::VMOVAPSrm:
1733 case X86::VMOVAPDrm:
1734 case X86::VMOVDQArm:
1735 case X86::VMOVUPSYrm:
1736 case X86::VMOVAPSYrm:
1737 case X86::VMOVUPDYrm:
1738 case X86::VMOVAPDYrm:
1739 case X86::VMOVDQUYrm:
1740 case X86::VMOVDQAYrm:
1741 case X86::MMX_MOVD64rm:
1742 case X86::MMX_MOVQ64rm:
1743 case X86::VMOVAPSZrm:
1744 case X86::VMOVUPSZrm:
1745 return true;
1746 }
1747 }
1749 static bool isFrameStoreOpcode(int Opcode) {
1750 switch (Opcode) {
1751 default: break;
1752 case X86::MOV8mr:
1753 case X86::MOV16mr:
1754 case X86::MOV32mr:
1755 case X86::MOV64mr:
1756 case X86::ST_FpP64m:
1757 case X86::MOVSSmr:
1758 case X86::MOVSDmr:
1759 case X86::MOVAPSmr:
1760 case X86::MOVAPDmr:
1761 case X86::MOVDQAmr:
1762 case X86::VMOVSSmr:
1763 case X86::VMOVSDmr:
1764 case X86::VMOVAPSmr:
1765 case X86::VMOVAPDmr:
1766 case X86::VMOVDQAmr:
1767 case X86::VMOVUPSYmr:
1768 case X86::VMOVAPSYmr:
1769 case X86::VMOVUPDYmr:
1770 case X86::VMOVAPDYmr:
1771 case X86::VMOVDQUYmr:
1772 case X86::VMOVDQAYmr:
1773 case X86::VMOVUPSZmr:
1774 case X86::VMOVAPSZmr:
1775 case X86::MMX_MOVD64mr:
1776 case X86::MMX_MOVQ64mr:
1777 case X86::MMX_MOVNTQmr:
1778 return true;
1779 }
1780 return false;
1781 }
1783 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
1784 int &FrameIndex) const {
1785 if (isFrameLoadOpcode(MI->getOpcode()))
1786 if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
1787 return MI->getOperand(0).getReg();
1788 return 0;
1789 }
1791 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
1792 int &FrameIndex) const {
1793 if (isFrameLoadOpcode(MI->getOpcode())) {
1794 unsigned Reg;
1795 if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
1796 return Reg;
1797 // Check for post-frame index elimination operations
1798 const MachineMemOperand *Dummy;
1799 return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
1800 }
1801 return 0;
1802 }
1804 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
1805 int &FrameIndex) const {
1806 if (isFrameStoreOpcode(MI->getOpcode()))
1807 if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
1808 isFrameOperand(MI, 0, FrameIndex))
1809 return MI->getOperand(X86::AddrNumOperands).getReg();
1810 return 0;
1811 }
1813 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
1814 int &FrameIndex) const {
1815 if (isFrameStoreOpcode(MI->getOpcode())) {
1816 unsigned Reg;
1817 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
1818 return Reg;
1819 // Check for post-frame index elimination operations
1820 const MachineMemOperand *Dummy;
1821 return hasStoreToStackSlot(MI, Dummy, FrameIndex);
1822 }
1823 return 0;
1824 }
1826 /// regIsPICBase - Return true if register is PIC base (i.e.g defined by
1827 /// X86::MOVPC32r.
1828 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
1829 // Don't waste compile time scanning use-def chains of physregs.
1830 if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
1831 return false;
1832 bool isPICBase = false;
1833 for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
1834 E = MRI.def_instr_end(); I != E; ++I) {
1835 MachineInstr *DefMI = &*I;
1836 if (DefMI->getOpcode() != X86::MOVPC32r)
1837 return false;
1838 assert(!isPICBase && "More than one PIC base?");
1839 isPICBase = true;
1840 }
1841 return isPICBase;
1842 }
1844 bool
1845 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
1846 AliasAnalysis *AA) const {
1847 switch (MI->getOpcode()) {
1848 default: break;
1849 case X86::MOV8rm:
1850 case X86::MOV16rm:
1851 case X86::MOV32rm:
1852 case X86::MOV64rm:
1853 case X86::LD_Fp64m:
1854 case X86::MOVSSrm:
1855 case X86::MOVSDrm:
1856 case X86::MOVAPSrm:
1857 case X86::MOVUPSrm:
1858 case X86::MOVAPDrm:
1859 case X86::MOVDQArm:
1860 case X86::MOVDQUrm:
1861 case X86::VMOVSSrm:
1862 case X86::VMOVSDrm:
1863 case X86::VMOVAPSrm:
1864 case X86::VMOVUPSrm:
1865 case X86::VMOVAPDrm:
1866 case X86::VMOVDQArm:
1867 case X86::VMOVDQUrm:
1868 case X86::VMOVAPSYrm:
1869 case X86::VMOVUPSYrm:
1870 case X86::VMOVAPDYrm:
1871 case X86::VMOVDQAYrm:
1872 case X86::VMOVDQUYrm:
1873 case X86::MMX_MOVD64rm:
1874 case X86::MMX_MOVQ64rm:
1875 case X86::FsVMOVAPSrm:
1876 case X86::FsVMOVAPDrm:
1877 case X86::FsMOVAPSrm:
1878 case X86::FsMOVAPDrm: {
1879 // Loads from constant pools are trivially rematerializable.
1880 if (MI->getOperand(1+X86::AddrBaseReg).isReg() &&
1881 MI->getOperand(1+X86::AddrScaleAmt).isImm() &&
1882 MI->getOperand(1+X86::AddrIndexReg).isReg() &&
1883 MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 &&
1884 MI->isInvariantLoad(AA)) {
1885 unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg();
1886 if (BaseReg == 0 || BaseReg == X86::RIP)
1887 return true;
1888 // Allow re-materialization of PIC load.
1889 if (!ReMatPICStubLoad && MI->getOperand(1+X86::AddrDisp).isGlobal())
1890 return false;
1891 const MachineFunction &MF = *MI->getParent()->getParent();
1892 const MachineRegisterInfo &MRI = MF.getRegInfo();
1893 return regIsPICBase(BaseReg, MRI);
1894 }
1895 return false;
1896 }
1898 case X86::LEA32r:
1899 case X86::LEA64r: {
1900 if (MI->getOperand(1+X86::AddrScaleAmt).isImm() &&
1901 MI->getOperand(1+X86::AddrIndexReg).isReg() &&
1902 MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 &&
1903 !MI->getOperand(1+X86::AddrDisp).isReg()) {
1904 // lea fi#, lea GV, etc. are all rematerializable.
1905 if (!MI->getOperand(1+X86::AddrBaseReg).isReg())
1906 return true;
1907 unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg();
1908 if (BaseReg == 0)
1909 return true;
1910 // Allow re-materialization of lea PICBase + x.
1911 const MachineFunction &MF = *MI->getParent()->getParent();
1912 const MachineRegisterInfo &MRI = MF.getRegInfo();
1913 return regIsPICBase(BaseReg, MRI);
1914 }
1915 return false;
1916 }
1917 }
1919 // All other instructions marked M_REMATERIALIZABLE are always trivially
1920 // rematerializable.
1921 return true;
1922 }
1924 bool X86InstrInfo::isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
1925 MachineBasicBlock::iterator I) const {
1926 MachineBasicBlock::iterator E = MBB.end();
1928 // For compile time consideration, if we are not able to determine the
1929 // safety after visiting 4 instructions in each direction, we will assume
1930 // it's not safe.
1931 MachineBasicBlock::iterator Iter = I;
1932 for (unsigned i = 0; Iter != E && i < 4; ++i) {
1933 bool SeenDef = false;
1934 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1935 MachineOperand &MO = Iter->getOperand(j);
1936 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
1937 SeenDef = true;
1938 if (!MO.isReg())
1939 continue;
1940 if (MO.getReg() == X86::EFLAGS) {
1941 if (MO.isUse())
1942 return false;
1943 SeenDef = true;
1944 }
1945 }
1947 if (SeenDef)
1948 // This instruction defines EFLAGS, no need to look any further.
1949 return true;
1950 ++Iter;
1951 // Skip over DBG_VALUE.
1952 while (Iter != E && Iter->isDebugValue())
1953 ++Iter;
1954 }
1956 // It is safe to clobber EFLAGS at the end of a block of no successor has it
1957 // live in.
1958 if (Iter == E) {
1959 for (MachineBasicBlock::succ_iterator SI = MBB.succ_begin(),
1960 SE = MBB.succ_end(); SI != SE; ++SI)
1961 if ((*SI)->isLiveIn(X86::EFLAGS))
1962 return false;
1963 return true;
1964 }
1966 MachineBasicBlock::iterator B = MBB.begin();
1967 Iter = I;
1968 for (unsigned i = 0; i < 4; ++i) {
1969 // If we make it to the beginning of the block, it's safe to clobber
1970 // EFLAGS iff EFLAGS is not live-in.
1971 if (Iter == B)
1972 return !MBB.isLiveIn(X86::EFLAGS);
1974 --Iter;
1975 // Skip over DBG_VALUE.
1976 while (Iter != B && Iter->isDebugValue())
1977 --Iter;
1979 bool SawKill = false;
1980 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1981 MachineOperand &MO = Iter->getOperand(j);
1982 // A register mask may clobber EFLAGS, but we should still look for a
1983 // live EFLAGS def.
1984 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
1985 SawKill = true;
1986 if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
1987 if (MO.isDef()) return MO.isDead();
1988 if (MO.isKill()) SawKill = true;
1989 }
1990 }
1992 if (SawKill)
1993 // This instruction kills EFLAGS and doesn't redefine it, so
1994 // there's no need to look further.
1995 return true;
1996 }
1998 // Conservative answer.
1999 return false;
2000 }
2002 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
2003 MachineBasicBlock::iterator I,
2004 unsigned DestReg, unsigned SubIdx,
2005 const MachineInstr *Orig,
2006 const TargetRegisterInfo &TRI) const {
2007 // MOV32r0 is implemented with a xor which clobbers condition code.
2008 // Re-materialize it as movri instructions to avoid side effects.
2009 unsigned Opc = Orig->getOpcode();
2010 if (Opc == X86::MOV32r0 && !isSafeToClobberEFLAGS(MBB, I)) {
2011 DebugLoc DL = Orig->getDebugLoc();
2012 BuildMI(MBB, I, DL, get(X86::MOV32ri)).addOperand(Orig->getOperand(0))
2013 .addImm(0);
2014 } else {
2015 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
2016 MBB.insert(I, MI);
2017 }
2019 MachineInstr *NewMI = std::prev(I);
2020 NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
2021 }
2023 /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
2024 /// is not marked dead.
2025 static bool hasLiveCondCodeDef(MachineInstr *MI) {
2026 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2027 MachineOperand &MO = MI->getOperand(i);
2028 if (MO.isReg() && MO.isDef() &&
2029 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
2030 return true;
2031 }
2032 }
2033 return false;
2034 }
2036 /// getTruncatedShiftCount - check whether the shift count for a machine operand
2037 /// is non-zero.
2038 inline static unsigned getTruncatedShiftCount(MachineInstr *MI,
2039 unsigned ShiftAmtOperandIdx) {
2040 // The shift count is six bits with the REX.W prefix and five bits without.
2041 unsigned ShiftCountMask = (MI->getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
2042 unsigned Imm = MI->getOperand(ShiftAmtOperandIdx).getImm();
2043 return Imm & ShiftCountMask;
2044 }
2046 /// isTruncatedShiftCountForLEA - check whether the given shift count is appropriate
2047 /// can be represented by a LEA instruction.
2048 inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
2049 // Left shift instructions can be transformed into load-effective-address
2050 // instructions if we can encode them appropriately.
2051 // A LEA instruction utilizes a SIB byte to encode it's scale factor.
2052 // The SIB.scale field is two bits wide which means that we can encode any
2053 // shift amount less than 4.
2054 return ShAmt < 4 && ShAmt > 0;
2055 }
2057 bool X86InstrInfo::classifyLEAReg(MachineInstr *MI, const MachineOperand &Src,
2058 unsigned Opc, bool AllowSP,
2059 unsigned &NewSrc, bool &isKill, bool &isUndef,
2060 MachineOperand &ImplicitOp) const {
2061 MachineFunction &MF = *MI->getParent()->getParent();
2062 const TargetRegisterClass *RC;
2063 if (AllowSP) {
2064 RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
2065 } else {
2066 RC = Opc != X86::LEA32r ?
2067 &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
2068 }
2069 unsigned SrcReg = Src.getReg();
2071 // For both LEA64 and LEA32 the register already has essentially the right
2072 // type (32-bit or 64-bit) we may just need to forbid SP.
2073 if (Opc != X86::LEA64_32r) {
2074 NewSrc = SrcReg;
2075 isKill = Src.isKill();
2076 isUndef = Src.isUndef();
2078 if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
2079 !MF.getRegInfo().constrainRegClass(NewSrc, RC))
2080 return false;
2082 return true;
2083 }
2085 // This is for an LEA64_32r and incoming registers are 32-bit. One way or
2086 // another we need to add 64-bit registers to the final MI.
2087 if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
2088 ImplicitOp = Src;
2089 ImplicitOp.setImplicit();
2091 NewSrc = getX86SubSuperRegister(Src.getReg(), MVT::i64);
2092 MachineBasicBlock::LivenessQueryResult LQR =
2093 MI->getParent()->computeRegisterLiveness(&getRegisterInfo(), NewSrc, MI);
2095 switch (LQR) {
2096 case MachineBasicBlock::LQR_Unknown:
2097 // We can't give sane liveness flags to the instruction, abandon LEA
2098 // formation.
2099 return false;
2100 case MachineBasicBlock::LQR_Live:
2101 isKill = MI->killsRegister(SrcReg);
2102 isUndef = false;
2103 break;
2104 default:
2105 // The physreg itself is dead, so we have to use it as an <undef>.
2106 isKill = false;
2107 isUndef = true;
2108 break;
2109 }
2110 } else {
2111 // Virtual register of the wrong class, we have to create a temporary 64-bit
2112 // vreg to feed into the LEA.
2113 NewSrc = MF.getRegInfo().createVirtualRegister(RC);
2114 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
2115 get(TargetOpcode::COPY))
2116 .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
2117 .addOperand(Src);
2119 // Which is obviously going to be dead after we're done with it.
2120 isKill = true;
2121 isUndef = false;
2122 }
2124 // We've set all the parameters without issue.
2125 return true;
2126 }
2128 /// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when
2129 /// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting
2130 /// to a 32-bit superregister and then truncating back down to a 16-bit
2131 /// subregister.
2132 MachineInstr *
2133 X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
2134 MachineFunction::iterator &MFI,
2135 MachineBasicBlock::iterator &MBBI,
2136 LiveVariables *LV) const {
2137 MachineInstr *MI = MBBI;
2138 unsigned Dest = MI->getOperand(0).getReg();
2139 unsigned Src = MI->getOperand(1).getReg();
2140 bool isDead = MI->getOperand(0).isDead();
2141 bool isKill = MI->getOperand(1).isKill();
2143 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
2144 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
2145 unsigned Opc, leaInReg;
2146 if (Subtarget.is64Bit()) {
2147 Opc = X86::LEA64_32r;
2148 leaInReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2149 } else {
2150 Opc = X86::LEA32r;
2151 leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2152 }
2154 // Build and insert into an implicit UNDEF value. This is OK because
2155 // well be shifting and then extracting the lower 16-bits.
2156 // This has the potential to cause partial register stall. e.g.
2157 // movw (%rbp,%rcx,2), %dx
2158 // leal -65(%rdx), %esi
2159 // But testing has shown this *does* help performance in 64-bit mode (at
2160 // least on modern x86 machines).
2161 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
2162 MachineInstr *InsMI =
2163 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
2164 .addReg(leaInReg, RegState::Define, X86::sub_16bit)
2165 .addReg(Src, getKillRegState(isKill));
2167 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
2168 get(Opc), leaOutReg);
2169 switch (MIOpc) {
2170 default: llvm_unreachable("Unreachable!");
2171 case X86::SHL16ri: {
2172 unsigned ShAmt = MI->getOperand(2).getImm();
2173 MIB.addReg(0).addImm(1 << ShAmt)
2174 .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
2175 break;
2176 }
2177 case X86::INC16r:
2178 case X86::INC64_16r:
2179 addRegOffset(MIB, leaInReg, true, 1);
2180 break;
2181 case X86::DEC16r:
2182 case X86::DEC64_16r:
2183 addRegOffset(MIB, leaInReg, true, -1);
2184 break;
2185 case X86::ADD16ri:
2186 case X86::ADD16ri8:
2187 case X86::ADD16ri_DB:
2188 case X86::ADD16ri8_DB:
2189 addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
2190 break;
2191 case X86::ADD16rr:
2192 case X86::ADD16rr_DB: {
2193 unsigned Src2 = MI->getOperand(2).getReg();
2194 bool isKill2 = MI->getOperand(2).isKill();
2195 unsigned leaInReg2 = 0;
2196 MachineInstr *InsMI2 = nullptr;
2197 if (Src == Src2) {
2198 // ADD16rr %reg1028<kill>, %reg1028
2199 // just a single insert_subreg.
2200 addRegReg(MIB, leaInReg, true, leaInReg, false);
2201 } else {
2202 if (Subtarget.is64Bit())
2203 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2204 else
2205 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2206 // Build and insert into an implicit UNDEF value. This is OK because
2207 // well be shifting and then extracting the lower 16-bits.
2208 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2);
2209 InsMI2 =
2210 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
2211 .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
2212 .addReg(Src2, getKillRegState(isKill2));
2213 addRegReg(MIB, leaInReg, true, leaInReg2, true);
2214 }
2215 if (LV && isKill2 && InsMI2)
2216 LV->replaceKillInstruction(Src2, MI, InsMI2);
2217 break;
2218 }
2219 }
2221 MachineInstr *NewMI = MIB;
2222 MachineInstr *ExtMI =
2223 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
2224 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
2225 .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
2227 if (LV) {
2228 // Update live variables
2229 LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
2230 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
2231 if (isKill)
2232 LV->replaceKillInstruction(Src, MI, InsMI);
2233 if (isDead)
2234 LV->replaceKillInstruction(Dest, MI, ExtMI);
2235 }
2237 return ExtMI;
2238 }
2240 /// convertToThreeAddress - This method must be implemented by targets that
2241 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
2242 /// may be able to convert a two-address instruction into a true
2243 /// three-address instruction on demand. This allows the X86 target (for
2244 /// example) to convert ADD and SHL instructions into LEA instructions if they
2245 /// would require register copies due to two-addressness.
2246 ///
2247 /// This method returns a null pointer if the transformation cannot be
2248 /// performed, otherwise it returns the new instruction.
2249 ///
2250 MachineInstr *
2251 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
2252 MachineBasicBlock::iterator &MBBI,
2253 LiveVariables *LV) const {
2254 MachineInstr *MI = MBBI;
2256 // The following opcodes also sets the condition code register(s). Only
2257 // convert them to equivalent lea if the condition code register def's
2258 // are dead!
2259 if (hasLiveCondCodeDef(MI))
2260 return nullptr;
2262 MachineFunction &MF = *MI->getParent()->getParent();
2263 // All instructions input are two-addr instructions. Get the known operands.
2264 const MachineOperand &Dest = MI->getOperand(0);
2265 const MachineOperand &Src = MI->getOperand(1);
2267 MachineInstr *NewMI = nullptr;
2268 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
2269 // we have better subtarget support, enable the 16-bit LEA generation here.
2270 // 16-bit LEA is also slow on Core2.
2271 bool DisableLEA16 = true;
2272 bool is64Bit = Subtarget.is64Bit();
2274 unsigned MIOpc = MI->getOpcode();
2275 switch (MIOpc) {
2276 case X86::SHL64ri: {
2277 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2278 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2279 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2281 // LEA can't handle RSP.
2282 if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
2283 !MF.getRegInfo().constrainRegClass(Src.getReg(),
2284 &X86::GR64_NOSPRegClass))
2285 return nullptr;
2287 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2288 .addOperand(Dest)
2289 .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
2290 break;
2291 }
2292 case X86::SHL32ri: {
2293 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2294 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2295 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2297 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2299 // LEA can't handle ESP.
2300 bool isKill, isUndef;
2301 unsigned SrcReg;
2302 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2303 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2304 SrcReg, isKill, isUndef, ImplicitOp))
2305 return nullptr;
2307 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2308 .addOperand(Dest)
2309 .addReg(0).addImm(1 << ShAmt)
2310 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
2311 .addImm(0).addReg(0);
2312 if (ImplicitOp.getReg() != 0)
2313 MIB.addOperand(ImplicitOp);
2314 NewMI = MIB;
2316 break;
2317 }
2318 case X86::SHL16ri: {
2319 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2320 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2321 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2323 if (DisableLEA16)
2324 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : nullptr;
2325 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2326 .addOperand(Dest)
2327 .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
2328 break;
2329 }
2330 default: {
2332 switch (MIOpc) {
2333 default: return nullptr;
2334 case X86::INC64r:
2335 case X86::INC32r:
2336 case X86::INC64_32r: {
2337 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2338 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
2339 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2340 bool isKill, isUndef;
2341 unsigned SrcReg;
2342 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2343 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2344 SrcReg, isKill, isUndef, ImplicitOp))
2345 return nullptr;
2347 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2348 .addOperand(Dest)
2349 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef));
2350 if (ImplicitOp.getReg() != 0)
2351 MIB.addOperand(ImplicitOp);
2353 NewMI = addOffset(MIB, 1);
2354 break;
2355 }
2356 case X86::INC16r:
2357 case X86::INC64_16r:
2358 if (DisableLEA16)
2359 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2360 : nullptr;
2361 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2362 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2363 .addOperand(Dest).addOperand(Src), 1);
2364 break;
2365 case X86::DEC64r:
2366 case X86::DEC32r:
2367 case X86::DEC64_32r: {
2368 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2369 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
2370 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2372 bool isKill, isUndef;
2373 unsigned SrcReg;
2374 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2375 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2376 SrcReg, isKill, isUndef, ImplicitOp))
2377 return nullptr;
2379 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2380 .addOperand(Dest)
2381 .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2382 if (ImplicitOp.getReg() != 0)
2383 MIB.addOperand(ImplicitOp);
2385 NewMI = addOffset(MIB, -1);
2387 break;
2388 }
2389 case X86::DEC16r:
2390 case X86::DEC64_16r:
2391 if (DisableLEA16)
2392 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2393 : nullptr;
2394 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2395 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2396 .addOperand(Dest).addOperand(Src), -1);
2397 break;
2398 case X86::ADD64rr:
2399 case X86::ADD64rr_DB:
2400 case X86::ADD32rr:
2401 case X86::ADD32rr_DB: {
2402 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2403 unsigned Opc;
2404 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
2405 Opc = X86::LEA64r;
2406 else
2407 Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2409 bool isKill, isUndef;
2410 unsigned SrcReg;
2411 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2412 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2413 SrcReg, isKill, isUndef, ImplicitOp))
2414 return nullptr;
2416 const MachineOperand &Src2 = MI->getOperand(2);
2417 bool isKill2, isUndef2;
2418 unsigned SrcReg2;
2419 MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
2420 if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
2421 SrcReg2, isKill2, isUndef2, ImplicitOp2))
2422 return nullptr;
2424 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2425 .addOperand(Dest);
2426 if (ImplicitOp.getReg() != 0)
2427 MIB.addOperand(ImplicitOp);
2428 if (ImplicitOp2.getReg() != 0)
2429 MIB.addOperand(ImplicitOp2);
2431 NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
2433 // Preserve undefness of the operands.
2434 NewMI->getOperand(1).setIsUndef(isUndef);
2435 NewMI->getOperand(3).setIsUndef(isUndef2);
2437 if (LV && Src2.isKill())
2438 LV->replaceKillInstruction(SrcReg2, MI, NewMI);
2439 break;
2440 }
2441 case X86::ADD16rr:
2442 case X86::ADD16rr_DB: {
2443 if (DisableLEA16)
2444 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2445 : nullptr;
2446 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2447 unsigned Src2 = MI->getOperand(2).getReg();
2448 bool isKill2 = MI->getOperand(2).isKill();
2449 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2450 .addOperand(Dest),
2451 Src.getReg(), Src.isKill(), Src2, isKill2);
2453 // Preserve undefness of the operands.
2454 bool isUndef = MI->getOperand(1).isUndef();
2455 bool isUndef2 = MI->getOperand(2).isUndef();
2456 NewMI->getOperand(1).setIsUndef(isUndef);
2457 NewMI->getOperand(3).setIsUndef(isUndef2);
2459 if (LV && isKill2)
2460 LV->replaceKillInstruction(Src2, MI, NewMI);
2461 break;
2462 }
2463 case X86::ADD64ri32:
2464 case X86::ADD64ri8:
2465 case X86::ADD64ri32_DB:
2466 case X86::ADD64ri8_DB:
2467 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2468 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2469 .addOperand(Dest).addOperand(Src),
2470 MI->getOperand(2).getImm());
2471 break;
2472 case X86::ADD32ri:
2473 case X86::ADD32ri8:
2474 case X86::ADD32ri_DB:
2475 case X86::ADD32ri8_DB: {
2476 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2477 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2479 bool isKill, isUndef;
2480 unsigned SrcReg;
2481 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2482 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2483 SrcReg, isKill, isUndef, ImplicitOp))
2484 return nullptr;
2486 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2487 .addOperand(Dest)
2488 .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2489 if (ImplicitOp.getReg() != 0)
2490 MIB.addOperand(ImplicitOp);
2492 NewMI = addOffset(MIB, MI->getOperand(2).getImm());
2493 break;
2494 }
2495 case X86::ADD16ri:
2496 case X86::ADD16ri8:
2497 case X86::ADD16ri_DB:
2498 case X86::ADD16ri8_DB:
2499 if (DisableLEA16)
2500 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2501 : nullptr;
2502 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2503 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2504 .addOperand(Dest).addOperand(Src),
2505 MI->getOperand(2).getImm());
2506 break;
2507 }
2508 }
2509 }
2511 if (!NewMI) return nullptr;
2513 if (LV) { // Update live variables
2514 if (Src.isKill())
2515 LV->replaceKillInstruction(Src.getReg(), MI, NewMI);
2516 if (Dest.isDead())
2517 LV->replaceKillInstruction(Dest.getReg(), MI, NewMI);
2518 }
2520 MFI->insert(MBBI, NewMI); // Insert the new inst
2521 return NewMI;
2522 }
2524 /// commuteInstruction - We have a few instructions that must be hacked on to
2525 /// commute them.
2526 ///
2527 MachineInstr *
2528 X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
2529 switch (MI->getOpcode()) {
2530 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
2531 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
2532 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
2533 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
2534 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
2535 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
2536 unsigned Opc;
2537 unsigned Size;
2538 switch (MI->getOpcode()) {
2539 default: llvm_unreachable("Unreachable!");
2540 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
2541 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
2542 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
2543 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
2544 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
2545 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
2546 }
2547 unsigned Amt = MI->getOperand(3).getImm();
2548 if (NewMI) {
2549 MachineFunction &MF = *MI->getParent()->getParent();
2550 MI = MF.CloneMachineInstr(MI);
2551 NewMI = false;
2552 }
2553 MI->setDesc(get(Opc));
2554 MI->getOperand(3).setImm(Size-Amt);
2555 return TargetInstrInfo::commuteInstruction(MI, NewMI);
2556 }
2557 case X86::BLENDPDrri:
2558 case X86::BLENDPSrri:
2559 case X86::PBLENDWrri:
2560 case X86::VBLENDPDrri:
2561 case X86::VBLENDPSrri:
2562 case X86::VBLENDPDYrri:
2563 case X86::VBLENDPSYrri:
2564 case X86::VPBLENDDrri:
2565 case X86::VPBLENDWrri:
2566 case X86::VPBLENDDYrri:
2567 case X86::VPBLENDWYrri:{
2568 unsigned Mask;
2569 switch (MI->getOpcode()) {
2570 default: llvm_unreachable("Unreachable!");
2571 case X86::BLENDPDrri: Mask = 0x03; break;
2572 case X86::BLENDPSrri: Mask = 0x0F; break;
2573 case X86::PBLENDWrri: Mask = 0xFF; break;
2574 case X86::VBLENDPDrri: Mask = 0x03; break;
2575 case X86::VBLENDPSrri: Mask = 0x0F; break;
2576 case X86::VBLENDPDYrri: Mask = 0x0F; break;
2577 case X86::VBLENDPSYrri: Mask = 0xFF; break;
2578 case X86::VPBLENDDrri: Mask = 0x0F; break;
2579 case X86::VPBLENDWrri: Mask = 0xFF; break;
2580 case X86::VPBLENDDYrri: Mask = 0xFF; break;
2581 case X86::VPBLENDWYrri: Mask = 0xFF; break;
2582 }
2583 // Only the least significant bits of Imm are used.
2584 unsigned Imm = MI->getOperand(3).getImm() & Mask;
2585 if (NewMI) {
2586 MachineFunction &MF = *MI->getParent()->getParent();
2587 MI = MF.CloneMachineInstr(MI);
2588 NewMI = false;
2589 }
2590 MI->getOperand(3).setImm(Mask ^ Imm);
2591 return TargetInstrInfo::commuteInstruction(MI, NewMI);
2592 }
2593 case X86::CMOVB16rr: case X86::CMOVB32rr: case X86::CMOVB64rr:
2594 case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
2595 case X86::CMOVE16rr: case X86::CMOVE32rr: case X86::CMOVE64rr:
2596 case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
2597 case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
2598 case X86::CMOVA16rr: case X86::CMOVA32rr: case X86::CMOVA64rr:
2599 case X86::CMOVL16rr: case X86::CMOVL32rr: case X86::CMOVL64rr:
2600 case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
2601 case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
2602 case X86::CMOVG16rr: case X86::CMOVG32rr: case X86::CMOVG64rr:
2603 case X86::CMOVS16rr: case X86::CMOVS32rr: case X86::CMOVS64rr:
2604 case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
2605 case X86::CMOVP16rr: case X86::CMOVP32rr: case X86::CMOVP64rr:
2606 case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
2607 case X86::CMOVO16rr: case X86::CMOVO32rr: case X86::CMOVO64rr:
2608 case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
2609 unsigned Opc;
2610 switch (MI->getOpcode()) {
2611 default: llvm_unreachable("Unreachable!");
2612 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
2613 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
2614 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
2615 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
2616 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
2617 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
2618 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
2619 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
2620 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
2621 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
2622 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
2623 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
2624 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
2625 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
2626 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
2627 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
2628 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
2629 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
2630 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
2631 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
2632 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
2633 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
2634 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
2635 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
2636 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
2637 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
2638 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
2639 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
2640 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
2641 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
2642 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
2643 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
2644 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break;
2645 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
2646 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
2647 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
2648 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
2649 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
2650 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break;
2651 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
2652 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
2653 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
2654 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
2655 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
2656 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break;
2657 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
2658 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
2659 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
2660 }
2661 if (NewMI) {
2662 MachineFunction &MF = *MI->getParent()->getParent();
2663 MI = MF.CloneMachineInstr(MI);
2664 NewMI = false;
2665 }
2666 MI->setDesc(get(Opc));
2667 // Fallthrough intended.
2668 }
2669 default:
2670 return TargetInstrInfo::commuteInstruction(MI, NewMI);
2671 }
2672 }
2674 bool X86InstrInfo::findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
2675 unsigned &SrcOpIdx2) const {
2676 switch (MI->getOpcode()) {
2677 case X86::BLENDPDrri:
2678 case X86::BLENDPSrri:
2679 case X86::PBLENDWrri:
2680 case X86::VBLENDPDrri:
2681 case X86::VBLENDPSrri:
2682 case X86::VBLENDPDYrri:
2683 case X86::VBLENDPSYrri:
2684 case X86::VPBLENDDrri:
2685 case X86::VPBLENDDYrri:
2686 case X86::VPBLENDWrri:
2687 case X86::VPBLENDWYrri:
2688 SrcOpIdx1 = 1;
2689 SrcOpIdx2 = 2;
2690 return true;
2691 case X86::VFMADDPDr231r:
2692 case X86::VFMADDPSr231r:
2693 case X86::VFMADDSDr231r:
2694 case X86::VFMADDSSr231r:
2695 case X86::VFMSUBPDr231r:
2696 case X86::VFMSUBPSr231r:
2697 case X86::VFMSUBSDr231r:
2698 case X86::VFMSUBSSr231r:
2699 case X86::VFNMADDPDr231r:
2700 case X86::VFNMADDPSr231r:
2701 case X86::VFNMADDSDr231r:
2702 case X86::VFNMADDSSr231r:
2703 case X86::VFNMSUBPDr231r:
2704 case X86::VFNMSUBPSr231r:
2705 case X86::VFNMSUBSDr231r:
2706 case X86::VFNMSUBSSr231r:
2707 case X86::VFMADDPDr231rY:
2708 case X86::VFMADDPSr231rY:
2709 case X86::VFMSUBPDr231rY:
2710 case X86::VFMSUBPSr231rY:
2711 case X86::VFNMADDPDr231rY:
2712 case X86::VFNMADDPSr231rY:
2713 case X86::VFNMSUBPDr231rY:
2714 case X86::VFNMSUBPSr231rY:
2715 SrcOpIdx1 = 2;
2716 SrcOpIdx2 = 3;
2717 return true;
2718 default:
2719 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2720 }
2721 }
2723 static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) {
2724 switch (BrOpc) {
2725 default: return X86::COND_INVALID;
2726 case X86::JE_4: return X86::COND_E;
2727 case X86::JNE_4: return X86::COND_NE;
2728 case X86::JL_4: return X86::COND_L;
2729 case X86::JLE_4: return X86::COND_LE;
2730 case X86::JG_4: return X86::COND_G;
2731 case X86::JGE_4: return X86::COND_GE;
2732 case X86::JB_4: return X86::COND_B;
2733 case X86::JBE_4: return X86::COND_BE;
2734 case X86::JA_4: return X86::COND_A;
2735 case X86::JAE_4: return X86::COND_AE;
2736 case X86::JS_4: return X86::COND_S;
2737 case X86::JNS_4: return X86::COND_NS;
2738 case X86::JP_4: return X86::COND_P;
2739 case X86::JNP_4: return X86::COND_NP;
2740 case X86::JO_4: return X86::COND_O;
2741 case X86::JNO_4: return X86::COND_NO;
2742 }
2743 }
2745 /// getCondFromSETOpc - return condition code of a SET opcode.
2746 static X86::CondCode getCondFromSETOpc(unsigned Opc) {
2747 switch (Opc) {
2748 default: return X86::COND_INVALID;
2749 case X86::SETAr: case X86::SETAm: return X86::COND_A;
2750 case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
2751 case X86::SETBr: case X86::SETBm: return X86::COND_B;
2752 case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
2753 case X86::SETEr: case X86::SETEm: return X86::COND_E;
2754 case X86::SETGr: case X86::SETGm: return X86::COND_G;
2755 case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
2756 case X86::SETLr: case X86::SETLm: return X86::COND_L;
2757 case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
2758 case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
2759 case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
2760 case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
2761 case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
2762 case X86::SETOr: case X86::SETOm: return X86::COND_O;
2763 case X86::SETPr: case X86::SETPm: return X86::COND_P;
2764 case X86::SETSr: case X86::SETSm: return X86::COND_S;
2765 }
2766 }
2768 /// getCondFromCmovOpc - return condition code of a CMov opcode.
2769 X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) {
2770 switch (Opc) {
2771 default: return X86::COND_INVALID;
2772 case X86::CMOVA16rm: case X86::CMOVA16rr: case X86::CMOVA32rm:
2773 case X86::CMOVA32rr: case X86::CMOVA64rm: case X86::CMOVA64rr:
2774 return X86::COND_A;
2775 case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
2776 case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
2777 return X86::COND_AE;
2778 case X86::CMOVB16rm: case X86::CMOVB16rr: case X86::CMOVB32rm:
2779 case X86::CMOVB32rr: case X86::CMOVB64rm: case X86::CMOVB64rr:
2780 return X86::COND_B;
2781 case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
2782 case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
2783 return X86::COND_BE;
2784 case X86::CMOVE16rm: case X86::CMOVE16rr: case X86::CMOVE32rm:
2785 case X86::CMOVE32rr: case X86::CMOVE64rm: case X86::CMOVE64rr:
2786 return X86::COND_E;
2787 case X86::CMOVG16rm: case X86::CMOVG16rr: case X86::CMOVG32rm:
2788 case X86::CMOVG32rr: case X86::CMOVG64rm: case X86::CMOVG64rr:
2789 return X86::COND_G;
2790 case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
2791 case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
2792 return X86::COND_GE;
2793 case X86::CMOVL16rm: case X86::CMOVL16rr: case X86::CMOVL32rm:
2794 case X86::CMOVL32rr: case X86::CMOVL64rm: case X86::CMOVL64rr:
2795 return X86::COND_L;
2796 case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
2797 case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
2798 return X86::COND_LE;
2799 case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
2800 case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
2801 return X86::COND_NE;
2802 case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
2803 case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
2804 return X86::COND_NO;
2805 case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
2806 case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
2807 return X86::COND_NP;
2808 case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
2809 case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
2810 return X86::COND_NS;
2811 case X86::CMOVO16rm: case X86::CMOVO16rr: case X86::CMOVO32rm:
2812 case X86::CMOVO32rr: case X86::CMOVO64rm: case X86::CMOVO64rr:
2813 return X86::COND_O;
2814 case X86::CMOVP16rm: case X86::CMOVP16rr: case X86::CMOVP32rm:
2815 case X86::CMOVP32rr: case X86::CMOVP64rm: case X86::CMOVP64rr:
2816 return X86::COND_P;
2817 case X86::CMOVS16rm: case X86::CMOVS16rr: case X86::CMOVS32rm:
2818 case X86::CMOVS32rr: case X86::CMOVS64rm: case X86::CMOVS64rr:
2819 return X86::COND_S;
2820 }
2821 }
2823 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
2824 switch (CC) {
2825 default: llvm_unreachable("Illegal condition code!");
2826 case X86::COND_E: return X86::JE_4;
2827 case X86::COND_NE: return X86::JNE_4;
2828 case X86::COND_L: return X86::JL_4;
2829 case X86::COND_LE: return X86::JLE_4;
2830 case X86::COND_G: return X86::JG_4;
2831 case X86::COND_GE: return X86::JGE_4;
2832 case X86::COND_B: return X86::JB_4;
2833 case X86::COND_BE: return X86::JBE_4;
2834 case X86::COND_A: return X86::JA_4;
2835 case X86::COND_AE: return X86::JAE_4;
2836 case X86::COND_S: return X86::JS_4;
2837 case X86::COND_NS: return X86::JNS_4;
2838 case X86::COND_P: return X86::JP_4;
2839 case X86::COND_NP: return X86::JNP_4;
2840 case X86::COND_O: return X86::JO_4;
2841 case X86::COND_NO: return X86::JNO_4;
2842 }
2843 }
2845 /// GetOppositeBranchCondition - Return the inverse of the specified condition,
2846 /// e.g. turning COND_E to COND_NE.
2847 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
2848 switch (CC) {
2849 default: llvm_unreachable("Illegal condition code!");
2850 case X86::COND_E: return X86::COND_NE;
2851 case X86::COND_NE: return X86::COND_E;
2852 case X86::COND_L: return X86::COND_GE;
2853 case X86::COND_LE: return X86::COND_G;
2854 case X86::COND_G: return X86::COND_LE;
2855 case X86::COND_GE: return X86::COND_L;
2856 case X86::COND_B: return X86::COND_AE;
2857 case X86::COND_BE: return X86::COND_A;
2858 case X86::COND_A: return X86::COND_BE;
2859 case X86::COND_AE: return X86::COND_B;
2860 case X86::COND_S: return X86::COND_NS;
2861 case X86::COND_NS: return X86::COND_S;
2862 case X86::COND_P: return X86::COND_NP;
2863 case X86::COND_NP: return X86::COND_P;
2864 case X86::COND_O: return X86::COND_NO;
2865 case X86::COND_NO: return X86::COND_O;
2866 }
2867 }
2869 /// getSwappedCondition - assume the flags are set by MI(a,b), return
2870 /// the condition code if we modify the instructions such that flags are
2871 /// set by MI(b,a).
2872 static X86::CondCode getSwappedCondition(X86::CondCode CC) {
2873 switch (CC) {
2874 default: return X86::COND_INVALID;
2875 case X86::COND_E: return X86::COND_E;
2876 case X86::COND_NE: return X86::COND_NE;
2877 case X86::COND_L: return X86::COND_G;
2878 case X86::COND_LE: return X86::COND_GE;
2879 case X86::COND_G: return X86::COND_L;
2880 case X86::COND_GE: return X86::COND_LE;
2881 case X86::COND_B: return X86::COND_A;
2882 case X86::COND_BE: return X86::COND_AE;
2883 case X86::COND_A: return X86::COND_B;
2884 case X86::COND_AE: return X86::COND_BE;
2885 }
2886 }
2888 /// getSETFromCond - Return a set opcode for the given condition and
2889 /// whether it has memory operand.
2890 unsigned X86::getSETFromCond(CondCode CC, bool HasMemoryOperand) {
2891 static const uint16_t Opc[16][2] = {
2892 { X86::SETAr, X86::SETAm },
2893 { X86::SETAEr, X86::SETAEm },
2894 { X86::SETBr, X86::SETBm },
2895 { X86::SETBEr, X86::SETBEm },
2896 { X86::SETEr, X86::SETEm },
2897 { X86::SETGr, X86::SETGm },
2898 { X86::SETGEr, X86::SETGEm },
2899 { X86::SETLr, X86::SETLm },
2900 { X86::SETLEr, X86::SETLEm },
2901 { X86::SETNEr, X86::SETNEm },
2902 { X86::SETNOr, X86::SETNOm },
2903 { X86::SETNPr, X86::SETNPm },
2904 { X86::SETNSr, X86::SETNSm },
2905 { X86::SETOr, X86::SETOm },
2906 { X86::SETPr, X86::SETPm },
2907 { X86::SETSr, X86::SETSm }
2908 };
2910 assert(CC <= LAST_VALID_COND && "Can only handle standard cond codes");
2911 return Opc[CC][HasMemoryOperand ? 1 : 0];
2912 }
2914 /// getCMovFromCond - Return a cmov opcode for the given condition,
2915 /// register size in bytes, and operand type.
2916 unsigned X86::getCMovFromCond(CondCode CC, unsigned RegBytes,
2917 bool HasMemoryOperand) {
2918 static const uint16_t Opc[32][3] = {
2919 { X86::CMOVA16rr, X86::CMOVA32rr, X86::CMOVA64rr },
2920 { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
2921 { X86::CMOVB16rr, X86::CMOVB32rr, X86::CMOVB64rr },
2922 { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
2923 { X86::CMOVE16rr, X86::CMOVE32rr, X86::CMOVE64rr },
2924 { X86::CMOVG16rr, X86::CMOVG32rr, X86::CMOVG64rr },
2925 { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
2926 { X86::CMOVL16rr, X86::CMOVL32rr, X86::CMOVL64rr },
2927 { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
2928 { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
2929 { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
2930 { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
2931 { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
2932 { X86::CMOVO16rr, X86::CMOVO32rr, X86::CMOVO64rr },
2933 { X86::CMOVP16rr, X86::CMOVP32rr, X86::CMOVP64rr },
2934 { X86::CMOVS16rr, X86::CMOVS32rr, X86::CMOVS64rr },
2935 { X86::CMOVA16rm, X86::CMOVA32rm, X86::CMOVA64rm },
2936 { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
2937 { X86::CMOVB16rm, X86::CMOVB32rm, X86::CMOVB64rm },
2938 { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
2939 { X86::CMOVE16rm, X86::CMOVE32rm, X86::CMOVE64rm },
2940 { X86::CMOVG16rm, X86::CMOVG32rm, X86::CMOVG64rm },
2941 { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
2942 { X86::CMOVL16rm, X86::CMOVL32rm, X86::CMOVL64rm },
2943 { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
2944 { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
2945 { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
2946 { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
2947 { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
2948 { X86::CMOVO16rm, X86::CMOVO32rm, X86::CMOVO64rm },
2949 { X86::CMOVP16rm, X86::CMOVP32rm, X86::CMOVP64rm },
2950 { X86::CMOVS16rm, X86::CMOVS32rm, X86::CMOVS64rm }
2951 };
2953 assert(CC < 16 && "Can only handle standard cond codes");
2954 unsigned Idx = HasMemoryOperand ? 16+CC : CC;
2955 switch(RegBytes) {
2956 default: llvm_unreachable("Illegal register size!");
2957 case 2: return Opc[Idx][0];
2958 case 4: return Opc[Idx][1];
2959 case 8: return Opc[Idx][2];
2960 }
2961 }
2963 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
2964 if (!MI->isTerminator()) return false;
2966 // Conditional branch is a special case.
2967 if (MI->isBranch() && !MI->isBarrier())
2968 return true;
2969 if (!MI->isPredicable())
2970 return true;
2971 return !isPredicated(MI);
2972 }
2974 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
2975 MachineBasicBlock *&TBB,
2976 MachineBasicBlock *&FBB,
2977 SmallVectorImpl<MachineOperand> &Cond,
2978 bool AllowModify) const {
2979 // Start from the bottom of the block and work up, examining the
2980 // terminator instructions.
2981 MachineBasicBlock::iterator I = MBB.end();
2982 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
2983 while (I != MBB.begin()) {
2984 --I;
2985 if (I->isDebugValue())
2986 continue;
2988 // Working from the bottom, when we see a non-terminator instruction, we're
2989 // done.
2990 if (!isUnpredicatedTerminator(I))
2991 break;
2993 // A terminator that isn't a branch can't easily be handled by this
2994 // analysis.
2995 if (!I->isBranch())
2996 return true;
2998 // Handle unconditional branches.
2999 if (I->getOpcode() == X86::JMP_4) {
3000 UnCondBrIter = I;
3002 if (!AllowModify) {
3003 TBB = I->getOperand(0).getMBB();
3004 continue;
3005 }
3007 // If the block has any instructions after a JMP, delete them.
3008 while (std::next(I) != MBB.end())
3009 std::next(I)->eraseFromParent();
3011 Cond.clear();
3012 FBB = nullptr;
3014 // Delete the JMP if it's equivalent to a fall-through.
3015 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
3016 TBB = nullptr;
3017 I->eraseFromParent();
3018 I = MBB.end();
3019 UnCondBrIter = MBB.end();
3020 continue;
3021 }
3023 // TBB is used to indicate the unconditional destination.
3024 TBB = I->getOperand(0).getMBB();
3025 continue;
3026 }
3028 // Handle conditional branches.
3029 X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode());
3030 if (BranchCode == X86::COND_INVALID)
3031 return true; // Can't handle indirect branch.
3033 // Working from the bottom, handle the first conditional branch.
3034 if (Cond.empty()) {
3035 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
3036 if (AllowModify && UnCondBrIter != MBB.end() &&
3037 MBB.isLayoutSuccessor(TargetBB)) {
3038 // If we can modify the code and it ends in something like:
3039 //
3040 // jCC L1
3041 // jmp L2
3042 // L1:
3043 // ...
3044 // L2:
3045 //
3046 // Then we can change this to:
3047 //
3048 // jnCC L2
3049 // L1:
3050 // ...
3051 // L2:
3052 //
3053 // Which is a bit more efficient.
3054 // We conditionally jump to the fall-through block.
3055 BranchCode = GetOppositeBranchCondition(BranchCode);
3056 unsigned JNCC = GetCondBranchFromCond(BranchCode);
3057 MachineBasicBlock::iterator OldInst = I;
3059 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
3060 .addMBB(UnCondBrIter->getOperand(0).getMBB());
3061 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_4))
3062 .addMBB(TargetBB);
3064 OldInst->eraseFromParent();
3065 UnCondBrIter->eraseFromParent();
3067 // Restart the analysis.
3068 UnCondBrIter = MBB.end();
3069 I = MBB.end();
3070 continue;
3071 }
3073 FBB = TBB;
3074 TBB = I->getOperand(0).getMBB();
3075 Cond.push_back(MachineOperand::CreateImm(BranchCode));
3076 continue;
3077 }
3079 // Handle subsequent conditional branches. Only handle the case where all
3080 // conditional branches branch to the same destination and their condition
3081 // opcodes fit one of the special multi-branch idioms.
3082 assert(Cond.size() == 1);
3083 assert(TBB);
3085 // Only handle the case where all conditional branches branch to the same
3086 // destination.
3087 if (TBB != I->getOperand(0).getMBB())
3088 return true;
3090 // If the conditions are the same, we can leave them alone.
3091 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
3092 if (OldBranchCode == BranchCode)
3093 continue;
3095 // If they differ, see if they fit one of the known patterns. Theoretically,
3096 // we could handle more patterns here, but we shouldn't expect to see them
3097 // if instruction selection has done a reasonable job.
3098 if ((OldBranchCode == X86::COND_NP &&
3099 BranchCode == X86::COND_E) ||
3100 (OldBranchCode == X86::COND_E &&
3101 BranchCode == X86::COND_NP))
3102 BranchCode = X86::COND_NP_OR_E;
3103 else if ((OldBranchCode == X86::COND_P &&
3104 BranchCode == X86::COND_NE) ||
3105 (OldBranchCode == X86::COND_NE &&
3106 BranchCode == X86::COND_P))
3107 BranchCode = X86::COND_NE_OR_P;
3108 else
3109 return true;
3111 // Update the MachineOperand.
3112 Cond[0].setImm(BranchCode);
3113 }
3115 return false;
3116 }
3118 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
3119 MachineBasicBlock::iterator I = MBB.end();
3120 unsigned Count = 0;
3122 while (I != MBB.begin()) {
3123 --I;
3124 if (I->isDebugValue())
3125 continue;
3126 if (I->getOpcode() != X86::JMP_4 &&
3127 getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
3128 break;
3129 // Remove the branch.
3130 I->eraseFromParent();
3131 I = MBB.end();
3132 ++Count;
3133 }
3135 return Count;
3136 }
3138 unsigned
3139 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
3140 MachineBasicBlock *FBB,
3141 const SmallVectorImpl<MachineOperand> &Cond,
3142 DebugLoc DL) const {
3143 // Shouldn't be a fall through.
3144 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
3145 assert((Cond.size() == 1 || Cond.size() == 0) &&
3146 "X86 branch conditions have one component!");
3148 if (Cond.empty()) {
3149 // Unconditional branch?
3150 assert(!FBB && "Unconditional branch with multiple successors!");
3151 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(TBB);
3152 return 1;
3153 }
3155 // Conditional branch.
3156 unsigned Count = 0;
3157 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
3158 switch (CC) {
3159 case X86::COND_NP_OR_E:
3160 // Synthesize NP_OR_E with two branches.
3161 BuildMI(&MBB, DL, get(X86::JNP_4)).addMBB(TBB);
3162 ++Count;
3163 BuildMI(&MBB, DL, get(X86::JE_4)).addMBB(TBB);
3164 ++Count;
3165 break;
3166 case X86::COND_NE_OR_P:
3167 // Synthesize NE_OR_P with two branches.
3168 BuildMI(&MBB, DL, get(X86::JNE_4)).addMBB(TBB);
3169 ++Count;
3170 BuildMI(&MBB, DL, get(X86::JP_4)).addMBB(TBB);
3171 ++Count;
3172 break;
3173 default: {
3174 unsigned Opc = GetCondBranchFromCond(CC);
3175 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
3176 ++Count;
3177 }
3178 }
3179 if (FBB) {
3180 // Two-way Conditional branch. Insert the second branch.
3181 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(FBB);
3182 ++Count;
3183 }
3184 return Count;
3185 }
3187 bool X86InstrInfo::
3188 canInsertSelect(const MachineBasicBlock &MBB,
3189 const SmallVectorImpl<MachineOperand> &Cond,
3190 unsigned TrueReg, unsigned FalseReg,
3191 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
3192 // Not all subtargets have cmov instructions.
3193 if (!Subtarget.hasCMov())
3194 return false;
3195 if (Cond.size() != 1)
3196 return false;
3197 // We cannot do the composite conditions, at least not in SSA form.
3198 if ((X86::CondCode)Cond[0].getImm() > X86::COND_S)
3199 return false;
3201 // Check register classes.
3202 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3203 const TargetRegisterClass *RC =
3204 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
3205 if (!RC)
3206 return false;
3208 // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
3209 if (X86::GR16RegClass.hasSubClassEq(RC) ||
3210 X86::GR32RegClass.hasSubClassEq(RC) ||
3211 X86::GR64RegClass.hasSubClassEq(RC)) {
3212 // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
3213 // Bridge. Probably Ivy Bridge as well.
3214 CondCycles = 2;
3215 TrueCycles = 2;
3216 FalseCycles = 2;
3217 return true;
3218 }
3220 // Can't do vectors.
3221 return false;
3222 }
3224 void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
3225 MachineBasicBlock::iterator I, DebugLoc DL,
3226 unsigned DstReg,
3227 const SmallVectorImpl<MachineOperand> &Cond,
3228 unsigned TrueReg, unsigned FalseReg) const {
3229 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3230 assert(Cond.size() == 1 && "Invalid Cond array");
3231 unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
3232 MRI.getRegClass(DstReg)->getSize(),
3233 false/*HasMemoryOperand*/);
3234 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
3235 }
3237 /// isHReg - Test if the given register is a physical h register.
3238 static bool isHReg(unsigned Reg) {
3239 return X86::GR8_ABCD_HRegClass.contains(Reg);
3240 }
3242 // Try and copy between VR128/VR64 and GR64 registers.
3243 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
3244 const X86Subtarget &Subtarget) {
3246 // SrcReg(VR128) -> DestReg(GR64)
3247 // SrcReg(VR64) -> DestReg(GR64)
3248 // SrcReg(GR64) -> DestReg(VR128)
3249 // SrcReg(GR64) -> DestReg(VR64)
3251 bool HasAVX = Subtarget.hasAVX();
3252 bool HasAVX512 = Subtarget.hasAVX512();
3253 if (X86::GR64RegClass.contains(DestReg)) {
3254 if (X86::VR128XRegClass.contains(SrcReg))
3255 // Copy from a VR128 register to a GR64 register.
3256 return HasAVX512 ? X86::VMOVPQIto64Zrr: (HasAVX ? X86::VMOVPQIto64rr :
3257 X86::MOVPQIto64rr);
3258 if (X86::VR64RegClass.contains(SrcReg))
3259 // Copy from a VR64 register to a GR64 register.
3260 return X86::MOVSDto64rr;
3261 } else if (X86::GR64RegClass.contains(SrcReg)) {
3262 // Copy from a GR64 register to a VR128 register.
3263 if (X86::VR128XRegClass.contains(DestReg))
3264 return HasAVX512 ? X86::VMOV64toPQIZrr: (HasAVX ? X86::VMOV64toPQIrr :
3265 X86::MOV64toPQIrr);
3266 // Copy from a GR64 register to a VR64 register.
3267 if (X86::VR64RegClass.contains(DestReg))
3268 return X86::MOV64toSDrr;
3269 }
3271 // SrcReg(FR32) -> DestReg(GR32)
3272 // SrcReg(GR32) -> DestReg(FR32)
3274 if (X86::GR32RegClass.contains(DestReg) && X86::FR32XRegClass.contains(SrcReg))
3275 // Copy from a FR32 register to a GR32 register.
3276 return HasAVX512 ? X86::VMOVSS2DIZrr : (HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr);
3278 if (X86::FR32XRegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg))
3279 // Copy from a GR32 register to a FR32 register.
3280 return HasAVX512 ? X86::VMOVDI2SSZrr : (HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr);
3281 return 0;
3282 }
3284 inline static bool MaskRegClassContains(unsigned Reg) {
3285 return X86::VK8RegClass.contains(Reg) ||
3286 X86::VK16RegClass.contains(Reg) ||
3287 X86::VK32RegClass.contains(Reg) ||
3288 X86::VK64RegClass.contains(Reg) ||
3289 X86::VK1RegClass.contains(Reg);
3290 }
3291 static
3292 unsigned copyPhysRegOpcode_AVX512(unsigned& DestReg, unsigned& SrcReg) {
3293 if (X86::VR128XRegClass.contains(DestReg, SrcReg) ||
3294 X86::VR256XRegClass.contains(DestReg, SrcReg) ||
3295 X86::VR512RegClass.contains(DestReg, SrcReg)) {
3296 DestReg = get512BitSuperRegister(DestReg);
3297 SrcReg = get512BitSuperRegister(SrcReg);
3298 return X86::VMOVAPSZrr;
3299 }
3300 if (MaskRegClassContains(DestReg) &&
3301 MaskRegClassContains(SrcReg))
3302 return X86::KMOVWkk;
3303 if (MaskRegClassContains(DestReg) &&
3304 (X86::GR32RegClass.contains(SrcReg) ||
3305 X86::GR16RegClass.contains(SrcReg) ||
3306 X86::GR8RegClass.contains(SrcReg))) {
3307 SrcReg = getX86SubSuperRegister(SrcReg, MVT::i32);
3308 return X86::KMOVWkr;
3309 }
3310 if ((X86::GR32RegClass.contains(DestReg) ||
3311 X86::GR16RegClass.contains(DestReg) ||
3312 X86::GR8RegClass.contains(DestReg)) &&
3313 MaskRegClassContains(SrcReg)) {
3314 DestReg = getX86SubSuperRegister(DestReg, MVT::i32);
3315 return X86::KMOVWrk;
3316 }
3317 return 0;
3318 }
3320 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
3321 MachineBasicBlock::iterator MI, DebugLoc DL,
3322 unsigned DestReg, unsigned SrcReg,
3323 bool KillSrc) const {
3324 // First deal with the normal symmetric copies.
3325 bool HasAVX = Subtarget.hasAVX();
3326 bool HasAVX512 = Subtarget.hasAVX512();
3327 unsigned Opc = 0;
3328 if (X86::GR64RegClass.contains(DestReg, SrcReg))
3329 Opc = X86::MOV64rr;
3330 else if (X86::GR32RegClass.contains(DestReg, SrcReg))
3331 Opc = X86::MOV32rr;
3332 else if (X86::GR16RegClass.contains(DestReg, SrcReg))
3333 Opc = X86::MOV16rr;
3334 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
3335 // Copying to or from a physical H register on x86-64 requires a NOREX
3336 // move. Otherwise use a normal move.
3337 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
3338 Subtarget.is64Bit()) {
3339 Opc = X86::MOV8rr_NOREX;
3340 // Both operands must be encodable without an REX prefix.
3341 assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
3342 "8-bit H register can not be copied outside GR8_NOREX");
3343 } else
3344 Opc = X86::MOV8rr;
3345 }
3346 else if (X86::VR64RegClass.contains(DestReg, SrcReg))
3347 Opc = X86::MMX_MOVQ64rr;
3348 else if (HasAVX512)
3349 Opc = copyPhysRegOpcode_AVX512(DestReg, SrcReg);
3350 else if (X86::VR128RegClass.contains(DestReg, SrcReg))
3351 Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
3352 else if (X86::VR256RegClass.contains(DestReg, SrcReg))
3353 Opc = X86::VMOVAPSYrr;
3354 if (!Opc)
3355 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
3357 if (Opc) {
3358 BuildMI(MBB, MI, DL, get(Opc), DestReg)
3359 .addReg(SrcReg, getKillRegState(KillSrc));
3360 return;
3361 }
3363 // Moving EFLAGS to / from another register requires a push and a pop.
3364 // Notice that we have to adjust the stack if we don't want to clobber the
3365 // first frame index. See X86FrameLowering.cpp - clobbersTheStack.
3366 if (SrcReg == X86::EFLAGS) {
3367 if (X86::GR64RegClass.contains(DestReg)) {
3368 BuildMI(MBB, MI, DL, get(X86::PUSHF64));
3369 BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
3370 return;
3371 }
3372 if (X86::GR32RegClass.contains(DestReg)) {
3373 BuildMI(MBB, MI, DL, get(X86::PUSHF32));
3374 BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
3375 return;
3376 }
3377 }
3378 if (DestReg == X86::EFLAGS) {
3379 if (X86::GR64RegClass.contains(SrcReg)) {
3380 BuildMI(MBB, MI, DL, get(X86::PUSH64r))
3381 .addReg(SrcReg, getKillRegState(KillSrc));
3382 BuildMI(MBB, MI, DL, get(X86::POPF64));
3383 return;
3384 }
3385 if (X86::GR32RegClass.contains(SrcReg)) {
3386 BuildMI(MBB, MI, DL, get(X86::PUSH32r))
3387 .addReg(SrcReg, getKillRegState(KillSrc));
3388 BuildMI(MBB, MI, DL, get(X86::POPF32));
3389 return;
3390 }
3391 }
3393 DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
3394 << " to " << RI.getName(DestReg) << '\n');
3395 llvm_unreachable("Cannot emit physreg copy instruction");
3396 }
3398 static unsigned getLoadStoreRegOpcode(unsigned Reg,
3399 const TargetRegisterClass *RC,
3400 bool isStackAligned,
3401 const X86Subtarget &STI,
3402 bool load) {
3403 if (STI.hasAVX512()) {
3404 if (X86::VK8RegClass.hasSubClassEq(RC) ||
3405 X86::VK16RegClass.hasSubClassEq(RC))
3406 return load ? X86::KMOVWkm : X86::KMOVWmk;
3407 if (RC->getSize() == 4 && X86::FR32XRegClass.hasSubClassEq(RC))
3408 return load ? X86::VMOVSSZrm : X86::VMOVSSZmr;
3409 if (RC->getSize() == 8 && X86::FR64XRegClass.hasSubClassEq(RC))
3410 return load ? X86::VMOVSDZrm : X86::VMOVSDZmr;
3411 if (X86::VR512RegClass.hasSubClassEq(RC))
3412 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3413 }
3415 bool HasAVX = STI.hasAVX();
3416 switch (RC->getSize()) {
3417 default:
3418 llvm_unreachable("Unknown spill size");
3419 case 1:
3420 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
3421 if (STI.is64Bit())
3422 // Copying to or from a physical H register on x86-64 requires a NOREX
3423 // move. Otherwise use a normal move.
3424 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
3425 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
3426 return load ? X86::MOV8rm : X86::MOV8mr;
3427 case 2:
3428 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
3429 return load ? X86::MOV16rm : X86::MOV16mr;
3430 case 4:
3431 if (X86::GR32RegClass.hasSubClassEq(RC))
3432 return load ? X86::MOV32rm : X86::MOV32mr;
3433 if (X86::FR32RegClass.hasSubClassEq(RC))
3434 return load ?
3435 (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
3436 (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
3437 if (X86::RFP32RegClass.hasSubClassEq(RC))
3438 return load ? X86::LD_Fp32m : X86::ST_Fp32m;
3439 llvm_unreachable("Unknown 4-byte regclass");
3440 case 8:
3441 if (X86::GR64RegClass.hasSubClassEq(RC))
3442 return load ? X86::MOV64rm : X86::MOV64mr;
3443 if (X86::FR64RegClass.hasSubClassEq(RC))
3444 return load ?
3445 (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
3446 (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
3447 if (X86::VR64RegClass.hasSubClassEq(RC))
3448 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
3449 if (X86::RFP64RegClass.hasSubClassEq(RC))
3450 return load ? X86::LD_Fp64m : X86::ST_Fp64m;
3451 llvm_unreachable("Unknown 8-byte regclass");
3452 case 10:
3453 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
3454 return load ? X86::LD_Fp80m : X86::ST_FpP80m;
3455 case 16: {
3456 assert((X86::VR128RegClass.hasSubClassEq(RC) ||
3457 X86::VR128XRegClass.hasSubClassEq(RC))&& "Unknown 16-byte regclass");
3458 // If stack is realigned we can use aligned stores.
3459 if (isStackAligned)
3460 return load ?
3461 (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) :
3462 (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
3463 else
3464 return load ?
3465 (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) :
3466 (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
3467 }
3468 case 32:
3469 assert((X86::VR256RegClass.hasSubClassEq(RC) ||
3470 X86::VR256XRegClass.hasSubClassEq(RC)) && "Unknown 32-byte regclass");
3471 // If stack is realigned we can use aligned stores.
3472 if (isStackAligned)
3473 return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr;
3474 else
3475 return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr;
3476 case 64:
3477 assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
3478 if (isStackAligned)
3479 return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
3480 else
3481 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3482 }
3483 }
3485 static unsigned getStoreRegOpcode(unsigned SrcReg,
3486 const TargetRegisterClass *RC,
3487 bool isStackAligned,
3488 const X86Subtarget &STI) {
3489 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false);
3490 }
3493 static unsigned getLoadRegOpcode(unsigned DestReg,
3494 const TargetRegisterClass *RC,
3495 bool isStackAligned,
3496 const X86Subtarget &STI) {
3497 return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true);
3498 }
3500 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
3501 MachineBasicBlock::iterator MI,
3502 unsigned SrcReg, bool isKill, int FrameIdx,
3503 const TargetRegisterClass *RC,
3504 const TargetRegisterInfo *TRI) const {
3505 const MachineFunction &MF = *MBB.getParent();
3506 assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() &&
3507 "Stack slot too small for store");
3508 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
3509 bool isAligned = (MF.getTarget()
3510 .getSubtargetImpl()
3511 ->getFrameLowering()
3512 ->getStackAlignment() >= Alignment) ||
3513 RI.canRealignStack(MF);
3514 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
3515 DebugLoc DL = MBB.findDebugLoc(MI);
3516 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
3517 .addReg(SrcReg, getKillRegState(isKill));
3518 }
3520 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
3521 bool isKill,
3522 SmallVectorImpl<MachineOperand> &Addr,
3523 const TargetRegisterClass *RC,
3524 MachineInstr::mmo_iterator MMOBegin,
3525 MachineInstr::mmo_iterator MMOEnd,
3526 SmallVectorImpl<MachineInstr*> &NewMIs) const {
3527 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
3528 bool isAligned = MMOBegin != MMOEnd &&
3529 (*MMOBegin)->getAlignment() >= Alignment;
3530 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
3531 DebugLoc DL;
3532 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
3533 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
3534 MIB.addOperand(Addr[i]);
3535 MIB.addReg(SrcReg, getKillRegState(isKill));
3536 (*MIB).setMemRefs(MMOBegin, MMOEnd);
3537 NewMIs.push_back(MIB);
3538 }
3541 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
3542 MachineBasicBlock::iterator MI,
3543 unsigned DestReg, int FrameIdx,
3544 const TargetRegisterClass *RC,
3545 const TargetRegisterInfo *TRI) const {
3546 const MachineFunction &MF = *MBB.getParent();
3547 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
3548 bool isAligned = (MF.getTarget()
3549 .getSubtargetImpl()
3550 ->getFrameLowering()
3551 ->getStackAlignment() >= Alignment) ||
3552 RI.canRealignStack(MF);
3553 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
3554 DebugLoc DL = MBB.findDebugLoc(MI);
3555 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
3556 }
3558 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
3559 SmallVectorImpl<MachineOperand> &Addr,
3560 const TargetRegisterClass *RC,
3561 MachineInstr::mmo_iterator MMOBegin,
3562 MachineInstr::mmo_iterator MMOEnd,
3563 SmallVectorImpl<MachineInstr*> &NewMIs) const {
3564 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
3565 bool isAligned = MMOBegin != MMOEnd &&
3566 (*MMOBegin)->getAlignment() >= Alignment;
3567 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
3568 DebugLoc DL;
3569 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
3570 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
3571 MIB.addOperand(Addr[i]);
3572 (*MIB).setMemRefs(MMOBegin, MMOEnd);
3573 NewMIs.push_back(MIB);
3574 }
3576 bool X86InstrInfo::
3577 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
3578 int &CmpMask, int &CmpValue) const {
3579 switch (MI->getOpcode()) {
3580 default: break;
3581 case X86::CMP64ri32:
3582 case X86::CMP64ri8:
3583 case X86::CMP32ri:
3584 case X86::CMP32ri8:
3585 case X86::CMP16ri:
3586 case X86::CMP16ri8:
3587 case X86::CMP8ri:
3588 SrcReg = MI->getOperand(0).getReg();
3589 SrcReg2 = 0;
3590 CmpMask = ~0;
3591 CmpValue = MI->getOperand(1).getImm();
3592 return true;
3593 // A SUB can be used to perform comparison.
3594 case X86::SUB64rm:
3595 case X86::SUB32rm:
3596 case X86::SUB16rm:
3597 case X86::SUB8rm:
3598 SrcReg = MI->getOperand(1).getReg();
3599 SrcReg2 = 0;
3600 CmpMask = ~0;
3601 CmpValue = 0;
3602 return true;
3603 case X86::SUB64rr:
3604 case X86::SUB32rr:
3605 case X86::SUB16rr:
3606 case X86::SUB8rr:
3607 SrcReg = MI->getOperand(1).getReg();
3608 SrcReg2 = MI->getOperand(2).getReg();
3609 CmpMask = ~0;
3610 CmpValue = 0;
3611 return true;
3612 case X86::SUB64ri32:
3613 case X86::SUB64ri8:
3614 case X86::SUB32ri:
3615 case X86::SUB32ri8:
3616 case X86::SUB16ri:
3617 case X86::SUB16ri8:
3618 case X86::SUB8ri:
3619 SrcReg = MI->getOperand(1).getReg();
3620 SrcReg2 = 0;
3621 CmpMask = ~0;
3622 CmpValue = MI->getOperand(2).getImm();
3623 return true;
3624 case X86::CMP64rr:
3625 case X86::CMP32rr:
3626 case X86::CMP16rr:
3627 case X86::CMP8rr:
3628 SrcReg = MI->getOperand(0).getReg();
3629 SrcReg2 = MI->getOperand(1).getReg();
3630 CmpMask = ~0;
3631 CmpValue = 0;
3632 return true;
3633 case X86::TEST8rr:
3634 case X86::TEST16rr:
3635 case X86::TEST32rr:
3636 case X86::TEST64rr:
3637 SrcReg = MI->getOperand(0).getReg();
3638 if (MI->getOperand(1).getReg() != SrcReg) return false;
3639 // Compare against zero.
3640 SrcReg2 = 0;
3641 CmpMask = ~0;
3642 CmpValue = 0;
3643 return true;
3644 }
3645 return false;
3646 }
3648 /// isRedundantFlagInstr - check whether the first instruction, whose only
3649 /// purpose is to update flags, can be made redundant.
3650 /// CMPrr can be made redundant by SUBrr if the operands are the same.
3651 /// This function can be extended later on.
3652 /// SrcReg, SrcRegs: register operands for FlagI.
3653 /// ImmValue: immediate for FlagI if it takes an immediate.
3654 inline static bool isRedundantFlagInstr(MachineInstr *FlagI, unsigned SrcReg,
3655 unsigned SrcReg2, int ImmValue,
3656 MachineInstr *OI) {
3657 if (((FlagI->getOpcode() == X86::CMP64rr &&
3658 OI->getOpcode() == X86::SUB64rr) ||
3659 (FlagI->getOpcode() == X86::CMP32rr &&
3660 OI->getOpcode() == X86::SUB32rr)||
3661 (FlagI->getOpcode() == X86::CMP16rr &&
3662 OI->getOpcode() == X86::SUB16rr)||
3663 (FlagI->getOpcode() == X86::CMP8rr &&
3664 OI->getOpcode() == X86::SUB8rr)) &&
3665 ((OI->getOperand(1).getReg() == SrcReg &&
3666 OI->getOperand(2).getReg() == SrcReg2) ||
3667 (OI->getOperand(1).getReg() == SrcReg2 &&
3668 OI->getOperand(2).getReg() == SrcReg)))
3669 return true;
3671 if (((FlagI->getOpcode() == X86::CMP64ri32 &&
3672 OI->getOpcode() == X86::SUB64ri32) ||
3673 (FlagI->getOpcode() == X86::CMP64ri8 &&
3674 OI->getOpcode() == X86::SUB64ri8) ||
3675 (FlagI->getOpcode() == X86::CMP32ri &&
3676 OI->getOpcode() == X86::SUB32ri) ||
3677 (FlagI->getOpcode() == X86::CMP32ri8 &&
3678 OI->getOpcode() == X86::SUB32ri8) ||
3679 (FlagI->getOpcode() == X86::CMP16ri &&
3680 OI->getOpcode() == X86::SUB16ri) ||
3681 (FlagI->getOpcode() == X86::CMP16ri8 &&
3682 OI->getOpcode() == X86::SUB16ri8) ||
3683 (FlagI->getOpcode() == X86::CMP8ri &&
3684 OI->getOpcode() == X86::SUB8ri)) &&
3685 OI->getOperand(1).getReg() == SrcReg &&
3686 OI->getOperand(2).getImm() == ImmValue)
3687 return true;
3688 return false;
3689 }
3691 /// isDefConvertible - check whether the definition can be converted
3692 /// to remove a comparison against zero.
3693 inline static bool isDefConvertible(MachineInstr *MI) {
3694 switch (MI->getOpcode()) {
3695 default: return false;
3697 // The shift instructions only modify ZF if their shift count is non-zero.
3698 // N.B.: The processor truncates the shift count depending on the encoding.
3699 case X86::SAR8ri: case X86::SAR16ri: case X86::SAR32ri:case X86::SAR64ri:
3700 case X86::SHR8ri: case X86::SHR16ri: case X86::SHR32ri:case X86::SHR64ri:
3701 return getTruncatedShiftCount(MI, 2) != 0;
3703 // Some left shift instructions can be turned into LEA instructions but only
3704 // if their flags aren't used. Avoid transforming such instructions.
3705 case X86::SHL8ri: case X86::SHL16ri: case X86::SHL32ri:case X86::SHL64ri:{
3706 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
3707 if (isTruncatedShiftCountForLEA(ShAmt)) return false;
3708 return ShAmt != 0;
3709 }
3711 case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
3712 case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
3713 return getTruncatedShiftCount(MI, 3) != 0;
3715 case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
3716 case X86::SUB32ri8: case X86::SUB16ri: case X86::SUB16ri8:
3717 case X86::SUB8ri: case X86::SUB64rr: case X86::SUB32rr:
3718 case X86::SUB16rr: case X86::SUB8rr: case X86::SUB64rm:
3719 case X86::SUB32rm: case X86::SUB16rm: case X86::SUB8rm:
3720 case X86::DEC64r: case X86::DEC32r: case X86::DEC16r: case X86::DEC8r:
3721 case X86::DEC64_32r: case X86::DEC64_16r:
3722 case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
3723 case X86::ADD32ri8: case X86::ADD16ri: case X86::ADD16ri8:
3724 case X86::ADD8ri: case X86::ADD64rr: case X86::ADD32rr:
3725 case X86::ADD16rr: case X86::ADD8rr: case X86::ADD64rm:
3726 case X86::ADD32rm: case X86::ADD16rm: case X86::ADD8rm:
3727 case X86::INC64r: case X86::INC32r: case X86::INC16r: case X86::INC8r:
3728 case X86::INC64_32r: case X86::INC64_16r:
3729 case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
3730 case X86::AND32ri8: case X86::AND16ri: case X86::AND16ri8:
3731 case X86::AND8ri: case X86::AND64rr: case X86::AND32rr:
3732 case X86::AND16rr: case X86::AND8rr: case X86::AND64rm:
3733 case X86::AND32rm: case X86::AND16rm: case X86::AND8rm:
3734 case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
3735 case X86::XOR32ri8: case X86::XOR16ri: case X86::XOR16ri8:
3736 case X86::XOR8ri: case X86::XOR64rr: case X86::XOR32rr:
3737 case X86::XOR16rr: case X86::XOR8rr: case X86::XOR64rm:
3738 case X86::XOR32rm: case X86::XOR16rm: case X86::XOR8rm:
3739 case X86::OR64ri32: case X86::OR64ri8: case X86::OR32ri:
3740 case X86::OR32ri8: case X86::OR16ri: case X86::OR16ri8:
3741 case X86::OR8ri: case X86::OR64rr: case X86::OR32rr:
3742 case X86::OR16rr: case X86::OR8rr: case X86::OR64rm:
3743 case X86::OR32rm: case X86::OR16rm: case X86::OR8rm:
3744 case X86::NEG8r: case X86::NEG16r: case X86::NEG32r: case X86::NEG64r:
3745 case X86::SAR8r1: case X86::SAR16r1: case X86::SAR32r1:case X86::SAR64r1:
3746 case X86::SHR8r1: case X86::SHR16r1: case X86::SHR32r1:case X86::SHR64r1:
3747 case X86::SHL8r1: case X86::SHL16r1: case X86::SHL32r1:case X86::SHL64r1:
3748 case X86::ADC32ri: case X86::ADC32ri8:
3749 case X86::ADC32rr: case X86::ADC64ri32:
3750 case X86::ADC64ri8: case X86::ADC64rr:
3751 case X86::SBB32ri: case X86::SBB32ri8:
3752 case X86::SBB32rr: case X86::SBB64ri32:
3753 case X86::SBB64ri8: case X86::SBB64rr:
3754 case X86::ANDN32rr: case X86::ANDN32rm:
3755 case X86::ANDN64rr: case X86::ANDN64rm:
3756 case X86::BEXTR32rr: case X86::BEXTR64rr:
3757 case X86::BEXTR32rm: case X86::BEXTR64rm:
3758 case X86::BLSI32rr: case X86::BLSI32rm:
3759 case X86::BLSI64rr: case X86::BLSI64rm:
3760 case X86::BLSMSK32rr:case X86::BLSMSK32rm:
3761 case X86::BLSMSK64rr:case X86::BLSMSK64rm:
3762 case X86::BLSR32rr: case X86::BLSR32rm:
3763 case X86::BLSR64rr: case X86::BLSR64rm:
3764 case X86::BZHI32rr: case X86::BZHI32rm:
3765 case X86::BZHI64rr: case X86::BZHI64rm:
3766 case X86::LZCNT16rr: case X86::LZCNT16rm:
3767 case X86::LZCNT32rr: case X86::LZCNT32rm:
3768 case X86::LZCNT64rr: case X86::LZCNT64rm:
3769 case X86::POPCNT16rr:case X86::POPCNT16rm:
3770 case X86::POPCNT32rr:case X86::POPCNT32rm:
3771 case X86::POPCNT64rr:case X86::POPCNT64rm:
3772 case X86::TZCNT16rr: case X86::TZCNT16rm:
3773 case X86::TZCNT32rr: case X86::TZCNT32rm:
3774 case X86::TZCNT64rr: case X86::TZCNT64rm:
3775 return true;
3776 }
3777 }
3779 /// isUseDefConvertible - check whether the use can be converted
3780 /// to remove a comparison against zero.
3781 static X86::CondCode isUseDefConvertible(MachineInstr *MI) {
3782 switch (MI->getOpcode()) {
3783 default: return X86::COND_INVALID;
3784 case X86::LZCNT16rr: case X86::LZCNT16rm:
3785 case X86::LZCNT32rr: case X86::LZCNT32rm:
3786 case X86::LZCNT64rr: case X86::LZCNT64rm:
3787 return X86::COND_B;
3788 case X86::POPCNT16rr:case X86::POPCNT16rm:
3789 case X86::POPCNT32rr:case X86::POPCNT32rm:
3790 case X86::POPCNT64rr:case X86::POPCNT64rm:
3791 return X86::COND_E;
3792 case X86::TZCNT16rr: case X86::TZCNT16rm:
3793 case X86::TZCNT32rr: case X86::TZCNT32rm:
3794 case X86::TZCNT64rr: case X86::TZCNT64rm:
3795 return X86::COND_B;
3796 }
3797 }
3799 /// optimizeCompareInstr - Check if there exists an earlier instruction that
3800 /// operates on the same source operands and sets flags in the same way as
3801 /// Compare; remove Compare if possible.
3802 bool X86InstrInfo::
3803 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
3804 int CmpMask, int CmpValue,
3805 const MachineRegisterInfo *MRI) const {
3806 // Check whether we can replace SUB with CMP.
3807 unsigned NewOpcode = 0;
3808 switch (CmpInstr->getOpcode()) {
3809 default: break;
3810 case X86::SUB64ri32:
3811 case X86::SUB64ri8:
3812 case X86::SUB32ri:
3813 case X86::SUB32ri8:
3814 case X86::SUB16ri:
3815 case X86::SUB16ri8:
3816 case X86::SUB8ri:
3817 case X86::SUB64rm:
3818 case X86::SUB32rm:
3819 case X86::SUB16rm:
3820 case X86::SUB8rm:
3821 case X86::SUB64rr:
3822 case X86::SUB32rr:
3823 case X86::SUB16rr:
3824 case X86::SUB8rr: {
3825 if (!MRI->use_nodbg_empty(CmpInstr->getOperand(0).getReg()))
3826 return false;
3827 // There is no use of the destination register, we can replace SUB with CMP.
3828 switch (CmpInstr->getOpcode()) {
3829 default: llvm_unreachable("Unreachable!");
3830 case X86::SUB64rm: NewOpcode = X86::CMP64rm; break;
3831 case X86::SUB32rm: NewOpcode = X86::CMP32rm; break;
3832 case X86::SUB16rm: NewOpcode = X86::CMP16rm; break;
3833 case X86::SUB8rm: NewOpcode = X86::CMP8rm; break;
3834 case X86::SUB64rr: NewOpcode = X86::CMP64rr; break;
3835 case X86::SUB32rr: NewOpcode = X86::CMP32rr; break;
3836 case X86::SUB16rr: NewOpcode = X86::CMP16rr; break;
3837 case X86::SUB8rr: NewOpcode = X86::CMP8rr; break;
3838 case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
3839 case X86::SUB64ri8: NewOpcode = X86::CMP64ri8; break;
3840 case X86::SUB32ri: NewOpcode = X86::CMP32ri; break;
3841 case X86::SUB32ri8: NewOpcode = X86::CMP32ri8; break;
3842 case X86::SUB16ri: NewOpcode = X86::CMP16ri; break;
3843 case X86::SUB16ri8: NewOpcode = X86::CMP16ri8; break;
3844 case X86::SUB8ri: NewOpcode = X86::CMP8ri; break;
3845 }
3846 CmpInstr->setDesc(get(NewOpcode));
3847 CmpInstr->RemoveOperand(0);
3848 // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
3849 if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
3850 NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
3851 return false;
3852 }
3853 }
3855 // Get the unique definition of SrcReg.
3856 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
3857 if (!MI) return false;
3859 // CmpInstr is the first instruction of the BB.
3860 MachineBasicBlock::iterator I = CmpInstr, Def = MI;
3862 // If we are comparing against zero, check whether we can use MI to update
3863 // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
3864 bool IsCmpZero = (SrcReg2 == 0 && CmpValue == 0);
3865 if (IsCmpZero && MI->getParent() != CmpInstr->getParent())
3866 return false;
3868 // If we have a use of the source register between the def and our compare
3869 // instruction we can eliminate the compare iff the use sets EFLAGS in the
3870 // right way.
3871 bool ShouldUpdateCC = false;
3872 X86::CondCode NewCC = X86::COND_INVALID;
3873 if (IsCmpZero && !isDefConvertible(MI)) {
3874 // Scan forward from the use until we hit the use we're looking for or the
3875 // compare instruction.
3876 for (MachineBasicBlock::iterator J = MI;; ++J) {
3877 // Do we have a convertible instruction?
3878 NewCC = isUseDefConvertible(J);
3879 if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
3880 J->getOperand(1).getReg() == SrcReg) {
3881 assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!");
3882 ShouldUpdateCC = true; // Update CC later on.
3883 // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
3884 // with the new def.
3885 MI = Def = J;
3886 break;
3887 }
3889 if (J == I)
3890 return false;
3891 }
3892 }
3894 // We are searching for an earlier instruction that can make CmpInstr
3895 // redundant and that instruction will be saved in Sub.
3896 MachineInstr *Sub = nullptr;
3897 const TargetRegisterInfo *TRI = &getRegisterInfo();
3899 // We iterate backward, starting from the instruction before CmpInstr and
3900 // stop when reaching the definition of a source register or done with the BB.
3901 // RI points to the instruction before CmpInstr.
3902 // If the definition is in this basic block, RE points to the definition;
3903 // otherwise, RE is the rend of the basic block.
3904 MachineBasicBlock::reverse_iterator
3905 RI = MachineBasicBlock::reverse_iterator(I),
3906 RE = CmpInstr->getParent() == MI->getParent() ?
3907 MachineBasicBlock::reverse_iterator(++Def) /* points to MI */ :
3908 CmpInstr->getParent()->rend();
3909 MachineInstr *Movr0Inst = nullptr;
3910 for (; RI != RE; ++RI) {
3911 MachineInstr *Instr = &*RI;
3912 // Check whether CmpInstr can be made redundant by the current instruction.
3913 if (!IsCmpZero &&
3914 isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) {
3915 Sub = Instr;
3916 break;
3917 }
3919 if (Instr->modifiesRegister(X86::EFLAGS, TRI) ||
3920 Instr->readsRegister(X86::EFLAGS, TRI)) {
3921 // This instruction modifies or uses EFLAGS.
3923 // MOV32r0 etc. are implemented with xor which clobbers condition code.
3924 // They are safe to move up, if the definition to EFLAGS is dead and
3925 // earlier instructions do not read or write EFLAGS.
3926 if (!Movr0Inst && Instr->getOpcode() == X86::MOV32r0 &&
3927 Instr->registerDefIsDead(X86::EFLAGS, TRI)) {
3928 Movr0Inst = Instr;
3929 continue;
3930 }
3932 // We can't remove CmpInstr.
3933 return false;
3934 }
3935 }
3937 // Return false if no candidates exist.
3938 if (!IsCmpZero && !Sub)
3939 return false;
3941 bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
3942 Sub->getOperand(2).getReg() == SrcReg);
3944 // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
3945 // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
3946 // If we are done with the basic block, we need to check whether EFLAGS is
3947 // live-out.
3948 bool IsSafe = false;
3949 SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
3950 MachineBasicBlock::iterator E = CmpInstr->getParent()->end();
3951 for (++I; I != E; ++I) {
3952 const MachineInstr &Instr = *I;
3953 bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
3954 bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
3955 // We should check the usage if this instruction uses and updates EFLAGS.
3956 if (!UseEFLAGS && ModifyEFLAGS) {
3957 // It is safe to remove CmpInstr if EFLAGS is updated again.
3958 IsSafe = true;
3959 break;
3960 }
3961 if (!UseEFLAGS && !ModifyEFLAGS)
3962 continue;
3964 // EFLAGS is used by this instruction.
3965 X86::CondCode OldCC = X86::COND_INVALID;
3966 bool OpcIsSET = false;
3967 if (IsCmpZero || IsSwapped) {
3968 // We decode the condition code from opcode.
3969 if (Instr.isBranch())
3970 OldCC = getCondFromBranchOpc(Instr.getOpcode());
3971 else {
3972 OldCC = getCondFromSETOpc(Instr.getOpcode());
3973 if (OldCC != X86::COND_INVALID)
3974 OpcIsSET = true;
3975 else
3976 OldCC = X86::getCondFromCMovOpc(Instr.getOpcode());
3977 }
3978 if (OldCC == X86::COND_INVALID) return false;
3979 }
3980 if (IsCmpZero) {
3981 switch (OldCC) {
3982 default: break;
3983 case X86::COND_A: case X86::COND_AE:
3984 case X86::COND_B: case X86::COND_BE:
3985 case X86::COND_G: case X86::COND_GE:
3986 case X86::COND_L: case X86::COND_LE:
3987 case X86::COND_O: case X86::COND_NO:
3988 // CF and OF are used, we can't perform this optimization.
3989 return false;
3990 }
3992 // If we're updating the condition code check if we have to reverse the
3993 // condition.
3994 if (ShouldUpdateCC)
3995 switch (OldCC) {
3996 default:
3997 return false;
3998 case X86::COND_E:
3999 break;
4000 case X86::COND_NE:
4001 NewCC = GetOppositeBranchCondition(NewCC);
4002 break;
4003 }
4004 } else if (IsSwapped) {
4005 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
4006 // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
4007 // We swap the condition code and synthesize the new opcode.
4008 NewCC = getSwappedCondition(OldCC);
4009 if (NewCC == X86::COND_INVALID) return false;
4010 }
4012 if ((ShouldUpdateCC || IsSwapped) && NewCC != OldCC) {
4013 // Synthesize the new opcode.
4014 bool HasMemoryOperand = Instr.hasOneMemOperand();
4015 unsigned NewOpc;
4016 if (Instr.isBranch())
4017 NewOpc = GetCondBranchFromCond(NewCC);
4018 else if(OpcIsSET)
4019 NewOpc = getSETFromCond(NewCC, HasMemoryOperand);
4020 else {
4021 unsigned DstReg = Instr.getOperand(0).getReg();
4022 NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(),
4023 HasMemoryOperand);
4024 }
4026 // Push the MachineInstr to OpsToUpdate.
4027 // If it is safe to remove CmpInstr, the condition code of these
4028 // instructions will be modified.
4029 OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
4030 }
4031 if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
4032 // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
4033 IsSafe = true;
4034 break;
4035 }
4036 }
4038 // If EFLAGS is not killed nor re-defined, we should check whether it is
4039 // live-out. If it is live-out, do not optimize.
4040 if ((IsCmpZero || IsSwapped) && !IsSafe) {
4041 MachineBasicBlock *MBB = CmpInstr->getParent();
4042 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
4043 SE = MBB->succ_end(); SI != SE; ++SI)
4044 if ((*SI)->isLiveIn(X86::EFLAGS))
4045 return false;
4046 }
4048 // The instruction to be updated is either Sub or MI.
4049 Sub = IsCmpZero ? MI : Sub;
4050 // Move Movr0Inst to the appropriate place before Sub.
4051 if (Movr0Inst) {
4052 // Look backwards until we find a def that doesn't use the current EFLAGS.
4053 Def = Sub;
4054 MachineBasicBlock::reverse_iterator
4055 InsertI = MachineBasicBlock::reverse_iterator(++Def),
4056 InsertE = Sub->getParent()->rend();
4057 for (; InsertI != InsertE; ++InsertI) {
4058 MachineInstr *Instr = &*InsertI;
4059 if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
4060 Instr->modifiesRegister(X86::EFLAGS, TRI)) {
4061 Sub->getParent()->remove(Movr0Inst);
4062 Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
4063 Movr0Inst);
4064 break;
4065 }
4066 }
4067 if (InsertI == InsertE)
4068 return false;
4069 }
4071 // Make sure Sub instruction defines EFLAGS and mark the def live.
4072 unsigned i = 0, e = Sub->getNumOperands();
4073 for (; i != e; ++i) {
4074 MachineOperand &MO = Sub->getOperand(i);
4075 if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
4076 MO.setIsDead(false);
4077 break;
4078 }
4079 }
4080 assert(i != e && "Unable to locate a def EFLAGS operand");
4082 CmpInstr->eraseFromParent();
4084 // Modify the condition code of instructions in OpsToUpdate.
4085 for (unsigned i = 0, e = OpsToUpdate.size(); i < e; i++)
4086 OpsToUpdate[i].first->setDesc(get(OpsToUpdate[i].second));
4087 return true;
4088 }
4090 /// optimizeLoadInstr - Try to remove the load by folding it to a register
4091 /// operand at the use. We fold the load instructions if load defines a virtual
4092 /// register, the virtual register is used once in the same BB, and the
4093 /// instructions in-between do not load or store, and have no side effects.
4094 MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr *MI,
4095 const MachineRegisterInfo *MRI,
4096 unsigned &FoldAsLoadDefReg,
4097 MachineInstr *&DefMI) const {
4098 if (FoldAsLoadDefReg == 0)
4099 return nullptr;
4100 // To be conservative, if there exists another load, clear the load candidate.
4101 if (MI->mayLoad()) {
4102 FoldAsLoadDefReg = 0;
4103 return nullptr;
4104 }
4106 // Check whether we can move DefMI here.
4107 DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
4108 assert(DefMI);
4109 bool SawStore = false;
4110 if (!DefMI->isSafeToMove(this, nullptr, SawStore))
4111 return nullptr;
4113 // Collect information about virtual register operands of MI.
4114 unsigned SrcOperandId = 0;
4115 bool FoundSrcOperand = false;
4116 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
4117 MachineOperand &MO = MI->getOperand(i);
4118 if (!MO.isReg())
4119 continue;
4120 unsigned Reg = MO.getReg();
4121 if (Reg != FoldAsLoadDefReg)
4122 continue;
4123 // Do not fold if we have a subreg use or a def or multiple uses.
4124 if (MO.getSubReg() || MO.isDef() || FoundSrcOperand)
4125 return nullptr;
4127 SrcOperandId = i;
4128 FoundSrcOperand = true;
4129 }
4130 if (!FoundSrcOperand)
4131 return nullptr;
4133 // Check whether we can fold the def into SrcOperandId.
4134 SmallVector<unsigned, 8> Ops;
4135 Ops.push_back(SrcOperandId);
4136 MachineInstr *FoldMI = foldMemoryOperand(MI, Ops, DefMI);
4137 if (FoldMI) {
4138 FoldAsLoadDefReg = 0;
4139 return FoldMI;
4140 }
4142 return nullptr;
4143 }
4145 /// Expand2AddrUndef - Expand a single-def pseudo instruction to a two-addr
4146 /// instruction with two undef reads of the register being defined. This is
4147 /// used for mapping:
4148 /// %xmm4 = V_SET0
4149 /// to:
4150 /// %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
4151 ///
4152 static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
4153 const MCInstrDesc &Desc) {
4154 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
4155 unsigned Reg = MIB->getOperand(0).getReg();
4156 MIB->setDesc(Desc);
4158 // MachineInstr::addOperand() will insert explicit operands before any
4159 // implicit operands.
4160 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
4161 // But we don't trust that.
4162 assert(MIB->getOperand(1).getReg() == Reg &&
4163 MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
4164 return true;
4165 }
4167 // LoadStackGuard has so far only been implemented for 64-bit MachO. Different
4168 // code sequence is needed for other targets.
4169 static void expandLoadStackGuard(MachineInstrBuilder &MIB,
4170 const TargetInstrInfo &TII) {
4171 MachineBasicBlock &MBB = *MIB->getParent();
4172 DebugLoc DL = MIB->getDebugLoc();
4173 unsigned Reg = MIB->getOperand(0).getReg();
4174 const GlobalValue *GV =
4175 cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
4176 unsigned Flag = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant;
4177 MachineMemOperand *MMO = MBB.getParent()->
4178 getMachineMemOperand(MachinePointerInfo::getGOT(), Flag, 8, 8);
4179 MachineBasicBlock::iterator I = MIB.getInstr();
4181 BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
4182 .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
4183 .addMemOperand(MMO);
4184 MIB->setDebugLoc(DL);
4185 MIB->setDesc(TII.get(X86::MOV64rm));
4186 MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
4187 }
4189 bool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
4190 bool HasAVX = Subtarget.hasAVX();
4191 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
4192 switch (MI->getOpcode()) {
4193 case X86::MOV32r0:
4194 return Expand2AddrUndef(MIB, get(X86::XOR32rr));
4195 case X86::SETB_C8r:
4196 return Expand2AddrUndef(MIB, get(X86::SBB8rr));
4197 case X86::SETB_C16r:
4198 return Expand2AddrUndef(MIB, get(X86::SBB16rr));
4199 case X86::SETB_C32r:
4200 return Expand2AddrUndef(MIB, get(X86::SBB32rr));
4201 case X86::SETB_C64r:
4202 return Expand2AddrUndef(MIB, get(X86::SBB64rr));
4203 case X86::V_SET0:
4204 case X86::FsFLD0SS:
4205 case X86::FsFLD0SD:
4206 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
4207 case X86::AVX_SET0:
4208 assert(HasAVX && "AVX not supported");
4209 return Expand2AddrUndef(MIB, get(X86::VXORPSYrr));
4210 case X86::AVX512_512_SET0:
4211 return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
4212 case X86::V_SETALLONES:
4213 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
4214 case X86::AVX2_SETALLONES:
4215 return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
4216 case X86::TEST8ri_NOREX:
4217 MI->setDesc(get(X86::TEST8ri));
4218 return true;
4219 case X86::KSET0B:
4220 case X86::KSET0W: return Expand2AddrUndef(MIB, get(X86::KXORWrr));
4221 case X86::KSET1B:
4222 case X86::KSET1W: return Expand2AddrUndef(MIB, get(X86::KXNORWrr));
4223 case TargetOpcode::LOAD_STACK_GUARD:
4224 expandLoadStackGuard(MIB, *this);
4225 return true;
4226 }
4227 return false;
4228 }
4230 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
4231 const SmallVectorImpl<MachineOperand> &MOs,
4232 MachineInstr *MI,
4233 const TargetInstrInfo &TII) {
4234 // Create the base instruction with the memory operand as the first part.
4235 // Omit the implicit operands, something BuildMI can't do.
4236 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
4237 MI->getDebugLoc(), true);
4238 MachineInstrBuilder MIB(MF, NewMI);
4239 unsigned NumAddrOps = MOs.size();
4240 for (unsigned i = 0; i != NumAddrOps; ++i)
4241 MIB.addOperand(MOs[i]);
4242 if (NumAddrOps < 4) // FrameIndex only
4243 addOffset(MIB, 0);
4245 // Loop over the rest of the ri operands, converting them over.
4246 unsigned NumOps = MI->getDesc().getNumOperands()-2;
4247 for (unsigned i = 0; i != NumOps; ++i) {
4248 MachineOperand &MO = MI->getOperand(i+2);
4249 MIB.addOperand(MO);
4250 }
4251 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
4252 MachineOperand &MO = MI->getOperand(i);
4253 MIB.addOperand(MO);
4254 }
4255 return MIB;
4256 }
4258 static MachineInstr *FuseInst(MachineFunction &MF,
4259 unsigned Opcode, unsigned OpNo,
4260 const SmallVectorImpl<MachineOperand> &MOs,
4261 MachineInstr *MI, const TargetInstrInfo &TII) {
4262 // Omit the implicit operands, something BuildMI can't do.
4263 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
4264 MI->getDebugLoc(), true);
4265 MachineInstrBuilder MIB(MF, NewMI);
4267 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
4268 MachineOperand &MO = MI->getOperand(i);
4269 if (i == OpNo) {
4270 assert(MO.isReg() && "Expected to fold into reg operand!");
4271 unsigned NumAddrOps = MOs.size();
4272 for (unsigned i = 0; i != NumAddrOps; ++i)
4273 MIB.addOperand(MOs[i]);
4274 if (NumAddrOps < 4) // FrameIndex only
4275 addOffset(MIB, 0);
4276 } else {
4277 MIB.addOperand(MO);
4278 }
4279 }
4280 return MIB;
4281 }
4283 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
4284 const SmallVectorImpl<MachineOperand> &MOs,
4285 MachineInstr *MI) {
4286 MachineFunction &MF = *MI->getParent()->getParent();
4287 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
4289 unsigned NumAddrOps = MOs.size();
4290 for (unsigned i = 0; i != NumAddrOps; ++i)
4291 MIB.addOperand(MOs[i]);
4292 if (NumAddrOps < 4) // FrameIndex only
4293 addOffset(MIB, 0);
4294 return MIB.addImm(0);
4295 }
4297 MachineInstr*
4298 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
4299 MachineInstr *MI, unsigned i,
4300 const SmallVectorImpl<MachineOperand> &MOs,
4301 unsigned Size, unsigned Align,
4302 bool AllowCommute) const {
4303 const DenseMap<unsigned,
4304 std::pair<unsigned,unsigned> > *OpcodeTablePtr = nullptr;
4305 bool isCallRegIndirect = Subtarget.callRegIndirect();
4306 bool isTwoAddrFold = false;
4308 // Atom favors register form of call. So, we do not fold loads into calls
4309 // when X86Subtarget is Atom.
4310 if (isCallRegIndirect &&
4311 (MI->getOpcode() == X86::CALL32r || MI->getOpcode() == X86::CALL64r)) {
4312 return nullptr;
4313 }
4315 unsigned NumOps = MI->getDesc().getNumOperands();
4316 bool isTwoAddr = NumOps > 1 &&
4317 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
4319 // FIXME: AsmPrinter doesn't know how to handle
4320 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
4321 if (MI->getOpcode() == X86::ADD32ri &&
4322 MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
4323 return nullptr;
4325 MachineInstr *NewMI = nullptr;
4326 // Folding a memory location into the two-address part of a two-address
4327 // instruction is different than folding it other places. It requires
4328 // replacing the *two* registers with the memory location.
4329 if (isTwoAddr && NumOps >= 2 && i < 2 &&
4330 MI->getOperand(0).isReg() &&
4331 MI->getOperand(1).isReg() &&
4332 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
4333 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
4334 isTwoAddrFold = true;
4335 } else if (i == 0) { // If operand 0
4336 if (MI->getOpcode() == X86::MOV32r0) {
4337 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
4338 if (NewMI)
4339 return NewMI;
4340 }
4342 OpcodeTablePtr = &RegOp2MemOpTable0;
4343 } else if (i == 1) {
4344 OpcodeTablePtr = &RegOp2MemOpTable1;
4345 } else if (i == 2) {
4346 OpcodeTablePtr = &RegOp2MemOpTable2;
4347 } else if (i == 3) {
4348 OpcodeTablePtr = &RegOp2MemOpTable3;
4349 } else if (i == 4) {
4350 OpcodeTablePtr = &RegOp2MemOpTable4;
4351 }
4353 // If table selected...
4354 if (OpcodeTablePtr) {
4355 // Find the Opcode to fuse
4356 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
4357 OpcodeTablePtr->find(MI->getOpcode());
4358 if (I != OpcodeTablePtr->end()) {
4359 unsigned Opcode = I->second.first;
4360 unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
4361 if (Align < MinAlign)
4362 return nullptr;
4363 bool NarrowToMOV32rm = false;
4364 if (Size) {
4365 unsigned RCSize = getRegClass(MI->getDesc(), i, &RI, MF)->getSize();
4366 if (Size < RCSize) {
4367 // Check if it's safe to fold the load. If the size of the object is
4368 // narrower than the load width, then it's not.
4369 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
4370 return nullptr;
4371 // If this is a 64-bit load, but the spill slot is 32, then we can do
4372 // a 32-bit load which is implicitly zero-extended. This likely is
4373 // due to live interval analysis remat'ing a load from stack slot.
4374 if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
4375 return nullptr;
4376 Opcode = X86::MOV32rm;
4377 NarrowToMOV32rm = true;
4378 }
4379 }
4381 if (isTwoAddrFold)
4382 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this);
4383 else
4384 NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this);
4386 if (NarrowToMOV32rm) {
4387 // If this is the special case where we use a MOV32rm to load a 32-bit
4388 // value and zero-extend the top bits. Change the destination register
4389 // to a 32-bit one.
4390 unsigned DstReg = NewMI->getOperand(0).getReg();
4391 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
4392 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
4393 else
4394 NewMI->getOperand(0).setSubReg(X86::sub_32bit);
4395 }
4396 return NewMI;
4397 }
4398 }
4400 // If the instruction and target operand are commutable, commute the
4401 // instruction and try again.
4402 if (AllowCommute) {
4403 unsigned OriginalOpIdx = i, CommuteOpIdx1, CommuteOpIdx2;
4404 if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
4405 bool HasDef = MI->getDesc().getNumDefs();
4406 unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0;
4407 unsigned Reg1 = MI->getOperand(CommuteOpIdx1).getReg();
4408 unsigned Reg2 = MI->getOperand(CommuteOpIdx2).getReg();
4409 bool Tied0 =
4410 0 == MI->getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
4411 bool Tied1 =
4412 0 == MI->getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
4414 // If either of the commutable operands are tied to the destination
4415 // then we can not commute + fold.
4416 if ((HasDef && Reg0 == Reg1 && Tied0) ||
4417 (HasDef && Reg0 == Reg2 && Tied1))
4418 return nullptr;
4420 if ((CommuteOpIdx1 == OriginalOpIdx) ||
4421 (CommuteOpIdx2 == OriginalOpIdx)) {
4422 MachineInstr *CommutedMI = commuteInstruction(MI, false);
4423 if (!CommutedMI) {
4424 // Unable to commute.
4425 return nullptr;
4426 }
4427 if (CommutedMI != MI) {
4428 // New instruction. We can't fold from this.
4429 CommutedMI->eraseFromParent();
4430 return nullptr;
4431 }
4433 // Attempt to fold with the commuted version of the instruction.
4434 unsigned CommuteOp =
4435 (CommuteOpIdx1 == OriginalOpIdx ? CommuteOpIdx2 : CommuteOpIdx1);
4436 NewMI = foldMemoryOperandImpl(MF, MI, CommuteOp, MOs, Size, Align,
4437 /*AllowCommute=*/false);
4438 if (NewMI)
4439 return NewMI;
4441 // Folding failed again - undo the commute before returning.
4442 MachineInstr *UncommutedMI = commuteInstruction(MI, false);
4443 if (!UncommutedMI) {
4444 // Unable to commute.
4445 return nullptr;
4446 }
4447 if (UncommutedMI != MI) {
4448 // New instruction. It doesn't need to be kept.
4449 UncommutedMI->eraseFromParent();
4450 return nullptr;
4451 }
4453 // Return here to prevent duplicate fuse failure report.
4454 return nullptr;
4455 }
4456 }
4457 }
4459 // No fusion
4460 if (PrintFailedFusing && !MI->isCopy())
4461 dbgs() << "We failed to fuse operand " << i << " in " << *MI;
4462 return nullptr;
4463 }
4465 /// hasPartialRegUpdate - Return true for all instructions that only update
4466 /// the first 32 or 64-bits of the destination register and leave the rest
4467 /// unmodified. This can be used to avoid folding loads if the instructions
4468 /// only update part of the destination register, and the non-updated part is
4469 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
4470 /// instructions breaks the partial register dependency and it can improve
4471 /// performance. e.g.:
4472 ///
4473 /// movss (%rdi), %xmm0
4474 /// cvtss2sd %xmm0, %xmm0
4475 ///
4476 /// Instead of
4477 /// cvtss2sd (%rdi), %xmm0
4478 ///
4479 /// FIXME: This should be turned into a TSFlags.
4480 ///
4481 static bool hasPartialRegUpdate(unsigned Opcode) {
4482 switch (Opcode) {
4483 case X86::CVTSI2SSrr:
4484 case X86::CVTSI2SSrm:
4485 case X86::CVTSI2SS64rr:
4486 case X86::CVTSI2SS64rm:
4487 case X86::CVTSI2SDrr:
4488 case X86::CVTSI2SDrm:
4489 case X86::CVTSI2SD64rr:
4490 case X86::CVTSI2SD64rm:
4491 case X86::CVTSD2SSrr:
4492 case X86::CVTSD2SSrm:
4493 case X86::Int_CVTSD2SSrr:
4494 case X86::Int_CVTSD2SSrm:
4495 case X86::CVTSS2SDrr:
4496 case X86::CVTSS2SDrm:
4497 case X86::Int_CVTSS2SDrr:
4498 case X86::Int_CVTSS2SDrm:
4499 case X86::RCPSSr:
4500 case X86::RCPSSm:
4501 case X86::RCPSSr_Int:
4502 case X86::RCPSSm_Int:
4503 case X86::ROUNDSDr:
4504 case X86::ROUNDSDm:
4505 case X86::ROUNDSDr_Int:
4506 case X86::ROUNDSSr:
4507 case X86::ROUNDSSm:
4508 case X86::ROUNDSSr_Int:
4509 case X86::RSQRTSSr:
4510 case X86::RSQRTSSm:
4511 case X86::RSQRTSSr_Int:
4512 case X86::RSQRTSSm_Int:
4513 case X86::SQRTSSr:
4514 case X86::SQRTSSm:
4515 case X86::SQRTSSr_Int:
4516 case X86::SQRTSSm_Int:
4517 case X86::SQRTSDr:
4518 case X86::SQRTSDm:
4519 case X86::SQRTSDr_Int:
4520 case X86::SQRTSDm_Int:
4521 return true;
4522 }
4524 return false;
4525 }
4527 /// getPartialRegUpdateClearance - Inform the ExeDepsFix pass how many idle
4528 /// instructions we would like before a partial register update.
4529 unsigned X86InstrInfo::
4530 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
4531 const TargetRegisterInfo *TRI) const {
4532 if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode()))
4533 return 0;
4535 // If MI is marked as reading Reg, the partial register update is wanted.
4536 const MachineOperand &MO = MI->getOperand(0);
4537 unsigned Reg = MO.getReg();
4538 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
4539 if (MO.readsReg() || MI->readsVirtualRegister(Reg))
4540 return 0;
4541 } else {
4542 if (MI->readsRegister(Reg, TRI))
4543 return 0;
4544 }
4546 // If any of the preceding 16 instructions are reading Reg, insert a
4547 // dependency breaking instruction. The magic number is based on a few
4548 // Nehalem experiments.
4549 return 16;
4550 }
4552 // Return true for any instruction the copies the high bits of the first source
4553 // operand into the unused high bits of the destination operand.
4554 static bool hasUndefRegUpdate(unsigned Opcode) {
4555 switch (Opcode) {
4556 case X86::VCVTSI2SSrr:
4557 case X86::Int_VCVTSI2SSrr:
4558 case X86::VCVTSI2SS64rr:
4559 case X86::Int_VCVTSI2SS64rr:
4560 case X86::VCVTSI2SDrr:
4561 case X86::Int_VCVTSI2SDrr:
4562 case X86::VCVTSI2SD64rr:
4563 case X86::Int_VCVTSI2SD64rr:
4564 case X86::VCVTSD2SSrr:
4565 case X86::Int_VCVTSD2SSrr:
4566 case X86::VCVTSS2SDrr:
4567 case X86::Int_VCVTSS2SDrr:
4568 case X86::VRCPSSr:
4569 case X86::VROUNDSDr:
4570 case X86::VROUNDSDr_Int:
4571 case X86::VROUNDSSr:
4572 case X86::VROUNDSSr_Int:
4573 case X86::VRSQRTSSr:
4574 case X86::VSQRTSSr:
4576 // AVX-512
4577 case X86::VCVTSD2SSZrr:
4578 case X86::VCVTSS2SDZrr:
4579 return true;
4580 }
4582 return false;
4583 }
4585 /// Inform the ExeDepsFix pass how many idle instructions we would like before
4586 /// certain undef register reads.
4587 ///
4588 /// This catches the VCVTSI2SD family of instructions:
4589 ///
4590 /// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14
4591 ///
4592 /// We should to be careful *not* to catch VXOR idioms which are presumably
4593 /// handled specially in the pipeline:
4594 ///
4595 /// vxorps %xmm1<undef>, %xmm1<undef>, %xmm1
4596 ///
4597 /// Like getPartialRegUpdateClearance, this makes a strong assumption that the
4598 /// high bits that are passed-through are not live.
4599 unsigned X86InstrInfo::
4600 getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum,
4601 const TargetRegisterInfo *TRI) const {
4602 if (!hasUndefRegUpdate(MI->getOpcode()))
4603 return 0;
4605 // Set the OpNum parameter to the first source operand.
4606 OpNum = 1;
4608 const MachineOperand &MO = MI->getOperand(OpNum);
4609 if (MO.isUndef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
4610 // Use the same magic number as getPartialRegUpdateClearance.
4611 return 16;
4612 }
4613 return 0;
4614 }
4616 void X86InstrInfo::
4617 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
4618 const TargetRegisterInfo *TRI) const {
4619 unsigned Reg = MI->getOperand(OpNum).getReg();
4620 // If MI kills this register, the false dependence is already broken.
4621 if (MI->killsRegister(Reg, TRI))
4622 return;
4623 if (X86::VR128RegClass.contains(Reg)) {
4624 // These instructions are all floating point domain, so xorps is the best
4625 // choice.
4626 bool HasAVX = Subtarget.hasAVX();
4627 unsigned Opc = HasAVX ? X86::VXORPSrr : X86::XORPSrr;
4628 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(Opc), Reg)
4629 .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
4630 } else if (X86::VR256RegClass.contains(Reg)) {
4631 // Use vxorps to clear the full ymm register.
4632 // It wants to read and write the xmm sub-register.
4633 unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
4634 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(X86::VXORPSrr), XReg)
4635 .addReg(XReg, RegState::Undef).addReg(XReg, RegState::Undef)
4636 .addReg(Reg, RegState::ImplicitDefine);
4637 } else
4638 return;
4639 MI->addRegisterKilled(Reg, TRI, true);
4640 }
4642 MachineInstr*
4643 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
4644 const SmallVectorImpl<unsigned> &Ops,
4645 int FrameIndex) const {
4646 // Check switch flag
4647 if (NoFusing) return nullptr;
4649 // Unless optimizing for size, don't fold to avoid partial
4650 // register update stalls
4651 if (!MF.getFunction()->getAttributes().
4652 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize) &&
4653 hasPartialRegUpdate(MI->getOpcode()))
4654 return nullptr;
4656 const MachineFrameInfo *MFI = MF.getFrameInfo();
4657 unsigned Size = MFI->getObjectSize(FrameIndex);
4658 unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
4659 // If the function stack isn't realigned we don't want to fold instructions
4660 // that need increased alignment.
4661 if (!RI.needsStackRealignment(MF))
4662 Alignment = std::min(Alignment, MF.getTarget()
4663 .getSubtargetImpl()
4664 ->getFrameLowering()
4665 ->getStackAlignment());
4666 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
4667 unsigned NewOpc = 0;
4668 unsigned RCSize = 0;
4669 switch (MI->getOpcode()) {
4670 default: return nullptr;
4671 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
4672 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
4673 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
4674 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
4675 }
4676 // Check if it's safe to fold the load. If the size of the object is
4677 // narrower than the load width, then it's not.
4678 if (Size < RCSize)
4679 return nullptr;
4680 // Change to CMPXXri r, 0 first.
4681 MI->setDesc(get(NewOpc));
4682 MI->getOperand(1).ChangeToImmediate(0);
4683 } else if (Ops.size() != 1)
4684 return nullptr;
4686 SmallVector<MachineOperand,4> MOs;
4687 MOs.push_back(MachineOperand::CreateFI(FrameIndex));
4688 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs,
4689 Size, Alignment, /*AllowCommute=*/true);
4690 }
4692 static bool isPartialRegisterLoad(const MachineInstr &LoadMI,
4693 const MachineFunction &MF) {
4694 unsigned Opc = LoadMI.getOpcode();
4695 unsigned RegSize =
4696 MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg())->getSize();
4698 if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm) && RegSize > 4)
4699 // These instructions only load 32 bits, we can't fold them if the
4700 // destination register is wider than 32 bits (4 bytes).
4701 return true;
4703 if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm) && RegSize > 8)
4704 // These instructions only load 64 bits, we can't fold them if the
4705 // destination register is wider than 64 bits (8 bytes).
4706 return true;
4708 return false;
4709 }
4711 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
4712 MachineInstr *MI,
4713 const SmallVectorImpl<unsigned> &Ops,
4714 MachineInstr *LoadMI) const {
4715 // If loading from a FrameIndex, fold directly from the FrameIndex.
4716 unsigned NumOps = LoadMI->getDesc().getNumOperands();
4717 int FrameIndex;
4718 if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
4719 if (isPartialRegisterLoad(*LoadMI, MF))
4720 return nullptr;
4721 return foldMemoryOperandImpl(MF, MI, Ops, FrameIndex);
4722 }
4724 // Check switch flag
4725 if (NoFusing) return nullptr;
4727 // Unless optimizing for size, don't fold to avoid partial
4728 // register update stalls
4729 if (!MF.getFunction()->getAttributes().
4730 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize) &&
4731 hasPartialRegUpdate(MI->getOpcode()))
4732 return nullptr;
4734 // Determine the alignment of the load.
4735 unsigned Alignment = 0;
4736 if (LoadMI->hasOneMemOperand())
4737 Alignment = (*LoadMI->memoperands_begin())->getAlignment();
4738 else
4739 switch (LoadMI->getOpcode()) {
4740 case X86::AVX2_SETALLONES:
4741 case X86::AVX_SET0:
4742 Alignment = 32;
4743 break;
4744 case X86::V_SET0:
4745 case X86::V_SETALLONES:
4746 Alignment = 16;
4747 break;
4748 case X86::FsFLD0SD:
4749 Alignment = 8;
4750 break;
4751 case X86::FsFLD0SS:
4752 Alignment = 4;
4753 break;
4754 default:
4755 return nullptr;
4756 }
4757 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
4758 unsigned NewOpc = 0;
4759 switch (MI->getOpcode()) {
4760 default: return nullptr;
4761 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
4762 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
4763 case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
4764 case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
4765 }
4766 // Change to CMPXXri r, 0 first.
4767 MI->setDesc(get(NewOpc));
4768 MI->getOperand(1).ChangeToImmediate(0);
4769 } else if (Ops.size() != 1)
4770 return nullptr;
4772 // Make sure the subregisters match.
4773 // Otherwise we risk changing the size of the load.
4774 if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg())
4775 return nullptr;
4777 SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
4778 switch (LoadMI->getOpcode()) {
4779 case X86::V_SET0:
4780 case X86::V_SETALLONES:
4781 case X86::AVX2_SETALLONES:
4782 case X86::AVX_SET0:
4783 case X86::FsFLD0SD:
4784 case X86::FsFLD0SS: {
4785 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
4786 // Create a constant-pool entry and operands to load from it.
4788 // Medium and large mode can't fold loads this way.
4789 if (MF.getTarget().getCodeModel() != CodeModel::Small &&
4790 MF.getTarget().getCodeModel() != CodeModel::Kernel)
4791 return nullptr;
4793 // x86-32 PIC requires a PIC base register for constant pools.
4794 unsigned PICBase = 0;
4795 if (MF.getTarget().getRelocationModel() == Reloc::PIC_) {
4796 if (Subtarget.is64Bit())
4797 PICBase = X86::RIP;
4798 else
4799 // FIXME: PICBase = getGlobalBaseReg(&MF);
4800 // This doesn't work for several reasons.
4801 // 1. GlobalBaseReg may have been spilled.
4802 // 2. It may not be live at MI.
4803 return nullptr;
4804 }
4806 // Create a constant-pool entry.
4807 MachineConstantPool &MCP = *MF.getConstantPool();
4808 Type *Ty;
4809 unsigned Opc = LoadMI->getOpcode();
4810 if (Opc == X86::FsFLD0SS)
4811 Ty = Type::getFloatTy(MF.getFunction()->getContext());
4812 else if (Opc == X86::FsFLD0SD)
4813 Ty = Type::getDoubleTy(MF.getFunction()->getContext());
4814 else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0)
4815 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8);
4816 else
4817 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
4819 bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES);
4820 const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
4821 Constant::getNullValue(Ty);
4822 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
4824 // Create operands to load from the constant pool entry.
4825 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
4826 MOs.push_back(MachineOperand::CreateImm(1));
4827 MOs.push_back(MachineOperand::CreateReg(0, false));
4828 MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
4829 MOs.push_back(MachineOperand::CreateReg(0, false));
4830 break;
4831 }
4832 default: {
4833 if (isPartialRegisterLoad(*LoadMI, MF))
4834 return nullptr;
4836 // Folding a normal load. Just copy the load's address operands.
4837 for (unsigned i = NumOps - X86::AddrNumOperands; i != NumOps; ++i)
4838 MOs.push_back(LoadMI->getOperand(i));
4839 break;
4840 }
4841 }
4842 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs,
4843 /*Size=*/0, Alignment, /*AllowCommute=*/true);
4844 }
4847 bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
4848 const SmallVectorImpl<unsigned> &Ops) const {
4849 // Check switch flag
4850 if (NoFusing) return 0;
4852 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
4853 switch (MI->getOpcode()) {
4854 default: return false;
4855 case X86::TEST8rr:
4856 case X86::TEST16rr:
4857 case X86::TEST32rr:
4858 case X86::TEST64rr:
4859 return true;
4860 case X86::ADD32ri:
4861 // FIXME: AsmPrinter doesn't know how to handle
4862 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
4863 if (MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
4864 return false;
4865 break;
4866 }
4867 }
4869 if (Ops.size() != 1)
4870 return false;
4872 unsigned OpNum = Ops[0];
4873 unsigned Opc = MI->getOpcode();
4874 unsigned NumOps = MI->getDesc().getNumOperands();
4875 bool isTwoAddr = NumOps > 1 &&
4876 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
4878 // Folding a memory location into the two-address part of a two-address
4879 // instruction is different than folding it other places. It requires
4880 // replacing the *two* registers with the memory location.
4881 const DenseMap<unsigned,
4882 std::pair<unsigned,unsigned> > *OpcodeTablePtr = nullptr;
4883 if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
4884 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
4885 } else if (OpNum == 0) { // If operand 0
4886 if (Opc == X86::MOV32r0)
4887 return true;
4889 OpcodeTablePtr = &RegOp2MemOpTable0;
4890 } else if (OpNum == 1) {
4891 OpcodeTablePtr = &RegOp2MemOpTable1;
4892 } else if (OpNum == 2) {
4893 OpcodeTablePtr = &RegOp2MemOpTable2;
4894 } else if (OpNum == 3) {
4895 OpcodeTablePtr = &RegOp2MemOpTable3;
4896 }
4898 if (OpcodeTablePtr && OpcodeTablePtr->count(Opc))
4899 return true;
4900 return TargetInstrInfo::canFoldMemoryOperand(MI, Ops);
4901 }
4903 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
4904 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
4905 SmallVectorImpl<MachineInstr*> &NewMIs) const {
4906 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
4907 MemOp2RegOpTable.find(MI->getOpcode());
4908 if (I == MemOp2RegOpTable.end())
4909 return false;
4910 unsigned Opc = I->second.first;
4911 unsigned Index = I->second.second & TB_INDEX_MASK;
4912 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
4913 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
4914 if (UnfoldLoad && !FoldedLoad)
4915 return false;
4916 UnfoldLoad &= FoldedLoad;
4917 if (UnfoldStore && !FoldedStore)
4918 return false;
4919 UnfoldStore &= FoldedStore;
4921 const MCInstrDesc &MCID = get(Opc);
4922 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
4923 if (!MI->hasOneMemOperand() &&
4924 RC == &X86::VR128RegClass &&
4925 !Subtarget.isUnalignedMemAccessFast())
4926 // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
4927 // conservatively assume the address is unaligned. That's bad for
4928 // performance.
4929 return false;
4930 SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
4931 SmallVector<MachineOperand,2> BeforeOps;
4932 SmallVector<MachineOperand,2> AfterOps;
4933 SmallVector<MachineOperand,4> ImpOps;
4934 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
4935 MachineOperand &Op = MI->getOperand(i);
4936 if (i >= Index && i < Index + X86::AddrNumOperands)
4937 AddrOps.push_back(Op);
4938 else if (Op.isReg() && Op.isImplicit())
4939 ImpOps.push_back(Op);
4940 else if (i < Index)
4941 BeforeOps.push_back(Op);
4942 else if (i > Index)
4943 AfterOps.push_back(Op);
4944 }
4946 // Emit the load instruction.
4947 if (UnfoldLoad) {
4948 std::pair<MachineInstr::mmo_iterator,
4949 MachineInstr::mmo_iterator> MMOs =
4950 MF.extractLoadMemRefs(MI->memoperands_begin(),
4951 MI->memoperands_end());
4952 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
4953 if (UnfoldStore) {
4954 // Address operands cannot be marked isKill.
4955 for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
4956 MachineOperand &MO = NewMIs[0]->getOperand(i);
4957 if (MO.isReg())
4958 MO.setIsKill(false);
4959 }
4960 }
4961 }
4963 // Emit the data processing instruction.
4964 MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI->getDebugLoc(), true);
4965 MachineInstrBuilder MIB(MF, DataMI);
4967 if (FoldedStore)
4968 MIB.addReg(Reg, RegState::Define);
4969 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
4970 MIB.addOperand(BeforeOps[i]);
4971 if (FoldedLoad)
4972 MIB.addReg(Reg);
4973 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
4974 MIB.addOperand(AfterOps[i]);
4975 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
4976 MachineOperand &MO = ImpOps[i];
4977 MIB.addReg(MO.getReg(),
4978 getDefRegState(MO.isDef()) |
4979 RegState::Implicit |
4980 getKillRegState(MO.isKill()) |
4981 getDeadRegState(MO.isDead()) |
4982 getUndefRegState(MO.isUndef()));
4983 }
4984 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
4985 switch (DataMI->getOpcode()) {
4986 default: break;
4987 case X86::CMP64ri32:
4988 case X86::CMP64ri8:
4989 case X86::CMP32ri:
4990 case X86::CMP32ri8:
4991 case X86::CMP16ri:
4992 case X86::CMP16ri8:
4993 case X86::CMP8ri: {
4994 MachineOperand &MO0 = DataMI->getOperand(0);
4995 MachineOperand &MO1 = DataMI->getOperand(1);
4996 if (MO1.getImm() == 0) {
4997 unsigned NewOpc;
4998 switch (DataMI->getOpcode()) {
4999 default: llvm_unreachable("Unreachable!");
5000 case X86::CMP64ri8:
5001 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
5002 case X86::CMP32ri8:
5003 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
5004 case X86::CMP16ri8:
5005 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
5006 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
5007 }
5008 DataMI->setDesc(get(NewOpc));
5009 MO1.ChangeToRegister(MO0.getReg(), false);
5010 }
5011 }
5012 }
5013 NewMIs.push_back(DataMI);
5015 // Emit the store instruction.
5016 if (UnfoldStore) {
5017 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
5018 std::pair<MachineInstr::mmo_iterator,
5019 MachineInstr::mmo_iterator> MMOs =
5020 MF.extractStoreMemRefs(MI->memoperands_begin(),
5021 MI->memoperands_end());
5022 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
5023 }
5025 return true;
5026 }
5028 bool
5029 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
5030 SmallVectorImpl<SDNode*> &NewNodes) const {
5031 if (!N->isMachineOpcode())
5032 return false;
5034 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
5035 MemOp2RegOpTable.find(N->getMachineOpcode());
5036 if (I == MemOp2RegOpTable.end())
5037 return false;
5038 unsigned Opc = I->second.first;
5039 unsigned Index = I->second.second & TB_INDEX_MASK;
5040 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
5041 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
5042 const MCInstrDesc &MCID = get(Opc);
5043 MachineFunction &MF = DAG.getMachineFunction();
5044 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
5045 unsigned NumDefs = MCID.NumDefs;
5046 std::vector<SDValue> AddrOps;
5047 std::vector<SDValue> BeforeOps;
5048 std::vector<SDValue> AfterOps;
5049 SDLoc dl(N);
5050 unsigned NumOps = N->getNumOperands();
5051 for (unsigned i = 0; i != NumOps-1; ++i) {
5052 SDValue Op = N->getOperand(i);
5053 if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
5054 AddrOps.push_back(Op);
5055 else if (i < Index-NumDefs)
5056 BeforeOps.push_back(Op);
5057 else if (i > Index-NumDefs)
5058 AfterOps.push_back(Op);
5059 }
5060 SDValue Chain = N->getOperand(NumOps-1);
5061 AddrOps.push_back(Chain);
5063 // Emit the load instruction.
5064 SDNode *Load = nullptr;
5065 if (FoldedLoad) {
5066 EVT VT = *RC->vt_begin();
5067 std::pair<MachineInstr::mmo_iterator,
5068 MachineInstr::mmo_iterator> MMOs =
5069 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
5070 cast<MachineSDNode>(N)->memoperands_end());
5071 if (!(*MMOs.first) &&
5072 RC == &X86::VR128RegClass &&
5073 !Subtarget.isUnalignedMemAccessFast())
5074 // Do not introduce a slow unaligned load.
5075 return false;
5076 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
5077 bool isAligned = (*MMOs.first) &&
5078 (*MMOs.first)->getAlignment() >= Alignment;
5079 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, Subtarget), dl,
5080 VT, MVT::Other, AddrOps);
5081 NewNodes.push_back(Load);
5083 // Preserve memory reference information.
5084 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
5085 }
5087 // Emit the data processing instruction.
5088 std::vector<EVT> VTs;
5089 const TargetRegisterClass *DstRC = nullptr;
5090 if (MCID.getNumDefs() > 0) {
5091 DstRC = getRegClass(MCID, 0, &RI, MF);
5092 VTs.push_back(*DstRC->vt_begin());
5093 }
5094 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
5095 EVT VT = N->getValueType(i);
5096 if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
5097 VTs.push_back(VT);
5098 }
5099 if (Load)
5100 BeforeOps.push_back(SDValue(Load, 0));
5101 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
5102 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
5103 NewNodes.push_back(NewNode);
5105 // Emit the store instruction.
5106 if (FoldedStore) {
5107 AddrOps.pop_back();
5108 AddrOps.push_back(SDValue(NewNode, 0));
5109 AddrOps.push_back(Chain);
5110 std::pair<MachineInstr::mmo_iterator,
5111 MachineInstr::mmo_iterator> MMOs =
5112 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
5113 cast<MachineSDNode>(N)->memoperands_end());
5114 if (!(*MMOs.first) &&
5115 RC == &X86::VR128RegClass &&
5116 !Subtarget.isUnalignedMemAccessFast())
5117 // Do not introduce a slow unaligned store.
5118 return false;
5119 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
5120 bool isAligned = (*MMOs.first) &&
5121 (*MMOs.first)->getAlignment() >= Alignment;
5122 SDNode *Store =
5123 DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
5124 dl, MVT::Other, AddrOps);
5125 NewNodes.push_back(Store);
5127 // Preserve memory reference information.
5128 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
5129 }
5131 return true;
5132 }
5134 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
5135 bool UnfoldLoad, bool UnfoldStore,
5136 unsigned *LoadRegIndex) const {
5137 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
5138 MemOp2RegOpTable.find(Opc);
5139 if (I == MemOp2RegOpTable.end())
5140 return 0;
5141 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
5142 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
5143 if (UnfoldLoad && !FoldedLoad)
5144 return 0;
5145 if (UnfoldStore && !FoldedStore)
5146 return 0;
5147 if (LoadRegIndex)
5148 *LoadRegIndex = I->second.second & TB_INDEX_MASK;
5149 return I->second.first;
5150 }
5152 bool
5153 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
5154 int64_t &Offset1, int64_t &Offset2) const {
5155 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
5156 return false;
5157 unsigned Opc1 = Load1->getMachineOpcode();
5158 unsigned Opc2 = Load2->getMachineOpcode();
5159 switch (Opc1) {
5160 default: return false;
5161 case X86::MOV8rm:
5162 case X86::MOV16rm:
5163 case X86::MOV32rm:
5164 case X86::MOV64rm:
5165 case X86::LD_Fp32m:
5166 case X86::LD_Fp64m:
5167 case X86::LD_Fp80m:
5168 case X86::MOVSSrm:
5169 case X86::MOVSDrm:
5170 case X86::MMX_MOVD64rm:
5171 case X86::MMX_MOVQ64rm:
5172 case X86::FsMOVAPSrm:
5173 case X86::FsMOVAPDrm:
5174 case X86::MOVAPSrm:
5175 case X86::MOVUPSrm:
5176 case X86::MOVAPDrm:
5177 case X86::MOVDQArm:
5178 case X86::MOVDQUrm:
5179 // AVX load instructions
5180 case X86::VMOVSSrm:
5181 case X86::VMOVSDrm:
5182 case X86::FsVMOVAPSrm:
5183 case X86::FsVMOVAPDrm:
5184 case X86::VMOVAPSrm:
5185 case X86::VMOVUPSrm:
5186 case X86::VMOVAPDrm:
5187 case X86::VMOVDQArm:
5188 case X86::VMOVDQUrm:
5189 case X86::VMOVAPSYrm:
5190 case X86::VMOVUPSYrm:
5191 case X86::VMOVAPDYrm:
5192 case X86::VMOVDQAYrm:
5193 case X86::VMOVDQUYrm:
5194 break;
5195 }
5196 switch (Opc2) {
5197 default: return false;
5198 case X86::MOV8rm:
5199 case X86::MOV16rm:
5200 case X86::MOV32rm:
5201 case X86::MOV64rm:
5202 case X86::LD_Fp32m:
5203 case X86::LD_Fp64m:
5204 case X86::LD_Fp80m:
5205 case X86::MOVSSrm:
5206 case X86::MOVSDrm:
5207 case X86::MMX_MOVD64rm:
5208 case X86::MMX_MOVQ64rm:
5209 case X86::FsMOVAPSrm:
5210 case X86::FsMOVAPDrm:
5211 case X86::MOVAPSrm:
5212 case X86::MOVUPSrm:
5213 case X86::MOVAPDrm:
5214 case X86::MOVDQArm:
5215 case X86::MOVDQUrm:
5216 // AVX load instructions
5217 case X86::VMOVSSrm:
5218 case X86::VMOVSDrm:
5219 case X86::FsVMOVAPSrm:
5220 case X86::FsVMOVAPDrm:
5221 case X86::VMOVAPSrm:
5222 case X86::VMOVUPSrm:
5223 case X86::VMOVAPDrm:
5224 case X86::VMOVDQArm:
5225 case X86::VMOVDQUrm:
5226 case X86::VMOVAPSYrm:
5227 case X86::VMOVUPSYrm:
5228 case X86::VMOVAPDYrm:
5229 case X86::VMOVDQAYrm:
5230 case X86::VMOVDQUYrm:
5231 break;
5232 }
5234 // Check if chain operands and base addresses match.
5235 if (Load1->getOperand(0) != Load2->getOperand(0) ||
5236 Load1->getOperand(5) != Load2->getOperand(5))
5237 return false;
5238 // Segment operands should match as well.
5239 if (Load1->getOperand(4) != Load2->getOperand(4))
5240 return false;
5241 // Scale should be 1, Index should be Reg0.
5242 if (Load1->getOperand(1) == Load2->getOperand(1) &&
5243 Load1->getOperand(2) == Load2->getOperand(2)) {
5244 if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
5245 return false;
5247 // Now let's examine the displacements.
5248 if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
5249 isa<ConstantSDNode>(Load2->getOperand(3))) {
5250 Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
5251 Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
5252 return true;
5253 }
5254 }
5255 return false;
5256 }
5258 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
5259 int64_t Offset1, int64_t Offset2,
5260 unsigned NumLoads) const {
5261 assert(Offset2 > Offset1);
5262 if ((Offset2 - Offset1) / 8 > 64)
5263 return false;
5265 unsigned Opc1 = Load1->getMachineOpcode();
5266 unsigned Opc2 = Load2->getMachineOpcode();
5267 if (Opc1 != Opc2)
5268 return false; // FIXME: overly conservative?
5270 switch (Opc1) {
5271 default: break;
5272 case X86::LD_Fp32m:
5273 case X86::LD_Fp64m:
5274 case X86::LD_Fp80m:
5275 case X86::MMX_MOVD64rm:
5276 case X86::MMX_MOVQ64rm:
5277 return false;
5278 }
5280 EVT VT = Load1->getValueType(0);
5281 switch (VT.getSimpleVT().SimpleTy) {
5282 default:
5283 // XMM registers. In 64-bit mode we can be a bit more aggressive since we
5284 // have 16 of them to play with.
5285 if (Subtarget.is64Bit()) {
5286 if (NumLoads >= 3)
5287 return false;
5288 } else if (NumLoads) {
5289 return false;
5290 }
5291 break;
5292 case MVT::i8:
5293 case MVT::i16:
5294 case MVT::i32:
5295 case MVT::i64:
5296 case MVT::f32:
5297 case MVT::f64:
5298 if (NumLoads)
5299 return false;
5300 break;
5301 }
5303 return true;
5304 }
5306 bool X86InstrInfo::shouldScheduleAdjacent(MachineInstr* First,
5307 MachineInstr *Second) const {
5308 // Check if this processor supports macro-fusion. Since this is a minor
5309 // heuristic, we haven't specifically reserved a feature. hasAVX is a decent
5310 // proxy for SandyBridge+.
5311 if (!Subtarget.hasAVX())
5312 return false;
5314 enum {
5315 FuseTest,
5316 FuseCmp,
5317 FuseInc
5318 } FuseKind;
5320 switch(Second->getOpcode()) {
5321 default:
5322 return false;
5323 case X86::JE_4:
5324 case X86::JNE_4:
5325 case X86::JL_4:
5326 case X86::JLE_4:
5327 case X86::JG_4:
5328 case X86::JGE_4:
5329 FuseKind = FuseInc;
5330 break;
5331 case X86::JB_4:
5332 case X86::JBE_4:
5333 case X86::JA_4:
5334 case X86::JAE_4:
5335 FuseKind = FuseCmp;
5336 break;
5337 case X86::JS_4:
5338 case X86::JNS_4:
5339 case X86::JP_4:
5340 case X86::JNP_4:
5341 case X86::JO_4:
5342 case X86::JNO_4:
5343 FuseKind = FuseTest;
5344 break;
5345 }
5346 switch (First->getOpcode()) {
5347 default:
5348 return false;
5349 case X86::TEST8rr:
5350 case X86::TEST16rr:
5351 case X86::TEST32rr:
5352 case X86::TEST64rr:
5353 case X86::TEST8ri:
5354 case X86::TEST16ri:
5355 case X86::TEST32ri:
5356 case X86::TEST32i32:
5357 case X86::TEST64i32:
5358 case X86::TEST64ri32:
5359 case X86::TEST8rm:
5360 case X86::TEST16rm:
5361 case X86::TEST32rm:
5362 case X86::TEST64rm:
5363 case X86::TEST8ri_NOREX:
5364 case X86::AND16i16:
5365 case X86::AND16ri:
5366 case X86::AND16ri8:
5367 case X86::AND16rm:
5368 case X86::AND16rr:
5369 case X86::AND32i32:
5370 case X86::AND32ri:
5371 case X86::AND32ri8:
5372 case X86::AND32rm:
5373 case X86::AND32rr:
5374 case X86::AND64i32:
5375 case X86::AND64ri32:
5376 case X86::AND64ri8:
5377 case X86::AND64rm:
5378 case X86::AND64rr:
5379 case X86::AND8i8:
5380 case X86::AND8ri:
5381 case X86::AND8rm:
5382 case X86::AND8rr:
5383 return true;
5384 case X86::CMP16i16:
5385 case X86::CMP16ri:
5386 case X86::CMP16ri8:
5387 case X86::CMP16rm:
5388 case X86::CMP16rr:
5389 case X86::CMP32i32:
5390 case X86::CMP32ri:
5391 case X86::CMP32ri8:
5392 case X86::CMP32rm:
5393 case X86::CMP32rr:
5394 case X86::CMP64i32:
5395 case X86::CMP64ri32:
5396 case X86::CMP64ri8:
5397 case X86::CMP64rm:
5398 case X86::CMP64rr:
5399 case X86::CMP8i8:
5400 case X86::CMP8ri:
5401 case X86::CMP8rm:
5402 case X86::CMP8rr:
5403 case X86::ADD16i16:
5404 case X86::ADD16ri:
5405 case X86::ADD16ri8:
5406 case X86::ADD16ri8_DB:
5407 case X86::ADD16ri_DB:
5408 case X86::ADD16rm:
5409 case X86::ADD16rr:
5410 case X86::ADD16rr_DB:
5411 case X86::ADD32i32:
5412 case X86::ADD32ri:
5413 case X86::ADD32ri8:
5414 case X86::ADD32ri8_DB:
5415 case X86::ADD32ri_DB:
5416 case X86::ADD32rm:
5417 case X86::ADD32rr:
5418 case X86::ADD32rr_DB:
5419 case X86::ADD64i32:
5420 case X86::ADD64ri32:
5421 case X86::ADD64ri32_DB:
5422 case X86::ADD64ri8:
5423 case X86::ADD64ri8_DB:
5424 case X86::ADD64rm:
5425 case X86::ADD64rr:
5426 case X86::ADD64rr_DB:
5427 case X86::ADD8i8:
5428 case X86::ADD8mi:
5429 case X86::ADD8mr:
5430 case X86::ADD8ri:
5431 case X86::ADD8rm:
5432 case X86::ADD8rr:
5433 case X86::SUB16i16:
5434 case X86::SUB16ri:
5435 case X86::SUB16ri8:
5436 case X86::SUB16rm:
5437 case X86::SUB16rr:
5438 case X86::SUB32i32:
5439 case X86::SUB32ri:
5440 case X86::SUB32ri8:
5441 case X86::SUB32rm:
5442 case X86::SUB32rr:
5443 case X86::SUB64i32:
5444 case X86::SUB64ri32:
5445 case X86::SUB64ri8:
5446 case X86::SUB64rm:
5447 case X86::SUB64rr:
5448 case X86::SUB8i8:
5449 case X86::SUB8ri:
5450 case X86::SUB8rm:
5451 case X86::SUB8rr:
5452 return FuseKind == FuseCmp || FuseKind == FuseInc;
5453 case X86::INC16r:
5454 case X86::INC32r:
5455 case X86::INC64_16r:
5456 case X86::INC64_32r:
5457 case X86::INC64r:
5458 case X86::INC8r:
5459 case X86::DEC16r:
5460 case X86::DEC32r:
5461 case X86::DEC64_16r:
5462 case X86::DEC64_32r:
5463 case X86::DEC64r:
5464 case X86::DEC8r:
5465 return FuseKind == FuseInc;
5466 }
5467 }
5469 bool X86InstrInfo::
5470 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
5471 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
5472 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
5473 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
5474 return true;
5475 Cond[0].setImm(GetOppositeBranchCondition(CC));
5476 return false;
5477 }
5479 bool X86InstrInfo::
5480 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
5481 // FIXME: Return false for x87 stack register classes for now. We can't
5482 // allow any loads of these registers before FpGet_ST0_80.
5483 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
5484 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
5485 }
5487 /// getGlobalBaseReg - Return a virtual register initialized with the
5488 /// the global base register value. Output instructions required to
5489 /// initialize the register in the function entry block, if necessary.
5490 ///
5491 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
5492 ///
5493 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
5494 assert(!Subtarget.is64Bit() &&
5495 "X86-64 PIC uses RIP relative addressing");
5497 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
5498 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
5499 if (GlobalBaseReg != 0)
5500 return GlobalBaseReg;
5502 // Create the register. The code to initialize it is inserted
5503 // later, by the CGBR pass (below).
5504 MachineRegisterInfo &RegInfo = MF->getRegInfo();
5505 GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
5506 X86FI->setGlobalBaseReg(GlobalBaseReg);
5507 return GlobalBaseReg;
5508 }
5510 // These are the replaceable SSE instructions. Some of these have Int variants
5511 // that we don't include here. We don't want to replace instructions selected
5512 // by intrinsics.
5513 static const uint16_t ReplaceableInstrs[][3] = {
5514 //PackedSingle PackedDouble PackedInt
5515 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr },
5516 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm },
5517 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr },
5518 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr },
5519 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm },
5520 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr },
5521 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm },
5522 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr },
5523 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm },
5524 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr },
5525 { X86::ORPSrm, X86::ORPDrm, X86::PORrm },
5526 { X86::ORPSrr, X86::ORPDrr, X86::PORrr },
5527 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm },
5528 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr },
5529 // AVX 128-bit support
5530 { X86::VMOVAPSmr, X86::VMOVAPDmr, X86::VMOVDQAmr },
5531 { X86::VMOVAPSrm, X86::VMOVAPDrm, X86::VMOVDQArm },
5532 { X86::VMOVAPSrr, X86::VMOVAPDrr, X86::VMOVDQArr },
5533 { X86::VMOVUPSmr, X86::VMOVUPDmr, X86::VMOVDQUmr },
5534 { X86::VMOVUPSrm, X86::VMOVUPDrm, X86::VMOVDQUrm },
5535 { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
5536 { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm },
5537 { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr },
5538 { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDrm },
5539 { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr },
5540 { X86::VORPSrm, X86::VORPDrm, X86::VPORrm },
5541 { X86::VORPSrr, X86::VORPDrr, X86::VPORrr },
5542 { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm },
5543 { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr },
5544 // AVX 256-bit support
5545 { X86::VMOVAPSYmr, X86::VMOVAPDYmr, X86::VMOVDQAYmr },
5546 { X86::VMOVAPSYrm, X86::VMOVAPDYrm, X86::VMOVDQAYrm },
5547 { X86::VMOVAPSYrr, X86::VMOVAPDYrr, X86::VMOVDQAYrr },
5548 { X86::VMOVUPSYmr, X86::VMOVUPDYmr, X86::VMOVDQUYmr },
5549 { X86::VMOVUPSYrm, X86::VMOVUPDYrm, X86::VMOVDQUYrm },
5550 { X86::VMOVNTPSYmr, X86::VMOVNTPDYmr, X86::VMOVNTDQYmr }
5551 };
5553 static const uint16_t ReplaceableInstrsAVX2[][3] = {
5554 //PackedSingle PackedDouble PackedInt
5555 { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNYrm },
5556 { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNYrr },
5557 { X86::VANDPSYrm, X86::VANDPDYrm, X86::VPANDYrm },
5558 { X86::VANDPSYrr, X86::VANDPDYrr, X86::VPANDYrr },
5559 { X86::VORPSYrm, X86::VORPDYrm, X86::VPORYrm },
5560 { X86::VORPSYrr, X86::VORPDYrr, X86::VPORYrr },
5561 { X86::VXORPSYrm, X86::VXORPDYrm, X86::VPXORYrm },
5562 { X86::VXORPSYrr, X86::VXORPDYrr, X86::VPXORYrr },
5563 { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
5564 { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
5565 { X86::VINSERTF128rm, X86::VINSERTF128rm, X86::VINSERTI128rm },
5566 { X86::VINSERTF128rr, X86::VINSERTF128rr, X86::VINSERTI128rr },
5567 { X86::VPERM2F128rm, X86::VPERM2F128rm, X86::VPERM2I128rm },
5568 { X86::VPERM2F128rr, X86::VPERM2F128rr, X86::VPERM2I128rr },
5569 { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
5570 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
5571 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
5572 { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
5573 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
5574 { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm}
5575 };
5577 // FIXME: Some shuffle and unpack instructions have equivalents in different
5578 // domains, but they require a bit more work than just switching opcodes.
5580 static const uint16_t *lookup(unsigned opcode, unsigned domain) {
5581 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i)
5582 if (ReplaceableInstrs[i][domain-1] == opcode)
5583 return ReplaceableInstrs[i];
5584 return nullptr;
5585 }
5587 static const uint16_t *lookupAVX2(unsigned opcode, unsigned domain) {
5588 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrsAVX2); i != e; ++i)
5589 if (ReplaceableInstrsAVX2[i][domain-1] == opcode)
5590 return ReplaceableInstrsAVX2[i];
5591 return nullptr;
5592 }
5594 std::pair<uint16_t, uint16_t>
5595 X86InstrInfo::getExecutionDomain(const MachineInstr *MI) const {
5596 uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
5597 bool hasAVX2 = Subtarget.hasAVX2();
5598 uint16_t validDomains = 0;
5599 if (domain && lookup(MI->getOpcode(), domain))
5600 validDomains = 0xe;
5601 else if (domain && lookupAVX2(MI->getOpcode(), domain))
5602 validDomains = hasAVX2 ? 0xe : 0x6;
5603 return std::make_pair(domain, validDomains);
5604 }
5606 void X86InstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
5607 assert(Domain>0 && Domain<4 && "Invalid execution domain");
5608 uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
5609 assert(dom && "Not an SSE instruction");
5610 const uint16_t *table = lookup(MI->getOpcode(), dom);
5611 if (!table) { // try the other table
5612 assert((Subtarget.hasAVX2() || Domain < 3) &&
5613 "256-bit vector operations only available in AVX2");
5614 table = lookupAVX2(MI->getOpcode(), dom);
5615 }
5616 assert(table && "Cannot change domain");
5617 MI->setDesc(get(table[Domain-1]));
5618 }
5620 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
5621 void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
5622 NopInst.setOpcode(X86::NOOP);
5623 }
5625 // This code must remain in sync with getJumpInstrTableEntryBound in this class!
5626 // In particular, getJumpInstrTableEntryBound must always return an upper bound
5627 // on the encoding lengths of the instructions generated by
5628 // getUnconditionalBranch and getTrap.
5629 void X86InstrInfo::getUnconditionalBranch(
5630 MCInst &Branch, const MCSymbolRefExpr *BranchTarget) const {
5631 Branch.setOpcode(X86::JMP_4);
5632 Branch.addOperand(MCOperand::CreateExpr(BranchTarget));
5633 }
5635 // This code must remain in sync with getJumpInstrTableEntryBound in this class!
5636 // In particular, getJumpInstrTableEntryBound must always return an upper bound
5637 // on the encoding lengths of the instructions generated by
5638 // getUnconditionalBranch and getTrap.
5639 void X86InstrInfo::getTrap(MCInst &MI) const {
5640 MI.setOpcode(X86::TRAP);
5641 }
5643 // See getTrap and getUnconditionalBranch for conditions on the value returned
5644 // by this function.
5645 unsigned X86InstrInfo::getJumpInstrTableEntryBound() const {
5646 // 5 bytes suffice: JMP_4 Symbol@PLT is uses 1 byte (E9) for the JMP_4 and 4
5647 // bytes for the symbol offset. And TRAP is ud2, which is two bytes (0F 0B).
5648 return 5;
5649 }
5651 bool X86InstrInfo::isHighLatencyDef(int opc) const {
5652 switch (opc) {
5653 default: return false;
5654 case X86::DIVSDrm:
5655 case X86::DIVSDrm_Int:
5656 case X86::DIVSDrr:
5657 case X86::DIVSDrr_Int:
5658 case X86::DIVSSrm:
5659 case X86::DIVSSrm_Int:
5660 case X86::DIVSSrr:
5661 case X86::DIVSSrr_Int:
5662 case X86::SQRTPDm:
5663 case X86::SQRTPDr:
5664 case X86::SQRTPSm:
5665 case X86::SQRTPSr:
5666 case X86::SQRTSDm:
5667 case X86::SQRTSDm_Int:
5668 case X86::SQRTSDr:
5669 case X86::SQRTSDr_Int:
5670 case X86::SQRTSSm:
5671 case X86::SQRTSSm_Int:
5672 case X86::SQRTSSr:
5673 case X86::SQRTSSr_Int:
5674 // AVX instructions with high latency
5675 case X86::VDIVSDrm:
5676 case X86::VDIVSDrm_Int:
5677 case X86::VDIVSDrr:
5678 case X86::VDIVSDrr_Int:
5679 case X86::VDIVSSrm:
5680 case X86::VDIVSSrm_Int:
5681 case X86::VDIVSSrr:
5682 case X86::VDIVSSrr_Int:
5683 case X86::VSQRTPDm:
5684 case X86::VSQRTPDr:
5685 case X86::VSQRTPSm:
5686 case X86::VSQRTPSr:
5687 case X86::VSQRTSDm:
5688 case X86::VSQRTSDm_Int:
5689 case X86::VSQRTSDr:
5690 case X86::VSQRTSSm:
5691 case X86::VSQRTSSm_Int:
5692 case X86::VSQRTSSr:
5693 case X86::VSQRTPDZm:
5694 case X86::VSQRTPDZr:
5695 case X86::VSQRTPSZm:
5696 case X86::VSQRTPSZr:
5697 case X86::VSQRTSDZm:
5698 case X86::VSQRTSDZm_Int:
5699 case X86::VSQRTSDZr:
5700 case X86::VSQRTSSZm_Int:
5701 case X86::VSQRTSSZr:
5702 case X86::VSQRTSSZm:
5703 case X86::VDIVSDZrm:
5704 case X86::VDIVSDZrr:
5705 case X86::VDIVSSZrm:
5706 case X86::VDIVSSZrr:
5708 case X86::VGATHERQPSZrm:
5709 case X86::VGATHERQPDZrm:
5710 case X86::VGATHERDPDZrm:
5711 case X86::VGATHERDPSZrm:
5712 case X86::VPGATHERQDZrm:
5713 case X86::VPGATHERQQZrm:
5714 case X86::VPGATHERDDZrm:
5715 case X86::VPGATHERDQZrm:
5716 case X86::VSCATTERQPDZmr:
5717 case X86::VSCATTERQPSZmr:
5718 case X86::VSCATTERDPDZmr:
5719 case X86::VSCATTERDPSZmr:
5720 case X86::VPSCATTERQDZmr:
5721 case X86::VPSCATTERQQZmr:
5722 case X86::VPSCATTERDDZmr:
5723 case X86::VPSCATTERDQZmr:
5724 return true;
5725 }
5726 }
5728 bool X86InstrInfo::
5729 hasHighOperandLatency(const InstrItineraryData *ItinData,
5730 const MachineRegisterInfo *MRI,
5731 const MachineInstr *DefMI, unsigned DefIdx,
5732 const MachineInstr *UseMI, unsigned UseIdx) const {
5733 return isHighLatencyDef(DefMI->getOpcode());
5734 }
5736 namespace {
5737 /// CGBR - Create Global Base Reg pass. This initializes the PIC
5738 /// global base register for x86-32.
5739 struct CGBR : public MachineFunctionPass {
5740 static char ID;
5741 CGBR() : MachineFunctionPass(ID) {}
5743 bool runOnMachineFunction(MachineFunction &MF) override {
5744 const X86TargetMachine *TM =
5745 static_cast<const X86TargetMachine *>(&MF.getTarget());
5747 // Don't do anything if this is 64-bit as 64-bit PIC
5748 // uses RIP relative addressing.
5749 if (TM->getSubtarget<X86Subtarget>().is64Bit())
5750 return false;
5752 // Only emit a global base reg in PIC mode.
5753 if (TM->getRelocationModel() != Reloc::PIC_)
5754 return false;
5756 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
5757 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
5759 // If we didn't need a GlobalBaseReg, don't insert code.
5760 if (GlobalBaseReg == 0)
5761 return false;
5763 // Insert the set of GlobalBaseReg into the first MBB of the function
5764 MachineBasicBlock &FirstMBB = MF.front();
5765 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
5766 DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
5767 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5768 const X86InstrInfo *TII = TM->getSubtargetImpl()->getInstrInfo();
5770 unsigned PC;
5771 if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT())
5772 PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
5773 else
5774 PC = GlobalBaseReg;
5776 // Operand of MovePCtoStack is completely ignored by asm printer. It's
5777 // only used in JIT code emission as displacement to pc.
5778 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
5780 // If we're using vanilla 'GOT' PIC style, we should use relative addressing
5781 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
5782 if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT()) {
5783 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
5784 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
5785 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
5786 X86II::MO_GOT_ABSOLUTE_ADDRESS);
5787 }
5789 return true;
5790 }
5792 const char *getPassName() const override {
5793 return "X86 PIC Global Base Reg Initialization";
5794 }
5796 void getAnalysisUsage(AnalysisUsage &AU) const override {
5797 AU.setPreservesCFG();
5798 MachineFunctionPass::getAnalysisUsage(AU);
5799 }
5800 };
5801 }
5803 char CGBR::ID = 0;
5804 FunctionPass*
5805 llvm::createX86GlobalBaseRegPass() { return new CGBR(); }
5807 namespace {
5808 struct LDTLSCleanup : public MachineFunctionPass {
5809 static char ID;
5810 LDTLSCleanup() : MachineFunctionPass(ID) {}
5812 bool runOnMachineFunction(MachineFunction &MF) override {
5813 X86MachineFunctionInfo* MFI = MF.getInfo<X86MachineFunctionInfo>();
5814 if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
5815 // No point folding accesses if there isn't at least two.
5816 return false;
5817 }
5819 MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
5820 return VisitNode(DT->getRootNode(), 0);
5821 }
5823 // Visit the dominator subtree rooted at Node in pre-order.
5824 // If TLSBaseAddrReg is non-null, then use that to replace any
5825 // TLS_base_addr instructions. Otherwise, create the register
5826 // when the first such instruction is seen, and then use it
5827 // as we encounter more instructions.
5828 bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
5829 MachineBasicBlock *BB = Node->getBlock();
5830 bool Changed = false;
5832 // Traverse the current block.
5833 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
5834 ++I) {
5835 switch (I->getOpcode()) {
5836 case X86::TLS_base_addr32:
5837 case X86::TLS_base_addr64:
5838 if (TLSBaseAddrReg)
5839 I = ReplaceTLSBaseAddrCall(I, TLSBaseAddrReg);
5840 else
5841 I = SetRegister(I, &TLSBaseAddrReg);
5842 Changed = true;
5843 break;
5844 default:
5845 break;
5846 }
5847 }
5849 // Visit the children of this block in the dominator tree.
5850 for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
5851 I != E; ++I) {
5852 Changed |= VisitNode(*I, TLSBaseAddrReg);
5853 }
5855 return Changed;
5856 }
5858 // Replace the TLS_base_addr instruction I with a copy from
5859 // TLSBaseAddrReg, returning the new instruction.
5860 MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr *I,
5861 unsigned TLSBaseAddrReg) {
5862 MachineFunction *MF = I->getParent()->getParent();
5863 const X86TargetMachine *TM =
5864 static_cast<const X86TargetMachine *>(&MF->getTarget());
5865 const bool is64Bit = TM->getSubtarget<X86Subtarget>().is64Bit();
5866 const X86InstrInfo *TII = TM->getSubtargetImpl()->getInstrInfo();
5868 // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
5869 MachineInstr *Copy = BuildMI(*I->getParent(), I, I->getDebugLoc(),
5870 TII->get(TargetOpcode::COPY),
5871 is64Bit ? X86::RAX : X86::EAX)
5872 .addReg(TLSBaseAddrReg);
5874 // Erase the TLS_base_addr instruction.
5875 I->eraseFromParent();
5877 return Copy;
5878 }
5880 // Create a virtal register in *TLSBaseAddrReg, and populate it by
5881 // inserting a copy instruction after I. Returns the new instruction.
5882 MachineInstr *SetRegister(MachineInstr *I, unsigned *TLSBaseAddrReg) {
5883 MachineFunction *MF = I->getParent()->getParent();
5884 const X86TargetMachine *TM =
5885 static_cast<const X86TargetMachine *>(&MF->getTarget());
5886 const bool is64Bit = TM->getSubtarget<X86Subtarget>().is64Bit();
5887 const X86InstrInfo *TII = TM->getSubtargetImpl()->getInstrInfo();
5889 // Create a virtual register for the TLS base address.
5890 MachineRegisterInfo &RegInfo = MF->getRegInfo();
5891 *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
5892 ? &X86::GR64RegClass
5893 : &X86::GR32RegClass);
5895 // Insert a copy from RAX/EAX to TLSBaseAddrReg.
5896 MachineInstr *Next = I->getNextNode();
5897 MachineInstr *Copy = BuildMI(*I->getParent(), Next, I->getDebugLoc(),
5898 TII->get(TargetOpcode::COPY),
5899 *TLSBaseAddrReg)
5900 .addReg(is64Bit ? X86::RAX : X86::EAX);
5902 return Copy;
5903 }
5905 const char *getPassName() const override {
5906 return "Local Dynamic TLS Access Clean-up";
5907 }
5909 void getAnalysisUsage(AnalysisUsage &AU) const override {
5910 AU.setPreservesCFG();
5911 AU.addRequired<MachineDominatorTree>();
5912 MachineFunctionPass::getAnalysisUsage(AU);
5913 }
5914 };
5915 }
5917 char LDTLSCleanup::ID = 0;
5918 FunctionPass*
5919 llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }