1 //====- X86InstrMMX.td - Describe the X86 Instruction Set --*- tablegen -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file describes the X86 MMX instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
13 //
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // MMX Pattern Fragments
18 //===----------------------------------------------------------------------===//
20 def load_mmx : PatFrag<(ops node:$ptr), (v1i64 (load node:$ptr))>;
22 def bc_v8i8 : PatFrag<(ops node:$in), (v8i8 (bitconvert node:$in))>;
23 def bc_v4i16 : PatFrag<(ops node:$in), (v4i16 (bitconvert node:$in))>;
24 def bc_v2i32 : PatFrag<(ops node:$in), (v2i32 (bitconvert node:$in))>;
25 def bc_v1i64 : PatFrag<(ops node:$in), (v1i64 (bitconvert node:$in))>;
27 //===----------------------------------------------------------------------===//
28 // MMX Masks
29 //===----------------------------------------------------------------------===//
31 // MMX_SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to
32 // PSHUFW imm.
33 def MMX_SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
34 return getI8Imm(X86::getShuffleSHUFImmediate(N));
35 }]>;
37 // Patterns for: vector_shuffle v1, v2, <2, 6, 3, 7, ...>
38 def MMX_UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{
39 return X86::isUNPCKHMask(N);
40 }]>;
42 // Patterns for: vector_shuffle v1, v2, <0, 4, 2, 5, ...>
43 def MMX_UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
44 return X86::isUNPCKLMask(N);
45 }]>;
47 // Patterns for: vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
48 def MMX_UNPCKH_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
49 return X86::isUNPCKH_v_undef_Mask(N);
50 }]>;
52 // Patterns for: vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
53 def MMX_UNPCKL_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
54 return X86::isUNPCKL_v_undef_Mask(N);
55 }]>;
57 // Patterns for shuffling.
58 def MMX_PSHUFW_shuffle_mask : PatLeaf<(build_vector), [{
59 return X86::isPSHUFDMask(N);
60 }], MMX_SHUFFLE_get_shuf_imm>;
62 // Patterns for: vector_shuffle v1, v2, <4, 5, 2, 3>; etc.
63 def MMX_MOVL_shuffle_mask : PatLeaf<(build_vector), [{
64 return X86::isMOVLMask(N);
65 }]>;
67 //===----------------------------------------------------------------------===//
68 // MMX Multiclasses
69 //===----------------------------------------------------------------------===//
71 let isTwoAddress = 1 in {
72 // MMXI_binop_rm - Simple MMX binary operator.
73 multiclass MMXI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
74 ValueType OpVT, bit Commutable = 0> {
75 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
76 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
77 [(set VR64:$dst, (OpVT (OpNode VR64:$src1, VR64:$src2)))]> {
78 let isCommutable = Commutable;
79 }
80 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
81 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
82 [(set VR64:$dst, (OpVT (OpNode VR64:$src1,
83 (bitconvert
84 (load_mmx addr:$src2)))))]>;
85 }
87 multiclass MMXI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
88 bit Commutable = 0> {
89 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
90 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
91 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]> {
92 let isCommutable = Commutable;
93 }
94 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
95 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
96 [(set VR64:$dst, (IntId VR64:$src1,
97 (bitconvert (load_mmx addr:$src2))))]>;
98 }
100 // MMXI_binop_rm_v1i64 - Simple MMX binary operator whose type is v1i64.
101 //
102 // FIXME: we could eliminate this and use MMXI_binop_rm instead if tblgen knew
103 // to collapse (bitconvert VT to VT) into its operand.
104 //
105 multiclass MMXI_binop_rm_v1i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
106 bit Commutable = 0> {
107 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
108 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
109 [(set VR64:$dst, (v1i64 (OpNode VR64:$src1, VR64:$src2)))]> {
110 let isCommutable = Commutable;
111 }
112 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
113 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
114 [(set VR64:$dst,
115 (OpNode VR64:$src1,(load_mmx addr:$src2)))]>;
116 }
118 multiclass MMXI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
119 string OpcodeStr, Intrinsic IntId,
120 Intrinsic ImmIntId> {
121 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
122 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
123 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]>;
124 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
125 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
126 [(set VR64:$dst, (IntId VR64:$src1,
127 (bitconvert (load_mmx addr:$src2))))]>;
128 def ri : MMXIi8<opc2, ImmForm, (outs VR64:$dst), (ins VR64:$src1, i32i8imm:$src2),
129 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
130 [(set VR64:$dst, (ImmIntId VR64:$src1, imm:$src2))]>;
131 }
132 }
134 //===----------------------------------------------------------------------===//
135 // MMX EMMS & FEMMS Instructions
136 //===----------------------------------------------------------------------===//
138 def MMX_EMMS : MMXI<0x77, RawFrm, (outs), (ins), "emms", [(int_x86_mmx_emms)]>;
139 def MMX_FEMMS : MMXI<0x0E, RawFrm, (outs), (ins), "femms", [(int_x86_mmx_femms)]>;
141 //===----------------------------------------------------------------------===//
142 // MMX Scalar Instructions
143 //===----------------------------------------------------------------------===//
145 // Data Transfer Instructions
146 def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
147 "movd\t{$src, $dst|$dst, $src}",
148 [(set VR64:$dst, (v2i32 (scalar_to_vector GR32:$src)))]>;
149 let isSimpleLoad = 1, isReMaterializable = 1 in
150 def MMX_MOVD64rm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src),
151 "movd\t{$src, $dst|$dst, $src}",
152 [(set VR64:$dst, (v2i32 (scalar_to_vector (loadi32 addr:$src))))]>;
153 let mayStore = 1 in
154 def MMX_MOVD64mr : MMXI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR64:$src),
155 "movd\t{$src, $dst|$dst, $src}", []>;
157 let neverHasSideEffects = 1 in
158 def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
159 "movd\t{$src, $dst|$dst, $src}", []>;
161 let neverHasSideEffects = 1 in
162 def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
163 "movq\t{$src, $dst|$dst, $src}", []>;
164 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
165 def MMX_MOVQ64rm : MMXI<0x6F, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
166 "movq\t{$src, $dst|$dst, $src}",
167 [(set VR64:$dst, (load_mmx addr:$src))]>;
168 def MMX_MOVQ64mr : MMXI<0x7F, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
169 "movq\t{$src, $dst|$dst, $src}",
170 [(store (v1i64 VR64:$src), addr:$dst)]>;
172 def MMX_MOVDQ2Qrr : MMXID<0xD6, MRMDestMem, (outs VR64:$dst), (ins VR128:$src),
173 "movdq2q\t{$src, $dst|$dst, $src}",
174 [(set VR64:$dst,
175 (v1i64 (vector_extract (v2i64 VR128:$src),
176 (iPTR 0))))]>;
178 def MMX_MOVQ2DQrr : MMXIS<0xD6, MRMDestMem, (outs VR128:$dst), (ins VR64:$src),
179 "movq2dq\t{$src, $dst|$dst, $src}",
180 [(set VR128:$dst,
181 (bitconvert (v1i64 VR64:$src)))]>;
183 def MMX_MOVNTQmr : MMXI<0xE7, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
184 "movntq\t{$src, $dst|$dst, $src}",
185 [(int_x86_mmx_movnt_dq addr:$dst, VR64:$src)]>;
187 let AddedComplexity = 15 in
188 // movd to MMX register zero-extends
189 def MMX_MOVZDI2PDIrr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
190 "movd\t{$src, $dst|$dst, $src}",
191 [(set VR64:$dst,
192 (v2i32 (vector_shuffle immAllZerosV,
193 (v2i32 (scalar_to_vector GR32:$src)),
194 MMX_MOVL_shuffle_mask)))]>;
195 let AddedComplexity = 20 in
196 def MMX_MOVZDI2PDIrm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src),
197 "movd\t{$src, $dst|$dst, $src}",
198 [(set VR64:$dst,
199 (v2i32 (vector_shuffle immAllZerosV,
200 (v2i32 (scalar_to_vector
201 (loadi32 addr:$src))),
202 MMX_MOVL_shuffle_mask)))]>;
204 // Arithmetic Instructions
206 // -- Addition
207 defm MMX_PADDB : MMXI_binop_rm<0xFC, "paddb", add, v8i8, 1>;
208 defm MMX_PADDW : MMXI_binop_rm<0xFD, "paddw", add, v4i16, 1>;
209 defm MMX_PADDD : MMXI_binop_rm<0xFE, "paddd", add, v2i32, 1>;
210 defm MMX_PADDQ : MMXI_binop_rm<0xD4, "paddq", add, v1i64, 1>;
212 defm MMX_PADDSB : MMXI_binop_rm_int<0xEC, "paddsb" , int_x86_mmx_padds_b, 1>;
213 defm MMX_PADDSW : MMXI_binop_rm_int<0xED, "paddsw" , int_x86_mmx_padds_w, 1>;
215 defm MMX_PADDUSB : MMXI_binop_rm_int<0xDC, "paddusb", int_x86_mmx_paddus_b, 1>;
216 defm MMX_PADDUSW : MMXI_binop_rm_int<0xDD, "paddusw", int_x86_mmx_paddus_w, 1>;
218 // -- Subtraction
219 defm MMX_PSUBB : MMXI_binop_rm<0xF8, "psubb", sub, v8i8>;
220 defm MMX_PSUBW : MMXI_binop_rm<0xF9, "psubw", sub, v4i16>;
221 defm MMX_PSUBD : MMXI_binop_rm<0xFA, "psubd", sub, v2i32>;
222 defm MMX_PSUBQ : MMXI_binop_rm<0xFB, "psubq", sub, v1i64>;
224 defm MMX_PSUBSB : MMXI_binop_rm_int<0xE8, "psubsb" , int_x86_mmx_psubs_b>;
225 defm MMX_PSUBSW : MMXI_binop_rm_int<0xE9, "psubsw" , int_x86_mmx_psubs_w>;
227 defm MMX_PSUBUSB : MMXI_binop_rm_int<0xD8, "psubusb", int_x86_mmx_psubus_b>;
228 defm MMX_PSUBUSW : MMXI_binop_rm_int<0xD9, "psubusw", int_x86_mmx_psubus_w>;
230 // -- Multiplication
231 defm MMX_PMULLW : MMXI_binop_rm<0xD5, "pmullw", mul, v4i16, 1>;
233 defm MMX_PMULHW : MMXI_binop_rm_int<0xE5, "pmulhw", int_x86_mmx_pmulh_w, 1>;
234 defm MMX_PMULHUW : MMXI_binop_rm_int<0xE4, "pmulhuw", int_x86_mmx_pmulhu_w, 1>;
235 defm MMX_PMULUDQ : MMXI_binop_rm_int<0xF4, "pmuludq", int_x86_mmx_pmulu_dq, 1>;
237 // -- Miscellanea
238 defm MMX_PMADDWD : MMXI_binop_rm_int<0xF5, "pmaddwd", int_x86_mmx_pmadd_wd, 1>;
240 defm MMX_PAVGB : MMXI_binop_rm_int<0xE0, "pavgb", int_x86_mmx_pavg_b, 1>;
241 defm MMX_PAVGW : MMXI_binop_rm_int<0xE3, "pavgw", int_x86_mmx_pavg_w, 1>;
243 defm MMX_PMINUB : MMXI_binop_rm_int<0xDA, "pminub", int_x86_mmx_pminu_b, 1>;
244 defm MMX_PMINSW : MMXI_binop_rm_int<0xEA, "pminsw", int_x86_mmx_pmins_w, 1>;
246 defm MMX_PMAXUB : MMXI_binop_rm_int<0xDE, "pmaxub", int_x86_mmx_pmaxu_b, 1>;
247 defm MMX_PMAXSW : MMXI_binop_rm_int<0xEE, "pmaxsw", int_x86_mmx_pmaxs_w, 1>;
249 defm MMX_PSADBW : MMXI_binop_rm_int<0xE0, "psadbw", int_x86_mmx_psad_bw, 1>;
251 // Logical Instructions
252 defm MMX_PAND : MMXI_binop_rm_v1i64<0xDB, "pand", and, 1>;
253 defm MMX_POR : MMXI_binop_rm_v1i64<0xEB, "por" , or, 1>;
254 defm MMX_PXOR : MMXI_binop_rm_v1i64<0xEF, "pxor", xor, 1>;
256 let isTwoAddress = 1 in {
257 def MMX_PANDNrr : MMXI<0xDF, MRMSrcReg,
258 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
259 "pandn\t{$src2, $dst|$dst, $src2}",
260 [(set VR64:$dst, (v1i64 (and (vnot VR64:$src1),
261 VR64:$src2)))]>;
262 def MMX_PANDNrm : MMXI<0xDF, MRMSrcMem,
263 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
264 "pandn\t{$src2, $dst|$dst, $src2}",
265 [(set VR64:$dst, (v1i64 (and (vnot VR64:$src1),
266 (load addr:$src2))))]>;
267 }
269 // Shift Instructions
270 defm MMX_PSRLW : MMXI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
271 int_x86_mmx_psrl_w, int_x86_mmx_psrli_w>;
272 defm MMX_PSRLD : MMXI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
273 int_x86_mmx_psrl_d, int_x86_mmx_psrli_d>;
274 defm MMX_PSRLQ : MMXI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
275 int_x86_mmx_psrl_q, int_x86_mmx_psrli_q>;
277 defm MMX_PSLLW : MMXI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
278 int_x86_mmx_psll_w, int_x86_mmx_pslli_w>;
279 defm MMX_PSLLD : MMXI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
280 int_x86_mmx_psll_d, int_x86_mmx_pslli_d>;
281 defm MMX_PSLLQ : MMXI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
282 int_x86_mmx_psll_q, int_x86_mmx_pslli_q>;
284 defm MMX_PSRAW : MMXI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
285 int_x86_mmx_psra_w, int_x86_mmx_psrai_w>;
286 defm MMX_PSRAD : MMXI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
287 int_x86_mmx_psra_d, int_x86_mmx_psrai_d>;
289 // Comparison Instructions
290 defm MMX_PCMPEQB : MMXI_binop_rm_int<0x74, "pcmpeqb", int_x86_mmx_pcmpeq_b>;
291 defm MMX_PCMPEQW : MMXI_binop_rm_int<0x75, "pcmpeqw", int_x86_mmx_pcmpeq_w>;
292 defm MMX_PCMPEQD : MMXI_binop_rm_int<0x76, "pcmpeqd", int_x86_mmx_pcmpeq_d>;
294 defm MMX_PCMPGTB : MMXI_binop_rm_int<0x64, "pcmpgtb", int_x86_mmx_pcmpgt_b>;
295 defm MMX_PCMPGTW : MMXI_binop_rm_int<0x65, "pcmpgtw", int_x86_mmx_pcmpgt_w>;
296 defm MMX_PCMPGTD : MMXI_binop_rm_int<0x66, "pcmpgtd", int_x86_mmx_pcmpgt_d>;
298 // Conversion Instructions
300 // -- Unpack Instructions
301 let isTwoAddress = 1 in {
302 // Unpack High Packed Data Instructions
303 def MMX_PUNPCKHBWrr : MMXI<0x68, MRMSrcReg,
304 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
305 "punpckhbw\t{$src2, $dst|$dst, $src2}",
306 [(set VR64:$dst,
307 (v8i8 (vector_shuffle VR64:$src1, VR64:$src2,
308 MMX_UNPCKH_shuffle_mask)))]>;
309 def MMX_PUNPCKHBWrm : MMXI<0x68, MRMSrcMem,
310 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
311 "punpckhbw\t{$src2, $dst|$dst, $src2}",
312 [(set VR64:$dst,
313 (v8i8 (vector_shuffle VR64:$src1,
314 (bc_v8i8 (load_mmx addr:$src2)),
315 MMX_UNPCKH_shuffle_mask)))]>;
317 def MMX_PUNPCKHWDrr : MMXI<0x69, MRMSrcReg,
318 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
319 "punpckhwd\t{$src2, $dst|$dst, $src2}",
320 [(set VR64:$dst,
321 (v4i16 (vector_shuffle VR64:$src1, VR64:$src2,
322 MMX_UNPCKH_shuffle_mask)))]>;
323 def MMX_PUNPCKHWDrm : MMXI<0x69, MRMSrcMem,
324 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
325 "punpckhwd\t{$src2, $dst|$dst, $src2}",
326 [(set VR64:$dst,
327 (v4i16 (vector_shuffle VR64:$src1,
328 (bc_v4i16 (load_mmx addr:$src2)),
329 MMX_UNPCKH_shuffle_mask)))]>;
331 def MMX_PUNPCKHDQrr : MMXI<0x6A, MRMSrcReg,
332 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
333 "punpckhdq\t{$src2, $dst|$dst, $src2}",
334 [(set VR64:$dst,
335 (v2i32 (vector_shuffle VR64:$src1, VR64:$src2,
336 MMX_UNPCKH_shuffle_mask)))]>;
337 def MMX_PUNPCKHDQrm : MMXI<0x6A, MRMSrcMem,
338 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
339 "punpckhdq\t{$src2, $dst|$dst, $src2}",
340 [(set VR64:$dst,
341 (v2i32 (vector_shuffle VR64:$src1,
342 (bc_v2i32 (load_mmx addr:$src2)),
343 MMX_UNPCKH_shuffle_mask)))]>;
345 // Unpack Low Packed Data Instructions
346 def MMX_PUNPCKLBWrr : MMXI<0x60, MRMSrcReg,
347 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
348 "punpcklbw\t{$src2, $dst|$dst, $src2}",
349 [(set VR64:$dst,
350 (v8i8 (vector_shuffle VR64:$src1, VR64:$src2,
351 MMX_UNPCKL_shuffle_mask)))]>;
352 def MMX_PUNPCKLBWrm : MMXI<0x60, MRMSrcMem,
353 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
354 "punpcklbw\t{$src2, $dst|$dst, $src2}",
355 [(set VR64:$dst,
356 (v8i8 (vector_shuffle VR64:$src1,
357 (bc_v8i8 (load_mmx addr:$src2)),
358 MMX_UNPCKL_shuffle_mask)))]>;
360 def MMX_PUNPCKLWDrr : MMXI<0x61, MRMSrcReg,
361 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
362 "punpcklwd\t{$src2, $dst|$dst, $src2}",
363 [(set VR64:$dst,
364 (v4i16 (vector_shuffle VR64:$src1, VR64:$src2,
365 MMX_UNPCKL_shuffle_mask)))]>;
366 def MMX_PUNPCKLWDrm : MMXI<0x61, MRMSrcMem,
367 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
368 "punpcklwd\t{$src2, $dst|$dst, $src2}",
369 [(set VR64:$dst,
370 (v4i16 (vector_shuffle VR64:$src1,
371 (bc_v4i16 (load_mmx addr:$src2)),
372 MMX_UNPCKL_shuffle_mask)))]>;
374 def MMX_PUNPCKLDQrr : MMXI<0x62, MRMSrcReg,
375 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
376 "punpckldq\t{$src2, $dst|$dst, $src2}",
377 [(set VR64:$dst,
378 (v2i32 (vector_shuffle VR64:$src1, VR64:$src2,
379 MMX_UNPCKL_shuffle_mask)))]>;
380 def MMX_PUNPCKLDQrm : MMXI<0x62, MRMSrcMem,
381 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
382 "punpckldq\t{$src2, $dst|$dst, $src2}",
383 [(set VR64:$dst,
384 (v2i32 (vector_shuffle VR64:$src1,
385 (bc_v2i32 (load_mmx addr:$src2)),
386 MMX_UNPCKL_shuffle_mask)))]>;
387 }
389 // -- Pack Instructions
390 defm MMX_PACKSSWB : MMXI_binop_rm_int<0x63, "packsswb", int_x86_mmx_packsswb>;
391 defm MMX_PACKSSDW : MMXI_binop_rm_int<0x6B, "packssdw", int_x86_mmx_packssdw>;
392 defm MMX_PACKUSWB : MMXI_binop_rm_int<0x67, "packuswb", int_x86_mmx_packuswb>;
394 // -- Shuffle Instructions
395 def MMX_PSHUFWri : MMXIi8<0x70, MRMSrcReg,
396 (outs VR64:$dst), (ins VR64:$src1, i8imm:$src2),
397 "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
398 [(set VR64:$dst,
399 (v4i16 (vector_shuffle
400 VR64:$src1, (undef),
401 MMX_PSHUFW_shuffle_mask:$src2)))]>;
402 def MMX_PSHUFWmi : MMXIi8<0x70, MRMSrcMem,
403 (outs VR64:$dst), (ins i64mem:$src1, i8imm:$src2),
404 "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
405 [(set VR64:$dst,
406 (v4i16 (vector_shuffle
407 (bc_v4i16 (load_mmx addr:$src1)),
408 (undef),
409 MMX_PSHUFW_shuffle_mask:$src2)))]>;
411 // -- Conversion Instructions
412 let neverHasSideEffects = 1 in {
413 def MMX_CVTPD2PIrr : MMX2I<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
414 "cvtpd2pi\t{$src, $dst|$dst, $src}", []>;
415 let mayLoad = 1 in
416 def MMX_CVTPD2PIrm : MMX2I<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
417 "cvtpd2pi\t{$src, $dst|$dst, $src}", []>;
419 def MMX_CVTPI2PDrr : MMX2I<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
420 "cvtpi2pd\t{$src, $dst|$dst, $src}", []>;
421 let mayLoad = 1 in
422 def MMX_CVTPI2PDrm : MMX2I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
423 "cvtpi2pd\t{$src, $dst|$dst, $src}", []>;
425 def MMX_CVTPI2PSrr : MMXI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
426 "cvtpi2ps\t{$src, $dst|$dst, $src}", []>;
427 let mayLoad = 1 in
428 def MMX_CVTPI2PSrm : MMXI<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
429 "cvtpi2ps\t{$src, $dst|$dst, $src}", []>;
431 def MMX_CVTPS2PIrr : MMXI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
432 "cvtps2pi\t{$src, $dst|$dst, $src}", []>;
433 let mayLoad = 1 in
434 def MMX_CVTPS2PIrm : MMXI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
435 "cvtps2pi\t{$src, $dst|$dst, $src}", []>;
437 def MMX_CVTTPD2PIrr : MMX2I<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
438 "cvttpd2pi\t{$src, $dst|$dst, $src}", []>;
439 let mayLoad = 1 in
440 def MMX_CVTTPD2PIrm : MMX2I<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
441 "cvttpd2pi\t{$src, $dst|$dst, $src}", []>;
443 def MMX_CVTTPS2PIrr : MMXI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
444 "cvttps2pi\t{$src, $dst|$dst, $src}", []>;
445 let mayLoad = 1 in
446 def MMX_CVTTPS2PIrm : MMXI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
447 "cvttps2pi\t{$src, $dst|$dst, $src}", []>;
448 } // end neverHasSideEffects
451 // Extract / Insert
452 def MMX_X86pextrw : SDNode<"X86ISD::PEXTRW", SDTypeProfile<1, 2, []>, []>;
453 def MMX_X86pinsrw : SDNode<"X86ISD::PINSRW", SDTypeProfile<1, 3, []>, []>;
455 def MMX_PEXTRWri : MMXIi8<0xC5, MRMSrcReg,
456 (outs GR32:$dst), (ins VR64:$src1, i16i8imm:$src2),
457 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
458 [(set GR32:$dst, (MMX_X86pextrw (v4i16 VR64:$src1),
459 (iPTR imm:$src2)))]>;
460 let isTwoAddress = 1 in {
461 def MMX_PINSRWrri : MMXIi8<0xC4, MRMSrcReg,
462 (outs VR64:$dst), (ins VR64:$src1, GR32:$src2, i16i8imm:$src3),
463 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
464 [(set VR64:$dst, (v4i16 (MMX_X86pinsrw (v4i16 VR64:$src1),
465 GR32:$src2, (iPTR imm:$src3))))]>;
466 def MMX_PINSRWrmi : MMXIi8<0xC4, MRMSrcMem,
467 (outs VR64:$dst), (ins VR64:$src1, i16mem:$src2, i16i8imm:$src3),
468 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
469 [(set VR64:$dst,
470 (v4i16 (MMX_X86pinsrw (v4i16 VR64:$src1),
471 (i32 (anyext (loadi16 addr:$src2))),
472 (iPTR imm:$src3))))]>;
473 }
475 // Mask creation
476 def MMX_PMOVMSKBrr : MMXI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR64:$src),
477 "pmovmskb\t{$src, $dst|$dst, $src}",
478 [(set GR32:$dst, (int_x86_mmx_pmovmskb VR64:$src))]>;
480 // Misc.
481 let Uses = [EDI] in
482 def MMX_MASKMOVQ : MMXI<0xF7, MRMDestMem, (outs), (ins VR64:$src, VR64:$mask),
483 "maskmovq\t{$mask, $src|$src, $mask}",
484 [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, EDI)]>;
486 //===----------------------------------------------------------------------===//
487 // Alias Instructions
488 //===----------------------------------------------------------------------===//
490 // Alias instructions that map zero vector to pxor.
491 let isReMaterializable = 1 in {
492 def MMX_V_SET0 : MMXI<0xEF, MRMInitReg, (outs VR64:$dst), (ins),
493 "pxor\t$dst, $dst",
494 [(set VR64:$dst, (v2i32 immAllZerosV))]>;
495 def MMX_V_SETALLONES : MMXI<0x76, MRMInitReg, (outs VR64:$dst), (ins),
496 "pcmpeqd\t$dst, $dst",
497 [(set VR64:$dst, (v2i32 immAllOnesV))]>;
498 }
500 let Predicates = [HasMMX] in {
501 def : Pat<(v1i64 immAllZerosV), (MMX_V_SET0)>;
502 def : Pat<(v4i16 immAllZerosV), (MMX_V_SET0)>;
503 def : Pat<(v8i8 immAllZerosV), (MMX_V_SET0)>;
504 }
506 //===----------------------------------------------------------------------===//
507 // Non-Instruction Patterns
508 //===----------------------------------------------------------------------===//
510 // Store 64-bit integer vector values.
511 def : Pat<(store (v8i8 VR64:$src), addr:$dst),
512 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
513 def : Pat<(store (v4i16 VR64:$src), addr:$dst),
514 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
515 def : Pat<(store (v2i32 VR64:$src), addr:$dst),
516 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
517 def : Pat<(store (v1i64 VR64:$src), addr:$dst),
518 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
520 // Bit convert.
521 def : Pat<(v8i8 (bitconvert (v1i64 VR64:$src))), (v8i8 VR64:$src)>;
522 def : Pat<(v8i8 (bitconvert (v2i32 VR64:$src))), (v8i8 VR64:$src)>;
523 def : Pat<(v8i8 (bitconvert (v4i16 VR64:$src))), (v8i8 VR64:$src)>;
524 def : Pat<(v4i16 (bitconvert (v1i64 VR64:$src))), (v4i16 VR64:$src)>;
525 def : Pat<(v4i16 (bitconvert (v2i32 VR64:$src))), (v4i16 VR64:$src)>;
526 def : Pat<(v4i16 (bitconvert (v8i8 VR64:$src))), (v4i16 VR64:$src)>;
527 def : Pat<(v2i32 (bitconvert (v1i64 VR64:$src))), (v2i32 VR64:$src)>;
528 def : Pat<(v2i32 (bitconvert (v4i16 VR64:$src))), (v2i32 VR64:$src)>;
529 def : Pat<(v2i32 (bitconvert (v8i8 VR64:$src))), (v2i32 VR64:$src)>;
530 def : Pat<(v1i64 (bitconvert (v2i32 VR64:$src))), (v1i64 VR64:$src)>;
531 def : Pat<(v1i64 (bitconvert (v4i16 VR64:$src))), (v1i64 VR64:$src)>;
532 def : Pat<(v1i64 (bitconvert (v8i8 VR64:$src))), (v1i64 VR64:$src)>;
534 // 64-bit bit convert.
535 def : Pat<(v1i64 (bitconvert (i64 GR64:$src))),
536 (MMX_MOVD64to64rr GR64:$src)>;
537 def : Pat<(v2i32 (bitconvert (i64 GR64:$src))),
538 (MMX_MOVD64to64rr GR64:$src)>;
539 def : Pat<(v4i16 (bitconvert (i64 GR64:$src))),
540 (MMX_MOVD64to64rr GR64:$src)>;
541 def : Pat<(v8i8 (bitconvert (i64 GR64:$src))),
542 (MMX_MOVD64to64rr GR64:$src)>;
544 // Move scalar to XMM zero-extended
545 // movd to XMM register zero-extends
546 let AddedComplexity = 15 in {
547 def : Pat<(v8i8 (vector_shuffle immAllZerosV_bc,
548 (bc_v8i8 (v2i32 (scalar_to_vector GR32:$src))),
549 MMX_MOVL_shuffle_mask)),
550 (MMX_MOVZDI2PDIrr GR32:$src)>;
551 def : Pat<(v4i16 (vector_shuffle immAllZerosV_bc,
552 (bc_v4i16 (v2i32 (scalar_to_vector GR32:$src))),
553 MMX_MOVL_shuffle_mask)),
554 (MMX_MOVZDI2PDIrr GR32:$src)>;
555 }
557 // Scalar to v4i16 / v8i8. The source may be a GR32, but only the lower
558 // 8 or 16-bits matter.
559 def : Pat<(bc_v8i8 (v2i32 (scalar_to_vector GR32:$src))),
560 (MMX_MOVD64rr GR32:$src)>;
561 def : Pat<(bc_v4i16 (v2i32 (scalar_to_vector GR32:$src))),
562 (MMX_MOVD64rr GR32:$src)>;
564 // Patterns to perform canonical versions of vector shuffling.
565 let AddedComplexity = 10 in {
566 def : Pat<(v8i8 (vector_shuffle VR64:$src, (undef),
567 MMX_UNPCKL_v_undef_shuffle_mask)),
568 (MMX_PUNPCKLBWrr VR64:$src, VR64:$src)>;
569 def : Pat<(v4i16 (vector_shuffle VR64:$src, (undef),
570 MMX_UNPCKL_v_undef_shuffle_mask)),
571 (MMX_PUNPCKLWDrr VR64:$src, VR64:$src)>;
572 def : Pat<(v2i32 (vector_shuffle VR64:$src, (undef),
573 MMX_UNPCKL_v_undef_shuffle_mask)),
574 (MMX_PUNPCKLDQrr VR64:$src, VR64:$src)>;
575 }
577 let AddedComplexity = 10 in {
578 def : Pat<(v8i8 (vector_shuffle VR64:$src, (undef),
579 MMX_UNPCKH_v_undef_shuffle_mask)),
580 (MMX_PUNPCKHBWrr VR64:$src, VR64:$src)>;
581 def : Pat<(v4i16 (vector_shuffle VR64:$src, (undef),
582 MMX_UNPCKH_v_undef_shuffle_mask)),
583 (MMX_PUNPCKHWDrr VR64:$src, VR64:$src)>;
584 def : Pat<(v2i32 (vector_shuffle VR64:$src, (undef),
585 MMX_UNPCKH_v_undef_shuffle_mask)),
586 (MMX_PUNPCKHDQrr VR64:$src, VR64:$src)>;
587 }
589 // Patterns to perform vector shuffling with a zeroed out vector.
590 let AddedComplexity = 20 in {
591 def : Pat<(bc_v2i32 (vector_shuffle immAllZerosV,
592 (v2i32 (scalar_to_vector (load_mmx addr:$src))),
593 MMX_UNPCKL_shuffle_mask)),
594 (MMX_PUNPCKLDQrm VR64:$src, VR64:$src)>;
595 }
597 // Some special case PANDN patterns.
598 // FIXME: Get rid of these.
599 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v2i32 immAllOnesV))),
600 VR64:$src2)),
601 (MMX_PANDNrr VR64:$src1, VR64:$src2)>;
602 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v4i16 immAllOnesV_bc))),
603 VR64:$src2)),
604 (MMX_PANDNrr VR64:$src1, VR64:$src2)>;
605 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v8i8 immAllOnesV_bc))),
606 VR64:$src2)),
607 (MMX_PANDNrr VR64:$src1, VR64:$src2)>;
609 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v2i32 immAllOnesV))),
610 (load addr:$src2))),
611 (MMX_PANDNrm VR64:$src1, addr:$src2)>;
612 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v4i16 immAllOnesV_bc))),
613 (load addr:$src2))),
614 (MMX_PANDNrm VR64:$src1, addr:$src2)>;
615 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v8i8 immAllOnesV_bc))),
616 (load addr:$src2))),
617 (MMX_PANDNrm VR64:$src1, addr:$src2)>;