1 //===-- XCoreISelLowering.h - XCore DAG Lowering Interface ------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that XCore uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
15 #ifndef XCOREISELLOWERING_H
16 #define XCOREISELLOWERING_H
18 #include "llvm/CodeGen/SelectionDAG.h"
19 #include "llvm/Target/TargetLowering.h"
20 #include "XCore.h"
22 namespace llvm {
24 // Forward delcarations
25 class XCoreSubtarget;
26 class XCoreTargetMachine;
28 namespace XCoreISD {
29 enum NodeType {
30 // Start the numbering where the builtin ops and target ops leave off.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
33 // Branch and link (call)
34 BL,
36 // pc relative address
37 PCRelativeWrapper,
39 // dp relative address
40 DPRelativeWrapper,
42 // cp relative address
43 CPRelativeWrapper,
45 // Store word to stack
46 STWSP,
48 // Corresponds to retsp instruction
49 RETSP,
51 // Corresponds to LADD instruction
52 LADD,
54 // Corresponds to LSUB instruction
55 LSUB,
57 // Jumptable branch.
58 BR_JT,
60 // Jumptable branch using long branches for each entry.
61 BR_JT32
62 };
63 }
65 //===--------------------------------------------------------------------===//
66 // TargetLowering Implementation
67 //===--------------------------------------------------------------------===//
68 class XCoreTargetLowering : public TargetLowering
69 {
70 public:
72 explicit XCoreTargetLowering(XCoreTargetMachine &TM);
74 /// LowerOperation - Provide custom lowering hooks for some operations.
75 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
77 /// ReplaceNodeResults - Replace the results of node with an illegal result
78 /// type with new values built out of custom code.
79 ///
80 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
81 SelectionDAG &DAG);
83 /// getTargetNodeName - This method returns the name of a target specific
84 // DAG node.
85 virtual const char *getTargetNodeName(unsigned Opcode) const;
87 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
88 MachineBasicBlock *MBB,
89 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const;
91 virtual bool isLegalAddressingMode(const AddrMode &AM,
92 const Type *Ty) const;
94 /// getFunctionAlignment - Return the Log2 alignment of this function.
95 virtual unsigned getFunctionAlignment(const Function *F) const;
97 private:
98 const XCoreTargetMachine &TM;
99 const XCoreSubtarget &Subtarget;
101 // Lower Operand helpers
102 SDValue LowerCCCArguments(SDValue Chain,
103 CallingConv::ID CallConv,
104 bool isVarArg,
105 const SmallVectorImpl<ISD::InputArg> &Ins,
106 DebugLoc dl, SelectionDAG &DAG,
107 SmallVectorImpl<SDValue> &InVals);
108 SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
109 CallingConv::ID CallConv, bool isVarArg,
110 bool isTailCall,
111 const SmallVectorImpl<ISD::OutputArg> &Outs,
112 const SmallVectorImpl<ISD::InputArg> &Ins,
113 DebugLoc dl, SelectionDAG &DAG,
114 SmallVectorImpl<SDValue> &InVals);
115 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
116 CallingConv::ID CallConv, bool isVarArg,
117 const SmallVectorImpl<ISD::InputArg> &Ins,
118 DebugLoc dl, SelectionDAG &DAG,
119 SmallVectorImpl<SDValue> &InVals);
120 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG);
121 SDValue getGlobalAddressWrapper(SDValue GA, GlobalValue *GV,
122 SelectionDAG &DAG);
124 // Lower Operand specifics
125 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG);
126 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG);
127 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG);
128 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG);
129 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG);
130 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG);
131 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG);
132 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG);
133 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG);
134 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG);
135 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG);
137 // Inline asm support
138 std::vector<unsigned>
139 getRegClassForInlineAsmConstraint(const std::string &Constraint,
140 EVT VT) const;
142 // Expand specifics
143 SDValue ExpandADDSUB(SDNode *Op, SelectionDAG &DAG);
145 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
147 virtual SDValue
148 LowerFormalArguments(SDValue Chain,
149 CallingConv::ID CallConv,
150 bool isVarArg,
151 const SmallVectorImpl<ISD::InputArg> &Ins,
152 DebugLoc dl, SelectionDAG &DAG,
153 SmallVectorImpl<SDValue> &InVals);
155 virtual SDValue
156 LowerCall(SDValue Chain, SDValue Callee,
157 CallingConv::ID CallConv, bool isVarArg,
158 bool &isTailCall,
159 const SmallVectorImpl<ISD::OutputArg> &Outs,
160 const SmallVectorImpl<ISD::InputArg> &Ins,
161 DebugLoc dl, SelectionDAG &DAG,
162 SmallVectorImpl<SDValue> &InVals);
164 virtual SDValue
165 LowerReturn(SDValue Chain,
166 CallingConv::ID CallConv, bool isVarArg,
167 const SmallVectorImpl<ISD::OutputArg> &Outs,
168 DebugLoc dl, SelectionDAG &DAG);
170 virtual bool
171 CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
172 const SmallVectorImpl<EVT> &OutTys,
173 const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
174 SelectionDAG &DAG);
175 };
176 }
178 #endif // XCOREISELLOWERING_H