1 //===-- XCoreInstrInfo.td - Target Description for XCore ---*- tablegen -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file describes the XCore instructions in TableGen format.
11 //
12 //===----------------------------------------------------------------------===//
14 // Uses of CP, DP are not currently reflected in the patterns, since
15 // having a physical register as an operand prevents loop hoisting and
16 // since the value of these registers never changes during the life of the
17 // function.
19 //===----------------------------------------------------------------------===//
20 // Instruction format superclass.
21 //===----------------------------------------------------------------------===//
23 include "XCoreInstrFormats.td"
25 //===----------------------------------------------------------------------===//
26 // XCore specific DAG Nodes.
27 //
29 // Call
30 def SDT_XCoreBranchLink : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
31 def XCoreBranchLink : SDNode<"XCoreISD::BL",SDT_XCoreBranchLink,
32 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
33 SDNPVariadic]>;
35 def XCoreRetsp : SDNode<"XCoreISD::RETSP", SDTBrind,
36 [SDNPHasChain, SDNPOptInGlue, SDNPMayLoad]>;
38 def SDT_XCoreBR_JT : SDTypeProfile<0, 2,
39 [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
41 def XCoreBR_JT : SDNode<"XCoreISD::BR_JT", SDT_XCoreBR_JT,
42 [SDNPHasChain]>;
44 def XCoreBR_JT32 : SDNode<"XCoreISD::BR_JT32", SDT_XCoreBR_JT,
45 [SDNPHasChain]>;
47 def SDT_XCoreAddress : SDTypeProfile<1, 1,
48 [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
50 def pcrelwrapper : SDNode<"XCoreISD::PCRelativeWrapper", SDT_XCoreAddress,
51 []>;
53 def dprelwrapper : SDNode<"XCoreISD::DPRelativeWrapper", SDT_XCoreAddress,
54 []>;
56 def cprelwrapper : SDNode<"XCoreISD::CPRelativeWrapper", SDT_XCoreAddress,
57 []>;
59 def SDT_XCoreStwsp : SDTypeProfile<0, 2, [SDTCisInt<1>]>;
60 def XCoreStwsp : SDNode<"XCoreISD::STWSP", SDT_XCoreStwsp,
61 [SDNPHasChain, SDNPMayStore]>;
63 // These are target-independent nodes, but have target-specific formats.
64 def SDT_XCoreCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
65 def SDT_XCoreCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
66 SDTCisVT<1, i32> ]>;
68 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_XCoreCallSeqStart,
69 [SDNPHasChain, SDNPOutGlue]>;
70 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_XCoreCallSeqEnd,
71 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
73 //===----------------------------------------------------------------------===//
74 // Instruction Pattern Stuff
75 //===----------------------------------------------------------------------===//
77 def div4_xform : SDNodeXForm<imm, [{
78 // Transformation function: imm/4
79 assert(N->getZExtValue() % 4 == 0);
80 return getI32Imm(N->getZExtValue()/4);
81 }]>;
83 def msksize_xform : SDNodeXForm<imm, [{
84 // Transformation function: get the size of a mask
85 assert(isMask_32(N->getZExtValue()));
86 // look for the first non-zero bit
87 return getI32Imm(32 - CountLeadingZeros_32(N->getZExtValue()));
88 }]>;
90 def neg_xform : SDNodeXForm<imm, [{
91 // Transformation function: -imm
92 uint32_t value = N->getZExtValue();
93 return getI32Imm(-value);
94 }]>;
96 def bpwsub_xform : SDNodeXForm<imm, [{
97 // Transformation function: 32-imm
98 uint32_t value = N->getZExtValue();
99 return getI32Imm(32-value);
100 }]>;
102 def div4neg_xform : SDNodeXForm<imm, [{
103 // Transformation function: -imm/4
104 uint32_t value = N->getZExtValue();
105 assert(-value % 4 == 0);
106 return getI32Imm(-value/4);
107 }]>;
109 def immUs4Neg : PatLeaf<(imm), [{
110 uint32_t value = (uint32_t)N->getZExtValue();
111 return (-value)%4 == 0 && (-value)/4 <= 11;
112 }]>;
114 def immUs4 : PatLeaf<(imm), [{
115 uint32_t value = (uint32_t)N->getZExtValue();
116 return value%4 == 0 && value/4 <= 11;
117 }]>;
119 def immUsNeg : PatLeaf<(imm), [{
120 return -((uint32_t)N->getZExtValue()) <= 11;
121 }]>;
123 def immUs : PatLeaf<(imm), [{
124 return (uint32_t)N->getZExtValue() <= 11;
125 }]>;
127 def immU6 : PatLeaf<(imm), [{
128 return (uint32_t)N->getZExtValue() < (1 << 6);
129 }]>;
131 def immU10 : PatLeaf<(imm), [{
132 return (uint32_t)N->getZExtValue() < (1 << 10);
133 }]>;
135 def immU16 : PatLeaf<(imm), [{
136 return (uint32_t)N->getZExtValue() < (1 << 16);
137 }]>;
139 def immU20 : PatLeaf<(imm), [{
140 return (uint32_t)N->getZExtValue() < (1 << 20);
141 }]>;
143 def immMskBitp : PatLeaf<(imm), [{ return immMskBitp(N); }]>;
145 def immBitp : PatLeaf<(imm), [{
146 uint32_t value = (uint32_t)N->getZExtValue();
147 return (value >= 1 && value <= 8)
148 || value == 16
149 || value == 24
150 || value == 32;
151 }]>;
153 def immBpwSubBitp : PatLeaf<(imm), [{
154 uint32_t value = (uint32_t)N->getZExtValue();
155 return (value >= 24 && value <= 31)
156 || value == 16
157 || value == 8
158 || value == 0;
159 }]>;
161 def lda16f : PatFrag<(ops node:$addr, node:$offset),
162 (add node:$addr, (shl node:$offset, 1))>;
163 def lda16b : PatFrag<(ops node:$addr, node:$offset),
164 (sub node:$addr, (shl node:$offset, 1))>;
165 def ldawf : PatFrag<(ops node:$addr, node:$offset),
166 (add node:$addr, (shl node:$offset, 2))>;
167 def ldawb : PatFrag<(ops node:$addr, node:$offset),
168 (sub node:$addr, (shl node:$offset, 2))>;
170 // Instruction operand types
171 def calltarget : Operand<i32>;
172 def brtarget : Operand<OtherVT>;
173 def pclabel : Operand<i32>;
175 // Addressing modes
176 def ADDRspii : ComplexPattern<i32, 2, "SelectADDRspii", [add, frameindex], []>;
177 def ADDRdpii : ComplexPattern<i32, 2, "SelectADDRdpii", [add, dprelwrapper],
178 []>;
179 def ADDRcpii : ComplexPattern<i32, 2, "SelectADDRcpii", [add, cprelwrapper],
180 []>;
182 // Address operands
183 def MEMii : Operand<i32> {
184 let PrintMethod = "printMemOperand";
185 let DecoderMethod = "DecodeMEMiiOperand";
186 let MIOperandInfo = (ops i32imm, i32imm);
187 }
189 // Jump tables.
190 def InlineJT : Operand<i32> {
191 let PrintMethod = "printInlineJT";
192 }
194 def InlineJT32 : Operand<i32> {
195 let PrintMethod = "printInlineJT32";
196 }
198 //===----------------------------------------------------------------------===//
199 // Instruction Class Templates
200 //===----------------------------------------------------------------------===//
202 // Three operand short
204 multiclass F3R_2RUS<bits<5> opc1, bits<5> opc2, string OpcStr, SDNode OpNode> {
205 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
206 !strconcat(OpcStr, " $dst, $b, $c"),
207 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
208 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
209 !strconcat(OpcStr, " $dst, $b, $c"),
210 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;
211 }
213 multiclass F3R_2RUS_np<bits<5> opc1, bits<5> opc2, string OpcStr> {
214 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
215 !strconcat(OpcStr, " $dst, $b, $c"), []>;
216 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
217 !strconcat(OpcStr, " $dst, $b, $c"), []>;
218 }
220 multiclass F3R_2RBITP<bits<5> opc1, bits<5> opc2, string OpcStr,
221 SDNode OpNode> {
222 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
223 !strconcat(OpcStr, " $dst, $b, $c"),
224 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
225 def _2rus : _F2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
226 !strconcat(OpcStr, " $dst, $b, $c"),
227 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
228 }
230 class F3R<bits<5> opc, string OpcStr, SDNode OpNode> :
231 _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
232 !strconcat(OpcStr, " $dst, $b, $c"),
233 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
235 class F3R_np<bits<5> opc, string OpcStr> :
236 _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
237 !strconcat(OpcStr, " $dst, $b, $c"), []>;
238 // Three operand long
240 /// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot.
241 multiclass FL3R_L2RUS<bits<9> opc1, bits<9> opc2, string OpcStr,
242 SDNode OpNode> {
243 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
244 !strconcat(OpcStr, " $dst, $b, $c"),
245 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
246 def _l2rus : _FL2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
247 !strconcat(OpcStr, " $dst, $b, $c"),
248 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;
249 }
251 /// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot.
252 multiclass FL3R_L2RBITP<bits<9> opc1, bits<9> opc2, string OpcStr,
253 SDNode OpNode> {
254 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
255 !strconcat(OpcStr, " $dst, $b, $c"),
256 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
257 def _l2rus : _FL2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
258 !strconcat(OpcStr, " $dst, $b, $c"),
259 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
260 }
262 class FL3R<bits<9> opc, string OpcStr, SDNode OpNode> :
263 _FL3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
264 !strconcat(OpcStr, " $dst, $b, $c"),
265 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
267 // Register - U6
268 // Operand register - U6
269 multiclass FRU6_LRU6_branch<bits<6> opc, string OpcStr> {
270 def _ru6: _FRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b),
271 !strconcat(OpcStr, " $a, $b"), []>;
272 def _lru6: _FLRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b),
273 !strconcat(OpcStr, " $a, $b"), []>;
274 }
276 multiclass FRU6_LRU6_backwards_branch<bits<6> opc, string OpcStr> {
277 def _ru6: _FRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b),
278 !strconcat(OpcStr, " $a, -$b"), []>;
279 def _lru6: _FLRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b),
280 !strconcat(OpcStr, " $a, -$b"), []>;
281 }
283 multiclass FRU6_LRU6_cp<bits<6> opc, string OpcStr> {
284 def _ru6: _FRU6<opc, (outs GRRegs:$a), (ins i32imm:$b),
285 !strconcat(OpcStr, " $a, cp[$b]"), []>;
286 def _lru6: _FLRU6<opc, (outs GRRegs:$a), (ins i32imm:$b),
287 !strconcat(OpcStr, " $a, cp[$b]"), []>;
288 }
290 // U6
291 multiclass FU6_LU6<bits<10> opc, string OpcStr, SDNode OpNode> {
292 def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"),
293 [(OpNode immU6:$a)]>;
294 def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"),
295 [(OpNode immU16:$a)]>;
296 }
298 multiclass FU6_LU6_int<bits<10> opc, string OpcStr, Intrinsic Int> {
299 def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"),
300 [(Int immU6:$a)]>;
301 def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"),
302 [(Int immU16:$a)]>;
303 }
305 multiclass FU6_LU6_np<bits<10> opc, string OpcStr> {
306 def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), []>;
307 def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), []>;
308 }
310 // Two operand short
312 class F2R_np<bits<6> opc, string OpcStr> :
313 _F2R<opc, (outs GRRegs:$dst), (ins GRRegs:$b),
314 !strconcat(OpcStr, " $dst, $b"), []>;
316 // Two operand long
318 //===----------------------------------------------------------------------===//
319 // Pseudo Instructions
320 //===----------------------------------------------------------------------===//
322 let Defs = [SP], Uses = [SP] in {
323 def ADJCALLSTACKDOWN : PseudoInstXCore<(outs), (ins i32imm:$amt),
324 "# ADJCALLSTACKDOWN $amt",
325 [(callseq_start timm:$amt)]>;
326 def ADJCALLSTACKUP : PseudoInstXCore<(outs), (ins i32imm:$amt1, i32imm:$amt2),
327 "# ADJCALLSTACKUP $amt1",
328 [(callseq_end timm:$amt1, timm:$amt2)]>;
329 }
331 def LDWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr),
332 "# LDWFI $dst, $addr",
333 [(set GRRegs:$dst, (load ADDRspii:$addr))]>;
335 def LDAWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr),
336 "# LDAWFI $dst, $addr",
337 [(set GRRegs:$dst, ADDRspii:$addr)]>;
339 def STWFI : PseudoInstXCore<(outs), (ins GRRegs:$src, MEMii:$addr),
340 "# STWFI $src, $addr",
341 [(store GRRegs:$src, ADDRspii:$addr)]>;
343 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
344 // instruction selection into a branch sequence.
345 let usesCustomInserter = 1 in {
346 def SELECT_CC : PseudoInstXCore<(outs GRRegs:$dst),
347 (ins GRRegs:$cond, GRRegs:$T, GRRegs:$F),
348 "# SELECT_CC PSEUDO!",
349 [(set GRRegs:$dst,
350 (select GRRegs:$cond, GRRegs:$T, GRRegs:$F))]>;
351 }
353 //===----------------------------------------------------------------------===//
354 // Instructions
355 //===----------------------------------------------------------------------===//
357 // Three operand short
358 defm ADD : F3R_2RUS<0b00010, 0b10010, "add", add>;
359 defm SUB : F3R_2RUS<0b00011, 0b10011, "sub", sub>;
360 let neverHasSideEffects = 1 in {
361 defm EQ : F3R_2RUS_np<0b00110, 0b10110, "eq">;
362 def LSS_3r : F3R_np<0b11000, "lss">;
363 def LSU_3r : F3R_np<0b11001, "lsu">;
364 }
365 def AND_3r : F3R<0b00111, "and", and>;
366 def OR_3r : F3R<0b01000, "or", or>;
368 let mayLoad=1 in {
369 def LDW_3r : _F3R<0b01001, (outs GRRegs:$dst),
370 (ins GRRegs:$addr, GRRegs:$offset),
371 "ldw $dst, $addr[$offset]", []>;
373 def LDW_2rus : _F2RUS<0b00001, (outs GRRegs:$dst),
374 (ins GRRegs:$addr, i32imm:$offset),
375 "ldw $dst, $addr[$offset]", []>;
377 def LD16S_3r : _F3R<0b10000, (outs GRRegs:$dst),
378 (ins GRRegs:$addr, GRRegs:$offset),
379 "ld16s $dst, $addr[$offset]", []>;
381 def LD8U_3r : _F3R<0b10001, (outs GRRegs:$dst),
382 (ins GRRegs:$addr, GRRegs:$offset),
383 "ld8u $dst, $addr[$offset]", []>;
384 }
386 let mayStore=1 in {
387 def STW_l3r : _FL3R<0b000001100, (outs),
388 (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
389 "stw $val, $addr[$offset]", []>;
391 def STW_2rus : _F2RUS<0b0000, (outs),
392 (ins GRRegs:$val, GRRegs:$addr, i32imm:$offset),
393 "stw $val, $addr[$offset]", []>;
394 }
396 defm SHL : F3R_2RBITP<0b00100, 0b10100, "shl", shl>;
397 defm SHR : F3R_2RBITP<0b00101, 0b10101, "shr", srl>;
398 // TODO tsetr
400 // Three operand long
401 def LDAWF_l3r : _FL3R<0b000111100, (outs GRRegs:$dst),
402 (ins GRRegs:$addr, GRRegs:$offset),
403 "ldaw $dst, $addr[$offset]",
404 [(set GRRegs:$dst,
405 (ldawf GRRegs:$addr, GRRegs:$offset))]>;
407 let neverHasSideEffects = 1 in
408 def LDAWF_l2rus : _FL2RUS<0b100111100, (outs GRRegs:$dst),
409 (ins GRRegs:$addr, i32imm:$offset),
410 "ldaw $dst, $addr[$offset]", []>;
412 def LDAWB_l3r : _FL3R<0b001001100, (outs GRRegs:$dst),
413 (ins GRRegs:$addr, GRRegs:$offset),
414 "ldaw $dst, $addr[-$offset]",
415 [(set GRRegs:$dst,
416 (ldawb GRRegs:$addr, GRRegs:$offset))]>;
418 let neverHasSideEffects = 1 in
419 def LDAWB_l2rus : _FL2RUS<0b101001100, (outs GRRegs:$dst),
420 (ins GRRegs:$addr, i32imm:$offset),
421 "ldaw $dst, $addr[-$offset]", []>;
423 def LDA16F_l3r : _FL3R<0b001011100, (outs GRRegs:$dst),
424 (ins GRRegs:$addr, GRRegs:$offset),
425 "lda16 $dst, $addr[$offset]",
426 [(set GRRegs:$dst,
427 (lda16f GRRegs:$addr, GRRegs:$offset))]>;
429 def LDA16B_l3r : _FL3R<0b001101100, (outs GRRegs:$dst),
430 (ins GRRegs:$addr, GRRegs:$offset),
431 "lda16 $dst, $addr[-$offset]",
432 [(set GRRegs:$dst,
433 (lda16b GRRegs:$addr, GRRegs:$offset))]>;
435 def MUL_l3r : FL3R<0b001111100, "mul", mul>;
436 // Instructions which may trap are marked as side effecting.
437 let hasSideEffects = 1 in {
438 def DIVS_l3r : FL3R<0b010001100, "divs", sdiv>;
439 def DIVU_l3r : FL3R<0b010011100, "divu", udiv>;
440 def REMS_l3r : FL3R<0b110001100, "rems", srem>;
441 def REMU_l3r : FL3R<0b110011100, "remu", urem>;
442 }
443 def XOR_l3r : FL3R<0b000011100, "xor", xor>;
444 defm ASHR : FL3R_L2RBITP<0b000101100, 0b100101100, "ashr", sra>;
446 let Constraints = "$src1 = $dst" in
447 def CRC_l3r : _FL3RSrcDst<0b101011100, (outs GRRegs:$dst),
448 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
449 "crc32 $dst, $src2, $src3",
450 [(set GRRegs:$dst,
451 (int_xcore_crc32 GRRegs:$src1, GRRegs:$src2,
452 GRRegs:$src3))]>;
454 let mayStore=1 in {
455 def ST16_l3r : _FL3R<0b100001100, (outs),
456 (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
457 "st16 $val, $addr[$offset]", []>;
459 def ST8_l3r : _FL3R<0b100011100, (outs),
460 (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
461 "st8 $val, $addr[$offset]", []>;
462 }
464 def INPW_l2rus : _FL2RUSBitp<0b100101110, (outs GRRegs:$a),
465 (ins GRRegs:$b, i32imm:$c), "inpw $a, res[$b], $c",
466 []>;
468 def OUTPW_l2rus : _FL2RUSBitp<0b100101101, (outs),
469 (ins GRRegs:$a, GRRegs:$b, i32imm:$c),
470 "outpw res[$b], $a, $c", []>;
472 // Four operand long
473 let Constraints = "$e = $a,$f = $b" in {
474 def MACCU_l4r : _FL4RSrcDstSrcDst<
475 0b000001, (outs GRRegs:$a, GRRegs:$b),
476 (ins GRRegs:$e, GRRegs:$f, GRRegs:$c, GRRegs:$d), "maccu $a, $b, $c, $d", []>;
478 def MACCS_l4r : _FL4RSrcDstSrcDst<
479 0b000010, (outs GRRegs:$a, GRRegs:$b),
480 (ins GRRegs:$e, GRRegs:$f, GRRegs:$c, GRRegs:$d), "maccs $a, $b, $c, $d", []>;
481 }
483 let Constraints = "$e = $b" in
484 def CRC8_l4r : _FL4RSrcDst<0b000000, (outs GRRegs:$a, GRRegs:$b),
485 (ins GRRegs:$e, GRRegs:$c, GRRegs:$d),
486 "crc8 $b, $a, $c, $d", []>;
488 // Five operand long
490 def LADD_l5r : _FL5R<0b000001, (outs GRRegs:$dst1, GRRegs:$dst2),
491 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
492 "ladd $dst2, $dst1, $src1, $src2, $src3",
493 []>;
495 def LSUB_l5r : _FL5R<0b000010, (outs GRRegs:$dst1, GRRegs:$dst2),
496 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
497 "lsub $dst2, $dst1, $src1, $src2, $src3", []>;
499 def LDIVU_l5r : _FL5R<0b000000, (outs GRRegs:$dst1, GRRegs:$dst2),
500 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
501 "ldivu $dst1, $dst2, $src3, $src1, $src2", []>;
503 // Six operand long
505 def LMUL_l6r : _FL6R<
506 0b00000, (outs GRRegs:$dst1, GRRegs:$dst2),
507 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, GRRegs:$src4),
508 "lmul $dst1, $dst2, $src1, $src2, $src3, $src4", []>;
510 // Register - U6
512 //let Uses = [DP] in ...
513 let neverHasSideEffects = 1, isReMaterializable = 1 in
514 def LDAWDP_ru6: _FRU6<0b011000, (outs GRRegs:$a), (ins MEMii:$b),
515 "ldaw $a, dp[$b]", []>;
517 let isReMaterializable = 1 in
518 def LDAWDP_lru6: _FLRU6<0b011000, (outs GRRegs:$a), (ins MEMii:$b),
519 "ldaw $a, dp[$b]",
520 [(set GRRegs:$a, ADDRdpii:$b)]>;
522 let mayLoad=1 in
523 def LDWDP_ru6: _FRU6<0b010110, (outs GRRegs:$a), (ins MEMii:$b),
524 "ldw $a, dp[$b]", []>;
526 def LDWDP_lru6: _FLRU6<0b010110, (outs GRRegs:$a), (ins MEMii:$b),
527 "ldw $a, dp[$b]",
528 [(set GRRegs:$a, (load ADDRdpii:$b))]>;
530 let mayStore=1 in
531 def STWDP_ru6 : _FRU6<0b010100, (outs), (ins GRRegs:$a, MEMii:$b),
532 "stw $a, dp[$b]", []>;
534 def STWDP_lru6 : _FLRU6<0b010100, (outs), (ins GRRegs:$a, MEMii:$b),
535 "stw $a, dp[$b]",
536 [(store GRRegs:$a, ADDRdpii:$b)]>;
538 //let Uses = [CP] in ..
539 let mayLoad = 1, isReMaterializable = 1, neverHasSideEffects = 1 in
540 defm LDWCP : FRU6_LRU6_cp<0b011011, "ldw">;
542 let Uses = [SP] in {
543 let mayStore=1 in {
544 def STWSP_ru6 : _FRU6<0b010101, (outs), (ins GRRegs:$a, i32imm:$b),
545 "stw $a, sp[$b]",
546 [(XCoreStwsp GRRegs:$a, immU6:$b)]>;
548 def STWSP_lru6 : _FLRU6<0b010101, (outs), (ins GRRegs:$a, i32imm:$b),
549 "stw $a, sp[$b]",
550 [(XCoreStwsp GRRegs:$a, immU16:$b)]>;
551 }
553 let mayLoad=1 in {
554 def LDWSP_ru6 : _FRU6<0b010111, (outs GRRegs:$a), (ins i32imm:$b),
555 "ldw $a, sp[$b]", []>;
557 def LDWSP_lru6 : _FLRU6<0b010111, (outs GRRegs:$a), (ins i32imm:$b),
558 "ldw $a, sp[$b]", []>;
559 }
561 let neverHasSideEffects = 1 in {
562 def LDAWSP_ru6 : _FRU6<0b011001, (outs GRRegs:$a), (ins i32imm:$b),
563 "ldaw $a, sp[$b]", []>;
565 def LDAWSP_lru6 : _FLRU6<0b011001, (outs GRRegs:$a), (ins i32imm:$b),
566 "ldaw $a, sp[$b]", []>;
568 let isCodeGenOnly = 1 in
569 def LDAWSP_ru6_RRegs : _FRU6<0b011001, (outs RRegs:$a), (ins i32imm:$b),
570 "ldaw $a, sp[$b]", []>;
572 let isCodeGenOnly = 1 in
573 def LDAWSP_lru6_RRegs : _FLRU6<0b011001, (outs RRegs:$a), (ins i32imm:$b),
574 "ldaw $a, sp[$b]", []>;
575 }
576 }
578 let isReMaterializable = 1 in {
579 def LDC_ru6 : _FRU6<0b011010, (outs GRRegs:$a), (ins i32imm:$b),
580 "ldc $a, $b", [(set GRRegs:$a, immU6:$b)]>;
582 def LDC_lru6 : _FLRU6<0b011010, (outs GRRegs:$a), (ins i32imm:$b),
583 "ldc $a, $b", [(set GRRegs:$a, immU16:$b)]>;
584 }
586 def SETC_ru6 : _FRU6<0b111010, (outs), (ins GRRegs:$a, i32imm:$b),
587 "setc res[$a], $b",
588 [(int_xcore_setc GRRegs:$a, immU6:$b)]>;
590 def SETC_lru6 : _FLRU6<0b111010, (outs), (ins GRRegs:$a, i32imm:$b),
591 "setc res[$a], $b",
592 [(int_xcore_setc GRRegs:$a, immU16:$b)]>;
594 // Operand register - U6
595 let isBranch = 1, isTerminator = 1 in {
596 defm BRFT: FRU6_LRU6_branch<0b011100, "bt">;
597 defm BRBT: FRU6_LRU6_backwards_branch<0b011101, "bt">;
598 defm BRFF: FRU6_LRU6_branch<0b011110, "bf">;
599 defm BRBF: FRU6_LRU6_backwards_branch<0b011111, "bf">;
600 }
602 // U6
603 let Defs = [SP], Uses = [SP] in {
604 let neverHasSideEffects = 1 in
605 defm EXTSP : FU6_LU6_np<0b0111011110, "extsp">;
606 let mayStore = 1 in
607 defm ENTSP : FU6_LU6_np<0b0111011101, "entsp">;
609 let isReturn = 1, isTerminator = 1, mayLoad = 1, isBarrier = 1 in {
610 defm RETSP : FU6_LU6<0b0111011111, "retsp", XCoreRetsp>;
611 }
612 }
614 // TODO extdp, kentsp, krestsp, blat
615 // getsr, kalli
616 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
617 def BRBU_u6 : _FU6<0b0111011100, (outs), (ins brtarget:$a), "bu -$a", []>;
619 def BRBU_lu6 : _FLU6<0b0111011100, (outs), (ins brtarget:$a), "bu -$a", []>;
621 def BRFU_u6 : _FU6<0b0111001100, (outs), (ins brtarget:$a), "bu $a", []>;
623 def BRFU_lu6 : _FLU6<0b0111001100, (outs), (ins brtarget:$a), "bu $a", []>;
624 }
626 //let Uses = [CP] in ...
627 let Defs = [R11], neverHasSideEffects = 1, isReMaterializable = 1 in
628 def LDAWCP_u6: _FU6<0b0111111101, (outs), (ins MEMii:$a), "ldaw r11, cp[$a]",
629 []>;
631 let Defs = [R11], isReMaterializable = 1 in
632 def LDAWCP_lu6: _FLU6<0b0111111101, (outs), (ins MEMii:$a), "ldaw r11, cp[$a]",
633 [(set R11, ADDRcpii:$a)]>;
635 defm SETSR : FU6_LU6_int<0b0111101101, "setsr", int_xcore_setsr>;
637 defm CLRSR : FU6_LU6_int<0b0111101100, "clrsr", int_xcore_clrsr>;
639 // setsr may cause a branch if it is used to enable events. clrsr may
640 // branch if it is executed while events are enabled.
641 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1,
642 isCodeGenOnly = 1 in {
643 defm SETSR_branch : FU6_LU6_np<0b0111101101, "setsr">;
644 defm CLRSR_branch : FU6_LU6_np<0b0111101100, "clrsr">;
645 }
647 // U10
648 // TODO ldwcpl, blacp
650 let Defs = [R11], isReMaterializable = 1, neverHasSideEffects = 1 in
651 def LDAPF_u10 : _FU10<0b110110, (outs), (ins i32imm:$a), "ldap r11, $a", []>;
653 let Defs = [R11], isReMaterializable = 1 in
654 def LDAPF_lu10 : _FLU10<0b110110, (outs), (ins i32imm:$a), "ldap r11, $a",
655 [(set R11, (pcrelwrapper tglobaladdr:$a))]>;
657 let Defs = [R11], isReMaterializable = 1, isCodeGenOnly = 1 in
658 def LDAPF_lu10_ba : _FLU10<0b110110, (outs), (ins i32imm:$a), "ldap r11, $a",
659 [(set R11, (pcrelwrapper tblockaddress:$a))]>;
661 let isCall=1,
662 // All calls clobber the link register and the non-callee-saved registers:
663 Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in {
664 def BLRF_u10 : _FU10<0b110100, (outs), (ins calltarget:$a), "bl $a",
665 [(XCoreBranchLink immU10:$a)]>;
667 def BLRF_lu10 : _FLU10<0b110100, (outs), (ins calltarget:$a), "bl $a",
668 [(XCoreBranchLink immU20:$a)]>;
669 }
671 // Two operand short
672 // TODO eet, eef, tsetmr
673 def NOT : _F2R<0b100010, (outs GRRegs:$dst), (ins GRRegs:$b),
674 "not $dst, $b", [(set GRRegs:$dst, (not GRRegs:$b))]>;
676 def NEG : _F2R<0b100100, (outs GRRegs:$dst), (ins GRRegs:$b),
677 "neg $dst, $b", [(set GRRegs:$dst, (ineg GRRegs:$b))]>;
679 let Constraints = "$src1 = $dst" in {
680 def SEXT_rus :
681 _FRUSSrcDstBitp<0b001101, (outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
682 "sext $dst, $src2",
683 [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1,
684 immBitp:$src2))]>;
686 def SEXT_2r :
687 _F2RSrcDst<0b001100, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
688 "sext $dst, $src2",
689 [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1, GRRegs:$src2))]>;
691 def ZEXT_rus :
692 _FRUSSrcDstBitp<0b010001, (outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
693 "zext $dst, $src2",
694 [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1,
695 immBitp:$src2))]>;
697 def ZEXT_2r :
698 _F2RSrcDst<0b010000, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
699 "zext $dst, $src2",
700 [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1, GRRegs:$src2))]>;
702 def ANDNOT_2r :
703 _F2RSrcDst<0b001010, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
704 "andnot $dst, $src2",
705 [(set GRRegs:$dst, (and GRRegs:$src1, (not GRRegs:$src2)))]>;
706 }
708 let isReMaterializable = 1, neverHasSideEffects = 1 in
709 def MKMSK_rus : _FRUSBitp<0b101001, (outs GRRegs:$dst), (ins i32imm:$size),
710 "mkmsk $dst, $size", []>;
712 def MKMSK_2r : _F2R<0b101000, (outs GRRegs:$dst), (ins GRRegs:$size),
713 "mkmsk $dst, $size",
714 [(set GRRegs:$dst, (add (shl 1, GRRegs:$size), -1))]>;
716 def GETR_rus : _FRUS<0b100000, (outs GRRegs:$dst), (ins i32imm:$type),
717 "getr $dst, $type",
718 [(set GRRegs:$dst, (int_xcore_getr immUs:$type))]>;
720 def GETTS_2r : _F2R<0b001110, (outs GRRegs:$dst), (ins GRRegs:$r),
721 "getts $dst, res[$r]",
722 [(set GRRegs:$dst, (int_xcore_getts GRRegs:$r))]>;
724 def SETPT_2r : _FR2R<0b001111, (outs), (ins GRRegs:$r, GRRegs:$val),
725 "setpt res[$r], $val",
726 [(int_xcore_setpt GRRegs:$r, GRRegs:$val)]>;
728 def OUTCT_2r : _F2R<0b010010, (outs), (ins GRRegs:$r, GRRegs:$val),
729 "outct res[$r], $val",
730 [(int_xcore_outct GRRegs:$r, GRRegs:$val)]>;
732 def OUTCT_rus : _FRUS<0b010011, (outs), (ins GRRegs:$r, i32imm:$val),
733 "outct res[$r], $val",
734 [(int_xcore_outct GRRegs:$r, immUs:$val)]>;
736 def OUTT_2r : _FR2R<0b000011, (outs), (ins GRRegs:$r, GRRegs:$val),
737 "outt res[$r], $val",
738 [(int_xcore_outt GRRegs:$r, GRRegs:$val)]>;
740 def OUT_2r : _FR2R<0b101010, (outs), (ins GRRegs:$r, GRRegs:$val),
741 "out res[$r], $val",
742 [(int_xcore_out GRRegs:$r, GRRegs:$val)]>;
744 let Constraints = "$src = $dst" in
745 def OUTSHR_2r :
746 _F2RSrcDst<0b101011, (outs GRRegs:$dst), (ins GRRegs:$src, GRRegs:$r),
747 "outshr res[$r], $src",
748 [(set GRRegs:$dst, (int_xcore_outshr GRRegs:$r, GRRegs:$src))]>;
750 def INCT_2r : _F2R<0b100001, (outs GRRegs:$dst), (ins GRRegs:$r),
751 "inct $dst, res[$r]",
752 [(set GRRegs:$dst, (int_xcore_inct GRRegs:$r))]>;
754 def INT_2r : _F2R<0b100011, (outs GRRegs:$dst), (ins GRRegs:$r),
755 "int $dst, res[$r]",
756 [(set GRRegs:$dst, (int_xcore_int GRRegs:$r))]>;
758 def IN_2r : _F2R<0b101100, (outs GRRegs:$dst), (ins GRRegs:$r),
759 "in $dst, res[$r]",
760 [(set GRRegs:$dst, (int_xcore_in GRRegs:$r))]>;
762 let Constraints = "$src = $dst" in
763 def INSHR_2r :
764 _F2RSrcDst<0b101101, (outs GRRegs:$dst), (ins GRRegs:$src, GRRegs:$r),
765 "inshr $dst, res[$r]",
766 [(set GRRegs:$dst, (int_xcore_inshr GRRegs:$r, GRRegs:$src))]>;
768 def CHKCT_2r : _F2R<0b110010, (outs), (ins GRRegs:$r, GRRegs:$val),
769 "chkct res[$r], $val",
770 [(int_xcore_chkct GRRegs:$r, GRRegs:$val)]>;
772 def CHKCT_rus : _FRUSBitp<0b110011, (outs), (ins GRRegs:$r, i32imm:$val),
773 "chkct res[$r], $val",
774 [(int_xcore_chkct GRRegs:$r, immUs:$val)]>;
776 def TESTCT_2r : _F2R<0b101111, (outs GRRegs:$dst), (ins GRRegs:$src),
777 "testct $dst, res[$src]",
778 [(set GRRegs:$dst, (int_xcore_testct GRRegs:$src))]>;
780 def TESTWCT_2r : _F2R<0b110001, (outs GRRegs:$dst), (ins GRRegs:$src),
781 "testwct $dst, res[$src]",
782 [(set GRRegs:$dst, (int_xcore_testwct GRRegs:$src))]>;
784 def SETD_2r : _FR2R<0b000101, (outs), (ins GRRegs:$r, GRRegs:$val),
785 "setd res[$r], $val",
786 [(int_xcore_setd GRRegs:$r, GRRegs:$val)]>;
788 def SETPSC_2r : _FR2R<0b110000, (outs), (ins GRRegs:$src1, GRRegs:$src2),
789 "setpsc res[$src1], $src2",
790 [(int_xcore_setpsc GRRegs:$src1, GRRegs:$src2)]>;
792 def GETST_2r : _F2R<0b000001, (outs GRRegs:$dst), (ins GRRegs:$r),
793 "getst $dst, res[$r]",
794 [(set GRRegs:$dst, (int_xcore_getst GRRegs:$r))]>;
796 def INITSP_2r : _F2R<0b000100, (outs), (ins GRRegs:$src, GRRegs:$t),
797 "init t[$t]:sp, $src",
798 [(int_xcore_initsp GRRegs:$t, GRRegs:$src)]>;
800 def INITPC_2r : _F2R<0b000000, (outs), (ins GRRegs:$src, GRRegs:$t),
801 "init t[$t]:pc, $src",
802 [(int_xcore_initpc GRRegs:$t, GRRegs:$src)]>;
804 def INITCP_2r : _F2R<0b000110, (outs), (ins GRRegs:$src, GRRegs:$t),
805 "init t[$t]:cp, $src",
806 [(int_xcore_initcp GRRegs:$t, GRRegs:$src)]>;
808 def INITDP_2r : _F2R<0b000010, (outs), (ins GRRegs:$src, GRRegs:$t),
809 "init t[$t]:dp, $src",
810 [(int_xcore_initdp GRRegs:$t, GRRegs:$src)]>;
812 def PEEK_2r : _F2R<0b101110, (outs GRRegs:$dst), (ins GRRegs:$src),
813 "peek $dst, res[$src]",
814 [(set GRRegs:$dst, (int_xcore_peek GRRegs:$src))]>;
816 def ENDIN_2r : _F2R<0b100101, (outs GRRegs:$dst), (ins GRRegs:$src),
817 "endin $dst, res[$src]",
818 [(set GRRegs:$dst, (int_xcore_endin GRRegs:$src))]>;
820 // Two operand long
821 def BITREV_l2r : _FL2R<0b0000011000, (outs GRRegs:$dst), (ins GRRegs:$src),
822 "bitrev $dst, $src",
823 [(set GRRegs:$dst, (int_xcore_bitrev GRRegs:$src))]>;
825 def BYTEREV_l2r : _FL2R<0b0000011001, (outs GRRegs:$dst), (ins GRRegs:$src),
826 "byterev $dst, $src",
827 [(set GRRegs:$dst, (bswap GRRegs:$src))]>;
829 def CLZ_l2r : _FL2R<0b000111000, (outs GRRegs:$dst), (ins GRRegs:$src),
830 "clz $dst, $src",
831 [(set GRRegs:$dst, (ctlz GRRegs:$src))]>;
833 def GETD_l2r : _FL2R<0b0001111001, (outs GRRegs:$dst), (ins GRRegs:$src),
834 "getd $dst, res[$src]", []>;
836 def GETN_l2r : _FL2R<0b0011011001, (outs GRRegs:$dst), (ins GRRegs:$src),
837 "getn $dst, res[$src]", []>;
839 def SETC_l2r : _FL2R<0b0010111001, (outs), (ins GRRegs:$r, GRRegs:$val),
840 "setc res[$r], $val",
841 [(int_xcore_setc GRRegs:$r, GRRegs:$val)]>;
843 def SETTW_l2r : _FLR2R<0b0010011001, (outs), (ins GRRegs:$r, GRRegs:$val),
844 "settw res[$r], $val",
845 [(int_xcore_settw GRRegs:$r, GRRegs:$val)]>;
847 def GETPS_l2r : _FL2R<0b0001011001, (outs GRRegs:$dst), (ins GRRegs:$src),
848 "get $dst, ps[$src]",
849 [(set GRRegs:$dst, (int_xcore_getps GRRegs:$src))]>;
851 def SETPS_l2r : _FLR2R<0b0001111000, (outs), (ins GRRegs:$src1, GRRegs:$src2),
852 "set ps[$src1], $src2",
853 [(int_xcore_setps GRRegs:$src1, GRRegs:$src2)]>;
855 def INITLR_l2r : _FL2R<0b0001011000, (outs), (ins GRRegs:$src, GRRegs:$t),
856 "init t[$t]:lr, $src",
857 [(int_xcore_initlr GRRegs:$t, GRRegs:$src)]>;
859 def SETCLK_l2r : _FLR2R<0b0000111001, (outs), (ins GRRegs:$src1, GRRegs:$src2),
860 "setclk res[$src1], $src2",
861 [(int_xcore_setclk GRRegs:$src1, GRRegs:$src2)]>;
863 def SETN_l2r : _FLR2R<0b0011011000, (outs), (ins GRRegs:$src1, GRRegs:$src2),
864 "setn res[$src1], $src2", []>;
866 def SETRDY_l2r : _FLR2R<0b0010111000, (outs), (ins GRRegs:$src1, GRRegs:$src2),
867 "setrdy res[$src1], $src2",
868 [(int_xcore_setrdy GRRegs:$src1, GRRegs:$src2)]>;
870 def TESTLCL_l2r : _FL2R<0b0010011000, (outs GRRegs:$dst), (ins GRRegs:$src),
871 "testlcl $dst, res[$src]", []>;
873 // One operand short
874 def MSYNC_1r : _F1R<0b000111, (outs), (ins GRRegs:$a),
875 "msync res[$a]",
876 [(int_xcore_msync GRRegs:$a)]>;
877 def MJOIN_1r : _F1R<0b000101, (outs), (ins GRRegs:$a),
878 "mjoin res[$a]",
879 [(int_xcore_mjoin GRRegs:$a)]>;
881 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
882 def BAU_1r : _F1R<0b001001, (outs), (ins GRRegs:$a),
883 "bau $a",
884 [(brind GRRegs:$a)]>;
886 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
887 def BR_JT : PseudoInstXCore<(outs), (ins InlineJT:$t, GRRegs:$i),
888 "bru $i\n$t",
889 [(XCoreBR_JT tjumptable:$t, GRRegs:$i)]>;
891 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
892 def BR_JT32 : PseudoInstXCore<(outs), (ins InlineJT32:$t, GRRegs:$i),
893 "bru $i\n$t",
894 [(XCoreBR_JT32 tjumptable:$t, GRRegs:$i)]>;
896 let Defs=[SP], neverHasSideEffects=1 in
897 def SETSP_1r : _F1R<0b001011, (outs), (ins GRRegs:$a), "set sp, $a", []>;
899 let neverHasSideEffects=1 in
900 def SETDP_1r : _F1R<0b001100, (outs), (ins GRRegs:$a), "set dp, $a", []>;
902 let neverHasSideEffects=1 in
903 def SETCP_1r : _F1R<0b001101, (outs), (ins GRRegs:$a), "set cp, $a", []>;
905 let hasCtrlDep = 1 in
906 def ECALLT_1r : _F1R<0b010011, (outs), (ins GRRegs:$a),
907 "ecallt $a",
908 []>;
910 let hasCtrlDep = 1 in
911 def ECALLF_1r : _F1R<0b010010, (outs), (ins GRRegs:$a),
912 "ecallf $a",
913 []>;
915 let isCall=1,
916 // All calls clobber the link register and the non-callee-saved registers:
917 Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in {
918 def BLA_1r : _F1R<0b001000, (outs), (ins GRRegs:$a),
919 "bla $a",
920 [(XCoreBranchLink GRRegs:$a)]>;
921 }
923 def SYNCR_1r : _F1R<0b100001, (outs), (ins GRRegs:$a),
924 "syncr res[$a]",
925 [(int_xcore_syncr GRRegs:$a)]>;
927 def FREER_1r : _F1R<0b000100, (outs), (ins GRRegs:$a),
928 "freer res[$a]",
929 [(int_xcore_freer GRRegs:$a)]>;
931 let Uses=[R11] in {
932 def SETV_1r : _F1R<0b010001, (outs), (ins GRRegs:$a),
933 "setv res[$a], r11",
934 [(int_xcore_setv GRRegs:$a, R11)]>;
936 def SETEV_1r : _F1R<0b001111, (outs), (ins GRRegs:$a),
937 "setev res[$a], r11",
938 [(int_xcore_setev GRRegs:$a, R11)]>;
939 }
941 def DGETREG_1r : _F1R<0b001110, (outs GRRegs:$a), (ins), "dgetreg $a", []>;
943 def EDU_1r : _F1R<0b000000, (outs), (ins GRRegs:$a), "edu res[$a]", []>;
945 def EEU_1r : _F1R<0b000001, (outs), (ins GRRegs:$a),
946 "eeu res[$a]",
947 [(int_xcore_eeu GRRegs:$a)]>;
949 def KCALL_1r : _F1R<0b010000, (outs), (ins GRRegs:$a), "kcall $a", []>;
951 def WAITEF_1R : _F1R<0b000011, (outs), (ins GRRegs:$a), "waitef $a", []>;
953 def WAITET_1R : _F1R<0b000010, (outs), (ins GRRegs:$a), "waitet $a", []>;
955 def TSTART_1R : _F1R<0b000110, (outs), (ins GRRegs:$a), "start t[$a]", []>;
957 def CLRPT_1R : _F1R<0b100000, (outs), (ins GRRegs:$a), "clrpt res[$a]", []>;
959 // Zero operand short
961 def CLRE_0R : _F0R<0b0000001101, (outs), (ins), "clre", [(int_xcore_clre)]>;
963 def DCALL_0R : _F0R<0b0000011100, (outs), (ins), "dcall", []>;
965 let Defs = [SP], Uses = [SP] in
966 def DENTSP_0R : _F0R<0b0001001100, (outs), (ins), "dentsp", []>;
968 let Defs = [SP] in
969 def DRESTSP_0R : _F0R<0b0001001101, (outs), (ins), "drestsp", []>;
971 def DRET_0R : _F0R<0b0000011110, (outs), (ins), "dret", []>;
973 def FREET_0R : _F0R<0b0000001111, (outs), (ins), "freet", []>;
975 let Defs = [R11] in {
976 def GETID_0R : _F0R<0b0001001110, (outs), (ins),
977 "get r11, id",
978 [(set R11, (int_xcore_getid))]>;
980 def GETED_0R : _F0R<0b0000111110, (outs), (ins),
981 "get r11, ed",
982 [(set R11, (int_xcore_geted))]>;
984 def GETET_0R : _F0R<0b0000111111, (outs), (ins),
985 "get r11, et",
986 [(set R11, (int_xcore_getet))]>;
988 def GETKEP_0R : _F0R<0b0001001111, (outs), (ins),
989 "get r11, kep", []>;
991 def GETKSP_0R : _F0R<0b0001011100, (outs), (ins),
992 "get r11, ksp", []>;
993 }
995 let Defs = [SP] in
996 def KRET_0R : _F0R<0b0000011101, (outs), (ins), "kret", []>;
998 let Uses = [SP], mayLoad = 1 in {
999 def LDET_0R : _F0R<0b0001011110, (outs), (ins), "ldw et, sp[4]", []>;
1001 def LDSED_0R : _F0R<0b0001011101, (outs), (ins), "ldw sed, sp[3]", []>;
1003 def LDSPC_0R : _F0R<0b0000101100, (outs), (ins), "ldw spc, sp[1]", []>;
1005 def LDSSR_0R : _F0R<0b0000101110, (outs), (ins), "ldw ssr, sp[2]", []>;
1006 }
1008 let Uses=[R11] in
1009 def SETKEP_0R : _F0R<0b0000011111, (outs), (ins), "set kep, r11", []>;
1011 def SSYNC_0r : _F0R<0b0000001110, (outs), (ins),
1012 "ssync",
1013 [(int_xcore_ssync)]>;
1015 let Uses = [SP], mayStore = 1 in {
1016 def STET_0R : _F0R<0b0000111101, (outs), (ins), "stw et, sp[4]", []>;
1018 def STSED_0R : _F0R<0b0000111100, (outs), (ins), "stw sed, sp[3]", []>;
1020 def STSPC_0R : _F0R<0b0000101101, (outs), (ins), "stw spc, sp[1]", []>;
1022 def STSSR_0R : _F0R<0b0000101111, (outs), (ins), "stw ssr, sp[2]", []>;
1023 }
1025 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1,
1026 hasSideEffects = 1 in
1027 def WAITEU_0R : _F0R<0b0000001100, (outs), (ins),
1028 "waiteu",
1029 [(brind (int_xcore_waitevent))]>;
1031 //===----------------------------------------------------------------------===//
1032 // Non-Instruction Patterns
1033 //===----------------------------------------------------------------------===//
1035 def : Pat<(XCoreBranchLink tglobaladdr:$addr), (BLRF_lu10 tglobaladdr:$addr)>;
1036 def : Pat<(XCoreBranchLink texternalsym:$addr), (BLRF_lu10 texternalsym:$addr)>;
1038 /// sext_inreg
1039 def : Pat<(sext_inreg GRRegs:$b, i1), (SEXT_rus GRRegs:$b, 1)>;
1040 def : Pat<(sext_inreg GRRegs:$b, i8), (SEXT_rus GRRegs:$b, 8)>;
1041 def : Pat<(sext_inreg GRRegs:$b, i16), (SEXT_rus GRRegs:$b, 16)>;
1043 /// loads
1044 def : Pat<(zextloadi8 (add GRRegs:$addr, GRRegs:$offset)),
1045 (LD8U_3r GRRegs:$addr, GRRegs:$offset)>;
1046 def : Pat<(zextloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>;
1048 def : Pat<(sextloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)),
1049 (LD16S_3r GRRegs:$addr, GRRegs:$offset)>;
1050 def : Pat<(sextloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>;
1052 def : Pat<(load (ldawf GRRegs:$addr, GRRegs:$offset)),
1053 (LDW_3r GRRegs:$addr, GRRegs:$offset)>;
1054 def : Pat<(load (add GRRegs:$addr, immUs4:$offset)),
1055 (LDW_2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;
1056 def : Pat<(load GRRegs:$addr), (LDW_2rus GRRegs:$addr, 0)>;
1058 /// anyext
1059 def : Pat<(extloadi8 (add GRRegs:$addr, GRRegs:$offset)),
1060 (LD8U_3r GRRegs:$addr, GRRegs:$offset)>;
1061 def : Pat<(extloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>;
1062 def : Pat<(extloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)),
1063 (LD16S_3r GRRegs:$addr, GRRegs:$offset)>;
1064 def : Pat<(extloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>;
1066 /// stores
1067 def : Pat<(truncstorei8 GRRegs:$val, (add GRRegs:$addr, GRRegs:$offset)),
1068 (ST8_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;
1069 def : Pat<(truncstorei8 GRRegs:$val, GRRegs:$addr),
1070 (ST8_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>;
1072 def : Pat<(truncstorei16 GRRegs:$val, (lda16f GRRegs:$addr, GRRegs:$offset)),
1073 (ST16_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;
1074 def : Pat<(truncstorei16 GRRegs:$val, GRRegs:$addr),
1075 (ST16_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>;
1077 def : Pat<(store GRRegs:$val, (ldawf GRRegs:$addr, GRRegs:$offset)),
1078 (STW_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;
1079 def : Pat<(store GRRegs:$val, (add GRRegs:$addr, immUs4:$offset)),
1080 (STW_2rus GRRegs:$val, GRRegs:$addr, (div4_xform immUs4:$offset))>;
1081 def : Pat<(store GRRegs:$val, GRRegs:$addr),
1082 (STW_2rus GRRegs:$val, GRRegs:$addr, 0)>;
1084 /// cttz
1085 def : Pat<(cttz GRRegs:$src), (CLZ_l2r (BITREV_l2r GRRegs:$src))>;
1087 /// trap
1088 def : Pat<(trap), (ECALLF_1r (LDC_ru6 0))>;
1090 ///
1091 /// branch patterns
1092 ///
1094 // unconditional branch
1095 def : Pat<(br bb:$addr), (BRFU_lu6 bb:$addr)>;
1097 // direct match equal/notequal zero brcond
1098 def : Pat<(brcond (setne GRRegs:$lhs, 0), bb:$dst),
1099 (BRFT_lru6 GRRegs:$lhs, bb:$dst)>;
1100 def : Pat<(brcond (seteq GRRegs:$lhs, 0), bb:$dst),
1101 (BRFF_lru6 GRRegs:$lhs, bb:$dst)>;
1103 def : Pat<(brcond (setle GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1104 (BRFF_lru6 (LSS_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>;
1105 def : Pat<(brcond (setule GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1106 (BRFF_lru6 (LSU_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>;
1107 def : Pat<(brcond (setge GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1108 (BRFF_lru6 (LSS_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>;
1109 def : Pat<(brcond (setuge GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1110 (BRFF_lru6 (LSU_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>;
1111 def : Pat<(brcond (setne GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1112 (BRFF_lru6 (EQ_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>;
1113 def : Pat<(brcond (setne GRRegs:$lhs, immUs:$rhs), bb:$dst),
1114 (BRFF_lru6 (EQ_2rus GRRegs:$lhs, immUs:$rhs), bb:$dst)>;
1116 // generic brcond pattern
1117 def : Pat<(brcond GRRegs:$cond, bb:$addr), (BRFT_lru6 GRRegs:$cond, bb:$addr)>;
1120 ///
1121 /// Select patterns
1122 ///
1124 // direct match equal/notequal zero select
1125 def : Pat<(select (setne GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),
1126 (SELECT_CC GRRegs:$lhs, GRRegs:$T, GRRegs:$F)>;
1128 def : Pat<(select (seteq GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),
1129 (SELECT_CC GRRegs:$lhs, GRRegs:$F, GRRegs:$T)>;
1131 def : Pat<(select (setle GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1132 (SELECT_CC (LSS_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>;
1133 def : Pat<(select (setule GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1134 (SELECT_CC (LSU_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>;
1135 def : Pat<(select (setge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1136 (SELECT_CC (LSS_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
1137 def : Pat<(select (setuge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1138 (SELECT_CC (LSU_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
1139 def : Pat<(select (setne GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1140 (SELECT_CC (EQ_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
1141 def : Pat<(select (setne GRRegs:$lhs, immUs:$rhs), GRRegs:$T, GRRegs:$F),
1142 (SELECT_CC (EQ_2rus GRRegs:$lhs, immUs:$rhs), GRRegs:$F, GRRegs:$T)>;
1144 ///
1145 /// setcc patterns, only matched when none of the above brcond
1146 /// patterns match
1147 ///
1149 // setcc 2 register operands
1150 def : Pat<(setle GRRegs:$lhs, GRRegs:$rhs),
1151 (EQ_2rus (LSS_3r GRRegs:$rhs, GRRegs:$lhs), 0)>;
1152 def : Pat<(setule GRRegs:$lhs, GRRegs:$rhs),
1153 (EQ_2rus (LSU_3r GRRegs:$rhs, GRRegs:$lhs), 0)>;
1155 def : Pat<(setgt GRRegs:$lhs, GRRegs:$rhs),
1156 (LSS_3r GRRegs:$rhs, GRRegs:$lhs)>;
1157 def : Pat<(setugt GRRegs:$lhs, GRRegs:$rhs),
1158 (LSU_3r GRRegs:$rhs, GRRegs:$lhs)>;
1160 def : Pat<(setge GRRegs:$lhs, GRRegs:$rhs),
1161 (EQ_2rus (LSS_3r GRRegs:$lhs, GRRegs:$rhs), 0)>;
1162 def : Pat<(setuge GRRegs:$lhs, GRRegs:$rhs),
1163 (EQ_2rus (LSU_3r GRRegs:$lhs, GRRegs:$rhs), 0)>;
1165 def : Pat<(setlt GRRegs:$lhs, GRRegs:$rhs),
1166 (LSS_3r GRRegs:$lhs, GRRegs:$rhs)>;
1167 def : Pat<(setult GRRegs:$lhs, GRRegs:$rhs),
1168 (LSU_3r GRRegs:$lhs, GRRegs:$rhs)>;
1170 def : Pat<(setne GRRegs:$lhs, GRRegs:$rhs),
1171 (EQ_2rus (EQ_3r GRRegs:$lhs, GRRegs:$rhs), 0)>;
1173 def : Pat<(seteq GRRegs:$lhs, GRRegs:$rhs),
1174 (EQ_3r GRRegs:$lhs, GRRegs:$rhs)>;
1176 // setcc reg/imm operands
1177 def : Pat<(seteq GRRegs:$lhs, immUs:$rhs),
1178 (EQ_2rus GRRegs:$lhs, immUs:$rhs)>;
1179 def : Pat<(setne GRRegs:$lhs, immUs:$rhs),
1180 (EQ_2rus (EQ_2rus GRRegs:$lhs, immUs:$rhs), 0)>;
1182 // misc
1183 def : Pat<(add GRRegs:$addr, immUs4:$offset),
1184 (LDAWF_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;
1186 def : Pat<(sub GRRegs:$addr, immUs4:$offset),
1187 (LDAWB_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;
1189 def : Pat<(and GRRegs:$val, immMskBitp:$mask),
1190 (ZEXT_rus GRRegs:$val, (msksize_xform immMskBitp:$mask))>;
1192 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1193 def : Pat<(add GRRegs:$src1, immUsNeg:$src2),
1194 (SUB_2rus GRRegs:$src1, (neg_xform immUsNeg:$src2))>;
1196 def : Pat<(add GRRegs:$src1, immUs4Neg:$src2),
1197 (LDAWB_l2rus GRRegs:$src1, (div4neg_xform immUs4Neg:$src2))>;
1199 ///
1200 /// Some peepholes
1201 ///
1203 def : Pat<(mul GRRegs:$src, 3),
1204 (LDA16F_l3r GRRegs:$src, GRRegs:$src)>;
1206 def : Pat<(mul GRRegs:$src, 5),
1207 (LDAWF_l3r GRRegs:$src, GRRegs:$src)>;
1209 def : Pat<(mul GRRegs:$src, -3),
1210 (LDAWB_l3r GRRegs:$src, GRRegs:$src)>;
1212 // ashr X, 32 is equivalent to ashr X, 31 on the XCore.
1213 def : Pat<(sra GRRegs:$src, 31),
1214 (ASHR_l2rus GRRegs:$src, 32)>;
1216 def : Pat<(brcond (setlt GRRegs:$lhs, 0), bb:$dst),
1217 (BRFT_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>;
1219 // setge X, 0 is canonicalized to setgt X, -1
1220 def : Pat<(brcond (setgt GRRegs:$lhs, -1), bb:$dst),
1221 (BRFF_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>;
1223 def : Pat<(select (setlt GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),
1224 (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$T, GRRegs:$F)>;
1226 def : Pat<(select (setgt GRRegs:$lhs, -1), GRRegs:$T, GRRegs:$F),
1227 (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$F, GRRegs:$T)>;
1229 def : Pat<(setgt GRRegs:$lhs, -1),
1230 (EQ_2rus (ASHR_l2rus GRRegs:$lhs, 32), 0)>;
1232 def : Pat<(sra (shl GRRegs:$src, immBpwSubBitp:$imm), immBpwSubBitp:$imm),
1233 (SEXT_rus GRRegs:$src, (bpwsub_xform immBpwSubBitp:$imm))>;