1 //===- XCoreInstrInfo.td - Target Description for XCore ----*- tablegen -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file describes the XCore instructions in TableGen format.
11 //
12 //===----------------------------------------------------------------------===//
14 // Uses of CP, DP are not currently reflected in the patterns, since
15 // having a physical register as an operand prevents loop hoisting and
16 // since the value of these registers never changes during the life of the
17 // function.
19 //===----------------------------------------------------------------------===//
20 // Instruction format superclass.
21 //===----------------------------------------------------------------------===//
23 include "XCoreInstrFormats.td"
25 //===----------------------------------------------------------------------===//
26 // XCore specific DAG Nodes.
27 //
29 // Call
30 def SDT_XCoreBranchLink : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
31 def XCoreBranchLink : SDNode<"XCoreISD::BL",SDT_XCoreBranchLink,
32 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
33 SDNPVariadic]>;
35 def XCoreRetsp : SDNode<"XCoreISD::RETSP", SDTBrind,
36 [SDNPHasChain, SDNPOptInGlue]>;
38 def SDT_XCoreBR_JT : SDTypeProfile<0, 2,
39 [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
41 def XCoreBR_JT : SDNode<"XCoreISD::BR_JT", SDT_XCoreBR_JT,
42 [SDNPHasChain]>;
44 def XCoreBR_JT32 : SDNode<"XCoreISD::BR_JT32", SDT_XCoreBR_JT,
45 [SDNPHasChain]>;
47 def SDT_XCoreAddress : SDTypeProfile<1, 1,
48 [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
50 def pcrelwrapper : SDNode<"XCoreISD::PCRelativeWrapper", SDT_XCoreAddress,
51 []>;
53 def dprelwrapper : SDNode<"XCoreISD::DPRelativeWrapper", SDT_XCoreAddress,
54 []>;
56 def cprelwrapper : SDNode<"XCoreISD::CPRelativeWrapper", SDT_XCoreAddress,
57 []>;
59 def SDT_XCoreStwsp : SDTypeProfile<0, 2, [SDTCisInt<1>]>;
60 def XCoreStwsp : SDNode<"XCoreISD::STWSP", SDT_XCoreStwsp,
61 [SDNPHasChain]>;
63 // These are target-independent nodes, but have target-specific formats.
64 def SDT_XCoreCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
65 def SDT_XCoreCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
66 SDTCisVT<1, i32> ]>;
68 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_XCoreCallSeqStart,
69 [SDNPHasChain, SDNPOutGlue]>;
70 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_XCoreCallSeqEnd,
71 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
73 //===----------------------------------------------------------------------===//
74 // Instruction Pattern Stuff
75 //===----------------------------------------------------------------------===//
77 def div4_xform : SDNodeXForm<imm, [{
78 // Transformation function: imm/4
79 assert(N->getZExtValue() % 4 == 0);
80 return getI32Imm(N->getZExtValue()/4);
81 }]>;
83 def msksize_xform : SDNodeXForm<imm, [{
84 // Transformation function: get the size of a mask
85 assert(isMask_32(N->getZExtValue()));
86 // look for the first non-zero bit
87 return getI32Imm(32 - CountLeadingZeros_32(N->getZExtValue()));
88 }]>;
90 def neg_xform : SDNodeXForm<imm, [{
91 // Transformation function: -imm
92 uint32_t value = N->getZExtValue();
93 return getI32Imm(-value);
94 }]>;
96 def bpwsub_xform : SDNodeXForm<imm, [{
97 // Transformation function: 32-imm
98 uint32_t value = N->getZExtValue();
99 return getI32Imm(32-value);
100 }]>;
102 def div4neg_xform : SDNodeXForm<imm, [{
103 // Transformation function: -imm/4
104 uint32_t value = N->getZExtValue();
105 assert(-value % 4 == 0);
106 return getI32Imm(-value/4);
107 }]>;
109 def immUs4Neg : PatLeaf<(imm), [{
110 uint32_t value = (uint32_t)N->getZExtValue();
111 return (-value)%4 == 0 && (-value)/4 <= 11;
112 }]>;
114 def immUs4 : PatLeaf<(imm), [{
115 uint32_t value = (uint32_t)N->getZExtValue();
116 return value%4 == 0 && value/4 <= 11;
117 }]>;
119 def immUsNeg : PatLeaf<(imm), [{
120 return -((uint32_t)N->getZExtValue()) <= 11;
121 }]>;
123 def immUs : PatLeaf<(imm), [{
124 return (uint32_t)N->getZExtValue() <= 11;
125 }]>;
127 def immU6 : PatLeaf<(imm), [{
128 return (uint32_t)N->getZExtValue() < (1 << 6);
129 }]>;
131 def immU10 : PatLeaf<(imm), [{
132 return (uint32_t)N->getZExtValue() < (1 << 10);
133 }]>;
135 def immU16 : PatLeaf<(imm), [{
136 return (uint32_t)N->getZExtValue() < (1 << 16);
137 }]>;
139 def immU20 : PatLeaf<(imm), [{
140 return (uint32_t)N->getZExtValue() < (1 << 20);
141 }]>;
143 def immMskBitp : PatLeaf<(imm), [{ return immMskBitp(N); }]>;
145 def immBitp : PatLeaf<(imm), [{
146 uint32_t value = (uint32_t)N->getZExtValue();
147 return (value >= 1 && value <= 8)
148 || value == 16
149 || value == 24
150 || value == 32;
151 }]>;
153 def immBpwSubBitp : PatLeaf<(imm), [{
154 uint32_t value = (uint32_t)N->getZExtValue();
155 return (value >= 24 && value <= 31)
156 || value == 16
157 || value == 8
158 || value == 0;
159 }]>;
161 def lda16f : PatFrag<(ops node:$addr, node:$offset),
162 (add node:$addr, (shl node:$offset, 1))>;
163 def lda16b : PatFrag<(ops node:$addr, node:$offset),
164 (sub node:$addr, (shl node:$offset, 1))>;
165 def ldawf : PatFrag<(ops node:$addr, node:$offset),
166 (add node:$addr, (shl node:$offset, 2))>;
167 def ldawb : PatFrag<(ops node:$addr, node:$offset),
168 (sub node:$addr, (shl node:$offset, 2))>;
170 // Instruction operand types
171 def calltarget : Operand<i32>;
172 def brtarget : Operand<OtherVT>;
173 def pclabel : Operand<i32>;
175 // Addressing modes
176 def ADDRspii : ComplexPattern<i32, 2, "SelectADDRspii", [add, frameindex], []>;
177 def ADDRdpii : ComplexPattern<i32, 2, "SelectADDRdpii", [add, dprelwrapper],
178 []>;
179 def ADDRcpii : ComplexPattern<i32, 2, "SelectADDRcpii", [add, cprelwrapper],
180 []>;
182 // Address operands
183 def MEMii : Operand<i32> {
184 let PrintMethod = "printMemOperand";
185 let MIOperandInfo = (ops i32imm, i32imm);
186 }
188 // Jump tables.
189 def InlineJT : Operand<i32> {
190 let PrintMethod = "printInlineJT";
191 }
193 def InlineJT32 : Operand<i32> {
194 let PrintMethod = "printInlineJT32";
195 }
197 //===----------------------------------------------------------------------===//
198 // Instruction Class Templates
199 //===----------------------------------------------------------------------===//
201 // Three operand short
203 multiclass F3R_2RUS<string OpcStr, SDNode OpNode> {
204 def _3r: _F3R<
205 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
206 !strconcat(OpcStr, " $dst, $b, $c"),
207 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
208 def _2rus : _F2RUS<
209 (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
210 !strconcat(OpcStr, " $dst, $b, $c"),
211 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;
212 }
214 multiclass F3R_2RUS_np<string OpcStr> {
215 def _3r: _F3R<
216 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
217 !strconcat(OpcStr, " $dst, $b, $c"),
218 []>;
219 def _2rus : _F2RUS<
220 (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
221 !strconcat(OpcStr, " $dst, $b, $c"),
222 []>;
223 }
225 multiclass F3R_2RBITP<string OpcStr, SDNode OpNode> {
226 def _3r: _F3R<
227 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
228 !strconcat(OpcStr, " $dst, $b, $c"),
229 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
230 def _2rus : _F2RUS<
231 (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
232 !strconcat(OpcStr, " $dst, $b, $c"),
233 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
234 }
236 class F3R<string OpcStr, SDNode OpNode> : _F3R<
237 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
238 !strconcat(OpcStr, " $dst, $b, $c"),
239 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
241 class F3R_np<string OpcStr> : _F3R<
242 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
243 !strconcat(OpcStr, " $dst, $b, $c"),
244 []>;
245 // Three operand long
247 /// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot.
248 multiclass FL3R_L2RUS<string OpcStr, SDNode OpNode> {
249 def _l3r: _FL3R<
250 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
251 !strconcat(OpcStr, " $dst, $b, $c"),
252 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
253 def _l2rus : _FL2RUS<
254 (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
255 !strconcat(OpcStr, " $dst, $b, $c"),
256 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;
257 }
259 /// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot.
260 multiclass FL3R_L2RBITP<string OpcStr, SDNode OpNode> {
261 def _l3r: _FL3R<
262 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
263 !strconcat(OpcStr, " $dst, $b, $c"),
264 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
265 def _l2rus : _FL2RUS<
266 (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
267 !strconcat(OpcStr, " $dst, $b, $c"),
268 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
269 }
271 class FL3R<string OpcStr, SDNode OpNode> : _FL3R<
272 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
273 !strconcat(OpcStr, " $dst, $b, $c"),
274 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
276 // Register - U6
277 // Operand register - U6
278 multiclass FRU6_LRU6_branch<string OpcStr> {
279 def _ru6: _FRU6<
280 (outs), (ins GRRegs:$cond, brtarget:$dest),
281 !strconcat(OpcStr, " $cond, $dest"),
282 []>;
283 def _lru6: _FLRU6<
284 (outs), (ins GRRegs:$cond, brtarget:$dest),
285 !strconcat(OpcStr, " $cond, $dest"),
286 []>;
287 }
289 multiclass FRU6_LRU6_cp<string OpcStr> {
290 def _ru6: _FRU6<
291 (outs GRRegs:$dst), (ins i32imm:$a),
292 !strconcat(OpcStr, " $dst, cp[$a]"),
293 []>;
294 def _lru6: _FLRU6<
295 (outs GRRegs:$dst), (ins i32imm:$a),
296 !strconcat(OpcStr, " $dst, cp[$a]"),
297 []>;
298 }
300 // U6
301 multiclass FU6_LU6<string OpcStr, SDNode OpNode> {
302 def _u6: _FU6<
303 (outs), (ins i32imm:$b),
304 !strconcat(OpcStr, " $b"),
305 [(OpNode immU6:$b)]>;
306 def _lu6: _FLU6<
307 (outs), (ins i32imm:$b),
308 !strconcat(OpcStr, " $b"),
309 [(OpNode immU16:$b)]>;
310 }
311 multiclass FU6_LU6_int<string OpcStr, Intrinsic Int> {
312 def _u6: _FU6<
313 (outs), (ins i32imm:$b),
314 !strconcat(OpcStr, " $b"),
315 [(Int immU6:$b)]>;
316 def _lu6: _FLU6<
317 (outs), (ins i32imm:$b),
318 !strconcat(OpcStr, " $b"),
319 [(Int immU16:$b)]>;
320 }
322 multiclass FU6_LU6_np<string OpcStr> {
323 def _u6: _FU6<
324 (outs), (ins i32imm:$b),
325 !strconcat(OpcStr, " $b"),
326 []>;
327 def _lu6: _FLU6<
328 (outs), (ins i32imm:$b),
329 !strconcat(OpcStr, " $b"),
330 []>;
331 }
333 // U10
334 multiclass FU10_LU10_np<string OpcStr> {
335 def _u10: _FU10<
336 (outs), (ins i32imm:$b),
337 !strconcat(OpcStr, " $b"),
338 []>;
339 def _lu10: _FLU10<
340 (outs), (ins i32imm:$b),
341 !strconcat(OpcStr, " $b"),
342 []>;
343 }
345 // Two operand short
347 class F2R_np<string OpcStr> : _F2R<
348 (outs GRRegs:$dst), (ins GRRegs:$b),
349 !strconcat(OpcStr, " $dst, $b"),
350 []>;
352 // Two operand long
354 //===----------------------------------------------------------------------===//
355 // Pseudo Instructions
356 //===----------------------------------------------------------------------===//
358 let Defs = [SP], Uses = [SP] in {
359 def ADJCALLSTACKDOWN : PseudoInstXCore<(outs), (ins i32imm:$amt),
360 "${:comment} ADJCALLSTACKDOWN $amt",
361 [(callseq_start timm:$amt)]>;
362 def ADJCALLSTACKUP : PseudoInstXCore<(outs), (ins i32imm:$amt1, i32imm:$amt2),
363 "${:comment} ADJCALLSTACKUP $amt1",
364 [(callseq_end timm:$amt1, timm:$amt2)]>;
365 }
367 def LDWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr),
368 "${:comment} LDWFI $dst, $addr",
369 [(set GRRegs:$dst, (load ADDRspii:$addr))]>;
371 def LDAWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr),
372 "${:comment} LDAWFI $dst, $addr",
373 [(set GRRegs:$dst, ADDRspii:$addr)]>;
375 def STWFI : PseudoInstXCore<(outs), (ins GRRegs:$src, MEMii:$addr),
376 "${:comment} STWFI $src, $addr",
377 [(store GRRegs:$src, ADDRspii:$addr)]>;
379 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
380 // instruction selection into a branch sequence.
381 let usesCustomInserter = 1 in {
382 def SELECT_CC : PseudoInstXCore<(outs GRRegs:$dst),
383 (ins GRRegs:$cond, GRRegs:$T, GRRegs:$F),
384 "${:comment} SELECT_CC PSEUDO!",
385 [(set GRRegs:$dst,
386 (select GRRegs:$cond, GRRegs:$T, GRRegs:$F))]>;
387 }
389 //===----------------------------------------------------------------------===//
390 // Instructions
391 //===----------------------------------------------------------------------===//
393 // Three operand short
394 defm ADD : F3R_2RUS<"add", add>;
395 defm SUB : F3R_2RUS<"sub", sub>;
396 let neverHasSideEffects = 1 in {
397 defm EQ : F3R_2RUS_np<"eq">;
398 def LSS_3r : F3R_np<"lss">;
399 def LSU_3r : F3R_np<"lsu">;
400 }
401 def AND_3r : F3R<"and", and>;
402 def OR_3r : F3R<"or", or>;
404 let mayLoad=1 in {
405 def LDW_3r : _F3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
406 "ldw $dst, $addr[$offset]",
407 []>;
409 def LDW_2rus : _F2RUS<(outs GRRegs:$dst), (ins GRRegs:$addr, i32imm:$offset),
410 "ldw $dst, $addr[$offset]",
411 []>;
413 def LD16S_3r : _F3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
414 "ld16s $dst, $addr[$offset]",
415 []>;
417 def LD8U_3r : _F3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
418 "ld8u $dst, $addr[$offset]",
419 []>;
420 }
422 let mayStore=1 in {
423 def STW_3r : _F3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
424 "stw $val, $addr[$offset]",
425 []>;
427 def STW_2rus : _F2RUS<(outs), (ins GRRegs:$val, GRRegs:$addr, i32imm:$offset),
428 "stw $val, $addr[$offset]",
429 []>;
430 }
432 defm SHL : F3R_2RBITP<"shl", shl>;
433 defm SHR : F3R_2RBITP<"shr", srl>;
434 // TODO tsetr
436 // Three operand long
437 def LDAWF_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
438 "ldaw $dst, $addr[$offset]",
439 [(set GRRegs:$dst, (ldawf GRRegs:$addr, GRRegs:$offset))]>;
441 let neverHasSideEffects = 1 in
442 def LDAWF_l2rus : _FL2RUS<(outs GRRegs:$dst),
443 (ins GRRegs:$addr, i32imm:$offset),
444 "ldaw $dst, $addr[$offset]",
445 []>;
447 def LDAWB_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
448 "ldaw $dst, $addr[-$offset]",
449 [(set GRRegs:$dst, (ldawb GRRegs:$addr, GRRegs:$offset))]>;
451 let neverHasSideEffects = 1 in
452 def LDAWB_l2rus : _FL2RUS<(outs GRRegs:$dst),
453 (ins GRRegs:$addr, i32imm:$offset),
454 "ldaw $dst, $addr[-$offset]",
455 []>;
457 def LDA16F_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
458 "lda16 $dst, $addr[$offset]",
459 [(set GRRegs:$dst, (lda16f GRRegs:$addr, GRRegs:$offset))]>;
461 def LDA16B_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset),
462 "lda16 $dst, $addr[-$offset]",
463 [(set GRRegs:$dst, (lda16b GRRegs:$addr, GRRegs:$offset))]>;
465 def MUL_l3r : FL3R<"mul", mul>;
466 // Instructions which may trap are marked as side effecting.
467 let hasSideEffects = 1 in {
468 def DIVS_l3r : FL3R<"divs", sdiv>;
469 def DIVU_l3r : FL3R<"divu", udiv>;
470 def REMS_l3r : FL3R<"rems", srem>;
471 def REMU_l3r : FL3R<"remu", urem>;
472 }
473 def XOR_l3r : FL3R<"xor", xor>;
474 defm ASHR : FL3R_L2RBITP<"ashr", sra>;
476 let Constraints = "$src1 = $dst" in
477 def CRC_l3r : _FL3R<(outs GRRegs:$dst),
478 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
479 "crc32 $dst, $src2, $src3",
480 [(set GRRegs:$dst,
481 (int_xcore_crc32 GRRegs:$src1, GRRegs:$src2,
482 GRRegs:$src3))]>;
484 // TODO inpw, outpw
485 let mayStore=1 in {
486 def ST16_l3r : _FL3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
487 "st16 $val, $addr[$offset]",
488 []>;
490 def ST8_l3r : _FL3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
491 "st8 $val, $addr[$offset]",
492 []>;
493 }
495 // Four operand long
496 let Constraints = "$src1 = $dst1,$src2 = $dst2" in {
497 def MACCU_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2),
498 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3,
499 GRRegs:$src4),
500 "maccu $dst1, $dst2, $src3, $src4",
501 []>;
503 def MACCS_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2),
504 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3,
505 GRRegs:$src4),
506 "maccs $dst1, $dst2, $src3, $src4",
507 []>;
508 }
510 let Constraints = "$src1 = $dst1" in
511 def CRC8_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2),
512 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
513 "crc8 $dst1, $dst2, $src2, $src3",
514 []>;
516 // Five operand long
518 def LADD_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2),
519 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
520 "ladd $dst1, $dst2, $src1, $src2, $src3",
521 []>;
523 def LSUB_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2),
524 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
525 "lsub $dst1, $dst2, $src1, $src2, $src3",
526 []>;
528 def LDIV_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2),
529 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
530 "ldiv $dst1, $dst2, $src1, $src2, $src3",
531 []>;
533 // Six operand long
535 def LMUL_l6r : _L6R<(outs GRRegs:$dst1, GRRegs:$dst2),
536 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3,
537 GRRegs:$src4),
538 "lmul $dst1, $dst2, $src1, $src2, $src3, $src4",
539 []>;
541 // Register - U6
543 //let Uses = [DP] in ...
544 let neverHasSideEffects = 1, isReMaterializable = 1 in
545 def LDAWDP_ru6: _FRU6<(outs GRRegs:$dst), (ins MEMii:$a),
546 "ldaw $dst, dp[$a]",
547 []>;
549 let isReMaterializable = 1 in
550 def LDAWDP_lru6: _FLRU6<
551 (outs GRRegs:$dst), (ins MEMii:$a),
552 "ldaw $dst, dp[$a]",
553 [(set GRRegs:$dst, ADDRdpii:$a)]>;
555 let mayLoad=1 in
556 def LDWDP_ru6: _FRU6<(outs GRRegs:$dst), (ins MEMii:$a),
557 "ldw $dst, dp[$a]",
558 []>;
560 def LDWDP_lru6: _FLRU6<
561 (outs GRRegs:$dst), (ins MEMii:$a),
562 "ldw $dst, dp[$a]",
563 [(set GRRegs:$dst, (load ADDRdpii:$a))]>;
565 let mayStore=1 in
566 def STWDP_ru6 : _FRU6<(outs), (ins GRRegs:$val, MEMii:$addr),
567 "stw $val, dp[$addr]",
568 []>;
570 def STWDP_lru6 : _FLRU6<(outs), (ins GRRegs:$val, MEMii:$addr),
571 "stw $val, dp[$addr]",
572 [(store GRRegs:$val, ADDRdpii:$addr)]>;
574 //let Uses = [CP] in ..
575 let mayLoad = 1, isReMaterializable = 1 in
576 defm LDWCP : FRU6_LRU6_cp<"ldw">;
578 let Uses = [SP] in {
579 let mayStore=1 in {
580 def STWSP_ru6 : _FRU6<
581 (outs), (ins GRRegs:$val, i32imm:$index),
582 "stw $val, sp[$index]",
583 [(XCoreStwsp GRRegs:$val, immU6:$index)]>;
585 def STWSP_lru6 : _FLRU6<
586 (outs), (ins GRRegs:$val, i32imm:$index),
587 "stw $val, sp[$index]",
588 [(XCoreStwsp GRRegs:$val, immU16:$index)]>;
589 }
591 let mayLoad=1 in {
592 def LDWSP_ru6 : _FRU6<
593 (outs GRRegs:$dst), (ins i32imm:$b),
594 "ldw $dst, sp[$b]",
595 []>;
597 def LDWSP_lru6 : _FLRU6<
598 (outs GRRegs:$dst), (ins i32imm:$b),
599 "ldw $dst, sp[$b]",
600 []>;
601 }
603 let neverHasSideEffects = 1 in {
604 def LDAWSP_ru6 : _FRU6<
605 (outs GRRegs:$dst), (ins i32imm:$b),
606 "ldaw $dst, sp[$b]",
607 []>;
609 def LDAWSP_lru6 : _FLRU6<
610 (outs GRRegs:$dst), (ins i32imm:$b),
611 "ldaw $dst, sp[$b]",
612 []>;
614 def LDAWSP_ru6_RRegs : _FRU6<
615 (outs RRegs:$dst), (ins i32imm:$b),
616 "ldaw $dst, sp[$b]",
617 []>;
619 def LDAWSP_lru6_RRegs : _FLRU6<
620 (outs RRegs:$dst), (ins i32imm:$b),
621 "ldaw $dst, sp[$b]",
622 []>;
623 }
624 }
626 let isReMaterializable = 1 in {
627 def LDC_ru6 : _FRU6<
628 (outs GRRegs:$dst), (ins i32imm:$b),
629 "ldc $dst, $b",
630 [(set GRRegs:$dst, immU6:$b)]>;
632 def LDC_lru6 : _FLRU6<
633 (outs GRRegs:$dst), (ins i32imm:$b),
634 "ldc $dst, $b",
635 [(set GRRegs:$dst, immU16:$b)]>;
636 }
638 def SETC_ru6 : _FRU6<(outs), (ins GRRegs:$r, i32imm:$val),
639 "setc res[$r], $val",
640 [(int_xcore_setc GRRegs:$r, immU6:$val)]>;
642 def SETC_lru6 : _FLRU6<(outs), (ins GRRegs:$r, i32imm:$val),
643 "setc res[$r], $val",
644 [(int_xcore_setc GRRegs:$r, immU16:$val)]>;
646 // Operand register - U6
647 let isBranch = 1, isTerminator = 1 in {
648 defm BRFT: FRU6_LRU6_branch<"bt">;
649 defm BRBT: FRU6_LRU6_branch<"bt">;
650 defm BRFF: FRU6_LRU6_branch<"bf">;
651 defm BRBF: FRU6_LRU6_branch<"bf">;
652 }
654 // U6
655 let Defs = [SP], Uses = [SP] in {
656 let neverHasSideEffects = 1 in
657 defm EXTSP : FU6_LU6_np<"extsp">;
658 let mayStore = 1 in
659 defm ENTSP : FU6_LU6_np<"entsp">;
661 let isReturn = 1, isTerminator = 1, mayLoad = 1, isBarrier = 1 in {
662 defm RETSP : FU6_LU6<"retsp", XCoreRetsp>;
663 }
664 }
666 // TODO extdp, kentsp, krestsp, blat
667 // getsr, kalli
668 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
669 def BRBU_u6 : _FU6<
670 (outs),
671 (ins brtarget:$target),
672 "bu $target",
673 []>;
675 def BRBU_lu6 : _FLU6<
676 (outs),
677 (ins brtarget:$target),
678 "bu $target",
679 []>;
681 def BRFU_u6 : _FU6<
682 (outs),
683 (ins brtarget:$target),
684 "bu $target",
685 []>;
687 def BRFU_lu6 : _FLU6<
688 (outs),
689 (ins brtarget:$target),
690 "bu $target",
691 []>;
692 }
694 //let Uses = [CP] in ...
695 let Defs = [R11], neverHasSideEffects = 1, isReMaterializable = 1 in
696 def LDAWCP_u6: _FRU6<(outs), (ins MEMii:$a),
697 "ldaw r11, cp[$a]",
698 []>;
700 let Defs = [R11], isReMaterializable = 1 in
701 def LDAWCP_lu6: _FLRU6<
702 (outs), (ins MEMii:$a),
703 "ldaw r11, cp[$a]",
704 [(set R11, ADDRcpii:$a)]>;
706 defm SETSR : FU6_LU6_int<"setsr", int_xcore_setsr>;
708 defm CLRSR : FU6_LU6_int<"clrsr", int_xcore_clrsr>;
710 // setsr may cause a branch if it is used to enable events. clrsr may
711 // branch if it is executed while events are enabled.
712 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in {
713 defm SETSR_branch : FU6_LU6_np<"setsr">;
714 defm CLRSR_branch : FU6_LU6_np<"clrsr">;
715 }
717 // U10
718 // TODO ldwcpl, blacp
720 let Defs = [R11], isReMaterializable = 1, neverHasSideEffects = 1 in
721 def LDAP_u10 : _FU10<
722 (outs),
723 (ins i32imm:$addr),
724 "ldap r11, $addr",
725 []>;
727 let Defs = [R11], isReMaterializable = 1 in
728 def LDAP_lu10 : _FLU10<
729 (outs),
730 (ins i32imm:$addr),
731 "ldap r11, $addr",
732 [(set R11, (pcrelwrapper tglobaladdr:$addr))]>;
734 let Defs = [R11], isReMaterializable = 1 in
735 def LDAP_lu10_ba : _FLU10<(outs),
736 (ins i32imm:$addr),
737 "ldap r11, $addr",
738 [(set R11, (pcrelwrapper tblockaddress:$addr))]>;
740 let isCall=1,
741 // All calls clobber the link register and the non-callee-saved registers:
742 Defs = [R0, R1, R2, R3, R11, LR] in {
743 def BL_u10 : _FU10<
744 (outs),
745 (ins calltarget:$target, variable_ops),
746 "bl $target",
747 [(XCoreBranchLink immU10:$target)]>;
749 def BL_lu10 : _FLU10<
750 (outs),
751 (ins calltarget:$target, variable_ops),
752 "bl $target",
753 [(XCoreBranchLink immU20:$target)]>;
754 }
756 // Two operand short
757 // TODO eet, eef, testwct, tsetmr, sext (reg), zext (reg)
758 def NOT : _F2R<(outs GRRegs:$dst), (ins GRRegs:$b),
759 "not $dst, $b",
760 [(set GRRegs:$dst, (not GRRegs:$b))]>;
762 def NEG : _F2R<(outs GRRegs:$dst), (ins GRRegs:$b),
763 "neg $dst, $b",
764 [(set GRRegs:$dst, (ineg GRRegs:$b))]>;
766 let Constraints = "$src1 = $dst" in {
767 let neverHasSideEffects = 1 in
768 def SEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
769 "sext $dst, $src2",
770 []>;
772 let neverHasSideEffects = 1 in
773 def ZEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
774 "zext $dst, $src2",
775 []>;
777 def ANDNOT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
778 "andnot $dst, $src2",
779 [(set GRRegs:$dst, (and GRRegs:$src1, (not GRRegs:$src2)))]>;
780 }
782 let isReMaterializable = 1, neverHasSideEffects = 1 in
783 def MKMSK_rus : _FRUS<(outs GRRegs:$dst), (ins i32imm:$size),
784 "mkmsk $dst, $size",
785 []>;
787 def MKMSK_2r : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$size),
788 "mkmsk $dst, $size",
789 [(set GRRegs:$dst, (add (shl 1, GRRegs:$size), 0xffffffff))]>;
791 def GETR_rus : _FRUS<(outs GRRegs:$dst), (ins i32imm:$type),
792 "getr $dst, $type",
793 [(set GRRegs:$dst, (int_xcore_getr immUs:$type))]>;
795 def GETTS_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r),
796 "getts $dst, res[$r]",
797 [(set GRRegs:$dst, (int_xcore_getts GRRegs:$r))]>;
799 def SETPT_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val),
800 "setpt res[$r], $val",
801 [(int_xcore_setpt GRRegs:$r, GRRegs:$val)]>;
803 def OUTCT_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val),
804 "outct res[$r], $val",
805 [(int_xcore_outct GRRegs:$r, GRRegs:$val)]>;
807 def OUTCT_rus : _F2R<(outs), (ins GRRegs:$r, i32imm:$val),
808 "outct res[$r], $val",
809 [(int_xcore_outct GRRegs:$r, immUs:$val)]>;
811 def OUTT_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val),
812 "outt res[$r], $val",
813 [(int_xcore_outt GRRegs:$r, GRRegs:$val)]>;
815 def OUT_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val),
816 "out res[$r], $val",
817 [(int_xcore_out GRRegs:$r, GRRegs:$val)]>;
819 let Constraints = "$src = $dst" in
820 def OUTSHR_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r, GRRegs:$src),
821 "outshr res[$r], $src",
822 [(set GRRegs:$dst, (int_xcore_outshr GRRegs:$r, GRRegs:$src))]>;
824 def INCT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r),
825 "inct $dst, res[$r]",
826 [(set GRRegs:$dst, (int_xcore_inct GRRegs:$r))]>;
828 def INT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r),
829 "int $dst, res[$r]",
830 [(set GRRegs:$dst, (int_xcore_int GRRegs:$r))]>;
832 def IN_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r),
833 "in $dst, res[$r]",
834 [(set GRRegs:$dst, (int_xcore_in GRRegs:$r))]>;
836 let Constraints = "$src = $dst" in
837 def INSHR_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r, GRRegs:$src),
838 "inshr $dst, res[$r]",
839 [(set GRRegs:$dst, (int_xcore_inshr GRRegs:$r, GRRegs:$src))]>;
841 def CHKCT_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val),
842 "chkct res[$r], $val",
843 [(int_xcore_chkct GRRegs:$r, GRRegs:$val)]>;
845 def CHKCT_rus : _F2R<(outs), (ins GRRegs:$r, i32imm:$val),
846 "chkct res[$r], $val",
847 [(int_xcore_chkct GRRegs:$r, immUs:$val)]>;
849 def SETD_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val),
850 "setd res[$r], $val",
851 [(int_xcore_setd GRRegs:$r, GRRegs:$val)]>;
853 def GETST_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r),
854 "getst $dst, res[$r]",
855 [(set GRRegs:$dst, (int_xcore_getst GRRegs:$r))]>;
857 def INITSP_2r : _F2R<(outs), (ins GRRegs:$t, GRRegs:$src),
858 "init t[$t]:sp, $src",
859 [(int_xcore_initsp GRRegs:$t, GRRegs:$src)]>;
861 def INITPC_2r : _F2R<(outs), (ins GRRegs:$t, GRRegs:$src),
862 "init t[$t]:pc, $src",
863 [(int_xcore_initpc GRRegs:$t, GRRegs:$src)]>;
865 def INITCP_2r : _F2R<(outs), (ins GRRegs:$t, GRRegs:$src),
866 "init t[$t]:cp, $src",
867 [(int_xcore_initcp GRRegs:$t, GRRegs:$src)]>;
869 def INITDP_2r : _F2R<(outs), (ins GRRegs:$t, GRRegs:$src),
870 "init t[$t]:dp, $src",
871 [(int_xcore_initdp GRRegs:$t, GRRegs:$src)]>;
873 // Two operand long
874 // TODO endin, peek,
875 // getd, testlcl
876 def BITREV_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
877 "bitrev $dst, $src",
878 [(set GRRegs:$dst, (int_xcore_bitrev GRRegs:$src))]>;
880 def BYTEREV_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
881 "byterev $dst, $src",
882 [(set GRRegs:$dst, (bswap GRRegs:$src))]>;
884 def CLZ_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
885 "clz $dst, $src",
886 [(set GRRegs:$dst, (ctlz GRRegs:$src))]>;
888 def SETC_l2r : _FL2R<(outs), (ins GRRegs:$r, GRRegs:$val),
889 "setc res[$r], $val",
890 [(int_xcore_setc GRRegs:$r, GRRegs:$val)]>;
892 def SETTW_l2r : _FL2R<(outs), (ins GRRegs:$r, GRRegs:$val),
893 "settw res[$r], $val",
894 [(int_xcore_settw GRRegs:$r, GRRegs:$val)]>;
896 def GETPS_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
897 "get $dst, ps[$src]",
898 [(set GRRegs:$dst, (int_xcore_getps GRRegs:$src))]>;
900 def SETPS_l2r : _FL2R<(outs), (ins GRRegs:$src1, GRRegs:$src2),
901 "set ps[$src1], $src2",
902 [(int_xcore_setps GRRegs:$src1, GRRegs:$src2)]>;
904 def INITLR_l2r : _FL2R<(outs), (ins GRRegs:$t, GRRegs:$src),
905 "init t[$t]:lr, $src",
906 [(int_xcore_initlr GRRegs:$t, GRRegs:$src)]>;
908 def SETCLK_l2r : _FL2R<(outs), (ins GRRegs:$src1, GRRegs:$src2),
909 "setclk res[$src1], $src2",
910 [(int_xcore_setclk GRRegs:$src1, GRRegs:$src2)]>;
912 def SETRDY_l2r : _FL2R<(outs), (ins GRRegs:$src1, GRRegs:$src2),
913 "setrdy res[$src1], $src2",
914 [(int_xcore_setrdy GRRegs:$src1, GRRegs:$src2)]>;
916 def SETPSC_l2r : _FL2R<(outs), (ins GRRegs:$src1, GRRegs:$src2),
917 "setpsc res[$src1], $src2",
918 [(int_xcore_setpsc GRRegs:$src1, GRRegs:$src2)]>;
920 // One operand short
921 // TODO edu, eeu, waitet, waitef, tstart, clrtp
922 // setdp, setcp, setev, kcall
923 // dgetreg
924 def MSYNC_1r : _F1R<(outs), (ins GRRegs:$i),
925 "msync res[$i]",
926 [(int_xcore_msync GRRegs:$i)]>;
927 def MJOIN_1r : _F1R<(outs), (ins GRRegs:$i),
928 "mjoin res[$i]",
929 [(int_xcore_mjoin GRRegs:$i)]>;
931 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
932 def BAU_1r : _F1R<(outs), (ins GRRegs:$addr),
933 "bau $addr",
934 [(brind GRRegs:$addr)]>;
936 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
937 def BR_JT : PseudoInstXCore<(outs), (ins InlineJT:$t, GRRegs:$i),
938 "bru $i\n$t",
939 [(XCoreBR_JT tjumptable:$t, GRRegs:$i)]>;
941 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
942 def BR_JT32 : PseudoInstXCore<(outs), (ins InlineJT32:$t, GRRegs:$i),
943 "bru $i\n$t",
944 [(XCoreBR_JT32 tjumptable:$t, GRRegs:$i)]>;
946 let Defs=[SP], neverHasSideEffects=1 in
947 def SETSP_1r : _F1R<(outs), (ins GRRegs:$src),
948 "set sp, $src",
949 []>;
951 let hasCtrlDep = 1 in
952 def ECALLT_1r : _F1R<(outs), (ins GRRegs:$src),
953 "ecallt $src",
954 []>;
956 let hasCtrlDep = 1 in
957 def ECALLF_1r : _F1R<(outs), (ins GRRegs:$src),
958 "ecallf $src",
959 []>;
961 let isCall=1,
962 // All calls clobber the link register and the non-callee-saved registers:
963 Defs = [R0, R1, R2, R3, R11, LR] in {
964 def BLA_1r : _F1R<(outs), (ins GRRegs:$addr, variable_ops),
965 "bla $addr",
966 [(XCoreBranchLink GRRegs:$addr)]>;
967 }
969 def SYNCR_1r : _F1R<(outs), (ins GRRegs:$r),
970 "syncr res[$r]",
971 [(int_xcore_syncr GRRegs:$r)]>;
973 def FREER_1r : _F1R<(outs), (ins GRRegs:$r),
974 "freer res[$r]",
975 [(int_xcore_freer GRRegs:$r)]>;
977 let Uses=[R11] in
978 def SETV_1r : _F1R<(outs), (ins GRRegs:$r),
979 "setv res[$r], r11",
980 [(int_xcore_setv GRRegs:$r, R11)]>;
982 def EEU_1r : _F1R<(outs), (ins GRRegs:$r),
983 "eeu res[$r]",
984 [(int_xcore_eeu GRRegs:$r)]>;
986 // Zero operand short
987 // TODO freet, ldspc, stspc, ldssr, stssr, ldsed, stsed,
988 // stet, geted, getet, getkep, getksp, setkep, getid, kret, dcall, dret,
989 // dentsp, drestsp
991 def CLRE_0R : _F0R<(outs), (ins), "clre", [(int_xcore_clre)]>;
993 let Defs = [R11] in
994 def GETID_0R : _F0R<(outs), (ins),
995 "get r11, id",
996 [(set R11, (int_xcore_getid))]>;
998 def SSYNC_0r : _F0R<(outs), (ins),
999 "ssync",
1000 [(int_xcore_ssync)]>;
1002 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1,
1003 hasSideEffects = 1 in
1004 def WAITEU_0R : _F0R<(outs), (ins),
1005 "waiteu",
1006 [(brind (int_xcore_waitevent))]>;
1008 //===----------------------------------------------------------------------===//
1009 // Non-Instruction Patterns
1010 //===----------------------------------------------------------------------===//
1012 def : Pat<(XCoreBranchLink tglobaladdr:$addr), (BL_lu10 tglobaladdr:$addr)>;
1013 def : Pat<(XCoreBranchLink texternalsym:$addr), (BL_lu10 texternalsym:$addr)>;
1015 /// sext_inreg
1016 def : Pat<(sext_inreg GRRegs:$b, i1), (SEXT_rus GRRegs:$b, 1)>;
1017 def : Pat<(sext_inreg GRRegs:$b, i8), (SEXT_rus GRRegs:$b, 8)>;
1018 def : Pat<(sext_inreg GRRegs:$b, i16), (SEXT_rus GRRegs:$b, 16)>;
1020 /// loads
1021 def : Pat<(zextloadi8 (add GRRegs:$addr, GRRegs:$offset)),
1022 (LD8U_3r GRRegs:$addr, GRRegs:$offset)>;
1023 def : Pat<(zextloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>;
1025 def : Pat<(sextloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)),
1026 (LD16S_3r GRRegs:$addr, GRRegs:$offset)>;
1027 def : Pat<(sextloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>;
1029 def : Pat<(load (ldawf GRRegs:$addr, GRRegs:$offset)),
1030 (LDW_3r GRRegs:$addr, GRRegs:$offset)>;
1031 def : Pat<(load (add GRRegs:$addr, immUs4:$offset)),
1032 (LDW_2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;
1033 def : Pat<(load GRRegs:$addr), (LDW_2rus GRRegs:$addr, 0)>;
1035 /// anyext
1036 def : Pat<(extloadi8 (add GRRegs:$addr, GRRegs:$offset)),
1037 (LD8U_3r GRRegs:$addr, GRRegs:$offset)>;
1038 def : Pat<(extloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>;
1039 def : Pat<(extloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)),
1040 (LD16S_3r GRRegs:$addr, GRRegs:$offset)>;
1041 def : Pat<(extloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>;
1043 /// stores
1044 def : Pat<(truncstorei8 GRRegs:$val, (add GRRegs:$addr, GRRegs:$offset)),
1045 (ST8_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;
1046 def : Pat<(truncstorei8 GRRegs:$val, GRRegs:$addr),
1047 (ST8_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>;
1049 def : Pat<(truncstorei16 GRRegs:$val, (lda16f GRRegs:$addr, GRRegs:$offset)),
1050 (ST16_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;
1051 def : Pat<(truncstorei16 GRRegs:$val, GRRegs:$addr),
1052 (ST16_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>;
1054 def : Pat<(store GRRegs:$val, (ldawf GRRegs:$addr, GRRegs:$offset)),
1055 (STW_3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;
1056 def : Pat<(store GRRegs:$val, (add GRRegs:$addr, immUs4:$offset)),
1057 (STW_2rus GRRegs:$val, GRRegs:$addr, (div4_xform immUs4:$offset))>;
1058 def : Pat<(store GRRegs:$val, GRRegs:$addr),
1059 (STW_2rus GRRegs:$val, GRRegs:$addr, 0)>;
1061 /// cttz
1062 def : Pat<(cttz GRRegs:$src), (CLZ_l2r (BITREV_l2r GRRegs:$src))>;
1064 /// trap
1065 def : Pat<(trap), (ECALLF_1r (LDC_ru6 0))>;
1067 ///
1068 /// branch patterns
1069 ///
1071 // unconditional branch
1072 def : Pat<(br bb:$addr), (BRFU_lu6 bb:$addr)>;
1074 // direct match equal/notequal zero brcond
1075 def : Pat<(brcond (setne GRRegs:$lhs, 0), bb:$dst),
1076 (BRFT_lru6 GRRegs:$lhs, bb:$dst)>;
1077 def : Pat<(brcond (seteq GRRegs:$lhs, 0), bb:$dst),
1078 (BRFF_lru6 GRRegs:$lhs, bb:$dst)>;
1080 def : Pat<(brcond (setle GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1081 (BRFF_lru6 (LSS_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>;
1082 def : Pat<(brcond (setule GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1083 (BRFF_lru6 (LSU_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>;
1084 def : Pat<(brcond (setge GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1085 (BRFF_lru6 (LSS_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>;
1086 def : Pat<(brcond (setuge GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1087 (BRFF_lru6 (LSU_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>;
1088 def : Pat<(brcond (setne GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1089 (BRFF_lru6 (EQ_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>;
1090 def : Pat<(brcond (setne GRRegs:$lhs, immUs:$rhs), bb:$dst),
1091 (BRFF_lru6 (EQ_2rus GRRegs:$lhs, immUs:$rhs), bb:$dst)>;
1093 // generic brcond pattern
1094 def : Pat<(brcond GRRegs:$cond, bb:$addr), (BRFT_lru6 GRRegs:$cond, bb:$addr)>;
1097 ///
1098 /// Select patterns
1099 ///
1101 // direct match equal/notequal zero select
1102 def : Pat<(select (setne GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),
1103 (SELECT_CC GRRegs:$lhs, GRRegs:$T, GRRegs:$F)>;
1105 def : Pat<(select (seteq GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),
1106 (SELECT_CC GRRegs:$lhs, GRRegs:$F, GRRegs:$T)>;
1108 def : Pat<(select (setle GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1109 (SELECT_CC (LSS_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>;
1110 def : Pat<(select (setule GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1111 (SELECT_CC (LSU_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>;
1112 def : Pat<(select (setge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1113 (SELECT_CC (LSS_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
1114 def : Pat<(select (setuge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1115 (SELECT_CC (LSU_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
1116 def : Pat<(select (setne GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1117 (SELECT_CC (EQ_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
1118 def : Pat<(select (setne GRRegs:$lhs, immUs:$rhs), GRRegs:$T, GRRegs:$F),
1119 (SELECT_CC (EQ_2rus GRRegs:$lhs, immUs:$rhs), GRRegs:$F, GRRegs:$T)>;
1121 ///
1122 /// setcc patterns, only matched when none of the above brcond
1123 /// patterns match
1124 ///
1126 // setcc 2 register operands
1127 def : Pat<(setle GRRegs:$lhs, GRRegs:$rhs),
1128 (EQ_2rus (LSS_3r GRRegs:$rhs, GRRegs:$lhs), 0)>;
1129 def : Pat<(setule GRRegs:$lhs, GRRegs:$rhs),
1130 (EQ_2rus (LSU_3r GRRegs:$rhs, GRRegs:$lhs), 0)>;
1132 def : Pat<(setgt GRRegs:$lhs, GRRegs:$rhs),
1133 (LSS_3r GRRegs:$rhs, GRRegs:$lhs)>;
1134 def : Pat<(setugt GRRegs:$lhs, GRRegs:$rhs),
1135 (LSU_3r GRRegs:$rhs, GRRegs:$lhs)>;
1137 def : Pat<(setge GRRegs:$lhs, GRRegs:$rhs),
1138 (EQ_2rus (LSS_3r GRRegs:$lhs, GRRegs:$rhs), 0)>;
1139 def : Pat<(setuge GRRegs:$lhs, GRRegs:$rhs),
1140 (EQ_2rus (LSU_3r GRRegs:$lhs, GRRegs:$rhs), 0)>;
1142 def : Pat<(setlt GRRegs:$lhs, GRRegs:$rhs),
1143 (LSS_3r GRRegs:$lhs, GRRegs:$rhs)>;
1144 def : Pat<(setult GRRegs:$lhs, GRRegs:$rhs),
1145 (LSU_3r GRRegs:$lhs, GRRegs:$rhs)>;
1147 def : Pat<(setne GRRegs:$lhs, GRRegs:$rhs),
1148 (EQ_2rus (EQ_3r GRRegs:$lhs, GRRegs:$rhs), 0)>;
1150 def : Pat<(seteq GRRegs:$lhs, GRRegs:$rhs),
1151 (EQ_3r GRRegs:$lhs, GRRegs:$rhs)>;
1153 // setcc reg/imm operands
1154 def : Pat<(seteq GRRegs:$lhs, immUs:$rhs),
1155 (EQ_2rus GRRegs:$lhs, immUs:$rhs)>;
1156 def : Pat<(setne GRRegs:$lhs, immUs:$rhs),
1157 (EQ_2rus (EQ_2rus GRRegs:$lhs, immUs:$rhs), 0)>;
1159 // misc
1160 def : Pat<(add GRRegs:$addr, immUs4:$offset),
1161 (LDAWF_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;
1163 def : Pat<(sub GRRegs:$addr, immUs4:$offset),
1164 (LDAWB_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;
1166 def : Pat<(and GRRegs:$val, immMskBitp:$mask),
1167 (ZEXT_rus GRRegs:$val, (msksize_xform immMskBitp:$mask))>;
1169 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1170 def : Pat<(add GRRegs:$src1, immUsNeg:$src2),
1171 (SUB_2rus GRRegs:$src1, (neg_xform immUsNeg:$src2))>;
1173 def : Pat<(add GRRegs:$src1, immUs4Neg:$src2),
1174 (LDAWB_l2rus GRRegs:$src1, (div4neg_xform immUs4Neg:$src2))>;
1176 ///
1177 /// Some peepholes
1178 ///
1180 def : Pat<(mul GRRegs:$src, 3),
1181 (LDA16F_l3r GRRegs:$src, GRRegs:$src)>;
1183 def : Pat<(mul GRRegs:$src, 5),
1184 (LDAWF_l3r GRRegs:$src, GRRegs:$src)>;
1186 def : Pat<(mul GRRegs:$src, -3),
1187 (LDAWB_l3r GRRegs:$src, GRRegs:$src)>;
1189 // ashr X, 32 is equivalent to ashr X, 31 on the XCore.
1190 def : Pat<(sra GRRegs:$src, 31),
1191 (ASHR_l2rus GRRegs:$src, 32)>;
1193 def : Pat<(brcond (setlt GRRegs:$lhs, 0), bb:$dst),
1194 (BRFT_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>;
1196 // setge X, 0 is canonicalized to setgt X, -1
1197 def : Pat<(brcond (setgt GRRegs:$lhs, -1), bb:$dst),
1198 (BRFF_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>;
1200 def : Pat<(select (setlt GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),
1201 (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$T, GRRegs:$F)>;
1203 def : Pat<(select (setgt GRRegs:$lhs, -1), GRRegs:$T, GRRegs:$F),
1204 (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$F, GRRegs:$T)>;
1206 def : Pat<(setgt GRRegs:$lhs, -1),
1207 (EQ_2rus (ASHR_l2rus GRRegs:$lhs, 32), 0)>;
1209 def : Pat<(sra (shl GRRegs:$src, immBpwSubBitp:$imm), immBpwSubBitp:$imm),
1210 (SEXT_rus GRRegs:$src, (bpwsub_xform immBpwSubBitp:$imm))>;