1 //===-- XCoreInstrInfo.td - Target Description for XCore ---*- tablegen -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file describes the XCore instructions in TableGen format.
11 //
12 //===----------------------------------------------------------------------===//
14 // Uses of CP, DP are not currently reflected in the patterns, since
15 // having a physical register as an operand prevents loop hoisting and
16 // since the value of these registers never changes during the life of the
17 // function.
19 //===----------------------------------------------------------------------===//
20 // Instruction format superclass.
21 //===----------------------------------------------------------------------===//
23 include "XCoreInstrFormats.td"
25 //===----------------------------------------------------------------------===//
26 // XCore specific DAG Nodes.
27 //
29 // Call
30 def SDT_XCoreBranchLink : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
31 def XCoreBranchLink : SDNode<"XCoreISD::BL",SDT_XCoreBranchLink,
32 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
33 SDNPVariadic]>;
35 def XCoreRetsp : SDNode<"XCoreISD::RETSP", SDTBrind,
36 [SDNPHasChain, SDNPOptInGlue, SDNPMayLoad]>;
38 def SDT_XCoreBR_JT : SDTypeProfile<0, 2,
39 [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
41 def XCoreBR_JT : SDNode<"XCoreISD::BR_JT", SDT_XCoreBR_JT,
42 [SDNPHasChain]>;
44 def XCoreBR_JT32 : SDNode<"XCoreISD::BR_JT32", SDT_XCoreBR_JT,
45 [SDNPHasChain]>;
47 def SDT_XCoreAddress : SDTypeProfile<1, 1,
48 [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
50 def pcrelwrapper : SDNode<"XCoreISD::PCRelativeWrapper", SDT_XCoreAddress,
51 []>;
53 def dprelwrapper : SDNode<"XCoreISD::DPRelativeWrapper", SDT_XCoreAddress,
54 []>;
56 def cprelwrapper : SDNode<"XCoreISD::CPRelativeWrapper", SDT_XCoreAddress,
57 []>;
59 def SDT_XCoreStwsp : SDTypeProfile<0, 2, [SDTCisInt<1>]>;
60 def XCoreStwsp : SDNode<"XCoreISD::STWSP", SDT_XCoreStwsp,
61 [SDNPHasChain, SDNPMayStore]>;
63 // These are target-independent nodes, but have target-specific formats.
64 def SDT_XCoreCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
65 def SDT_XCoreCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
66 SDTCisVT<1, i32> ]>;
68 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_XCoreCallSeqStart,
69 [SDNPHasChain, SDNPOutGlue]>;
70 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_XCoreCallSeqEnd,
71 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
73 //===----------------------------------------------------------------------===//
74 // Instruction Pattern Stuff
75 //===----------------------------------------------------------------------===//
77 def div4_xform : SDNodeXForm<imm, [{
78 // Transformation function: imm/4
79 assert(N->getZExtValue() % 4 == 0);
80 return getI32Imm(N->getZExtValue()/4);
81 }]>;
83 def msksize_xform : SDNodeXForm<imm, [{
84 // Transformation function: get the size of a mask
85 assert(isMask_32(N->getZExtValue()));
86 // look for the first non-zero bit
87 return getI32Imm(32 - CountLeadingZeros_32(N->getZExtValue()));
88 }]>;
90 def neg_xform : SDNodeXForm<imm, [{
91 // Transformation function: -imm
92 uint32_t value = N->getZExtValue();
93 return getI32Imm(-value);
94 }]>;
96 def bpwsub_xform : SDNodeXForm<imm, [{
97 // Transformation function: 32-imm
98 uint32_t value = N->getZExtValue();
99 return getI32Imm(32-value);
100 }]>;
102 def div4neg_xform : SDNodeXForm<imm, [{
103 // Transformation function: -imm/4
104 uint32_t value = N->getZExtValue();
105 assert(-value % 4 == 0);
106 return getI32Imm(-value/4);
107 }]>;
109 def immUs4Neg : PatLeaf<(imm), [{
110 uint32_t value = (uint32_t)N->getZExtValue();
111 return (-value)%4 == 0 && (-value)/4 <= 11;
112 }]>;
114 def immUs4 : PatLeaf<(imm), [{
115 uint32_t value = (uint32_t)N->getZExtValue();
116 return value%4 == 0 && value/4 <= 11;
117 }]>;
119 def immUsNeg : PatLeaf<(imm), [{
120 return -((uint32_t)N->getZExtValue()) <= 11;
121 }]>;
123 def immUs : PatLeaf<(imm), [{
124 return (uint32_t)N->getZExtValue() <= 11;
125 }]>;
127 def immU6 : PatLeaf<(imm), [{
128 return (uint32_t)N->getZExtValue() < (1 << 6);
129 }]>;
131 def immU10 : PatLeaf<(imm), [{
132 return (uint32_t)N->getZExtValue() < (1 << 10);
133 }]>;
135 def immU16 : PatLeaf<(imm), [{
136 return (uint32_t)N->getZExtValue() < (1 << 16);
137 }]>;
139 def immU20 : PatLeaf<(imm), [{
140 return (uint32_t)N->getZExtValue() < (1 << 20);
141 }]>;
143 def immMskBitp : PatLeaf<(imm), [{ return immMskBitp(N); }]>;
145 def immBitp : PatLeaf<(imm), [{
146 uint32_t value = (uint32_t)N->getZExtValue();
147 return (value >= 1 && value <= 8)
148 || value == 16
149 || value == 24
150 || value == 32;
151 }]>;
153 def immBpwSubBitp : PatLeaf<(imm), [{
154 uint32_t value = (uint32_t)N->getZExtValue();
155 return (value >= 24 && value <= 31)
156 || value == 16
157 || value == 8
158 || value == 0;
159 }]>;
161 def lda16f : PatFrag<(ops node:$addr, node:$offset),
162 (add node:$addr, (shl node:$offset, 1))>;
163 def lda16b : PatFrag<(ops node:$addr, node:$offset),
164 (sub node:$addr, (shl node:$offset, 1))>;
165 def ldawf : PatFrag<(ops node:$addr, node:$offset),
166 (add node:$addr, (shl node:$offset, 2))>;
167 def ldawb : PatFrag<(ops node:$addr, node:$offset),
168 (sub node:$addr, (shl node:$offset, 2))>;
170 // Instruction operand types
171 def calltarget : Operand<i32>;
172 def brtarget : Operand<OtherVT>;
173 def pclabel : Operand<i32>;
175 // Addressing modes
176 def ADDRspii : ComplexPattern<i32, 2, "SelectADDRspii", [add, frameindex], []>;
177 def ADDRdpii : ComplexPattern<i32, 2, "SelectADDRdpii", [add, dprelwrapper],
178 []>;
179 def ADDRcpii : ComplexPattern<i32, 2, "SelectADDRcpii", [add, cprelwrapper],
180 []>;
182 // Address operands
183 def MEMii : Operand<i32> {
184 let PrintMethod = "printMemOperand";
185 let DecoderMethod = "DecodeMEMiiOperand";
186 let MIOperandInfo = (ops i32imm, i32imm);
187 }
189 // Jump tables.
190 def InlineJT : Operand<i32> {
191 let PrintMethod = "printInlineJT";
192 }
194 def InlineJT32 : Operand<i32> {
195 let PrintMethod = "printInlineJT32";
196 }
198 //===----------------------------------------------------------------------===//
199 // Instruction Class Templates
200 //===----------------------------------------------------------------------===//
202 // Three operand short
204 multiclass F3R_2RUS<bits<5> opc1, bits<5> opc2, string OpcStr, SDNode OpNode> {
205 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
206 !strconcat(OpcStr, " $dst, $b, $c"),
207 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
208 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
209 !strconcat(OpcStr, " $dst, $b, $c"),
210 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;
211 }
213 multiclass F3R_2RUS_np<bits<5> opc1, bits<5> opc2, string OpcStr> {
214 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
215 !strconcat(OpcStr, " $dst, $b, $c"), []>;
216 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
217 !strconcat(OpcStr, " $dst, $b, $c"), []>;
218 }
220 multiclass F3R_2RBITP<bits<5> opc1, bits<5> opc2, string OpcStr,
221 SDNode OpNode> {
222 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
223 !strconcat(OpcStr, " $dst, $b, $c"),
224 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
225 def _2rus : _F2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
226 !strconcat(OpcStr, " $dst, $b, $c"),
227 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
228 }
230 class F3R<bits<5> opc, string OpcStr, SDNode OpNode> :
231 _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
232 !strconcat(OpcStr, " $dst, $b, $c"),
233 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
235 class F3R_np<bits<5> opc, string OpcStr> :
236 _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
237 !strconcat(OpcStr, " $dst, $b, $c"), []>;
238 // Three operand long
240 /// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot.
241 multiclass FL3R_L2RUS<bits<9> opc1, bits<9> opc2, string OpcStr,
242 SDNode OpNode> {
243 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
244 !strconcat(OpcStr, " $dst, $b, $c"),
245 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
246 def _l2rus : _FL2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
247 !strconcat(OpcStr, " $dst, $b, $c"),
248 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;
249 }
251 /// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot.
252 multiclass FL3R_L2RBITP<bits<9> opc1, bits<9> opc2, string OpcStr,
253 SDNode OpNode> {
254 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
255 !strconcat(OpcStr, " $dst, $b, $c"),
256 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
257 def _l2rus : _FL2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
258 !strconcat(OpcStr, " $dst, $b, $c"),
259 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
260 }
262 class FL3R<bits<9> opc, string OpcStr, SDNode OpNode> :
263 _FL3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
264 !strconcat(OpcStr, " $dst, $b, $c"),
265 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
267 // Register - U6
268 // Operand register - U6
269 multiclass FRU6_LRU6_branch<bits<6> opc, string OpcStr> {
270 def _ru6: _FRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b),
271 !strconcat(OpcStr, " $a, $b"), []>;
272 def _lru6: _FLRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b),
273 !strconcat(OpcStr, " $a, $b"), []>;
274 }
276 multiclass FRU6_LRU6_backwards_branch<bits<6> opc, string OpcStr> {
277 def _ru6: _FRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b),
278 !strconcat(OpcStr, " $a, -$b"), []>;
279 def _lru6: _FLRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b),
280 !strconcat(OpcStr, " $a, -$b"), []>;
281 }
283 multiclass FRU6_LRU6_cp<bits<6> opc, string OpcStr> {
284 def _ru6: _FRU6<opc, (outs GRRegs:$a), (ins i32imm:$b),
285 !strconcat(OpcStr, " $a, cp[$b]"), []>;
286 def _lru6: _FLRU6<opc, (outs GRRegs:$a), (ins i32imm:$b),
287 !strconcat(OpcStr, " $a, cp[$b]"), []>;
288 }
290 // U6
291 multiclass FU6_LU6<bits<10> opc, string OpcStr, SDNode OpNode> {
292 def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"),
293 [(OpNode immU6:$a)]>;
294 def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"),
295 [(OpNode immU16:$a)]>;
296 }
298 multiclass FU6_LU6_int<bits<10> opc, string OpcStr, Intrinsic Int> {
299 def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"),
300 [(Int immU6:$a)]>;
301 def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"),
302 [(Int immU16:$a)]>;
303 }
305 multiclass FU6_LU6_np<bits<10> opc, string OpcStr> {
306 def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), []>;
307 def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), []>;
308 }
310 // Two operand short
312 class F2R_np<bits<6> opc, string OpcStr> :
313 _F2R<opc, (outs GRRegs:$dst), (ins GRRegs:$b),
314 !strconcat(OpcStr, " $dst, $b"), []>;
316 // Two operand long
318 //===----------------------------------------------------------------------===//
319 // Pseudo Instructions
320 //===----------------------------------------------------------------------===//
322 let Defs = [SP], Uses = [SP] in {
323 def ADJCALLSTACKDOWN : PseudoInstXCore<(outs), (ins i32imm:$amt),
324 "# ADJCALLSTACKDOWN $amt",
325 [(callseq_start timm:$amt)]>;
326 def ADJCALLSTACKUP : PseudoInstXCore<(outs), (ins i32imm:$amt1, i32imm:$amt2),
327 "# ADJCALLSTACKUP $amt1",
328 [(callseq_end timm:$amt1, timm:$amt2)]>;
329 }
331 def LDWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr),
332 "# LDWFI $dst, $addr",
333 [(set GRRegs:$dst, (load ADDRspii:$addr))]>;
335 def LDAWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr),
336 "# LDAWFI $dst, $addr",
337 [(set GRRegs:$dst, ADDRspii:$addr)]>;
339 def STWFI : PseudoInstXCore<(outs), (ins GRRegs:$src, MEMii:$addr),
340 "# STWFI $src, $addr",
341 [(store GRRegs:$src, ADDRspii:$addr)]>;
343 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
344 // instruction selection into a branch sequence.
345 let usesCustomInserter = 1 in {
346 def SELECT_CC : PseudoInstXCore<(outs GRRegs:$dst),
347 (ins GRRegs:$cond, GRRegs:$T, GRRegs:$F),
348 "# SELECT_CC PSEUDO!",
349 [(set GRRegs:$dst,
350 (select GRRegs:$cond, GRRegs:$T, GRRegs:$F))]>;
351 }
353 //===----------------------------------------------------------------------===//
354 // Instructions
355 //===----------------------------------------------------------------------===//
357 // Three operand short
358 defm ADD : F3R_2RUS<0b00010, 0b10010, "add", add>;
359 defm SUB : F3R_2RUS<0b00011, 0b10011, "sub", sub>;
360 let neverHasSideEffects = 1 in {
361 defm EQ : F3R_2RUS_np<0b00110, 0b10110, "eq">;
362 def LSS_3r : F3R_np<0b11000, "lss">;
363 def LSU_3r : F3R_np<0b11001, "lsu">;
364 }
365 def AND_3r : F3R<0b00111, "and", and>;
366 def OR_3r : F3R<0b01000, "or", or>;
368 let mayLoad=1 in {
369 def LDW_3r : _F3R<0b01001, (outs GRRegs:$dst),
370 (ins GRRegs:$addr, GRRegs:$offset),
371 "ldw $dst, $addr[$offset]", []>;
373 def LDW_2rus : _F2RUS<0b00001, (outs GRRegs:$dst),
374 (ins GRRegs:$addr, i32imm:$offset),
375 "ldw $dst, $addr[$offset]", []>;
377 def LD16S_3r : _F3R<0b10000, (outs GRRegs:$dst),
378 (ins GRRegs:$addr, GRRegs:$offset),
379 "ld16s $dst, $addr[$offset]", []>;
381 def LD8U_3r : _F3R<0b10001, (outs GRRegs:$dst),
382 (ins GRRegs:$addr, GRRegs:$offset),
383 "ld8u $dst, $addr[$offset]", []>;
384 }
386 let mayStore=1 in {
387 def STW_3r : _FL3R<0b000001100, (outs),
388 (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
389 "stw $val, $addr[$offset]", []>;
391 def STW_2rus : _F2RUS<0b0000, (outs),
392 (ins GRRegs:$val, GRRegs:$addr, i32imm:$offset),
393 "stw $val, $addr[$offset]", []>;
394 }
396 defm SHL : F3R_2RBITP<0b00100, 0b10100, "shl", shl>;
397 defm SHR : F3R_2RBITP<0b00101, 0b10101, "shr", srl>;
398 // TODO tsetr
400 // Three operand long
401 def LDAWF_l3r : _FL3R<0b000111100, (outs GRRegs:$dst),
402 (ins GRRegs:$addr, GRRegs:$offset),
403 "ldaw $dst, $addr[$offset]",
404 [(set GRRegs:$dst,
405 (ldawf GRRegs:$addr, GRRegs:$offset))]>;
407 let neverHasSideEffects = 1 in
408 def LDAWF_l2rus : _FL2RUS<0b100111100, (outs GRRegs:$dst),
409 (ins GRRegs:$addr, i32imm:$offset),
410 "ldaw $dst, $addr[$offset]", []>;
412 def LDAWB_l3r : _FL3R<0b001001100, (outs GRRegs:$dst),
413 (ins GRRegs:$addr, GRRegs:$offset),
414 "ldaw $dst, $addr[-$offset]",
415 [(set GRRegs:$dst,
416 (ldawb GRRegs:$addr, GRRegs:$offset))]>;
418 let neverHasSideEffects = 1 in
419 def LDAWB_l2rus : _FL2RUS<0b101001100, (outs GRRegs:$dst),
420 (ins GRRegs:$addr, i32imm:$offset),
421 "ldaw $dst, $addr[-$offset]", []>;
423 def LDA16F_l3r : _FL3R<0b001011100, (outs GRRegs:$dst),
424 (ins GRRegs:$addr, GRRegs:$offset),
425 "lda16 $dst, $addr[$offset]",
426 [(set GRRegs:$dst,
427 (lda16f GRRegs:$addr, GRRegs:$offset))]>;
429 def LDA16B_l3r : _FL3R<0b001101100, (outs GRRegs:$dst),
430 (ins GRRegs:$addr, GRRegs:$offset),
431 "lda16 $dst, $addr[-$offset]",
432 [(set GRRegs:$dst,
433 (lda16b GRRegs:$addr, GRRegs:$offset))]>;
435 def MUL_l3r : FL3R<0b001111100, "mul", mul>;
436 // Instructions which may trap are marked as side effecting.
437 let hasSideEffects = 1 in {
438 def DIVS_l3r : FL3R<0b010001100, "divs", sdiv>;
439 def DIVU_l3r : FL3R<0b010011100, "divu", udiv>;
440 def REMS_l3r : FL3R<0b110001100, "rems", srem>;
441 def REMU_l3r : FL3R<0b110011100, "remu", urem>;
442 }
443 def XOR_l3r : FL3R<0b000011100, "xor", xor>;
444 defm ASHR : FL3R_L2RBITP<0b000101100, 0b100101100, "ashr", sra>;
446 let Constraints = "$src1 = $dst" in
447 def CRC_l3r : _FL3RSrcDst<0b101011100, (outs GRRegs:$dst),
448 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
449 "crc32 $dst, $src2, $src3",
450 [(set GRRegs:$dst,
451 (int_xcore_crc32 GRRegs:$src1, GRRegs:$src2,
452 GRRegs:$src3))]>;
454 // TODO inpw, outpw
455 let mayStore=1 in {
456 def ST16_l3r : _FL3R<0b100001100, (outs),
457 (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
458 "st16 $val, $addr[$offset]", []>;
460 def ST8_l3r : _FL3R<0b100011100, (outs),
461 (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
462 "st8 $val, $addr[$offset]", []>;
463 }
465 // Four operand long
466 let Constraints = "$src1 = $dst1,$src2 = $dst2" in {
467 def MACCU_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2),
468 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3,
469 GRRegs:$src4),
470 "maccu $dst1, $dst2, $src3, $src4",
471 []>;
473 def MACCS_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2),
474 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3,
475 GRRegs:$src4),
476 "maccs $dst1, $dst2, $src3, $src4",
477 []>;
478 }
480 let Constraints = "$src1 = $dst1" in
481 def CRC8_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2),
482 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
483 "crc8 $dst1, $dst2, $src2, $src3",
484 []>;
486 // Five operand long
488 def LADD_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2),
489 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
490 "ladd $dst1, $dst2, $src1, $src2, $src3",
491 []>;
493 def LSUB_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2),
494 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
495 "lsub $dst1, $dst2, $src1, $src2, $src3",
496 []>;
498 def LDIV_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2),
499 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
500 "ldiv $dst1, $dst2, $src1, $src2, $src3",
501 []>;
503 // Six operand long
505 def LMUL_l6r : _L6R<(outs GRRegs:$dst1, GRRegs:$dst2),
506 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3,
507 GRRegs:$src4),
508 "lmul $dst1, $dst2, $src1, $src2, $src3, $src4",
509 []>;
511 // Register - U6
513 //let Uses = [DP] in ...
514 let neverHasSideEffects = 1, isReMaterializable = 1 in
515 def LDAWDP_ru6: _FRU6<0b011000, (outs GRRegs:$a), (ins MEMii:$b),
516 "ldaw $a, dp[$b]", []>;
518 let isReMaterializable = 1 in
519 def LDAWDP_lru6: _FLRU6<0b011000, (outs GRRegs:$a), (ins MEMii:$b),
520 "ldaw $a, dp[$b]",
521 [(set GRRegs:$a, ADDRdpii:$b)]>;
523 let mayLoad=1 in
524 def LDWDP_ru6: _FRU6<0b010110, (outs GRRegs:$a), (ins MEMii:$b),
525 "ldw $a, dp[$b]", []>;
527 def LDWDP_lru6: _FLRU6<0b010110, (outs GRRegs:$a), (ins MEMii:$b),
528 "ldw $a, dp[$b]",
529 [(set GRRegs:$a, (load ADDRdpii:$b))]>;
531 let mayStore=1 in
532 def STWDP_ru6 : _FRU6<0b010100, (outs), (ins GRRegs:$a, MEMii:$b),
533 "stw $a, dp[$b]", []>;
535 def STWDP_lru6 : _FLRU6<0b010100, (outs), (ins GRRegs:$a, MEMii:$b),
536 "stw $a, dp[$b]",
537 [(store GRRegs:$a, ADDRdpii:$b)]>;
539 //let Uses = [CP] in ..
540 let mayLoad = 1, isReMaterializable = 1, neverHasSideEffects = 1 in
541 defm LDWCP : FRU6_LRU6_cp<0b011011, "ldw">;
543 let Uses = [SP] in {
544 let mayStore=1 in {
545 def STWSP_ru6 : _FRU6<0b010101, (outs), (ins GRRegs:$a, i32imm:$b),
546 "stw $a, sp[$b]",
547 [(XCoreStwsp GRRegs:$a, immU6:$b)]>;
549 def STWSP_lru6 : _FLRU6<0b010101, (outs), (ins GRRegs:$a, i32imm:$b),
550 "stw $a, sp[$b]",
551 [(XCoreStwsp GRRegs:$a, immU16:$b)]>;
552 }
554 let mayLoad=1 in {
555 def LDWSP_ru6 : _FRU6<0b010111, (outs GRRegs:$a), (ins i32imm:$b),
556 "ldw $a, sp[$b]", []>;
558 def LDWSP_lru6 : _FLRU6<0b010111, (outs GRRegs:$a), (ins i32imm:$b),
559 "ldw $a, sp[$b]", []>;
560 }
562 let neverHasSideEffects = 1 in {
563 def LDAWSP_ru6 : _FRU6<0b011001, (outs GRRegs:$a), (ins i32imm:$b),
564 "ldaw $a, sp[$b]", []>;
566 def LDAWSP_lru6 : _FLRU6<0b011001, (outs GRRegs:$a), (ins i32imm:$b),
567 "ldaw $a, sp[$b]", []>;
569 let isCodeGenOnly = 1 in
570 def LDAWSP_ru6_RRegs : _FRU6<0b011001, (outs RRegs:$a), (ins i32imm:$b),
571 "ldaw $a, sp[$b]", []>;
573 let isCodeGenOnly = 1 in
574 def LDAWSP_lru6_RRegs : _FLRU6<0b011001, (outs RRegs:$a), (ins i32imm:$b),
575 "ldaw $a, sp[$b]", []>;
576 }
577 }
579 let isReMaterializable = 1 in {
580 def LDC_ru6 : _FRU6<0b011010, (outs GRRegs:$a), (ins i32imm:$b),
581 "ldc $a, $b", [(set GRRegs:$a, immU6:$b)]>;
583 def LDC_lru6 : _FLRU6<0b011010, (outs GRRegs:$a), (ins i32imm:$b),
584 "ldc $a, $b", [(set GRRegs:$a, immU16:$b)]>;
585 }
587 def SETC_ru6 : _FRU6<0b111010, (outs), (ins GRRegs:$a, i32imm:$b),
588 "setc res[$a], $b",
589 [(int_xcore_setc GRRegs:$a, immU6:$b)]>;
591 def SETC_lru6 : _FLRU6<0b111010, (outs), (ins GRRegs:$a, i32imm:$b),
592 "setc res[$a], $b",
593 [(int_xcore_setc GRRegs:$a, immU16:$b)]>;
595 // Operand register - U6
596 let isBranch = 1, isTerminator = 1 in {
597 defm BRFT: FRU6_LRU6_branch<0b011100, "bt">;
598 defm BRBT: FRU6_LRU6_backwards_branch<0b011101, "bt">;
599 defm BRFF: FRU6_LRU6_branch<0b011110, "bf">;
600 defm BRBF: FRU6_LRU6_backwards_branch<0b011111, "bf">;
601 }
603 // U6
604 let Defs = [SP], Uses = [SP] in {
605 let neverHasSideEffects = 1 in
606 defm EXTSP : FU6_LU6_np<0b0111011110, "extsp">;
607 let mayStore = 1 in
608 defm ENTSP : FU6_LU6_np<0b0111011101, "entsp">;
610 let isReturn = 1, isTerminator = 1, mayLoad = 1, isBarrier = 1 in {
611 defm RETSP : FU6_LU6<0b0111011111, "retsp", XCoreRetsp>;
612 }
613 }
615 // TODO extdp, kentsp, krestsp, blat
616 // getsr, kalli
617 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
618 def BRBU_u6 : _FU6<0b0111011100, (outs), (ins brtarget:$a), "bu -$a", []>;
620 def BRBU_lu6 : _FLU6<0b0111011100, (outs), (ins brtarget:$a), "bu -$a", []>;
622 def BRFU_u6 : _FU6<0b0111001100, (outs), (ins brtarget:$a), "bu $a", []>;
624 def BRFU_lu6 : _FLU6<0b0111001100, (outs), (ins brtarget:$a), "bu $a", []>;
625 }
627 //let Uses = [CP] in ...
628 let Defs = [R11], neverHasSideEffects = 1, isReMaterializable = 1 in
629 def LDAWCP_u6: _FU6<0b0111111101, (outs), (ins MEMii:$a), "ldaw r11, cp[$a]",
630 []>;
632 let Defs = [R11], isReMaterializable = 1 in
633 def LDAWCP_lu6: _FLU6<0b0111111101, (outs), (ins MEMii:$a), "ldaw r11, cp[$a]",
634 [(set R11, ADDRcpii:$a)]>;
636 defm SETSR : FU6_LU6_int<0b0111101101, "setsr", int_xcore_setsr>;
638 defm CLRSR : FU6_LU6_int<0b0111101100, "clrsr", int_xcore_clrsr>;
640 // setsr may cause a branch if it is used to enable events. clrsr may
641 // branch if it is executed while events are enabled.
642 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1,
643 isCodeGenOnly = 1 in {
644 defm SETSR_branch : FU6_LU6_np<0b0111101101, "setsr">;
645 defm CLRSR_branch : FU6_LU6_np<0b0111101100, "clrsr">;
646 }
648 // U10
649 // TODO ldwcpl, blacp
651 let Defs = [R11], isReMaterializable = 1, neverHasSideEffects = 1 in
652 def LDAP_u10 : _FU10<
653 (outs),
654 (ins i32imm:$addr),
655 "ldap r11, $addr",
656 []>;
658 let Defs = [R11], isReMaterializable = 1 in
659 def LDAP_lu10 : _FLU10<
660 (outs),
661 (ins i32imm:$addr),
662 "ldap r11, $addr",
663 [(set R11, (pcrelwrapper tglobaladdr:$addr))]>;
665 let Defs = [R11], isReMaterializable = 1 in
666 def LDAP_lu10_ba : _FLU10<(outs),
667 (ins i32imm:$addr),
668 "ldap r11, $addr",
669 [(set R11, (pcrelwrapper tblockaddress:$addr))]>;
671 let isCall=1,
672 // All calls clobber the link register and the non-callee-saved registers:
673 Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in {
674 def BL_u10 : _FU10<
675 (outs), (ins calltarget:$target),
676 "bl $target",
677 [(XCoreBranchLink immU10:$target)]>;
679 def BL_lu10 : _FLU10<
680 (outs), (ins calltarget:$target),
681 "bl $target",
682 [(XCoreBranchLink immU20:$target)]>;
683 }
685 // Two operand short
686 // TODO eet, eef, tsetmr
687 def NOT : _F2R<0b100010, (outs GRRegs:$dst), (ins GRRegs:$b),
688 "not $dst, $b", [(set GRRegs:$dst, (not GRRegs:$b))]>;
690 def NEG : _F2R<0b100100, (outs GRRegs:$dst), (ins GRRegs:$b),
691 "neg $dst, $b", [(set GRRegs:$dst, (ineg GRRegs:$b))]>;
693 let Constraints = "$src1 = $dst" in {
694 def SEXT_rus :
695 _FRUSSrcDstBitp<0b001101, (outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
696 "sext $dst, $src2",
697 [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1,
698 immBitp:$src2))]>;
700 def SEXT_2r :
701 _F2RSrcDst<0b001100, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
702 "sext $dst, $src2",
703 [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1, GRRegs:$src2))]>;
705 def ZEXT_rus :
706 _FRUSSrcDstBitp<0b010001, (outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
707 "zext $dst, $src2",
708 [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1,
709 immBitp:$src2))]>;
711 def ZEXT_2r :
712 _F2RSrcDst<0b010000, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
713 "zext $dst, $src2",
714 [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1, GRRegs:$src2))]>;
716 def ANDNOT_2r :
717 _F2RSrcDst<0b001010, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
718 "andnot $dst, $src2",
719 [(set GRRegs:$dst, (and GRRegs:$src1, (not GRRegs:$src2)))]>;
720 }
722 let isReMaterializable = 1, neverHasSideEffects = 1 in
723 def MKMSK_rus : _FRUSBitp<0b101001, (outs GRRegs:$dst), (ins i32imm:$size),
724 "mkmsk $dst, $size", []>;
726 def MKMSK_2r : _F2R<0b101000, (outs GRRegs:$dst), (ins GRRegs:$size),
727 "mkmsk $dst, $size",
728 [(set GRRegs:$dst, (add (shl 1, GRRegs:$size), -1))]>;
730 def GETR_rus : _FRUS<0b100000, (outs GRRegs:$dst), (ins i32imm:$type),
731 "getr $dst, $type",
732 [(set GRRegs:$dst, (int_xcore_getr immUs:$type))]>;
734 def GETTS_2r : _F2R<0b001110, (outs GRRegs:$dst), (ins GRRegs:$r),
735 "getts $dst, res[$r]",
736 [(set GRRegs:$dst, (int_xcore_getts GRRegs:$r))]>;
738 def SETPT_2r : _FR2R<0b001111, (outs), (ins GRRegs:$r, GRRegs:$val),
739 "setpt res[$r], $val",
740 [(int_xcore_setpt GRRegs:$r, GRRegs:$val)]>;
742 def OUTCT_2r : _F2R<0b010010, (outs), (ins GRRegs:$r, GRRegs:$val),
743 "outct res[$r], $val",
744 [(int_xcore_outct GRRegs:$r, GRRegs:$val)]>;
746 def OUTCT_rus : _FRUS<0b010011, (outs), (ins GRRegs:$r, i32imm:$val),
747 "outct res[$r], $val",
748 [(int_xcore_outct GRRegs:$r, immUs:$val)]>;
750 def OUTT_2r : _FR2R<0b000011, (outs), (ins GRRegs:$r, GRRegs:$val),
751 "outt res[$r], $val",
752 [(int_xcore_outt GRRegs:$r, GRRegs:$val)]>;
754 def OUT_2r : _FR2R<0b101010, (outs), (ins GRRegs:$r, GRRegs:$val),
755 "out res[$r], $val",
756 [(int_xcore_out GRRegs:$r, GRRegs:$val)]>;
758 let Constraints = "$src = $dst" in
759 def OUTSHR_2r :
760 _F2RSrcDst<0b101011, (outs GRRegs:$dst), (ins GRRegs:$src, GRRegs:$r),
761 "outshr res[$r], $src",
762 [(set GRRegs:$dst, (int_xcore_outshr GRRegs:$r, GRRegs:$src))]>;
764 def INCT_2r : _F2R<0b100001, (outs GRRegs:$dst), (ins GRRegs:$r),
765 "inct $dst, res[$r]",
766 [(set GRRegs:$dst, (int_xcore_inct GRRegs:$r))]>;
768 def INT_2r : _F2R<0b100011, (outs GRRegs:$dst), (ins GRRegs:$r),
769 "int $dst, res[$r]",
770 [(set GRRegs:$dst, (int_xcore_int GRRegs:$r))]>;
772 def IN_2r : _F2R<0b101100, (outs GRRegs:$dst), (ins GRRegs:$r),
773 "in $dst, res[$r]",
774 [(set GRRegs:$dst, (int_xcore_in GRRegs:$r))]>;
776 let Constraints = "$src = $dst" in
777 def INSHR_2r :
778 _F2RSrcDst<0b101101, (outs GRRegs:$dst), (ins GRRegs:$src, GRRegs:$r),
779 "inshr $dst, res[$r]",
780 [(set GRRegs:$dst, (int_xcore_inshr GRRegs:$r, GRRegs:$src))]>;
782 def CHKCT_2r : _F2R<0b110010, (outs), (ins GRRegs:$r, GRRegs:$val),
783 "chkct res[$r], $val",
784 [(int_xcore_chkct GRRegs:$r, GRRegs:$val)]>;
786 def CHKCT_rus : _FRUSBitp<0b110011, (outs), (ins GRRegs:$r, i32imm:$val),
787 "chkct res[$r], $val",
788 [(int_xcore_chkct GRRegs:$r, immUs:$val)]>;
790 def TESTCT_2r : _F2R<0b101111, (outs GRRegs:$dst), (ins GRRegs:$src),
791 "testct $dst, res[$src]",
792 [(set GRRegs:$dst, (int_xcore_testct GRRegs:$src))]>;
794 def TESTWCT_2r : _F2R<0b110001, (outs GRRegs:$dst), (ins GRRegs:$src),
795 "testwct $dst, res[$src]",
796 [(set GRRegs:$dst, (int_xcore_testwct GRRegs:$src))]>;
798 def SETD_2r : _FR2R<0b000101, (outs), (ins GRRegs:$r, GRRegs:$val),
799 "setd res[$r], $val",
800 [(int_xcore_setd GRRegs:$r, GRRegs:$val)]>;
802 def SETPSC_l2r : _FR2R<0b110000, (outs), (ins GRRegs:$src1, GRRegs:$src2),
803 "setpsc res[$src1], $src2",
804 [(int_xcore_setpsc GRRegs:$src1, GRRegs:$src2)]>;
806 def GETST_2r : _F2R<0b000001, (outs GRRegs:$dst), (ins GRRegs:$r),
807 "getst $dst, res[$r]",
808 [(set GRRegs:$dst, (int_xcore_getst GRRegs:$r))]>;
810 def INITSP_2r : _F2R<0b000100, (outs), (ins GRRegs:$src, GRRegs:$t),
811 "init t[$t]:sp, $src",
812 [(int_xcore_initsp GRRegs:$t, GRRegs:$src)]>;
814 def INITPC_2r : _F2R<0b000000, (outs), (ins GRRegs:$src, GRRegs:$t),
815 "init t[$t]:pc, $src",
816 [(int_xcore_initpc GRRegs:$t, GRRegs:$src)]>;
818 def INITCP_2r : _F2R<0b000110, (outs), (ins GRRegs:$src, GRRegs:$t),
819 "init t[$t]:cp, $src",
820 [(int_xcore_initcp GRRegs:$t, GRRegs:$src)]>;
822 def INITDP_2r : _F2R<0b000010, (outs), (ins GRRegs:$src, GRRegs:$t),
823 "init t[$t]:dp, $src",
824 [(int_xcore_initdp GRRegs:$t, GRRegs:$src)]>;
826 def PEEK_2r : _F2R<0b101110, (outs GRRegs:$dst), (ins GRRegs:$src),
827 "peek $dst, res[$src]",
828 [(set GRRegs:$dst, (int_xcore_peek GRRegs:$src))]>;
830 def ENDIN_2r : _F2R<0b100101, (outs GRRegs:$dst), (ins GRRegs:$src),
831 "endin $dst, res[$src]",
832 [(set GRRegs:$dst, (int_xcore_endin GRRegs:$src))]>;
834 // Two operand long
835 // getd, testlcl
836 def BITREV_l2r : _FL2R<0b0000011000, (outs GRRegs:$dst), (ins GRRegs:$src),
837 "bitrev $dst, $src",
838 [(set GRRegs:$dst, (int_xcore_bitrev GRRegs:$src))]>;
840 def BYTEREV_l2r : _FL2R<0b0000011001, (outs GRRegs:$dst), (ins GRRegs:$src),
841 "byterev $dst, $src",
842 [(set GRRegs:$dst, (bswap GRRegs:$src))]>;
844 def CLZ_l2r : _FL2R<0b000111000, (outs GRRegs:$dst), (ins GRRegs:$src),
845 "clz $dst, $src",
846 [(set GRRegs:$dst, (ctlz GRRegs:$src))]>;
848 def SETC_l2r : _FL2R<0b0010111001, (outs), (ins GRRegs:$r, GRRegs:$val),
849 "setc res[$r], $val",
850 [(int_xcore_setc GRRegs:$r, GRRegs:$val)]>;
852 def SETTW_l2r : _FLR2R<0b0010011001, (outs), (ins GRRegs:$r, GRRegs:$val),
853 "settw res[$r], $val",
854 [(int_xcore_settw GRRegs:$r, GRRegs:$val)]>;
856 def GETPS_l2r : _FL2R<0b0001011001, (outs GRRegs:$dst), (ins GRRegs:$src),
857 "get $dst, ps[$src]",
858 [(set GRRegs:$dst, (int_xcore_getps GRRegs:$src))]>;
860 def SETPS_l2r : _FLR2R<0b0001111000, (outs), (ins GRRegs:$src1, GRRegs:$src2),
861 "set ps[$src1], $src2",
862 [(int_xcore_setps GRRegs:$src1, GRRegs:$src2)]>;
864 def INITLR_l2r : _FL2R<0b0001011000, (outs), (ins GRRegs:$src, GRRegs:$t),
865 "init t[$t]:lr, $src",
866 [(int_xcore_initlr GRRegs:$t, GRRegs:$src)]>;
868 def SETCLK_l2r : _FLR2R<0b0000111001, (outs), (ins GRRegs:$src1, GRRegs:$src2),
869 "setclk res[$src1], $src2",
870 [(int_xcore_setclk GRRegs:$src1, GRRegs:$src2)]>;
872 def SETRDY_l2r : _FLR2R<0b0010111000, (outs), (ins GRRegs:$src1, GRRegs:$src2),
873 "setrdy res[$src1], $src2",
874 [(int_xcore_setrdy GRRegs:$src1, GRRegs:$src2)]>;
876 // One operand short
877 // TODO edu, eeu, waitet, waitef, tstart, clrtp
878 // setdp, setcp, setev, kcall
879 // dgetreg
880 def MSYNC_1r : _F1R<0b000111, (outs), (ins GRRegs:$a),
881 "msync res[$a]",
882 [(int_xcore_msync GRRegs:$a)]>;
883 def MJOIN_1r : _F1R<0b000101, (outs), (ins GRRegs:$a),
884 "mjoin res[$a]",
885 [(int_xcore_mjoin GRRegs:$a)]>;
887 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
888 def BAU_1r : _F1R<0b001001, (outs), (ins GRRegs:$a),
889 "bau $a",
890 [(brind GRRegs:$a)]>;
892 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
893 def BR_JT : PseudoInstXCore<(outs), (ins InlineJT:$t, GRRegs:$i),
894 "bru $i\n$t",
895 [(XCoreBR_JT tjumptable:$t, GRRegs:$i)]>;
897 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
898 def BR_JT32 : PseudoInstXCore<(outs), (ins InlineJT32:$t, GRRegs:$i),
899 "bru $i\n$t",
900 [(XCoreBR_JT32 tjumptable:$t, GRRegs:$i)]>;
902 let Defs=[SP], neverHasSideEffects=1 in
903 def SETSP_1r : _F1R<0b001011, (outs), (ins GRRegs:$a),
904 "set sp, $a",
905 []>;
907 let hasCtrlDep = 1 in
908 def ECALLT_1r : _F1R<0b010011, (outs), (ins GRRegs:$a),
909 "ecallt $a",
910 []>;
912 let hasCtrlDep = 1 in
913 def ECALLF_1r : _F1R<0b010010, (outs), (ins GRRegs:$a),
914 "ecallf $a",
915 []>;
917 let isCall=1,
918 // All calls clobber the link register and the non-callee-saved registers:
919 Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in {
920 def BLA_1r : _F1R<0b001000, (outs), (ins GRRegs:$a),
921 "bla $a",
922 [(XCoreBranchLink GRRegs:$a)]>;
923 }
925 def SYNCR_1r : _F1R<0b100001, (outs), (ins GRRegs:$a),
926 "syncr res[$a]",
927 [(int_xcore_syncr GRRegs:$a)]>;
929 def FREER_1r : _F1R<0b000100, (outs), (ins GRRegs:$a),
930 "freer res[$a]",
931 [(int_xcore_freer GRRegs:$a)]>;
933 let Uses=[R11] in {
934 def SETV_1r : _F1R<0b010001, (outs), (ins GRRegs:$a),
935 "setv res[$a], r11",
936 [(int_xcore_setv GRRegs:$a, R11)]>;
938 def SETEV_1r : _F1R<0b001111, (outs), (ins GRRegs:$a),
939 "setev res[$a], r11",
940 [(int_xcore_setev GRRegs:$a, R11)]>;
941 }
943 def EEU_1r : _F1R<0b000001, (outs), (ins GRRegs:$a),
944 "eeu res[$a]",
945 [(int_xcore_eeu GRRegs:$a)]>;
947 // Zero operand short
948 // TODO freet, ldspc, stspc, ldssr, stssr, ldsed, stsed,
949 // stet, getkep, getksp, setkep, getid, kret, dcall, dret,
950 // dentsp, drestsp
952 def CLRE_0R : _F0R<0b0000001101, (outs), (ins), "clre", [(int_xcore_clre)]>;
954 let Defs = [R11] in {
955 def GETID_0R : _F0R<0b0001001110, (outs), (ins),
956 "get r11, id",
957 [(set R11, (int_xcore_getid))]>;
959 def GETED_0R : _F0R<0b0000111110, (outs), (ins),
960 "get r11, ed",
961 [(set R11, (int_xcore_geted))]>;
963 def GETET_0R : _F0R<0b0000111111, (outs), (ins),
964 "get r11, et",
965 [(set R11, (int_xcore_getet))]>;
966 }
968 def SSYNC_0r : _F0R<0b0000001110, (outs), (ins),
969 "ssync",
970 [(int_xcore_ssync)]>;
972 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1,
973 hasSideEffects = 1 in
974 def WAITEU_0R : _F0R<0b0000001100, (outs), (ins),
975 "waiteu",
976 [(brind (int_xcore_waitevent))]>;
978 //===----------------------------------------------------------------------===//
979 // Non-Instruction Patterns
980 //===----------------------------------------------------------------------===//
982 def : Pat<(XCoreBranchLink tglobaladdr:$addr), (BL_lu10 tglobaladdr:$addr)>;
983 def : Pat<(XCoreBranchLink texternalsym:$addr), (BL_lu10 texternalsym:$addr)>;
985 /// sext_inreg
986 def : Pat<(sext_inreg GRRegs:$b, i1), (SEXT_rus GRRegs:$b, 1)>;
987 def : Pat<(sext_inreg GRRegs:$b, i8), (SEXT_rus GRRegs:$b, 8)>;
988 def : Pat<(sext_inreg GRRegs:$b, i16), (SEXT_rus GRRegs:$b, 16)>;
990 /// loads
991 def : Pat<(zextloadi8 (add GRRegs:$addr, GRRegs:$offset)),
992 (LD8U_3r GRRegs:$addr, GRRegs:$offset)>;
993 def : Pat<(zextloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>;
995 def : Pat<(sextloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)),
996 (LD16S_3r GRRegs:$addr, GRRegs:$offset)>;
997 def : Pat<(sextloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>;
999 def : Pat<(load (ldawf GRRegs:$addr, GRRegs:$offset)),
1000 (LDW_3r GRRegs:$addr, GRRegs:$offset)>;
1001 def : Pat<(load (add GRRegs:$addr, immUs4:$offset)),
1002 (LDW_2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;
1003 def : Pat<(load GRRegs:$addr), (LDW_2rus GRRegs:$addr, 0)>;
1005 /// anyext
1006 def : Pat<(extloadi8 (add GRRegs:$addr, GRRegs:$offset)),
1007 (LD8U_3r GRRegs:$addr, GRRegs:$offset)>;
1008 def : Pat<(extloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>;
1009 def : Pat<(extloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)),
1010 (LD16S_3r GRRegs:$addr, GRRegs:$offset)>;
1011 def : Pat<(extloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>;
1013 /// stores
1014 def : Pat<(truncstorei8 GRRegs:$val, (add GRRegs:$addr, GRRegs:$offset)),
1015 (ST8_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;
1016 def : Pat<(truncstorei8 GRRegs:$val, GRRegs:$addr),
1017 (ST8_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>;
1019 def : Pat<(truncstorei16 GRRegs:$val, (lda16f GRRegs:$addr, GRRegs:$offset)),
1020 (ST16_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;
1021 def : Pat<(truncstorei16 GRRegs:$val, GRRegs:$addr),
1022 (ST16_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>;
1024 def : Pat<(store GRRegs:$val, (ldawf GRRegs:$addr, GRRegs:$offset)),
1025 (STW_3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;
1026 def : Pat<(store GRRegs:$val, (add GRRegs:$addr, immUs4:$offset)),
1027 (STW_2rus GRRegs:$val, GRRegs:$addr, (div4_xform immUs4:$offset))>;
1028 def : Pat<(store GRRegs:$val, GRRegs:$addr),
1029 (STW_2rus GRRegs:$val, GRRegs:$addr, 0)>;
1031 /// cttz
1032 def : Pat<(cttz GRRegs:$src), (CLZ_l2r (BITREV_l2r GRRegs:$src))>;
1034 /// trap
1035 def : Pat<(trap), (ECALLF_1r (LDC_ru6 0))>;
1037 ///
1038 /// branch patterns
1039 ///
1041 // unconditional branch
1042 def : Pat<(br bb:$addr), (BRFU_lu6 bb:$addr)>;
1044 // direct match equal/notequal zero brcond
1045 def : Pat<(brcond (setne GRRegs:$lhs, 0), bb:$dst),
1046 (BRFT_lru6 GRRegs:$lhs, bb:$dst)>;
1047 def : Pat<(brcond (seteq GRRegs:$lhs, 0), bb:$dst),
1048 (BRFF_lru6 GRRegs:$lhs, bb:$dst)>;
1050 def : Pat<(brcond (setle GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1051 (BRFF_lru6 (LSS_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>;
1052 def : Pat<(brcond (setule GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1053 (BRFF_lru6 (LSU_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>;
1054 def : Pat<(brcond (setge GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1055 (BRFF_lru6 (LSS_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>;
1056 def : Pat<(brcond (setuge GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1057 (BRFF_lru6 (LSU_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>;
1058 def : Pat<(brcond (setne GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1059 (BRFF_lru6 (EQ_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>;
1060 def : Pat<(brcond (setne GRRegs:$lhs, immUs:$rhs), bb:$dst),
1061 (BRFF_lru6 (EQ_2rus GRRegs:$lhs, immUs:$rhs), bb:$dst)>;
1063 // generic brcond pattern
1064 def : Pat<(brcond GRRegs:$cond, bb:$addr), (BRFT_lru6 GRRegs:$cond, bb:$addr)>;
1067 ///
1068 /// Select patterns
1069 ///
1071 // direct match equal/notequal zero select
1072 def : Pat<(select (setne GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),
1073 (SELECT_CC GRRegs:$lhs, GRRegs:$T, GRRegs:$F)>;
1075 def : Pat<(select (seteq GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),
1076 (SELECT_CC GRRegs:$lhs, GRRegs:$F, GRRegs:$T)>;
1078 def : Pat<(select (setle GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1079 (SELECT_CC (LSS_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>;
1080 def : Pat<(select (setule GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1081 (SELECT_CC (LSU_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>;
1082 def : Pat<(select (setge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1083 (SELECT_CC (LSS_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
1084 def : Pat<(select (setuge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1085 (SELECT_CC (LSU_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
1086 def : Pat<(select (setne GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1087 (SELECT_CC (EQ_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
1088 def : Pat<(select (setne GRRegs:$lhs, immUs:$rhs), GRRegs:$T, GRRegs:$F),
1089 (SELECT_CC (EQ_2rus GRRegs:$lhs, immUs:$rhs), GRRegs:$F, GRRegs:$T)>;
1091 ///
1092 /// setcc patterns, only matched when none of the above brcond
1093 /// patterns match
1094 ///
1096 // setcc 2 register operands
1097 def : Pat<(setle GRRegs:$lhs, GRRegs:$rhs),
1098 (EQ_2rus (LSS_3r GRRegs:$rhs, GRRegs:$lhs), 0)>;
1099 def : Pat<(setule GRRegs:$lhs, GRRegs:$rhs),
1100 (EQ_2rus (LSU_3r GRRegs:$rhs, GRRegs:$lhs), 0)>;
1102 def : Pat<(setgt GRRegs:$lhs, GRRegs:$rhs),
1103 (LSS_3r GRRegs:$rhs, GRRegs:$lhs)>;
1104 def : Pat<(setugt GRRegs:$lhs, GRRegs:$rhs),
1105 (LSU_3r GRRegs:$rhs, GRRegs:$lhs)>;
1107 def : Pat<(setge GRRegs:$lhs, GRRegs:$rhs),
1108 (EQ_2rus (LSS_3r GRRegs:$lhs, GRRegs:$rhs), 0)>;
1109 def : Pat<(setuge GRRegs:$lhs, GRRegs:$rhs),
1110 (EQ_2rus (LSU_3r GRRegs:$lhs, GRRegs:$rhs), 0)>;
1112 def : Pat<(setlt GRRegs:$lhs, GRRegs:$rhs),
1113 (LSS_3r GRRegs:$lhs, GRRegs:$rhs)>;
1114 def : Pat<(setult GRRegs:$lhs, GRRegs:$rhs),
1115 (LSU_3r GRRegs:$lhs, GRRegs:$rhs)>;
1117 def : Pat<(setne GRRegs:$lhs, GRRegs:$rhs),
1118 (EQ_2rus (EQ_3r GRRegs:$lhs, GRRegs:$rhs), 0)>;
1120 def : Pat<(seteq GRRegs:$lhs, GRRegs:$rhs),
1121 (EQ_3r GRRegs:$lhs, GRRegs:$rhs)>;
1123 // setcc reg/imm operands
1124 def : Pat<(seteq GRRegs:$lhs, immUs:$rhs),
1125 (EQ_2rus GRRegs:$lhs, immUs:$rhs)>;
1126 def : Pat<(setne GRRegs:$lhs, immUs:$rhs),
1127 (EQ_2rus (EQ_2rus GRRegs:$lhs, immUs:$rhs), 0)>;
1129 // misc
1130 def : Pat<(add GRRegs:$addr, immUs4:$offset),
1131 (LDAWF_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;
1133 def : Pat<(sub GRRegs:$addr, immUs4:$offset),
1134 (LDAWB_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;
1136 def : Pat<(and GRRegs:$val, immMskBitp:$mask),
1137 (ZEXT_rus GRRegs:$val, (msksize_xform immMskBitp:$mask))>;
1139 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1140 def : Pat<(add GRRegs:$src1, immUsNeg:$src2),
1141 (SUB_2rus GRRegs:$src1, (neg_xform immUsNeg:$src2))>;
1143 def : Pat<(add GRRegs:$src1, immUs4Neg:$src2),
1144 (LDAWB_l2rus GRRegs:$src1, (div4neg_xform immUs4Neg:$src2))>;
1146 ///
1147 /// Some peepholes
1148 ///
1150 def : Pat<(mul GRRegs:$src, 3),
1151 (LDA16F_l3r GRRegs:$src, GRRegs:$src)>;
1153 def : Pat<(mul GRRegs:$src, 5),
1154 (LDAWF_l3r GRRegs:$src, GRRegs:$src)>;
1156 def : Pat<(mul GRRegs:$src, -3),
1157 (LDAWB_l3r GRRegs:$src, GRRegs:$src)>;
1159 // ashr X, 32 is equivalent to ashr X, 31 on the XCore.
1160 def : Pat<(sra GRRegs:$src, 31),
1161 (ASHR_l2rus GRRegs:$src, 32)>;
1163 def : Pat<(brcond (setlt GRRegs:$lhs, 0), bb:$dst),
1164 (BRFT_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>;
1166 // setge X, 0 is canonicalized to setgt X, -1
1167 def : Pat<(brcond (setgt GRRegs:$lhs, -1), bb:$dst),
1168 (BRFF_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>;
1170 def : Pat<(select (setlt GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),
1171 (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$T, GRRegs:$F)>;
1173 def : Pat<(select (setgt GRRegs:$lhs, -1), GRRegs:$T, GRRegs:$F),
1174 (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$F, GRRegs:$T)>;
1176 def : Pat<(setgt GRRegs:$lhs, -1),
1177 (EQ_2rus (ASHR_l2rus GRRegs:$lhs, 32), 0)>;
1179 def : Pat<(sra (shl GRRegs:$src, immBpwSubBitp:$imm), immBpwSubBitp:$imm),
1180 (SEXT_rus GRRegs:$src, (bpwsub_xform immBpwSubBitp:$imm))>;