1 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
3 define <2 x i32> @vrecpei32(<2 x i32>* %A) nounwind {
4 ;CHECK-LABEL: vrecpei32:
5 ;CHECK: vrecpe.u32
6 %tmp1 = load <2 x i32>* %A
7 %tmp2 = call <2 x i32> @llvm.arm.neon.vrecpe.v2i32(<2 x i32> %tmp1)
8 ret <2 x i32> %tmp2
9 }
11 define <4 x i32> @vrecpeQi32(<4 x i32>* %A) nounwind {
12 ;CHECK-LABEL: vrecpeQi32:
13 ;CHECK: vrecpe.u32
14 %tmp1 = load <4 x i32>* %A
15 %tmp2 = call <4 x i32> @llvm.arm.neon.vrecpe.v4i32(<4 x i32> %tmp1)
16 ret <4 x i32> %tmp2
17 }
19 define <2 x float> @vrecpef32(<2 x float>* %A) nounwind {
20 ;CHECK-LABEL: vrecpef32:
21 ;CHECK: vrecpe.f32
22 %tmp1 = load <2 x float>* %A
23 %tmp2 = call <2 x float> @llvm.arm.neon.vrecpe.v2f32(<2 x float> %tmp1)
24 ret <2 x float> %tmp2
25 }
27 define <4 x float> @vrecpeQf32(<4 x float>* %A) nounwind {
28 ;CHECK-LABEL: vrecpeQf32:
29 ;CHECK: vrecpe.f32
30 %tmp1 = load <4 x float>* %A
31 %tmp2 = call <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float> %tmp1)
32 ret <4 x float> %tmp2
33 }
35 declare <2 x i32> @llvm.arm.neon.vrecpe.v2i32(<2 x i32>) nounwind readnone
36 declare <4 x i32> @llvm.arm.neon.vrecpe.v4i32(<4 x i32>) nounwind readnone
38 declare <2 x float> @llvm.arm.neon.vrecpe.v2f32(<2 x float>) nounwind readnone
39 declare <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float>) nounwind readnone
41 define <2 x float> @vrecpsf32(<2 x float>* %A, <2 x float>* %B) nounwind {
42 ;CHECK-LABEL: vrecpsf32:
43 ;CHECK: vrecps.f32
44 %tmp1 = load <2 x float>* %A
45 %tmp2 = load <2 x float>* %B
46 %tmp3 = call <2 x float> @llvm.arm.neon.vrecps.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
47 ret <2 x float> %tmp3
48 }
50 define <4 x float> @vrecpsQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
51 ;CHECK-LABEL: vrecpsQf32:
52 ;CHECK: vrecps.f32
53 %tmp1 = load <4 x float>* %A
54 %tmp2 = load <4 x float>* %B
55 %tmp3 = call <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
56 ret <4 x float> %tmp3
57 }
59 declare <2 x float> @llvm.arm.neon.vrecps.v2f32(<2 x float>, <2 x float>) nounwind readnone
60 declare <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float>, <4 x float>) nounwind readnone
62 define <2 x i32> @vrsqrtei32(<2 x i32>* %A) nounwind {
63 ;CHECK-LABEL: vrsqrtei32:
64 ;CHECK: vrsqrte.u32
65 %tmp1 = load <2 x i32>* %A
66 %tmp2 = call <2 x i32> @llvm.arm.neon.vrsqrte.v2i32(<2 x i32> %tmp1)
67 ret <2 x i32> %tmp2
68 }
70 define <4 x i32> @vrsqrteQi32(<4 x i32>* %A) nounwind {
71 ;CHECK-LABEL: vrsqrteQi32:
72 ;CHECK: vrsqrte.u32
73 %tmp1 = load <4 x i32>* %A
74 %tmp2 = call <4 x i32> @llvm.arm.neon.vrsqrte.v4i32(<4 x i32> %tmp1)
75 ret <4 x i32> %tmp2
76 }
78 define <2 x float> @vrsqrtef32(<2 x float>* %A) nounwind {
79 ;CHECK-LABEL: vrsqrtef32:
80 ;CHECK: vrsqrte.f32
81 %tmp1 = load <2 x float>* %A
82 %tmp2 = call <2 x float> @llvm.arm.neon.vrsqrte.v2f32(<2 x float> %tmp1)
83 ret <2 x float> %tmp2
84 }
86 define <4 x float> @vrsqrteQf32(<4 x float>* %A) nounwind {
87 ;CHECK-LABEL: vrsqrteQf32:
88 ;CHECK: vrsqrte.f32
89 %tmp1 = load <4 x float>* %A
90 %tmp2 = call <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float> %tmp1)
91 ret <4 x float> %tmp2
92 }
94 declare <2 x i32> @llvm.arm.neon.vrsqrte.v2i32(<2 x i32>) nounwind readnone
95 declare <4 x i32> @llvm.arm.neon.vrsqrte.v4i32(<4 x i32>) nounwind readnone
97 declare <2 x float> @llvm.arm.neon.vrsqrte.v2f32(<2 x float>) nounwind readnone
98 declare <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float>) nounwind readnone
100 define <2 x float> @vrsqrtsf32(<2 x float>* %A, <2 x float>* %B) nounwind {
101 ;CHECK-LABEL: vrsqrtsf32:
102 ;CHECK: vrsqrts.f32
103 %tmp1 = load <2 x float>* %A
104 %tmp2 = load <2 x float>* %B
105 %tmp3 = call <2 x float> @llvm.arm.neon.vrsqrts.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
106 ret <2 x float> %tmp3
107 }
109 define <4 x float> @vrsqrtsQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
110 ;CHECK-LABEL: vrsqrtsQf32:
111 ;CHECK: vrsqrts.f32
112 %tmp1 = load <4 x float>* %A
113 %tmp2 = load <4 x float>* %B
114 %tmp3 = call <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
115 ret <4 x float> %tmp3
116 }
118 declare <2 x float> @llvm.arm.neon.vrsqrts.v2f32(<2 x float>, <2 x float>) nounwind readnone
119 declare <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float>, <4 x float>) nounwind readnone