1 ; Test zero extensions from a byte to an i32.
2 ;
3 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
5 ; Test register extension, starting with an i32.
6 define i32 @f1(i32 %a) {
7 ; CHECK-LABEL: f1:
8 ; CHECK: llcr %r2, %r2
9 ; CHECK: br %r14
10 %byte = trunc i32 %a to i8
11 %ext = zext i8 %byte to i32
12 ret i32 %ext
13 }
15 ; ...and again with an i64.
16 define i32 @f2(i64 %a) {
17 ; CHECK-LABEL: f2:
18 ; CHECK: llcr %r2, %r2
19 ; CHECK: br %r14
20 %byte = trunc i64 %a to i8
21 %ext = zext i8 %byte to i32
22 ret i32 %ext
23 }
25 ; Check ANDs that are equivalent to zero extension.
26 define i32 @f3(i32 %a) {
27 ; CHECK-LABEL: f3:
28 ; CHECK: llcr %r2, %r2
29 ; CHECK: br %r14
30 %ext = and i32 %a, 255
31 ret i32 %ext
32 }
34 ; Check LLC with no displacement.
35 define i32 @f4(i8 *%src) {
36 ; CHECK-LABEL: f4:
37 ; CHECK: llc %r2, 0(%r2)
38 ; CHECK: br %r14
39 %byte = load i8 *%src
40 %ext = zext i8 %byte to i32
41 ret i32 %ext
42 }
44 ; Check the high end of the LLC range.
45 define i32 @f5(i8 *%src) {
46 ; CHECK-LABEL: f5:
47 ; CHECK: llc %r2, 524287(%r2)
48 ; CHECK: br %r14
49 %ptr = getelementptr i8 *%src, i64 524287
50 %byte = load i8 *%ptr
51 %ext = zext i8 %byte to i32
52 ret i32 %ext
53 }
55 ; Check the next byte up, which needs separate address logic.
56 ; Other sequences besides this one would be OK.
57 define i32 @f6(i8 *%src) {
58 ; CHECK-LABEL: f6:
59 ; CHECK: agfi %r2, 524288
60 ; CHECK: llc %r2, 0(%r2)
61 ; CHECK: br %r14
62 %ptr = getelementptr i8 *%src, i64 524288
63 %byte = load i8 *%ptr
64 %ext = zext i8 %byte to i32
65 ret i32 %ext
66 }
68 ; Check the high end of the negative LLC range.
69 define i32 @f7(i8 *%src) {
70 ; CHECK-LABEL: f7:
71 ; CHECK: llc %r2, -1(%r2)
72 ; CHECK: br %r14
73 %ptr = getelementptr i8 *%src, i64 -1
74 %byte = load i8 *%ptr
75 %ext = zext i8 %byte to i32
76 ret i32 %ext
77 }
79 ; Check the low end of the LLC range.
80 define i32 @f8(i8 *%src) {
81 ; CHECK-LABEL: f8:
82 ; CHECK: llc %r2, -524288(%r2)
83 ; CHECK: br %r14
84 %ptr = getelementptr i8 *%src, i64 -524288
85 %byte = load i8 *%ptr
86 %ext = zext i8 %byte to i32
87 ret i32 %ext
88 }
90 ; Check the next byte down, which needs separate address logic.
91 ; Other sequences besides this one would be OK.
92 define i32 @f9(i8 *%src) {
93 ; CHECK-LABEL: f9:
94 ; CHECK: agfi %r2, -524289
95 ; CHECK: llc %r2, 0(%r2)
96 ; CHECK: br %r14
97 %ptr = getelementptr i8 *%src, i64 -524289
98 %byte = load i8 *%ptr
99 %ext = zext i8 %byte to i32
100 ret i32 %ext
101 }
103 ; Check that LLC allows an index
104 define i32 @f10(i64 %src, i64 %index) {
105 ; CHECK-LABEL: f10:
106 ; CHECK: llc %r2, 524287(%r3,%r2)
107 ; CHECK: br %r14
108 %add1 = add i64 %src, %index
109 %add2 = add i64 %add1, 524287
110 %ptr = inttoptr i64 %add2 to i8 *
111 %byte = load i8 *%ptr
112 %ext = zext i8 %byte to i32
113 ret i32 %ext
114 }
116 ; Test a case where we spill the source of at least one LLCR. We want
117 ; to use LLC if possible.
118 define void @f11(i32 *%ptr) {
119 ; CHECK-LABEL: f11:
120 ; CHECK: llc {{%r[0-9]+}}, 16{{[37]}}(%r15)
121 ; CHECK: br %r14
122 %val0 = load volatile i32 *%ptr
123 %val1 = load volatile i32 *%ptr
124 %val2 = load volatile i32 *%ptr
125 %val3 = load volatile i32 *%ptr
126 %val4 = load volatile i32 *%ptr
127 %val5 = load volatile i32 *%ptr
128 %val6 = load volatile i32 *%ptr
129 %val7 = load volatile i32 *%ptr
130 %val8 = load volatile i32 *%ptr
131 %val9 = load volatile i32 *%ptr
132 %val10 = load volatile i32 *%ptr
133 %val11 = load volatile i32 *%ptr
134 %val12 = load volatile i32 *%ptr
135 %val13 = load volatile i32 *%ptr
136 %val14 = load volatile i32 *%ptr
137 %val15 = load volatile i32 *%ptr
139 %trunc0 = trunc i32 %val0 to i8
140 %trunc1 = trunc i32 %val1 to i8
141 %trunc2 = trunc i32 %val2 to i8
142 %trunc3 = trunc i32 %val3 to i8
143 %trunc4 = trunc i32 %val4 to i8
144 %trunc5 = trunc i32 %val5 to i8
145 %trunc6 = trunc i32 %val6 to i8
146 %trunc7 = trunc i32 %val7 to i8
147 %trunc8 = trunc i32 %val8 to i8
148 %trunc9 = trunc i32 %val9 to i8
149 %trunc10 = trunc i32 %val10 to i8
150 %trunc11 = trunc i32 %val11 to i8
151 %trunc12 = trunc i32 %val12 to i8
152 %trunc13 = trunc i32 %val13 to i8
153 %trunc14 = trunc i32 %val14 to i8
154 %trunc15 = trunc i32 %val15 to i8
156 %ext0 = zext i8 %trunc0 to i32
157 %ext1 = zext i8 %trunc1 to i32
158 %ext2 = zext i8 %trunc2 to i32
159 %ext3 = zext i8 %trunc3 to i32
160 %ext4 = zext i8 %trunc4 to i32
161 %ext5 = zext i8 %trunc5 to i32
162 %ext6 = zext i8 %trunc6 to i32
163 %ext7 = zext i8 %trunc7 to i32
164 %ext8 = zext i8 %trunc8 to i32
165 %ext9 = zext i8 %trunc9 to i32
166 %ext10 = zext i8 %trunc10 to i32
167 %ext11 = zext i8 %trunc11 to i32
168 %ext12 = zext i8 %trunc12 to i32
169 %ext13 = zext i8 %trunc13 to i32
170 %ext14 = zext i8 %trunc14 to i32
171 %ext15 = zext i8 %trunc15 to i32
173 store volatile i32 %val0, i32 *%ptr
174 store volatile i32 %val1, i32 *%ptr
175 store volatile i32 %val2, i32 *%ptr
176 store volatile i32 %val3, i32 *%ptr
177 store volatile i32 %val4, i32 *%ptr
178 store volatile i32 %val5, i32 *%ptr
179 store volatile i32 %val6, i32 *%ptr
180 store volatile i32 %val7, i32 *%ptr
181 store volatile i32 %val8, i32 *%ptr
182 store volatile i32 %val9, i32 *%ptr
183 store volatile i32 %val10, i32 *%ptr
184 store volatile i32 %val11, i32 *%ptr
185 store volatile i32 %val12, i32 *%ptr
186 store volatile i32 %val13, i32 *%ptr
187 store volatile i32 %val14, i32 *%ptr
188 store volatile i32 %val15, i32 *%ptr
190 store volatile i32 %ext0, i32 *%ptr
191 store volatile i32 %ext1, i32 *%ptr
192 store volatile i32 %ext2, i32 *%ptr
193 store volatile i32 %ext3, i32 *%ptr
194 store volatile i32 %ext4, i32 *%ptr
195 store volatile i32 %ext5, i32 *%ptr
196 store volatile i32 %ext6, i32 *%ptr
197 store volatile i32 %ext7, i32 *%ptr
198 store volatile i32 %ext8, i32 *%ptr
199 store volatile i32 %ext9, i32 *%ptr
200 store volatile i32 %ext10, i32 *%ptr
201 store volatile i32 %ext11, i32 *%ptr
202 store volatile i32 %ext12, i32 *%ptr
203 store volatile i32 %ext13, i32 *%ptr
204 store volatile i32 %ext14, i32 *%ptr
205 store volatile i32 %ext15, i32 *%ptr
207 ret void
208 }