1 ; Test sequences that can use RISBG.
2 ;
3 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
5 ; Test an extraction of bit 0 from a right-shifted value.
6 define i32 @f1(i32 %foo) {
7 ; CHECK-LABEL: f1:
8 ; CHECK: risbg %r2, %r2, 63, 191, 54
9 ; CHECK: br %r14
10 %shr = lshr i32 %foo, 10
11 %and = and i32 %shr, 1
12 ret i32 %and
13 }
15 ; ...and again with i64.
16 define i64 @f2(i64 %foo) {
17 ; CHECK-LABEL: f2:
18 ; CHECK: risbg %r2, %r2, 63, 191, 54
19 ; CHECK: br %r14
20 %shr = lshr i64 %foo, 10
21 %and = and i64 %shr, 1
22 ret i64 %and
23 }
25 ; Test an extraction of other bits from a right-shifted value.
26 define i32 @f3(i32 %foo) {
27 ; CHECK-LABEL: f3:
28 ; CHECK: risbg %r2, %r2, 60, 189, 42
29 ; CHECK: br %r14
30 %shr = lshr i32 %foo, 22
31 %and = and i32 %shr, 12
32 ret i32 %and
33 }
35 ; ...and again with i64.
36 define i64 @f4(i64 %foo) {
37 ; CHECK-LABEL: f4:
38 ; CHECK: risbg %r2, %r2, 60, 189, 42
39 ; CHECK: br %r14
40 %shr = lshr i64 %foo, 22
41 %and = and i64 %shr, 12
42 ret i64 %and
43 }
45 ; Test an extraction of most bits from a right-shifted value.
46 ; The range should be reduced to exclude the zeroed high bits.
47 define i32 @f5(i32 %foo) {
48 ; CHECK-LABEL: f5:
49 ; CHECK: risbg %r2, %r2, 34, 188, 62
50 ; CHECK: br %r14
51 %shr = lshr i32 %foo, 2
52 %and = and i32 %shr, -8
53 ret i32 %and
54 }
56 ; ...and again with i64.
57 define i64 @f6(i64 %foo) {
58 ; CHECK-LABEL: f6:
59 ; CHECK: risbg %r2, %r2, 2, 188, 62
60 ; CHECK: br %r14
61 %shr = lshr i64 %foo, 2
62 %and = and i64 %shr, -8
63 ret i64 %and
64 }
66 ; Try the next value up (mask ....1111001). The mask itself is suitable
67 ; for RISBG, but the shift is still needed.
68 define i32 @f7(i32 %foo) {
69 ; CHECK-LABEL: f7:
70 ; CHECK: srl %r2, 2
71 ; CHECK: risbg %r2, %r2, 63, 188, 0
72 ; CHECK: br %r14
73 %shr = lshr i32 %foo, 2
74 %and = and i32 %shr, -7
75 ret i32 %and
76 }
78 ; ...and again with i64.
79 define i64 @f8(i64 %foo) {
80 ; CHECK-LABEL: f8:
81 ; CHECK: srlg [[REG:%r[0-5]]], %r2, 2
82 ; CHECK: risbg %r2, [[REG]], 63, 188, 0
83 ; CHECK: br %r14
84 %shr = lshr i64 %foo, 2
85 %and = and i64 %shr, -7
86 ret i64 %and
87 }
89 ; Test an extraction of bits from a left-shifted value. The range should
90 ; be reduced to exclude the zeroed low bits.
91 define i32 @f9(i32 %foo) {
92 ; CHECK-LABEL: f9:
93 ; CHECK: risbg %r2, %r2, 56, 189, 2
94 ; CHECK: br %r14
95 %shr = shl i32 %foo, 2
96 %and = and i32 %shr, 255
97 ret i32 %and
98 }
100 ; ...and again with i64.
101 define i64 @f10(i64 %foo) {
102 ; CHECK-LABEL: f10:
103 ; CHECK: risbg %r2, %r2, 56, 189, 2
104 ; CHECK: br %r14
105 %shr = shl i64 %foo, 2
106 %and = and i64 %shr, 255
107 ret i64 %and
108 }
110 ; Try a wrap-around mask (mask ....111100001111). The mask itself is suitable
111 ; for RISBG, but the shift is still needed.
112 define i32 @f11(i32 %foo) {
113 ; CHECK-LABEL: f11:
114 ; CHECK: sll %r2, 2
115 ; CHECK: risbg %r2, %r2, 60, 183, 0
116 ; CHECK: br %r14
117 %shr = shl i32 %foo, 2
118 %and = and i32 %shr, -241
119 ret i32 %and
120 }
122 ; ...and again with i64.
123 define i64 @f12(i64 %foo) {
124 ; CHECK-LABEL: f12:
125 ; CHECK: sllg [[REG:%r[0-5]]], %r2, 2
126 ; CHECK: risbg %r2, [[REG]], 60, 183, 0
127 ; CHECK: br %r14
128 %shr = shl i64 %foo, 2
129 %and = and i64 %shr, -241
130 ret i64 %and
131 }
133 ; Test an extraction from a rotated value, no mask wraparound.
134 ; This is equivalent to the lshr case, because the bits from the
135 ; shl are not used.
136 define i32 @f13(i32 %foo) {
137 ; CHECK-LABEL: f13:
138 ; CHECK: risbg %r2, %r2, 56, 188, 46
139 ; CHECK: br %r14
140 %parta = shl i32 %foo, 14
141 %partb = lshr i32 %foo, 18
142 %rotl = or i32 %parta, %partb
143 %and = and i32 %rotl, 248
144 ret i32 %and
145 }
147 ; ...and again with i64.
148 define i64 @f14(i64 %foo) {
149 ; CHECK-LABEL: f14:
150 ; CHECK: risbg %r2, %r2, 56, 188, 14
151 ; CHECK: br %r14
152 %parta = shl i64 %foo, 14
153 %partb = lshr i64 %foo, 50
154 %rotl = or i64 %parta, %partb
155 %and = and i64 %rotl, 248
156 ret i64 %and
157 }
159 ; Try a case in which only the bits from the shl are used.
160 define i32 @f15(i32 %foo) {
161 ; CHECK-LABEL: f15:
162 ; CHECK: risbg %r2, %r2, 47, 177, 14
163 ; CHECK: br %r14
164 %parta = shl i32 %foo, 14
165 %partb = lshr i32 %foo, 18
166 %rotl = or i32 %parta, %partb
167 %and = and i32 %rotl, 114688
168 ret i32 %and
169 }
171 ; ...and again with i64.
172 define i64 @f16(i64 %foo) {
173 ; CHECK-LABEL: f16:
174 ; CHECK: risbg %r2, %r2, 47, 177, 14
175 ; CHECK: br %r14
176 %parta = shl i64 %foo, 14
177 %partb = lshr i64 %foo, 50
178 %rotl = or i64 %parta, %partb
179 %and = and i64 %rotl, 114688
180 ret i64 %and
181 }
183 ; Test a 32-bit rotate in which both parts of the OR are needed.
184 ; This needs a separate shift (although RISBLG would be better
185 ; if supported).
186 define i32 @f17(i32 %foo) {
187 ; CHECK-LABEL: f17:
188 ; CHECK: rll [[REG:%r[0-5]]], %r2, 4
189 ; CHECK: risbg %r2, [[REG]], 57, 190, 0
190 ; CHECK: br %r14
191 %parta = shl i32 %foo, 4
192 %partb = lshr i32 %foo, 28
193 %rotl = or i32 %parta, %partb
194 %and = and i32 %rotl, 126
195 ret i32 %and
196 }
198 ; ...and for i64, where RISBG should do the rotate too.
199 define i64 @f18(i64 %foo) {
200 ; CHECK-LABEL: f18:
201 ; CHECK: risbg %r2, %r2, 57, 190, 4
202 ; CHECK: br %r14
203 %parta = shl i64 %foo, 4
204 %partb = lshr i64 %foo, 60
205 %rotl = or i64 %parta, %partb
206 %and = and i64 %rotl, 126
207 ret i64 %and
208 }
210 ; Test an arithmetic shift right in which some of the sign bits are kept.
211 ; The SRA is still needed.
212 define i32 @f19(i32 %foo) {
213 ; CHECK-LABEL: f19:
214 ; CHECK: sra %r2, 28
215 ; CHECK: risbg %r2, %r2, 59, 190, 0
216 ; CHECK: br %r14
217 %shr = ashr i32 %foo, 28
218 %and = and i32 %shr, 30
219 ret i32 %and
220 }
222 ; ...and again with i64.
223 define i64 @f20(i64 %foo) {
224 ; CHECK-LABEL: f20:
225 ; CHECK: srag [[REG:%r[0-5]]], %r2, 60
226 ; CHECK: risbg %r2, [[REG]], 59, 190, 0
227 ; CHECK: br %r14
228 %shr = ashr i64 %foo, 60
229 %and = and i64 %shr, 30
230 ret i64 %and
231 }
233 ; Now try an arithmetic right shift in which the sign bits aren't needed.
234 ; Introduce a second use of %shr so that the ashr doesn't decompose to
235 ; an lshr.
236 define i32 @f21(i32 %foo, i32 *%dest) {
237 ; CHECK-LABEL: f21:
238 ; CHECK: risbg %r2, %r2, 60, 190, 36
239 ; CHECK: br %r14
240 %shr = ashr i32 %foo, 28
241 store i32 %shr, i32 *%dest
242 %and = and i32 %shr, 14
243 ret i32 %and
244 }
246 ; ...and again with i64.
247 define i64 @f22(i64 %foo, i64 *%dest) {
248 ; CHECK-LABEL: f22:
249 ; CHECK: risbg %r2, %r2, 60, 190, 4
250 ; CHECK: br %r14
251 %shr = ashr i64 %foo, 60
252 store i64 %shr, i64 *%dest
253 %and = and i64 %shr, 14
254 ret i64 %and
255 }
257 ; Check that we use RISBG for shifted values even if the AND is a
258 ; natural zero extension.
259 define i64 @f23(i64 %foo) {
260 ; CHECK-LABEL: f23:
261 ; CHECK: risbg %r2, %r2, 56, 191, 62
262 ; CHECK: br %r14
263 %shr = lshr i64 %foo, 2
264 %and = and i64 %shr, 255
265 ret i64 %and
266 }