1 //===- CodeGenRegisters.h - Register and RegisterClass Info -----*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines structures to encapsulate information gleaned from the
11 // target register and register class definitions.
12 //
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_UTILS_TABLEGEN_CODEGENREGISTERS_H
16 #define LLVM_UTILS_TABLEGEN_CODEGENREGISTERS_H
18 #include "llvm/ADT/ArrayRef.h"
19 #include "llvm/ADT/BitVector.h"
20 #include "llvm/ADT/DenseMap.h"
21 #include "llvm/ADT/SetVector.h"
22 #include "llvm/CodeGen/MachineValueType.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/TableGen/Record.h"
25 #include "llvm/TableGen/SetTheory.h"
26 #include <cstdlib>
27 #include <list>
28 #include <map>
29 #include <set>
30 #include <string>
31 #include <vector>
32 #include <deque>
34 namespace llvm {
35 class CodeGenRegBank;
37 /// CodeGenSubRegIndex - Represents a sub-register index.
38 class CodeGenSubRegIndex {
39 Record *const TheDef;
40 std::string Name;
41 std::string Namespace;
43 public:
44 uint16_t Size;
45 uint16_t Offset;
46 const unsigned EnumValue;
47 mutable unsigned LaneMask;
49 // Are all super-registers containing this SubRegIndex covered by their
50 // sub-registers?
51 bool AllSuperRegsCovered;
53 CodeGenSubRegIndex(Record *R, unsigned Enum);
54 CodeGenSubRegIndex(StringRef N, StringRef Nspace, unsigned Enum);
56 const std::string &getName() const { return Name; }
57 const std::string &getNamespace() const { return Namespace; }
58 std::string getQualifiedName() const;
60 // Order CodeGenSubRegIndex pointers by EnumValue.
61 struct Less {
62 bool operator()(const CodeGenSubRegIndex *A,
63 const CodeGenSubRegIndex *B) const {
64 assert(A && B);
65 return A->EnumValue < B->EnumValue;
66 }
67 };
69 // Map of composite subreg indices.
70 typedef std::map<CodeGenSubRegIndex*, CodeGenSubRegIndex*, Less> CompMap;
72 // Returns the subreg index that results from composing this with Idx.
73 // Returns NULL if this and Idx don't compose.
74 CodeGenSubRegIndex *compose(CodeGenSubRegIndex *Idx) const {
75 CompMap::const_iterator I = Composed.find(Idx);
76 return I == Composed.end() ? nullptr : I->second;
77 }
79 // Add a composite subreg index: this+A = B.
80 // Return a conflicting composite, or NULL
81 CodeGenSubRegIndex *addComposite(CodeGenSubRegIndex *A,
82 CodeGenSubRegIndex *B) {
83 assert(A && B);
84 std::pair<CompMap::iterator, bool> Ins =
85 Composed.insert(std::make_pair(A, B));
86 // Synthetic subreg indices that aren't contiguous (for instance ARM
87 // register tuples) don't have a bit range, so it's OK to let
88 // B->Offset == -1. For the other cases, accumulate the offset and set
89 // the size here. Only do so if there is no offset yet though.
90 if ((Offset != (uint16_t)-1 && A->Offset != (uint16_t)-1) &&
91 (B->Offset == (uint16_t)-1)) {
92 B->Offset = Offset + A->Offset;
93 B->Size = A->Size;
94 }
95 return (Ins.second || Ins.first->second == B) ? nullptr
96 : Ins.first->second;
97 }
99 // Update the composite maps of components specified in 'ComposedOf'.
100 void updateComponents(CodeGenRegBank&);
102 // Return the map of composites.
103 const CompMap &getComposites() const { return Composed; }
105 // Compute LaneMask from Composed. Return LaneMask.
106 unsigned computeLaneMask() const;
108 private:
109 CompMap Composed;
110 };
112 /// CodeGenRegister - Represents a register definition.
113 struct CodeGenRegister {
114 Record *TheDef;
115 unsigned EnumValue;
116 unsigned CostPerUse;
117 bool CoveredBySubRegs;
119 // Map SubRegIndex -> Register.
120 typedef std::map<CodeGenSubRegIndex*, CodeGenRegister*,
121 CodeGenSubRegIndex::Less> SubRegMap;
123 CodeGenRegister(Record *R, unsigned Enum);
125 const std::string &getName() const;
127 // Extract more information from TheDef. This is used to build an object
128 // graph after all CodeGenRegister objects have been created.
129 void buildObjectGraph(CodeGenRegBank&);
131 // Lazily compute a map of all sub-registers.
132 // This includes unique entries for all sub-sub-registers.
133 const SubRegMap &computeSubRegs(CodeGenRegBank&);
135 // Compute extra sub-registers by combining the existing sub-registers.
136 void computeSecondarySubRegs(CodeGenRegBank&);
138 // Add this as a super-register to all sub-registers after the sub-register
139 // graph has been built.
140 void computeSuperRegs(CodeGenRegBank&);
142 const SubRegMap &getSubRegs() const {
143 assert(SubRegsComplete && "Must precompute sub-registers");
144 return SubRegs;
145 }
147 // Add sub-registers to OSet following a pre-order defined by the .td file.
148 void addSubRegsPreOrder(SetVector<const CodeGenRegister*> &OSet,
149 CodeGenRegBank&) const;
151 // Return the sub-register index naming Reg as a sub-register of this
152 // register. Returns NULL if Reg is not a sub-register.
153 CodeGenSubRegIndex *getSubRegIndex(const CodeGenRegister *Reg) const {
154 return SubReg2Idx.lookup(Reg);
155 }
157 typedef std::vector<const CodeGenRegister*> SuperRegList;
159 // Get the list of super-registers in topological order, small to large.
160 // This is valid after computeSubRegs visits all registers during RegBank
161 // construction.
162 const SuperRegList &getSuperRegs() const {
163 assert(SubRegsComplete && "Must precompute sub-registers");
164 return SuperRegs;
165 }
167 // Get the list of ad hoc aliases. The graph is symmetric, so the list
168 // contains all registers in 'Aliases', and all registers that mention this
169 // register in 'Aliases'.
170 ArrayRef<CodeGenRegister*> getExplicitAliases() const {
171 return ExplicitAliases;
172 }
174 // Get the topological signature of this register. This is a small integer
175 // less than RegBank.getNumTopoSigs(). Registers with the same TopoSig have
176 // identical sub-register structure. That is, they support the same set of
177 // sub-register indices mapping to the same kind of sub-registers
178 // (TopoSig-wise).
179 unsigned getTopoSig() const {
180 assert(SuperRegsComplete && "TopoSigs haven't been computed yet.");
181 return TopoSig;
182 }
184 // List of register units in ascending order.
185 typedef SmallVector<unsigned, 16> RegUnitList;
187 // How many entries in RegUnitList are native?
188 unsigned NumNativeRegUnits;
190 // Get the list of register units.
191 // This is only valid after computeSubRegs() completes.
192 const RegUnitList &getRegUnits() const { return RegUnits; }
194 // Get the native register units. This is a prefix of getRegUnits().
195 ArrayRef<unsigned> getNativeRegUnits() const {
196 return makeArrayRef(RegUnits).slice(0, NumNativeRegUnits);
197 }
199 // Inherit register units from subregisters.
200 // Return true if the RegUnits changed.
201 bool inheritRegUnits(CodeGenRegBank &RegBank);
203 // Adopt a register unit for pressure tracking.
204 // A unit is adopted iff its unit number is >= NumNativeRegUnits.
205 void adoptRegUnit(unsigned RUID) { RegUnits.push_back(RUID); }
207 // Get the sum of this register's register unit weights.
208 unsigned getWeight(const CodeGenRegBank &RegBank) const;
210 // Order CodeGenRegister pointers by EnumValue.
211 struct Less {
212 bool operator()(const CodeGenRegister *A,
213 const CodeGenRegister *B) const {
214 assert(A && B);
215 return A->EnumValue < B->EnumValue;
216 }
217 };
219 // Canonically ordered set.
220 typedef std::set<const CodeGenRegister*, Less> Set;
222 private:
223 bool SubRegsComplete;
224 bool SuperRegsComplete;
225 unsigned TopoSig;
227 // The sub-registers explicit in the .td file form a tree.
228 SmallVector<CodeGenSubRegIndex*, 8> ExplicitSubRegIndices;
229 SmallVector<CodeGenRegister*, 8> ExplicitSubRegs;
231 // Explicit ad hoc aliases, symmetrized to form an undirected graph.
232 SmallVector<CodeGenRegister*, 8> ExplicitAliases;
234 // Super-registers where this is the first explicit sub-register.
235 SuperRegList LeadingSuperRegs;
237 SubRegMap SubRegs;
238 SuperRegList SuperRegs;
239 DenseMap<const CodeGenRegister*, CodeGenSubRegIndex*> SubReg2Idx;
240 RegUnitList RegUnits;
241 };
244 class CodeGenRegisterClass {
245 CodeGenRegister::Set Members;
246 // Allocation orders. Order[0] always contains all registers in Members.
247 std::vector<SmallVector<Record*, 16> > Orders;
248 // Bit mask of sub-classes including this, indexed by their EnumValue.
249 BitVector SubClasses;
250 // List of super-classes, topologocally ordered to have the larger classes
251 // first. This is the same as sorting by EnumValue.
252 SmallVector<CodeGenRegisterClass*, 4> SuperClasses;
253 Record *TheDef;
254 std::string Name;
256 // For a synthesized class, inherit missing properties from the nearest
257 // super-class.
258 void inheritProperties(CodeGenRegBank&);
260 // Map SubRegIndex -> sub-class. This is the largest sub-class where all
261 // registers have a SubRegIndex sub-register.
262 DenseMap<const CodeGenSubRegIndex *, CodeGenRegisterClass *>
263 SubClassWithSubReg;
265 // Map SubRegIndex -> set of super-reg classes. This is all register
266 // classes SuperRC such that:
267 //
268 // R:SubRegIndex in this RC for all R in SuperRC.
269 //
270 DenseMap<const CodeGenSubRegIndex *, SmallPtrSet<CodeGenRegisterClass *, 8>>
271 SuperRegClasses;
273 // Bit vector of TopoSigs for the registers in this class. This will be
274 // very sparse on regular architectures.
275 BitVector TopoSigs;
277 public:
278 unsigned EnumValue;
279 std::string Namespace;
280 SmallVector<MVT::SimpleValueType, 4> VTs;
281 unsigned SpillSize;
282 unsigned SpillAlignment;
283 int CopyCost;
284 bool Allocatable;
285 std::string AltOrderSelect;
287 // Return the Record that defined this class, or NULL if the class was
288 // created by TableGen.
289 Record *getDef() const { return TheDef; }
291 const std::string &getName() const { return Name; }
292 std::string getQualifiedName() const;
293 ArrayRef<MVT::SimpleValueType> getValueTypes() const {return VTs;}
294 unsigned getNumValueTypes() const { return VTs.size(); }
296 MVT::SimpleValueType getValueTypeNum(unsigned VTNum) const {
297 if (VTNum < VTs.size())
298 return VTs[VTNum];
299 llvm_unreachable("VTNum greater than number of ValueTypes in RegClass!");
300 }
302 // Return true if this this class contains the register.
303 bool contains(const CodeGenRegister*) const;
305 // Returns true if RC is a subclass.
306 // RC is a sub-class of this class if it is a valid replacement for any
307 // instruction operand where a register of this classis required. It must
308 // satisfy these conditions:
309 //
310 // 1. All RC registers are also in this.
311 // 2. The RC spill size must not be smaller than our spill size.
312 // 3. RC spill alignment must be compatible with ours.
313 //
314 bool hasSubClass(const CodeGenRegisterClass *RC) const {
315 return SubClasses.test(RC->EnumValue);
316 }
318 // getSubClassWithSubReg - Returns the largest sub-class where all
319 // registers have a SubIdx sub-register.
320 CodeGenRegisterClass *
321 getSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx) const {
322 return SubClassWithSubReg.lookup(SubIdx);
323 }
325 void setSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx,
326 CodeGenRegisterClass *SubRC) {
327 SubClassWithSubReg[SubIdx] = SubRC;
328 }
330 // getSuperRegClasses - Returns a bit vector of all register classes
331 // containing only SubIdx super-registers of this class.
332 void getSuperRegClasses(const CodeGenSubRegIndex *SubIdx,
333 BitVector &Out) const;
335 // addSuperRegClass - Add a class containing only SudIdx super-registers.
336 void addSuperRegClass(CodeGenSubRegIndex *SubIdx,
337 CodeGenRegisterClass *SuperRC) {
338 SuperRegClasses[SubIdx].insert(SuperRC);
339 }
341 // getSubClasses - Returns a constant BitVector of subclasses indexed by
342 // EnumValue.
343 // The SubClasses vector includes an entry for this class.
344 const BitVector &getSubClasses() const { return SubClasses; }
346 // getSuperClasses - Returns a list of super classes ordered by EnumValue.
347 // The array does not include an entry for this class.
348 ArrayRef<CodeGenRegisterClass*> getSuperClasses() const {
349 return SuperClasses;
350 }
352 // Returns an ordered list of class members.
353 // The order of registers is the same as in the .td file.
354 // No = 0 is the default allocation order, No = 1 is the first alternative.
355 ArrayRef<Record*> getOrder(unsigned No = 0) const {
356 return Orders[No];
357 }
359 // Return the total number of allocation orders available.
360 unsigned getNumOrders() const { return Orders.size(); }
362 // Get the set of registers. This set contains the same registers as
363 // getOrder(0).
364 const CodeGenRegister::Set &getMembers() const { return Members; }
366 // Get a bit vector of TopoSigs present in this register class.
367 const BitVector &getTopoSigs() const { return TopoSigs; }
369 // Populate a unique sorted list of units from a register set.
370 void buildRegUnitSet(std::vector<unsigned> &RegUnits) const;
372 CodeGenRegisterClass(CodeGenRegBank&, Record *R);
374 // A key representing the parts of a register class used for forming
375 // sub-classes. Note the ordering provided by this key is not the same as
376 // the topological order used for the EnumValues.
377 struct Key {
378 const CodeGenRegister::Set *Members;
379 unsigned SpillSize;
380 unsigned SpillAlignment;
382 Key(const CodeGenRegister::Set *M, unsigned S = 0, unsigned A = 0)
383 : Members(M), SpillSize(S), SpillAlignment(A) {}
385 Key(const CodeGenRegisterClass &RC)
386 : Members(&RC.getMembers()),
387 SpillSize(RC.SpillSize),
388 SpillAlignment(RC.SpillAlignment) {}
390 // Lexicographical order of (Members, SpillSize, SpillAlignment).
391 bool operator<(const Key&) const;
392 };
394 // Create a non-user defined register class.
395 CodeGenRegisterClass(CodeGenRegBank&, StringRef Name, Key Props);
397 // Called by CodeGenRegBank::CodeGenRegBank().
398 static void computeSubClasses(CodeGenRegBank&);
399 };
401 // Register units are used to model interference and register pressure.
402 // Every register is assigned one or more register units such that two
403 // registers overlap if and only if they have a register unit in common.
404 //
405 // Normally, one register unit is created per leaf register. Non-leaf
406 // registers inherit the units of their sub-registers.
407 struct RegUnit {
408 // Weight assigned to this RegUnit for estimating register pressure.
409 // This is useful when equalizing weights in register classes with mixed
410 // register topologies.
411 unsigned Weight;
413 // Each native RegUnit corresponds to one or two root registers. The full
414 // set of registers containing this unit can be computed as the union of
415 // these two registers and their super-registers.
416 const CodeGenRegister *Roots[2];
418 // Index into RegClassUnitSets where we can find the list of UnitSets that
419 // contain this unit.
420 unsigned RegClassUnitSetsIdx;
422 RegUnit() : Weight(0), RegClassUnitSetsIdx(0) {
423 Roots[0] = Roots[1] = nullptr;
424 }
426 ArrayRef<const CodeGenRegister*> getRoots() const {
427 assert(!(Roots[1] && !Roots[0]) && "Invalid roots array");
428 return makeArrayRef(Roots, !!Roots[0] + !!Roots[1]);
429 }
430 };
432 // Each RegUnitSet is a sorted vector with a name.
433 struct RegUnitSet {
434 typedef std::vector<unsigned>::const_iterator iterator;
436 std::string Name;
437 std::vector<unsigned> Units;
438 unsigned Weight; // Cache the sum of all unit weights.
439 unsigned Order; // Cache the sort key.
441 RegUnitSet() : Weight(0), Order(0) {}
442 };
444 // Base vector for identifying TopoSigs. The contents uniquely identify a
445 // TopoSig, only computeSuperRegs needs to know how.
446 typedef SmallVector<unsigned, 16> TopoSigId;
448 // CodeGenRegBank - Represent a target's registers and the relations between
449 // them.
450 class CodeGenRegBank {
451 SetTheory Sets;
453 std::deque<CodeGenSubRegIndex> SubRegIndices;
454 DenseMap<Record*, CodeGenSubRegIndex*> Def2SubRegIdx;
456 CodeGenSubRegIndex *createSubRegIndex(StringRef Name, StringRef NameSpace);
458 typedef std::map<SmallVector<CodeGenSubRegIndex*, 8>,
459 CodeGenSubRegIndex*> ConcatIdxMap;
460 ConcatIdxMap ConcatIdx;
462 // Registers.
463 std::deque<CodeGenRegister> Registers;
464 StringMap<CodeGenRegister*> RegistersByName;
465 DenseMap<Record*, CodeGenRegister*> Def2Reg;
466 unsigned NumNativeRegUnits;
468 std::map<TopoSigId, unsigned> TopoSigs;
470 // Includes native (0..NumNativeRegUnits-1) and adopted register units.
471 SmallVector<RegUnit, 8> RegUnits;
473 // Register classes.
474 std::list<CodeGenRegisterClass> RegClasses;
475 DenseMap<Record*, CodeGenRegisterClass*> Def2RC;
476 typedef std::map<CodeGenRegisterClass::Key, CodeGenRegisterClass*> RCKeyMap;
477 RCKeyMap Key2RC;
479 // Remember each unique set of register units. Initially, this contains a
480 // unique set for each register class. Simliar sets are coalesced with
481 // pruneUnitSets and new supersets are inferred during computeRegUnitSets.
482 std::vector<RegUnitSet> RegUnitSets;
484 // Map RegisterClass index to the index of the RegUnitSet that contains the
485 // class's units and any inferred RegUnit supersets.
486 //
487 // NOTE: This could grow beyond the number of register classes when we map
488 // register units to lists of unit sets. If the list of unit sets does not
489 // already exist for a register class, we create a new entry in this vector.
490 std::vector<std::vector<unsigned> > RegClassUnitSets;
492 // Give each register unit set an order based on sorting criteria.
493 std::vector<unsigned> RegUnitSetOrder;
495 // Add RC to *2RC maps.
496 void addToMaps(CodeGenRegisterClass*);
498 // Create a synthetic sub-class if it is missing.
499 CodeGenRegisterClass *getOrCreateSubClass(const CodeGenRegisterClass *RC,
500 const CodeGenRegister::Set *Membs,
501 StringRef Name);
503 // Infer missing register classes.
504 void computeInferredRegisterClasses();
505 void inferCommonSubClass(CodeGenRegisterClass *RC);
506 void inferSubClassWithSubReg(CodeGenRegisterClass *RC);
507 void inferMatchingSuperRegClass(CodeGenRegisterClass *RC,
508 unsigned FirstSubRegRC = 0);
510 // Iteratively prune unit sets.
511 void pruneUnitSets();
513 // Compute a weight for each register unit created during getSubRegs.
514 void computeRegUnitWeights();
516 // Create a RegUnitSet for each RegClass and infer superclasses.
517 void computeRegUnitSets();
519 // Populate the Composite map from sub-register relationships.
520 void computeComposites();
522 // Compute a lane mask for each sub-register index.
523 void computeSubRegIndexLaneMasks();
525 public:
526 CodeGenRegBank(RecordKeeper&);
528 SetTheory &getSets() { return Sets; }
530 // Sub-register indices. The first NumNamedIndices are defined by the user
531 // in the .td files. The rest are synthesized such that all sub-registers
532 // have a unique name.
533 const std::deque<CodeGenSubRegIndex> &getSubRegIndices() const {
534 return SubRegIndices;
535 }
537 // Find a SubRegIndex form its Record def.
538 CodeGenSubRegIndex *getSubRegIdx(Record*);
540 // Find or create a sub-register index representing the A+B composition.
541 CodeGenSubRegIndex *getCompositeSubRegIndex(CodeGenSubRegIndex *A,
542 CodeGenSubRegIndex *B);
544 // Find or create a sub-register index representing the concatenation of
545 // non-overlapping sibling indices.
546 CodeGenSubRegIndex *
547 getConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex *, 8>&);
549 void
550 addConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex *, 8> &Parts,
551 CodeGenSubRegIndex *Idx) {
552 ConcatIdx.insert(std::make_pair(Parts, Idx));
553 }
555 const std::deque<CodeGenRegister> &getRegisters() { return Registers; }
556 const StringMap<CodeGenRegister*> &getRegistersByName() {
557 return RegistersByName;
558 }
560 // Find a register from its Record def.
561 CodeGenRegister *getReg(Record*);
563 // Get a Register's index into the Registers array.
564 unsigned getRegIndex(const CodeGenRegister *Reg) const {
565 return Reg->EnumValue - 1;
566 }
568 // Return the number of allocated TopoSigs. The first TopoSig representing
569 // leaf registers is allocated number 0.
570 unsigned getNumTopoSigs() const {
571 return TopoSigs.size();
572 }
574 // Find or create a TopoSig for the given TopoSigId.
575 // This function is only for use by CodeGenRegister::computeSuperRegs().
576 // Others should simply use Reg->getTopoSig().
577 unsigned getTopoSig(const TopoSigId &Id) {
578 return TopoSigs.insert(std::make_pair(Id, TopoSigs.size())).first->second;
579 }
581 // Create a native register unit that is associated with one or two root
582 // registers.
583 unsigned newRegUnit(CodeGenRegister *R0, CodeGenRegister *R1 = nullptr) {
584 RegUnits.resize(RegUnits.size() + 1);
585 RegUnits.back().Roots[0] = R0;
586 RegUnits.back().Roots[1] = R1;
587 return RegUnits.size() - 1;
588 }
590 // Create a new non-native register unit that can be adopted by a register
591 // to increase its pressure. Note that NumNativeRegUnits is not increased.
592 unsigned newRegUnit(unsigned Weight) {
593 RegUnits.resize(RegUnits.size() + 1);
594 RegUnits.back().Weight = Weight;
595 return RegUnits.size() - 1;
596 }
598 // Native units are the singular unit of a leaf register. Register aliasing
599 // is completely characterized by native units. Adopted units exist to give
600 // register additional weight but don't affect aliasing.
601 bool isNativeUnit(unsigned RUID) {
602 return RUID < NumNativeRegUnits;
603 }
605 unsigned getNumNativeRegUnits() const {
606 return NumNativeRegUnits;
607 }
609 RegUnit &getRegUnit(unsigned RUID) { return RegUnits[RUID]; }
610 const RegUnit &getRegUnit(unsigned RUID) const { return RegUnits[RUID]; }
612 std::list<CodeGenRegisterClass> &getRegClasses() { return RegClasses; }
614 const std::list<CodeGenRegisterClass> &getRegClasses() const {
615 return RegClasses;
616 }
618 // Find a register class from its def.
619 CodeGenRegisterClass *getRegClass(Record*);
621 /// getRegisterClassForRegister - Find the register class that contains the
622 /// specified physical register. If the register is not in a register
623 /// class, return null. If the register is in multiple classes, and the
624 /// classes have a superset-subset relationship and the same set of types,
625 /// return the superclass. Otherwise return null.
626 const CodeGenRegisterClass* getRegClassForRegister(Record *R);
628 // Get the sum of unit weights.
629 unsigned getRegUnitSetWeight(const std::vector<unsigned> &Units) const {
630 unsigned Weight = 0;
631 for (std::vector<unsigned>::const_iterator
632 I = Units.begin(), E = Units.end(); I != E; ++I)
633 Weight += getRegUnit(*I).Weight;
634 return Weight;
635 }
637 unsigned getRegSetIDAt(unsigned Order) const {
638 return RegUnitSetOrder[Order];
639 }
640 const RegUnitSet &getRegSetAt(unsigned Order) const {
641 return RegUnitSets[RegUnitSetOrder[Order]];
642 }
644 // Increase a RegUnitWeight.
645 void increaseRegUnitWeight(unsigned RUID, unsigned Inc) {
646 getRegUnit(RUID).Weight += Inc;
647 }
649 // Get the number of register pressure dimensions.
650 unsigned getNumRegPressureSets() const { return RegUnitSets.size(); }
652 // Get a set of register unit IDs for a given dimension of pressure.
653 const RegUnitSet &getRegPressureSet(unsigned Idx) const {
654 return RegUnitSets[Idx];
655 }
657 // The number of pressure set lists may be larget than the number of
658 // register classes if some register units appeared in a list of sets that
659 // did not correspond to an existing register class.
660 unsigned getNumRegClassPressureSetLists() const {
661 return RegClassUnitSets.size();
662 }
664 // Get a list of pressure set IDs for a register class. Liveness of a
665 // register in this class impacts each pressure set in this list by the
666 // weight of the register. An exact solution requires all registers in a
667 // class to have the same class, but it is not strictly guaranteed.
668 ArrayRef<unsigned> getRCPressureSetIDs(unsigned RCIdx) const {
669 return RegClassUnitSets[RCIdx];
670 }
672 // Computed derived records such as missing sub-register indices.
673 void computeDerivedInfo();
675 // Compute the set of registers completely covered by the registers in Regs.
676 // The returned BitVector will have a bit set for each register in Regs,
677 // all sub-registers, and all super-registers that are covered by the
678 // registers in Regs.
679 //
680 // This is used to compute the mask of call-preserved registers from a list
681 // of callee-saves.
682 BitVector computeCoveredRegisters(ArrayRef<Record*> Regs);
684 // Bit mask of lanes that cover their registers. A sub-register index whose
685 // LaneMask is contained in CoveringLanes will be completely covered by
686 // another sub-register with the same or larger lane mask.
687 unsigned CoveringLanes;
688 };
689 }
691 #endif