1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
14 //
15 //===----------------------------------------------------------------------===//
17 #include "X86RecognizableInstr.h"
18 #include "X86DisassemblerShared.h"
19 #include "X86ModRMFilters.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include <string>
23 using namespace llvm;
25 #define MRM_MAPPING \
26 MAP(C0, 32) \
27 MAP(C1, 33) \
28 MAP(C2, 34) \
29 MAP(C3, 35) \
30 MAP(C4, 36) \
31 MAP(C8, 37) \
32 MAP(C9, 38) \
33 MAP(CA, 39) \
34 MAP(CB, 40) \
35 MAP(CF, 41) \
36 MAP(D0, 42) \
37 MAP(D1, 43) \
38 MAP(D4, 44) \
39 MAP(D5, 45) \
40 MAP(D6, 46) \
41 MAP(D7, 47) \
42 MAP(D8, 48) \
43 MAP(D9, 49) \
44 MAP(DA, 50) \
45 MAP(DB, 51) \
46 MAP(DC, 52) \
47 MAP(DD, 53) \
48 MAP(DE, 54) \
49 MAP(DF, 55) \
50 MAP(E0, 56) \
51 MAP(E1, 57) \
52 MAP(E2, 58) \
53 MAP(E3, 59) \
54 MAP(E4, 60) \
55 MAP(E5, 61) \
56 MAP(E8, 62) \
57 MAP(E9, 63) \
58 MAP(EA, 64) \
59 MAP(EB, 65) \
60 MAP(EC, 66) \
61 MAP(ED, 67) \
62 MAP(EE, 68) \
63 MAP(F0, 69) \
64 MAP(F1, 70) \
65 MAP(F2, 71) \
66 MAP(F3, 72) \
67 MAP(F4, 73) \
68 MAP(F5, 74) \
69 MAP(F6, 75) \
70 MAP(F7, 76) \
71 MAP(F8, 77) \
72 MAP(F9, 78) \
73 MAP(FA, 79) \
74 MAP(FB, 80) \
75 MAP(FC, 81) \
76 MAP(FD, 82) \
77 MAP(FE, 83) \
78 MAP(FF, 84)
80 // A clone of X86 since we can't depend on something that is generated.
81 namespace X86Local {
82 enum {
83 Pseudo = 0,
84 RawFrm = 1,
85 AddRegFrm = 2,
86 MRMDestReg = 3,
87 MRMDestMem = 4,
88 MRMSrcReg = 5,
89 MRMSrcMem = 6,
90 RawFrmMemOffs = 7,
91 RawFrmSrc = 8,
92 RawFrmDst = 9,
93 RawFrmDstSrc = 10,
94 RawFrmImm8 = 11,
95 RawFrmImm16 = 12,
96 MRMXr = 14, MRMXm = 15,
97 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
98 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
99 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
100 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
101 #define MAP(from, to) MRM_##from = to,
102 MRM_MAPPING
103 #undef MAP
104 lastMRM
105 };
107 enum {
108 OB = 0, TB = 1, T8 = 2, TA = 3, XOP8 = 4, XOP9 = 5, XOPA = 6
109 };
111 enum {
112 PS = 1, PD = 2, XS = 3, XD = 4
113 };
115 enum {
116 VEX = 1, XOP = 2, EVEX = 3
117 };
119 enum {
120 OpSize16 = 1, OpSize32 = 2
121 };
123 enum {
124 AdSize16 = 1, AdSize32 = 2, AdSize64 = 3
125 };
126 }
128 using namespace X86Disassembler;
130 /// isRegFormat - Indicates whether a particular form requires the Mod field of
131 /// the ModR/M byte to be 0b11.
132 ///
133 /// @param form - The form of the instruction.
134 /// @return - true if the form implies that Mod must be 0b11, false
135 /// otherwise.
136 static bool isRegFormat(uint8_t form) {
137 return (form == X86Local::MRMDestReg ||
138 form == X86Local::MRMSrcReg ||
139 form == X86Local::MRMXr ||
140 (form >= X86Local::MRM0r && form <= X86Local::MRM7r));
141 }
143 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
144 /// Useful for switch statements and the like.
145 ///
146 /// @param init - A reference to the BitsInit to be decoded.
147 /// @return - The field, with the first bit in the BitsInit as the lowest
148 /// order bit.
149 static uint8_t byteFromBitsInit(BitsInit &init) {
150 int width = init.getNumBits();
152 assert(width <= 8 && "Field is too large for uint8_t!");
154 int index;
155 uint8_t mask = 0x01;
157 uint8_t ret = 0;
159 for (index = 0; index < width; index++) {
160 if (static_cast<BitInit*>(init.getBit(index))->getValue())
161 ret |= mask;
163 mask <<= 1;
164 }
166 return ret;
167 }
169 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
170 /// name of the field.
171 ///
172 /// @param rec - The record from which to extract the value.
173 /// @param name - The name of the field in the record.
174 /// @return - The field, as translated by byteFromBitsInit().
175 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
176 BitsInit* bits = rec->getValueAsBitsInit(name);
177 return byteFromBitsInit(*bits);
178 }
180 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
181 const CodeGenInstruction &insn,
182 InstrUID uid) {
183 UID = uid;
185 Rec = insn.TheDef;
186 Name = Rec->getName();
187 Spec = &tables.specForUID(UID);
189 if (!Rec->isSubClassOf("X86Inst")) {
190 ShouldBeEmitted = false;
191 return;
192 }
194 OpPrefix = byteFromRec(Rec, "OpPrefixBits");
195 OpMap = byteFromRec(Rec, "OpMapBits");
196 Opcode = byteFromRec(Rec, "Opcode");
197 Form = byteFromRec(Rec, "FormBits");
198 Encoding = byteFromRec(Rec, "OpEncBits");
200 OpSize = byteFromRec(Rec, "OpSizeBits");
201 AdSize = byteFromRec(Rec, "AdSizeBits");
202 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
203 HasVEX_4V = Rec->getValueAsBit("hasVEX_4V");
204 HasVEX_4VOp3 = Rec->getValueAsBit("hasVEX_4VOp3");
205 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix");
206 HasMemOp4Prefix = Rec->getValueAsBit("hasMemOp4Prefix");
207 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
208 HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2");
209 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K");
210 HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z");
211 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B");
212 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
213 ForceDisassemble = Rec->getValueAsBit("ForceDisassemble");
214 CD8_Scale = byteFromRec(Rec, "CD8_Scale");
216 Name = Rec->getName();
217 AsmString = Rec->getValueAsString("AsmString");
219 Operands = &insn.Operands.OperandList;
221 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L");
223 // Check for 64-bit inst which does not require REX
224 Is32Bit = false;
225 Is64Bit = false;
226 // FIXME: Is there some better way to check for In64BitMode?
227 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
228 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
229 if (Predicates[i]->getName().find("Not64Bit") != Name.npos ||
230 Predicates[i]->getName().find("In32Bit") != Name.npos) {
231 Is32Bit = true;
232 break;
233 }
234 if (Predicates[i]->getName().find("In64Bit") != Name.npos) {
235 Is64Bit = true;
236 break;
237 }
238 }
240 if (Form == X86Local::Pseudo || (IsCodeGenOnly && !ForceDisassemble)) {
241 ShouldBeEmitted = false;
242 return;
243 }
245 // Special case since there is no attribute class for 64-bit and VEX
246 if (Name == "VMASKMOVDQU64") {
247 ShouldBeEmitted = false;
248 return;
249 }
251 ShouldBeEmitted = true;
252 }
254 void RecognizableInstr::processInstr(DisassemblerTables &tables,
255 const CodeGenInstruction &insn,
256 InstrUID uid)
257 {
258 // Ignore "asm parser only" instructions.
259 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
260 return;
262 RecognizableInstr recogInstr(tables, insn, uid);
264 if (recogInstr.shouldBeEmitted()) {
265 recogInstr.emitInstructionSpecifier();
266 recogInstr.emitDecodePath(tables);
267 }
268 }
270 #define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \
271 (HasEVEX_K && HasEVEX_B ? n##_K_B : \
272 (HasEVEX_KZ ? n##_KZ : \
273 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n)))))
275 InstructionContext RecognizableInstr::insnContext() const {
276 InstructionContext insnContext;
278 if (Encoding == X86Local::EVEX) {
279 if (HasVEX_LPrefix && HasEVEX_L2Prefix) {
280 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n";
281 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled");
282 }
283 // VEX_L & VEX_W
284 if (HasVEX_LPrefix && HasVEX_WPrefix) {
285 if (OpPrefix == X86Local::PD)
286 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE);
287 else if (OpPrefix == X86Local::XS)
288 insnContext = EVEX_KB(IC_EVEX_L_W_XS);
289 else if (OpPrefix == X86Local::XD)
290 insnContext = EVEX_KB(IC_EVEX_L_W_XD);
291 else if (OpPrefix == X86Local::PS)
292 insnContext = EVEX_KB(IC_EVEX_L_W);
293 else {
294 errs() << "Instruction does not use a prefix: " << Name << "\n";
295 llvm_unreachable("Invalid prefix");
296 }
297 } else if (HasVEX_LPrefix) {
298 // VEX_L
299 if (OpPrefix == X86Local::PD)
300 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE);
301 else if (OpPrefix == X86Local::XS)
302 insnContext = EVEX_KB(IC_EVEX_L_XS);
303 else if (OpPrefix == X86Local::XD)
304 insnContext = EVEX_KB(IC_EVEX_L_XD);
305 else if (OpPrefix == X86Local::PS)
306 insnContext = EVEX_KB(IC_EVEX_L);
307 else {
308 errs() << "Instruction does not use a prefix: " << Name << "\n";
309 llvm_unreachable("Invalid prefix");
310 }
311 }
312 else if (HasEVEX_L2Prefix && HasVEX_WPrefix) {
313 // EVEX_L2 & VEX_W
314 if (OpPrefix == X86Local::PD)
315 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE);
316 else if (OpPrefix == X86Local::XS)
317 insnContext = EVEX_KB(IC_EVEX_L2_W_XS);
318 else if (OpPrefix == X86Local::XD)
319 insnContext = EVEX_KB(IC_EVEX_L2_W_XD);
320 else if (OpPrefix == X86Local::PS)
321 insnContext = EVEX_KB(IC_EVEX_L2_W);
322 else {
323 errs() << "Instruction does not use a prefix: " << Name << "\n";
324 llvm_unreachable("Invalid prefix");
325 }
326 } else if (HasEVEX_L2Prefix) {
327 // EVEX_L2
328 if (OpPrefix == X86Local::PD)
329 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE);
330 else if (OpPrefix == X86Local::XD)
331 insnContext = EVEX_KB(IC_EVEX_L2_XD);
332 else if (OpPrefix == X86Local::XS)
333 insnContext = EVEX_KB(IC_EVEX_L2_XS);
334 else if (OpPrefix == X86Local::PS)
335 insnContext = EVEX_KB(IC_EVEX_L2);
336 else {
337 errs() << "Instruction does not use a prefix: " << Name << "\n";
338 llvm_unreachable("Invalid prefix");
339 }
340 }
341 else if (HasVEX_WPrefix) {
342 // VEX_W
343 if (OpPrefix == X86Local::PD)
344 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE);
345 else if (OpPrefix == X86Local::XS)
346 insnContext = EVEX_KB(IC_EVEX_W_XS);
347 else if (OpPrefix == X86Local::XD)
348 insnContext = EVEX_KB(IC_EVEX_W_XD);
349 else if (OpPrefix == X86Local::PS)
350 insnContext = EVEX_KB(IC_EVEX_W);
351 else {
352 errs() << "Instruction does not use a prefix: " << Name << "\n";
353 llvm_unreachable("Invalid prefix");
354 }
355 }
356 // No L, no W
357 else if (OpPrefix == X86Local::PD)
358 insnContext = EVEX_KB(IC_EVEX_OPSIZE);
359 else if (OpPrefix == X86Local::XD)
360 insnContext = EVEX_KB(IC_EVEX_XD);
361 else if (OpPrefix == X86Local::XS)
362 insnContext = EVEX_KB(IC_EVEX_XS);
363 else
364 insnContext = EVEX_KB(IC_EVEX);
365 /// eof EVEX
366 } else if (Encoding == X86Local::VEX || Encoding == X86Local::XOP) {
367 if (HasVEX_LPrefix && HasVEX_WPrefix) {
368 if (OpPrefix == X86Local::PD)
369 insnContext = IC_VEX_L_W_OPSIZE;
370 else if (OpPrefix == X86Local::XS)
371 insnContext = IC_VEX_L_W_XS;
372 else if (OpPrefix == X86Local::XD)
373 insnContext = IC_VEX_L_W_XD;
374 else if (OpPrefix == X86Local::PS)
375 insnContext = IC_VEX_L_W;
376 else {
377 errs() << "Instruction does not use a prefix: " << Name << "\n";
378 llvm_unreachable("Invalid prefix");
379 }
380 } else if (OpPrefix == X86Local::PD && HasVEX_LPrefix)
381 insnContext = IC_VEX_L_OPSIZE;
382 else if (OpPrefix == X86Local::PD && HasVEX_WPrefix)
383 insnContext = IC_VEX_W_OPSIZE;
384 else if (OpPrefix == X86Local::PD)
385 insnContext = IC_VEX_OPSIZE;
386 else if (HasVEX_LPrefix && OpPrefix == X86Local::XS)
387 insnContext = IC_VEX_L_XS;
388 else if (HasVEX_LPrefix && OpPrefix == X86Local::XD)
389 insnContext = IC_VEX_L_XD;
390 else if (HasVEX_WPrefix && OpPrefix == X86Local::XS)
391 insnContext = IC_VEX_W_XS;
392 else if (HasVEX_WPrefix && OpPrefix == X86Local::XD)
393 insnContext = IC_VEX_W_XD;
394 else if (HasVEX_WPrefix && OpPrefix == X86Local::PS)
395 insnContext = IC_VEX_W;
396 else if (HasVEX_LPrefix && OpPrefix == X86Local::PS)
397 insnContext = IC_VEX_L;
398 else if (OpPrefix == X86Local::XD)
399 insnContext = IC_VEX_XD;
400 else if (OpPrefix == X86Local::XS)
401 insnContext = IC_VEX_XS;
402 else if (OpPrefix == X86Local::PS)
403 insnContext = IC_VEX;
404 else {
405 errs() << "Instruction does not use a prefix: " << Name << "\n";
406 llvm_unreachable("Invalid prefix");
407 }
408 } else if (Is64Bit || HasREX_WPrefix || AdSize == X86Local::AdSize64) {
409 if (HasREX_WPrefix && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD))
410 insnContext = IC_64BIT_REXW_OPSIZE;
411 else if (HasREX_WPrefix && AdSize == X86Local::AdSize32)
412 insnContext = IC_64BIT_REXW_ADSIZE;
413 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD)
414 insnContext = IC_64BIT_XD_OPSIZE;
415 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
416 insnContext = IC_64BIT_XS_OPSIZE;
417 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize32)
418 insnContext = IC_64BIT_OPSIZE_ADSIZE;
419 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
420 insnContext = IC_64BIT_OPSIZE;
421 else if (AdSize == X86Local::AdSize32)
422 insnContext = IC_64BIT_ADSIZE;
423 else if (HasREX_WPrefix && OpPrefix == X86Local::XS)
424 insnContext = IC_64BIT_REXW_XS;
425 else if (HasREX_WPrefix && OpPrefix == X86Local::XD)
426 insnContext = IC_64BIT_REXW_XD;
427 else if (OpPrefix == X86Local::XD)
428 insnContext = IC_64BIT_XD;
429 else if (OpPrefix == X86Local::XS)
430 insnContext = IC_64BIT_XS;
431 else if (HasREX_WPrefix)
432 insnContext = IC_64BIT_REXW;
433 else
434 insnContext = IC_64BIT;
435 } else {
436 if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD)
437 insnContext = IC_XD_OPSIZE;
438 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
439 insnContext = IC_XS_OPSIZE;
440 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize16)
441 insnContext = IC_OPSIZE_ADSIZE;
442 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
443 insnContext = IC_OPSIZE;
444 else if (AdSize == X86Local::AdSize16)
445 insnContext = IC_ADSIZE;
446 else if (OpPrefix == X86Local::XD)
447 insnContext = IC_XD;
448 else if (OpPrefix == X86Local::XS)
449 insnContext = IC_XS;
450 else
451 insnContext = IC;
452 }
454 return insnContext;
455 }
457 void RecognizableInstr::adjustOperandEncoding(OperandEncoding &encoding) {
458 // The scaling factor for AVX512 compressed displacement encoding is an
459 // instruction attribute. Adjust the ModRM encoding type to include the
460 // scale for compressed displacement.
461 if (encoding != ENCODING_RM || CD8_Scale == 0)
462 return;
463 encoding = (OperandEncoding)(encoding + Log2_32(CD8_Scale));
464 assert(encoding <= ENCODING_RM_CD64 && "Invalid CDisp scaling");
465 }
467 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
468 unsigned &physicalOperandIndex,
469 unsigned &numPhysicalOperands,
470 const unsigned *operandMapping,
471 OperandEncoding (*encodingFromString)
472 (const std::string&,
473 uint8_t OpSize)) {
474 if (optional) {
475 if (physicalOperandIndex >= numPhysicalOperands)
476 return;
477 } else {
478 assert(physicalOperandIndex < numPhysicalOperands);
479 }
481 while (operandMapping[operandIndex] != operandIndex) {
482 Spec->operands[operandIndex].encoding = ENCODING_DUP;
483 Spec->operands[operandIndex].type =
484 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
485 ++operandIndex;
486 }
488 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
490 OperandEncoding encoding = encodingFromString(typeName, OpSize);
491 // Adjust the encoding type for an operand based on the instruction.
492 adjustOperandEncoding(encoding);
493 Spec->operands[operandIndex].encoding = encoding;
494 Spec->operands[operandIndex].type = typeFromString(typeName,
495 HasREX_WPrefix, OpSize);
497 ++operandIndex;
498 ++physicalOperandIndex;
499 }
501 void RecognizableInstr::emitInstructionSpecifier() {
502 Spec->name = Name;
504 Spec->insnContext = insnContext();
506 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
508 unsigned numOperands = OperandList.size();
509 unsigned numPhysicalOperands = 0;
511 // operandMapping maps from operands in OperandList to their originals.
512 // If operandMapping[i] != i, then the entry is a duplicate.
513 unsigned operandMapping[X86_MAX_OPERANDS];
514 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
516 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
517 if (!OperandList[operandIndex].Constraints.empty()) {
518 const CGIOperandList::ConstraintInfo &Constraint =
519 OperandList[operandIndex].Constraints[0];
520 if (Constraint.isTied()) {
521 operandMapping[operandIndex] = operandIndex;
522 operandMapping[Constraint.getTiedOperand()] = operandIndex;
523 } else {
524 ++numPhysicalOperands;
525 operandMapping[operandIndex] = operandIndex;
526 }
527 } else {
528 ++numPhysicalOperands;
529 operandMapping[operandIndex] = operandIndex;
530 }
531 }
533 #define HANDLE_OPERAND(class) \
534 handleOperand(false, \
535 operandIndex, \
536 physicalOperandIndex, \
537 numPhysicalOperands, \
538 operandMapping, \
539 class##EncodingFromString);
541 #define HANDLE_OPTIONAL(class) \
542 handleOperand(true, \
543 operandIndex, \
544 physicalOperandIndex, \
545 numPhysicalOperands, \
546 operandMapping, \
547 class##EncodingFromString);
549 // operandIndex should always be < numOperands
550 unsigned operandIndex = 0;
551 // physicalOperandIndex should always be < numPhysicalOperands
552 unsigned physicalOperandIndex = 0;
554 // Given the set of prefix bits, how many additional operands does the
555 // instruction have?
556 unsigned additionalOperands = 0;
557 if (HasVEX_4V || HasVEX_4VOp3)
558 ++additionalOperands;
559 if (HasEVEX_K)
560 ++additionalOperands;
562 switch (Form) {
563 default: llvm_unreachable("Unhandled form");
564 case X86Local::RawFrmSrc:
565 HANDLE_OPERAND(relocation);
566 return;
567 case X86Local::RawFrmDst:
568 HANDLE_OPERAND(relocation);
569 return;
570 case X86Local::RawFrmDstSrc:
571 HANDLE_OPERAND(relocation);
572 HANDLE_OPERAND(relocation);
573 return;
574 case X86Local::RawFrm:
575 // Operand 1 (optional) is an address or immediate.
576 // Operand 2 (optional) is an immediate.
577 assert(numPhysicalOperands <= 2 &&
578 "Unexpected number of operands for RawFrm");
579 HANDLE_OPTIONAL(relocation)
580 HANDLE_OPTIONAL(immediate)
581 break;
582 case X86Local::RawFrmMemOffs:
583 // Operand 1 is an address.
584 HANDLE_OPERAND(relocation);
585 break;
586 case X86Local::AddRegFrm:
587 // Operand 1 is added to the opcode.
588 // Operand 2 (optional) is an address.
589 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
590 "Unexpected number of operands for AddRegFrm");
591 HANDLE_OPERAND(opcodeModifier)
592 HANDLE_OPTIONAL(relocation)
593 break;
594 case X86Local::MRMDestReg:
595 // Operand 1 is a register operand in the R/M field.
596 // - In AVX512 there may be a mask operand here -
597 // Operand 2 is a register operand in the Reg/Opcode field.
598 // - In AVX, there is a register operand in the VEX.vvvv field here -
599 // Operand 3 (optional) is an immediate.
600 assert(numPhysicalOperands >= 2 + additionalOperands &&
601 numPhysicalOperands <= 3 + additionalOperands &&
602 "Unexpected number of operands for MRMDestRegFrm");
604 HANDLE_OPERAND(rmRegister)
605 if (HasEVEX_K)
606 HANDLE_OPERAND(writemaskRegister)
608 if (HasVEX_4V)
609 // FIXME: In AVX, the register below becomes the one encoded
610 // in ModRMVEX and the one above the one in the VEX.VVVV field
611 HANDLE_OPERAND(vvvvRegister)
613 HANDLE_OPERAND(roRegister)
614 HANDLE_OPTIONAL(immediate)
615 break;
616 case X86Local::MRMDestMem:
617 // Operand 1 is a memory operand (possibly SIB-extended)
618 // Operand 2 is a register operand in the Reg/Opcode field.
619 // - In AVX, there is a register operand in the VEX.vvvv field here -
620 // Operand 3 (optional) is an immediate.
621 assert(numPhysicalOperands >= 2 + additionalOperands &&
622 numPhysicalOperands <= 3 + additionalOperands &&
623 "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
625 HANDLE_OPERAND(memory)
627 if (HasEVEX_K)
628 HANDLE_OPERAND(writemaskRegister)
630 if (HasVEX_4V)
631 // FIXME: In AVX, the register below becomes the one encoded
632 // in ModRMVEX and the one above the one in the VEX.VVVV field
633 HANDLE_OPERAND(vvvvRegister)
635 HANDLE_OPERAND(roRegister)
636 HANDLE_OPTIONAL(immediate)
637 break;
638 case X86Local::MRMSrcReg:
639 // Operand 1 is a register operand in the Reg/Opcode field.
640 // Operand 2 is a register operand in the R/M field.
641 // - In AVX, there is a register operand in the VEX.vvvv field here -
642 // Operand 3 (optional) is an immediate.
643 // Operand 4 (optional) is an immediate.
645 assert(numPhysicalOperands >= 2 + additionalOperands &&
646 numPhysicalOperands <= 4 + additionalOperands &&
647 "Unexpected number of operands for MRMSrcRegFrm");
649 HANDLE_OPERAND(roRegister)
651 if (HasEVEX_K)
652 HANDLE_OPERAND(writemaskRegister)
654 if (HasVEX_4V)
655 // FIXME: In AVX, the register below becomes the one encoded
656 // in ModRMVEX and the one above the one in the VEX.VVVV field
657 HANDLE_OPERAND(vvvvRegister)
659 if (HasMemOp4Prefix)
660 HANDLE_OPERAND(immediate)
662 HANDLE_OPERAND(rmRegister)
664 if (HasVEX_4VOp3)
665 HANDLE_OPERAND(vvvvRegister)
667 if (!HasMemOp4Prefix)
668 HANDLE_OPTIONAL(immediate)
669 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
670 HANDLE_OPTIONAL(immediate)
671 break;
672 case X86Local::MRMSrcMem:
673 // Operand 1 is a register operand in the Reg/Opcode field.
674 // Operand 2 is a memory operand (possibly SIB-extended)
675 // - In AVX, there is a register operand in the VEX.vvvv field here -
676 // Operand 3 (optional) is an immediate.
678 assert(numPhysicalOperands >= 2 + additionalOperands &&
679 numPhysicalOperands <= 4 + additionalOperands &&
680 "Unexpected number of operands for MRMSrcMemFrm");
682 HANDLE_OPERAND(roRegister)
684 if (HasEVEX_K)
685 HANDLE_OPERAND(writemaskRegister)
687 if (HasVEX_4V)
688 // FIXME: In AVX, the register below becomes the one encoded
689 // in ModRMVEX and the one above the one in the VEX.VVVV field
690 HANDLE_OPERAND(vvvvRegister)
692 if (HasMemOp4Prefix)
693 HANDLE_OPERAND(immediate)
695 HANDLE_OPERAND(memory)
697 if (HasVEX_4VOp3)
698 HANDLE_OPERAND(vvvvRegister)
700 if (!HasMemOp4Prefix)
701 HANDLE_OPTIONAL(immediate)
702 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
703 break;
704 case X86Local::MRMXr:
705 case X86Local::MRM0r:
706 case X86Local::MRM1r:
707 case X86Local::MRM2r:
708 case X86Local::MRM3r:
709 case X86Local::MRM4r:
710 case X86Local::MRM5r:
711 case X86Local::MRM6r:
712 case X86Local::MRM7r:
713 // Operand 1 is a register operand in the R/M field.
714 // Operand 2 (optional) is an immediate or relocation.
715 // Operand 3 (optional) is an immediate.
716 assert(numPhysicalOperands >= 0 + additionalOperands &&
717 numPhysicalOperands <= 3 + additionalOperands &&
718 "Unexpected number of operands for MRMnr");
720 if (HasVEX_4V)
721 HANDLE_OPERAND(vvvvRegister)
723 if (HasEVEX_K)
724 HANDLE_OPERAND(writemaskRegister)
725 HANDLE_OPTIONAL(rmRegister)
726 HANDLE_OPTIONAL(relocation)
727 HANDLE_OPTIONAL(immediate)
728 break;
729 case X86Local::MRMXm:
730 case X86Local::MRM0m:
731 case X86Local::MRM1m:
732 case X86Local::MRM2m:
733 case X86Local::MRM3m:
734 case X86Local::MRM4m:
735 case X86Local::MRM5m:
736 case X86Local::MRM6m:
737 case X86Local::MRM7m:
738 // Operand 1 is a memory operand (possibly SIB-extended)
739 // Operand 2 (optional) is an immediate or relocation.
740 assert(numPhysicalOperands >= 1 + additionalOperands &&
741 numPhysicalOperands <= 2 + additionalOperands &&
742 "Unexpected number of operands for MRMnm");
744 if (HasVEX_4V)
745 HANDLE_OPERAND(vvvvRegister)
746 if (HasEVEX_K)
747 HANDLE_OPERAND(writemaskRegister)
748 HANDLE_OPERAND(memory)
749 HANDLE_OPTIONAL(relocation)
750 break;
751 case X86Local::RawFrmImm8:
752 // operand 1 is a 16-bit immediate
753 // operand 2 is an 8-bit immediate
754 assert(numPhysicalOperands == 2 &&
755 "Unexpected number of operands for X86Local::RawFrmImm8");
756 HANDLE_OPERAND(immediate)
757 HANDLE_OPERAND(immediate)
758 break;
759 case X86Local::RawFrmImm16:
760 // operand 1 is a 16-bit immediate
761 // operand 2 is a 16-bit immediate
762 HANDLE_OPERAND(immediate)
763 HANDLE_OPERAND(immediate)
764 break;
765 case X86Local::MRM_F8:
766 if (Opcode == 0xc6) {
767 assert(numPhysicalOperands == 1 &&
768 "Unexpected number of operands for X86Local::MRM_F8");
769 HANDLE_OPERAND(immediate)
770 } else if (Opcode == 0xc7) {
771 assert(numPhysicalOperands == 1 &&
772 "Unexpected number of operands for X86Local::MRM_F8");
773 HANDLE_OPERAND(relocation)
774 }
775 break;
776 case X86Local::MRM_C0: case X86Local::MRM_C1: case X86Local::MRM_C2:
777 case X86Local::MRM_C3: case X86Local::MRM_C4: case X86Local::MRM_C8:
778 case X86Local::MRM_C9: case X86Local::MRM_CA: case X86Local::MRM_CB:
779 case X86Local::MRM_CF: case X86Local::MRM_D0: case X86Local::MRM_D1:
780 case X86Local::MRM_D4: case X86Local::MRM_D5: case X86Local::MRM_D6:
781 case X86Local::MRM_D7: case X86Local::MRM_D8: case X86Local::MRM_D9:
782 case X86Local::MRM_DA: case X86Local::MRM_DB: case X86Local::MRM_DC:
783 case X86Local::MRM_DD: case X86Local::MRM_DE: case X86Local::MRM_DF:
784 case X86Local::MRM_E0: case X86Local::MRM_E1: case X86Local::MRM_E2:
785 case X86Local::MRM_E3: case X86Local::MRM_E4: case X86Local::MRM_E5:
786 case X86Local::MRM_E8: case X86Local::MRM_E9: case X86Local::MRM_EA:
787 case X86Local::MRM_EB: case X86Local::MRM_EC: case X86Local::MRM_ED:
788 case X86Local::MRM_EE: case X86Local::MRM_F0: case X86Local::MRM_F1:
789 case X86Local::MRM_F2: case X86Local::MRM_F3: case X86Local::MRM_F4:
790 case X86Local::MRM_F5: case X86Local::MRM_F6: case X86Local::MRM_F7:
791 case X86Local::MRM_F9: case X86Local::MRM_FA: case X86Local::MRM_FB:
792 case X86Local::MRM_FC: case X86Local::MRM_FD: case X86Local::MRM_FE:
793 case X86Local::MRM_FF:
794 // Ignored.
795 break;
796 }
798 #undef HANDLE_OPERAND
799 #undef HANDLE_OPTIONAL
800 }
802 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
803 // Special cases where the LLVM tables are not complete
805 #define MAP(from, to) \
806 case X86Local::MRM_##from: \
807 filter = new ExactFilter(0x##from); \
808 break;
810 OpcodeType opcodeType = (OpcodeType)-1;
812 ModRMFilter* filter = nullptr;
813 uint8_t opcodeToSet = 0;
815 switch (OpMap) {
816 default: llvm_unreachable("Invalid map!");
817 case X86Local::OB:
818 case X86Local::TB:
819 case X86Local::T8:
820 case X86Local::TA:
821 case X86Local::XOP8:
822 case X86Local::XOP9:
823 case X86Local::XOPA:
824 switch (OpMap) {
825 default: llvm_unreachable("Unexpected map!");
826 case X86Local::OB: opcodeType = ONEBYTE; break;
827 case X86Local::TB: opcodeType = TWOBYTE; break;
828 case X86Local::T8: opcodeType = THREEBYTE_38; break;
829 case X86Local::TA: opcodeType = THREEBYTE_3A; break;
830 case X86Local::XOP8: opcodeType = XOP8_MAP; break;
831 case X86Local::XOP9: opcodeType = XOP9_MAP; break;
832 case X86Local::XOPA: opcodeType = XOPA_MAP; break;
833 }
835 switch (Form) {
836 default:
837 filter = new DumbFilter();
838 break;
839 case X86Local::MRMDestReg: case X86Local::MRMDestMem:
840 case X86Local::MRMSrcReg: case X86Local::MRMSrcMem:
841 case X86Local::MRMXr: case X86Local::MRMXm:
842 filter = new ModFilter(isRegFormat(Form));
843 break;
844 case X86Local::MRM0r: case X86Local::MRM1r:
845 case X86Local::MRM2r: case X86Local::MRM3r:
846 case X86Local::MRM4r: case X86Local::MRM5r:
847 case X86Local::MRM6r: case X86Local::MRM7r:
848 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
849 break;
850 case X86Local::MRM0m: case X86Local::MRM1m:
851 case X86Local::MRM2m: case X86Local::MRM3m:
852 case X86Local::MRM4m: case X86Local::MRM5m:
853 case X86Local::MRM6m: case X86Local::MRM7m:
854 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
855 break;
856 MRM_MAPPING
857 } // switch (Form)
859 opcodeToSet = Opcode;
860 break;
861 } // switch (OpMap)
863 unsigned AddressSize = 0;
864 switch (AdSize) {
865 case X86Local::AdSize16: AddressSize = 16; break;
866 case X86Local::AdSize32: AddressSize = 32; break;
867 case X86Local::AdSize64: AddressSize = 64; break;
868 }
870 assert(opcodeType != (OpcodeType)-1 &&
871 "Opcode type not set");
872 assert(filter && "Filter not set");
874 if (Form == X86Local::AddRegFrm) {
875 assert(((opcodeToSet & 7) == 0) &&
876 "ADDREG_FRM opcode not aligned");
878 uint8_t currentOpcode;
880 for (currentOpcode = opcodeToSet;
881 currentOpcode < opcodeToSet + 8;
882 ++currentOpcode)
883 tables.setTableFields(opcodeType,
884 insnContext(),
885 currentOpcode,
886 *filter,
887 UID, Is32Bit, IgnoresVEX_L, AddressSize);
888 } else {
889 tables.setTableFields(opcodeType,
890 insnContext(),
891 opcodeToSet,
892 *filter,
893 UID, Is32Bit, IgnoresVEX_L, AddressSize);
894 }
896 delete filter;
898 #undef MAP
899 }
901 #define TYPE(str, type) if (s == str) return type;
902 OperandType RecognizableInstr::typeFromString(const std::string &s,
903 bool hasREX_WPrefix,
904 uint8_t OpSize) {
905 if(hasREX_WPrefix) {
906 // For instructions with a REX_W prefix, a declared 32-bit register encoding
907 // is special.
908 TYPE("GR32", TYPE_R32)
909 }
910 if(OpSize == X86Local::OpSize16) {
911 // For OpSize16 instructions, a declared 16-bit register or
912 // immediate encoding is special.
913 TYPE("GR16", TYPE_Rv)
914 TYPE("i16imm", TYPE_IMMv)
915 } else if(OpSize == X86Local::OpSize32) {
916 // For OpSize32 instructions, a declared 32-bit register or
917 // immediate encoding is special.
918 TYPE("GR32", TYPE_Rv)
919 }
920 TYPE("i16mem", TYPE_Mv)
921 TYPE("i16imm", TYPE_IMM16)
922 TYPE("i16i8imm", TYPE_IMMv)
923 TYPE("GR16", TYPE_R16)
924 TYPE("i32mem", TYPE_Mv)
925 TYPE("i32imm", TYPE_IMMv)
926 TYPE("i32i8imm", TYPE_IMM32)
927 TYPE("GR32", TYPE_R32)
928 TYPE("GR32orGR64", TYPE_R32)
929 TYPE("i64mem", TYPE_Mv)
930 TYPE("i64i32imm", TYPE_IMM64)
931 TYPE("i64i8imm", TYPE_IMM64)
932 TYPE("GR64", TYPE_R64)
933 TYPE("i8mem", TYPE_M8)
934 TYPE("i8imm", TYPE_IMM8)
935 TYPE("u8imm", TYPE_UIMM8)
936 TYPE("GR8", TYPE_R8)
937 TYPE("VR128", TYPE_XMM128)
938 TYPE("VR128X", TYPE_XMM128)
939 TYPE("f128mem", TYPE_M128)
940 TYPE("f256mem", TYPE_M256)
941 TYPE("f512mem", TYPE_M512)
942 TYPE("FR64", TYPE_XMM64)
943 TYPE("FR64X", TYPE_XMM64)
944 TYPE("f64mem", TYPE_M64FP)
945 TYPE("sdmem", TYPE_M64FP)
946 TYPE("FR32", TYPE_XMM32)
947 TYPE("FR32X", TYPE_XMM32)
948 TYPE("f32mem", TYPE_M32FP)
949 TYPE("ssmem", TYPE_M32FP)
950 TYPE("RST", TYPE_ST)
951 TYPE("i128mem", TYPE_M128)
952 TYPE("i256mem", TYPE_M256)
953 TYPE("i512mem", TYPE_M512)
954 TYPE("i64i32imm_pcrel", TYPE_REL64)
955 TYPE("i16imm_pcrel", TYPE_REL16)
956 TYPE("i32imm_pcrel", TYPE_REL32)
957 TYPE("SSECC", TYPE_IMM3)
958 TYPE("AVXCC", TYPE_IMM5)
959 TYPE("AVX512RC", TYPE_IMM32)
960 TYPE("brtarget32", TYPE_RELv)
961 TYPE("brtarget16", TYPE_RELv)
962 TYPE("brtarget8", TYPE_REL8)
963 TYPE("f80mem", TYPE_M80FP)
964 TYPE("lea64_32mem", TYPE_LEA)
965 TYPE("lea64mem", TYPE_LEA)
966 TYPE("VR64", TYPE_MM64)
967 TYPE("i64imm", TYPE_IMMv)
968 TYPE("anymem", TYPE_M)
969 TYPE("opaque32mem", TYPE_M1616)
970 TYPE("opaque48mem", TYPE_M1632)
971 TYPE("opaque80mem", TYPE_M1664)
972 TYPE("opaque512mem", TYPE_M512)
973 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
974 TYPE("DEBUG_REG", TYPE_DEBUGREG)
975 TYPE("CONTROL_REG", TYPE_CONTROLREG)
976 TYPE("srcidx8", TYPE_SRCIDX8)
977 TYPE("srcidx16", TYPE_SRCIDX16)
978 TYPE("srcidx32", TYPE_SRCIDX32)
979 TYPE("srcidx64", TYPE_SRCIDX64)
980 TYPE("dstidx8", TYPE_DSTIDX8)
981 TYPE("dstidx16", TYPE_DSTIDX16)
982 TYPE("dstidx32", TYPE_DSTIDX32)
983 TYPE("dstidx64", TYPE_DSTIDX64)
984 TYPE("offset16_8", TYPE_MOFFS8)
985 TYPE("offset16_16", TYPE_MOFFS16)
986 TYPE("offset16_32", TYPE_MOFFS32)
987 TYPE("offset32_8", TYPE_MOFFS8)
988 TYPE("offset32_16", TYPE_MOFFS16)
989 TYPE("offset32_32", TYPE_MOFFS32)
990 TYPE("offset32_64", TYPE_MOFFS64)
991 TYPE("offset64_8", TYPE_MOFFS8)
992 TYPE("offset64_16", TYPE_MOFFS16)
993 TYPE("offset64_32", TYPE_MOFFS32)
994 TYPE("offset64_64", TYPE_MOFFS64)
995 TYPE("VR256", TYPE_XMM256)
996 TYPE("VR256X", TYPE_XMM256)
997 TYPE("VR512", TYPE_XMM512)
998 TYPE("VK1", TYPE_VK1)
999 TYPE("VK1WM", TYPE_VK1)
1000 TYPE("VK2", TYPE_VK2)
1001 TYPE("VK2WM", TYPE_VK2)
1002 TYPE("VK4", TYPE_VK4)
1003 TYPE("VK4WM", TYPE_VK4)
1004 TYPE("VK8", TYPE_VK8)
1005 TYPE("VK8WM", TYPE_VK8)
1006 TYPE("VK16", TYPE_VK16)
1007 TYPE("VK16WM", TYPE_VK16)
1008 TYPE("VK32", TYPE_VK32)
1009 TYPE("VK32WM", TYPE_VK32)
1010 TYPE("VK64", TYPE_VK64)
1011 TYPE("VK64WM", TYPE_VK64)
1012 TYPE("GR16_NOAX", TYPE_Rv)
1013 TYPE("GR32_NOAX", TYPE_Rv)
1014 TYPE("GR64_NOAX", TYPE_R64)
1015 TYPE("vx32mem", TYPE_M32)
1016 TYPE("vy32mem", TYPE_M32)
1017 TYPE("vz32mem", TYPE_M32)
1018 TYPE("vx64mem", TYPE_M64)
1019 TYPE("vy64mem", TYPE_M64)
1020 TYPE("vy64xmem", TYPE_M64)
1021 TYPE("vz64mem", TYPE_M64)
1022 errs() << "Unhandled type string " << s << "\n";
1023 llvm_unreachable("Unhandled type string");
1024 }
1025 #undef TYPE
1027 #define ENCODING(str, encoding) if (s == str) return encoding;
1028 OperandEncoding
1029 RecognizableInstr::immediateEncodingFromString(const std::string &s,
1030 uint8_t OpSize) {
1031 if(OpSize != X86Local::OpSize16) {
1032 // For instructions without an OpSize prefix, a declared 16-bit register or
1033 // immediate encoding is special.
1034 ENCODING("i16imm", ENCODING_IW)
1035 }
1036 ENCODING("i32i8imm", ENCODING_IB)
1037 ENCODING("SSECC", ENCODING_IB)
1038 ENCODING("AVXCC", ENCODING_IB)
1039 ENCODING("AVX512RC", ENCODING_IB)
1040 ENCODING("i16imm", ENCODING_Iv)
1041 ENCODING("i16i8imm", ENCODING_IB)
1042 ENCODING("i32imm", ENCODING_Iv)
1043 ENCODING("i64i32imm", ENCODING_ID)
1044 ENCODING("i64i8imm", ENCODING_IB)
1045 ENCODING("i8imm", ENCODING_IB)
1046 ENCODING("u8imm", ENCODING_IB)
1047 // This is not a typo. Instructions like BLENDVPD put
1048 // register IDs in 8-bit immediates nowadays.
1049 ENCODING("FR32", ENCODING_IB)
1050 ENCODING("FR64", ENCODING_IB)
1051 ENCODING("VR128", ENCODING_IB)
1052 ENCODING("VR256", ENCODING_IB)
1053 ENCODING("FR32X", ENCODING_IB)
1054 ENCODING("FR64X", ENCODING_IB)
1055 ENCODING("VR128X", ENCODING_IB)
1056 ENCODING("VR256X", ENCODING_IB)
1057 ENCODING("VR512", ENCODING_IB)
1058 errs() << "Unhandled immediate encoding " << s << "\n";
1059 llvm_unreachable("Unhandled immediate encoding");
1060 }
1062 OperandEncoding
1063 RecognizableInstr::rmRegisterEncodingFromString(const std::string &s,
1064 uint8_t OpSize) {
1065 ENCODING("RST", ENCODING_FP)
1066 ENCODING("GR16", ENCODING_RM)
1067 ENCODING("GR32", ENCODING_RM)
1068 ENCODING("GR32orGR64", ENCODING_RM)
1069 ENCODING("GR64", ENCODING_RM)
1070 ENCODING("GR8", ENCODING_RM)
1071 ENCODING("VR128", ENCODING_RM)
1072 ENCODING("VR128X", ENCODING_RM)
1073 ENCODING("FR64", ENCODING_RM)
1074 ENCODING("FR32", ENCODING_RM)
1075 ENCODING("FR64X", ENCODING_RM)
1076 ENCODING("FR32X", ENCODING_RM)
1077 ENCODING("VR64", ENCODING_RM)
1078 ENCODING("VR256", ENCODING_RM)
1079 ENCODING("VR256X", ENCODING_RM)
1080 ENCODING("VR512", ENCODING_RM)
1081 ENCODING("VK1", ENCODING_RM)
1082 ENCODING("VK8", ENCODING_RM)
1083 ENCODING("VK16", ENCODING_RM)
1084 ENCODING("VK32", ENCODING_RM)
1085 ENCODING("VK64", ENCODING_RM)
1086 errs() << "Unhandled R/M register encoding " << s << "\n";
1087 llvm_unreachable("Unhandled R/M register encoding");
1088 }
1090 OperandEncoding
1091 RecognizableInstr::roRegisterEncodingFromString(const std::string &s,
1092 uint8_t OpSize) {
1093 ENCODING("GR16", ENCODING_REG)
1094 ENCODING("GR32", ENCODING_REG)
1095 ENCODING("GR32orGR64", ENCODING_REG)
1096 ENCODING("GR64", ENCODING_REG)
1097 ENCODING("GR8", ENCODING_REG)
1098 ENCODING("VR128", ENCODING_REG)
1099 ENCODING("FR64", ENCODING_REG)
1100 ENCODING("FR32", ENCODING_REG)
1101 ENCODING("VR64", ENCODING_REG)
1102 ENCODING("SEGMENT_REG", ENCODING_REG)
1103 ENCODING("DEBUG_REG", ENCODING_REG)
1104 ENCODING("CONTROL_REG", ENCODING_REG)
1105 ENCODING("VR256", ENCODING_REG)
1106 ENCODING("VR256X", ENCODING_REG)
1107 ENCODING("VR128X", ENCODING_REG)
1108 ENCODING("FR64X", ENCODING_REG)
1109 ENCODING("FR32X", ENCODING_REG)
1110 ENCODING("VR512", ENCODING_REG)
1111 ENCODING("VK1", ENCODING_REG)
1112 ENCODING("VK2", ENCODING_REG)
1113 ENCODING("VK4", ENCODING_REG)
1114 ENCODING("VK8", ENCODING_REG)
1115 ENCODING("VK16", ENCODING_REG)
1116 ENCODING("VK32", ENCODING_REG)
1117 ENCODING("VK64", ENCODING_REG)
1118 ENCODING("VK1WM", ENCODING_REG)
1119 ENCODING("VK8WM", ENCODING_REG)
1120 ENCODING("VK16WM", ENCODING_REG)
1121 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1122 llvm_unreachable("Unhandled reg/opcode register encoding");
1123 }
1125 OperandEncoding
1126 RecognizableInstr::vvvvRegisterEncodingFromString(const std::string &s,
1127 uint8_t OpSize) {
1128 ENCODING("GR32", ENCODING_VVVV)
1129 ENCODING("GR64", ENCODING_VVVV)
1130 ENCODING("FR32", ENCODING_VVVV)
1131 ENCODING("FR64", ENCODING_VVVV)
1132 ENCODING("VR128", ENCODING_VVVV)
1133 ENCODING("VR256", ENCODING_VVVV)
1134 ENCODING("FR32X", ENCODING_VVVV)
1135 ENCODING("FR64X", ENCODING_VVVV)
1136 ENCODING("VR128X", ENCODING_VVVV)
1137 ENCODING("VR256X", ENCODING_VVVV)
1138 ENCODING("VR512", ENCODING_VVVV)
1139 ENCODING("VK1", ENCODING_VVVV)
1140 ENCODING("VK2", ENCODING_VVVV)
1141 ENCODING("VK4", ENCODING_VVVV)
1142 ENCODING("VK8", ENCODING_VVVV)
1143 ENCODING("VK16", ENCODING_VVVV)
1144 ENCODING("VK32", ENCODING_VVVV)
1145 ENCODING("VK64", ENCODING_VVVV)
1146 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1147 llvm_unreachable("Unhandled VEX.vvvv register encoding");
1148 }
1150 OperandEncoding
1151 RecognizableInstr::writemaskRegisterEncodingFromString(const std::string &s,
1152 uint8_t OpSize) {
1153 ENCODING("VK1WM", ENCODING_WRITEMASK)
1154 ENCODING("VK2WM", ENCODING_WRITEMASK)
1155 ENCODING("VK4WM", ENCODING_WRITEMASK)
1156 ENCODING("VK8WM", ENCODING_WRITEMASK)
1157 ENCODING("VK16WM", ENCODING_WRITEMASK)
1158 ENCODING("VK32WM", ENCODING_WRITEMASK)
1159 ENCODING("VK64WM", ENCODING_WRITEMASK)
1160 errs() << "Unhandled mask register encoding " << s << "\n";
1161 llvm_unreachable("Unhandled mask register encoding");
1162 }
1164 OperandEncoding
1165 RecognizableInstr::memoryEncodingFromString(const std::string &s,
1166 uint8_t OpSize) {
1167 ENCODING("i16mem", ENCODING_RM)
1168 ENCODING("i32mem", ENCODING_RM)
1169 ENCODING("i64mem", ENCODING_RM)
1170 ENCODING("i8mem", ENCODING_RM)
1171 ENCODING("ssmem", ENCODING_RM)
1172 ENCODING("sdmem", ENCODING_RM)
1173 ENCODING("f128mem", ENCODING_RM)
1174 ENCODING("f256mem", ENCODING_RM)
1175 ENCODING("f512mem", ENCODING_RM)
1176 ENCODING("f64mem", ENCODING_RM)
1177 ENCODING("f32mem", ENCODING_RM)
1178 ENCODING("i128mem", ENCODING_RM)
1179 ENCODING("i256mem", ENCODING_RM)
1180 ENCODING("i512mem", ENCODING_RM)
1181 ENCODING("f80mem", ENCODING_RM)
1182 ENCODING("lea64_32mem", ENCODING_RM)
1183 ENCODING("lea64mem", ENCODING_RM)
1184 ENCODING("anymem", ENCODING_RM)
1185 ENCODING("opaque32mem", ENCODING_RM)
1186 ENCODING("opaque48mem", ENCODING_RM)
1187 ENCODING("opaque80mem", ENCODING_RM)
1188 ENCODING("opaque512mem", ENCODING_RM)
1189 ENCODING("vx32mem", ENCODING_RM)
1190 ENCODING("vy32mem", ENCODING_RM)
1191 ENCODING("vz32mem", ENCODING_RM)
1192 ENCODING("vx64mem", ENCODING_RM)
1193 ENCODING("vy64mem", ENCODING_RM)
1194 ENCODING("vy64xmem", ENCODING_RM)
1195 ENCODING("vz64mem", ENCODING_RM)
1196 errs() << "Unhandled memory encoding " << s << "\n";
1197 llvm_unreachable("Unhandled memory encoding");
1198 }
1200 OperandEncoding
1201 RecognizableInstr::relocationEncodingFromString(const std::string &s,
1202 uint8_t OpSize) {
1203 if(OpSize != X86Local::OpSize16) {
1204 // For instructions without an OpSize prefix, a declared 16-bit register or
1205 // immediate encoding is special.
1206 ENCODING("i16imm", ENCODING_IW)
1207 }
1208 ENCODING("i16imm", ENCODING_Iv)
1209 ENCODING("i16i8imm", ENCODING_IB)
1210 ENCODING("i32imm", ENCODING_Iv)
1211 ENCODING("i32i8imm", ENCODING_IB)
1212 ENCODING("i64i32imm", ENCODING_ID)
1213 ENCODING("i64i8imm", ENCODING_IB)
1214 ENCODING("i8imm", ENCODING_IB)
1215 ENCODING("u8imm", ENCODING_IB)
1216 ENCODING("i64i32imm_pcrel", ENCODING_ID)
1217 ENCODING("i16imm_pcrel", ENCODING_IW)
1218 ENCODING("i32imm_pcrel", ENCODING_ID)
1219 ENCODING("brtarget32", ENCODING_Iv)
1220 ENCODING("brtarget16", ENCODING_Iv)
1221 ENCODING("brtarget8", ENCODING_IB)
1222 ENCODING("i64imm", ENCODING_IO)
1223 ENCODING("offset16_8", ENCODING_Ia)
1224 ENCODING("offset16_16", ENCODING_Ia)
1225 ENCODING("offset16_32", ENCODING_Ia)
1226 ENCODING("offset32_8", ENCODING_Ia)
1227 ENCODING("offset32_16", ENCODING_Ia)
1228 ENCODING("offset32_32", ENCODING_Ia)
1229 ENCODING("offset32_64", ENCODING_Ia)
1230 ENCODING("offset64_8", ENCODING_Ia)
1231 ENCODING("offset64_16", ENCODING_Ia)
1232 ENCODING("offset64_32", ENCODING_Ia)
1233 ENCODING("offset64_64", ENCODING_Ia)
1234 ENCODING("srcidx8", ENCODING_SI)
1235 ENCODING("srcidx16", ENCODING_SI)
1236 ENCODING("srcidx32", ENCODING_SI)
1237 ENCODING("srcidx64", ENCODING_SI)
1238 ENCODING("dstidx8", ENCODING_DI)
1239 ENCODING("dstidx16", ENCODING_DI)
1240 ENCODING("dstidx32", ENCODING_DI)
1241 ENCODING("dstidx64", ENCODING_DI)
1242 errs() << "Unhandled relocation encoding " << s << "\n";
1243 llvm_unreachable("Unhandled relocation encoding");
1244 }
1246 OperandEncoding
1247 RecognizableInstr::opcodeModifierEncodingFromString(const std::string &s,
1248 uint8_t OpSize) {
1249 ENCODING("GR32", ENCODING_Rv)
1250 ENCODING("GR64", ENCODING_RO)
1251 ENCODING("GR16", ENCODING_Rv)
1252 ENCODING("GR8", ENCODING_RB)
1253 ENCODING("GR16_NOAX", ENCODING_Rv)
1254 ENCODING("GR32_NOAX", ENCODING_Rv)
1255 ENCODING("GR64_NOAX", ENCODING_RO)
1256 errs() << "Unhandled opcode modifier encoding " << s << "\n";
1257 llvm_unreachable("Unhandled opcode modifier encoding");
1258 }
1259 #undef ENCODING