1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
14 //
15 //===----------------------------------------------------------------------===//
17 #include "X86RecognizableInstr.h"
18 #include "X86DisassemblerShared.h"
19 #include "X86ModRMFilters.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include <string>
23 using namespace llvm;
25 #define MRM_MAPPING \
26 MAP(C1, 33) \
27 MAP(C2, 34) \
28 MAP(C3, 35) \
29 MAP(C4, 36) \
30 MAP(C8, 37) \
31 MAP(C9, 38) \
32 MAP(CA, 39) \
33 MAP(CB, 40) \
34 MAP(E8, 41) \
35 MAP(F0, 42) \
36 MAP(F8, 45) \
37 MAP(F9, 46) \
38 MAP(D0, 47) \
39 MAP(D1, 48) \
40 MAP(D4, 49) \
41 MAP(D5, 50) \
42 MAP(D6, 51) \
43 MAP(D8, 52) \
44 MAP(D9, 53) \
45 MAP(DA, 54) \
46 MAP(DB, 55) \
47 MAP(DC, 56) \
48 MAP(DD, 57) \
49 MAP(DE, 58) \
50 MAP(DF, 59)
52 // A clone of X86 since we can't depend on something that is generated.
53 namespace X86Local {
54 enum {
55 Pseudo = 0,
56 RawFrm = 1,
57 AddRegFrm = 2,
58 MRMDestReg = 3,
59 MRMDestMem = 4,
60 MRMSrcReg = 5,
61 MRMSrcMem = 6,
62 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
63 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
64 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
65 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
66 MRMInitReg = 32,
67 RawFrmImm8 = 43,
68 RawFrmImm16 = 44,
69 #define MAP(from, to) MRM_##from = to,
70 MRM_MAPPING
71 #undef MAP
72 lastMRM
73 };
75 enum {
76 TB = 1,
77 REP = 2,
78 D8 = 3, D9 = 4, DA = 5, DB = 6,
79 DC = 7, DD = 8, DE = 9, DF = 10,
80 XD = 11, XS = 12,
81 T8 = 13, P_TA = 14,
82 A6 = 15, A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19,
83 XOP8 = 20, XOP9 = 21, XOPA = 22
84 };
85 }
87 // If rows are added to the opcode extension tables, then corresponding entries
88 // must be added here.
89 //
90 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
91 // that byte to ONE_BYTE_EXTENSION_TABLES.
92 //
93 // If the row corresponds to two bytes where the first is 0f, add an entry for
94 // the second byte to TWO_BYTE_EXTENSION_TABLES.
95 //
96 // If the row corresponds to some other set of bytes, you will need to modify
97 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
98 // to the X86 TD files, except in two cases: if the first two bytes of such a
99 // new combination are 0f 38 or 0f 3a, you just have to add maps called
100 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
101 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
102 // in RecognizableInstr::emitDecodePath().
104 #define ONE_BYTE_EXTENSION_TABLES \
105 EXTENSION_TABLE(80) \
106 EXTENSION_TABLE(81) \
107 EXTENSION_TABLE(82) \
108 EXTENSION_TABLE(83) \
109 EXTENSION_TABLE(8f) \
110 EXTENSION_TABLE(c0) \
111 EXTENSION_TABLE(c1) \
112 EXTENSION_TABLE(c6) \
113 EXTENSION_TABLE(c7) \
114 EXTENSION_TABLE(d0) \
115 EXTENSION_TABLE(d1) \
116 EXTENSION_TABLE(d2) \
117 EXTENSION_TABLE(d3) \
118 EXTENSION_TABLE(f6) \
119 EXTENSION_TABLE(f7) \
120 EXTENSION_TABLE(fe) \
121 EXTENSION_TABLE(ff)
123 #define TWO_BYTE_EXTENSION_TABLES \
124 EXTENSION_TABLE(00) \
125 EXTENSION_TABLE(01) \
126 EXTENSION_TABLE(0d) \
127 EXTENSION_TABLE(18) \
128 EXTENSION_TABLE(71) \
129 EXTENSION_TABLE(72) \
130 EXTENSION_TABLE(73) \
131 EXTENSION_TABLE(ae) \
132 EXTENSION_TABLE(ba) \
133 EXTENSION_TABLE(c7)
135 #define THREE_BYTE_38_EXTENSION_TABLES \
136 EXTENSION_TABLE(F3)
138 #define XOP9_MAP_EXTENSION_TABLES \
139 EXTENSION_TABLE(01) \
140 EXTENSION_TABLE(02)
142 using namespace X86Disassembler;
144 /// needsModRMForDecode - Indicates whether a particular instruction requires a
145 /// ModR/M byte for the instruction to be properly decoded. For example, a
146 /// MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
147 /// 0b11.
148 ///
149 /// @param form - The form of the instruction.
150 /// @return - true if the form implies that a ModR/M byte is required, false
151 /// otherwise.
152 static bool needsModRMForDecode(uint8_t form) {
153 if (form == X86Local::MRMDestReg ||
154 form == X86Local::MRMDestMem ||
155 form == X86Local::MRMSrcReg ||
156 form == X86Local::MRMSrcMem ||
157 (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
158 (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
159 return true;
160 else
161 return false;
162 }
164 /// isRegFormat - Indicates whether a particular form requires the Mod field of
165 /// the ModR/M byte to be 0b11.
166 ///
167 /// @param form - The form of the instruction.
168 /// @return - true if the form implies that Mod must be 0b11, false
169 /// otherwise.
170 static bool isRegFormat(uint8_t form) {
171 if (form == X86Local::MRMDestReg ||
172 form == X86Local::MRMSrcReg ||
173 (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
174 return true;
175 else
176 return false;
177 }
179 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
180 /// Useful for switch statements and the like.
181 ///
182 /// @param init - A reference to the BitsInit to be decoded.
183 /// @return - The field, with the first bit in the BitsInit as the lowest
184 /// order bit.
185 static uint8_t byteFromBitsInit(BitsInit &init) {
186 int width = init.getNumBits();
188 assert(width <= 8 && "Field is too large for uint8_t!");
190 int index;
191 uint8_t mask = 0x01;
193 uint8_t ret = 0;
195 for (index = 0; index < width; index++) {
196 if (static_cast<BitInit*>(init.getBit(index))->getValue())
197 ret |= mask;
199 mask <<= 1;
200 }
202 return ret;
203 }
205 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
206 /// name of the field.
207 ///
208 /// @param rec - The record from which to extract the value.
209 /// @param name - The name of the field in the record.
210 /// @return - The field, as translated by byteFromBitsInit().
211 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
212 BitsInit* bits = rec->getValueAsBitsInit(name);
213 return byteFromBitsInit(*bits);
214 }
216 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
217 const CodeGenInstruction &insn,
218 InstrUID uid) {
219 UID = uid;
221 Rec = insn.TheDef;
222 Name = Rec->getName();
223 Spec = &tables.specForUID(UID);
225 if (!Rec->isSubClassOf("X86Inst")) {
226 ShouldBeEmitted = false;
227 return;
228 }
230 Prefix = byteFromRec(Rec, "Prefix");
231 Opcode = byteFromRec(Rec, "Opcode");
232 Form = byteFromRec(Rec, "FormBits");
233 SegOvr = byteFromRec(Rec, "SegOvrBits");
235 HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix");
236 HasAdSizePrefix = Rec->getValueAsBit("hasAdSizePrefix");
237 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
238 HasVEXPrefix = Rec->getValueAsBit("hasVEXPrefix");
239 HasVEX_4VPrefix = Rec->getValueAsBit("hasVEX_4VPrefix");
240 HasVEX_4VOp3Prefix = Rec->getValueAsBit("hasVEX_4VOp3Prefix");
241 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix");
242 HasMemOp4Prefix = Rec->getValueAsBit("hasMemOp4Prefix");
243 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
244 HasEVEXPrefix = Rec->getValueAsBit("hasEVEXPrefix");
245 HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2");
246 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K");
247 HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z");
248 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B");
249 HasLockPrefix = Rec->getValueAsBit("hasLockPrefix");
250 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
251 ForceDisassemble = Rec->getValueAsBit("ForceDisassemble");
253 Name = Rec->getName();
254 AsmString = Rec->getValueAsString("AsmString");
256 Operands = &insn.Operands.OperandList;
258 IsSSE = (HasOpSizePrefix && (Name.find("16") == Name.npos)) ||
259 (Name.find("CRC32") != Name.npos);
260 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L");
262 // Check for 64-bit inst which does not require REX
263 Is32Bit = false;
264 Is64Bit = false;
265 // FIXME: Is there some better way to check for In64BitMode?
266 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
267 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
268 if (Predicates[i]->getName().find("Not64Bit") != Name.npos ||
269 Predicates[i]->getName().find("In32Bit") != Name.npos) {
270 Is32Bit = true;
271 break;
272 }
273 if (Predicates[i]->getName().find("In64Bit") != Name.npos) {
274 Is64Bit = true;
275 break;
276 }
277 }
279 ShouldBeEmitted = true;
280 }
282 void RecognizableInstr::processInstr(DisassemblerTables &tables,
283 const CodeGenInstruction &insn,
284 InstrUID uid)
285 {
286 // Ignore "asm parser only" instructions.
287 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
288 return;
290 RecognizableInstr recogInstr(tables, insn, uid);
292 recogInstr.emitInstructionSpecifier();
294 if (recogInstr.shouldBeEmitted())
295 recogInstr.emitDecodePath(tables);
296 }
298 #define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \
299 (HasEVEX_K && HasEVEX_B ? n##_K_B : \
300 (HasEVEX_KZ ? n##_KZ : \
301 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n)))))
303 InstructionContext RecognizableInstr::insnContext() const {
304 InstructionContext insnContext;
306 if (HasEVEXPrefix) {
307 if (HasVEX_LPrefix && HasEVEX_L2Prefix) {
308 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n";
309 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled");
310 }
311 // VEX_L & VEX_W
312 if (HasVEX_LPrefix && HasVEX_WPrefix) {
313 if (HasOpSizePrefix)
314 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE);
315 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
316 insnContext = EVEX_KB(IC_EVEX_L_W_XS);
317 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
318 Prefix == X86Local::TAXD)
319 insnContext = EVEX_KB(IC_EVEX_L_W_XD);
320 else
321 insnContext = EVEX_KB(IC_EVEX_L_W);
322 } else if (HasVEX_LPrefix) {
323 // VEX_L
324 if (HasOpSizePrefix)
325 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE);
326 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
327 insnContext = EVEX_KB(IC_EVEX_L_XS);
328 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
329 Prefix == X86Local::TAXD)
330 insnContext = EVEX_KB(IC_EVEX_L_XD);
331 else
332 insnContext = EVEX_KB(IC_EVEX_L);
333 }
334 else if (HasEVEX_L2Prefix && HasVEX_WPrefix) {
335 // EVEX_L2 & VEX_W
336 if (HasOpSizePrefix)
337 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE);
338 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
339 insnContext = EVEX_KB(IC_EVEX_L2_W_XS);
340 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
341 Prefix == X86Local::TAXD)
342 insnContext = EVEX_KB(IC_EVEX_L2_W_XD);
343 else
344 insnContext = EVEX_KB(IC_EVEX_L2_W);
345 } else if (HasEVEX_L2Prefix) {
346 // EVEX_L2
347 if (HasOpSizePrefix)
348 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE);
349 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
350 Prefix == X86Local::TAXD)
351 insnContext = EVEX_KB(IC_EVEX_L2_XD);
352 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
353 insnContext = EVEX_KB(IC_EVEX_L2_XS);
354 else
355 insnContext = EVEX_KB(IC_EVEX_L2);
356 }
357 else if (HasVEX_WPrefix) {
358 // VEX_W
359 if (HasOpSizePrefix)
360 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE);
361 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
362 insnContext = EVEX_KB(IC_EVEX_W_XS);
363 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
364 Prefix == X86Local::TAXD)
365 insnContext = EVEX_KB(IC_EVEX_W_XD);
366 else
367 insnContext = EVEX_KB(IC_EVEX_W);
368 }
369 // No L, no W
370 else if (HasOpSizePrefix)
371 insnContext = EVEX_KB(IC_EVEX_OPSIZE);
372 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
373 Prefix == X86Local::TAXD)
374 insnContext = EVEX_KB(IC_EVEX_XD);
375 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
376 insnContext = EVEX_KB(IC_EVEX_XS);
377 else
378 insnContext = EVEX_KB(IC_EVEX);
379 /// eof EVEX
380 } else if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) {
381 if (HasVEX_LPrefix && HasVEX_WPrefix) {
382 if (HasOpSizePrefix)
383 insnContext = IC_VEX_L_W_OPSIZE;
384 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
385 insnContext = IC_VEX_L_W_XS;
386 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
387 Prefix == X86Local::TAXD)
388 insnContext = IC_VEX_L_W_XD;
389 else
390 insnContext = IC_VEX_L_W;
391 } else if (HasOpSizePrefix && HasVEX_LPrefix)
392 insnContext = IC_VEX_L_OPSIZE;
393 else if (HasOpSizePrefix && HasVEX_WPrefix)
394 insnContext = IC_VEX_W_OPSIZE;
395 else if (HasOpSizePrefix)
396 insnContext = IC_VEX_OPSIZE;
397 else if (HasVEX_LPrefix &&
398 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
399 insnContext = IC_VEX_L_XS;
400 else if (HasVEX_LPrefix && (Prefix == X86Local::XD ||
401 Prefix == X86Local::T8XD ||
402 Prefix == X86Local::TAXD))
403 insnContext = IC_VEX_L_XD;
404 else if (HasVEX_WPrefix &&
405 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
406 insnContext = IC_VEX_W_XS;
407 else if (HasVEX_WPrefix && (Prefix == X86Local::XD ||
408 Prefix == X86Local::T8XD ||
409 Prefix == X86Local::TAXD))
410 insnContext = IC_VEX_W_XD;
411 else if (HasVEX_WPrefix)
412 insnContext = IC_VEX_W;
413 else if (HasVEX_LPrefix)
414 insnContext = IC_VEX_L;
415 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
416 Prefix == X86Local::TAXD)
417 insnContext = IC_VEX_XD;
418 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
419 insnContext = IC_VEX_XS;
420 else
421 insnContext = IC_VEX;
422 } else if (Is64Bit || HasREX_WPrefix) {
423 if (HasREX_WPrefix && HasOpSizePrefix)
424 insnContext = IC_64BIT_REXW_OPSIZE;
425 else if (HasOpSizePrefix && (Prefix == X86Local::XD ||
426 Prefix == X86Local::T8XD ||
427 Prefix == X86Local::TAXD))
428 insnContext = IC_64BIT_XD_OPSIZE;
429 else if (HasOpSizePrefix &&
430 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
431 insnContext = IC_64BIT_XS_OPSIZE;
432 else if (HasOpSizePrefix)
433 insnContext = IC_64BIT_OPSIZE;
434 else if (HasAdSizePrefix)
435 insnContext = IC_64BIT_ADSIZE;
436 else if (HasREX_WPrefix &&
437 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
438 insnContext = IC_64BIT_REXW_XS;
439 else if (HasREX_WPrefix && (Prefix == X86Local::XD ||
440 Prefix == X86Local::T8XD ||
441 Prefix == X86Local::TAXD))
442 insnContext = IC_64BIT_REXW_XD;
443 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
444 Prefix == X86Local::TAXD)
445 insnContext = IC_64BIT_XD;
446 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
447 insnContext = IC_64BIT_XS;
448 else if (HasREX_WPrefix)
449 insnContext = IC_64BIT_REXW;
450 else
451 insnContext = IC_64BIT;
452 } else {
453 if (HasOpSizePrefix && (Prefix == X86Local::XD ||
454 Prefix == X86Local::T8XD ||
455 Prefix == X86Local::TAXD))
456 insnContext = IC_XD_OPSIZE;
457 else if (HasOpSizePrefix &&
458 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
459 insnContext = IC_XS_OPSIZE;
460 else if (HasOpSizePrefix)
461 insnContext = IC_OPSIZE;
462 else if (HasAdSizePrefix)
463 insnContext = IC_ADSIZE;
464 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
465 Prefix == X86Local::TAXD)
466 insnContext = IC_XD;
467 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS ||
468 Prefix == X86Local::REP)
469 insnContext = IC_XS;
470 else
471 insnContext = IC;
472 }
474 return insnContext;
475 }
477 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
478 ///////////////////
479 // FILTER_STRONG
480 //
482 // Filter out intrinsics
484 assert(Rec->isSubClassOf("X86Inst") && "Can only filter X86 instructions");
486 if (Form == X86Local::Pseudo ||
487 (IsCodeGenOnly && !ForceDisassemble &&
488 Name.find("INC32") == Name.npos && Name.find("DEC32") == Name.npos))
489 return FILTER_STRONG;
492 // Filter out artificial instructions but leave in the LOCK_PREFIX so it is
493 // printed as a separate "instruction".
495 // Filter out instructions with segment override prefixes.
496 // They're too messy to handle now and we'll special case them if needed.
498 if (SegOvr)
499 return FILTER_STRONG;
502 /////////////////
503 // FILTER_WEAK
504 //
507 // Filter out instructions with a LOCK prefix;
508 // prefer forms that do not have the prefix
509 if (HasLockPrefix)
510 return FILTER_WEAK;
512 // Filter out alternate forms of AVX instructions
513 if (Name.find("_alt") != Name.npos ||
514 (Name.find("r64r") != Name.npos && Name.find("r64r64") == Name.npos && Name.find("r64r8") == Name.npos) ||
515 Name.find("_64mr") != Name.npos ||
516 Name.find("rr64") != Name.npos)
517 return FILTER_WEAK;
519 // Special cases.
521 if (Name == "PUSH64i16" ||
522 Name == "MOVPQI2QImr" ||
523 Name == "VMOVPQI2QImr" ||
524 Name == "VMASKMOVDQU64")
525 return FILTER_WEAK;
527 // XACQUIRE and XRELEASE reuse REPNE and REP respectively.
528 // For now, just prefer the REP versions.
529 if (Name == "XACQUIRE_PREFIX" ||
530 Name == "XRELEASE_PREFIX")
531 return FILTER_WEAK;
533 return FILTER_NORMAL;
534 }
536 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
537 unsigned &physicalOperandIndex,
538 unsigned &numPhysicalOperands,
539 const unsigned *operandMapping,
540 OperandEncoding (*encodingFromString)
541 (const std::string&,
542 bool hasOpSizePrefix)) {
543 if (optional) {
544 if (physicalOperandIndex >= numPhysicalOperands)
545 return;
546 } else {
547 assert(physicalOperandIndex < numPhysicalOperands);
548 }
550 while (operandMapping[operandIndex] != operandIndex) {
551 Spec->operands[operandIndex].encoding = ENCODING_DUP;
552 Spec->operands[operandIndex].type =
553 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
554 ++operandIndex;
555 }
557 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
559 Spec->operands[operandIndex].encoding = encodingFromString(typeName,
560 HasOpSizePrefix);
561 Spec->operands[operandIndex].type = typeFromString(typeName,
562 IsSSE,
563 HasREX_WPrefix,
564 HasOpSizePrefix);
566 ++operandIndex;
567 ++physicalOperandIndex;
568 }
570 void RecognizableInstr::emitInstructionSpecifier() {
571 Spec->name = Name;
573 if (!ShouldBeEmitted)
574 return;
576 switch (filter()) {
577 case FILTER_WEAK:
578 Spec->filtered = true;
579 break;
580 case FILTER_STRONG:
581 ShouldBeEmitted = false;
582 return;
583 case FILTER_NORMAL:
584 break;
585 }
587 Spec->insnContext = insnContext();
589 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
591 unsigned numOperands = OperandList.size();
592 unsigned numPhysicalOperands = 0;
594 // operandMapping maps from operands in OperandList to their originals.
595 // If operandMapping[i] != i, then the entry is a duplicate.
596 unsigned operandMapping[X86_MAX_OPERANDS];
597 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
599 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
600 if (OperandList[operandIndex].Constraints.size()) {
601 const CGIOperandList::ConstraintInfo &Constraint =
602 OperandList[operandIndex].Constraints[0];
603 if (Constraint.isTied()) {
604 operandMapping[operandIndex] = operandIndex;
605 operandMapping[Constraint.getTiedOperand()] = operandIndex;
606 } else {
607 ++numPhysicalOperands;
608 operandMapping[operandIndex] = operandIndex;
609 }
610 } else {
611 ++numPhysicalOperands;
612 operandMapping[operandIndex] = operandIndex;
613 }
614 }
616 #define HANDLE_OPERAND(class) \
617 handleOperand(false, \
618 operandIndex, \
619 physicalOperandIndex, \
620 numPhysicalOperands, \
621 operandMapping, \
622 class##EncodingFromString);
624 #define HANDLE_OPTIONAL(class) \
625 handleOperand(true, \
626 operandIndex, \
627 physicalOperandIndex, \
628 numPhysicalOperands, \
629 operandMapping, \
630 class##EncodingFromString);
632 // operandIndex should always be < numOperands
633 unsigned operandIndex = 0;
634 // physicalOperandIndex should always be < numPhysicalOperands
635 unsigned physicalOperandIndex = 0;
637 switch (Form) {
638 case X86Local::RawFrm:
639 // Operand 1 (optional) is an address or immediate.
640 // Operand 2 (optional) is an immediate.
641 assert(numPhysicalOperands <= 2 &&
642 "Unexpected number of operands for RawFrm");
643 HANDLE_OPTIONAL(relocation)
644 HANDLE_OPTIONAL(immediate)
645 break;
646 case X86Local::AddRegFrm:
647 // Operand 1 is added to the opcode.
648 // Operand 2 (optional) is an address.
649 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
650 "Unexpected number of operands for AddRegFrm");
651 HANDLE_OPERAND(opcodeModifier)
652 HANDLE_OPTIONAL(relocation)
653 break;
654 case X86Local::MRMDestReg:
655 // Operand 1 is a register operand in the R/M field.
656 // Operand 2 is a register operand in the Reg/Opcode field.
657 // - In AVX, there is a register operand in the VEX.vvvv field here -
658 // Operand 3 (optional) is an immediate.
659 if (HasVEX_4VPrefix)
660 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
661 "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
662 else
663 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
664 "Unexpected number of operands for MRMDestRegFrm");
666 HANDLE_OPERAND(rmRegister)
668 if (HasVEX_4VPrefix)
669 // FIXME: In AVX, the register below becomes the one encoded
670 // in ModRMVEX and the one above the one in the VEX.VVVV field
671 HANDLE_OPERAND(vvvvRegister)
673 HANDLE_OPERAND(roRegister)
674 HANDLE_OPTIONAL(immediate)
675 break;
676 case X86Local::MRMDestMem:
677 // Operand 1 is a memory operand (possibly SIB-extended)
678 // Operand 2 is a register operand in the Reg/Opcode field.
679 // - In AVX, there is a register operand in the VEX.vvvv field here -
680 // Operand 3 (optional) is an immediate.
681 if (HasVEX_4VPrefix)
682 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
683 "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
684 else
685 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
686 "Unexpected number of operands for MRMDestMemFrm");
687 HANDLE_OPERAND(memory)
689 if (HasEVEX_K)
690 HANDLE_OPERAND(writemaskRegister)
692 if (HasVEX_4VPrefix)
693 // FIXME: In AVX, the register below becomes the one encoded
694 // in ModRMVEX and the one above the one in the VEX.VVVV field
695 HANDLE_OPERAND(vvvvRegister)
697 HANDLE_OPERAND(roRegister)
698 HANDLE_OPTIONAL(immediate)
699 break;
700 case X86Local::MRMSrcReg:
701 // Operand 1 is a register operand in the Reg/Opcode field.
702 // Operand 2 is a register operand in the R/M field.
703 // - In AVX, there is a register operand in the VEX.vvvv field here -
704 // Operand 3 (optional) is an immediate.
705 // Operand 4 (optional) is an immediate.
707 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
708 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
709 "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
710 else
711 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 4 &&
712 "Unexpected number of operands for MRMSrcRegFrm");
714 HANDLE_OPERAND(roRegister)
716 if (HasEVEX_K)
717 HANDLE_OPERAND(writemaskRegister)
719 if (HasVEX_4VPrefix)
720 // FIXME: In AVX, the register below becomes the one encoded
721 // in ModRMVEX and the one above the one in the VEX.VVVV field
722 HANDLE_OPERAND(vvvvRegister)
724 if (HasMemOp4Prefix)
725 HANDLE_OPERAND(immediate)
727 HANDLE_OPERAND(rmRegister)
729 if (HasVEX_4VOp3Prefix)
730 HANDLE_OPERAND(vvvvRegister)
732 if (!HasMemOp4Prefix)
733 HANDLE_OPTIONAL(immediate)
734 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
735 HANDLE_OPTIONAL(immediate)
736 break;
737 case X86Local::MRMSrcMem:
738 // Operand 1 is a register operand in the Reg/Opcode field.
739 // Operand 2 is a memory operand (possibly SIB-extended)
740 // - In AVX, there is a register operand in the VEX.vvvv field here -
741 // Operand 3 (optional) is an immediate.
743 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
744 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
745 "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
746 else
747 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
748 "Unexpected number of operands for MRMSrcMemFrm");
750 HANDLE_OPERAND(roRegister)
752 if (HasEVEX_K)
753 HANDLE_OPERAND(writemaskRegister)
755 if (HasVEX_4VPrefix)
756 // FIXME: In AVX, the register below becomes the one encoded
757 // in ModRMVEX and the one above the one in the VEX.VVVV field
758 HANDLE_OPERAND(vvvvRegister)
760 if (HasMemOp4Prefix)
761 HANDLE_OPERAND(immediate)
763 HANDLE_OPERAND(memory)
765 if (HasVEX_4VOp3Prefix)
766 HANDLE_OPERAND(vvvvRegister)
768 if (!HasMemOp4Prefix)
769 HANDLE_OPTIONAL(immediate)
770 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
771 break;
772 case X86Local::MRM0r:
773 case X86Local::MRM1r:
774 case X86Local::MRM2r:
775 case X86Local::MRM3r:
776 case X86Local::MRM4r:
777 case X86Local::MRM5r:
778 case X86Local::MRM6r:
779 case X86Local::MRM7r:
780 {
781 // Operand 1 is a register operand in the R/M field.
782 // Operand 2 (optional) is an immediate or relocation.
783 // Operand 3 (optional) is an immediate.
784 unsigned kOp = (HasEVEX_K) ? 1:0;
785 unsigned Op4v = (HasVEX_4VPrefix) ? 1:0;
786 if (numPhysicalOperands > 3 + kOp + Op4v)
787 llvm_unreachable("Unexpected number of operands for MRMnr");
788 }
789 if (HasVEX_4VPrefix)
790 HANDLE_OPERAND(vvvvRegister)
792 if (HasEVEX_K)
793 HANDLE_OPERAND(writemaskRegister)
794 HANDLE_OPTIONAL(rmRegister)
795 HANDLE_OPTIONAL(relocation)
796 HANDLE_OPTIONAL(immediate)
797 break;
798 case X86Local::MRM0m:
799 case X86Local::MRM1m:
800 case X86Local::MRM2m:
801 case X86Local::MRM3m:
802 case X86Local::MRM4m:
803 case X86Local::MRM5m:
804 case X86Local::MRM6m:
805 case X86Local::MRM7m:
806 {
807 // Operand 1 is a memory operand (possibly SIB-extended)
808 // Operand 2 (optional) is an immediate or relocation.
809 unsigned kOp = (HasEVEX_K) ? 1:0;
810 unsigned Op4v = (HasVEX_4VPrefix) ? 1:0;
811 if (numPhysicalOperands < 1 + kOp + Op4v ||
812 numPhysicalOperands > 2 + kOp + Op4v)
813 llvm_unreachable("Unexpected number of operands for MRMnm");
814 }
815 if (HasVEX_4VPrefix)
816 HANDLE_OPERAND(vvvvRegister)
817 if (HasEVEX_K)
818 HANDLE_OPERAND(writemaskRegister)
819 HANDLE_OPERAND(memory)
820 HANDLE_OPTIONAL(relocation)
821 break;
822 case X86Local::RawFrmImm8:
823 // operand 1 is a 16-bit immediate
824 // operand 2 is an 8-bit immediate
825 assert(numPhysicalOperands == 2 &&
826 "Unexpected number of operands for X86Local::RawFrmImm8");
827 HANDLE_OPERAND(immediate)
828 HANDLE_OPERAND(immediate)
829 break;
830 case X86Local::RawFrmImm16:
831 // operand 1 is a 16-bit immediate
832 // operand 2 is a 16-bit immediate
833 HANDLE_OPERAND(immediate)
834 HANDLE_OPERAND(immediate)
835 break;
836 case X86Local::MRM_F8:
837 if (Opcode == 0xc6) {
838 assert(numPhysicalOperands == 1 &&
839 "Unexpected number of operands for X86Local::MRM_F8");
840 HANDLE_OPERAND(immediate)
841 } else if (Opcode == 0xc7) {
842 assert(numPhysicalOperands == 1 &&
843 "Unexpected number of operands for X86Local::MRM_F8");
844 HANDLE_OPERAND(relocation)
845 }
846 break;
847 case X86Local::MRMInitReg:
848 // Ignored.
849 break;
850 }
852 #undef HANDLE_OPERAND
853 #undef HANDLE_OPTIONAL
854 }
856 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
857 // Special cases where the LLVM tables are not complete
859 #define MAP(from, to) \
860 case X86Local::MRM_##from: \
861 filter = new ExactFilter(0x##from); \
862 break;
864 OpcodeType opcodeType = (OpcodeType)-1;
866 ModRMFilter* filter = NULL;
867 uint8_t opcodeToSet = 0;
869 switch (Prefix) {
870 default: llvm_unreachable("Invalid prefix!");
871 // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
872 case X86Local::XD:
873 case X86Local::XS:
874 case X86Local::TB:
875 opcodeType = TWOBYTE;
877 switch (Opcode) {
878 default:
879 if (needsModRMForDecode(Form))
880 filter = new ModFilter(isRegFormat(Form));
881 else
882 filter = new DumbFilter();
883 break;
884 #define EXTENSION_TABLE(n) case 0x##n:
885 TWO_BYTE_EXTENSION_TABLES
886 #undef EXTENSION_TABLE
887 switch (Form) {
888 default:
889 llvm_unreachable("Unhandled two-byte extended opcode");
890 case X86Local::MRM0r:
891 case X86Local::MRM1r:
892 case X86Local::MRM2r:
893 case X86Local::MRM3r:
894 case X86Local::MRM4r:
895 case X86Local::MRM5r:
896 case X86Local::MRM6r:
897 case X86Local::MRM7r:
898 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
899 break;
900 case X86Local::MRM0m:
901 case X86Local::MRM1m:
902 case X86Local::MRM2m:
903 case X86Local::MRM3m:
904 case X86Local::MRM4m:
905 case X86Local::MRM5m:
906 case X86Local::MRM6m:
907 case X86Local::MRM7m:
908 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
909 break;
910 MRM_MAPPING
911 } // switch (Form)
912 break;
913 } // switch (Opcode)
914 opcodeToSet = Opcode;
915 break;
916 case X86Local::T8:
917 case X86Local::T8XD:
918 case X86Local::T8XS:
919 opcodeType = THREEBYTE_38;
920 switch (Opcode) {
921 default:
922 if (needsModRMForDecode(Form))
923 filter = new ModFilter(isRegFormat(Form));
924 else
925 filter = new DumbFilter();
926 break;
927 #define EXTENSION_TABLE(n) case 0x##n:
928 THREE_BYTE_38_EXTENSION_TABLES
929 #undef EXTENSION_TABLE
930 switch (Form) {
931 default:
932 llvm_unreachable("Unhandled two-byte extended opcode");
933 case X86Local::MRM0r:
934 case X86Local::MRM1r:
935 case X86Local::MRM2r:
936 case X86Local::MRM3r:
937 case X86Local::MRM4r:
938 case X86Local::MRM5r:
939 case X86Local::MRM6r:
940 case X86Local::MRM7r:
941 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
942 break;
943 case X86Local::MRM0m:
944 case X86Local::MRM1m:
945 case X86Local::MRM2m:
946 case X86Local::MRM3m:
947 case X86Local::MRM4m:
948 case X86Local::MRM5m:
949 case X86Local::MRM6m:
950 case X86Local::MRM7m:
951 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
952 break;
953 MRM_MAPPING
954 } // switch (Form)
955 break;
956 } // switch (Opcode)
957 opcodeToSet = Opcode;
958 break;
959 case X86Local::P_TA:
960 case X86Local::TAXD:
961 opcodeType = THREEBYTE_3A;
962 if (needsModRMForDecode(Form))
963 filter = new ModFilter(isRegFormat(Form));
964 else
965 filter = new DumbFilter();
966 opcodeToSet = Opcode;
967 break;
968 case X86Local::A6:
969 opcodeType = THREEBYTE_A6;
970 if (needsModRMForDecode(Form))
971 filter = new ModFilter(isRegFormat(Form));
972 else
973 filter = new DumbFilter();
974 opcodeToSet = Opcode;
975 break;
976 case X86Local::A7:
977 opcodeType = THREEBYTE_A7;
978 if (needsModRMForDecode(Form))
979 filter = new ModFilter(isRegFormat(Form));
980 else
981 filter = new DumbFilter();
982 opcodeToSet = Opcode;
983 break;
984 case X86Local::XOP8:
985 opcodeType = XOP8_MAP;
986 if (needsModRMForDecode(Form))
987 filter = new ModFilter(isRegFormat(Form));
988 else
989 filter = new DumbFilter();
990 opcodeToSet = Opcode;
991 break;
992 case X86Local::XOP9:
993 opcodeType = XOP9_MAP;
994 switch (Opcode) {
995 default:
996 if (needsModRMForDecode(Form))
997 filter = new ModFilter(isRegFormat(Form));
998 else
999 filter = new DumbFilter();
1000 break;
1001 #define EXTENSION_TABLE(n) case 0x##n:
1002 XOP9_MAP_EXTENSION_TABLES
1003 #undef EXTENSION_TABLE
1004 switch (Form) {
1005 default:
1006 llvm_unreachable("Unhandled XOP9 extended opcode");
1007 case X86Local::MRM0r:
1008 case X86Local::MRM1r:
1009 case X86Local::MRM2r:
1010 case X86Local::MRM3r:
1011 case X86Local::MRM4r:
1012 case X86Local::MRM5r:
1013 case X86Local::MRM6r:
1014 case X86Local::MRM7r:
1015 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1016 break;
1017 case X86Local::MRM0m:
1018 case X86Local::MRM1m:
1019 case X86Local::MRM2m:
1020 case X86Local::MRM3m:
1021 case X86Local::MRM4m:
1022 case X86Local::MRM5m:
1023 case X86Local::MRM6m:
1024 case X86Local::MRM7m:
1025 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1026 break;
1027 MRM_MAPPING
1028 } // switch (Form)
1029 break;
1030 } // switch (Opcode)
1031 opcodeToSet = Opcode;
1032 break;
1033 case X86Local::XOPA:
1034 opcodeType = XOPA_MAP;
1035 if (needsModRMForDecode(Form))
1036 filter = new ModFilter(isRegFormat(Form));
1037 else
1038 filter = new DumbFilter();
1039 opcodeToSet = Opcode;
1040 break;
1041 case X86Local::D8:
1042 case X86Local::D9:
1043 case X86Local::DA:
1044 case X86Local::DB:
1045 case X86Local::DC:
1046 case X86Local::DD:
1047 case X86Local::DE:
1048 case X86Local::DF:
1049 assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
1050 assert(Form == X86Local::RawFrm);
1051 opcodeType = ONEBYTE;
1052 filter = new ExactFilter(Opcode);
1053 opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
1054 break;
1055 case X86Local::REP:
1056 case 0:
1057 opcodeType = ONEBYTE;
1058 switch (Opcode) {
1059 #define EXTENSION_TABLE(n) case 0x##n:
1060 ONE_BYTE_EXTENSION_TABLES
1061 #undef EXTENSION_TABLE
1062 switch (Form) {
1063 default:
1064 llvm_unreachable("Fell through the cracks of a single-byte "
1065 "extended opcode");
1066 case X86Local::MRM0r:
1067 case X86Local::MRM1r:
1068 case X86Local::MRM2r:
1069 case X86Local::MRM3r:
1070 case X86Local::MRM4r:
1071 case X86Local::MRM5r:
1072 case X86Local::MRM6r:
1073 case X86Local::MRM7r:
1074 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1075 break;
1076 case X86Local::MRM0m:
1077 case X86Local::MRM1m:
1078 case X86Local::MRM2m:
1079 case X86Local::MRM3m:
1080 case X86Local::MRM4m:
1081 case X86Local::MRM5m:
1082 case X86Local::MRM6m:
1083 case X86Local::MRM7m:
1084 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1085 break;
1086 MRM_MAPPING
1087 } // switch (Form)
1088 break;
1089 case 0xd8:
1090 case 0xd9:
1091 case 0xda:
1092 case 0xdb:
1093 case 0xdc:
1094 case 0xdd:
1095 case 0xde:
1096 case 0xdf:
1097 switch (Form) {
1098 default:
1099 llvm_unreachable("Unhandled escape opcode form");
1100 case X86Local::MRM0r:
1101 case X86Local::MRM1r:
1102 case X86Local::MRM2r:
1103 case X86Local::MRM3r:
1104 case X86Local::MRM4r:
1105 case X86Local::MRM5r:
1106 case X86Local::MRM6r:
1107 case X86Local::MRM7r:
1108 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1109 break;
1110 case X86Local::MRM0m:
1111 case X86Local::MRM1m:
1112 case X86Local::MRM2m:
1113 case X86Local::MRM3m:
1114 case X86Local::MRM4m:
1115 case X86Local::MRM5m:
1116 case X86Local::MRM6m:
1117 case X86Local::MRM7m:
1118 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1119 break;
1120 } // switch (Form)
1121 break;
1122 default:
1123 if (needsModRMForDecode(Form))
1124 filter = new ModFilter(isRegFormat(Form));
1125 else
1126 filter = new DumbFilter();
1127 break;
1128 } // switch (Opcode)
1129 opcodeToSet = Opcode;
1130 } // switch (Prefix)
1132 assert(opcodeType != (OpcodeType)-1 &&
1133 "Opcode type not set");
1134 assert(filter && "Filter not set");
1136 if (Form == X86Local::AddRegFrm) {
1137 assert(((opcodeToSet & 7) == 0) &&
1138 "ADDREG_FRM opcode not aligned");
1140 uint8_t currentOpcode;
1142 for (currentOpcode = opcodeToSet;
1143 currentOpcode < opcodeToSet + 8;
1144 ++currentOpcode)
1145 tables.setTableFields(opcodeType,
1146 insnContext(),
1147 currentOpcode,
1148 *filter,
1149 UID, Is32Bit, IgnoresVEX_L);
1150 } else {
1151 tables.setTableFields(opcodeType,
1152 insnContext(),
1153 opcodeToSet,
1154 *filter,
1155 UID, Is32Bit, IgnoresVEX_L);
1156 }
1158 delete filter;
1160 #undef MAP
1161 }
1163 #define TYPE(str, type) if (s == str) return type;
1164 OperandType RecognizableInstr::typeFromString(const std::string &s,
1165 bool isSSE,
1166 bool hasREX_WPrefix,
1167 bool hasOpSizePrefix) {
1168 if (isSSE) {
1169 // For SSE instructions, we ignore the OpSize prefix and force operand
1170 // sizes.
1171 TYPE("GR16", TYPE_R16)
1172 TYPE("GR32", TYPE_R32)
1173 TYPE("GR64", TYPE_R64)
1174 }
1175 if(hasREX_WPrefix) {
1176 // For instructions with a REX_W prefix, a declared 32-bit register encoding
1177 // is special.
1178 TYPE("GR32", TYPE_R32)
1179 }
1180 if(!hasOpSizePrefix) {
1181 // For instructions without an OpSize prefix, a declared 16-bit register or
1182 // immediate encoding is special.
1183 TYPE("GR16", TYPE_R16)
1184 TYPE("i16imm", TYPE_IMM16)
1185 }
1186 TYPE("i16mem", TYPE_Mv)
1187 TYPE("i16imm", TYPE_IMMv)
1188 TYPE("i16i8imm", TYPE_IMMv)
1189 TYPE("GR16", TYPE_Rv)
1190 TYPE("i32mem", TYPE_Mv)
1191 TYPE("i32imm", TYPE_IMMv)
1192 TYPE("i32i8imm", TYPE_IMM32)
1193 TYPE("u32u8imm", TYPE_IMM32)
1194 TYPE("GR32", TYPE_Rv)
1195 TYPE("GR32orGR64", TYPE_R32)
1196 TYPE("i64mem", TYPE_Mv)
1197 TYPE("i64i32imm", TYPE_IMM64)
1198 TYPE("i64i8imm", TYPE_IMM64)
1199 TYPE("GR64", TYPE_R64)
1200 TYPE("i8mem", TYPE_M8)
1201 TYPE("i8imm", TYPE_IMM8)
1202 TYPE("GR8", TYPE_R8)
1203 TYPE("VR128", TYPE_XMM128)
1204 TYPE("VR128X", TYPE_XMM128)
1205 TYPE("f128mem", TYPE_M128)
1206 TYPE("f256mem", TYPE_M256)
1207 TYPE("f512mem", TYPE_M512)
1208 TYPE("FR64", TYPE_XMM64)
1209 TYPE("FR64X", TYPE_XMM64)
1210 TYPE("f64mem", TYPE_M64FP)
1211 TYPE("sdmem", TYPE_M64FP)
1212 TYPE("FR32", TYPE_XMM32)
1213 TYPE("FR32X", TYPE_XMM32)
1214 TYPE("f32mem", TYPE_M32FP)
1215 TYPE("ssmem", TYPE_M32FP)
1216 TYPE("RST", TYPE_ST)
1217 TYPE("i128mem", TYPE_M128)
1218 TYPE("i256mem", TYPE_M256)
1219 TYPE("i512mem", TYPE_M512)
1220 TYPE("i64i32imm_pcrel", TYPE_REL64)
1221 TYPE("i16imm_pcrel", TYPE_REL16)
1222 TYPE("i32imm_pcrel", TYPE_REL32)
1223 TYPE("SSECC", TYPE_IMM3)
1224 TYPE("AVXCC", TYPE_IMM5)
1225 TYPE("AVX512RC", TYPE_IMM32)
1226 TYPE("brtarget", TYPE_RELv)
1227 TYPE("uncondbrtarget", TYPE_RELv)
1228 TYPE("brtarget8", TYPE_REL8)
1229 TYPE("f80mem", TYPE_M80FP)
1230 TYPE("lea32mem", TYPE_LEA)
1231 TYPE("lea64_32mem", TYPE_LEA)
1232 TYPE("lea64mem", TYPE_LEA)
1233 TYPE("VR64", TYPE_MM64)
1234 TYPE("i64imm", TYPE_IMMv)
1235 TYPE("opaque32mem", TYPE_M1616)
1236 TYPE("opaque48mem", TYPE_M1632)
1237 TYPE("opaque80mem", TYPE_M1664)
1238 TYPE("opaque512mem", TYPE_M512)
1239 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
1240 TYPE("DEBUG_REG", TYPE_DEBUGREG)
1241 TYPE("CONTROL_REG", TYPE_CONTROLREG)
1242 TYPE("offset8", TYPE_MOFFS8)
1243 TYPE("offset16", TYPE_MOFFS16)
1244 TYPE("offset32", TYPE_MOFFS32)
1245 TYPE("offset64", TYPE_MOFFS64)
1246 TYPE("VR256", TYPE_XMM256)
1247 TYPE("VR256X", TYPE_XMM256)
1248 TYPE("VR512", TYPE_XMM512)
1249 TYPE("VK1", TYPE_VK1)
1250 TYPE("VK1WM", TYPE_VK1)
1251 TYPE("VK8", TYPE_VK8)
1252 TYPE("VK8WM", TYPE_VK8)
1253 TYPE("VK16", TYPE_VK16)
1254 TYPE("VK16WM", TYPE_VK16)
1255 TYPE("GR16_NOAX", TYPE_Rv)
1256 TYPE("GR32_NOAX", TYPE_Rv)
1257 TYPE("GR64_NOAX", TYPE_R64)
1258 TYPE("vx32mem", TYPE_M32)
1259 TYPE("vy32mem", TYPE_M32)
1260 TYPE("vz32mem", TYPE_M32)
1261 TYPE("vx64mem", TYPE_M64)
1262 TYPE("vy64mem", TYPE_M64)
1263 TYPE("vy64xmem", TYPE_M64)
1264 TYPE("vz64mem", TYPE_M64)
1265 errs() << "Unhandled type string " << s << "\n";
1266 llvm_unreachable("Unhandled type string");
1267 }
1268 #undef TYPE
1270 #define ENCODING(str, encoding) if (s == str) return encoding;
1271 OperandEncoding RecognizableInstr::immediateEncodingFromString
1272 (const std::string &s,
1273 bool hasOpSizePrefix) {
1274 if(!hasOpSizePrefix) {
1275 // For instructions without an OpSize prefix, a declared 16-bit register or
1276 // immediate encoding is special.
1277 ENCODING("i16imm", ENCODING_IW)
1278 }
1279 ENCODING("i32i8imm", ENCODING_IB)
1280 ENCODING("u32u8imm", ENCODING_IB)
1281 ENCODING("SSECC", ENCODING_IB)
1282 ENCODING("AVXCC", ENCODING_IB)
1283 ENCODING("AVX512RC", ENCODING_IB)
1284 ENCODING("i16imm", ENCODING_Iv)
1285 ENCODING("i16i8imm", ENCODING_IB)
1286 ENCODING("i32imm", ENCODING_Iv)
1287 ENCODING("i64i32imm", ENCODING_ID)
1288 ENCODING("i64i8imm", ENCODING_IB)
1289 ENCODING("i8imm", ENCODING_IB)
1290 // This is not a typo. Instructions like BLENDVPD put
1291 // register IDs in 8-bit immediates nowadays.
1292 ENCODING("FR32", ENCODING_IB)
1293 ENCODING("FR64", ENCODING_IB)
1294 ENCODING("VR128", ENCODING_IB)
1295 ENCODING("VR256", ENCODING_IB)
1296 ENCODING("FR32X", ENCODING_IB)
1297 ENCODING("FR64X", ENCODING_IB)
1298 ENCODING("VR128X", ENCODING_IB)
1299 ENCODING("VR256X", ENCODING_IB)
1300 ENCODING("VR512", ENCODING_IB)
1301 errs() << "Unhandled immediate encoding " << s << "\n";
1302 llvm_unreachable("Unhandled immediate encoding");
1303 }
1305 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1306 (const std::string &s,
1307 bool hasOpSizePrefix) {
1308 ENCODING("RST", ENCODING_FP)
1309 ENCODING("GR16", ENCODING_RM)
1310 ENCODING("GR32", ENCODING_RM)
1311 ENCODING("GR32orGR64", ENCODING_RM)
1312 ENCODING("GR64", ENCODING_RM)
1313 ENCODING("GR8", ENCODING_RM)
1314 ENCODING("VR128", ENCODING_RM)
1315 ENCODING("VR128X", ENCODING_RM)
1316 ENCODING("FR64", ENCODING_RM)
1317 ENCODING("FR32", ENCODING_RM)
1318 ENCODING("FR64X", ENCODING_RM)
1319 ENCODING("FR32X", ENCODING_RM)
1320 ENCODING("VR64", ENCODING_RM)
1321 ENCODING("VR256", ENCODING_RM)
1322 ENCODING("VR256X", ENCODING_RM)
1323 ENCODING("VR512", ENCODING_RM)
1324 ENCODING("VK1", ENCODING_RM)
1325 ENCODING("VK8", ENCODING_RM)
1326 ENCODING("VK16", ENCODING_RM)
1327 errs() << "Unhandled R/M register encoding " << s << "\n";
1328 llvm_unreachable("Unhandled R/M register encoding");
1329 }
1331 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1332 (const std::string &s,
1333 bool hasOpSizePrefix) {
1334 ENCODING("GR16", ENCODING_REG)
1335 ENCODING("GR32", ENCODING_REG)
1336 ENCODING("GR32orGR64", ENCODING_REG)
1337 ENCODING("GR64", ENCODING_REG)
1338 ENCODING("GR8", ENCODING_REG)
1339 ENCODING("VR128", ENCODING_REG)
1340 ENCODING("FR64", ENCODING_REG)
1341 ENCODING("FR32", ENCODING_REG)
1342 ENCODING("VR64", ENCODING_REG)
1343 ENCODING("SEGMENT_REG", ENCODING_REG)
1344 ENCODING("DEBUG_REG", ENCODING_REG)
1345 ENCODING("CONTROL_REG", ENCODING_REG)
1346 ENCODING("VR256", ENCODING_REG)
1347 ENCODING("VR256X", ENCODING_REG)
1348 ENCODING("VR128X", ENCODING_REG)
1349 ENCODING("FR64X", ENCODING_REG)
1350 ENCODING("FR32X", ENCODING_REG)
1351 ENCODING("VR512", ENCODING_REG)
1352 ENCODING("VK1", ENCODING_REG)
1353 ENCODING("VK8", ENCODING_REG)
1354 ENCODING("VK16", ENCODING_REG)
1355 ENCODING("VK1WM", ENCODING_REG)
1356 ENCODING("VK8WM", ENCODING_REG)
1357 ENCODING("VK16WM", ENCODING_REG)
1358 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1359 llvm_unreachable("Unhandled reg/opcode register encoding");
1360 }
1362 OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1363 (const std::string &s,
1364 bool hasOpSizePrefix) {
1365 ENCODING("GR32", ENCODING_VVVV)
1366 ENCODING("GR64", ENCODING_VVVV)
1367 ENCODING("FR32", ENCODING_VVVV)
1368 ENCODING("FR64", ENCODING_VVVV)
1369 ENCODING("VR128", ENCODING_VVVV)
1370 ENCODING("VR256", ENCODING_VVVV)
1371 ENCODING("FR32X", ENCODING_VVVV)
1372 ENCODING("FR64X", ENCODING_VVVV)
1373 ENCODING("VR128X", ENCODING_VVVV)
1374 ENCODING("VR256X", ENCODING_VVVV)
1375 ENCODING("VR512", ENCODING_VVVV)
1376 ENCODING("VK1", ENCODING_VVVV)
1377 ENCODING("VK8", ENCODING_VVVV)
1378 ENCODING("VK16", ENCODING_VVVV)
1379 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1380 llvm_unreachable("Unhandled VEX.vvvv register encoding");
1381 }
1383 OperandEncoding RecognizableInstr::writemaskRegisterEncodingFromString
1384 (const std::string &s,
1385 bool hasOpSizePrefix) {
1386 ENCODING("VK1WM", ENCODING_WRITEMASK)
1387 ENCODING("VK8WM", ENCODING_WRITEMASK)
1388 ENCODING("VK16WM", ENCODING_WRITEMASK)
1389 errs() << "Unhandled mask register encoding " << s << "\n";
1390 llvm_unreachable("Unhandled mask register encoding");
1391 }
1393 OperandEncoding RecognizableInstr::memoryEncodingFromString
1394 (const std::string &s,
1395 bool hasOpSizePrefix) {
1396 ENCODING("i16mem", ENCODING_RM)
1397 ENCODING("i32mem", ENCODING_RM)
1398 ENCODING("i64mem", ENCODING_RM)
1399 ENCODING("i8mem", ENCODING_RM)
1400 ENCODING("ssmem", ENCODING_RM)
1401 ENCODING("sdmem", ENCODING_RM)
1402 ENCODING("f128mem", ENCODING_RM)
1403 ENCODING("f256mem", ENCODING_RM)
1404 ENCODING("f512mem", ENCODING_RM)
1405 ENCODING("f64mem", ENCODING_RM)
1406 ENCODING("f32mem", ENCODING_RM)
1407 ENCODING("i128mem", ENCODING_RM)
1408 ENCODING("i256mem", ENCODING_RM)
1409 ENCODING("i512mem", ENCODING_RM)
1410 ENCODING("f80mem", ENCODING_RM)
1411 ENCODING("lea32mem", ENCODING_RM)
1412 ENCODING("lea64_32mem", ENCODING_RM)
1413 ENCODING("lea64mem", ENCODING_RM)
1414 ENCODING("opaque32mem", ENCODING_RM)
1415 ENCODING("opaque48mem", ENCODING_RM)
1416 ENCODING("opaque80mem", ENCODING_RM)
1417 ENCODING("opaque512mem", ENCODING_RM)
1418 ENCODING("vx32mem", ENCODING_RM)
1419 ENCODING("vy32mem", ENCODING_RM)
1420 ENCODING("vz32mem", ENCODING_RM)
1421 ENCODING("vx64mem", ENCODING_RM)
1422 ENCODING("vy64mem", ENCODING_RM)
1423 ENCODING("vy64xmem", ENCODING_RM)
1424 ENCODING("vz64mem", ENCODING_RM)
1425 errs() << "Unhandled memory encoding " << s << "\n";
1426 llvm_unreachable("Unhandled memory encoding");
1427 }
1429 OperandEncoding RecognizableInstr::relocationEncodingFromString
1430 (const std::string &s,
1431 bool hasOpSizePrefix) {
1432 if(!hasOpSizePrefix) {
1433 // For instructions without an OpSize prefix, a declared 16-bit register or
1434 // immediate encoding is special.
1435 ENCODING("i16imm", ENCODING_IW)
1436 }
1437 ENCODING("i16imm", ENCODING_Iv)
1438 ENCODING("i16i8imm", ENCODING_IB)
1439 ENCODING("i32imm", ENCODING_Iv)
1440 ENCODING("i32i8imm", ENCODING_IB)
1441 ENCODING("i64i32imm", ENCODING_ID)
1442 ENCODING("i64i8imm", ENCODING_IB)
1443 ENCODING("i8imm", ENCODING_IB)
1444 ENCODING("i64i32imm_pcrel", ENCODING_ID)
1445 ENCODING("i16imm_pcrel", ENCODING_IW)
1446 ENCODING("i32imm_pcrel", ENCODING_ID)
1447 ENCODING("brtarget", ENCODING_Iv)
1448 ENCODING("brtarget8", ENCODING_IB)
1449 ENCODING("i64imm", ENCODING_IO)
1450 ENCODING("offset8", ENCODING_Ia)
1451 ENCODING("offset16", ENCODING_Ia)
1452 ENCODING("offset32", ENCODING_Ia)
1453 ENCODING("offset64", ENCODING_Ia)
1454 errs() << "Unhandled relocation encoding " << s << "\n";
1455 llvm_unreachable("Unhandled relocation encoding");
1456 }
1458 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1459 (const std::string &s,
1460 bool hasOpSizePrefix) {
1461 ENCODING("GR32", ENCODING_Rv)
1462 ENCODING("GR64", ENCODING_RO)
1463 ENCODING("GR16", ENCODING_Rv)
1464 ENCODING("GR8", ENCODING_RB)
1465 ENCODING("GR16_NOAX", ENCODING_Rv)
1466 ENCODING("GR32_NOAX", ENCODING_Rv)
1467 ENCODING("GR64_NOAX", ENCODING_RO)
1468 errs() << "Unhandled opcode modifier encoding " << s << "\n";
1469 llvm_unreachable("Unhandled opcode modifier encoding");
1470 }
1471 #undef ENCODING