1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
14 //
15 //===----------------------------------------------------------------------===//
17 #include "X86RecognizableInstr.h"
18 #include "X86DisassemblerShared.h"
19 #include "X86ModRMFilters.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include <string>
23 using namespace llvm;
25 #define MRM_MAPPING \
26 MAP(C1, 33) \
27 MAP(C2, 34) \
28 MAP(C3, 35) \
29 MAP(C4, 36) \
30 MAP(C8, 37) \
31 MAP(C9, 38) \
32 MAP(CA, 39) \
33 MAP(CB, 40) \
34 MAP(E8, 41) \
35 MAP(F0, 42) \
36 MAP(F8, 45) \
37 MAP(F9, 46) \
38 MAP(D0, 47) \
39 MAP(D1, 48) \
40 MAP(D4, 49) \
41 MAP(D5, 50) \
42 MAP(D6, 51) \
43 MAP(D8, 52) \
44 MAP(D9, 53) \
45 MAP(DA, 54) \
46 MAP(DB, 55) \
47 MAP(DC, 56) \
48 MAP(DD, 57) \
49 MAP(DE, 58) \
50 MAP(DF, 59)
52 // A clone of X86 since we can't depend on something that is generated.
53 namespace X86Local {
54 enum {
55 Pseudo = 0,
56 RawFrm = 1,
57 AddRegFrm = 2,
58 MRMDestReg = 3,
59 MRMDestMem = 4,
60 MRMSrcReg = 5,
61 MRMSrcMem = 6,
62 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
63 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
64 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
65 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
66 MRMInitReg = 32,
67 RawFrmImm8 = 43,
68 RawFrmImm16 = 44,
69 #define MAP(from, to) MRM_##from = to,
70 MRM_MAPPING
71 #undef MAP
72 lastMRM
73 };
75 enum {
76 TB = 1,
77 REP = 2,
78 D8 = 3, D9 = 4, DA = 5, DB = 6,
79 DC = 7, DD = 8, DE = 9, DF = 10,
80 XD = 11, XS = 12,
81 T8 = 13, P_TA = 14,
82 A6 = 15, A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19,
83 XOP8 = 20, XOP9 = 21, XOPA = 22, PD = 23, T8PD = 24, TAPD = 25
84 };
85 }
87 // If rows are added to the opcode extension tables, then corresponding entries
88 // must be added here.
89 //
90 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
91 // that byte to ONE_BYTE_EXTENSION_TABLES.
92 //
93 // If the row corresponds to two bytes where the first is 0f, add an entry for
94 // the second byte to TWO_BYTE_EXTENSION_TABLES.
95 //
96 // If the row corresponds to some other set of bytes, you will need to modify
97 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
98 // to the X86 TD files, except in two cases: if the first two bytes of such a
99 // new combination are 0f 38 or 0f 3a, you just have to add maps called
100 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
101 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
102 // in RecognizableInstr::emitDecodePath().
104 #define ONE_BYTE_EXTENSION_TABLES \
105 EXTENSION_TABLE(80) \
106 EXTENSION_TABLE(81) \
107 EXTENSION_TABLE(82) \
108 EXTENSION_TABLE(83) \
109 EXTENSION_TABLE(8f) \
110 EXTENSION_TABLE(c0) \
111 EXTENSION_TABLE(c1) \
112 EXTENSION_TABLE(c6) \
113 EXTENSION_TABLE(c7) \
114 EXTENSION_TABLE(d0) \
115 EXTENSION_TABLE(d1) \
116 EXTENSION_TABLE(d2) \
117 EXTENSION_TABLE(d3) \
118 EXTENSION_TABLE(f6) \
119 EXTENSION_TABLE(f7) \
120 EXTENSION_TABLE(fe) \
121 EXTENSION_TABLE(ff)
123 #define TWO_BYTE_EXTENSION_TABLES \
124 EXTENSION_TABLE(00) \
125 EXTENSION_TABLE(01) \
126 EXTENSION_TABLE(0d) \
127 EXTENSION_TABLE(18) \
128 EXTENSION_TABLE(71) \
129 EXTENSION_TABLE(72) \
130 EXTENSION_TABLE(73) \
131 EXTENSION_TABLE(ae) \
132 EXTENSION_TABLE(ba) \
133 EXTENSION_TABLE(c7)
135 #define THREE_BYTE_38_EXTENSION_TABLES \
136 EXTENSION_TABLE(F3)
138 #define XOP9_MAP_EXTENSION_TABLES \
139 EXTENSION_TABLE(01) \
140 EXTENSION_TABLE(02)
142 using namespace X86Disassembler;
144 /// needsModRMForDecode - Indicates whether a particular instruction requires a
145 /// ModR/M byte for the instruction to be properly decoded. For example, a
146 /// MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
147 /// 0b11.
148 ///
149 /// @param form - The form of the instruction.
150 /// @return - true if the form implies that a ModR/M byte is required, false
151 /// otherwise.
152 static bool needsModRMForDecode(uint8_t form) {
153 if (form == X86Local::MRMDestReg ||
154 form == X86Local::MRMDestMem ||
155 form == X86Local::MRMSrcReg ||
156 form == X86Local::MRMSrcMem ||
157 (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
158 (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
159 return true;
160 else
161 return false;
162 }
164 /// isRegFormat - Indicates whether a particular form requires the Mod field of
165 /// the ModR/M byte to be 0b11.
166 ///
167 /// @param form - The form of the instruction.
168 /// @return - true if the form implies that Mod must be 0b11, false
169 /// otherwise.
170 static bool isRegFormat(uint8_t form) {
171 if (form == X86Local::MRMDestReg ||
172 form == X86Local::MRMSrcReg ||
173 (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
174 return true;
175 else
176 return false;
177 }
179 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
180 /// Useful for switch statements and the like.
181 ///
182 /// @param init - A reference to the BitsInit to be decoded.
183 /// @return - The field, with the first bit in the BitsInit as the lowest
184 /// order bit.
185 static uint8_t byteFromBitsInit(BitsInit &init) {
186 int width = init.getNumBits();
188 assert(width <= 8 && "Field is too large for uint8_t!");
190 int index;
191 uint8_t mask = 0x01;
193 uint8_t ret = 0;
195 for (index = 0; index < width; index++) {
196 if (static_cast<BitInit*>(init.getBit(index))->getValue())
197 ret |= mask;
199 mask <<= 1;
200 }
202 return ret;
203 }
205 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
206 /// name of the field.
207 ///
208 /// @param rec - The record from which to extract the value.
209 /// @param name - The name of the field in the record.
210 /// @return - The field, as translated by byteFromBitsInit().
211 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
212 BitsInit* bits = rec->getValueAsBitsInit(name);
213 return byteFromBitsInit(*bits);
214 }
216 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
217 const CodeGenInstruction &insn,
218 InstrUID uid) {
219 UID = uid;
221 Rec = insn.TheDef;
222 Name = Rec->getName();
223 Spec = &tables.specForUID(UID);
225 if (!Rec->isSubClassOf("X86Inst")) {
226 ShouldBeEmitted = false;
227 return;
228 }
230 Prefix = byteFromRec(Rec, "Prefix");
231 Opcode = byteFromRec(Rec, "Opcode");
232 Form = byteFromRec(Rec, "FormBits");
234 HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix");
235 HasAdSizePrefix = Rec->getValueAsBit("hasAdSizePrefix");
236 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
237 HasVEXPrefix = Rec->getValueAsBit("hasVEXPrefix");
238 HasVEX_4VPrefix = Rec->getValueAsBit("hasVEX_4VPrefix");
239 HasVEX_4VOp3Prefix = Rec->getValueAsBit("hasVEX_4VOp3Prefix");
240 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix");
241 HasMemOp4Prefix = Rec->getValueAsBit("hasMemOp4Prefix");
242 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
243 HasEVEXPrefix = Rec->getValueAsBit("hasEVEXPrefix");
244 HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2");
245 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K");
246 HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z");
247 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B");
248 HasLockPrefix = Rec->getValueAsBit("hasLockPrefix");
249 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
250 ForceDisassemble = Rec->getValueAsBit("ForceDisassemble");
252 Name = Rec->getName();
253 AsmString = Rec->getValueAsString("AsmString");
255 Operands = &insn.Operands.OperandList;
257 IsSSE = ((HasOpSizePrefix || Prefix == X86Local::PD ||
258 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD) &&
259 (Name.find("16") == Name.npos)) ||
260 (Name.find("CRC32") != Name.npos);
261 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L");
263 // Check for 64-bit inst which does not require REX
264 Is32Bit = false;
265 Is64Bit = false;
266 // FIXME: Is there some better way to check for In64BitMode?
267 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
268 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
269 if (Predicates[i]->getName().find("Not64Bit") != Name.npos ||
270 Predicates[i]->getName().find("In32Bit") != Name.npos) {
271 Is32Bit = true;
272 break;
273 }
274 if (Predicates[i]->getName().find("In64Bit") != Name.npos) {
275 Is64Bit = true;
276 break;
277 }
278 }
280 ShouldBeEmitted = true;
281 }
283 void RecognizableInstr::processInstr(DisassemblerTables &tables,
284 const CodeGenInstruction &insn,
285 InstrUID uid)
286 {
287 // Ignore "asm parser only" instructions.
288 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
289 return;
291 RecognizableInstr recogInstr(tables, insn, uid);
293 recogInstr.emitInstructionSpecifier();
295 if (recogInstr.shouldBeEmitted())
296 recogInstr.emitDecodePath(tables);
297 }
299 #define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \
300 (HasEVEX_K && HasEVEX_B ? n##_K_B : \
301 (HasEVEX_KZ ? n##_KZ : \
302 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n)))))
304 InstructionContext RecognizableInstr::insnContext() const {
305 InstructionContext insnContext;
307 if (HasEVEXPrefix) {
308 if (HasVEX_LPrefix && HasEVEX_L2Prefix) {
309 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n";
310 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled");
311 }
312 // VEX_L & VEX_W
313 if (HasVEX_LPrefix && HasVEX_WPrefix) {
314 if (HasOpSizePrefix || Prefix == X86Local::PD)
315 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE);
316 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
317 insnContext = EVEX_KB(IC_EVEX_L_W_XS);
318 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
319 Prefix == X86Local::TAXD)
320 insnContext = EVEX_KB(IC_EVEX_L_W_XD);
321 else
322 insnContext = EVEX_KB(IC_EVEX_L_W);
323 } else if (HasVEX_LPrefix) {
324 // VEX_L
325 if (HasOpSizePrefix || Prefix == X86Local::PD ||
326 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
327 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE);
328 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
329 insnContext = EVEX_KB(IC_EVEX_L_XS);
330 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
331 Prefix == X86Local::TAXD)
332 insnContext = EVEX_KB(IC_EVEX_L_XD);
333 else
334 insnContext = EVEX_KB(IC_EVEX_L);
335 }
336 else if (HasEVEX_L2Prefix && HasVEX_WPrefix) {
337 // EVEX_L2 & VEX_W
338 if (HasOpSizePrefix || Prefix == X86Local::PD ||
339 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
340 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE);
341 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
342 insnContext = EVEX_KB(IC_EVEX_L2_W_XS);
343 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
344 Prefix == X86Local::TAXD)
345 insnContext = EVEX_KB(IC_EVEX_L2_W_XD);
346 else
347 insnContext = EVEX_KB(IC_EVEX_L2_W);
348 } else if (HasEVEX_L2Prefix) {
349 // EVEX_L2
350 if (HasOpSizePrefix || Prefix == X86Local::PD ||
351 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
352 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE);
353 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
354 Prefix == X86Local::TAXD)
355 insnContext = EVEX_KB(IC_EVEX_L2_XD);
356 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
357 insnContext = EVEX_KB(IC_EVEX_L2_XS);
358 else
359 insnContext = EVEX_KB(IC_EVEX_L2);
360 }
361 else if (HasVEX_WPrefix) {
362 // VEX_W
363 if (HasOpSizePrefix || Prefix == X86Local::PD ||
364 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
365 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE);
366 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
367 insnContext = EVEX_KB(IC_EVEX_W_XS);
368 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
369 Prefix == X86Local::TAXD)
370 insnContext = EVEX_KB(IC_EVEX_W_XD);
371 else
372 insnContext = EVEX_KB(IC_EVEX_W);
373 }
374 // No L, no W
375 else if (HasOpSizePrefix || Prefix == X86Local::PD ||
376 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
377 insnContext = EVEX_KB(IC_EVEX_OPSIZE);
378 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
379 Prefix == X86Local::TAXD)
380 insnContext = EVEX_KB(IC_EVEX_XD);
381 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
382 insnContext = EVEX_KB(IC_EVEX_XS);
383 else
384 insnContext = EVEX_KB(IC_EVEX);
385 /// eof EVEX
386 } else if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) {
387 if (HasVEX_LPrefix && HasVEX_WPrefix) {
388 if (HasOpSizePrefix || Prefix == X86Local::PD ||
389 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
390 insnContext = IC_VEX_L_W_OPSIZE;
391 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
392 insnContext = IC_VEX_L_W_XS;
393 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
394 Prefix == X86Local::TAXD)
395 insnContext = IC_VEX_L_W_XD;
396 else
397 insnContext = IC_VEX_L_W;
398 } else if ((HasOpSizePrefix || Prefix == X86Local::PD ||
399 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD) &&
400 HasVEX_LPrefix)
401 insnContext = IC_VEX_L_OPSIZE;
402 else if ((HasOpSizePrefix || Prefix == X86Local::PD ||
403 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD) &&
404 HasVEX_WPrefix)
405 insnContext = IC_VEX_W_OPSIZE;
406 else if (HasOpSizePrefix || Prefix == X86Local::PD ||
407 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
408 insnContext = IC_VEX_OPSIZE;
409 else if (HasVEX_LPrefix &&
410 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
411 insnContext = IC_VEX_L_XS;
412 else if (HasVEX_LPrefix && (Prefix == X86Local::XD ||
413 Prefix == X86Local::T8XD ||
414 Prefix == X86Local::TAXD))
415 insnContext = IC_VEX_L_XD;
416 else if (HasVEX_WPrefix &&
417 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
418 insnContext = IC_VEX_W_XS;
419 else if (HasVEX_WPrefix && (Prefix == X86Local::XD ||
420 Prefix == X86Local::T8XD ||
421 Prefix == X86Local::TAXD))
422 insnContext = IC_VEX_W_XD;
423 else if (HasVEX_WPrefix)
424 insnContext = IC_VEX_W;
425 else if (HasVEX_LPrefix)
426 insnContext = IC_VEX_L;
427 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
428 Prefix == X86Local::TAXD)
429 insnContext = IC_VEX_XD;
430 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
431 insnContext = IC_VEX_XS;
432 else
433 insnContext = IC_VEX;
434 } else if (Is64Bit || HasREX_WPrefix) {
435 if (HasREX_WPrefix && (HasOpSizePrefix || Prefix == X86Local::PD ||
436 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD))
437 insnContext = IC_64BIT_REXW_OPSIZE;
438 else if (HasOpSizePrefix && (Prefix == X86Local::XD ||
439 Prefix == X86Local::T8XD ||
440 Prefix == X86Local::TAXD))
441 insnContext = IC_64BIT_XD_OPSIZE;
442 else if (HasOpSizePrefix &&
443 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
444 insnContext = IC_64BIT_XS_OPSIZE;
445 else if (HasOpSizePrefix || Prefix == X86Local::PD ||
446 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
447 insnContext = IC_64BIT_OPSIZE;
448 else if (HasAdSizePrefix)
449 insnContext = IC_64BIT_ADSIZE;
450 else if (HasREX_WPrefix &&
451 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
452 insnContext = IC_64BIT_REXW_XS;
453 else if (HasREX_WPrefix && (Prefix == X86Local::XD ||
454 Prefix == X86Local::T8XD ||
455 Prefix == X86Local::TAXD))
456 insnContext = IC_64BIT_REXW_XD;
457 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
458 Prefix == X86Local::TAXD)
459 insnContext = IC_64BIT_XD;
460 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
461 insnContext = IC_64BIT_XS;
462 else if (HasREX_WPrefix)
463 insnContext = IC_64BIT_REXW;
464 else
465 insnContext = IC_64BIT;
466 } else {
467 if (HasOpSizePrefix && (Prefix == X86Local::XD ||
468 Prefix == X86Local::T8XD ||
469 Prefix == X86Local::TAXD))
470 insnContext = IC_XD_OPSIZE;
471 else if (HasOpSizePrefix &&
472 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
473 insnContext = IC_XS_OPSIZE;
474 else if (HasOpSizePrefix && HasAdSizePrefix)
475 insnContext = IC_OPSIZE_ADSIZE;
476 else if (HasOpSizePrefix || Prefix == X86Local::PD ||
477 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
478 insnContext = IC_OPSIZE;
479 else if (HasAdSizePrefix)
480 insnContext = IC_ADSIZE;
481 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
482 Prefix == X86Local::TAXD)
483 insnContext = IC_XD;
484 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS ||
485 Prefix == X86Local::REP)
486 insnContext = IC_XS;
487 else
488 insnContext = IC;
489 }
491 return insnContext;
492 }
494 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
495 ///////////////////
496 // FILTER_STRONG
497 //
499 // Filter out intrinsics
501 assert(Rec->isSubClassOf("X86Inst") && "Can only filter X86 instructions");
503 if (Form == X86Local::Pseudo || (IsCodeGenOnly && !ForceDisassemble))
504 return FILTER_STRONG;
507 // Filter out artificial instructions but leave in the LOCK_PREFIX so it is
508 // printed as a separate "instruction".
511 /////////////////
512 // FILTER_WEAK
513 //
516 // Filter out instructions with a LOCK prefix;
517 // prefer forms that do not have the prefix
518 if (HasLockPrefix)
519 return FILTER_WEAK;
521 // Special cases.
523 if (Name == "VMASKMOVDQU64")
524 return FILTER_WEAK;
526 // XACQUIRE and XRELEASE reuse REPNE and REP respectively.
527 // For now, just prefer the REP versions.
528 if (Name == "XACQUIRE_PREFIX" ||
529 Name == "XRELEASE_PREFIX")
530 return FILTER_WEAK;
532 return FILTER_NORMAL;
533 }
535 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
536 unsigned &physicalOperandIndex,
537 unsigned &numPhysicalOperands,
538 const unsigned *operandMapping,
539 OperandEncoding (*encodingFromString)
540 (const std::string&,
541 bool hasOpSizePrefix)) {
542 if (optional) {
543 if (physicalOperandIndex >= numPhysicalOperands)
544 return;
545 } else {
546 assert(physicalOperandIndex < numPhysicalOperands);
547 }
549 while (operandMapping[operandIndex] != operandIndex) {
550 Spec->operands[operandIndex].encoding = ENCODING_DUP;
551 Spec->operands[operandIndex].type =
552 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
553 ++operandIndex;
554 }
556 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
558 Spec->operands[operandIndex].encoding = encodingFromString(typeName,
559 HasOpSizePrefix);
560 Spec->operands[operandIndex].type = typeFromString(typeName,
561 IsSSE,
562 HasREX_WPrefix,
563 HasOpSizePrefix);
565 ++operandIndex;
566 ++physicalOperandIndex;
567 }
569 void RecognizableInstr::emitInstructionSpecifier() {
570 Spec->name = Name;
572 if (!ShouldBeEmitted)
573 return;
575 switch (filter()) {
576 case FILTER_WEAK:
577 Spec->filtered = true;
578 break;
579 case FILTER_STRONG:
580 ShouldBeEmitted = false;
581 return;
582 case FILTER_NORMAL:
583 break;
584 }
586 Spec->insnContext = insnContext();
588 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
590 unsigned numOperands = OperandList.size();
591 unsigned numPhysicalOperands = 0;
593 // operandMapping maps from operands in OperandList to their originals.
594 // If operandMapping[i] != i, then the entry is a duplicate.
595 unsigned operandMapping[X86_MAX_OPERANDS];
596 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
598 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
599 if (OperandList[operandIndex].Constraints.size()) {
600 const CGIOperandList::ConstraintInfo &Constraint =
601 OperandList[operandIndex].Constraints[0];
602 if (Constraint.isTied()) {
603 operandMapping[operandIndex] = operandIndex;
604 operandMapping[Constraint.getTiedOperand()] = operandIndex;
605 } else {
606 ++numPhysicalOperands;
607 operandMapping[operandIndex] = operandIndex;
608 }
609 } else {
610 ++numPhysicalOperands;
611 operandMapping[operandIndex] = operandIndex;
612 }
613 }
615 #define HANDLE_OPERAND(class) \
616 handleOperand(false, \
617 operandIndex, \
618 physicalOperandIndex, \
619 numPhysicalOperands, \
620 operandMapping, \
621 class##EncodingFromString);
623 #define HANDLE_OPTIONAL(class) \
624 handleOperand(true, \
625 operandIndex, \
626 physicalOperandIndex, \
627 numPhysicalOperands, \
628 operandMapping, \
629 class##EncodingFromString);
631 // operandIndex should always be < numOperands
632 unsigned operandIndex = 0;
633 // physicalOperandIndex should always be < numPhysicalOperands
634 unsigned physicalOperandIndex = 0;
636 switch (Form) {
637 case X86Local::RawFrm:
638 // Operand 1 (optional) is an address or immediate.
639 // Operand 2 (optional) is an immediate.
640 assert(numPhysicalOperands <= 2 &&
641 "Unexpected number of operands for RawFrm");
642 HANDLE_OPTIONAL(relocation)
643 HANDLE_OPTIONAL(immediate)
644 break;
645 case X86Local::AddRegFrm:
646 // Operand 1 is added to the opcode.
647 // Operand 2 (optional) is an address.
648 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
649 "Unexpected number of operands for AddRegFrm");
650 HANDLE_OPERAND(opcodeModifier)
651 HANDLE_OPTIONAL(relocation)
652 break;
653 case X86Local::MRMDestReg:
654 // Operand 1 is a register operand in the R/M field.
655 // Operand 2 is a register operand in the Reg/Opcode field.
656 // - In AVX, there is a register operand in the VEX.vvvv field here -
657 // Operand 3 (optional) is an immediate.
658 if (HasVEX_4VPrefix)
659 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
660 "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
661 else
662 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
663 "Unexpected number of operands for MRMDestRegFrm");
665 HANDLE_OPERAND(rmRegister)
667 if (HasVEX_4VPrefix)
668 // FIXME: In AVX, the register below becomes the one encoded
669 // in ModRMVEX and the one above the one in the VEX.VVVV field
670 HANDLE_OPERAND(vvvvRegister)
672 HANDLE_OPERAND(roRegister)
673 HANDLE_OPTIONAL(immediate)
674 break;
675 case X86Local::MRMDestMem:
676 // Operand 1 is a memory operand (possibly SIB-extended)
677 // Operand 2 is a register operand in the Reg/Opcode field.
678 // - In AVX, there is a register operand in the VEX.vvvv field here -
679 // Operand 3 (optional) is an immediate.
680 if (HasVEX_4VPrefix)
681 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
682 "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
683 else
684 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
685 "Unexpected number of operands for MRMDestMemFrm");
686 HANDLE_OPERAND(memory)
688 if (HasEVEX_K)
689 HANDLE_OPERAND(writemaskRegister)
691 if (HasVEX_4VPrefix)
692 // FIXME: In AVX, the register below becomes the one encoded
693 // in ModRMVEX and the one above the one in the VEX.VVVV field
694 HANDLE_OPERAND(vvvvRegister)
696 HANDLE_OPERAND(roRegister)
697 HANDLE_OPTIONAL(immediate)
698 break;
699 case X86Local::MRMSrcReg:
700 // Operand 1 is a register operand in the Reg/Opcode field.
701 // Operand 2 is a register operand in the R/M field.
702 // - In AVX, there is a register operand in the VEX.vvvv field here -
703 // Operand 3 (optional) is an immediate.
704 // Operand 4 (optional) is an immediate.
706 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
707 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
708 "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
709 else
710 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 4 &&
711 "Unexpected number of operands for MRMSrcRegFrm");
713 HANDLE_OPERAND(roRegister)
715 if (HasEVEX_K)
716 HANDLE_OPERAND(writemaskRegister)
718 if (HasVEX_4VPrefix)
719 // FIXME: In AVX, the register below becomes the one encoded
720 // in ModRMVEX and the one above the one in the VEX.VVVV field
721 HANDLE_OPERAND(vvvvRegister)
723 if (HasMemOp4Prefix)
724 HANDLE_OPERAND(immediate)
726 HANDLE_OPERAND(rmRegister)
728 if (HasVEX_4VOp3Prefix)
729 HANDLE_OPERAND(vvvvRegister)
731 if (!HasMemOp4Prefix)
732 HANDLE_OPTIONAL(immediate)
733 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
734 HANDLE_OPTIONAL(immediate)
735 break;
736 case X86Local::MRMSrcMem:
737 // Operand 1 is a register operand in the Reg/Opcode field.
738 // Operand 2 is a memory operand (possibly SIB-extended)
739 // - In AVX, there is a register operand in the VEX.vvvv field here -
740 // Operand 3 (optional) is an immediate.
742 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
743 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
744 "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
745 else
746 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
747 "Unexpected number of operands for MRMSrcMemFrm");
749 HANDLE_OPERAND(roRegister)
751 if (HasEVEX_K)
752 HANDLE_OPERAND(writemaskRegister)
754 if (HasVEX_4VPrefix)
755 // FIXME: In AVX, the register below becomes the one encoded
756 // in ModRMVEX and the one above the one in the VEX.VVVV field
757 HANDLE_OPERAND(vvvvRegister)
759 if (HasMemOp4Prefix)
760 HANDLE_OPERAND(immediate)
762 HANDLE_OPERAND(memory)
764 if (HasVEX_4VOp3Prefix)
765 HANDLE_OPERAND(vvvvRegister)
767 if (!HasMemOp4Prefix)
768 HANDLE_OPTIONAL(immediate)
769 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
770 break;
771 case X86Local::MRM0r:
772 case X86Local::MRM1r:
773 case X86Local::MRM2r:
774 case X86Local::MRM3r:
775 case X86Local::MRM4r:
776 case X86Local::MRM5r:
777 case X86Local::MRM6r:
778 case X86Local::MRM7r:
779 {
780 // Operand 1 is a register operand in the R/M field.
781 // Operand 2 (optional) is an immediate or relocation.
782 // Operand 3 (optional) is an immediate.
783 unsigned kOp = (HasEVEX_K) ? 1:0;
784 unsigned Op4v = (HasVEX_4VPrefix) ? 1:0;
785 if (numPhysicalOperands > 3 + kOp + Op4v)
786 llvm_unreachable("Unexpected number of operands for MRMnr");
787 }
788 if (HasVEX_4VPrefix)
789 HANDLE_OPERAND(vvvvRegister)
791 if (HasEVEX_K)
792 HANDLE_OPERAND(writemaskRegister)
793 HANDLE_OPTIONAL(rmRegister)
794 HANDLE_OPTIONAL(relocation)
795 HANDLE_OPTIONAL(immediate)
796 break;
797 case X86Local::MRM0m:
798 case X86Local::MRM1m:
799 case X86Local::MRM2m:
800 case X86Local::MRM3m:
801 case X86Local::MRM4m:
802 case X86Local::MRM5m:
803 case X86Local::MRM6m:
804 case X86Local::MRM7m:
805 {
806 // Operand 1 is a memory operand (possibly SIB-extended)
807 // Operand 2 (optional) is an immediate or relocation.
808 unsigned kOp = (HasEVEX_K) ? 1:0;
809 unsigned Op4v = (HasVEX_4VPrefix) ? 1:0;
810 if (numPhysicalOperands < 1 + kOp + Op4v ||
811 numPhysicalOperands > 2 + kOp + Op4v)
812 llvm_unreachable("Unexpected number of operands for MRMnm");
813 }
814 if (HasVEX_4VPrefix)
815 HANDLE_OPERAND(vvvvRegister)
816 if (HasEVEX_K)
817 HANDLE_OPERAND(writemaskRegister)
818 HANDLE_OPERAND(memory)
819 HANDLE_OPTIONAL(relocation)
820 break;
821 case X86Local::RawFrmImm8:
822 // operand 1 is a 16-bit immediate
823 // operand 2 is an 8-bit immediate
824 assert(numPhysicalOperands == 2 &&
825 "Unexpected number of operands for X86Local::RawFrmImm8");
826 HANDLE_OPERAND(immediate)
827 HANDLE_OPERAND(immediate)
828 break;
829 case X86Local::RawFrmImm16:
830 // operand 1 is a 16-bit immediate
831 // operand 2 is a 16-bit immediate
832 HANDLE_OPERAND(immediate)
833 HANDLE_OPERAND(immediate)
834 break;
835 case X86Local::MRM_F8:
836 if (Opcode == 0xc6) {
837 assert(numPhysicalOperands == 1 &&
838 "Unexpected number of operands for X86Local::MRM_F8");
839 HANDLE_OPERAND(immediate)
840 } else if (Opcode == 0xc7) {
841 assert(numPhysicalOperands == 1 &&
842 "Unexpected number of operands for X86Local::MRM_F8");
843 HANDLE_OPERAND(relocation)
844 }
845 break;
846 case X86Local::MRMInitReg:
847 // Ignored.
848 break;
849 }
851 #undef HANDLE_OPERAND
852 #undef HANDLE_OPTIONAL
853 }
855 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
856 // Special cases where the LLVM tables are not complete
858 #define MAP(from, to) \
859 case X86Local::MRM_##from: \
860 filter = new ExactFilter(0x##from); \
861 break;
863 OpcodeType opcodeType = (OpcodeType)-1;
865 ModRMFilter* filter = NULL;
866 uint8_t opcodeToSet = 0;
868 switch (Prefix) {
869 default: llvm_unreachable("Invalid prefix!");
870 // Extended two-byte opcodes can start with 66 0f, f2 0f, f3 0f, or 0f
871 case X86Local::PD:
872 case X86Local::XD:
873 case X86Local::XS:
874 case X86Local::TB:
875 opcodeType = TWOBYTE;
877 switch (Opcode) {
878 default:
879 if (needsModRMForDecode(Form))
880 filter = new ModFilter(isRegFormat(Form));
881 else
882 filter = new DumbFilter();
883 break;
884 #define EXTENSION_TABLE(n) case 0x##n:
885 TWO_BYTE_EXTENSION_TABLES
886 #undef EXTENSION_TABLE
887 switch (Form) {
888 default:
889 llvm_unreachable("Unhandled two-byte extended opcode");
890 case X86Local::MRM0r:
891 case X86Local::MRM1r:
892 case X86Local::MRM2r:
893 case X86Local::MRM3r:
894 case X86Local::MRM4r:
895 case X86Local::MRM5r:
896 case X86Local::MRM6r:
897 case X86Local::MRM7r:
898 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
899 break;
900 case X86Local::MRM0m:
901 case X86Local::MRM1m:
902 case X86Local::MRM2m:
903 case X86Local::MRM3m:
904 case X86Local::MRM4m:
905 case X86Local::MRM5m:
906 case X86Local::MRM6m:
907 case X86Local::MRM7m:
908 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
909 break;
910 MRM_MAPPING
911 } // switch (Form)
912 break;
913 } // switch (Opcode)
914 opcodeToSet = Opcode;
915 break;
916 case X86Local::T8:
917 case X86Local::T8PD:
918 case X86Local::T8XD:
919 case X86Local::T8XS:
920 opcodeType = THREEBYTE_38;
921 switch (Opcode) {
922 default:
923 if (needsModRMForDecode(Form))
924 filter = new ModFilter(isRegFormat(Form));
925 else
926 filter = new DumbFilter();
927 break;
928 #define EXTENSION_TABLE(n) case 0x##n:
929 THREE_BYTE_38_EXTENSION_TABLES
930 #undef EXTENSION_TABLE
931 switch (Form) {
932 default:
933 llvm_unreachable("Unhandled two-byte extended opcode");
934 case X86Local::MRM0r:
935 case X86Local::MRM1r:
936 case X86Local::MRM2r:
937 case X86Local::MRM3r:
938 case X86Local::MRM4r:
939 case X86Local::MRM5r:
940 case X86Local::MRM6r:
941 case X86Local::MRM7r:
942 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
943 break;
944 case X86Local::MRM0m:
945 case X86Local::MRM1m:
946 case X86Local::MRM2m:
947 case X86Local::MRM3m:
948 case X86Local::MRM4m:
949 case X86Local::MRM5m:
950 case X86Local::MRM6m:
951 case X86Local::MRM7m:
952 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
953 break;
954 MRM_MAPPING
955 } // switch (Form)
956 break;
957 } // switch (Opcode)
958 opcodeToSet = Opcode;
959 break;
960 case X86Local::P_TA:
961 case X86Local::TAPD:
962 case X86Local::TAXD:
963 opcodeType = THREEBYTE_3A;
964 if (needsModRMForDecode(Form))
965 filter = new ModFilter(isRegFormat(Form));
966 else
967 filter = new DumbFilter();
968 opcodeToSet = Opcode;
969 break;
970 case X86Local::A6:
971 opcodeType = THREEBYTE_A6;
972 if (needsModRMForDecode(Form))
973 filter = new ModFilter(isRegFormat(Form));
974 else
975 filter = new DumbFilter();
976 opcodeToSet = Opcode;
977 break;
978 case X86Local::A7:
979 opcodeType = THREEBYTE_A7;
980 if (needsModRMForDecode(Form))
981 filter = new ModFilter(isRegFormat(Form));
982 else
983 filter = new DumbFilter();
984 opcodeToSet = Opcode;
985 break;
986 case X86Local::XOP8:
987 opcodeType = XOP8_MAP;
988 if (needsModRMForDecode(Form))
989 filter = new ModFilter(isRegFormat(Form));
990 else
991 filter = new DumbFilter();
992 opcodeToSet = Opcode;
993 break;
994 case X86Local::XOP9:
995 opcodeType = XOP9_MAP;
996 switch (Opcode) {
997 default:
998 if (needsModRMForDecode(Form))
999 filter = new ModFilter(isRegFormat(Form));
1000 else
1001 filter = new DumbFilter();
1002 break;
1003 #define EXTENSION_TABLE(n) case 0x##n:
1004 XOP9_MAP_EXTENSION_TABLES
1005 #undef EXTENSION_TABLE
1006 switch (Form) {
1007 default:
1008 llvm_unreachable("Unhandled XOP9 extended opcode");
1009 case X86Local::MRM0r:
1010 case X86Local::MRM1r:
1011 case X86Local::MRM2r:
1012 case X86Local::MRM3r:
1013 case X86Local::MRM4r:
1014 case X86Local::MRM5r:
1015 case X86Local::MRM6r:
1016 case X86Local::MRM7r:
1017 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1018 break;
1019 case X86Local::MRM0m:
1020 case X86Local::MRM1m:
1021 case X86Local::MRM2m:
1022 case X86Local::MRM3m:
1023 case X86Local::MRM4m:
1024 case X86Local::MRM5m:
1025 case X86Local::MRM6m:
1026 case X86Local::MRM7m:
1027 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1028 break;
1029 MRM_MAPPING
1030 } // switch (Form)
1031 break;
1032 } // switch (Opcode)
1033 opcodeToSet = Opcode;
1034 break;
1035 case X86Local::XOPA:
1036 opcodeType = XOPA_MAP;
1037 if (needsModRMForDecode(Form))
1038 filter = new ModFilter(isRegFormat(Form));
1039 else
1040 filter = new DumbFilter();
1041 opcodeToSet = Opcode;
1042 break;
1043 case X86Local::D8:
1044 case X86Local::D9:
1045 case X86Local::DA:
1046 case X86Local::DB:
1047 case X86Local::DC:
1048 case X86Local::DD:
1049 case X86Local::DE:
1050 case X86Local::DF:
1051 assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
1052 assert(Form == X86Local::RawFrm);
1053 opcodeType = ONEBYTE;
1054 filter = new ExactFilter(Opcode);
1055 opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
1056 break;
1057 case X86Local::REP:
1058 case 0:
1059 opcodeType = ONEBYTE;
1060 switch (Opcode) {
1061 #define EXTENSION_TABLE(n) case 0x##n:
1062 ONE_BYTE_EXTENSION_TABLES
1063 #undef EXTENSION_TABLE
1064 switch (Form) {
1065 default:
1066 llvm_unreachable("Fell through the cracks of a single-byte "
1067 "extended opcode");
1068 case X86Local::MRM0r:
1069 case X86Local::MRM1r:
1070 case X86Local::MRM2r:
1071 case X86Local::MRM3r:
1072 case X86Local::MRM4r:
1073 case X86Local::MRM5r:
1074 case X86Local::MRM6r:
1075 case X86Local::MRM7r:
1076 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1077 break;
1078 case X86Local::MRM0m:
1079 case X86Local::MRM1m:
1080 case X86Local::MRM2m:
1081 case X86Local::MRM3m:
1082 case X86Local::MRM4m:
1083 case X86Local::MRM5m:
1084 case X86Local::MRM6m:
1085 case X86Local::MRM7m:
1086 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1087 break;
1088 MRM_MAPPING
1089 } // switch (Form)
1090 break;
1091 case 0xd8:
1092 case 0xd9:
1093 case 0xda:
1094 case 0xdb:
1095 case 0xdc:
1096 case 0xdd:
1097 case 0xde:
1098 case 0xdf:
1099 switch (Form) {
1100 default:
1101 llvm_unreachable("Unhandled escape opcode form");
1102 case X86Local::MRM0r:
1103 case X86Local::MRM1r:
1104 case X86Local::MRM2r:
1105 case X86Local::MRM3r:
1106 case X86Local::MRM4r:
1107 case X86Local::MRM5r:
1108 case X86Local::MRM6r:
1109 case X86Local::MRM7r:
1110 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1111 break;
1112 case X86Local::MRM0m:
1113 case X86Local::MRM1m:
1114 case X86Local::MRM2m:
1115 case X86Local::MRM3m:
1116 case X86Local::MRM4m:
1117 case X86Local::MRM5m:
1118 case X86Local::MRM6m:
1119 case X86Local::MRM7m:
1120 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1121 break;
1122 } // switch (Form)
1123 break;
1124 default:
1125 if (needsModRMForDecode(Form))
1126 filter = new ModFilter(isRegFormat(Form));
1127 else
1128 filter = new DumbFilter();
1129 break;
1130 } // switch (Opcode)
1131 opcodeToSet = Opcode;
1132 } // switch (Prefix)
1134 assert(opcodeType != (OpcodeType)-1 &&
1135 "Opcode type not set");
1136 assert(filter && "Filter not set");
1138 if (Form == X86Local::AddRegFrm) {
1139 assert(((opcodeToSet & 7) == 0) &&
1140 "ADDREG_FRM opcode not aligned");
1142 uint8_t currentOpcode;
1144 for (currentOpcode = opcodeToSet;
1145 currentOpcode < opcodeToSet + 8;
1146 ++currentOpcode)
1147 tables.setTableFields(opcodeType,
1148 insnContext(),
1149 currentOpcode,
1150 *filter,
1151 UID, Is32Bit, IgnoresVEX_L);
1152 } else {
1153 tables.setTableFields(opcodeType,
1154 insnContext(),
1155 opcodeToSet,
1156 *filter,
1157 UID, Is32Bit, IgnoresVEX_L);
1158 }
1160 delete filter;
1162 #undef MAP
1163 }
1165 #define TYPE(str, type) if (s == str) return type;
1166 OperandType RecognizableInstr::typeFromString(const std::string &s,
1167 bool isSSE,
1168 bool hasREX_WPrefix,
1169 bool hasOpSizePrefix) {
1170 if (isSSE) {
1171 // For SSE instructions, we ignore the OpSize prefix and force operand
1172 // sizes.
1173 TYPE("GR16", TYPE_R16)
1174 TYPE("GR32", TYPE_R32)
1175 TYPE("GR64", TYPE_R64)
1176 }
1177 if(hasREX_WPrefix) {
1178 // For instructions with a REX_W prefix, a declared 32-bit register encoding
1179 // is special.
1180 TYPE("GR32", TYPE_R32)
1181 }
1182 if(!hasOpSizePrefix) {
1183 // For instructions without an OpSize prefix, a declared 16-bit register or
1184 // immediate encoding is special.
1185 TYPE("GR16", TYPE_R16)
1186 TYPE("i16imm", TYPE_IMM16)
1187 }
1188 TYPE("i16mem", TYPE_Mv)
1189 TYPE("i16imm", TYPE_IMMv)
1190 TYPE("i16i8imm", TYPE_IMMv)
1191 TYPE("GR16", TYPE_Rv)
1192 TYPE("i32mem", TYPE_Mv)
1193 TYPE("i32imm", TYPE_IMMv)
1194 TYPE("i32i8imm", TYPE_IMM32)
1195 TYPE("u32u8imm", TYPE_IMM32)
1196 TYPE("GR32", TYPE_Rv)
1197 TYPE("GR32orGR64", TYPE_R32)
1198 TYPE("i64mem", TYPE_Mv)
1199 TYPE("i64i32imm", TYPE_IMM64)
1200 TYPE("i64i8imm", TYPE_IMM64)
1201 TYPE("GR64", TYPE_R64)
1202 TYPE("i8mem", TYPE_M8)
1203 TYPE("i8imm", TYPE_IMM8)
1204 TYPE("GR8", TYPE_R8)
1205 TYPE("VR128", TYPE_XMM128)
1206 TYPE("VR128X", TYPE_XMM128)
1207 TYPE("f128mem", TYPE_M128)
1208 TYPE("f256mem", TYPE_M256)
1209 TYPE("f512mem", TYPE_M512)
1210 TYPE("FR64", TYPE_XMM64)
1211 TYPE("FR64X", TYPE_XMM64)
1212 TYPE("f64mem", TYPE_M64FP)
1213 TYPE("sdmem", TYPE_M64FP)
1214 TYPE("FR32", TYPE_XMM32)
1215 TYPE("FR32X", TYPE_XMM32)
1216 TYPE("f32mem", TYPE_M32FP)
1217 TYPE("ssmem", TYPE_M32FP)
1218 TYPE("RST", TYPE_ST)
1219 TYPE("i128mem", TYPE_M128)
1220 TYPE("i256mem", TYPE_M256)
1221 TYPE("i512mem", TYPE_M512)
1222 TYPE("i64i32imm_pcrel", TYPE_REL64)
1223 TYPE("i16imm_pcrel", TYPE_REL16)
1224 TYPE("i32imm_pcrel", TYPE_REL32)
1225 TYPE("SSECC", TYPE_IMM3)
1226 TYPE("AVXCC", TYPE_IMM5)
1227 TYPE("AVX512RC", TYPE_IMM32)
1228 TYPE("brtarget", TYPE_RELv)
1229 TYPE("uncondbrtarget", TYPE_RELv)
1230 TYPE("brtarget8", TYPE_REL8)
1231 TYPE("f80mem", TYPE_M80FP)
1232 TYPE("lea32mem", TYPE_LEA)
1233 TYPE("lea64_32mem", TYPE_LEA)
1234 TYPE("lea64mem", TYPE_LEA)
1235 TYPE("VR64", TYPE_MM64)
1236 TYPE("i64imm", TYPE_IMMv)
1237 TYPE("opaque32mem", TYPE_M1616)
1238 TYPE("opaque48mem", TYPE_M1632)
1239 TYPE("opaque80mem", TYPE_M1664)
1240 TYPE("opaque512mem", TYPE_M512)
1241 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
1242 TYPE("DEBUG_REG", TYPE_DEBUGREG)
1243 TYPE("CONTROL_REG", TYPE_CONTROLREG)
1244 TYPE("offset8", TYPE_MOFFS8)
1245 TYPE("offset16", TYPE_MOFFS16)
1246 TYPE("offset32", TYPE_MOFFS32)
1247 TYPE("offset64", TYPE_MOFFS64)
1248 TYPE("VR256", TYPE_XMM256)
1249 TYPE("VR256X", TYPE_XMM256)
1250 TYPE("VR512", TYPE_XMM512)
1251 TYPE("VK1", TYPE_VK1)
1252 TYPE("VK1WM", TYPE_VK1)
1253 TYPE("VK8", TYPE_VK8)
1254 TYPE("VK8WM", TYPE_VK8)
1255 TYPE("VK16", TYPE_VK16)
1256 TYPE("VK16WM", TYPE_VK16)
1257 TYPE("GR16_NOAX", TYPE_Rv)
1258 TYPE("GR32_NOAX", TYPE_Rv)
1259 TYPE("GR64_NOAX", TYPE_R64)
1260 TYPE("vx32mem", TYPE_M32)
1261 TYPE("vy32mem", TYPE_M32)
1262 TYPE("vz32mem", TYPE_M32)
1263 TYPE("vx64mem", TYPE_M64)
1264 TYPE("vy64mem", TYPE_M64)
1265 TYPE("vy64xmem", TYPE_M64)
1266 TYPE("vz64mem", TYPE_M64)
1267 errs() << "Unhandled type string " << s << "\n";
1268 llvm_unreachable("Unhandled type string");
1269 }
1270 #undef TYPE
1272 #define ENCODING(str, encoding) if (s == str) return encoding;
1273 OperandEncoding RecognizableInstr::immediateEncodingFromString
1274 (const std::string &s,
1275 bool hasOpSizePrefix) {
1276 if(!hasOpSizePrefix) {
1277 // For instructions without an OpSize prefix, a declared 16-bit register or
1278 // immediate encoding is special.
1279 ENCODING("i16imm", ENCODING_IW)
1280 }
1281 ENCODING("i32i8imm", ENCODING_IB)
1282 ENCODING("u32u8imm", ENCODING_IB)
1283 ENCODING("SSECC", ENCODING_IB)
1284 ENCODING("AVXCC", ENCODING_IB)
1285 ENCODING("AVX512RC", ENCODING_IB)
1286 ENCODING("i16imm", ENCODING_Iv)
1287 ENCODING("i16i8imm", ENCODING_IB)
1288 ENCODING("i32imm", ENCODING_Iv)
1289 ENCODING("i64i32imm", ENCODING_ID)
1290 ENCODING("i64i8imm", ENCODING_IB)
1291 ENCODING("i8imm", ENCODING_IB)
1292 // This is not a typo. Instructions like BLENDVPD put
1293 // register IDs in 8-bit immediates nowadays.
1294 ENCODING("FR32", ENCODING_IB)
1295 ENCODING("FR64", ENCODING_IB)
1296 ENCODING("VR128", ENCODING_IB)
1297 ENCODING("VR256", ENCODING_IB)
1298 ENCODING("FR32X", ENCODING_IB)
1299 ENCODING("FR64X", ENCODING_IB)
1300 ENCODING("VR128X", ENCODING_IB)
1301 ENCODING("VR256X", ENCODING_IB)
1302 ENCODING("VR512", ENCODING_IB)
1303 errs() << "Unhandled immediate encoding " << s << "\n";
1304 llvm_unreachable("Unhandled immediate encoding");
1305 }
1307 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1308 (const std::string &s,
1309 bool hasOpSizePrefix) {
1310 ENCODING("RST", ENCODING_FP)
1311 ENCODING("GR16", ENCODING_RM)
1312 ENCODING("GR32", ENCODING_RM)
1313 ENCODING("GR32orGR64", ENCODING_RM)
1314 ENCODING("GR64", ENCODING_RM)
1315 ENCODING("GR8", ENCODING_RM)
1316 ENCODING("VR128", ENCODING_RM)
1317 ENCODING("VR128X", ENCODING_RM)
1318 ENCODING("FR64", ENCODING_RM)
1319 ENCODING("FR32", ENCODING_RM)
1320 ENCODING("FR64X", ENCODING_RM)
1321 ENCODING("FR32X", ENCODING_RM)
1322 ENCODING("VR64", ENCODING_RM)
1323 ENCODING("VR256", ENCODING_RM)
1324 ENCODING("VR256X", ENCODING_RM)
1325 ENCODING("VR512", ENCODING_RM)
1326 ENCODING("VK1", ENCODING_RM)
1327 ENCODING("VK8", ENCODING_RM)
1328 ENCODING("VK16", ENCODING_RM)
1329 errs() << "Unhandled R/M register encoding " << s << "\n";
1330 llvm_unreachable("Unhandled R/M register encoding");
1331 }
1333 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1334 (const std::string &s,
1335 bool hasOpSizePrefix) {
1336 ENCODING("GR16", ENCODING_REG)
1337 ENCODING("GR32", ENCODING_REG)
1338 ENCODING("GR32orGR64", ENCODING_REG)
1339 ENCODING("GR64", ENCODING_REG)
1340 ENCODING("GR8", ENCODING_REG)
1341 ENCODING("VR128", ENCODING_REG)
1342 ENCODING("FR64", ENCODING_REG)
1343 ENCODING("FR32", ENCODING_REG)
1344 ENCODING("VR64", ENCODING_REG)
1345 ENCODING("SEGMENT_REG", ENCODING_REG)
1346 ENCODING("DEBUG_REG", ENCODING_REG)
1347 ENCODING("CONTROL_REG", ENCODING_REG)
1348 ENCODING("VR256", ENCODING_REG)
1349 ENCODING("VR256X", ENCODING_REG)
1350 ENCODING("VR128X", ENCODING_REG)
1351 ENCODING("FR64X", ENCODING_REG)
1352 ENCODING("FR32X", ENCODING_REG)
1353 ENCODING("VR512", ENCODING_REG)
1354 ENCODING("VK1", ENCODING_REG)
1355 ENCODING("VK8", ENCODING_REG)
1356 ENCODING("VK16", ENCODING_REG)
1357 ENCODING("VK1WM", ENCODING_REG)
1358 ENCODING("VK8WM", ENCODING_REG)
1359 ENCODING("VK16WM", ENCODING_REG)
1360 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1361 llvm_unreachable("Unhandled reg/opcode register encoding");
1362 }
1364 OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1365 (const std::string &s,
1366 bool hasOpSizePrefix) {
1367 ENCODING("GR32", ENCODING_VVVV)
1368 ENCODING("GR64", ENCODING_VVVV)
1369 ENCODING("FR32", ENCODING_VVVV)
1370 ENCODING("FR64", ENCODING_VVVV)
1371 ENCODING("VR128", ENCODING_VVVV)
1372 ENCODING("VR256", ENCODING_VVVV)
1373 ENCODING("FR32X", ENCODING_VVVV)
1374 ENCODING("FR64X", ENCODING_VVVV)
1375 ENCODING("VR128X", ENCODING_VVVV)
1376 ENCODING("VR256X", ENCODING_VVVV)
1377 ENCODING("VR512", ENCODING_VVVV)
1378 ENCODING("VK1", ENCODING_VVVV)
1379 ENCODING("VK8", ENCODING_VVVV)
1380 ENCODING("VK16", ENCODING_VVVV)
1381 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1382 llvm_unreachable("Unhandled VEX.vvvv register encoding");
1383 }
1385 OperandEncoding RecognizableInstr::writemaskRegisterEncodingFromString
1386 (const std::string &s,
1387 bool hasOpSizePrefix) {
1388 ENCODING("VK1WM", ENCODING_WRITEMASK)
1389 ENCODING("VK8WM", ENCODING_WRITEMASK)
1390 ENCODING("VK16WM", ENCODING_WRITEMASK)
1391 errs() << "Unhandled mask register encoding " << s << "\n";
1392 llvm_unreachable("Unhandled mask register encoding");
1393 }
1395 OperandEncoding RecognizableInstr::memoryEncodingFromString
1396 (const std::string &s,
1397 bool hasOpSizePrefix) {
1398 ENCODING("i16mem", ENCODING_RM)
1399 ENCODING("i32mem", ENCODING_RM)
1400 ENCODING("i64mem", ENCODING_RM)
1401 ENCODING("i8mem", ENCODING_RM)
1402 ENCODING("ssmem", ENCODING_RM)
1403 ENCODING("sdmem", ENCODING_RM)
1404 ENCODING("f128mem", ENCODING_RM)
1405 ENCODING("f256mem", ENCODING_RM)
1406 ENCODING("f512mem", ENCODING_RM)
1407 ENCODING("f64mem", ENCODING_RM)
1408 ENCODING("f32mem", ENCODING_RM)
1409 ENCODING("i128mem", ENCODING_RM)
1410 ENCODING("i256mem", ENCODING_RM)
1411 ENCODING("i512mem", ENCODING_RM)
1412 ENCODING("f80mem", ENCODING_RM)
1413 ENCODING("lea32mem", ENCODING_RM)
1414 ENCODING("lea64_32mem", ENCODING_RM)
1415 ENCODING("lea64mem", ENCODING_RM)
1416 ENCODING("opaque32mem", ENCODING_RM)
1417 ENCODING("opaque48mem", ENCODING_RM)
1418 ENCODING("opaque80mem", ENCODING_RM)
1419 ENCODING("opaque512mem", ENCODING_RM)
1420 ENCODING("vx32mem", ENCODING_RM)
1421 ENCODING("vy32mem", ENCODING_RM)
1422 ENCODING("vz32mem", ENCODING_RM)
1423 ENCODING("vx64mem", ENCODING_RM)
1424 ENCODING("vy64mem", ENCODING_RM)
1425 ENCODING("vy64xmem", ENCODING_RM)
1426 ENCODING("vz64mem", ENCODING_RM)
1427 errs() << "Unhandled memory encoding " << s << "\n";
1428 llvm_unreachable("Unhandled memory encoding");
1429 }
1431 OperandEncoding RecognizableInstr::relocationEncodingFromString
1432 (const std::string &s,
1433 bool hasOpSizePrefix) {
1434 if(!hasOpSizePrefix) {
1435 // For instructions without an OpSize prefix, a declared 16-bit register or
1436 // immediate encoding is special.
1437 ENCODING("i16imm", ENCODING_IW)
1438 }
1439 ENCODING("i16imm", ENCODING_Iv)
1440 ENCODING("i16i8imm", ENCODING_IB)
1441 ENCODING("i32imm", ENCODING_Iv)
1442 ENCODING("i32i8imm", ENCODING_IB)
1443 ENCODING("i64i32imm", ENCODING_ID)
1444 ENCODING("i64i8imm", ENCODING_IB)
1445 ENCODING("i8imm", ENCODING_IB)
1446 ENCODING("i64i32imm_pcrel", ENCODING_ID)
1447 ENCODING("i16imm_pcrel", ENCODING_IW)
1448 ENCODING("i32imm_pcrel", ENCODING_ID)
1449 ENCODING("brtarget", ENCODING_Iv)
1450 ENCODING("brtarget8", ENCODING_IB)
1451 ENCODING("i64imm", ENCODING_IO)
1452 ENCODING("offset8", ENCODING_Ia)
1453 ENCODING("offset16", ENCODING_Ia)
1454 ENCODING("offset32", ENCODING_Ia)
1455 ENCODING("offset64", ENCODING_Ia)
1456 errs() << "Unhandled relocation encoding " << s << "\n";
1457 llvm_unreachable("Unhandled relocation encoding");
1458 }
1460 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1461 (const std::string &s,
1462 bool hasOpSizePrefix) {
1463 ENCODING("GR32", ENCODING_Rv)
1464 ENCODING("GR64", ENCODING_RO)
1465 ENCODING("GR16", ENCODING_Rv)
1466 ENCODING("GR8", ENCODING_RB)
1467 ENCODING("GR16_NOAX", ENCODING_Rv)
1468 ENCODING("GR32_NOAX", ENCODING_Rv)
1469 ENCODING("GR64_NOAX", ENCODING_RO)
1470 errs() << "Unhandled opcode modifier encoding " << s << "\n";
1471 llvm_unreachable("Unhandled opcode modifier encoding");
1472 }
1473 #undef ENCODING