1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
14 //
15 //===----------------------------------------------------------------------===//
17 #include "X86RecognizableInstr.h"
18 #include "X86DisassemblerShared.h"
19 #include "X86ModRMFilters.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include <string>
23 using namespace llvm;
25 #define MRM_MAPPING \
26 MAP(C1, 33) \
27 MAP(C2, 34) \
28 MAP(C3, 35) \
29 MAP(C4, 36) \
30 MAP(C8, 37) \
31 MAP(C9, 38) \
32 MAP(CA, 39) \
33 MAP(CB, 40) \
34 MAP(E8, 41) \
35 MAP(F0, 42) \
36 MAP(F8, 45) \
37 MAP(F9, 46) \
38 MAP(D0, 47) \
39 MAP(D1, 48) \
40 MAP(D4, 49) \
41 MAP(D5, 50) \
42 MAP(D6, 51) \
43 MAP(D8, 52) \
44 MAP(D9, 53) \
45 MAP(DA, 54) \
46 MAP(DB, 55) \
47 MAP(DC, 56) \
48 MAP(DD, 57) \
49 MAP(DE, 58) \
50 MAP(DF, 59)
52 // A clone of X86 since we can't depend on something that is generated.
53 namespace X86Local {
54 enum {
55 Pseudo = 0,
56 RawFrm = 1,
57 AddRegFrm = 2,
58 MRMDestReg = 3,
59 MRMDestMem = 4,
60 MRMSrcReg = 5,
61 MRMSrcMem = 6,
62 RawFrmMemOffs = 7,
63 RawFrmSrc = 8,
64 RawFrmDst = 9,
65 RawFrmDstSrc = 10,
66 MRMXr = 14, MRMXm = 15,
67 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
68 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
69 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
70 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
71 RawFrmImm8 = 43,
72 RawFrmImm16 = 44,
73 #define MAP(from, to) MRM_##from = to,
74 MRM_MAPPING
75 #undef MAP
76 lastMRM
77 };
79 enum {
80 OB = 0, TB = 1, T8 = 2, TA = 3, XOP8 = 4, XOP9 = 5, XOPA = 6,
81 D8 = 7, D9 = 8, DA = 9, DB = 10,
82 DC = 11, DD = 12, DE = 13, DF = 14,
83 A6 = 15, A7 = 16
84 };
86 enum {
87 PD = 1, XS = 2, XD = 3
88 };
90 enum {
91 VEX = 1, XOP = 2, EVEX = 3
92 };
94 enum {
95 OpSize16 = 1, OpSize32 = 2
96 };
97 }
99 using namespace X86Disassembler;
101 /// isRegFormat - Indicates whether a particular form requires the Mod field of
102 /// the ModR/M byte to be 0b11.
103 ///
104 /// @param form - The form of the instruction.
105 /// @return - true if the form implies that Mod must be 0b11, false
106 /// otherwise.
107 static bool isRegFormat(uint8_t form) {
108 return (form == X86Local::MRMDestReg ||
109 form == X86Local::MRMSrcReg ||
110 form == X86Local::MRMXr ||
111 (form >= X86Local::MRM0r && form <= X86Local::MRM7r));
112 }
114 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
115 /// Useful for switch statements and the like.
116 ///
117 /// @param init - A reference to the BitsInit to be decoded.
118 /// @return - The field, with the first bit in the BitsInit as the lowest
119 /// order bit.
120 static uint8_t byteFromBitsInit(BitsInit &init) {
121 int width = init.getNumBits();
123 assert(width <= 8 && "Field is too large for uint8_t!");
125 int index;
126 uint8_t mask = 0x01;
128 uint8_t ret = 0;
130 for (index = 0; index < width; index++) {
131 if (static_cast<BitInit*>(init.getBit(index))->getValue())
132 ret |= mask;
134 mask <<= 1;
135 }
137 return ret;
138 }
140 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
141 /// name of the field.
142 ///
143 /// @param rec - The record from which to extract the value.
144 /// @param name - The name of the field in the record.
145 /// @return - The field, as translated by byteFromBitsInit().
146 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
147 BitsInit* bits = rec->getValueAsBitsInit(name);
148 return byteFromBitsInit(*bits);
149 }
151 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
152 const CodeGenInstruction &insn,
153 InstrUID uid) {
154 UID = uid;
156 Rec = insn.TheDef;
157 Name = Rec->getName();
158 Spec = &tables.specForUID(UID);
160 if (!Rec->isSubClassOf("X86Inst")) {
161 ShouldBeEmitted = false;
162 return;
163 }
165 OpPrefix = byteFromRec(Rec->getValueAsDef("OpPrefix"), "Value");
166 OpMap = byteFromRec(Rec->getValueAsDef("OpMap"), "Value");
167 Opcode = byteFromRec(Rec, "Opcode");
168 Form = byteFromRec(Rec, "FormBits");
169 Encoding = byteFromRec(Rec->getValueAsDef("OpEnc"), "Value");
171 OpSize = byteFromRec(Rec->getValueAsDef("OpSize"), "Value");
172 HasAdSizePrefix = Rec->getValueAsBit("hasAdSizePrefix");
173 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
174 HasVEX_4V = Rec->getValueAsBit("hasVEX_4V");
175 HasVEX_4VOp3 = Rec->getValueAsBit("hasVEX_4VOp3");
176 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix");
177 HasMemOp4Prefix = Rec->getValueAsBit("hasMemOp4Prefix");
178 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
179 HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2");
180 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K");
181 HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z");
182 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B");
183 HasLockPrefix = Rec->getValueAsBit("hasLockPrefix");
184 HasREPPrefix = Rec->getValueAsBit("hasREPPrefix");
185 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
186 ForceDisassemble = Rec->getValueAsBit("ForceDisassemble");
188 Name = Rec->getName();
189 AsmString = Rec->getValueAsString("AsmString");
191 Operands = &insn.Operands.OperandList;
193 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L");
195 // Check for 64-bit inst which does not require REX
196 Is32Bit = false;
197 Is64Bit = false;
198 // FIXME: Is there some better way to check for In64BitMode?
199 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
200 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
201 if (Predicates[i]->getName().find("Not64Bit") != Name.npos ||
202 Predicates[i]->getName().find("In32Bit") != Name.npos) {
203 Is32Bit = true;
204 break;
205 }
206 if (Predicates[i]->getName().find("In64Bit") != Name.npos) {
207 Is64Bit = true;
208 break;
209 }
210 }
212 ShouldBeEmitted = true;
213 }
215 void RecognizableInstr::processInstr(DisassemblerTables &tables,
216 const CodeGenInstruction &insn,
217 InstrUID uid)
218 {
219 // Ignore "asm parser only" instructions.
220 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
221 return;
223 RecognizableInstr recogInstr(tables, insn, uid);
225 recogInstr.emitInstructionSpecifier();
227 if (recogInstr.shouldBeEmitted())
228 recogInstr.emitDecodePath(tables);
229 }
231 #define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \
232 (HasEVEX_K && HasEVEX_B ? n##_K_B : \
233 (HasEVEX_KZ ? n##_KZ : \
234 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n)))))
236 InstructionContext RecognizableInstr::insnContext() const {
237 InstructionContext insnContext;
239 if (Encoding == X86Local::EVEX) {
240 if (HasVEX_LPrefix && HasEVEX_L2Prefix) {
241 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n";
242 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled");
243 }
244 // VEX_L & VEX_W
245 if (HasVEX_LPrefix && HasVEX_WPrefix) {
246 if (OpPrefix == X86Local::PD)
247 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE);
248 else if (OpPrefix == X86Local::XS)
249 insnContext = EVEX_KB(IC_EVEX_L_W_XS);
250 else if (OpPrefix == X86Local::XD)
251 insnContext = EVEX_KB(IC_EVEX_L_W_XD);
252 else
253 insnContext = EVEX_KB(IC_EVEX_L_W);
254 } else if (HasVEX_LPrefix) {
255 // VEX_L
256 if (OpPrefix == X86Local::PD)
257 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE);
258 else if (OpPrefix == X86Local::XS)
259 insnContext = EVEX_KB(IC_EVEX_L_XS);
260 else if (OpPrefix == X86Local::XD)
261 insnContext = EVEX_KB(IC_EVEX_L_XD);
262 else
263 insnContext = EVEX_KB(IC_EVEX_L);
264 }
265 else if (HasEVEX_L2Prefix && HasVEX_WPrefix) {
266 // EVEX_L2 & VEX_W
267 if (OpPrefix == X86Local::PD)
268 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE);
269 else if (OpPrefix == X86Local::XS)
270 insnContext = EVEX_KB(IC_EVEX_L2_W_XS);
271 else if (OpPrefix == X86Local::XD)
272 insnContext = EVEX_KB(IC_EVEX_L2_W_XD);
273 else
274 insnContext = EVEX_KB(IC_EVEX_L2_W);
275 } else if (HasEVEX_L2Prefix) {
276 // EVEX_L2
277 if (OpPrefix == X86Local::PD)
278 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE);
279 else if (OpPrefix == X86Local::XD)
280 insnContext = EVEX_KB(IC_EVEX_L2_XD);
281 else if (OpPrefix == X86Local::XS)
282 insnContext = EVEX_KB(IC_EVEX_L2_XS);
283 else
284 insnContext = EVEX_KB(IC_EVEX_L2);
285 }
286 else if (HasVEX_WPrefix) {
287 // VEX_W
288 if (OpPrefix == X86Local::PD)
289 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE);
290 else if (OpPrefix == X86Local::XS)
291 insnContext = EVEX_KB(IC_EVEX_W_XS);
292 else if (OpPrefix == X86Local::XD)
293 insnContext = EVEX_KB(IC_EVEX_W_XD);
294 else
295 insnContext = EVEX_KB(IC_EVEX_W);
296 }
297 // No L, no W
298 else if (OpPrefix == X86Local::PD)
299 insnContext = EVEX_KB(IC_EVEX_OPSIZE);
300 else if (OpPrefix == X86Local::XD)
301 insnContext = EVEX_KB(IC_EVEX_XD);
302 else if (OpPrefix == X86Local::XS)
303 insnContext = EVEX_KB(IC_EVEX_XS);
304 else
305 insnContext = EVEX_KB(IC_EVEX);
306 /// eof EVEX
307 } else if (Encoding == X86Local::VEX || Encoding == X86Local::XOP) {
308 if (HasVEX_LPrefix && HasVEX_WPrefix) {
309 if (OpPrefix == X86Local::PD)
310 insnContext = IC_VEX_L_W_OPSIZE;
311 else if (OpPrefix == X86Local::XS)
312 insnContext = IC_VEX_L_W_XS;
313 else if (OpPrefix == X86Local::XD)
314 insnContext = IC_VEX_L_W_XD;
315 else
316 insnContext = IC_VEX_L_W;
317 } else if (OpPrefix == X86Local::PD && HasVEX_LPrefix)
318 insnContext = IC_VEX_L_OPSIZE;
319 else if (OpPrefix == X86Local::PD && HasVEX_WPrefix)
320 insnContext = IC_VEX_W_OPSIZE;
321 else if (OpPrefix == X86Local::PD)
322 insnContext = IC_VEX_OPSIZE;
323 else if (HasVEX_LPrefix && OpPrefix == X86Local::XS)
324 insnContext = IC_VEX_L_XS;
325 else if (HasVEX_LPrefix && OpPrefix == X86Local::XD)
326 insnContext = IC_VEX_L_XD;
327 else if (HasVEX_WPrefix && OpPrefix == X86Local::XS)
328 insnContext = IC_VEX_W_XS;
329 else if (HasVEX_WPrefix && OpPrefix == X86Local::XD)
330 insnContext = IC_VEX_W_XD;
331 else if (HasVEX_WPrefix)
332 insnContext = IC_VEX_W;
333 else if (HasVEX_LPrefix)
334 insnContext = IC_VEX_L;
335 else if (OpPrefix == X86Local::XD)
336 insnContext = IC_VEX_XD;
337 else if (OpPrefix == X86Local::XS)
338 insnContext = IC_VEX_XS;
339 else
340 insnContext = IC_VEX;
341 } else if (Is64Bit || HasREX_WPrefix) {
342 if (HasREX_WPrefix && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD))
343 insnContext = IC_64BIT_REXW_OPSIZE;
344 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD)
345 insnContext = IC_64BIT_XD_OPSIZE;
346 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
347 insnContext = IC_64BIT_XS_OPSIZE;
348 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
349 insnContext = IC_64BIT_OPSIZE;
350 else if (HasAdSizePrefix)
351 insnContext = IC_64BIT_ADSIZE;
352 else if (HasREX_WPrefix && OpPrefix == X86Local::XS)
353 insnContext = IC_64BIT_REXW_XS;
354 else if (HasREX_WPrefix && OpPrefix == X86Local::XD)
355 insnContext = IC_64BIT_REXW_XD;
356 else if (OpPrefix == X86Local::XD)
357 insnContext = IC_64BIT_XD;
358 else if (OpPrefix == X86Local::XS)
359 insnContext = IC_64BIT_XS;
360 else if (HasREX_WPrefix)
361 insnContext = IC_64BIT_REXW;
362 else
363 insnContext = IC_64BIT;
364 } else {
365 if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD)
366 insnContext = IC_XD_OPSIZE;
367 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
368 insnContext = IC_XS_OPSIZE;
369 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
370 insnContext = IC_OPSIZE;
371 else if (HasAdSizePrefix)
372 insnContext = IC_ADSIZE;
373 else if (OpPrefix == X86Local::XD)
374 insnContext = IC_XD;
375 else if (OpPrefix == X86Local::XS || HasREPPrefix)
376 insnContext = IC_XS;
377 else
378 insnContext = IC;
379 }
381 return insnContext;
382 }
384 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
385 ///////////////////
386 // FILTER_STRONG
387 //
389 // Filter out intrinsics
391 assert(Rec->isSubClassOf("X86Inst") && "Can only filter X86 instructions");
393 if (Form == X86Local::Pseudo || (IsCodeGenOnly && !ForceDisassemble))
394 return FILTER_STRONG;
397 // Filter out artificial instructions but leave in the LOCK_PREFIX so it is
398 // printed as a separate "instruction".
401 /////////////////
402 // FILTER_WEAK
403 //
406 // Filter out instructions with a LOCK prefix;
407 // prefer forms that do not have the prefix
408 if (HasLockPrefix)
409 return FILTER_WEAK;
411 // Special cases.
413 if (Name == "VMASKMOVDQU64")
414 return FILTER_WEAK;
416 // XACQUIRE and XRELEASE reuse REPNE and REP respectively.
417 // For now, just prefer the REP versions.
418 if (Name == "XACQUIRE_PREFIX" ||
419 Name == "XRELEASE_PREFIX")
420 return FILTER_WEAK;
422 return FILTER_NORMAL;
423 }
425 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
426 unsigned &physicalOperandIndex,
427 unsigned &numPhysicalOperands,
428 const unsigned *operandMapping,
429 OperandEncoding (*encodingFromString)
430 (const std::string&,
431 uint8_t OpSize)) {
432 if (optional) {
433 if (physicalOperandIndex >= numPhysicalOperands)
434 return;
435 } else {
436 assert(physicalOperandIndex < numPhysicalOperands);
437 }
439 while (operandMapping[operandIndex] != operandIndex) {
440 Spec->operands[operandIndex].encoding = ENCODING_DUP;
441 Spec->operands[operandIndex].type =
442 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
443 ++operandIndex;
444 }
446 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
448 Spec->operands[operandIndex].encoding = encodingFromString(typeName,
449 OpSize);
450 Spec->operands[operandIndex].type = typeFromString(typeName,
451 HasREX_WPrefix, OpSize);
453 ++operandIndex;
454 ++physicalOperandIndex;
455 }
457 void RecognizableInstr::emitInstructionSpecifier() {
458 Spec->name = Name;
460 if (!ShouldBeEmitted)
461 return;
463 switch (filter()) {
464 case FILTER_WEAK:
465 Spec->filtered = true;
466 break;
467 case FILTER_STRONG:
468 ShouldBeEmitted = false;
469 return;
470 case FILTER_NORMAL:
471 break;
472 }
474 Spec->insnContext = insnContext();
476 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
478 unsigned numOperands = OperandList.size();
479 unsigned numPhysicalOperands = 0;
481 // operandMapping maps from operands in OperandList to their originals.
482 // If operandMapping[i] != i, then the entry is a duplicate.
483 unsigned operandMapping[X86_MAX_OPERANDS];
484 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
486 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
487 if (OperandList[operandIndex].Constraints.size()) {
488 const CGIOperandList::ConstraintInfo &Constraint =
489 OperandList[operandIndex].Constraints[0];
490 if (Constraint.isTied()) {
491 operandMapping[operandIndex] = operandIndex;
492 operandMapping[Constraint.getTiedOperand()] = operandIndex;
493 } else {
494 ++numPhysicalOperands;
495 operandMapping[operandIndex] = operandIndex;
496 }
497 } else {
498 ++numPhysicalOperands;
499 operandMapping[operandIndex] = operandIndex;
500 }
501 }
503 #define HANDLE_OPERAND(class) \
504 handleOperand(false, \
505 operandIndex, \
506 physicalOperandIndex, \
507 numPhysicalOperands, \
508 operandMapping, \
509 class##EncodingFromString);
511 #define HANDLE_OPTIONAL(class) \
512 handleOperand(true, \
513 operandIndex, \
514 physicalOperandIndex, \
515 numPhysicalOperands, \
516 operandMapping, \
517 class##EncodingFromString);
519 // operandIndex should always be < numOperands
520 unsigned operandIndex = 0;
521 // physicalOperandIndex should always be < numPhysicalOperands
522 unsigned physicalOperandIndex = 0;
524 switch (Form) {
525 default: llvm_unreachable("Unhandled form");
526 case X86Local::RawFrmSrc:
527 HANDLE_OPERAND(relocation);
528 return;
529 case X86Local::RawFrmDst:
530 HANDLE_OPERAND(relocation);
531 return;
532 case X86Local::RawFrmDstSrc:
533 HANDLE_OPERAND(relocation);
534 HANDLE_OPERAND(relocation);
535 return;
536 case X86Local::RawFrm:
537 // Operand 1 (optional) is an address or immediate.
538 // Operand 2 (optional) is an immediate.
539 assert(numPhysicalOperands <= 2 &&
540 "Unexpected number of operands for RawFrm");
541 HANDLE_OPTIONAL(relocation)
542 HANDLE_OPTIONAL(immediate)
543 break;
544 case X86Local::RawFrmMemOffs:
545 // Operand 1 is an address.
546 HANDLE_OPERAND(relocation);
547 break;
548 case X86Local::AddRegFrm:
549 // Operand 1 is added to the opcode.
550 // Operand 2 (optional) is an address.
551 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
552 "Unexpected number of operands for AddRegFrm");
553 HANDLE_OPERAND(opcodeModifier)
554 HANDLE_OPTIONAL(relocation)
555 break;
556 case X86Local::MRMDestReg:
557 // Operand 1 is a register operand in the R/M field.
558 // Operand 2 is a register operand in the Reg/Opcode field.
559 // - In AVX, there is a register operand in the VEX.vvvv field here -
560 // Operand 3 (optional) is an immediate.
561 if (HasVEX_4V)
562 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
563 "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
564 else
565 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
566 "Unexpected number of operands for MRMDestRegFrm");
568 HANDLE_OPERAND(rmRegister)
570 if (HasVEX_4V)
571 // FIXME: In AVX, the register below becomes the one encoded
572 // in ModRMVEX and the one above the one in the VEX.VVVV field
573 HANDLE_OPERAND(vvvvRegister)
575 HANDLE_OPERAND(roRegister)
576 HANDLE_OPTIONAL(immediate)
577 break;
578 case X86Local::MRMDestMem:
579 // Operand 1 is a memory operand (possibly SIB-extended)
580 // Operand 2 is a register operand in the Reg/Opcode field.
581 // - In AVX, there is a register operand in the VEX.vvvv field here -
582 // Operand 3 (optional) is an immediate.
583 if (HasVEX_4V)
584 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
585 "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
586 else
587 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
588 "Unexpected number of operands for MRMDestMemFrm");
589 HANDLE_OPERAND(memory)
591 if (HasEVEX_K)
592 HANDLE_OPERAND(writemaskRegister)
594 if (HasVEX_4V)
595 // FIXME: In AVX, the register below becomes the one encoded
596 // in ModRMVEX and the one above the one in the VEX.VVVV field
597 HANDLE_OPERAND(vvvvRegister)
599 HANDLE_OPERAND(roRegister)
600 HANDLE_OPTIONAL(immediate)
601 break;
602 case X86Local::MRMSrcReg:
603 // Operand 1 is a register operand in the Reg/Opcode field.
604 // Operand 2 is a register operand in the R/M field.
605 // - In AVX, there is a register operand in the VEX.vvvv field here -
606 // Operand 3 (optional) is an immediate.
607 // Operand 4 (optional) is an immediate.
609 if (HasVEX_4V || HasVEX_4VOp3)
610 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
611 "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
612 else
613 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 4 &&
614 "Unexpected number of operands for MRMSrcRegFrm");
616 HANDLE_OPERAND(roRegister)
618 if (HasEVEX_K)
619 HANDLE_OPERAND(writemaskRegister)
621 if (HasVEX_4V)
622 // FIXME: In AVX, the register below becomes the one encoded
623 // in ModRMVEX and the one above the one in the VEX.VVVV field
624 HANDLE_OPERAND(vvvvRegister)
626 if (HasMemOp4Prefix)
627 HANDLE_OPERAND(immediate)
629 HANDLE_OPERAND(rmRegister)
631 if (HasVEX_4VOp3)
632 HANDLE_OPERAND(vvvvRegister)
634 if (!HasMemOp4Prefix)
635 HANDLE_OPTIONAL(immediate)
636 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
637 HANDLE_OPTIONAL(immediate)
638 break;
639 case X86Local::MRMSrcMem:
640 // Operand 1 is a register operand in the Reg/Opcode field.
641 // Operand 2 is a memory operand (possibly SIB-extended)
642 // - In AVX, there is a register operand in the VEX.vvvv field here -
643 // Operand 3 (optional) is an immediate.
645 if (HasVEX_4V || HasVEX_4VOp3)
646 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
647 "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
648 else
649 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
650 "Unexpected number of operands for MRMSrcMemFrm");
652 HANDLE_OPERAND(roRegister)
654 if (HasEVEX_K)
655 HANDLE_OPERAND(writemaskRegister)
657 if (HasVEX_4V)
658 // FIXME: In AVX, the register below becomes the one encoded
659 // in ModRMVEX and the one above the one in the VEX.VVVV field
660 HANDLE_OPERAND(vvvvRegister)
662 if (HasMemOp4Prefix)
663 HANDLE_OPERAND(immediate)
665 HANDLE_OPERAND(memory)
667 if (HasVEX_4VOp3)
668 HANDLE_OPERAND(vvvvRegister)
670 if (!HasMemOp4Prefix)
671 HANDLE_OPTIONAL(immediate)
672 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
673 break;
674 case X86Local::MRMXr:
675 case X86Local::MRM0r:
676 case X86Local::MRM1r:
677 case X86Local::MRM2r:
678 case X86Local::MRM3r:
679 case X86Local::MRM4r:
680 case X86Local::MRM5r:
681 case X86Local::MRM6r:
682 case X86Local::MRM7r:
683 {
684 // Operand 1 is a register operand in the R/M field.
685 // Operand 2 (optional) is an immediate or relocation.
686 // Operand 3 (optional) is an immediate.
687 unsigned kOp = (HasEVEX_K) ? 1:0;
688 unsigned Op4v = (HasVEX_4V) ? 1:0;
689 if (numPhysicalOperands > 3 + kOp + Op4v)
690 llvm_unreachable("Unexpected number of operands for MRMnr");
691 }
692 if (HasVEX_4V)
693 HANDLE_OPERAND(vvvvRegister)
695 if (HasEVEX_K)
696 HANDLE_OPERAND(writemaskRegister)
697 HANDLE_OPTIONAL(rmRegister)
698 HANDLE_OPTIONAL(relocation)
699 HANDLE_OPTIONAL(immediate)
700 break;
701 case X86Local::MRMXm:
702 case X86Local::MRM0m:
703 case X86Local::MRM1m:
704 case X86Local::MRM2m:
705 case X86Local::MRM3m:
706 case X86Local::MRM4m:
707 case X86Local::MRM5m:
708 case X86Local::MRM6m:
709 case X86Local::MRM7m:
710 {
711 // Operand 1 is a memory operand (possibly SIB-extended)
712 // Operand 2 (optional) is an immediate or relocation.
713 unsigned kOp = (HasEVEX_K) ? 1:0;
714 unsigned Op4v = (HasVEX_4V) ? 1:0;
715 if (numPhysicalOperands < 1 + kOp + Op4v ||
716 numPhysicalOperands > 2 + kOp + Op4v)
717 llvm_unreachable("Unexpected number of operands for MRMnm");
718 }
719 if (HasVEX_4V)
720 HANDLE_OPERAND(vvvvRegister)
721 if (HasEVEX_K)
722 HANDLE_OPERAND(writemaskRegister)
723 HANDLE_OPERAND(memory)
724 HANDLE_OPTIONAL(relocation)
725 break;
726 case X86Local::RawFrmImm8:
727 // operand 1 is a 16-bit immediate
728 // operand 2 is an 8-bit immediate
729 assert(numPhysicalOperands == 2 &&
730 "Unexpected number of operands for X86Local::RawFrmImm8");
731 HANDLE_OPERAND(immediate)
732 HANDLE_OPERAND(immediate)
733 break;
734 case X86Local::RawFrmImm16:
735 // operand 1 is a 16-bit immediate
736 // operand 2 is a 16-bit immediate
737 HANDLE_OPERAND(immediate)
738 HANDLE_OPERAND(immediate)
739 break;
740 case X86Local::MRM_F8:
741 if (Opcode == 0xc6) {
742 assert(numPhysicalOperands == 1 &&
743 "Unexpected number of operands for X86Local::MRM_F8");
744 HANDLE_OPERAND(immediate)
745 } else if (Opcode == 0xc7) {
746 assert(numPhysicalOperands == 1 &&
747 "Unexpected number of operands for X86Local::MRM_F8");
748 HANDLE_OPERAND(relocation)
749 }
750 break;
751 case X86Local::MRM_C1:
752 case X86Local::MRM_C2:
753 case X86Local::MRM_C3:
754 case X86Local::MRM_C4:
755 case X86Local::MRM_C8:
756 case X86Local::MRM_C9:
757 case X86Local::MRM_CA:
758 case X86Local::MRM_CB:
759 case X86Local::MRM_E8:
760 case X86Local::MRM_F0:
761 case X86Local::MRM_F9:
762 case X86Local::MRM_D0:
763 case X86Local::MRM_D1:
764 case X86Local::MRM_D4:
765 case X86Local::MRM_D5:
766 case X86Local::MRM_D6:
767 case X86Local::MRM_D8:
768 case X86Local::MRM_D9:
769 case X86Local::MRM_DA:
770 case X86Local::MRM_DB:
771 case X86Local::MRM_DC:
772 case X86Local::MRM_DD:
773 case X86Local::MRM_DE:
774 case X86Local::MRM_DF:
775 // Ignored.
776 break;
777 }
779 #undef HANDLE_OPERAND
780 #undef HANDLE_OPTIONAL
781 }
783 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
784 // Special cases where the LLVM tables are not complete
786 #define MAP(from, to) \
787 case X86Local::MRM_##from: \
788 filter = new ExactFilter(0x##from); \
789 break;
791 OpcodeType opcodeType = (OpcodeType)-1;
793 ModRMFilter* filter = NULL;
794 uint8_t opcodeToSet = 0;
796 switch (OpMap) {
797 default: llvm_unreachable("Invalid map!");
798 case X86Local::OB:
799 case X86Local::TB:
800 case X86Local::T8:
801 case X86Local::TA:
802 case X86Local::A6:
803 case X86Local::A7:
804 case X86Local::XOP8:
805 case X86Local::XOP9:
806 case X86Local::XOPA:
807 switch (OpMap) {
808 default: llvm_unreachable("Unexpected map!");
809 case X86Local::OB: opcodeType = ONEBYTE; break;
810 case X86Local::TB: opcodeType = TWOBYTE; break;
811 case X86Local::T8: opcodeType = THREEBYTE_38; break;
812 case X86Local::TA: opcodeType = THREEBYTE_3A; break;
813 case X86Local::A6: opcodeType = THREEBYTE_A6; break;
814 case X86Local::A7: opcodeType = THREEBYTE_A7; break;
815 case X86Local::XOP8: opcodeType = XOP8_MAP; break;
816 case X86Local::XOP9: opcodeType = XOP9_MAP; break;
817 case X86Local::XOPA: opcodeType = XOPA_MAP; break;
818 }
820 switch (Form) {
821 default:
822 filter = new DumbFilter();
823 break;
824 case X86Local::MRMDestReg: case X86Local::MRMDestMem:
825 case X86Local::MRMSrcReg: case X86Local::MRMSrcMem:
826 case X86Local::MRMXr: case X86Local::MRMXm:
827 filter = new ModFilter(isRegFormat(Form));
828 break;
829 case X86Local::MRM0r: case X86Local::MRM1r:
830 case X86Local::MRM2r: case X86Local::MRM3r:
831 case X86Local::MRM4r: case X86Local::MRM5r:
832 case X86Local::MRM6r: case X86Local::MRM7r:
833 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
834 break;
835 case X86Local::MRM0m: case X86Local::MRM1m:
836 case X86Local::MRM2m: case X86Local::MRM3m:
837 case X86Local::MRM4m: case X86Local::MRM5m:
838 case X86Local::MRM6m: case X86Local::MRM7m:
839 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
840 break;
841 MRM_MAPPING
842 } // switch (Form)
844 opcodeToSet = Opcode;
845 break;
846 case X86Local::D8:
847 case X86Local::D9:
848 case X86Local::DA:
849 case X86Local::DB:
850 case X86Local::DC:
851 case X86Local::DD:
852 case X86Local::DE:
853 case X86Local::DF:
854 assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
855 assert(Form == X86Local::RawFrm);
856 opcodeType = ONEBYTE;
857 filter = new ExactFilter(Opcode);
858 opcodeToSet = 0xd8 + (OpMap - X86Local::D8);
859 break;
860 } // switch (OpMap)
862 assert(opcodeType != (OpcodeType)-1 &&
863 "Opcode type not set");
864 assert(filter && "Filter not set");
866 if (Form == X86Local::AddRegFrm) {
867 assert(((opcodeToSet & 7) == 0) &&
868 "ADDREG_FRM opcode not aligned");
870 uint8_t currentOpcode;
872 for (currentOpcode = opcodeToSet;
873 currentOpcode < opcodeToSet + 8;
874 ++currentOpcode)
875 tables.setTableFields(opcodeType,
876 insnContext(),
877 currentOpcode,
878 *filter,
879 UID, Is32Bit, IgnoresVEX_L);
880 } else {
881 tables.setTableFields(opcodeType,
882 insnContext(),
883 opcodeToSet,
884 *filter,
885 UID, Is32Bit, IgnoresVEX_L);
886 }
888 delete filter;
890 #undef MAP
891 }
893 #define TYPE(str, type) if (s == str) return type;
894 OperandType RecognizableInstr::typeFromString(const std::string &s,
895 bool hasREX_WPrefix,
896 uint8_t OpSize) {
897 if(hasREX_WPrefix) {
898 // For instructions with a REX_W prefix, a declared 32-bit register encoding
899 // is special.
900 TYPE("GR32", TYPE_R32)
901 }
902 if(OpSize == X86Local::OpSize16) {
903 // For OpSize16 instructions, a declared 16-bit register or
904 // immediate encoding is special.
905 TYPE("GR16", TYPE_Rv)
906 TYPE("i16imm", TYPE_IMMv)
907 } else if(OpSize == X86Local::OpSize32) {
908 // For OpSize32 instructions, a declared 32-bit register or
909 // immediate encoding is special.
910 TYPE("GR32", TYPE_Rv)
911 }
912 TYPE("i16mem", TYPE_Mv)
913 TYPE("i16imm", TYPE_IMM16)
914 TYPE("i16i8imm", TYPE_IMMv)
915 TYPE("GR16", TYPE_R16)
916 TYPE("i32mem", TYPE_Mv)
917 TYPE("i32imm", TYPE_IMMv)
918 TYPE("i32i8imm", TYPE_IMM32)
919 TYPE("u32u8imm", TYPE_IMM32)
920 TYPE("GR32", TYPE_R32)
921 TYPE("GR32orGR64", TYPE_R32)
922 TYPE("i64mem", TYPE_Mv)
923 TYPE("i64i32imm", TYPE_IMM64)
924 TYPE("i64i8imm", TYPE_IMM64)
925 TYPE("GR64", TYPE_R64)
926 TYPE("i8mem", TYPE_M8)
927 TYPE("i8imm", TYPE_IMM8)
928 TYPE("GR8", TYPE_R8)
929 TYPE("VR128", TYPE_XMM128)
930 TYPE("VR128X", TYPE_XMM128)
931 TYPE("f128mem", TYPE_M128)
932 TYPE("f256mem", TYPE_M256)
933 TYPE("f512mem", TYPE_M512)
934 TYPE("FR64", TYPE_XMM64)
935 TYPE("FR64X", TYPE_XMM64)
936 TYPE("f64mem", TYPE_M64FP)
937 TYPE("sdmem", TYPE_M64FP)
938 TYPE("FR32", TYPE_XMM32)
939 TYPE("FR32X", TYPE_XMM32)
940 TYPE("f32mem", TYPE_M32FP)
941 TYPE("ssmem", TYPE_M32FP)
942 TYPE("RST", TYPE_ST)
943 TYPE("i128mem", TYPE_M128)
944 TYPE("i256mem", TYPE_M256)
945 TYPE("i512mem", TYPE_M512)
946 TYPE("i64i32imm_pcrel", TYPE_REL64)
947 TYPE("i16imm_pcrel", TYPE_REL16)
948 TYPE("i32imm_pcrel", TYPE_REL32)
949 TYPE("SSECC", TYPE_IMM3)
950 TYPE("AVXCC", TYPE_IMM5)
951 TYPE("AVX512RC", TYPE_IMM32)
952 TYPE("brtarget", TYPE_RELv)
953 TYPE("uncondbrtarget", TYPE_RELv)
954 TYPE("brtarget8", TYPE_REL8)
955 TYPE("f80mem", TYPE_M80FP)
956 TYPE("lea32mem", TYPE_LEA)
957 TYPE("lea64_32mem", TYPE_LEA)
958 TYPE("lea64mem", TYPE_LEA)
959 TYPE("VR64", TYPE_MM64)
960 TYPE("i64imm", TYPE_IMMv)
961 TYPE("opaque32mem", TYPE_M1616)
962 TYPE("opaque48mem", TYPE_M1632)
963 TYPE("opaque80mem", TYPE_M1664)
964 TYPE("opaque512mem", TYPE_M512)
965 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
966 TYPE("DEBUG_REG", TYPE_DEBUGREG)
967 TYPE("CONTROL_REG", TYPE_CONTROLREG)
968 TYPE("srcidx8", TYPE_SRCIDX8)
969 TYPE("srcidx16", TYPE_SRCIDX16)
970 TYPE("srcidx32", TYPE_SRCIDX32)
971 TYPE("srcidx64", TYPE_SRCIDX64)
972 TYPE("dstidx8", TYPE_DSTIDX8)
973 TYPE("dstidx16", TYPE_DSTIDX16)
974 TYPE("dstidx32", TYPE_DSTIDX32)
975 TYPE("dstidx64", TYPE_DSTIDX64)
976 TYPE("offset8", TYPE_MOFFS8)
977 TYPE("offset16", TYPE_MOFFS16)
978 TYPE("offset32", TYPE_MOFFS32)
979 TYPE("offset64", TYPE_MOFFS64)
980 TYPE("VR256", TYPE_XMM256)
981 TYPE("VR256X", TYPE_XMM256)
982 TYPE("VR512", TYPE_XMM512)
983 TYPE("VK1", TYPE_VK1)
984 TYPE("VK1WM", TYPE_VK1)
985 TYPE("VK8", TYPE_VK8)
986 TYPE("VK8WM", TYPE_VK8)
987 TYPE("VK16", TYPE_VK16)
988 TYPE("VK16WM", TYPE_VK16)
989 TYPE("GR16_NOAX", TYPE_Rv)
990 TYPE("GR32_NOAX", TYPE_Rv)
991 TYPE("GR64_NOAX", TYPE_R64)
992 TYPE("vx32mem", TYPE_M32)
993 TYPE("vy32mem", TYPE_M32)
994 TYPE("vz32mem", TYPE_M32)
995 TYPE("vx64mem", TYPE_M64)
996 TYPE("vy64mem", TYPE_M64)
997 TYPE("vy64xmem", TYPE_M64)
998 TYPE("vz64mem", TYPE_M64)
999 errs() << "Unhandled type string " << s << "\n";
1000 llvm_unreachable("Unhandled type string");
1001 }
1002 #undef TYPE
1004 #define ENCODING(str, encoding) if (s == str) return encoding;
1005 OperandEncoding
1006 RecognizableInstr::immediateEncodingFromString(const std::string &s,
1007 uint8_t OpSize) {
1008 if(OpSize != X86Local::OpSize16) {
1009 // For instructions without an OpSize prefix, a declared 16-bit register or
1010 // immediate encoding is special.
1011 ENCODING("i16imm", ENCODING_IW)
1012 }
1013 ENCODING("i32i8imm", ENCODING_IB)
1014 ENCODING("u32u8imm", ENCODING_IB)
1015 ENCODING("SSECC", ENCODING_IB)
1016 ENCODING("AVXCC", ENCODING_IB)
1017 ENCODING("AVX512RC", ENCODING_IB)
1018 ENCODING("i16imm", ENCODING_Iv)
1019 ENCODING("i16i8imm", ENCODING_IB)
1020 ENCODING("i32imm", ENCODING_Iv)
1021 ENCODING("i64i32imm", ENCODING_ID)
1022 ENCODING("i64i8imm", ENCODING_IB)
1023 ENCODING("i8imm", ENCODING_IB)
1024 // This is not a typo. Instructions like BLENDVPD put
1025 // register IDs in 8-bit immediates nowadays.
1026 ENCODING("FR32", ENCODING_IB)
1027 ENCODING("FR64", ENCODING_IB)
1028 ENCODING("VR128", ENCODING_IB)
1029 ENCODING("VR256", ENCODING_IB)
1030 ENCODING("FR32X", ENCODING_IB)
1031 ENCODING("FR64X", ENCODING_IB)
1032 ENCODING("VR128X", ENCODING_IB)
1033 ENCODING("VR256X", ENCODING_IB)
1034 ENCODING("VR512", ENCODING_IB)
1035 errs() << "Unhandled immediate encoding " << s << "\n";
1036 llvm_unreachable("Unhandled immediate encoding");
1037 }
1039 OperandEncoding
1040 RecognizableInstr::rmRegisterEncodingFromString(const std::string &s,
1041 uint8_t OpSize) {
1042 ENCODING("RST", ENCODING_FP)
1043 ENCODING("GR16", ENCODING_RM)
1044 ENCODING("GR32", ENCODING_RM)
1045 ENCODING("GR32orGR64", ENCODING_RM)
1046 ENCODING("GR64", ENCODING_RM)
1047 ENCODING("GR8", ENCODING_RM)
1048 ENCODING("VR128", ENCODING_RM)
1049 ENCODING("VR128X", ENCODING_RM)
1050 ENCODING("FR64", ENCODING_RM)
1051 ENCODING("FR32", ENCODING_RM)
1052 ENCODING("FR64X", ENCODING_RM)
1053 ENCODING("FR32X", ENCODING_RM)
1054 ENCODING("VR64", ENCODING_RM)
1055 ENCODING("VR256", ENCODING_RM)
1056 ENCODING("VR256X", ENCODING_RM)
1057 ENCODING("VR512", ENCODING_RM)
1058 ENCODING("VK1", ENCODING_RM)
1059 ENCODING("VK8", ENCODING_RM)
1060 ENCODING("VK16", ENCODING_RM)
1061 errs() << "Unhandled R/M register encoding " << s << "\n";
1062 llvm_unreachable("Unhandled R/M register encoding");
1063 }
1065 OperandEncoding
1066 RecognizableInstr::roRegisterEncodingFromString(const std::string &s,
1067 uint8_t OpSize) {
1068 ENCODING("GR16", ENCODING_REG)
1069 ENCODING("GR32", ENCODING_REG)
1070 ENCODING("GR32orGR64", ENCODING_REG)
1071 ENCODING("GR64", ENCODING_REG)
1072 ENCODING("GR8", ENCODING_REG)
1073 ENCODING("VR128", ENCODING_REG)
1074 ENCODING("FR64", ENCODING_REG)
1075 ENCODING("FR32", ENCODING_REG)
1076 ENCODING("VR64", ENCODING_REG)
1077 ENCODING("SEGMENT_REG", ENCODING_REG)
1078 ENCODING("DEBUG_REG", ENCODING_REG)
1079 ENCODING("CONTROL_REG", ENCODING_REG)
1080 ENCODING("VR256", ENCODING_REG)
1081 ENCODING("VR256X", ENCODING_REG)
1082 ENCODING("VR128X", ENCODING_REG)
1083 ENCODING("FR64X", ENCODING_REG)
1084 ENCODING("FR32X", ENCODING_REG)
1085 ENCODING("VR512", ENCODING_REG)
1086 ENCODING("VK1", ENCODING_REG)
1087 ENCODING("VK8", ENCODING_REG)
1088 ENCODING("VK16", ENCODING_REG)
1089 ENCODING("VK1WM", ENCODING_REG)
1090 ENCODING("VK8WM", ENCODING_REG)
1091 ENCODING("VK16WM", ENCODING_REG)
1092 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1093 llvm_unreachable("Unhandled reg/opcode register encoding");
1094 }
1096 OperandEncoding
1097 RecognizableInstr::vvvvRegisterEncodingFromString(const std::string &s,
1098 uint8_t OpSize) {
1099 ENCODING("GR32", ENCODING_VVVV)
1100 ENCODING("GR64", ENCODING_VVVV)
1101 ENCODING("FR32", ENCODING_VVVV)
1102 ENCODING("FR64", ENCODING_VVVV)
1103 ENCODING("VR128", ENCODING_VVVV)
1104 ENCODING("VR256", ENCODING_VVVV)
1105 ENCODING("FR32X", ENCODING_VVVV)
1106 ENCODING("FR64X", ENCODING_VVVV)
1107 ENCODING("VR128X", ENCODING_VVVV)
1108 ENCODING("VR256X", ENCODING_VVVV)
1109 ENCODING("VR512", ENCODING_VVVV)
1110 ENCODING("VK1", ENCODING_VVVV)
1111 ENCODING("VK8", ENCODING_VVVV)
1112 ENCODING("VK16", ENCODING_VVVV)
1113 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1114 llvm_unreachable("Unhandled VEX.vvvv register encoding");
1115 }
1117 OperandEncoding
1118 RecognizableInstr::writemaskRegisterEncodingFromString(const std::string &s,
1119 uint8_t OpSize) {
1120 ENCODING("VK1WM", ENCODING_WRITEMASK)
1121 ENCODING("VK8WM", ENCODING_WRITEMASK)
1122 ENCODING("VK16WM", ENCODING_WRITEMASK)
1123 errs() << "Unhandled mask register encoding " << s << "\n";
1124 llvm_unreachable("Unhandled mask register encoding");
1125 }
1127 OperandEncoding
1128 RecognizableInstr::memoryEncodingFromString(const std::string &s,
1129 uint8_t OpSize) {
1130 ENCODING("i16mem", ENCODING_RM)
1131 ENCODING("i32mem", ENCODING_RM)
1132 ENCODING("i64mem", ENCODING_RM)
1133 ENCODING("i8mem", ENCODING_RM)
1134 ENCODING("ssmem", ENCODING_RM)
1135 ENCODING("sdmem", ENCODING_RM)
1136 ENCODING("f128mem", ENCODING_RM)
1137 ENCODING("f256mem", ENCODING_RM)
1138 ENCODING("f512mem", ENCODING_RM)
1139 ENCODING("f64mem", ENCODING_RM)
1140 ENCODING("f32mem", ENCODING_RM)
1141 ENCODING("i128mem", ENCODING_RM)
1142 ENCODING("i256mem", ENCODING_RM)
1143 ENCODING("i512mem", ENCODING_RM)
1144 ENCODING("f80mem", ENCODING_RM)
1145 ENCODING("lea32mem", ENCODING_RM)
1146 ENCODING("lea64_32mem", ENCODING_RM)
1147 ENCODING("lea64mem", ENCODING_RM)
1148 ENCODING("opaque32mem", ENCODING_RM)
1149 ENCODING("opaque48mem", ENCODING_RM)
1150 ENCODING("opaque80mem", ENCODING_RM)
1151 ENCODING("opaque512mem", ENCODING_RM)
1152 ENCODING("vx32mem", ENCODING_RM)
1153 ENCODING("vy32mem", ENCODING_RM)
1154 ENCODING("vz32mem", ENCODING_RM)
1155 ENCODING("vx64mem", ENCODING_RM)
1156 ENCODING("vy64mem", ENCODING_RM)
1157 ENCODING("vy64xmem", ENCODING_RM)
1158 ENCODING("vz64mem", ENCODING_RM)
1159 errs() << "Unhandled memory encoding " << s << "\n";
1160 llvm_unreachable("Unhandled memory encoding");
1161 }
1163 OperandEncoding
1164 RecognizableInstr::relocationEncodingFromString(const std::string &s,
1165 uint8_t OpSize) {
1166 if(OpSize != X86Local::OpSize16) {
1167 // For instructions without an OpSize prefix, a declared 16-bit register or
1168 // immediate encoding is special.
1169 ENCODING("i16imm", ENCODING_IW)
1170 }
1171 ENCODING("i16imm", ENCODING_Iv)
1172 ENCODING("i16i8imm", ENCODING_IB)
1173 ENCODING("i32imm", ENCODING_Iv)
1174 ENCODING("i32i8imm", ENCODING_IB)
1175 ENCODING("i64i32imm", ENCODING_ID)
1176 ENCODING("i64i8imm", ENCODING_IB)
1177 ENCODING("i8imm", ENCODING_IB)
1178 ENCODING("i64i32imm_pcrel", ENCODING_ID)
1179 ENCODING("i16imm_pcrel", ENCODING_IW)
1180 ENCODING("i32imm_pcrel", ENCODING_ID)
1181 ENCODING("brtarget", ENCODING_Iv)
1182 ENCODING("brtarget8", ENCODING_IB)
1183 ENCODING("i64imm", ENCODING_IO)
1184 ENCODING("offset8", ENCODING_Ia)
1185 ENCODING("offset16", ENCODING_Ia)
1186 ENCODING("offset32", ENCODING_Ia)
1187 ENCODING("offset64", ENCODING_Ia)
1188 ENCODING("srcidx8", ENCODING_SI)
1189 ENCODING("srcidx16", ENCODING_SI)
1190 ENCODING("srcidx32", ENCODING_SI)
1191 ENCODING("srcidx64", ENCODING_SI)
1192 ENCODING("dstidx8", ENCODING_DI)
1193 ENCODING("dstidx16", ENCODING_DI)
1194 ENCODING("dstidx32", ENCODING_DI)
1195 ENCODING("dstidx64", ENCODING_DI)
1196 errs() << "Unhandled relocation encoding " << s << "\n";
1197 llvm_unreachable("Unhandled relocation encoding");
1198 }
1200 OperandEncoding
1201 RecognizableInstr::opcodeModifierEncodingFromString(const std::string &s,
1202 uint8_t OpSize) {
1203 ENCODING("GR32", ENCODING_Rv)
1204 ENCODING("GR64", ENCODING_RO)
1205 ENCODING("GR16", ENCODING_Rv)
1206 ENCODING("GR8", ENCODING_RB)
1207 ENCODING("GR16_NOAX", ENCODING_Rv)
1208 ENCODING("GR32_NOAX", ENCODING_Rv)
1209 ENCODING("GR64_NOAX", ENCODING_RO)
1210 errs() << "Unhandled opcode modifier encoding " << s << "\n";
1211 llvm_unreachable("Unhandled opcode modifier encoding");
1212 }
1213 #undef ENCODING