1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
14 //
15 //===----------------------------------------------------------------------===//
17 #include "X86RecognizableInstr.h"
18 #include "X86DisassemblerShared.h"
19 #include "X86ModRMFilters.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include <string>
23 using namespace llvm;
25 #define MRM_MAPPING \
26 MAP(C1, 33) \
27 MAP(C2, 34) \
28 MAP(C3, 35) \
29 MAP(C4, 36) \
30 MAP(C8, 37) \
31 MAP(C9, 38) \
32 MAP(CA, 39) \
33 MAP(CB, 40) \
34 MAP(E8, 41) \
35 MAP(F0, 42) \
36 MAP(F8, 45) \
37 MAP(F9, 46) \
38 MAP(D0, 47) \
39 MAP(D1, 48) \
40 MAP(D4, 49) \
41 MAP(D5, 50) \
42 MAP(D6, 51) \
43 MAP(D8, 52) \
44 MAP(D9, 53) \
45 MAP(DA, 54) \
46 MAP(DB, 55) \
47 MAP(DC, 56) \
48 MAP(DD, 57) \
49 MAP(DE, 58) \
50 MAP(DF, 59)
52 // A clone of X86 since we can't depend on something that is generated.
53 namespace X86Local {
54 enum {
55 Pseudo = 0,
56 RawFrm = 1,
57 AddRegFrm = 2,
58 MRMDestReg = 3,
59 MRMDestMem = 4,
60 MRMSrcReg = 5,
61 MRMSrcMem = 6,
62 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
63 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
64 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
65 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
66 MRMInitReg = 32,
67 RawFrmImm8 = 43,
68 RawFrmImm16 = 44,
69 #define MAP(from, to) MRM_##from = to,
70 MRM_MAPPING
71 #undef MAP
72 lastMRM
73 };
75 enum {
76 TB = 1,
77 REP = 2,
78 D8 = 3, D9 = 4, DA = 5, DB = 6,
79 DC = 7, DD = 8, DE = 9, DF = 10,
80 XD = 11, XS = 12,
81 T8 = 13, P_TA = 14,
82 A6 = 15, A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19,
83 XOP8 = 20, XOP9 = 21, XOPA = 22
84 };
85 }
87 // If rows are added to the opcode extension tables, then corresponding entries
88 // must be added here.
89 //
90 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
91 // that byte to ONE_BYTE_EXTENSION_TABLES.
92 //
93 // If the row corresponds to two bytes where the first is 0f, add an entry for
94 // the second byte to TWO_BYTE_EXTENSION_TABLES.
95 //
96 // If the row corresponds to some other set of bytes, you will need to modify
97 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
98 // to the X86 TD files, except in two cases: if the first two bytes of such a
99 // new combination are 0f 38 or 0f 3a, you just have to add maps called
100 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
101 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
102 // in RecognizableInstr::emitDecodePath().
104 #define ONE_BYTE_EXTENSION_TABLES \
105 EXTENSION_TABLE(80) \
106 EXTENSION_TABLE(81) \
107 EXTENSION_TABLE(82) \
108 EXTENSION_TABLE(83) \
109 EXTENSION_TABLE(8f) \
110 EXTENSION_TABLE(c0) \
111 EXTENSION_TABLE(c1) \
112 EXTENSION_TABLE(c6) \
113 EXTENSION_TABLE(c7) \
114 EXTENSION_TABLE(d0) \
115 EXTENSION_TABLE(d1) \
116 EXTENSION_TABLE(d2) \
117 EXTENSION_TABLE(d3) \
118 EXTENSION_TABLE(f6) \
119 EXTENSION_TABLE(f7) \
120 EXTENSION_TABLE(fe) \
121 EXTENSION_TABLE(ff)
123 #define TWO_BYTE_EXTENSION_TABLES \
124 EXTENSION_TABLE(00) \
125 EXTENSION_TABLE(01) \
126 EXTENSION_TABLE(0d) \
127 EXTENSION_TABLE(18) \
128 EXTENSION_TABLE(71) \
129 EXTENSION_TABLE(72) \
130 EXTENSION_TABLE(73) \
131 EXTENSION_TABLE(ae) \
132 EXTENSION_TABLE(ba) \
133 EXTENSION_TABLE(c7)
135 #define THREE_BYTE_38_EXTENSION_TABLES \
136 EXTENSION_TABLE(F3)
138 #define XOP9_MAP_EXTENSION_TABLES \
139 EXTENSION_TABLE(01) \
140 EXTENSION_TABLE(02)
142 using namespace X86Disassembler;
144 /// needsModRMForDecode - Indicates whether a particular instruction requires a
145 /// ModR/M byte for the instruction to be properly decoded. For example, a
146 /// MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
147 /// 0b11.
148 ///
149 /// @param form - The form of the instruction.
150 /// @return - true if the form implies that a ModR/M byte is required, false
151 /// otherwise.
152 static bool needsModRMForDecode(uint8_t form) {
153 if (form == X86Local::MRMDestReg ||
154 form == X86Local::MRMDestMem ||
155 form == X86Local::MRMSrcReg ||
156 form == X86Local::MRMSrcMem ||
157 (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
158 (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
159 return true;
160 else
161 return false;
162 }
164 /// isRegFormat - Indicates whether a particular form requires the Mod field of
165 /// the ModR/M byte to be 0b11.
166 ///
167 /// @param form - The form of the instruction.
168 /// @return - true if the form implies that Mod must be 0b11, false
169 /// otherwise.
170 static bool isRegFormat(uint8_t form) {
171 if (form == X86Local::MRMDestReg ||
172 form == X86Local::MRMSrcReg ||
173 (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
174 return true;
175 else
176 return false;
177 }
179 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
180 /// Useful for switch statements and the like.
181 ///
182 /// @param init - A reference to the BitsInit to be decoded.
183 /// @return - The field, with the first bit in the BitsInit as the lowest
184 /// order bit.
185 static uint8_t byteFromBitsInit(BitsInit &init) {
186 int width = init.getNumBits();
188 assert(width <= 8 && "Field is too large for uint8_t!");
190 int index;
191 uint8_t mask = 0x01;
193 uint8_t ret = 0;
195 for (index = 0; index < width; index++) {
196 if (static_cast<BitInit*>(init.getBit(index))->getValue())
197 ret |= mask;
199 mask <<= 1;
200 }
202 return ret;
203 }
205 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
206 /// name of the field.
207 ///
208 /// @param rec - The record from which to extract the value.
209 /// @param name - The name of the field in the record.
210 /// @return - The field, as translated by byteFromBitsInit().
211 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
212 BitsInit* bits = rec->getValueAsBitsInit(name);
213 return byteFromBitsInit(*bits);
214 }
216 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
217 const CodeGenInstruction &insn,
218 InstrUID uid) {
219 UID = uid;
221 Rec = insn.TheDef;
222 Name = Rec->getName();
223 Spec = &tables.specForUID(UID);
225 if (!Rec->isSubClassOf("X86Inst")) {
226 ShouldBeEmitted = false;
227 return;
228 }
230 Prefix = byteFromRec(Rec, "Prefix");
231 Opcode = byteFromRec(Rec, "Opcode");
232 Form = byteFromRec(Rec, "FormBits");
233 SegOvr = byteFromRec(Rec, "SegOvrBits");
235 HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix");
236 HasAdSizePrefix = Rec->getValueAsBit("hasAdSizePrefix");
237 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
238 HasVEXPrefix = Rec->getValueAsBit("hasVEXPrefix");
239 HasVEX_4VPrefix = Rec->getValueAsBit("hasVEX_4VPrefix");
240 HasVEX_4VOp3Prefix = Rec->getValueAsBit("hasVEX_4VOp3Prefix");
241 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix");
242 HasMemOp4Prefix = Rec->getValueAsBit("hasMemOp4Prefix");
243 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
244 HasEVEXPrefix = Rec->getValueAsBit("hasEVEXPrefix");
245 HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2");
246 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K");
247 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B");
248 HasLockPrefix = Rec->getValueAsBit("hasLockPrefix");
249 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
251 Name = Rec->getName();
252 AsmString = Rec->getValueAsString("AsmString");
254 Operands = &insn.Operands.OperandList;
256 IsSSE = (HasOpSizePrefix && (Name.find("16") == Name.npos)) ||
257 (Name.find("CRC32") != Name.npos);
258 HasFROperands = hasFROperands();
259 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L");
261 // Check for 64-bit inst which does not require REX
262 Is32Bit = false;
263 Is64Bit = false;
264 // FIXME: Is there some better way to check for In64BitMode?
265 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
266 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
267 if (Predicates[i]->getName().find("32Bit") != Name.npos) {
268 Is32Bit = true;
269 break;
270 }
271 if (Predicates[i]->getName().find("64Bit") != Name.npos) {
272 Is64Bit = true;
273 break;
274 }
275 }
276 // FIXME: These instructions aren't marked as 64-bit in any way
277 Is64Bit |= Rec->getName() == "JMP64pcrel32" ||
278 Rec->getName() == "MASKMOVDQU64" ||
279 Rec->getName() == "POPFS64" ||
280 Rec->getName() == "POPGS64" ||
281 Rec->getName() == "PUSHFS64" ||
282 Rec->getName() == "PUSHGS64" ||
283 Rec->getName() == "REX64_PREFIX" ||
284 Rec->getName().find("MOV64") != Name.npos ||
285 Rec->getName().find("PUSH64") != Name.npos ||
286 Rec->getName().find("POP64") != Name.npos;
288 ShouldBeEmitted = true;
289 }
291 void RecognizableInstr::processInstr(DisassemblerTables &tables,
292 const CodeGenInstruction &insn,
293 InstrUID uid)
294 {
295 // Ignore "asm parser only" instructions.
296 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
297 return;
299 RecognizableInstr recogInstr(tables, insn, uid);
301 recogInstr.emitInstructionSpecifier(tables);
303 if (recogInstr.shouldBeEmitted())
304 recogInstr.emitDecodePath(tables);
305 }
307 #define EVEX_KB(n) (HasEVEX_K && HasEVEX_B? n##_K_B : \
308 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n)))
310 InstructionContext RecognizableInstr::insnContext() const {
311 InstructionContext insnContext;
313 if (HasEVEXPrefix) {
314 if (HasVEX_LPrefix && HasEVEX_L2Prefix) {
315 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n";
316 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled");
317 }
318 // VEX_L & VEX_W
319 if (HasVEX_LPrefix && HasVEX_WPrefix) {
320 if (HasOpSizePrefix)
321 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE);
322 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
323 insnContext = EVEX_KB(IC_EVEX_L_W_XS);
324 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
325 Prefix == X86Local::TAXD)
326 insnContext = EVEX_KB(IC_EVEX_L_W_XD);
327 else
328 insnContext = EVEX_KB(IC_EVEX_L_W);
329 } else if (HasVEX_LPrefix) {
330 // VEX_L
331 if (HasOpSizePrefix)
332 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE);
333 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
334 insnContext = EVEX_KB(IC_EVEX_L_XS);
335 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
336 Prefix == X86Local::TAXD)
337 insnContext = EVEX_KB(IC_EVEX_L_XD);
338 else
339 insnContext = EVEX_KB(IC_EVEX_L);
340 }
341 else if (HasEVEX_L2Prefix && HasVEX_WPrefix) {
342 // EVEX_L2 & VEX_W
343 if (HasOpSizePrefix)
344 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE);
345 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
346 insnContext = EVEX_KB(IC_EVEX_L2_W_XS);
347 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
348 Prefix == X86Local::TAXD)
349 insnContext = EVEX_KB(IC_EVEX_L2_W_XD);
350 else
351 insnContext = EVEX_KB(IC_EVEX_L2_W);
352 } else if (HasEVEX_L2Prefix) {
353 // EVEX_L2
354 if (HasOpSizePrefix)
355 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE);
356 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
357 Prefix == X86Local::TAXD)
358 insnContext = EVEX_KB(IC_EVEX_L2_XD);
359 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
360 insnContext = EVEX_KB(IC_EVEX_L2_XS);
361 else
362 insnContext = EVEX_KB(IC_EVEX_L2);
363 }
364 else if (HasVEX_WPrefix) {
365 // VEX_W
366 if (HasOpSizePrefix)
367 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE);
368 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
369 insnContext = EVEX_KB(IC_EVEX_W_XS);
370 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
371 Prefix == X86Local::TAXD)
372 insnContext = EVEX_KB(IC_EVEX_W_XD);
373 else
374 insnContext = EVEX_KB(IC_EVEX_W);
375 }
376 // No L, no W
377 else if (HasOpSizePrefix)
378 insnContext = EVEX_KB(IC_EVEX_OPSIZE);
379 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
380 Prefix == X86Local::TAXD)
381 insnContext = EVEX_KB(IC_EVEX_XD);
382 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
383 insnContext = EVEX_KB(IC_EVEX_XS);
384 else
385 insnContext = EVEX_KB(IC_EVEX);
386 /// eof EVEX
387 } else if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) {
388 if (HasVEX_LPrefix && HasVEX_WPrefix) {
389 if (HasOpSizePrefix)
390 insnContext = IC_VEX_L_W_OPSIZE;
391 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
392 insnContext = IC_VEX_L_W_XS;
393 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
394 Prefix == X86Local::TAXD)
395 insnContext = IC_VEX_L_W_XD;
396 else
397 insnContext = IC_VEX_L_W;
398 } else if (HasOpSizePrefix && HasVEX_LPrefix)
399 insnContext = IC_VEX_L_OPSIZE;
400 else if (HasOpSizePrefix && HasVEX_WPrefix)
401 insnContext = IC_VEX_W_OPSIZE;
402 else if (HasOpSizePrefix)
403 insnContext = IC_VEX_OPSIZE;
404 else if (HasVEX_LPrefix &&
405 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
406 insnContext = IC_VEX_L_XS;
407 else if (HasVEX_LPrefix && (Prefix == X86Local::XD ||
408 Prefix == X86Local::T8XD ||
409 Prefix == X86Local::TAXD))
410 insnContext = IC_VEX_L_XD;
411 else if (HasVEX_WPrefix &&
412 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
413 insnContext = IC_VEX_W_XS;
414 else if (HasVEX_WPrefix && (Prefix == X86Local::XD ||
415 Prefix == X86Local::T8XD ||
416 Prefix == X86Local::TAXD))
417 insnContext = IC_VEX_W_XD;
418 else if (HasVEX_WPrefix)
419 insnContext = IC_VEX_W;
420 else if (HasVEX_LPrefix)
421 insnContext = IC_VEX_L;
422 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
423 Prefix == X86Local::TAXD)
424 insnContext = IC_VEX_XD;
425 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
426 insnContext = IC_VEX_XS;
427 else
428 insnContext = IC_VEX;
429 } else if (Is64Bit || HasREX_WPrefix) {
430 if (HasREX_WPrefix && HasOpSizePrefix)
431 insnContext = IC_64BIT_REXW_OPSIZE;
432 else if (HasOpSizePrefix && (Prefix == X86Local::XD ||
433 Prefix == X86Local::T8XD ||
434 Prefix == X86Local::TAXD))
435 insnContext = IC_64BIT_XD_OPSIZE;
436 else if (HasOpSizePrefix &&
437 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
438 insnContext = IC_64BIT_XS_OPSIZE;
439 else if (HasOpSizePrefix)
440 insnContext = IC_64BIT_OPSIZE;
441 else if (HasAdSizePrefix)
442 insnContext = IC_64BIT_ADSIZE;
443 else if (HasREX_WPrefix &&
444 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
445 insnContext = IC_64BIT_REXW_XS;
446 else if (HasREX_WPrefix && (Prefix == X86Local::XD ||
447 Prefix == X86Local::T8XD ||
448 Prefix == X86Local::TAXD))
449 insnContext = IC_64BIT_REXW_XD;
450 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
451 Prefix == X86Local::TAXD)
452 insnContext = IC_64BIT_XD;
453 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
454 insnContext = IC_64BIT_XS;
455 else if (HasREX_WPrefix)
456 insnContext = IC_64BIT_REXW;
457 else
458 insnContext = IC_64BIT;
459 } else {
460 if (HasOpSizePrefix && (Prefix == X86Local::XD ||
461 Prefix == X86Local::T8XD ||
462 Prefix == X86Local::TAXD))
463 insnContext = IC_XD_OPSIZE;
464 else if (HasOpSizePrefix &&
465 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
466 insnContext = IC_XS_OPSIZE;
467 else if (HasOpSizePrefix)
468 insnContext = IC_OPSIZE;
469 else if (HasAdSizePrefix)
470 insnContext = IC_ADSIZE;
471 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
472 Prefix == X86Local::TAXD)
473 insnContext = IC_XD;
474 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS ||
475 Prefix == X86Local::REP)
476 insnContext = IC_XS;
477 else
478 insnContext = IC;
479 }
481 return insnContext;
482 }
484 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
485 ///////////////////
486 // FILTER_STRONG
487 //
489 // Filter out intrinsics
491 assert(Rec->isSubClassOf("X86Inst") && "Can only filter X86 instructions");
493 if (Form == X86Local::Pseudo ||
494 (IsCodeGenOnly && Name.find("_REV") == Name.npos &&
495 Name.find("INC32") == Name.npos && Name.find("DEC32") == Name.npos))
496 return FILTER_STRONG;
499 // Filter out artificial instructions but leave in the LOCK_PREFIX so it is
500 // printed as a separate "instruction".
502 if (Name.find("_Int") != Name.npos ||
503 Name.find("Int_") != Name.npos)
504 return FILTER_STRONG;
506 // Filter out instructions with segment override prefixes.
507 // They're too messy to handle now and we'll special case them if needed.
509 if (SegOvr)
510 return FILTER_STRONG;
513 /////////////////
514 // FILTER_WEAK
515 //
518 // Filter out instructions with a LOCK prefix;
519 // prefer forms that do not have the prefix
520 if (HasLockPrefix)
521 return FILTER_WEAK;
523 // Filter out alternate forms of AVX instructions
524 if (Name.find("_alt") != Name.npos ||
525 (Name.find("r64r") != Name.npos && Name.find("r64r64") == Name.npos && Name.find("r64r8") == Name.npos) ||
526 Name.find("_64mr") != Name.npos ||
527 Name.find("rr64") != Name.npos)
528 return FILTER_WEAK;
530 // Special cases.
532 if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos)
533 return FILTER_WEAK;
534 if (Name.find("Fs") != Name.npos)
535 return FILTER_WEAK;
536 if (Name == "PUSH64i16" ||
537 Name == "MOVPQI2QImr" ||
538 Name == "VMOVPQI2QImr" ||
539 Name == "VMASKMOVDQU64")
540 return FILTER_WEAK;
542 // XACQUIRE and XRELEASE reuse REPNE and REP respectively.
543 // For now, just prefer the REP versions.
544 if (Name == "XACQUIRE_PREFIX" ||
545 Name == "XRELEASE_PREFIX")
546 return FILTER_WEAK;
548 if (HasFROperands && Name.find("MOV") != Name.npos &&
549 ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
550 (Name.find("to") != Name.npos)))
551 return FILTER_STRONG;
553 return FILTER_NORMAL;
554 }
556 bool RecognizableInstr::hasFROperands() const {
557 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
558 unsigned numOperands = OperandList.size();
560 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
561 const std::string &recName = OperandList[operandIndex].Rec->getName();
563 if (recName.find("FR") != recName.npos)
564 return true;
565 }
566 return false;
567 }
569 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
570 unsigned &physicalOperandIndex,
571 unsigned &numPhysicalOperands,
572 const unsigned *operandMapping,
573 OperandEncoding (*encodingFromString)
574 (const std::string&,
575 bool hasOpSizePrefix)) {
576 if (optional) {
577 if (physicalOperandIndex >= numPhysicalOperands)
578 return;
579 } else {
580 assert(physicalOperandIndex < numPhysicalOperands);
581 }
583 while (operandMapping[operandIndex] != operandIndex) {
584 Spec->operands[operandIndex].encoding = ENCODING_DUP;
585 Spec->operands[operandIndex].type =
586 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
587 ++operandIndex;
588 }
590 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
592 Spec->operands[operandIndex].encoding = encodingFromString(typeName,
593 HasOpSizePrefix);
594 Spec->operands[operandIndex].type = typeFromString(typeName,
595 IsSSE,
596 HasREX_WPrefix,
597 HasOpSizePrefix);
599 ++operandIndex;
600 ++physicalOperandIndex;
601 }
603 void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
604 Spec->name = Name;
606 if (!ShouldBeEmitted)
607 return;
609 switch (filter()) {
610 case FILTER_WEAK:
611 Spec->filtered = true;
612 break;
613 case FILTER_STRONG:
614 ShouldBeEmitted = false;
615 return;
616 case FILTER_NORMAL:
617 break;
618 }
620 Spec->insnContext = insnContext();
622 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
624 unsigned numOperands = OperandList.size();
625 unsigned numPhysicalOperands = 0;
627 // operandMapping maps from operands in OperandList to their originals.
628 // If operandMapping[i] != i, then the entry is a duplicate.
629 unsigned operandMapping[X86_MAX_OPERANDS];
630 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
632 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
633 if (OperandList[operandIndex].Constraints.size()) {
634 const CGIOperandList::ConstraintInfo &Constraint =
635 OperandList[operandIndex].Constraints[0];
636 if (Constraint.isTied()) {
637 operandMapping[operandIndex] = operandIndex;
638 operandMapping[Constraint.getTiedOperand()] = operandIndex;
639 } else {
640 ++numPhysicalOperands;
641 operandMapping[operandIndex] = operandIndex;
642 }
643 } else {
644 ++numPhysicalOperands;
645 operandMapping[operandIndex] = operandIndex;
646 }
647 }
649 #define HANDLE_OPERAND(class) \
650 handleOperand(false, \
651 operandIndex, \
652 physicalOperandIndex, \
653 numPhysicalOperands, \
654 operandMapping, \
655 class##EncodingFromString);
657 #define HANDLE_OPTIONAL(class) \
658 handleOperand(true, \
659 operandIndex, \
660 physicalOperandIndex, \
661 numPhysicalOperands, \
662 operandMapping, \
663 class##EncodingFromString);
665 // operandIndex should always be < numOperands
666 unsigned operandIndex = 0;
667 // physicalOperandIndex should always be < numPhysicalOperands
668 unsigned physicalOperandIndex = 0;
670 switch (Form) {
671 case X86Local::RawFrm:
672 // Operand 1 (optional) is an address or immediate.
673 // Operand 2 (optional) is an immediate.
674 assert(numPhysicalOperands <= 2 &&
675 "Unexpected number of operands for RawFrm");
676 HANDLE_OPTIONAL(relocation)
677 HANDLE_OPTIONAL(immediate)
678 break;
679 case X86Local::AddRegFrm:
680 // Operand 1 is added to the opcode.
681 // Operand 2 (optional) is an address.
682 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
683 "Unexpected number of operands for AddRegFrm");
684 HANDLE_OPERAND(opcodeModifier)
685 HANDLE_OPTIONAL(relocation)
686 break;
687 case X86Local::MRMDestReg:
688 // Operand 1 is a register operand in the R/M field.
689 // Operand 2 is a register operand in the Reg/Opcode field.
690 // - In AVX, there is a register operand in the VEX.vvvv field here -
691 // Operand 3 (optional) is an immediate.
692 if (HasVEX_4VPrefix)
693 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
694 "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
695 else
696 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
697 "Unexpected number of operands for MRMDestRegFrm");
699 HANDLE_OPERAND(rmRegister)
701 if (HasVEX_4VPrefix)
702 // FIXME: In AVX, the register below becomes the one encoded
703 // in ModRMVEX and the one above the one in the VEX.VVVV field
704 HANDLE_OPERAND(vvvvRegister)
706 HANDLE_OPERAND(roRegister)
707 HANDLE_OPTIONAL(immediate)
708 break;
709 case X86Local::MRMDestMem:
710 // Operand 1 is a memory operand (possibly SIB-extended)
711 // Operand 2 is a register operand in the Reg/Opcode field.
712 // - In AVX, there is a register operand in the VEX.vvvv field here -
713 // Operand 3 (optional) is an immediate.
714 if (HasVEX_4VPrefix)
715 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
716 "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
717 else
718 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
719 "Unexpected number of operands for MRMDestMemFrm");
720 HANDLE_OPERAND(memory)
722 if (HasEVEX_K)
723 HANDLE_OPERAND(writemaskRegister)
725 if (HasVEX_4VPrefix)
726 // FIXME: In AVX, the register below becomes the one encoded
727 // in ModRMVEX and the one above the one in the VEX.VVVV field
728 HANDLE_OPERAND(vvvvRegister)
730 HANDLE_OPERAND(roRegister)
731 HANDLE_OPTIONAL(immediate)
732 break;
733 case X86Local::MRMSrcReg:
734 // Operand 1 is a register operand in the Reg/Opcode field.
735 // Operand 2 is a register operand in the R/M field.
736 // - In AVX, there is a register operand in the VEX.vvvv field here -
737 // Operand 3 (optional) is an immediate.
738 // Operand 4 (optional) is an immediate.
740 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
741 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
742 "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
743 else
744 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 4 &&
745 "Unexpected number of operands for MRMSrcRegFrm");
747 HANDLE_OPERAND(roRegister)
749 if (HasEVEX_K)
750 HANDLE_OPERAND(writemaskRegister)
752 if (HasVEX_4VPrefix)
753 // FIXME: In AVX, the register below becomes the one encoded
754 // in ModRMVEX and the one above the one in the VEX.VVVV field
755 HANDLE_OPERAND(vvvvRegister)
757 if (HasMemOp4Prefix)
758 HANDLE_OPERAND(immediate)
760 HANDLE_OPERAND(rmRegister)
762 if (HasVEX_4VOp3Prefix)
763 HANDLE_OPERAND(vvvvRegister)
765 if (!HasMemOp4Prefix)
766 HANDLE_OPTIONAL(immediate)
767 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
768 HANDLE_OPTIONAL(immediate)
769 break;
770 case X86Local::MRMSrcMem:
771 // Operand 1 is a register operand in the Reg/Opcode field.
772 // Operand 2 is a memory operand (possibly SIB-extended)
773 // - In AVX, there is a register operand in the VEX.vvvv field here -
774 // Operand 3 (optional) is an immediate.
776 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
777 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
778 "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
779 else
780 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
781 "Unexpected number of operands for MRMSrcMemFrm");
783 HANDLE_OPERAND(roRegister)
785 if (HasEVEX_K)
786 HANDLE_OPERAND(writemaskRegister)
788 if (HasVEX_4VPrefix)
789 // FIXME: In AVX, the register below becomes the one encoded
790 // in ModRMVEX and the one above the one in the VEX.VVVV field
791 HANDLE_OPERAND(vvvvRegister)
793 if (HasMemOp4Prefix)
794 HANDLE_OPERAND(immediate)
796 HANDLE_OPERAND(memory)
798 if (HasVEX_4VOp3Prefix)
799 HANDLE_OPERAND(vvvvRegister)
801 if (!HasMemOp4Prefix)
802 HANDLE_OPTIONAL(immediate)
803 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
804 break;
805 case X86Local::MRM0r:
806 case X86Local::MRM1r:
807 case X86Local::MRM2r:
808 case X86Local::MRM3r:
809 case X86Local::MRM4r:
810 case X86Local::MRM5r:
811 case X86Local::MRM6r:
812 case X86Local::MRM7r:
813 {
814 // Operand 1 is a register operand in the R/M field.
815 // Operand 2 (optional) is an immediate or relocation.
816 // Operand 3 (optional) is an immediate.
817 unsigned kOp = (HasEVEX_K) ? 1:0;
818 unsigned Op4v = (HasVEX_4VPrefix) ? 1:0;
819 if (numPhysicalOperands > 3 + kOp + Op4v)
820 llvm_unreachable("Unexpected number of operands for MRMnr");
821 }
822 if (HasVEX_4VPrefix)
823 HANDLE_OPERAND(vvvvRegister)
825 if (HasEVEX_K)
826 HANDLE_OPERAND(writemaskRegister)
827 HANDLE_OPTIONAL(rmRegister)
828 HANDLE_OPTIONAL(relocation)
829 HANDLE_OPTIONAL(immediate)
830 break;
831 case X86Local::MRM0m:
832 case X86Local::MRM1m:
833 case X86Local::MRM2m:
834 case X86Local::MRM3m:
835 case X86Local::MRM4m:
836 case X86Local::MRM5m:
837 case X86Local::MRM6m:
838 case X86Local::MRM7m:
839 {
840 // Operand 1 is a memory operand (possibly SIB-extended)
841 // Operand 2 (optional) is an immediate or relocation.
842 unsigned kOp = (HasEVEX_K) ? 1:0;
843 unsigned Op4v = (HasVEX_4VPrefix) ? 1:0;
844 if (numPhysicalOperands < 1 + kOp + Op4v ||
845 numPhysicalOperands > 2 + kOp + Op4v)
846 llvm_unreachable("Unexpected number of operands for MRMnm");
847 }
848 if (HasVEX_4VPrefix)
849 HANDLE_OPERAND(vvvvRegister)
850 if (HasEVEX_K)
851 HANDLE_OPERAND(writemaskRegister)
852 HANDLE_OPERAND(memory)
853 HANDLE_OPTIONAL(relocation)
854 break;
855 case X86Local::RawFrmImm8:
856 // operand 1 is a 16-bit immediate
857 // operand 2 is an 8-bit immediate
858 assert(numPhysicalOperands == 2 &&
859 "Unexpected number of operands for X86Local::RawFrmImm8");
860 HANDLE_OPERAND(immediate)
861 HANDLE_OPERAND(immediate)
862 break;
863 case X86Local::RawFrmImm16:
864 // operand 1 is a 16-bit immediate
865 // operand 2 is a 16-bit immediate
866 HANDLE_OPERAND(immediate)
867 HANDLE_OPERAND(immediate)
868 break;
869 case X86Local::MRM_F8:
870 if (Opcode == 0xc6) {
871 assert(numPhysicalOperands == 1 &&
872 "Unexpected number of operands for X86Local::MRM_F8");
873 HANDLE_OPERAND(immediate)
874 } else if (Opcode == 0xc7) {
875 assert(numPhysicalOperands == 1 &&
876 "Unexpected number of operands for X86Local::MRM_F8");
877 HANDLE_OPERAND(relocation)
878 }
879 break;
880 case X86Local::MRMInitReg:
881 // Ignored.
882 break;
883 }
885 #undef HANDLE_OPERAND
886 #undef HANDLE_OPTIONAL
887 }
889 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
890 // Special cases where the LLVM tables are not complete
892 #define MAP(from, to) \
893 case X86Local::MRM_##from: \
894 filter = new ExactFilter(0x##from); \
895 break;
897 OpcodeType opcodeType = (OpcodeType)-1;
899 ModRMFilter* filter = NULL;
900 uint8_t opcodeToSet = 0;
902 switch (Prefix) {
903 default: llvm_unreachable("Invalid prefix!");
904 // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
905 case X86Local::XD:
906 case X86Local::XS:
907 case X86Local::TB:
908 opcodeType = TWOBYTE;
910 switch (Opcode) {
911 default:
912 if (needsModRMForDecode(Form))
913 filter = new ModFilter(isRegFormat(Form));
914 else
915 filter = new DumbFilter();
916 break;
917 #define EXTENSION_TABLE(n) case 0x##n:
918 TWO_BYTE_EXTENSION_TABLES
919 #undef EXTENSION_TABLE
920 switch (Form) {
921 default:
922 llvm_unreachable("Unhandled two-byte extended opcode");
923 case X86Local::MRM0r:
924 case X86Local::MRM1r:
925 case X86Local::MRM2r:
926 case X86Local::MRM3r:
927 case X86Local::MRM4r:
928 case X86Local::MRM5r:
929 case X86Local::MRM6r:
930 case X86Local::MRM7r:
931 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
932 break;
933 case X86Local::MRM0m:
934 case X86Local::MRM1m:
935 case X86Local::MRM2m:
936 case X86Local::MRM3m:
937 case X86Local::MRM4m:
938 case X86Local::MRM5m:
939 case X86Local::MRM6m:
940 case X86Local::MRM7m:
941 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
942 break;
943 MRM_MAPPING
944 } // switch (Form)
945 break;
946 } // switch (Opcode)
947 opcodeToSet = Opcode;
948 break;
949 case X86Local::T8:
950 case X86Local::T8XD:
951 case X86Local::T8XS:
952 opcodeType = THREEBYTE_38;
953 switch (Opcode) {
954 default:
955 if (needsModRMForDecode(Form))
956 filter = new ModFilter(isRegFormat(Form));
957 else
958 filter = new DumbFilter();
959 break;
960 #define EXTENSION_TABLE(n) case 0x##n:
961 THREE_BYTE_38_EXTENSION_TABLES
962 #undef EXTENSION_TABLE
963 switch (Form) {
964 default:
965 llvm_unreachable("Unhandled two-byte extended opcode");
966 case X86Local::MRM0r:
967 case X86Local::MRM1r:
968 case X86Local::MRM2r:
969 case X86Local::MRM3r:
970 case X86Local::MRM4r:
971 case X86Local::MRM5r:
972 case X86Local::MRM6r:
973 case X86Local::MRM7r:
974 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
975 break;
976 case X86Local::MRM0m:
977 case X86Local::MRM1m:
978 case X86Local::MRM2m:
979 case X86Local::MRM3m:
980 case X86Local::MRM4m:
981 case X86Local::MRM5m:
982 case X86Local::MRM6m:
983 case X86Local::MRM7m:
984 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
985 break;
986 MRM_MAPPING
987 } // switch (Form)
988 break;
989 } // switch (Opcode)
990 opcodeToSet = Opcode;
991 break;
992 case X86Local::P_TA:
993 case X86Local::TAXD:
994 opcodeType = THREEBYTE_3A;
995 if (needsModRMForDecode(Form))
996 filter = new ModFilter(isRegFormat(Form));
997 else
998 filter = new DumbFilter();
999 opcodeToSet = Opcode;
1000 break;
1001 case X86Local::A6:
1002 opcodeType = THREEBYTE_A6;
1003 if (needsModRMForDecode(Form))
1004 filter = new ModFilter(isRegFormat(Form));
1005 else
1006 filter = new DumbFilter();
1007 opcodeToSet = Opcode;
1008 break;
1009 case X86Local::A7:
1010 opcodeType = THREEBYTE_A7;
1011 if (needsModRMForDecode(Form))
1012 filter = new ModFilter(isRegFormat(Form));
1013 else
1014 filter = new DumbFilter();
1015 opcodeToSet = Opcode;
1016 break;
1017 case X86Local::XOP8:
1018 opcodeType = XOP8_MAP;
1019 if (needsModRMForDecode(Form))
1020 filter = new ModFilter(isRegFormat(Form));
1021 else
1022 filter = new DumbFilter();
1023 opcodeToSet = Opcode;
1024 break;
1025 case X86Local::XOP9:
1026 opcodeType = XOP9_MAP;
1027 switch (Opcode) {
1028 default:
1029 if (needsModRMForDecode(Form))
1030 filter = new ModFilter(isRegFormat(Form));
1031 else
1032 filter = new DumbFilter();
1033 break;
1034 #define EXTENSION_TABLE(n) case 0x##n:
1035 XOP9_MAP_EXTENSION_TABLES
1036 #undef EXTENSION_TABLE
1037 switch (Form) {
1038 default:
1039 llvm_unreachable("Unhandled XOP9 extended opcode");
1040 case X86Local::MRM0r:
1041 case X86Local::MRM1r:
1042 case X86Local::MRM2r:
1043 case X86Local::MRM3r:
1044 case X86Local::MRM4r:
1045 case X86Local::MRM5r:
1046 case X86Local::MRM6r:
1047 case X86Local::MRM7r:
1048 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1049 break;
1050 case X86Local::MRM0m:
1051 case X86Local::MRM1m:
1052 case X86Local::MRM2m:
1053 case X86Local::MRM3m:
1054 case X86Local::MRM4m:
1055 case X86Local::MRM5m:
1056 case X86Local::MRM6m:
1057 case X86Local::MRM7m:
1058 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1059 break;
1060 MRM_MAPPING
1061 } // switch (Form)
1062 break;
1063 } // switch (Opcode)
1064 opcodeToSet = Opcode;
1065 break;
1066 case X86Local::XOPA:
1067 opcodeType = XOPA_MAP;
1068 if (needsModRMForDecode(Form))
1069 filter = new ModFilter(isRegFormat(Form));
1070 else
1071 filter = new DumbFilter();
1072 opcodeToSet = Opcode;
1073 break;
1074 case X86Local::D8:
1075 case X86Local::D9:
1076 case X86Local::DA:
1077 case X86Local::DB:
1078 case X86Local::DC:
1079 case X86Local::DD:
1080 case X86Local::DE:
1081 case X86Local::DF:
1082 assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
1083 opcodeType = ONEBYTE;
1084 if (Form == X86Local::AddRegFrm) {
1085 Spec->modifierType = MODIFIER_MODRM;
1086 Spec->modifierBase = Opcode;
1087 filter = new AddRegEscapeFilter(Opcode);
1088 } else {
1089 filter = new EscapeFilter(true, Opcode);
1090 }
1091 opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
1092 break;
1093 case X86Local::REP:
1094 case 0:
1095 opcodeType = ONEBYTE;
1096 switch (Opcode) {
1097 #define EXTENSION_TABLE(n) case 0x##n:
1098 ONE_BYTE_EXTENSION_TABLES
1099 #undef EXTENSION_TABLE
1100 switch (Form) {
1101 default:
1102 llvm_unreachable("Fell through the cracks of a single-byte "
1103 "extended opcode");
1104 case X86Local::MRM0r:
1105 case X86Local::MRM1r:
1106 case X86Local::MRM2r:
1107 case X86Local::MRM3r:
1108 case X86Local::MRM4r:
1109 case X86Local::MRM5r:
1110 case X86Local::MRM6r:
1111 case X86Local::MRM7r:
1112 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1113 break;
1114 case X86Local::MRM0m:
1115 case X86Local::MRM1m:
1116 case X86Local::MRM2m:
1117 case X86Local::MRM3m:
1118 case X86Local::MRM4m:
1119 case X86Local::MRM5m:
1120 case X86Local::MRM6m:
1121 case X86Local::MRM7m:
1122 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1123 break;
1124 MRM_MAPPING
1125 } // switch (Form)
1126 break;
1127 case 0xd8:
1128 case 0xd9:
1129 case 0xda:
1130 case 0xdb:
1131 case 0xdc:
1132 case 0xdd:
1133 case 0xde:
1134 case 0xdf:
1135 filter = new EscapeFilter(false, Form - X86Local::MRM0m);
1136 break;
1137 default:
1138 if (needsModRMForDecode(Form))
1139 filter = new ModFilter(isRegFormat(Form));
1140 else
1141 filter = new DumbFilter();
1142 break;
1143 } // switch (Opcode)
1144 opcodeToSet = Opcode;
1145 } // switch (Prefix)
1147 assert(opcodeType != (OpcodeType)-1 &&
1148 "Opcode type not set");
1149 assert(filter && "Filter not set");
1151 if (Form == X86Local::AddRegFrm) {
1152 if(Spec->modifierType != MODIFIER_MODRM) {
1153 assert(opcodeToSet < 0xf9 &&
1154 "Not enough room for all ADDREG_FRM operands");
1156 uint8_t currentOpcode;
1158 for (currentOpcode = opcodeToSet;
1159 currentOpcode < opcodeToSet + 8;
1160 ++currentOpcode)
1161 tables.setTableFields(opcodeType,
1162 insnContext(),
1163 currentOpcode,
1164 *filter,
1165 UID, Is32Bit, IgnoresVEX_L);
1167 Spec->modifierType = MODIFIER_OPCODE;
1168 Spec->modifierBase = opcodeToSet;
1169 } else {
1170 // modifierBase was set where MODIFIER_MODRM was set
1171 tables.setTableFields(opcodeType,
1172 insnContext(),
1173 opcodeToSet,
1174 *filter,
1175 UID, Is32Bit, IgnoresVEX_L);
1176 }
1177 } else {
1178 tables.setTableFields(opcodeType,
1179 insnContext(),
1180 opcodeToSet,
1181 *filter,
1182 UID, Is32Bit, IgnoresVEX_L);
1184 Spec->modifierType = MODIFIER_NONE;
1185 Spec->modifierBase = opcodeToSet;
1186 }
1188 delete filter;
1190 #undef MAP
1191 }
1193 #define TYPE(str, type) if (s == str) return type;
1194 OperandType RecognizableInstr::typeFromString(const std::string &s,
1195 bool isSSE,
1196 bool hasREX_WPrefix,
1197 bool hasOpSizePrefix) {
1198 if (isSSE) {
1199 // For SSE instructions, we ignore the OpSize prefix and force operand
1200 // sizes.
1201 TYPE("GR16", TYPE_R16)
1202 TYPE("GR32", TYPE_R32)
1203 TYPE("GR64", TYPE_R64)
1204 }
1205 if(hasREX_WPrefix) {
1206 // For instructions with a REX_W prefix, a declared 32-bit register encoding
1207 // is special.
1208 TYPE("GR32", TYPE_R32)
1209 }
1210 if(!hasOpSizePrefix) {
1211 // For instructions without an OpSize prefix, a declared 16-bit register or
1212 // immediate encoding is special.
1213 TYPE("GR16", TYPE_R16)
1214 TYPE("i16imm", TYPE_IMM16)
1215 }
1216 TYPE("i16mem", TYPE_Mv)
1217 TYPE("i16imm", TYPE_IMMv)
1218 TYPE("i16i8imm", TYPE_IMMv)
1219 TYPE("GR16", TYPE_Rv)
1220 TYPE("i32mem", TYPE_Mv)
1221 TYPE("i32imm", TYPE_IMMv)
1222 TYPE("i32i8imm", TYPE_IMM32)
1223 TYPE("u32u8imm", TYPE_IMM32)
1224 TYPE("GR32", TYPE_Rv)
1225 TYPE("i64mem", TYPE_Mv)
1226 TYPE("i64i32imm", TYPE_IMM64)
1227 TYPE("i64i8imm", TYPE_IMM64)
1228 TYPE("GR64", TYPE_R64)
1229 TYPE("i8mem", TYPE_M8)
1230 TYPE("i8imm", TYPE_IMM8)
1231 TYPE("GR8", TYPE_R8)
1232 TYPE("VR128", TYPE_XMM128)
1233 TYPE("VR128X", TYPE_XMM128)
1234 TYPE("f128mem", TYPE_M128)
1235 TYPE("f256mem", TYPE_M256)
1236 TYPE("f512mem", TYPE_M512)
1237 TYPE("FR64", TYPE_XMM64)
1238 TYPE("FR64X", TYPE_XMM64)
1239 TYPE("f64mem", TYPE_M64FP)
1240 TYPE("sdmem", TYPE_M64FP)
1241 TYPE("FR32", TYPE_XMM32)
1242 TYPE("FR32X", TYPE_XMM32)
1243 TYPE("f32mem", TYPE_M32FP)
1244 TYPE("ssmem", TYPE_M32FP)
1245 TYPE("RST", TYPE_ST)
1246 TYPE("i128mem", TYPE_M128)
1247 TYPE("i256mem", TYPE_M256)
1248 TYPE("i512mem", TYPE_M512)
1249 TYPE("i64i32imm_pcrel", TYPE_REL64)
1250 TYPE("i16imm_pcrel", TYPE_REL16)
1251 TYPE("i32imm_pcrel", TYPE_REL32)
1252 TYPE("SSECC", TYPE_IMM3)
1253 TYPE("AVXCC", TYPE_IMM5)
1254 TYPE("brtarget", TYPE_RELv)
1255 TYPE("uncondbrtarget", TYPE_RELv)
1256 TYPE("brtarget8", TYPE_REL8)
1257 TYPE("f80mem", TYPE_M80FP)
1258 TYPE("lea32mem", TYPE_LEA)
1259 TYPE("lea64_32mem", TYPE_LEA)
1260 TYPE("lea64mem", TYPE_LEA)
1261 TYPE("VR64", TYPE_MM64)
1262 TYPE("i64imm", TYPE_IMMv)
1263 TYPE("opaque32mem", TYPE_M1616)
1264 TYPE("opaque48mem", TYPE_M1632)
1265 TYPE("opaque80mem", TYPE_M1664)
1266 TYPE("opaque512mem", TYPE_M512)
1267 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
1268 TYPE("DEBUG_REG", TYPE_DEBUGREG)
1269 TYPE("CONTROL_REG", TYPE_CONTROLREG)
1270 TYPE("offset8", TYPE_MOFFS8)
1271 TYPE("offset16", TYPE_MOFFS16)
1272 TYPE("offset32", TYPE_MOFFS32)
1273 TYPE("offset64", TYPE_MOFFS64)
1274 TYPE("VR256", TYPE_XMM256)
1275 TYPE("VR256X", TYPE_XMM256)
1276 TYPE("VR512", TYPE_XMM512)
1277 TYPE("VK8", TYPE_VK8)
1278 TYPE("VK8WM", TYPE_VK8)
1279 TYPE("VK16", TYPE_VK16)
1280 TYPE("VK16WM", TYPE_VK16)
1281 TYPE("GR16_NOAX", TYPE_Rv)
1282 TYPE("GR32_NOAX", TYPE_Rv)
1283 TYPE("GR64_NOAX", TYPE_R64)
1284 TYPE("vx32mem", TYPE_M32)
1285 TYPE("vy32mem", TYPE_M32)
1286 TYPE("vz32mem", TYPE_M32)
1287 TYPE("vx64mem", TYPE_M64)
1288 TYPE("vy64mem", TYPE_M64)
1289 TYPE("vy64xmem", TYPE_M64)
1290 TYPE("vz64mem", TYPE_M64)
1291 errs() << "Unhandled type string " << s << "\n";
1292 llvm_unreachable("Unhandled type string");
1293 }
1294 #undef TYPE
1296 #define ENCODING(str, encoding) if (s == str) return encoding;
1297 OperandEncoding RecognizableInstr::immediateEncodingFromString
1298 (const std::string &s,
1299 bool hasOpSizePrefix) {
1300 if(!hasOpSizePrefix) {
1301 // For instructions without an OpSize prefix, a declared 16-bit register or
1302 // immediate encoding is special.
1303 ENCODING("i16imm", ENCODING_IW)
1304 }
1305 ENCODING("i32i8imm", ENCODING_IB)
1306 ENCODING("u32u8imm", ENCODING_IB)
1307 ENCODING("SSECC", ENCODING_IB)
1308 ENCODING("AVXCC", ENCODING_IB)
1309 ENCODING("i16imm", ENCODING_Iv)
1310 ENCODING("i16i8imm", ENCODING_IB)
1311 ENCODING("i32imm", ENCODING_Iv)
1312 ENCODING("i64i32imm", ENCODING_ID)
1313 ENCODING("i64i8imm", ENCODING_IB)
1314 ENCODING("i8imm", ENCODING_IB)
1315 // This is not a typo. Instructions like BLENDVPD put
1316 // register IDs in 8-bit immediates nowadays.
1317 ENCODING("FR32", ENCODING_IB)
1318 ENCODING("FR64", ENCODING_IB)
1319 ENCODING("VR128", ENCODING_IB)
1320 ENCODING("VR256", ENCODING_IB)
1321 ENCODING("FR32X", ENCODING_IB)
1322 ENCODING("FR64X", ENCODING_IB)
1323 ENCODING("VR128X", ENCODING_IB)
1324 ENCODING("VR256X", ENCODING_IB)
1325 ENCODING("VR512", ENCODING_IB)
1326 errs() << "Unhandled immediate encoding " << s << "\n";
1327 llvm_unreachable("Unhandled immediate encoding");
1328 }
1330 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1331 (const std::string &s,
1332 bool hasOpSizePrefix) {
1333 ENCODING("GR16", ENCODING_RM)
1334 ENCODING("GR32", ENCODING_RM)
1335 ENCODING("GR64", ENCODING_RM)
1336 ENCODING("GR8", ENCODING_RM)
1337 ENCODING("VR128", ENCODING_RM)
1338 ENCODING("VR128X", ENCODING_RM)
1339 ENCODING("FR64", ENCODING_RM)
1340 ENCODING("FR32", ENCODING_RM)
1341 ENCODING("FR64X", ENCODING_RM)
1342 ENCODING("FR32X", ENCODING_RM)
1343 ENCODING("VR64", ENCODING_RM)
1344 ENCODING("VR256", ENCODING_RM)
1345 ENCODING("VR256X", ENCODING_RM)
1346 ENCODING("VR512", ENCODING_RM)
1347 ENCODING("VK8", ENCODING_RM)
1348 ENCODING("VK16", ENCODING_RM)
1349 errs() << "Unhandled R/M register encoding " << s << "\n";
1350 llvm_unreachable("Unhandled R/M register encoding");
1351 }
1353 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1354 (const std::string &s,
1355 bool hasOpSizePrefix) {
1356 ENCODING("GR16", ENCODING_REG)
1357 ENCODING("GR32", ENCODING_REG)
1358 ENCODING("GR64", ENCODING_REG)
1359 ENCODING("GR8", ENCODING_REG)
1360 ENCODING("VR128", ENCODING_REG)
1361 ENCODING("FR64", ENCODING_REG)
1362 ENCODING("FR32", ENCODING_REG)
1363 ENCODING("VR64", ENCODING_REG)
1364 ENCODING("SEGMENT_REG", ENCODING_REG)
1365 ENCODING("DEBUG_REG", ENCODING_REG)
1366 ENCODING("CONTROL_REG", ENCODING_REG)
1367 ENCODING("VR256", ENCODING_REG)
1368 ENCODING("VR256X", ENCODING_REG)
1369 ENCODING("VR128X", ENCODING_REG)
1370 ENCODING("FR64X", ENCODING_REG)
1371 ENCODING("FR32X", ENCODING_REG)
1372 ENCODING("VR512", ENCODING_REG)
1373 ENCODING("VK8", ENCODING_REG)
1374 ENCODING("VK16", ENCODING_REG)
1375 ENCODING("VK8WM", ENCODING_REG)
1376 ENCODING("VK16WM", ENCODING_REG)
1377 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1378 llvm_unreachable("Unhandled reg/opcode register encoding");
1379 }
1381 OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1382 (const std::string &s,
1383 bool hasOpSizePrefix) {
1384 ENCODING("GR32", ENCODING_VVVV)
1385 ENCODING("GR64", ENCODING_VVVV)
1386 ENCODING("FR32", ENCODING_VVVV)
1387 ENCODING("FR64", ENCODING_VVVV)
1388 ENCODING("VR128", ENCODING_VVVV)
1389 ENCODING("VR256", ENCODING_VVVV)
1390 ENCODING("FR32X", ENCODING_VVVV)
1391 ENCODING("FR64X", ENCODING_VVVV)
1392 ENCODING("VR128X", ENCODING_VVVV)
1393 ENCODING("VR256X", ENCODING_VVVV)
1394 ENCODING("VR512", ENCODING_VVVV)
1395 ENCODING("VK8", ENCODING_VVVV)
1396 ENCODING("VK16", ENCODING_VVVV)
1397 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1398 llvm_unreachable("Unhandled VEX.vvvv register encoding");
1399 }
1401 OperandEncoding RecognizableInstr::writemaskRegisterEncodingFromString
1402 (const std::string &s,
1403 bool hasOpSizePrefix) {
1404 ENCODING("VK8WM", ENCODING_WRITEMASK)
1405 ENCODING("VK16WM", ENCODING_WRITEMASK)
1406 errs() << "Unhandled mask register encoding " << s << "\n";
1407 llvm_unreachable("Unhandled mask register encoding");
1408 }
1410 OperandEncoding RecognizableInstr::memoryEncodingFromString
1411 (const std::string &s,
1412 bool hasOpSizePrefix) {
1413 ENCODING("i16mem", ENCODING_RM)
1414 ENCODING("i32mem", ENCODING_RM)
1415 ENCODING("i64mem", ENCODING_RM)
1416 ENCODING("i8mem", ENCODING_RM)
1417 ENCODING("ssmem", ENCODING_RM)
1418 ENCODING("sdmem", ENCODING_RM)
1419 ENCODING("f128mem", ENCODING_RM)
1420 ENCODING("f256mem", ENCODING_RM)
1421 ENCODING("f512mem", ENCODING_RM)
1422 ENCODING("f64mem", ENCODING_RM)
1423 ENCODING("f32mem", ENCODING_RM)
1424 ENCODING("i128mem", ENCODING_RM)
1425 ENCODING("i256mem", ENCODING_RM)
1426 ENCODING("i512mem", ENCODING_RM)
1427 ENCODING("f80mem", ENCODING_RM)
1428 ENCODING("lea32mem", ENCODING_RM)
1429 ENCODING("lea64_32mem", ENCODING_RM)
1430 ENCODING("lea64mem", ENCODING_RM)
1431 ENCODING("opaque32mem", ENCODING_RM)
1432 ENCODING("opaque48mem", ENCODING_RM)
1433 ENCODING("opaque80mem", ENCODING_RM)
1434 ENCODING("opaque512mem", ENCODING_RM)
1435 ENCODING("vx32mem", ENCODING_RM)
1436 ENCODING("vy32mem", ENCODING_RM)
1437 ENCODING("vz32mem", ENCODING_RM)
1438 ENCODING("vx64mem", ENCODING_RM)
1439 ENCODING("vy64mem", ENCODING_RM)
1440 ENCODING("vy64xmem", ENCODING_RM)
1441 ENCODING("vz64mem", ENCODING_RM)
1442 errs() << "Unhandled memory encoding " << s << "\n";
1443 llvm_unreachable("Unhandled memory encoding");
1444 }
1446 OperandEncoding RecognizableInstr::relocationEncodingFromString
1447 (const std::string &s,
1448 bool hasOpSizePrefix) {
1449 if(!hasOpSizePrefix) {
1450 // For instructions without an OpSize prefix, a declared 16-bit register or
1451 // immediate encoding is special.
1452 ENCODING("i16imm", ENCODING_IW)
1453 }
1454 ENCODING("i16imm", ENCODING_Iv)
1455 ENCODING("i16i8imm", ENCODING_IB)
1456 ENCODING("i32imm", ENCODING_Iv)
1457 ENCODING("i32i8imm", ENCODING_IB)
1458 ENCODING("i64i32imm", ENCODING_ID)
1459 ENCODING("i64i8imm", ENCODING_IB)
1460 ENCODING("i8imm", ENCODING_IB)
1461 ENCODING("i64i32imm_pcrel", ENCODING_ID)
1462 ENCODING("i16imm_pcrel", ENCODING_IW)
1463 ENCODING("i32imm_pcrel", ENCODING_ID)
1464 ENCODING("brtarget", ENCODING_Iv)
1465 ENCODING("brtarget8", ENCODING_IB)
1466 ENCODING("i64imm", ENCODING_IO)
1467 ENCODING("offset8", ENCODING_Ia)
1468 ENCODING("offset16", ENCODING_Ia)
1469 ENCODING("offset32", ENCODING_Ia)
1470 ENCODING("offset64", ENCODING_Ia)
1471 errs() << "Unhandled relocation encoding " << s << "\n";
1472 llvm_unreachable("Unhandled relocation encoding");
1473 }
1475 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1476 (const std::string &s,
1477 bool hasOpSizePrefix) {
1478 ENCODING("RST", ENCODING_I)
1479 ENCODING("GR32", ENCODING_Rv)
1480 ENCODING("GR64", ENCODING_RO)
1481 ENCODING("GR16", ENCODING_Rv)
1482 ENCODING("GR8", ENCODING_RB)
1483 ENCODING("GR16_NOAX", ENCODING_Rv)
1484 ENCODING("GR32_NOAX", ENCODING_Rv)
1485 ENCODING("GR64_NOAX", ENCODING_RO)
1486 errs() << "Unhandled opcode modifier encoding " << s << "\n";
1487 llvm_unreachable("Unhandled opcode modifier encoding");
1488 }
1489 #undef ENCODING