diff --git a/lib/CodeGen/AsmPrinter/DwarfExpression.cpp b/lib/CodeGen/AsmPrinter/DwarfExpression.cpp
index 1df0ea4f79f2fe9bedc1070ed90cf41c6216f007..d1b648ffabca5bccd04a311ed63295c279bc7af3 100644 (file)
//===----------------------------------------------------------------------===//
#include "DwarfExpression.h"
-
#include "DwarfDebug.h"
#include "llvm/ADT/SmallBitVector.h"
#include "llvm/CodeGen/AsmPrinter.h"
if (DwarfReg < 0)
return false;
- if (MachineReg == getFrameRegister()) {
+ if (isFrameRegister(MachineReg)) {
// If variable offset is based in frame register then use fbreg.
EmitOp(dwarf::DW_OP_fbreg);
EmitSigned(Offset);
return true;
}
-void DwarfExpression::AddMachineRegPiece(unsigned MachineReg,
+bool DwarfExpression::AddMachineRegPiece(unsigned MachineReg,
unsigned PieceSizeInBits,
unsigned PieceOffsetInBits) {
const TargetRegisterInfo *TRI = getTRI();
AddReg(Reg);
if (PieceSizeInBits)
AddOpPiece(PieceSizeInBits, PieceOffsetInBits);
- return;
+ return true;
}
// Walk up the super-register chain until we find a valid number.
AddShr(RegOffset);
AddOpPiece(Size, PieceOffsetInBits);
}
- return;
+ return true;
}
}
}
}
- if (CurPos == PieceOffsetInBits)
- // FIXME: We have no reasonable way of handling errors in here.
- EmitOp(dwarf::DW_OP_nop, "nop (could not find a dwarf register number)");
+ return CurPos > PieceOffsetInBits;
}
void DwarfExpression::AddSignedConstant(int Value) {
if (getDwarfVersion() >= 4)
EmitOp(dwarf::DW_OP_stack_value);
}
+
+static unsigned getOffsetOrZero(unsigned OffsetInBits,
+ unsigned PieceOffsetInBits) {
+ if (OffsetInBits == PieceOffsetInBits)
+ return 0;
+ assert(OffsetInBits >= PieceOffsetInBits && "overlapping pieces");
+ return OffsetInBits;
+}
+
+bool DwarfExpression::AddMachineRegExpression(DIExpression Expr,
+ unsigned MachineReg,
+ unsigned PieceOffsetInBits) {
+ auto I = Expr.begin();
+ // Pattern-match combinations for which more efficient representations exist
+ // first.
+ if (I == Expr.end())
+ return AddMachineRegPiece(MachineReg);
+
+ bool ValidReg = false;
+ switch (*I) {
+ case dwarf::DW_OP_piece: {
+ unsigned SizeOfByte = 8;
+ unsigned OffsetInBits = I.getArg(1) * SizeOfByte;
+ unsigned SizeInBits = I.getArg(2) * SizeOfByte;
+ // Piece always comes at the end of the expression.
+ return AddMachineRegPiece(MachineReg, SizeInBits,
+ getOffsetOrZero(OffsetInBits, PieceOffsetInBits));
+ }
+ case dwarf::DW_OP_plus:
+ // [DW_OP_reg,Offset,DW_OP_plus,DW_OP_deref] --> [DW_OP_breg,Offset].
+ if (*std::next(I) == dwarf::DW_OP_deref) {
+ unsigned Offset = I.getArg(1);
+ ValidReg = AddMachineRegIndirect(MachineReg, Offset);
+ std::advance(I, 2);
+ break;
+ } else
+ ValidReg = AddMachineRegPiece(MachineReg);
+ case dwarf::DW_OP_deref:
+ // [DW_OP_reg,DW_OP_deref] --> [DW_OP_breg].
+ ValidReg = AddMachineRegIndirect(MachineReg);
+ ++I;
+ break;
+ default:
+ llvm_unreachable("unsupported operand");
+ }
+
+ if (!ValidReg)
+ return false;
+
+ // Emit remaining elements of the expression.
+ AddExpression(I, PieceOffsetInBits);
+ return true;
+}
+
+void DwarfExpression::AddExpression(DIExpressionIterator I,
+ unsigned PieceOffsetInBits) {
+ for (; I != DIExpressionIterator(); ++I) {
+ switch (*I) {
+ case dwarf::DW_OP_piece: {
+ unsigned SizeOfByte = 8;
+ unsigned OffsetInBits = I.getArg(1) * SizeOfByte;
+ unsigned SizeInBits = I.getArg(2) * SizeOfByte;
+ AddOpPiece(SizeInBits, getOffsetOrZero(OffsetInBits, PieceOffsetInBits));
+ break;
+ }
+ case dwarf::DW_OP_plus:
+ EmitOp(dwarf::DW_OP_plus_uconst);
+ EmitUnsigned(I.getArg(1));
+ break;
+ case dwarf::DW_OP_deref:
+ EmitOp(dwarf::DW_OP_deref);
+ break;
+ default:
+ llvm_unreachable("unhandled opcode found in DIExpression");
+ }
+ }
+}