author | Ahmed Bougacha <ahmed.bougacha@gmail.com> | |
Mon, 1 Dec 2014 20:59:00 +0000 (20:59 +0000) | ||
committer | Ahmed Bougacha <ahmed.bougacha@gmail.com> | |
Mon, 1 Dec 2014 20:59:00 +0000 (20:59 +0000) | ||
commit | 14fe2e6948c394b0565787eddf59feec29a765da | |
tree | 8afa3739c55d81bbe1a7f297b3af59d50712f9f8 | tree | snapshot (tar.xz tar.gz zip) |
parent | 217a4a87ce1ffef091248665735980839a306dbb | commit | diff |
[AArch64] Don't combine "select (setcc i1 LHS, RHS), vL, vR".
r208210 introduced an optimization that improves the vector select
codegen by doing the setcc on vectors directly.
This is a problem they the setcc operands are i1s, because the
optimization would create vectors of i1, which aren't legal.
Part of PR21549.
Differential Revision: http://reviews.llvm.org/D6308
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223075 91177308-0d34-0410-b5e6-96231b3b80d8
r208210 introduced an optimization that improves the vector select
codegen by doing the setcc on vectors directly.
This is a problem they the setcc operands are i1s, because the
optimization would create vectors of i1, which aren't legal.
Part of PR21549.
Differential Revision: http://reviews.llvm.org/D6308
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223075 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/AArch64/AArch64ISelLowering.cpp | diff | blob | history | |
test/CodeGen/AArch64/arm64-neon-select_cc.ll | diff | blob | history |