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raw | patch | inline | side by side (parent: b59d46e)
raw | patch | inline | side by side (parent: b59d46e)
author | Matt Arsenault <Matthew.Arsenault@amd.com> | |
Tue, 10 Dec 2013 21:37:42 +0000 (21:37 +0000) | ||
committer | Matt Arsenault <Matthew.Arsenault@amd.com> | |
Tue, 10 Dec 2013 21:37:42 +0000 (21:37 +0000) |
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196971 91177308-0d34-0410-b5e6-96231b3b80d8
index 160e6f730e1e69db8a14f8436b63c5ca852466fd..8aca57a6b4794cf7e896b8586476c2259dab6281 100644 (file)
isSGPR = false;
width = 16;
} else {
- assert(!"Unknown register class");
+ llvm_unreachable("Unknown register class");
}
hwReg = RI->getEncodingValue(reg) & 0xff;
maxUsed = hwReg + width - 1;
index c4d75ffa0d06fccce2c486da20bdd56db579bc52..e0f273f83b80aaf562ea88f9a918070c5f268b74 100644 (file)
switch (Op.getOpcode()) {
default:
Op.getNode()->dump();
- assert(0 && "Custom lowering code for this"
- "instruction is not implemented yet!");
+ llvm_unreachable("Custom lowering code for this"
+ "instruction is not implemented yet!");
break;
// AMDIL DAG lowering
case ISD::SDIV: return LowerSDIV(Op, DAG);
case ISD::SETTRUE2:
case ISD::SETUO:
case ISD::SETO:
- assert(0 && "Operation should already be optimised !");
+ llvm_unreachable("Operation should already be optimised!");
case ISD::SETULE:
case ISD::SETULT:
case ISD::SETOLE:
return DAG.getNode(AMDGPUISD::FMIN, DL, VT, LHS, RHS);
}
case ISD::SETCC_INVALID:
- assert(0 && "Invalid setcc condcode !");
+ llvm_unreachable("Invalid setcc condcode!");
}
return Op;
}
index 4f7084b9202fd42aabc3dd6e68fa40d698f5922e..4bc90c0404e55370eae160b24a5219a63280e9d6 100644 (file)
int FrameIndex,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const {
- assert(!"Not Implemented");
+ llvm_unreachable("Not Implemented");
}
void
unsigned DestReg, int FrameIndex,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const {
- assert(!"Not Implemented");
+ llvm_unreachable("Not Implemented");
}
bool AMDGPUInstrInfo::expandPostRAPseudo (MachineBasicBlock::iterator MI) const {
index 47617a72990d766d8e3eed3c2fc30eecd34ae4bc..8fbec4ec378312758b221198b0a2ab4501628549 100644 (file)
int SPAdj,
unsigned FIOperandNum,
RegScavenger *RS) const {
- assert(!"Subroutines not supported yet");
+ llvm_unreachable("Subroutines not supported yet");
}
unsigned AMDGPURegisterInfo::getFrameRegister(const MachineFunction &MF) const {
index 21a2b0dd170f692e3dedf35a54e9e93936cec14a..8d71919704dff96b40a192c847ce534c909a591b 100644 (file)
HWFalse = DAG.getConstant(0, CompareVT);
}
else {
- assert(!"Unhandled value type in LowerSELECT_CC");
+ llvm_unreachable("Unhandled value type in LowerSELECT_CC");
}
// Lower this unsupported SELECT_CC into a combination of two supported
Ptr, DAG.getConstant(2, MVT::i32)));
if (StoreNode->isTruncatingStore() || StoreNode->isIndexed()) {
- assert(!"Truncated and indexed stores not supported yet");
+ llvm_unreachable("Truncated and indexed stores not supported yet");
} else {
Chain = DAG.getStore(Chain, DL, Value, Ptr, StoreNode->getMemOperand());
}
diff --git a/lib/Target/R600/R600OptimizeVectorRegisters.cpp b/lib/Target/R600/R600OptimizeVectorRegisters.cpp
index cf719c0b9fe12200aa031e1a2a3cbbc9dcedb627..8e0946ed2528100ca6c3f7adff1170dbea894ddf 100644 (file)
DenseMap<unsigned, unsigned> RegToChan;
std::vector<unsigned> UndefReg;
RegSeqInfo(MachineRegisterInfo &MRI, MachineInstr *MI) : Instr(MI) {
- assert (MI->getOpcode() == AMDGPU::REG_SEQUENCE);
+ assert(MI->getOpcode() == AMDGPU::REG_SEQUENCE);
for (unsigned i = 1, e = Instr->getNumOperands(); i < e; i+=2) {
MachineOperand &MO = Instr->getOperand(i);
unsigned Chan = Instr->getOperand(i + 1).getImm();
index 9c0feff375bba482aeb63e5ce91c8ae8a3b05e43..5240c48dd1667a732a5d44a290953992a1360cc6 100644 (file)
PhiInserter.AddAvailableValue(Parent, Ret);
} else {
- assert(0 && "Unhandled loop condition!");
+ llvm_unreachable("Unhandled loop condition!");
}
}
index 618deafbde521dc7d3f71c366f6b61d079ad613e..19bcf0cd946f7f62519ccaee381ee05c349944d4 100644 (file)
virtual MachineInstr *commuteInstruction(MachineInstr *MI,
bool NewMI=false) const;
- virtual unsigned getIEQOpcode() const { assert(!"Implement"); return 0;}
+ virtual unsigned getIEQOpcode() const {
+ llvm_unreachable("Unimplemented");
+ }
+
MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
MachineBasicBlock::iterator I,
unsigned DstReg, unsigned SrcReg) const;
index 958763dffc224b603fa6e14c140d07e8c0c1d4c7..8c12e1357f03defe180b19706808d9afb44c965d 100644 (file)
}
void SILowerControlFlowPass::Branch(MachineInstr &MI) {
- MachineBasicBlock *Next = MI.getParent()->getNextNode();
- MachineBasicBlock *Target = MI.getOperand(0).getMBB();
- if (Target == Next)
- MI.eraseFromParent();
- else
- assert(0);
+ assert(MI.getOperand(0).getMBB() == MI.getParent()->getNextNode());
+ MI.eraseFromParent();
}
void SILowerControlFlowPass::Kill(MachineInstr &MI) {
-
MachineBasicBlock &MBB = *MI.getParent();
DebugLoc DL = MI.getDebugLoc();