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raw | patch | inline | side by side (parent: 8ade909)
author | Ulrich Weigand <ulrich.weigand@de.ibm.com> | |
Fri, 26 Apr 2013 15:39:12 +0000 (15:39 +0000) | ||
committer | Ulrich Weigand <ulrich.weigand@de.ibm.com> | |
Fri, 26 Apr 2013 15:39:12 +0000 (15:39 +0000) |
When testing the asm parser, I noticed wrong encodings for the
above instructions (wrong operand name in rldimi, wrong form
and sub-opcode for rldcl).
Tests will be added together with the asm parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180606 91177308-0d34-0410-b5e6-96231b3b80d8
above instructions (wrong operand name in rldimi, wrong form
and sub-opcode for rldcl).
Tests will be added together with the asm parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180606 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/PowerPC/PPCInstr64Bit.td | patch | blob | history | |
lib/Target/PowerPC/PPCInstrFormats.td | patch | blob | history | |
lib/Target/PowerPC/PPCInstrInfo.td | patch | blob | history |
index 7f76751be4bb141ab5ce8fb7d6a29749d1af5b1d..5cc450c335c0e5bd8e4fc4ea94c53e14e012137f 100644 (file)
let neverHasSideEffects = 1 in {
let isCommutable = 1 in {
defm RLDIMI : MDForm_1r<30, 3, (outs G8RC:$rA),
- (ins G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB),
- "rldimi", "$rA, $rS, $SH, $MB", IntRotateDI,
+ (ins G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MBE),
+ "rldimi", "$rA, $rS, $SH, $MBE", IntRotateDI,
[]>, isPPC64, RegConstraint<"$rSi = $rA">,
NoEncode<"$rSi">;
}
// Rotate instructions.
-defm RLDCL : MDForm_1r<30, 0,
+defm RLDCL : MDSForm_1r<30, 8,
(outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB, u6imm:$MBE),
"rldcl", "$rA, $rS, $rB, $MBE", IntRotateD,
[]>, isPPC64;
index 36f193be993698c03e4773aa78f158550939526e..41b4e017e65c45a77cfef827dc9d869358e98d57 100644 (file)
let Inst{31} = RC;
}
+class MDSForm_1<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, string asmstr,
+ InstrItinClass itin, list<dag> pattern>
+ : I<opcode, OOL, IOL, asmstr, itin> {
+ bits<5> RA;
+ bits<5> RS;
+ bits<5> RB;
+ bits<6> MBE;
+
+ let Pattern = pattern;
+
+ bit RC = 0; // set by isDOT
+
+ let Inst{6-10} = RS;
+ let Inst{11-15} = RA;
+ let Inst{16-20} = RB;
+ let Inst{21-26} = MBE{4,3,2,1,0,5};
+ let Inst{27-30} = xo;
+ let Inst{31} = RC;
+}
// E-1 VA-Form
index a84d62dd7d9492d806cf49cebb9892bf3033ce0e..6d8ef6bb6a80847208b1173dc599efb368076ce4 100644 (file)
}
}
+multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
+ string asmbase, string asmstr, InstrItinClass itin,
+ list<dag> pattern> {
+ let BaseName = asmbase in {
+ def NAME : MDSForm_1<opcode, xo, OOL, IOL,
+ !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
+ pattern>, RecFormRel;
+ let Defs = [CR0] in
+ def o : MDSForm_1<opcode, xo, OOL, IOL,
+ !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
+ []>, isDOT, RecFormRel;
+ }
+}
+
multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
string asmbase, string asmstr, InstrItinClass itin,
list<dag> pattern> {