summary | shortlog | log | commit | commitdiff | tree
raw | patch | inline | side by side (parent: 8631a90)
raw | patch | inline | side by side (parent: 8631a90)
author | Dmitri Gribenko <gribozavr@gmail.com> | |
Mon, 10 Sep 2012 21:26:47 +0000 (21:26 +0000) | ||
committer | Dmitri Gribenko <gribozavr@gmail.com> | |
Mon, 10 Sep 2012 21:26:47 +0000 (21:26 +0000) |
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163547 91177308-0d34-0410-b5e6-96231b3b80d8
index 9b81772207fbdffa14a6afe414496ef56d970178..17f9d9e982176bfd6020ff2831c6ec801c029ffe 100644 (file)
// Compute the number of register mask instructions in this block.
std::pair<unsigned, unsigned> &RMB = RegMaskBlocks[MBB->getNumber()];
- RMB.second = RegMaskSlots.size() - RMB.first;;
+ RMB.second = RegMaskSlots.size() - RMB.first;
}
// Create empty intervals for registers defined by implicit_def's (except
RegMaskBits.push_back(MO->getRegMask());
}
// Compute the number of register mask instructions in this block.
- RMB.second = RegMaskSlots.size() - RMB.first;;
+ RMB.second = RegMaskSlots.size() - RMB.first;
}
}
index 927ecef17160ba8971397e156acf4bc6d520d049..dbfa4bb22bc7ed40f6fb8112ff077a089c841455 100644 (file)
FI != FE; ++FI) {
// Assign a serial number to this basic block.
- BasicBlocks[*FI] = BasicBlockNumbering.size();;
+ BasicBlocks[*FI] = BasicBlockNumbering.size();
BasicBlockNumbering.push_back(*FI);
BlockLiveness[*FI].Begin.resize(NumSlot);
index 9316bb1c1cdb5257732374eadda4a5d46a20c6ec..d55de1f3fbe82239f26adc9b5303e1216d17a571 100644 (file)
StringRef Name;
if (getParser().ParseIdentifier(Name))
return TokError("expected identifier in directive");
- MCSymbol *Sym = getContext().GetOrCreateSymbol(Name);;
+ MCSymbol *Sym = getContext().GetOrCreateSymbol(Name);
if (getLexer().isNot(AsmToken::Comma))
return TokError("unexpected token in directive");
diff --git a/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp b/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp
index a51e0fa3fbc53cca7eea301f74a95e8e969aec20..95640f7df951bfaf90ffeb40a1010a6bef614758 100644 (file)
if (Type == macho::RIT_ARM_Half) {
// The other-half value only gets populated for the movt and movw
// relocation entries.
- uint32_t Value = 0;;
+ uint32_t Value = 0;
switch ((unsigned)Fixup.getKind()) {
default: break;
case ARM::fixup_arm_movw_lo16:
index 8057f9811e593a5c3ca995b2a9a7000ef4094091..e780134033f7b5dafeb892161d98d5440c9fa49f 100644 (file)
case MipsSubtarget::N32: return "abiN32";
case MipsSubtarget::N64: return "abi64";
case MipsSubtarget::EABI: return "eabi32"; // TODO: handle eabi64
- default: llvm_unreachable("Unknown Mips ABI");;
+ default: llvm_unreachable("Unknown Mips ABI");
}
}
index 21791d5be9badba419451c9fb22f43bf5fdc4ebf..c353d9695d9c428951a39fefa19f80a48ef5d479 100644 (file)
LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
- return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);;
+ return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
}
// fall through
case MVT::v4i32: