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raw | patch | inline | side by side (parent: a9cc4e7)
raw | patch | inline | side by side (parent: a9cc4e7)
author | Aditya Nandakumar <aditya_nandakumar@apple.com> | |
Thu, 13 Nov 2014 21:29:21 +0000 (21:29 +0000) | ||
committer | Aditya Nandakumar <aditya_nandakumar@apple.com> | |
Thu, 13 Nov 2014 21:29:21 +0000 (21:29 +0000) |
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221926 91177308-0d34-0410-b5e6-96231b3b80d8
15 files changed:
index 09b46626bfd13776c8a61cd69f3f4016033386ba..882dab40e4199096d9a9536b2488a007bb5272c4 100644 (file)
}
/// NOTE: The TargetMachine owns TLOF.
- explicit TargetLoweringBase(const TargetMachine &TM,
- const TargetLoweringObjectFile *TLOF);
+ explicit TargetLoweringBase(const TargetMachine &TM);
virtual ~TargetLoweringBase() {}
protected:
public:
const TargetMachine &getTargetMachine() const { return TM; }
const DataLayout *getDataLayout() const { return DL; }
- const TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; }
+ const TargetLoweringObjectFile &getObjFileLowering() const {
+ return *TM.getObjFileLowering();
+ }
bool isBigEndian() const { return !IsLittleEndian; }
bool isLittleEndian() const { return IsLittleEndian; }
private:
const TargetMachine &TM;
const DataLayout *DL;
- const TargetLoweringObjectFile &TLOF;
/// True if this is a little endian target.
bool IsLittleEndian;
void operator=(const TargetLowering&) LLVM_DELETED_FUNCTION;
public:
- /// NOTE: The constructor takes ownership of TLOF.
- explicit TargetLowering(const TargetMachine &TM,
- const TargetLoweringObjectFile *TLOF);
+ /// NOTE: The TargetMachine owns TLOF.
+ explicit TargetLowering(const TargetMachine &TM);
/// Returns true by value, base pointer and offset pointer and addressing mode
/// by reference if the node's address can be legally represented as
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 4fbe672f3e754a14ac8b0cf5035ebf273915d65e..9aef5edcd54f60ad7f3abec158b37878751aad8f 100644 (file)
#include <cctype>
using namespace llvm;
-/// NOTE: The constructor takes ownership of TLOF.
-TargetLowering::TargetLowering(const TargetMachine &tm,
- const TargetLoweringObjectFile *tlof)
- : TargetLoweringBase(tm, tlof) {}
+/// NOTE: The TargetMachine owns TLOF.
+TargetLowering::TargetLowering(const TargetMachine &tm)
+ : TargetLoweringBase(tm) {}
const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
return nullptr;
index 6d499e3489ac5803fd1107bc9ca73cfc0a5a0718..ffb875981fe85a5927a68f338ea5b0cbd3d4156f 100644 (file)
CCs[RTLIB::O_F128] = ISD::SETEQ;
}
-/// NOTE: The constructor takes ownership of TLOF.
-TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm,
- const TargetLoweringObjectFile *tlof)
- : TM(tm), DL(TM.getSubtargetImpl()->getDataLayout()), TLOF(*tlof) {
+/// NOTE: The TargetMachine owns TLOF.
+TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm)
+ : TM(tm), DL(TM.getSubtargetImpl()->getDataLayout()) {
initActions();
// Perform these initializations only once.
diff --git a/lib/Target/AArch64/AArch64ISelLowering.cpp b/lib/Target/AArch64/AArch64ISelLowering.cpp
index b600cb07bf18ff38139bd149d42c3afd7a39ecc3..04ea60c51b078e46352798f21f3df0b918a00b9a 100644 (file)
AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM)
- : TargetLowering(TM, TM.getObjFileLowering()) {
+ : TargetLowering(TM) {
Subtarget = &TM.getSubtarget<AArch64Subtarget>();
// AArch64 doesn't have comparisons which set GPRs or setcc instructions, so
index 337ceefc9bebb19caff30fb31ce98b624b2428a0..a7a6ddd0b751401daafde5b9b0a30c3aa0ff864b 100644 (file)
}
ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM)
- : TargetLowering(TM, TM.getObjFileLowering()) {
+ : TargetLowering(TM) {
Subtarget = &TM.getSubtarget<ARMSubtarget>();
RegInfo = TM.getSubtargetImpl()->getRegisterInfo();
Itins = TM.getSubtargetImpl()->getInstrItineraryData();
diff --git a/lib/Target/Hexagon/HexagonISelLowering.cpp b/lib/Target/Hexagon/HexagonISelLowering.cpp
index 03791a1784e68e95318d3b849b90645a415ce2cc..764608857b82361cc828146ebce513e9b0b4e166 100644 (file)
@@ -1043,7 +1043,7 @@ HexagonTargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
//===----------------------------------------------------------------------===//
HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &targetmachine)
- : TargetLowering(targetmachine, targetmachine.getObjFileLowering()),
+ : TargetLowering(targetmachine),
TM(targetmachine) {
const HexagonSubtarget &Subtarget = TM.getSubtarget<HexagonSubtarget>();
index 216ffb132e6f7c06f55db7e11650b54d34dcf6e7..22936dd5e4fd218745eb9be2971417dee4af6801 100644 (file)
clEnumValEnd));
MSP430TargetLowering::MSP430TargetLowering(const TargetMachine &TM)
- : TargetLowering(TM, TM.getObjFileLowering()) {
+ : TargetLowering(TM) {
// Set up the register classes.
addRegisterClass(MVT::i8, &MSP430::GR8RegClass);
index 4fb2f781c9add3639873bd8f95e023d6f7e321dd..a7117adbdeb355905e971bec848b6f1eb6a3b44d 100644 (file)
MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
const MipsSubtarget &STI)
- : TargetLowering(TM, TM.getObjFileLowering()), Subtarget(STI) {
+ : TargetLowering(TM), Subtarget(STI) {
// Mips does not have i1 type, so use i32 for
// setcc operations results (slt, sgt, ...).
setBooleanContents(ZeroOrOneBooleanContent);
index 55c97375afec953f3f7dd08d839155b1b5e81d4a..0b0b5366886df4c3cc9f00c3152d7f717e88cd8a 100644 (file)
// NVPTXTargetLowering Constructor.
NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM)
- : TargetLowering(TM, TM.getObjFileLowering()), nvTM(&TM),
+ : TargetLowering(TM), nvTM(&TM),
nvptxSubtarget(TM.getSubtarget<NVPTXSubtarget>()) {
// always lower memset, memcpy, and memmove intrinsics to load/store
index 38656df9998133fc40dea00f117ece74b6d63ddc..e8e4da57de98b21a12cb776da2f4067fcf3a96d9 100644 (file)
extern cl::opt<bool> ANDIGlueBug;
PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM)
- : TargetLowering(TM, TM.getObjFileLowering()),
+ : TargetLowering(TM),
Subtarget(*TM.getSubtargetImpl()) {
setPow2SDivIsCheap();
index 81192b7014d53367f7887f0a343fc62d043f1949..5561bf8976c2352b99cdbb57b6184e5e3a53ac26 100644 (file)
}
AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
- TargetLowering(TM, TM.getObjFileLowering()) {
+ TargetLowering(TM) {
Subtarget = &TM.getSubtarget<AMDGPUSubtarget>();
index c7356cb59fecb1d37aefb96e5a00f1f21f2c2f3e..e6a69d2cd3fad0b430f49ee5469a01052b8da509 100644 (file)
}
SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
- : TargetLowering(TM, TM.getObjFileLowering()) {
+ : TargetLowering(TM) {
Subtarget = &TM.getSubtarget<SparcSubtarget>();
// Set up the register classes.
diff --git a/lib/Target/SystemZ/SystemZISelLowering.cpp b/lib/Target/SystemZ/SystemZISelLowering.cpp
index 2df36770d50b0b53192e4d5addf105d6969e6ba0..b282fca14da9e5ee1ff59a0b7051703513b0da2c 100644 (file)
}
SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &tm)
- : TargetLowering(tm, tm.getObjFileLowering()),
+ : TargetLowering(tm),
Subtarget(tm.getSubtarget<SystemZSubtarget>()) {
MVT PtrVT = getPointerTy();
index 47c8ce0329635c4e3b4b55d1f202aa2abf46b37e..92cbbe68a28fd9398ef4bb3039d414d1660fe816 100644 (file)
// FIXME: This should stop caching the target machine as soon as
// we can remove resetOperationActions et al.
X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM)
- : TargetLowering(TM, TM.getObjFileLowering()) {
+ : TargetLowering(TM) {
Subtarget = &TM.getSubtarget<X86Subtarget>();
X86ScalarSSEf64 = Subtarget->hasSSE2();
X86ScalarSSEf32 = Subtarget->hasSSE1();
index 5aff27bfe4b3617cd52e92266420a59d9652f3b9..96c43ae8ba9c3eaf2c67c0e9e99c8880d36407ee 100644 (file)
}
XCoreTargetLowering::XCoreTargetLowering(const TargetMachine &TM)
- : TargetLowering(TM, TM.getObjFileLowering()), TM(TM),
+ : TargetLowering(TM), TM(TM),
Subtarget(TM.getSubtarget<XCoreSubtarget>()) {
// Set up the register classes.