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raw | patch | inline | side by side (parent: 29e068b)
raw | patch | inline | side by side (parent: 29e068b)
author | Aaron Ballman <aaron@aaronballman.com> | |
Mon, 19 May 2014 14:29:04 +0000 (14:29 +0000) | ||
committer | Aaron Ballman <aaron@aaronballman.com> | |
Mon, 19 May 2014 14:29:04 +0000 (14:29 +0000) |
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209126 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/ARM64/ARM64InstrInfo.cpp | patch | blob | history | |
lib/Target/R600/AMDGPUMCInstLower.cpp | patch | blob | history |
index 75d906d9da0f8260095f153661af4b0f4e50a1e9..e4112655f8dbdc0bf0b6cb8d6d82a81b451c1380 100644 (file)
/// Return true if this is this instruction has a non-zero immediate
bool ARM64InstrInfo::hasNonZeroImm(const MachineInstr *MI) const {
- switch (MI->getOpcode()) {
- default:
- if (MI->getOperand(3).isImm()) {
- unsigned val = MI->getOperand(3).getImm();
- return (val != 0);
- }
- break;
+ if (MI->getOperand(3).isImm()) {
+ unsigned val = MI->getOperand(3).getImm();
+ return (val != 0);
}
+
return false;
}
index 66d107432163a7b7cd263ab0c1b6944deadcd4bb..b759495ad8e2a5fae5fe7fce5b3281fd6bc727a3 100644 (file)
{ }
enum AMDGPUMCInstLower::SISubtarget
-AMDGPUMCInstLower::AMDGPUSubtargetToSISubtarget(unsigned Gen) const {
- switch (Gen) {
- default: return AMDGPUMCInstLower::SI;
- }
+AMDGPUMCInstLower::AMDGPUSubtargetToSISubtarget(unsigned) const {
+ return AMDGPUMCInstLower::SI;
}
unsigned AMDGPUMCInstLower::getMCOpcode(unsigned MIOpcode) const {