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author | Adam Nemet <anemet@apple.com> | |
Thu, 2 Oct 2014 23:18:30 +0000 (23:18 +0000) | ||
committer | Adam Nemet <anemet@apple.com> | |
Thu, 2 Oct 2014 23:18:30 +0000 (23:18 +0000) |
No functional change intended.
Very similar to the change I made for subvector extract in r218480.
test/CodeGen/X86/avx512-insert-extract.ll covers this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218928 91177308-0d34-0410-b5e6-96231b3b80d8
Very similar to the change I made for subvector extract in r218480.
test/CodeGen/X86/avx512-insert-extract.ll covers this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218928 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/X86/X86InstrAVX512.td | patch | blob | history |
index f3c87ccc8ebf7d65350605eeb9e6b3a8582253a8..10055d065dc4cee8e22c9bfea09edb1fc26d014c 100644 (file)
(ins VR512:$src1, From.RC:$src2, i8imm:$src3),
"vinsert" # From.EltTypeName # "x4\t{$src3, $src2, $src1, $dst|"
"$dst, $src1, $src2, $src3}",
- []>, EVEX_4V, EVEX_V512;
+ [(set To.RC:$dst, (vinsert_insert:$src3 (To.VT VR512:$src1),
+ (From.VT From.RC:$src2),
+ (iPTR imm)))]>,
+ EVEX_4V, EVEX_V512;
let mayLoad = 1 in
def rm : AVX512AIi8<Opcode, MRMSrcMem, (outs VR512:$dst),
[]>, EVEX_4V, EVEX_V512, EVEX_CD8<From.EltSize, CD8VT4>;
}
- // Codegen pattern, e.g. v4i32 -> v16i32 for vinserti32x4
- def : Pat<(vinsert_insert:$ins
- (To.VT VR512:$src1), (From.VT From.RC:$src2), (iPTR imm)),
- (To.VT (!cast<Instruction>(NAME # From.EltSize # "x4rr")
- VR512:$src1, From.RC:$src2,
- (INSERT_get_vinsert_imm VR512:$ins)))>;
-
// Codegen pattern with the alternative types, e.g. v2i64 -> v8i64 for
// vinserti32x4
def : Pat<(vinsert_insert:$ins