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raw | patch | inline | side by side (parent: 2f5f1c2)
author | Matt Arsenault <Matthew.Arsenault@amd.com> | |
Mon, 12 May 2014 19:23:21 +0000 (19:23 +0000) | ||
committer | Matt Arsenault <Matthew.Arsenault@amd.com> | |
Mon, 12 May 2014 19:23:21 +0000 (19:23 +0000) |
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208617 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/R600/R600ISelLowering.cpp | patch | blob | history | |
lib/Target/R600/SIRegisterInfo.cpp | patch | blob | history |
index e3bcab02e3fb4a45ec3336e43b4efd60fc1ba0a8..1ead0b19c24ae0279c91612877d4ab7fa1b8937f 100644 (file)
TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_W)
};
std::vector<unsigned> Consts;
- for (unsigned i = 0; i < sizeof(SrcIndices) / sizeof(int); i++) {
- int OtherSrcIdx = SrcIndices[i];
+ for (int OtherSrcIdx : SrcIndices) {
int OtherSelIdx = TII->getSelIdx(Opcode, OtherSrcIdx);
if (OtherSrcIdx < 0 || OtherSelIdx < 0)
continue;
index 8dc9a05799c37a40805b2c187f3c905bccc6564e..c72d549a3dd1beacc4a9440b55c2ba1afcbc7238 100644 (file)
&AMDGPU::SReg_256RegClass
};
- for (unsigned i = 0, e = sizeof(BaseClasses) /
- sizeof(const TargetRegisterClass*); i != e; ++i) {
- if (BaseClasses[i]->contains(Reg)) {
- return BaseClasses[i];
+ for (const TargetRegisterClass *BaseClass : BaseClasses) {
+ if (BaseClass->contains(Reg)) {
+ return BaseClass;
}
}
return nullptr;