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raw | patch | inline | side by side (parent: 0ad7f9b)
raw | patch | inline | side by side (parent: 0ad7f9b)
| author | Owen Anderson <resistor@mac.com> | |
| Tue, 11 Aug 2009 20:47:22 +0000 (20:47 +0000) | ||
| committer | Owen Anderson <resistor@mac.com> | |
| Tue, 11 Aug 2009 20:47:22 +0000 (20:47 +0000) |
the latter is capable of representing either a primitive or an extended type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78713 91177308-0d34-0410-b5e6-96231b3b80d8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78713 91177308-0d34-0410-b5e6-96231b3b80d8
86 files changed:
index d0a24ebc7851fffffcd1a0dd2a91503db22df685..b2acbc174559c7a4eca81fcf080ef11818988b9f 100644 (file)
return false;
if (Chain->getNumOperands() > 0) {
SDValue C0 = Chain->getOperand(0);
- if (C0.getValueType() == EVT::Other)
+ if (C0.getValueType() == MVT::Other)
return C0.getNode() != Op && IsChainCompatible(C0.getNode(), Op);
}
return true;
index b159dd970cbdabd82a221feb4ed4547e5e47d935..b2cc94db4e58dc24b112f8df40907cb010db113a 100644 (file)
/// FastEmit_r - This method is called by target-independent code
/// to request that an instruction with the given type and opcode
/// be emitted.
- virtual unsigned FastEmit_(EVT::SimpleValueType VT,
- EVT::SimpleValueType RetVT,
+ virtual unsigned FastEmit_(MVT VT,
+ MVT RetVT,
ISD::NodeType Opcode);
/// FastEmit_r - This method is called by target-independent code
/// to request that an instruction with the given type, opcode, and
/// register operand be emitted.
///
- virtual unsigned FastEmit_r(EVT::SimpleValueType VT,
- EVT::SimpleValueType RetVT,
+ virtual unsigned FastEmit_r(MVT VT,
+ MVT RetVT,
ISD::NodeType Opcode, unsigned Op0);
/// FastEmit_rr - This method is called by target-independent code
/// to request that an instruction with the given type, opcode, and
/// register operands be emitted.
///
- virtual unsigned FastEmit_rr(EVT::SimpleValueType VT,
- EVT::SimpleValueType RetVT,
+ virtual unsigned FastEmit_rr(MVT VT,
+ MVT RetVT,
ISD::NodeType Opcode,
unsigned Op0, unsigned Op1);
/// to request that an instruction with the given type, opcode, and
/// register and immediate operands be emitted.
///
- virtual unsigned FastEmit_ri(EVT::SimpleValueType VT,
- EVT::SimpleValueType RetVT,
+ virtual unsigned FastEmit_ri(MVT VT,
+ MVT RetVT,
ISD::NodeType Opcode,
unsigned Op0, uint64_t Imm);
/// to request that an instruction with the given type, opcode, and
/// register and floating-point immediate operands be emitted.
///
- virtual unsigned FastEmit_rf(EVT::SimpleValueType VT,
- EVT::SimpleValueType RetVT,
+ virtual unsigned FastEmit_rf(MVT VT,
+ MVT RetVT,
ISD::NodeType Opcode,
unsigned Op0, ConstantFP *FPImm);
/// to request that an instruction with the given type, opcode, and
/// register and immediate operands be emitted.
///
- virtual unsigned FastEmit_rri(EVT::SimpleValueType VT,
- EVT::SimpleValueType RetVT,
+ virtual unsigned FastEmit_rri(MVT VT,
+ MVT RetVT,
ISD::NodeType Opcode,
unsigned Op0, unsigned Op1, uint64_t Imm);
/// to emit an instruction with an immediate operand using FastEmit_ri.
/// If that fails, it materializes the immediate into a register and try
/// FastEmit_rr instead.
- unsigned FastEmit_ri_(EVT::SimpleValueType VT,
+ unsigned FastEmit_ri_(MVT VT,
ISD::NodeType Opcode,
unsigned Op0, uint64_t Imm,
- EVT::SimpleValueType ImmType);
+ MVT ImmType);
/// FastEmit_rf_ - This method is a wrapper of FastEmit_rf. It first tries
/// to emit an instruction with an immediate operand using FastEmit_rf.
/// If that fails, it materializes the immediate into a register and try
/// FastEmit_rr instead.
- unsigned FastEmit_rf_(EVT::SimpleValueType VT,
+ unsigned FastEmit_rf_(MVT VT,
ISD::NodeType Opcode,
unsigned Op0, ConstantFP *FPImm,
- EVT::SimpleValueType ImmType);
+ MVT ImmType);
/// FastEmit_i - This method is called by target-independent code
/// to request that an instruction with the given type, opcode, and
/// immediate operand be emitted.
- virtual unsigned FastEmit_i(EVT::SimpleValueType VT,
- EVT::SimpleValueType RetVT,
+ virtual unsigned FastEmit_i(MVT VT,
+ MVT RetVT,
ISD::NodeType Opcode,
uint64_t Imm);
/// FastEmit_f - This method is called by target-independent code
/// to request that an instruction with the given type, opcode, and
/// floating-point immediate operand be emitted.
- virtual unsigned FastEmit_f(EVT::SimpleValueType VT,
- EVT::SimpleValueType RetVT,
+ virtual unsigned FastEmit_f(MVT VT,
+ MVT RetVT,
ISD::NodeType Opcode,
ConstantFP *FPImm);
/// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg
/// from a specified index of a superregister to a specified type.
- unsigned FastEmitInst_extractsubreg(EVT::SimpleValueType RetVT,
+ unsigned FastEmitInst_extractsubreg(MVT RetVT,
unsigned Op0, uint32_t Idx);
/// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
/// with all but the least significant bit set to zero.
- unsigned FastEmitZExtFromI1(EVT::SimpleValueType VT,
+ unsigned FastEmitZExtFromI1(MVT VT,
unsigned Op);
/// FastEmitBranch - Emit an unconditional branch to the given block,
index 73b88951273f5f91baa56381d2b80f1d3a49a3d7..47df8672f4747454f138e28c95ead9f1634e5b14 100644 (file)
/// setRoot - Set the current root tag of the SelectionDAG.
///
const SDValue &setRoot(SDValue N) {
- assert((!N.getNode() || N.getValueType() == EVT::Other) &&
+ assert((!N.getNode() || N.getValueType() == MVT::Other) &&
"DAG root value is not a chain!");
return Root = N;
}
unsigned LabelID);
SDValue getCopyToReg(SDValue Chain, DebugLoc dl, unsigned Reg, SDValue N) {
- return getNode(ISD::CopyToReg, dl, EVT::Other, Chain,
+ return getNode(ISD::CopyToReg, dl, MVT::Other, Chain,
getRegister(Reg, N.getValueType()), N);
}
// null) and that there should be a flag result.
SDValue getCopyToReg(SDValue Chain, DebugLoc dl, unsigned Reg, SDValue N,
SDValue Flag) {
- SDVTList VTs = getVTList(EVT::Other, EVT::Flag);
+ SDVTList VTs = getVTList(MVT::Other, MVT::Flag);
SDValue Ops[] = { Chain, getRegister(Reg, N.getValueType()), N, Flag };
return getNode(ISD::CopyToReg, dl, VTs, Ops, Flag.getNode() ? 4 : 3);
}
// Similar to last getCopyToReg() except parameter Reg is a SDValue
SDValue getCopyToReg(SDValue Chain, DebugLoc dl, SDValue Reg, SDValue N,
SDValue Flag) {
- SDVTList VTs = getVTList(EVT::Other, EVT::Flag);
+ SDVTList VTs = getVTList(MVT::Other, MVT::Flag);
SDValue Ops[] = { Chain, Reg, N, Flag };
return getNode(ISD::CopyToReg, dl, VTs, Ops, Flag.getNode() ? 4 : 3);
}
SDValue getCopyFromReg(SDValue Chain, DebugLoc dl, unsigned Reg, EVT VT) {
- SDVTList VTs = getVTList(VT, EVT::Other);
+ SDVTList VTs = getVTList(VT, MVT::Other);
SDValue Ops[] = { Chain, getRegister(Reg, VT) };
return getNode(ISD::CopyFromReg, dl, VTs, Ops, 2);
}
// null) and that there should be a flag result.
SDValue getCopyFromReg(SDValue Chain, DebugLoc dl, unsigned Reg, EVT VT,
SDValue Flag) {
- SDVTList VTs = getVTList(VT, EVT::Other, EVT::Flag);
+ SDVTList VTs = getVTList(VT, MVT::Other, MVT::Flag);
SDValue Ops[] = { Chain, getRegister(Reg, VT), Flag };
return getNode(ISD::CopyFromReg, dl, VTs, Ops, Flag.getNode() ? 3 : 2);
}
/// a flag result (to ensure it's not CSE'd). CALLSEQ_START does not have a
/// useful DebugLoc.
SDValue getCALLSEQ_START(SDValue Chain, SDValue Op) {
- SDVTList VTs = getVTList(EVT::Other, EVT::Flag);
+ SDVTList VTs = getVTList(MVT::Other, MVT::Flag);
SDValue Ops[] = { Chain, Op };
return getNode(ISD::CALLSEQ_START, DebugLoc::getUnknownLoc(),
VTs, Ops, 2);
/// a useful DebugLoc.
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2,
SDValue InFlag) {
- SDVTList NodeTys = getVTList(EVT::Other, EVT::Flag);
+ SDVTList NodeTys = getVTList(MVT::Other, MVT::Flag);
SmallVector<SDValue, 4> Ops;
Ops.push_back(Chain);
Ops.push_back(Op1);
index 7229463d4e5eb1c2c8714a14408d671a4181fbc2..f1a5e2e69ebfea88d5612d55f27117c3c18210b5 100644 (file)
/// to which the flag operand points. Otherwise return NULL.
SDNode *getFlaggedNode() const {
if (getNumOperands() != 0 &&
- getOperand(getNumOperands()-1).getValueType() == EVT::Flag)
+ getOperand(getNumOperands()-1).getValueType().getSimpleVT() == MVT::Flag)
return getOperand(getNumOperands()-1).getNode();
return 0;
}
return ValueList[ResNo];
}
- /// getValueSizeInBits - Returns EVT::getSizeInBits(getValueType(ResNo)).
+ /// getValueSizeInBits - Returns MVT::getSizeInBits(getValueType(ResNo)).
///
unsigned getValueSizeInBits(unsigned ResNo) const {
return getValueType(ResNo).getSizeInBits();
explicit HandleSDNode(SDValue X)
#endif
: SDNode(ISD::HANDLENODE, DebugLoc::getUnknownLoc(),
- getSDVTList(EVT::Other)) {
+ getSDVTList(MVT::Other)) {
InitOperands(&Op, X);
}
~HandleSDNode();
/// harder. Let's see if we need it first.
explicit BasicBlockSDNode(MachineBasicBlock *mbb)
: SDNode(ISD::BasicBlock, DebugLoc::getUnknownLoc(),
- getSDVTList(EVT::Other)), MBB(mbb) {
+ getSDVTList(MVT::Other)), MBB(mbb) {
}
public:
/// Create a SrcValue for a general value.
explicit SrcValueSDNode(const Value *v)
: SDNode(ISD::SRCVALUE, DebugLoc::getUnknownLoc(),
- getSDVTList(EVT::Other)), V(v) {}
+ getSDVTList(MVT::Other)), V(v) {}
public:
/// getValue - return the contained Value.
/// Create a MachineMemOperand node
explicit MemOperandSDNode(const MachineMemOperand &mo)
: SDNode(ISD::MEMOPERAND, DebugLoc::getUnknownLoc(),
- getSDVTList(EVT::Other)), MO(mo) {}
+ getSDVTList(MVT::Other)), MO(mo) {}
public:
/// MO - The contained MachineMemOperand.
DbgStopPointSDNode(SDValue ch, unsigned l, unsigned c,
Value *cu)
: SDNode(ISD::DBG_STOPPOINT, DebugLoc::getUnknownLoc(),
- getSDVTList(EVT::Other)), Line(l), Column(c), CU(cu) {
+ getSDVTList(MVT::Other)), Line(l), Column(c), CU(cu) {
InitOperands(&Chain, ch);
}
public:
unsigned LabelID;
friend class SelectionDAG;
LabelSDNode(unsigned NodeTy, DebugLoc dl, SDValue ch, unsigned id)
- : SDNode(NodeTy, dl, getSDVTList(EVT::Other)), LabelID(id) {
+ : SDNode(NodeTy, dl, getSDVTList(MVT::Other)), LabelID(id) {
InitOperands(&Chain, ch);
}
public:
friend class SelectionDAG;
explicit CondCodeSDNode(ISD::CondCode Cond)
: SDNode(ISD::CONDCODE, DebugLoc::getUnknownLoc(),
- getSDVTList(EVT::Other)), Condition(Cond) {
+ getSDVTList(MVT::Other)), Condition(Cond) {
}
public:
EVT VT;
bool Used;
- InputArg() : VT(EVT::Other), Used(false) {}
+ InputArg() : VT(MVT::Other), Used(false) {}
InputArg(ISD::ArgFlagsTy flags, EVT vt, bool used)
: Flags(flags), VT(vt), Used(used) {
assert(VT.isSimple() &&
friend class SelectionDAG;
explicit VTSDNode(EVT VT)
: SDNode(ISD::VALUETYPE, DebugLoc::getUnknownLoc(),
- getSDVTList(EVT::Other)), ValueType(VT) {
+ getSDVTList(MVT::Other)), ValueType(VT) {
}
public:
index 2427f99b971dfdb3ca291304a8a32ea0e5cbbfe2..3767c1930b7e7479f0d7622625ea9651eebae0fe 100644 (file)
namespace llvm {
class Type;
class LLVMContext;
+ struct EVT;
- struct EVT { // EVT = Machine Value Type
- public:
+ struct MVT { // MVT = Machine Value Type
enum SimpleValueType {
// If you change this numbering, you must change the values in
// ValueTypes.td as well!
LastSimpleValueType = 255
};
- private:
- /// This union holds low-level value types. Valid values include any of
- /// the values in the SimpleValueType enum, or any value returned from one
- /// of the EVT methods. Any value type equal to one of the SimpleValueType
- /// enum values is a "simple" value type. All others are "extended".
- ///
- /// Note that simple doesn't necessary mean legal for the target machine.
- /// All legal value types must be simple, but often there are some simple
- /// value types that are not legal.
- ///
- union {
- uintptr_t V;
- const Type *LLVMTy;
- };
+ SimpleValueType SimpleTy;
+
+ MVT() : SimpleTy((SimpleValueType)(LastSimpleValueType+1)) {}
+ MVT(SimpleValueType SVT) : SimpleTy(SVT) { }
+
+ bool operator>(const MVT& S) const { return SimpleTy > S.SimpleTy; }
+ bool operator<(const MVT& S) const { return SimpleTy < S.SimpleTy; }
+ bool operator==(const MVT& S) const { return SimpleTy == S.SimpleTy; }
+ bool operator>=(const MVT& S) const { return SimpleTy >= S.SimpleTy; }
+ bool operator<=(const MVT& S) const { return SimpleTy <= S.SimpleTy; }
+
+ /// isFloatingPoint - Return true if this is a FP, or a vector FP type.
+ bool isFloatingPoint() const {
+ return ((SimpleTy >= MVT::f32 && SimpleTy <= MVT::ppcf128) ||
+ (SimpleTy >= MVT::v2f32 && SimpleTy <= MVT::v4f64));
+ }
- public:
- EVT() {}
- EVT(SimpleValueType S) : V(S) {}
+ /// isInteger - Return true if this is an integer, or a vector integer type.
+ bool isInteger() const {
+ return ((SimpleTy >= MVT::FIRST_INTEGER_VALUETYPE &&
+ SimpleTy <= MVT::LAST_INTEGER_VALUETYPE) ||
+ (SimpleTy >= MVT::v2i8 && SimpleTy <= MVT::v4i64));
+ }
- bool operator==(const EVT VT) const {
- return getRawBits() == VT.getRawBits();
+ /// isVector - Return true if this is a vector value type.
+ bool isVector() const {
+ return (SimpleTy >= MVT::FIRST_VECTOR_VALUETYPE &&
+ SimpleTy <= MVT::LAST_VECTOR_VALUETYPE);
}
- bool operator!=(const EVT VT) const {
- return getRawBits() != VT.getRawBits();
+
+ MVT getVectorElementType() const {
+ switch (SimpleTy) {
+ default:
+ return (MVT::SimpleValueType)(MVT::LastSimpleValueType+1);
+ case v2i8 :
+ case v4i8 :
+ case v8i8 :
+ case v16i8:
+ case v32i8: return i8;
+ case v2i16:
+ case v4i16:
+ case v8i16:
+ case v16i16: return i16;
+ case v2i32:
+ case v4i32:
+ case v8i32: return i32;
+ case v1i64:
+ case v2i64:
+ case v4i64: return i64;
+ case v2f32:
+ case v4f32:
+ case v8f32: return f32;
+ case v2f64:
+ case v4f64: return f64;
+ }
}
-
- /// getFloatingPointVT - Returns the EVT that represents a floating point
- /// type with the given number of bits. There are two floating point types
- /// with 128 bits - this returns f128 rather than ppcf128.
- static EVT getFloatingPointVT(unsigned BitWidth) {
+
+ unsigned getVectorNumElements() const {
+ switch (SimpleTy) {
+ default:
+ return ~0U;
+ case v32i8: return 32;
+ case v16i8:
+ case v16i16: return 16;
+ case v8i8 :
+ case v8i16:
+ case v8i32:
+ case v8f32: return 8;
+ case v4i8:
+ case v4i16:
+ case v4i32:
+ case v4i64:
+ case v4f32:
+ case v4f64: return 4;
+ case v2i8:
+ case v2i16:
+ case v2i32:
+ case v2i64:
+ case v2f32:
+ case v2f64: return 2;
+ case v1i64: return 1;
+ }
+ }
+
+ unsigned getSizeInBits() const {
+ switch (SimpleTy) {
+ case iPTR:
+ assert(0 && "Value type size is target-dependent. Ask TLI.");
+ case iPTRAny:
+ case iAny:
+ case fAny:
+ assert(0 && "Value type is overloaded.");
+ default:
+ assert(0 && "getSizeInBits called on extended MVT.");
+ case i1 : return 1;
+ case i8 : return 8;
+ case i16 :
+ case v2i8: return 16;
+ case f32 :
+ case i32 :
+ case v4i8:
+ case v2i16: return 32;
+ case f64 :
+ case i64 :
+ case v8i8:
+ case v4i16:
+ case v2i32:
+ case v1i64:
+ case v2f32: return 64;
+ case f80 : return 80;
+ case f128:
+ case ppcf128:
+ case i128:
+ case v16i8:
+ case v8i16:
+ case v4i32:
+ case v2i64:
+ case v4f32:
+ case v2f64: return 128;
+ case v32i8:
+ case v16i16:
+ case v8i32:
+ case v4i64:
+ case v8f32:
+ case v4f64: return 256;
+ }
+ }
+
+ static MVT getFloatingPointVT(unsigned BitWidth) {
switch (BitWidth) {
default:
assert(false && "Bad bit width!");
case 32:
- return f32;
+ return MVT::f32;
case 64:
- return f64;
+ return MVT::f64;
case 80:
- return f80;
+ return MVT::f80;
case 128:
- return f128;
+ return MVT::f128;
}
}
-
- /// getIntegerVT - Returns the EVT that represents an integer with the given
- /// number of bits.
- static EVT getIntegerVT(unsigned BitWidth) {
+
+ static MVT getIntegerVT(unsigned BitWidth) {
switch (BitWidth) {
default:
- break;
+ return (MVT::SimpleValueType)(MVT::LastSimpleValueType+1);
case 1:
- return i1;
+ return MVT::i1;
case 8:
- return i8;
+ return MVT::i8;
case 16:
- return i16;
+ return MVT::i16;
case 32:
- return i32;
+ return MVT::i32;
case 64:
- return i64;
+ return MVT::i64;
case 128:
- return i128;
+ return MVT::i128;
}
- return getExtendedIntegerVT(BitWidth);
}
-
- /// getVectorVT - Returns the EVT that represents a vector NumElements in
- /// length, where each element is of type VT.
- static EVT getVectorVT(EVT VT, unsigned NumElements) {
- switch (VT.V) {
+
+ static MVT getVectorVT(MVT VT, unsigned NumElements) {
+ switch (VT.SimpleTy) {
default:
break;
- case i8:
- if (NumElements == 2) return v2i8;
- if (NumElements == 4) return v4i8;
- if (NumElements == 8) return v8i8;
- if (NumElements == 16) return v16i8;
- if (NumElements == 32) return v32i8;
+ case MVT::i8:
+ if (NumElements == 2) return MVT::v2i8;
+ if (NumElements == 4) return MVT::v4i8;
+ if (NumElements == 8) return MVT::v8i8;
+ if (NumElements == 16) return MVT::v16i8;
+ if (NumElements == 32) return MVT::v32i8;
break;
- case i16:
- if (NumElements == 2) return v2i16;
- if (NumElements == 4) return v4i16;
- if (NumElements == 8) return v8i16;
- if (NumElements == 16) return v16i16;
+ case MVT::i16:
+ if (NumElements == 2) return MVT::v2i16;
+ if (NumElements == 4) return MVT::v4i16;
+ if (NumElements == 8) return MVT::v8i16;
+ if (NumElements == 16) return MVT::v16i16;
break;
- case i32:
- if (NumElements == 2) return v2i32;
- if (NumElements == 4) return v4i32;
- if (NumElements == 8) return v8i32;
+ case MVT::i32:
+ if (NumElements == 2) return MVT::v2i32;
+ if (NumElements == 4) return MVT::v4i32;
+ if (NumElements == 8) return MVT::v8i32;
break;
- case i64:
- if (NumElements == 1) return v1i64;
- if (NumElements == 2) return v2i64;
- if (NumElements == 4) return v4i64;
+ case MVT::i64:
+ if (NumElements == 1) return MVT::v1i64;
+ if (NumElements == 2) return MVT::v2i64;
+ if (NumElements == 4) return MVT::v4i64;
break;
- case f32:
- if (NumElements == 2) return v2f32;
- if (NumElements == 4) return v4f32;
- if (NumElements == 8) return v8f32;
+ case MVT::f32:
+ if (NumElements == 2) return MVT::v2f32;
+ if (NumElements == 4) return MVT::v4f32;
+ if (NumElements == 8) return MVT::v8f32;
break;
- case f64:
- if (NumElements == 2) return v2f64;
- if (NumElements == 4) return v4f64;
+ case MVT::f64:
+ if (NumElements == 2) return MVT::v2f64;
+ if (NumElements == 4) return MVT::v4f64;
break;
}
- return getExtendedVectorVT(VT, NumElements);
+ return (MVT::SimpleValueType)(MVT::LastSimpleValueType+1);
+ }
+
+ static MVT getIntVectorWithNumElements(unsigned NumElts) {
+ switch (NumElts) {
+ default: return (MVT::SimpleValueType)(MVT::LastSimpleValueType+1);
+ case 1: return MVT::v1i64;
+ case 2: return MVT::v2i32;
+ case 4: return MVT::v4i16;
+ case 8: return MVT::v8i8;
+ case 16: return MVT::v16i8;
+ }
+ }
+ };
+
+ struct EVT { // EVT = Extended Value Type
+ private:
+ MVT V;
+ const Type *LLVMTy;
+
+ public:
+ EVT() : V((MVT::SimpleValueType)(MVT::LastSimpleValueType+1)) {}
+ EVT(MVT::SimpleValueType SVT) : V(SVT) { }
+ EVT(MVT S) : V(S) {}
+
+ bool operator==(const EVT VT) const {
+ if (V.SimpleTy == VT.V.SimpleTy) {
+ if (V.SimpleTy == MVT::LastSimpleValueType+1)
+ return LLVMTy == VT.LLVMTy;
+ return true;
+ }
+ return false;
+ }
+ bool operator!=(const EVT VT) const {
+ if (V.SimpleTy == VT.V.SimpleTy) {
+ if (V.SimpleTy == MVT::LastSimpleValueType+1)
+ return LLVMTy != VT.LLVMTy;
+ return false;
+ }
+ return true;
+ }
+
+ /// getFloatingPointVT - Returns the EVT that represents a floating point
+ /// type with the given number of bits. There are two floating point types
+ /// with 128 bits - this returns f128 rather than ppcf128.
+ static EVT getFloatingPointVT(unsigned BitWidth) {
+ return MVT::getFloatingPointVT(BitWidth);
+ }
+
+ /// getIntegerVT - Returns the EVT that represents an integer with the given
+ /// number of bits.
+ static EVT getIntegerVT(unsigned BitWidth) {
+ MVT M = MVT::getIntegerVT(BitWidth);
+ if (M.SimpleTy == MVT::LastSimpleValueType+1)
+ return getExtendedIntegerVT(BitWidth);
+ else
+ return M;
+ }
+
+ /// getVectorVT - Returns the EVT that represents a vector NumElements in
+ /// length, where each element is of type VT.
+ static EVT getVectorVT(EVT VT, unsigned NumElements) {
+ MVT M = MVT::getVectorVT(VT.V, NumElements);
+ if (M.SimpleTy == MVT::LastSimpleValueType+1)
+ return getExtendedVectorVT(VT, NumElements);
+ else
+ return M;
}
/// getIntVectorWithNumElements - Return any integer vector type that has
/// the specified number of elements.
static EVT getIntVectorWithNumElements(unsigned NumElts) {
- switch (NumElts) {
- default: return getVectorVT(i8, NumElts);
- case 1: return v1i64;
- case 2: return v2i32;
- case 4: return v4i16;
- case 8: return v8i8;
- case 16: return v16i8;
- }
+ MVT M = MVT::getIntVectorWithNumElements(NumElts);
+ if (M.SimpleTy == MVT::LastSimpleValueType+1)
+ return getVectorVT(EVT(MVT::i8), NumElts);
+ else
+ return M;
}
/// isSimple - Test if the given EVT is simple (as opposed to being
/// extended).
bool isSimple() const {
- return V <= LastSimpleValueType;
+ return V.SimpleTy <= MVT::LastSimpleValueType;
}
/// isExtended - Test if the given EVT is extended (as opposed to
/// isFloatingPoint - Return true if this is a FP, or a vector FP type.
bool isFloatingPoint() const {
return isSimple() ?
- ((V >= f32 && V <= ppcf128) ||
- (V >= v2f32 && V <= v4f64)) : isExtendedFloatingPoint();
+ ((V >= MVT::f32 && V <= MVT::ppcf128) ||
+ (V >= MVT::v2f32 && V <= MVT::v4f64)) : isExtendedFloatingPoint();
}
/// isInteger - Return true if this is an integer, or a vector integer type.
bool isInteger() const {
return isSimple() ?
- ((V >= FIRST_INTEGER_VALUETYPE && V <= LAST_INTEGER_VALUETYPE) ||
- (V >= v2i8 && V <= v4i64)) : isExtendedInteger();
+ ((V >= MVT::FIRST_INTEGER_VALUETYPE &&
+ V <= MVT::LAST_INTEGER_VALUETYPE) ||
+ (V >= MVT::v2i8 && V <= MVT::v4i64)) : isExtendedInteger();
}
/// isVector - Return true if this is a vector value type.
bool isVector() const {
return isSimple() ?
- (V >= FIRST_VECTOR_VALUETYPE && V <= LAST_VECTOR_VALUETYPE) :
+ (V >= MVT::FIRST_VECTOR_VALUETYPE && V <=
+ MVT::LAST_VECTOR_VALUETYPE) :
isExtendedVector();
}
/// is64BitVector - Return true if this is a 64-bit vector type.
bool is64BitVector() const {
return isSimple() ?
- (V==v8i8 || V==v4i16 || V==v2i32 || V==v1i64 || V==v2f32) :
+ (V==MVT::v8i8 || V==MVT::v4i16 || V==MVT::v2i32 ||
+ V==MVT::v1i64 || V==MVT::v2f32) :
isExtended64BitVector();
}
/// is128BitVector - Return true if this is a 128-bit vector type.
bool is128BitVector() const {
return isSimple() ?
- (V==v16i8 || V==v8i16 || V==v4i32 ||
- V==v2i64 || V==v4f32 || V==v2f64) :
+ (V==MVT::v16i8 || V==MVT::v8i16 || V==MVT::v4i32 ||
+ V==MVT::v2i64 || V==MVT::v4f32 || V==MVT::v2f64) :
isExtended128BitVector();
}
/// is256BitVector - Return true if this is a 256-bit vector type.
inline bool is256BitVector() const {
return isSimple() ?
- (V==v8f32 || V==v4f64 || V==v32i8 || V==v16i16 || V==v8i32 ||
- V==v4i64) : isExtended256BitVector();
+ (V==MVT::v8f32 || V==MVT::v4f64 || V==MVT::v32i8 ||
+ V==MVT::v16i16 || V==MVT::v8i32 || V==MVT::v4i64) :
+ isExtended256BitVector();
}
/// isOverloaded - Return true if this is an overloaded type for TableGen.
bool isOverloaded() const {
- return (V==iAny || V==fAny || V==vAny || V==iPTRAny);
+ return (V==MVT::iAny || V==MVT::fAny || V==MVT::vAny || V==MVT::iPTRAny);
}
/// isByteSized - Return true if the bit size is a multiple of 8.
/// getSimpleVT - Return the SimpleValueType held in the specified
/// simple EVT.
- SimpleValueType getSimpleVT() const {
+ MVT getSimpleVT() const {
assert(isSimple() && "Expected a SimpleValueType!");
- return SimpleValueType(V);
+ return V;
}
/// getVectorElementType - Given a vector type, return the type of
/// each element.
EVT getVectorElementType() const {
assert(isVector() && "Invalid vector type!");
- switch (V) {
- default:
+ if (isSimple())
+ return V.getVectorElementType();
+ else
return getExtendedVectorElementType();
- case v2i8 :
- case v4i8 :
- case v8i8 :
- case v16i8:
- case v32i8: return i8;
- case v2i16:
- case v4i16:
- case v8i16:
- case v16i16: return i16;
- case v2i32:
- case v4i32:
- case v8i32: return i32;
- case v1i64:
- case v2i64:
- case v4i64: return i64;
- case v2f32:
- case v4f32:
- case v8f32: return f32;
- case v2f64:
- case v4f64: return f64;
- }
}
/// getVectorNumElements - Given a vector type, return the number of
/// elements it contains.
unsigned getVectorNumElements() const {
assert(isVector() && "Invalid vector type!");
- switch (V) {
- default:
+ if (isSimple())
+ return V.getVectorNumElements();
+ else
return getExtendedVectorNumElements();
- case v32i8: return 32;
- case v16i8:
- case v16i16: return 16;
- case v8i8 :
- case v8i16:
- case v8i32:
- case v8f32: return 8;
- case v4i8:
- case v4i16:
- case v4i32:
- case v4i64:
- case v4f32:
- case v4f64: return 4;
- case v2i8:
- case v2i16:
- case v2i32:
- case v2i64:
- case v2f32:
- case v2f64: return 2;
- case v1i64: return 1;
- }
}
/// getSizeInBits - Return the size of the specified value type in bits.
unsigned getSizeInBits() const {
- switch (V) {
- case iPTR:
- assert(0 && "Value type size is target-dependent. Ask TLI.");
- case iPTRAny:
- case iAny:
- case fAny:
- case vAny:
- assert(0 && "Value type is overloaded.");
- default:
+ if (isSimple())
+ return V.getSizeInBits();
+ else
return getExtendedSizeInBits();
- case i1 : return 1;
- case i8 : return 8;
- case i16 :
- case v2i8: return 16;
- case f32 :
- case i32 :
- case v4i8:
- case v2i16: return 32;
- case f64 :
- case i64 :
- case v8i8:
- case v4i16:
- case v2i32:
- case v1i64:
- case v2f32: return 64;
- case f80 : return 80;
- case f128:
- case ppcf128:
- case i128:
- case v16i8:
- case v8i16:
- case v4i32:
- case v2i64:
- case v4f32:
- case v2f64: return 128;
- case v32i8:
- case v16i16:
- case v8i32:
- case v4i64:
- case v8f32:
- case v4f64: return 256;
- }
}
/// getStoreSizeInBits - Return the number of bits overwritten by a store
assert(isInteger() && !isVector() && "Invalid integer type!");
unsigned BitWidth = getSizeInBits();
if (BitWidth <= 8)
- return i8;
+ return EVT(MVT::i8);
else
return getIntegerVT(1 << Log2_32_Ceil(BitWidth));
}
/// types are returned as Other, otherwise they are invalid.
static EVT getEVT(const Type *Ty, bool HandleUnknown = false);
- /// getRawBits - Represent the type as a bunch of bits.
- uintptr_t getRawBits() const { return V; }
+ intptr_t getRawBits() {
+ if (V.SimpleTy <= MVT::LastSimpleValueType)
+ return V.SimpleTy;
+ else
+ return (intptr_t)(LLVMTy);
+ }
/// compareRawBits - A meaningless but well-behaved order, useful for
/// constructing containers.
struct compareRawBits {
bool operator()(EVT L, EVT R) const {
- return L.getRawBits() < R.getRawBits();
+ if (L.V.SimpleTy == R.V.SimpleTy)
+ return L.LLVMTy < R.LLVMTy;
+ else
+ return L.V.SimpleTy < R.V.SimpleTy;
}
};
index aa3a651f749851f8535b10225a90ce4bc059df21..01951ce5f201a6e2afa292fcaad46d94f85ceecd 100644 (file)
bool isBigEndian() const { return !IsLittleEndian; }
bool isLittleEndian() const { return IsLittleEndian; }
- EVT::SimpleValueType getPointerTy() const { return PointerTy; }
- EVT::SimpleValueType getShiftAmountTy() const { return ShiftAmountTy; }
+ MVT getPointerTy() const { return PointerTy; }
+ MVT getShiftAmountTy() const { return ShiftAmountTy; }
/// usesGlobalOffsetTable - Return true if this target uses a GOT for PIC
/// codegen.
/// getSetCCResultType - Return the ValueType of the result of SETCC
/// operations. Also used to obtain the target's preferred type for
/// the condition operand of SELECT and BRCOND nodes. In the case of
- /// BRCOND the argument passed is EVT::Other since there are no other
+ /// BRCOND the argument passed is MVT::Other since there are no other
/// operands to get a type hint from.
virtual
- EVT::SimpleValueType getSetCCResultType(EVT VT) const;
+ MVT::SimpleValueType getSetCCResultType(EVT VT) const;
/// getBooleanContents - For targets without i1 registers, this gives the
/// nature of the high-bits of boolean values held in types wider than i1.
/// specified value type. This may only be called on legal types.
TargetRegisterClass *getRegClassFor(EVT VT) const {
assert(VT.isSimple() && "getRegClassFor called on illegal type!");
- TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT()];
+ TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy];
assert(RC && "This value type is not natively supported!");
return RC;
}
/// holds it without promotions or expansions.
bool isTypeLegal(EVT VT) const {
assert(!VT.isSimple() ||
- (unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT));
- return VT.isSimple() && RegClassForVT[VT.getSimpleVT()] != 0;
+ (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
+ return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != 0;
}
class ValueTypeActionImpl {
/// ValueTypeActions - This is a bitvector that contains two bits for each
/// value type, where the two bits correspond to the LegalizeAction enum.
/// This can be queried with "getTypeAction(VT)".
- /// dimension by (EVT::MAX_ALLOWED_VALUETYPE/32) * 2
- uint32_t ValueTypeActions[(EVT::MAX_ALLOWED_VALUETYPE/32)*2];
+ /// dimension by (MVT::MAX_ALLOWED_VALUETYPE/32) * 2
+ uint32_t ValueTypeActions[(MVT::MAX_ALLOWED_VALUETYPE/32)*2];
public:
ValueTypeActionImpl() {
ValueTypeActions[0] = ValueTypeActions[1] = 0;
assert(0 && "Unsupported extended type!");
return Legal;
}
- unsigned I = VT.getSimpleVT();
+ unsigned I = VT.getSimpleVT().SimpleTy;
assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0]));
return (LegalizeAction)((ValueTypeActions[I>>4] >> ((2*I) & 31)) & 3);
}
void setTypeAction(EVT VT, LegalizeAction Action) {
- unsigned I = VT.getSimpleVT();
+ unsigned I = VT.getSimpleVT().SimpleTy;
assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0]));
ValueTypeActions[I>>4] |= Action << ((I*2) & 31);
}
/// returns the integer type to transform to.
EVT getTypeToTransformTo(EVT VT) const {
if (VT.isSimple()) {
- assert((unsigned)VT.getSimpleVT() < array_lengthof(TransformToType));
- EVT NVT = TransformToType[VT.getSimpleVT()];
+ assert((unsigned)VT.getSimpleVT().SimpleTy <
+ array_lengthof(TransformToType));
+ EVT NVT = TransformToType[VT.getSimpleVT().SimpleTy];
assert(getTypeAction(NVT) != Promote &&
"Promote may not follow Expand or Promote");
return NVT;
return getTypeAction(NVT) == Promote ? getTypeToTransformTo(NVT) : NVT;
}
assert(0 && "Unsupported extended type!");
- return EVT(EVT::Other); // Not reached
+ return MVT(MVT::Other); // Not reached
}
/// getTypeToExpandTo - For types supported by the target, this is an
/// getWidenVectorType: given a vector type, returns the type to widen to
/// (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
- /// If there is no vector type that we want to widen to, returns EVT::Other
+ /// If there is no vector type that we want to widen to, returns MVT::Other
/// When and were to widen is target dependent based on the cost of
/// scalarizing vs using the wider vector type.
virtual EVT getWidenVectorType(EVT VT) const;
LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
if (VT.isExtended()) return Expand;
assert(Op < array_lengthof(OpActions[0]) &&
- (unsigned)VT.getSimpleVT() < sizeof(OpActions[0][0])*8 &&
+ (unsigned)VT.getSimpleVT().SimpleTy < sizeof(OpActions[0][0])*8 &&
"Table isn't big enough!");
- unsigned I = (unsigned) VT.getSimpleVT();
+ unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
unsigned J = I & 31;
I = I >> 5;
return (LegalizeAction)((OpActions[I][Op] >> (J*2) ) & 3);
/// legal on this target or can be made legal with custom lowering. This
/// is used to help guide high-level lowering decisions.
bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
- return (VT == EVT::Other || isTypeLegal(VT)) &&
+ return (VT == MVT::Other || isTypeLegal(VT)) &&
(getOperationAction(Op, VT) == Legal ||
getOperationAction(Op, VT) == Custom);
}
/// isOperationLegal - Return true if the specified operation is legal on this
/// target.
bool isOperationLegal(unsigned Op, EVT VT) const {
- return (VT == EVT::Other || isTypeLegal(VT)) &&
+ return (VT == MVT::Other || isTypeLegal(VT)) &&
getOperationAction(Op, VT) == Legal;
}
/// for it.
LegalizeAction getLoadExtAction(unsigned LType, EVT VT) const {
assert(LType < array_lengthof(LoadExtActions) &&
- (unsigned)VT.getSimpleVT() < sizeof(LoadExtActions[0])*4 &&
+ (unsigned)VT.getSimpleVT().SimpleTy < sizeof(LoadExtActions[0])*4 &&
"Table isn't big enough!");
- return (LegalizeAction)((LoadExtActions[LType] >> (2*VT.getSimpleVT())) & 3);
+ return (LegalizeAction)((LoadExtActions[LType] >>
+ (2*VT.getSimpleVT().SimpleTy)) & 3);
}
/// isLoadExtLegal - Return true if the specified load with extension is legal
/// expander for it.
LegalizeAction getTruncStoreAction(EVT ValVT,
EVT MemVT) const {
- assert((unsigned)ValVT.getSimpleVT() < array_lengthof(TruncStoreActions) &&
- (unsigned)MemVT.getSimpleVT() < sizeof(TruncStoreActions[0])*4 &&
+ assert((unsigned)ValVT.getSimpleVT().SimpleTy <
+ array_lengthof(TruncStoreActions) &&
+ (unsigned)MemVT.getSimpleVT().SimpleTy <
+ sizeof(TruncStoreActions[0])*4 &&
"Table isn't big enough!");
- return (LegalizeAction)((TruncStoreActions[ValVT.getSimpleVT()] >>
- (2*MemVT.getSimpleVT())) & 3);
+ return (LegalizeAction)((TruncStoreActions[ValVT.getSimpleVT().SimpleTy] >>
+ (2*MemVT.getSimpleVT().SimpleTy)) & 3);
}
/// isTruncStoreLegal - Return true if the specified store with truncation is
LegalizeAction
getIndexedLoadAction(unsigned IdxMode, EVT VT) const {
assert( IdxMode < array_lengthof(IndexedModeActions[0][0]) &&
- ((unsigned)VT.getSimpleVT()) < EVT::LAST_VALUETYPE &&
+ ((unsigned)VT.getSimpleVT().SimpleTy) < MVT::LAST_VALUETYPE &&
"Table isn't big enough!");
- return (LegalizeAction)((IndexedModeActions[(unsigned)VT.getSimpleVT()][0][IdxMode]));
+ return (LegalizeAction)((IndexedModeActions[
+ (unsigned)VT.getSimpleVT().SimpleTy][0][IdxMode]));
}
/// isIndexedLoadLegal - Return true if the specified indexed load is legal
LegalizeAction
getIndexedStoreAction(unsigned IdxMode, EVT VT) const {
assert(IdxMode < array_lengthof(IndexedModeActions[0][1]) &&
- (unsigned)VT.getSimpleVT() < EVT::LAST_VALUETYPE &&
+ (unsigned)VT.getSimpleVT().SimpleTy < MVT::LAST_VALUETYPE &&
"Table isn't big enough!");
- return (LegalizeAction)((IndexedModeActions[(unsigned)VT.getSimpleVT()][1][IdxMode]));
+ return (LegalizeAction)((IndexedModeActions[
+ (unsigned)VT.getSimpleVT().SimpleTy][1][IdxMode]));
}
/// isIndexedStoreLegal - Return true if the specified indexed load is legal
/// for it.
LegalizeAction
getConvertAction(EVT FromVT, EVT ToVT) const {
- assert((unsigned)FromVT.getSimpleVT() < array_lengthof(ConvertActions) &&
- (unsigned)ToVT.getSimpleVT() < sizeof(ConvertActions[0])*4 &&
+ assert((unsigned)FromVT.getSimpleVT().SimpleTy <
+ array_lengthof(ConvertActions) &&
+ (unsigned)ToVT.getSimpleVT().SimpleTy <
+ sizeof(ConvertActions[0])*4 &&
"Table isn't big enough!");
- return (LegalizeAction)((ConvertActions[FromVT.getSimpleVT()] >>
- (2*ToVT.getSimpleVT())) & 3);
+ return (LegalizeAction)((ConvertActions[FromVT.getSimpleVT().SimpleTy] >>
+ (2*ToVT.getSimpleVT().SimpleTy)) & 3);
}
/// isConvertLegal - Return true if the specified conversion is legal
LegalizeAction
getCondCodeAction(ISD::CondCode CC, EVT VT) const {
assert((unsigned)CC < array_lengthof(CondCodeActions) &&
- (unsigned)VT.getSimpleVT() < sizeof(CondCodeActions[0])*4 &&
+ (unsigned)VT.getSimpleVT().SimpleTy < sizeof(CondCodeActions[0])*4 &&
"Table isn't big enough!");
LegalizeAction Action = (LegalizeAction)
- ((CondCodeActions[CC] >> (2*VT.getSimpleVT())) & 3);
+ ((CondCodeActions[CC] >> (2*VT.getSimpleVT().SimpleTy)) & 3);
assert(Action != Promote && "Can't promote condition code!");
return Action;
}
"This operation isn't promoted!");
// See if this has an explicit type specified.
- std::map<std::pair<unsigned, EVT::SimpleValueType>,
- EVT::SimpleValueType>::const_iterator PTTI =
- PromoteToType.find(std::make_pair(Op, VT.getSimpleVT()));
+ std::map<std::pair<unsigned, MVT::SimpleValueType>,
+ MVT::SimpleValueType>::const_iterator PTTI =
+ PromoteToType.find(std::make_pair(Op, VT.getSimpleVT().SimpleTy));
if (PTTI != PromoteToType.end()) return PTTI->second;
assert((VT.isInteger() || VT.isFloatingPoint()) &&
EVT NVT = VT;
do {
- NVT = (EVT::SimpleValueType)(NVT.getSimpleVT()+1);
- assert(NVT.isInteger() == VT.isInteger() && NVT != EVT::isVoid &&
+ NVT = (MVT::SimpleValueType)(NVT.getSimpleVT().SimpleTy+1);
+ assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
"Didn't find type to promote to!");
} while (!isTypeLegal(NVT) ||
getOperationAction(Op, NVT) == Promote);
/// getValueType - Return the EVT corresponding to this LLVM type.
/// This is fixed by the LLVM operations except for the pointer size. If
- /// AllowUnknown is true, this will return EVT::Other for types with no EVT
+ /// AllowUnknown is true, this will return MVT::Other for types with no EVT
/// counterpart (e.g. structs), otherwise it will assert.
EVT getValueType(const Type *Ty, bool AllowUnknown = false) const {
EVT VT = EVT::getEVT(Ty, AllowUnknown);
- return VT == EVT::iPTR ? PointerTy : VT;
+ return VT == MVT:: iPTR ? PointerTy : VT;
}
/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
/// eventually require.
EVT getRegisterType(EVT VT) const {
if (VT.isSimple()) {
- assert((unsigned)VT.getSimpleVT() < array_lengthof(RegisterTypeForVT));
- return RegisterTypeForVT[VT.getSimpleVT()];
+ assert((unsigned)VT.getSimpleVT().SimpleTy <
+ array_lengthof(RegisterTypeForVT));
+ return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
}
if (VT.isVector()) {
EVT VT1, RegisterVT;
return getRegisterType(getTypeToTransformTo(VT));
}
assert(0 && "Unsupported extended type!");
- return EVT(EVT::Other); // Not reached
+ return EVT(MVT::Other); // Not reached
}
/// getNumRegisters - Return the number of registers that this ValueType will
/// type. For an i140 on a 32 bit machine this means 5 registers.
unsigned getNumRegisters(EVT VT) const {
if (VT.isSimple()) {
- assert((unsigned)VT.getSimpleVT() < array_lengthof(NumRegistersForVT));
- return NumRegistersForVT[VT.getSimpleVT()];
+ assert((unsigned)VT.getSimpleVT().SimpleTy <
+ array_lengthof(NumRegistersForVT));
+ return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
}
if (VT.isVector()) {
EVT VT1, VT2;
virtual EVT getOptimalMemOpType(uint64_t Size, unsigned Align,
bool isSrcConst, bool isSrcStr,
SelectionDAG &DAG) const {
- return EVT::iAny;
+ return MVT::iAny;
}
/// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp
/// setShiftAmountType - Describe the type that should be used for shift
/// amounts. This type defaults to the pointer type.
- void setShiftAmountType(EVT::SimpleValueType VT) { ShiftAmountTy = VT; }
+ void setShiftAmountType(MVT VT) { ShiftAmountTy = VT; }
/// setBooleanContents - Specify how the target extends the result of a
/// boolean value from i1 to a wider type. See getBooleanContents.
/// regclass for the specified value type. This indicates the selector can
/// handle values of that class natively.
void addRegisterClass(EVT VT, TargetRegisterClass *RC) {
- assert((unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT));
+ assert((unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
AvailableRegClasses.push_back(std::make_pair(VT, RC));
- RegClassForVT[VT.getSimpleVT()] = RC;
+ RegClassForVT[VT.getSimpleVT().SimpleTy] = RC;
}
/// computeRegisterProperties - Once all of the register classes are added,
/// setOperationAction - Indicate that the specified operation does not work
/// with the specified type and indicate what to do about it.
- void setOperationAction(unsigned Op, EVT::SimpleValueType VT,
+ void setOperationAction(unsigned Op, MVT VT,
LegalizeAction Action) {
- unsigned I = (unsigned)VT;
+ unsigned I = (unsigned)VT.SimpleTy;
unsigned J = I & 31;
I = I >> 5;
OpActions[I][Op] &= ~(uint64_t(3UL) << (J*2));
/// setLoadExtAction - Indicate that the specified load with extension does
/// not work with the with specified type and indicate what to do about it.
- void setLoadExtAction(unsigned ExtType, EVT::SimpleValueType VT,
+ void setLoadExtAction(unsigned ExtType, MVT VT,
LegalizeAction Action) {
- assert((unsigned)VT < sizeof(LoadExtActions[0])*4 &&
+ assert((unsigned)VT.SimpleTy < sizeof(LoadExtActions[0])*4 &&
ExtType < array_lengthof(LoadExtActions) &&
"Table isn't big enough!");
- LoadExtActions[ExtType] &= ~(uint64_t(3UL) << VT*2);
- LoadExtActions[ExtType] |= (uint64_t)Action << VT*2;
+ LoadExtActions[ExtType] &= ~(uint64_t(3UL) << VT.SimpleTy*2);
+ LoadExtActions[ExtType] |= (uint64_t)Action << VT.SimpleTy*2;
}
/// setTruncStoreAction - Indicate that the specified truncating store does
/// not work with the with specified type and indicate what to do about it.
- void setTruncStoreAction(EVT::SimpleValueType ValVT,
- EVT::SimpleValueType MemVT,
+ void setTruncStoreAction(MVT ValVT, MVT MemVT,
LegalizeAction Action) {
- assert((unsigned)ValVT < array_lengthof(TruncStoreActions) &&
- (unsigned)MemVT < sizeof(TruncStoreActions[0])*4 &&
+ assert((unsigned)ValVT.SimpleTy < array_lengthof(TruncStoreActions) &&
+ (unsigned)MemVT.SimpleTy < sizeof(TruncStoreActions[0])*4 &&
"Table isn't big enough!");
- TruncStoreActions[ValVT] &= ~(uint64_t(3UL) << MemVT*2);
- TruncStoreActions[ValVT] |= (uint64_t)Action << MemVT*2;
+ TruncStoreActions[ValVT.SimpleTy] &= ~(uint64_t(3UL) << MemVT.SimpleTy*2);
+ TruncStoreActions[ValVT.SimpleTy] |= (uint64_t)Action << MemVT.SimpleTy*2;
}
/// setIndexedLoadAction - Indicate that the specified indexed load does or
/// does not work with the with specified type and indicate what to do abort
/// it. NOTE: All indexed mode loads are initialized to Expand in
/// TargetLowering.cpp
- void setIndexedLoadAction(unsigned IdxMode, EVT::SimpleValueType VT,
+ void setIndexedLoadAction(unsigned IdxMode, MVT VT,
LegalizeAction Action) {
- assert((unsigned)VT < EVT::LAST_VALUETYPE &&
+ assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
IdxMode < array_lengthof(IndexedModeActions[0][0]) &&
"Table isn't big enough!");
- IndexedModeActions[(unsigned)VT][0][IdxMode] = (uint8_t)Action;
+ IndexedModeActions[(unsigned)VT.SimpleTy][0][IdxMode] = (uint8_t)Action;
}
/// setIndexedStoreAction - Indicate that the specified indexed store does or
/// does not work with the with specified type and indicate what to do about
/// it. NOTE: All indexed mode stores are initialized to Expand in
/// TargetLowering.cpp
- void setIndexedStoreAction(unsigned IdxMode, EVT::SimpleValueType VT,
+ void setIndexedStoreAction(unsigned IdxMode, MVT VT,
LegalizeAction Action) {
- assert((unsigned)VT < EVT::LAST_VALUETYPE &&
+ assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
IdxMode < array_lengthof(IndexedModeActions[0][1] ) &&
"Table isn't big enough!");
- IndexedModeActions[(unsigned)VT][1][IdxMode] = (uint8_t)Action;
+ IndexedModeActions[(unsigned)VT.SimpleTy][1][IdxMode] = (uint8_t)Action;
}
/// setConvertAction - Indicate that the specified conversion does or does
/// not work with the with specified type and indicate what to do about it.
- void setConvertAction(EVT::SimpleValueType FromVT, EVT::SimpleValueType ToVT,
+ void setConvertAction(MVT FromVT, MVT ToVT,
LegalizeAction Action) {
- assert((unsigned)FromVT < array_lengthof(ConvertActions) &&
- (unsigned)ToVT < sizeof(ConvertActions[0])*4 &&
+ assert((unsigned)FromVT.SimpleTy < array_lengthof(ConvertActions) &&
+ (unsigned)ToVT.SimpleTy < sizeof(ConvertActions[0])*4 &&
"Table isn't big enough!");
- ConvertActions[FromVT] &= ~(uint64_t(3UL) << ToVT*2);
- ConvertActions[FromVT] |= (uint64_t)Action << ToVT*2;
+ ConvertActions[FromVT.SimpleTy] &= ~(uint64_t(3UL) << ToVT.SimpleTy*2);
+ ConvertActions[FromVT.SimpleTy] |= (uint64_t)Action << ToVT.SimpleTy*2;
}
/// setCondCodeAction - Indicate that the specified condition code is or isn't
/// supported on the target and indicate what to do about it.
- void setCondCodeAction(ISD::CondCode CC, EVT::SimpleValueType VT,
+ void setCondCodeAction(ISD::CondCode CC, MVT VT,
LegalizeAction Action) {
- assert((unsigned)VT < sizeof(CondCodeActions[0])*4 &&
+ assert((unsigned)VT.SimpleTy < sizeof(CondCodeActions[0])*4 &&
(unsigned)CC < array_lengthof(CondCodeActions) &&
"Table isn't big enough!");
- CondCodeActions[(unsigned)CC] &= ~(uint64_t(3UL) << VT*2);
- CondCodeActions[(unsigned)CC] |= (uint64_t)Action << VT*2;
+ CondCodeActions[(unsigned)CC] &= ~(uint64_t(3UL) << VT.SimpleTy*2);
+ CondCodeActions[(unsigned)CC] |= (uint64_t)Action << VT.SimpleTy*2;
}
/// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the
/// promotion code defaults to trying a larger integer/fp until it can find
/// one that works. If that default is insufficient, this method can be used
/// by the target to override the default.
- void AddPromotedToType(unsigned Opc, EVT::SimpleValueType OrigVT,
- EVT::SimpleValueType DestVT) {
- PromoteToType[std::make_pair(Opc, OrigVT)] = DestVT;
+ void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
+ PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
}
/// addLegalFPImmediate - Indicate that this target can instruction select
AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
: InlineAsm::ConstraintInfo(info),
ConstraintType(TargetLowering::C_Unknown),
- CallOperandVal(0), ConstraintVT(EVT::Other) {
+ CallOperandVal(0), ConstraintVT(MVT::Other) {
}
};
/// PointerTy - The type to use for pointers, usually i32 or i64.
///
- EVT::SimpleValueType PointerTy;
+ MVT PointerTy;
/// IsLittleEndian - True if this is a little endian target.
///
/// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever
/// PointerTy is.
- EVT::SimpleValueType ShiftAmountTy;
+ MVT ShiftAmountTy;
/// BooleanContents - Information about the contents of the high-bits in
/// boolean values held in a type wider than i1. See getBooleanContents.
/// RegClassForVT - This indicates the default register class to use for
/// each ValueType the target supports natively.
- TargetRegisterClass *RegClassForVT[EVT::LAST_VALUETYPE];
- unsigned char NumRegistersForVT[EVT::LAST_VALUETYPE];
- EVT RegisterTypeForVT[EVT::LAST_VALUETYPE];
+ TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
+ unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
+ EVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
/// TransformToType - For any value types we are promoting or expanding, this
/// contains the value type that we are changing to. For Expanded types, this
/// contains one step of the expand (e.g. i64 -> i32), even if there are
/// multiple steps required (e.g. i64 -> i16). For types natively supported
/// by the system, this holds the same type (e.g. i32 -> i32).
- EVT TransformToType[EVT::LAST_VALUETYPE];
+ EVT TransformToType[MVT::LAST_VALUETYPE];
/// OpActions - For each operation and each value type, keep a LegalizeAction
/// that indicates how instruction selection should deal with the operation.
/// operations that are not should be described. Note that operations on
/// non-legal value types are not described here.
/// This array is accessed using VT.getSimpleVT(), so it is subject to
- /// the EVT::MAX_ALLOWED_VALUETYPE * 2 bits.
- uint64_t OpActions[EVT::MAX_ALLOWED_VALUETYPE/(sizeof(uint64_t)*4)][ISD::BUILTIN_OP_END];
+ /// the MVT::MAX_ALLOWED_VALUETYPE * 2 bits.
+ uint64_t OpActions[MVT::MAX_ALLOWED_VALUETYPE/(sizeof(uint64_t)*4)][ISD::BUILTIN_OP_END];
/// LoadExtActions - For each load of load extension type and each value type,
/// keep a LegalizeAction that indicates how instruction selection should deal
/// TruncStoreActions - For each truncating store, keep a LegalizeAction that
/// indicates how instruction selection should deal with the store.
- uint64_t TruncStoreActions[EVT::LAST_VALUETYPE];
+ uint64_t TruncStoreActions[MVT::LAST_VALUETYPE];
/// IndexedModeActions - For each indexed mode and each value type,
/// keep a pair of LegalizeAction that indicates how instruction
/// dimension is now the value_type for the reference. The second
/// dimension is the load [0] vs. store[1]. The third dimension
/// represents the various modes for load store.
- uint8_t IndexedModeActions[EVT::LAST_VALUETYPE][2][ISD::LAST_INDEXED_MODE];
+ uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][2][ISD::LAST_INDEXED_MODE];
/// ConvertActions - For each conversion from source type to destination type,
/// keep a LegalizeAction that indicates how instruction selection should
/// deal with the conversion.
/// Currently, this is used only for floating->floating conversions
/// (FP_EXTEND and FP_ROUND).
- uint64_t ConvertActions[EVT::LAST_VALUETYPE];
+ uint64_t ConvertActions[MVT::LAST_VALUETYPE];
/// CondCodeActions - For each condition code (ISD::CondCode) keep a
/// LegalizeAction that indicates how instruction selection should
///
/// Targets add entries to this map with AddPromotedToType(..), clients access
/// this with getTypeToPromoteTo(..).
- std::map<std::pair<unsigned, EVT::SimpleValueType>, EVT::SimpleValueType>
+ std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
PromoteToType;
/// LibcallRoutineNames - Stores the name each libcall.
index ac0d7da0f0c7ac1298fae9c5eda2a7c4b951a131..1673c9a55977b7cad5c18eb7f09dcba205d071b7 100644 (file)
/// hasType - return true if this TargetRegisterClass has the ValueType vt.
///
bool hasType(EVT vt) const {
- for(int i = 0; VTs[i] != EVT::Other; ++i)
+ for(int i = 0; VTs[i].getSimpleVT().SimpleTy != MVT::Other; ++i)
if (VTs[i] == vt)
return true;
return false;
vt_iterator vt_end() const {
vt_iterator I = VTs;
- while (*I != EVT::Other) ++I;
+ while (I->getSimpleVT().SimpleTy != MVT::Other) ++I;
return I;
}
/// register of the given type. If type is EVT::Other, then just return any
/// register class the register belongs to.
virtual const TargetRegisterClass *
- getPhysicalRegisterRegClass(unsigned Reg, EVT VT = EVT::Other) const;
+ getPhysicalRegisterRegClass(unsigned Reg, EVT VT = MVT::Other) const;
/// getAllocatableSet - Returns a bitset indexed by register number
/// indicating if a register is allocatable or not. If a register class is
index 1ee52a746b09b704f976ff333718f721227542f5..9a9125e578c3f485c8d982c04ff23092920c94bf 100644 (file)
}]>;
def extloadi1 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
- return cast<LoadSDNode>(N)->getMemoryVT() == EVT::i1;
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
}]>;
def extloadi8 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
- return cast<LoadSDNode>(N)->getMemoryVT() == EVT::i8;
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
}]>;
def extloadi16 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
- return cast<LoadSDNode>(N)->getMemoryVT() == EVT::i16;
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
}]>;
def extloadi32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
- return cast<LoadSDNode>(N)->getMemoryVT() == EVT::i32;
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
}]>;
def extloadf32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
- return cast<LoadSDNode>(N)->getMemoryVT() == EVT::f32;
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f32;
}]>;
def extloadf64 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
- return cast<LoadSDNode>(N)->getMemoryVT() == EVT::f64;
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f64;
}]>;
def sextloadi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
- return cast<LoadSDNode>(N)->getMemoryVT() == EVT::i1;
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
}]>;
def sextloadi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
- return cast<LoadSDNode>(N)->getMemoryVT() == EVT::i8;
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
}]>;
def sextloadi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
- return cast<LoadSDNode>(N)->getMemoryVT() == EVT::i16;
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
}]>;
def sextloadi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
- return cast<LoadSDNode>(N)->getMemoryVT() == EVT::i32;
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
}]>;
def zextloadi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
- return cast<LoadSDNode>(N)->getMemoryVT() == EVT::i1;
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
}]>;
def zextloadi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
- return cast<LoadSDNode>(N)->getMemoryVT() == EVT::i8;
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
}]>;
def zextloadi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
- return cast<LoadSDNode>(N)->getMemoryVT() == EVT::i16;
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
}]>;
def zextloadi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
- return cast<LoadSDNode>(N)->getMemoryVT() == EVT::i32;
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
}]>;
// store fragments.
}]>;
def truncstorei8 : PatFrag<(ops node:$val, node:$ptr),
(truncstore node:$val, node:$ptr), [{
- return cast<StoreSDNode>(N)->getMemoryVT() == EVT::i8;
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
}]>;
def truncstorei16 : PatFrag<(ops node:$val, node:$ptr),
(truncstore node:$val, node:$ptr), [{
- return cast<StoreSDNode>(N)->getMemoryVT() == EVT::i16;
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
}]>;
def truncstorei32 : PatFrag<(ops node:$val, node:$ptr),
(truncstore node:$val, node:$ptr), [{
- return cast<StoreSDNode>(N)->getMemoryVT() == EVT::i32;
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
}]>;
def truncstoref32 : PatFrag<(ops node:$val, node:$ptr),
(truncstore node:$val, node:$ptr), [{
- return cast<StoreSDNode>(N)->getMemoryVT() == EVT::f32;
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
}]>;
def truncstoref64 : PatFrag<(ops node:$val, node:$ptr),
(truncstore node:$val, node:$ptr), [{
- return cast<StoreSDNode>(N)->getMemoryVT() == EVT::f64;
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f64;
}]>;
// indexed store fragments.
}]>;
def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
(pre_truncst node:$val, node:$base, node:$offset), [{
- return cast<StoreSDNode>(N)->getMemoryVT() == EVT::i1;
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
}]>;
def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
(pre_truncst node:$val, node:$base, node:$offset), [{
- return cast<StoreSDNode>(N)->getMemoryVT() == EVT::i8;
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
}]>;
def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
(pre_truncst node:$val, node:$base, node:$offset), [{
- return cast<StoreSDNode>(N)->getMemoryVT() == EVT::i16;
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
}]>;
def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
(pre_truncst node:$val, node:$base, node:$offset), [{
- return cast<StoreSDNode>(N)->getMemoryVT() == EVT::i32;
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
}]>;
def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
(pre_truncst node:$val, node:$base, node:$offset), [{
- return cast<StoreSDNode>(N)->getMemoryVT() == EVT::f32;
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
}]>;
def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
}]>;
def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
(post_truncst node:$val, node:$base, node:$offset), [{
- return cast<StoreSDNode>(N)->getMemoryVT() == EVT::i1;
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
}]>;
def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
(post_truncst node:$val, node:$base, node:$offset), [{
- return cast<StoreSDNode>(N)->getMemoryVT() == EVT::i8;
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
}]>;
def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
(post_truncst node:$val, node:$base, node:$offset), [{
- return cast<StoreSDNode>(N)->getMemoryVT() == EVT::i16;
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
}]>;
def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
(post_truncst node:$val, node:$base, node:$offset), [{
- return cast<StoreSDNode>(N)->getMemoryVT() == EVT::i32;
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
}]>;
def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
(post_truncst node:$val, node:$base, node:$offset), [{
- return cast<StoreSDNode>(N)->getMemoryVT() == EVT::f32;
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
}]>;
// setcc convenience fragments.
def atomic_cmp_swap_8 :
PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
(atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
- return cast<AtomicSDNode>(N)->getMemoryVT() == EVT::i8;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
}]>;
def atomic_cmp_swap_16 :
PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
(atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
- return cast<AtomicSDNode>(N)->getMemoryVT() == EVT::i16;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
}]>;
def atomic_cmp_swap_32 :
PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
(atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
- return cast<AtomicSDNode>(N)->getMemoryVT() == EVT::i32;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
}]>;
def atomic_cmp_swap_64 :
PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
(atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
- return cast<AtomicSDNode>(N)->getMemoryVT() == EVT::i64;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
}]>;
multiclass binary_atomic_op<SDNode atomic_op> {
def _8 : PatFrag<(ops node:$ptr, node:$val),
(atomic_op node:$ptr, node:$val), [{
- return cast<AtomicSDNode>(N)->getMemoryVT() == EVT::i8;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
}]>;
def _16 : PatFrag<(ops node:$ptr, node:$val),
(atomic_op node:$ptr, node:$val), [{
- return cast<AtomicSDNode>(N)->getMemoryVT() == EVT::i16;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
}]>;
def _32 : PatFrag<(ops node:$ptr, node:$val),
(atomic_op node:$ptr, node:$val), [{
- return cast<AtomicSDNode>(N)->getMemoryVT() == EVT::i32;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
}]>;
def _64 : PatFrag<(ops node:$ptr, node:$val),
(atomic_op node:$ptr, node:$val), [{
- return cast<AtomicSDNode>(N)->getMemoryVT() == EVT::i64;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
}]>;
}
index d4d13884cb0c3c6da90e4172b5af151dd9326331..2d7147d24944a32ac82a112dda6cc3ad6fa41589 100644 (file)
static char isNegatibleForFree(SDValue Op, bool LegalOperations,
unsigned Depth = 0) {
// No compile time optimizations on this type.
- if (Op.getValueType() == EVT::ppcf128)
+ if (Op.getValueType() == MVT::ppcf128)
return 0;
// fneg is removable even if it has multiple uses.
/// otherwise return a null sd operand.
static SDValue getInputChainForNode(SDNode *N) {
if (unsigned NumOps = N->getNumOperands()) {
- if (N->getOperand(0).getValueType() == EVT::Other)
+ if (N->getOperand(0).getValueType() == MVT::Other)
return N->getOperand(0);
- else if (N->getOperand(NumOps-1).getValueType() == EVT::Other)
+ else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
return N->getOperand(NumOps-1);
for (unsigned i = 1; i < NumOps-1; ++i)
- if (N->getOperand(i).getValueType() == EVT::Other)
+ if (N->getOperand(i).getValueType() == MVT::Other)
return N->getOperand(i);
}
return SDValue();
} else {
// New and improved token factor.
Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
- EVT::Other, &Ops[0], Ops.size());
+ MVT::Other, &Ops[0], Ops.size());
}
// Don't add users to work list.
if (N->hasNUsesOfValue(0, 1))
return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0),
DAG.getNode(ISD::CARRY_FALSE,
- N->getDebugLoc(), EVT::Flag));
+ N->getDebugLoc(), MVT::Flag));
// canonicalize constant to RHS.
if (N0C && !N1C)
// fold (addc x, 0) -> x + no carry out
if (N1C && N1C->isNullValue())
return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
- N->getDebugLoc(), EVT::Flag));
+ N->getDebugLoc(), MVT::Flag));
// fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
APInt LHSZero, LHSOne;
(LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1),
DAG.getNode(ISD::CARRY_FALSE,
- N->getDebugLoc(), EVT::Flag));
+ N->getDebugLoc(), MVT::Flag));
}
return SDValue();
LN0->isUnindexed() && N0.hasOneUse() &&
// Do not change the width of a volatile load.
!LN0->isVolatile()) {
- EVT ExtVT = EVT::Other;
+ EVT ExtVT = MVT::Other;
uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits();
if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue()))
ExtVT = EVT::getIntegerVT(ActiveBits);
// Do not generate loads of non-round integer types since these can
// be expensive (and would be wrong if the type is not byte sized).
- if (ExtVT != EVT::Other && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() &&
+ if (ExtVT != MVT::Other && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() &&
(!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
EVT PtrType = N0.getOperand(1).getValueType();
}
// fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc
- if (N1C && N1C->getAPIntValue() == 1 && VT == EVT::i1 &&
+ if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 &&
(N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
if (N0C && N0C->isNullValue())
return N2;
// fold (select C, 1, X) -> (or C, X)
- if (VT == EVT::i1 && N1C && N1C->getAPIntValue() == 1)
+ if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1)
return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
// fold (select C, 0, 1) -> (xor C, 1)
if (VT.isInteger() &&
- (VT0 == EVT::i1 ||
+ (VT0 == MVT::i1 ||
(VT0.isInteger() &&
TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) &&
N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode);
}
// fold (select C, 0, X) -> (and (not C), X)
- if (VT == VT0 && VT == EVT::i1 && N1C && N1C->isNullValue()) {
+ if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
AddToWorkList(NOTNode.getNode());
return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2);
}
// fold (select C, X, 1) -> (or (not C), X)
- if (VT == VT0 && VT == EVT::i1 && N2C && N2C->getAPIntValue() == 1) {
+ if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
AddToWorkList(NOTNode.getNode());
return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1);
}
// fold (select C, X, 0) -> (and C, X)
- if (VT == EVT::i1 && N2C && N2C->isNullValue())
+ if (VT == MVT::i1 && N2C && N2C->isNullValue())
return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
// fold (select X, X, Y) -> (or X, Y)
// fold (select X, 1, Y) -> (or X, Y)
- if (VT == EVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
+ if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
// fold (select X, Y, X) -> (and X, Y)
// fold (select X, Y, 0) -> (and X, Y)
- if (VT == EVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
+ if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
// If we can fold this based on the true/false value, do so.
// fold selects based on a setcc into other things, such as min/max/abs
if (N0.getOpcode() == ISD::SETCC) {
// FIXME:
- // Check against EVT::Other for SELECT_CC, which is a workaround for targets
+ // Check against MVT::Other for SELECT_CC, which is a workaround for targets
// having to say they don't support SELECT_CC on every type the DAG knows
// about, since there is no way to mark an opcode illegal at all value types
- if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, EVT::Other) &&
+ if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) &&
TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT))
return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT,
N0.getOperand(0), N0.getOperand(1),
if (SrcEltVT.isFloatingPoint()) {
// Convert the input float vector to a int vector where the elements are the
// same sizes.
- assert((SrcEltVT == EVT::f32 || SrcEltVT == EVT::f64) && "Unknown FP VT!");
+ assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
EVT IntVT = EVT::getIntegerVT(SrcEltVT.getSizeInBits());
BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode();
SrcEltVT = IntVT;
// Now we know the input is an integer vector. If the output is a FP type,
// convert to integer first, then to FP of the right size.
if (DstEltVT.isFloatingPoint()) {
- assert((DstEltVT == EVT::f32 || DstEltVT == EVT::f64) && "Unknown FP VT!");
+ assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
EVT TmpVT = EVT::getIntegerVT(DstEltVT.getSizeInBits());
SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode();
}
// fold (fadd c1, c2) -> (fadd c1, c2)
- if (N0CFP && N1CFP && VT != EVT::ppcf128)
+ if (N0CFP && N1CFP && VT != MVT::ppcf128)
return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1);
// canonicalize constant to RHS
if (N0CFP && !N1CFP)
}
// fold (fsub c1, c2) -> c1-c2
- if (N0CFP && N1CFP && VT != EVT::ppcf128)
+ if (N0CFP && N1CFP && VT != MVT::ppcf128)
return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1);
// fold (fsub A, 0) -> A
if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
}
// fold (fmul c1, c2) -> c1*c2
- if (N0CFP && N1CFP && VT != EVT::ppcf128)
+ if (N0CFP && N1CFP && VT != MVT::ppcf128)
return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1);
// canonicalize constant to RHS
if (N0CFP && !N1CFP)
}
// fold (fdiv c1, c2) -> c1/c2
- if (N0CFP && N1CFP && VT != EVT::ppcf128)
+ if (N0CFP && N1CFP && VT != MVT::ppcf128)
return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1);
EVT VT = N->getValueType(0);
// fold (frem c1, c2) -> fmod(c1,c2)
- if (N0CFP && N1CFP && VT != EVT::ppcf128)
+ if (N0CFP && N1CFP && VT != MVT::ppcf128)
return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1);
return SDValue();
ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
EVT VT = N->getValueType(0);
- if (N0CFP && N1CFP && VT != EVT::ppcf128) // Constant fold
+ if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold
return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1);
if (N1CFP) {
EVT OpVT = N0.getValueType();
// fold (sint_to_fp c1) -> c1fp
- if (N0C && OpVT != EVT::ppcf128)
+ if (N0C && OpVT != MVT::ppcf128)
return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
// If the input is a legal type, and SINT_TO_FP is not legal on this target,
EVT OpVT = N0.getValueType();
// fold (uint_to_fp c1) -> c1fp
- if (N0C && OpVT != EVT::ppcf128)
+ if (N0C && OpVT != MVT::ppcf128)
return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
// If the input is a legal type, and UINT_TO_FP is not legal on this target,
EVT VT = N->getValueType(0);
// fold (fp_to_uint c1fp) -> c1
- if (N0CFP && VT != EVT::ppcf128)
+ if (N0CFP && VT != MVT::ppcf128)
return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0);
return SDValue();
EVT VT = N->getValueType(0);
// fold (fp_round c1fp) -> c1fp
- if (N0CFP && N0.getValueType() != EVT::ppcf128)
+ if (N0CFP && N0.getValueType() != MVT::ppcf128)
return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1);
// fold (fp_round (fp_extend x)) -> x
return SDValue();
// fold (fp_extend c1fp) -> c1fp
- if (N0CFP && VT != EVT::ppcf128)
+ if (N0CFP && VT != MVT::ppcf128)
return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0);
// Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
EVT VT = N->getValueType(0);
// fold (fabs c1) -> fabs(c1)
- if (N0CFP && VT != EVT::ppcf128)
+ if (N0CFP && VT != MVT::ppcf128)
return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
// fold (fabs (fabs x)) -> (fabs x)
if (N0.getOpcode() == ISD::FABS)
return Chain;
// unconditional branch
if (N1C && N1C->getAPIntValue() == 1)
- return DAG.getNode(ISD::BR, N->getDebugLoc(), EVT::Other, Chain, N2);
+ return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other, Chain, N2);
// fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
// on the target.
if (N1.getOpcode() == ISD::SETCC &&
- TLI.isOperationLegalOrCustom(ISD::BR_CC, EVT::Other)) {
- return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), EVT::Other,
+ TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) {
+ return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
Chain, N1.getOperand(2),
N1.getOperand(0), N1.getOperand(1), N2);
}
removeFromWorkList(N1.getNode());
DAG.DeleteNode(N1.getNode());
return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
- EVT::Other, Chain, SetCC, N2);
+ MVT::Other, Chain, SetCC, N2);
}
}
}
// fold br_cc true, dest -> br dest (unconditional branch)
if (SCCC && !SCCC->isNullValue())
- return DAG.getNode(ISD::BR, N->getDebugLoc(), EVT::Other,
+ return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other,
N->getOperand(0), N->getOperand(4));
// fold br_cc false, dest -> unconditional fall through
if (SCCC && SCCC->isNullValue())
// fold to a simpler setcc
if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
- return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), EVT::Other,
+ return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
N->getOperand(0), Simp.getOperand(2),
Simp.getOperand(0), Simp.getOperand(1),
N->getOperand(4));
// the updated indexed value in case of indexed loads), change uses of the
// chain value into uses of the chain input (i.e. delete the dead load).
if (!LD->isVolatile()) {
- if (N->getValueType(1) == EVT::Other) {
+ if (N->getValueType(1) == MVT::Other) {
// Unindexed loads.
if (N->hasNUsesOfValue(0, 0)) {
// It's not safe to use the two value CombineTo variant here. e.g.
}
} else {
// Indexed loads.
- assert(N->getValueType(2) == EVT::Other && "Malformed indexed loads?");
+ assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) {
SDValue Undef = DAG.getUNDEF(N->getValueType(0));
DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG));
// Create token factor to keep old chain connected.
SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
- EVT::Other, Chain, ReplLoad.getValue(1));
+ MVT::Other, Chain, ReplLoad.getValue(1));
// Replace uses with load result and token factor. Don't add users
// to work list.
// transform should not be done in this case.
if (Value.getOpcode() != ISD::TargetConstantFP) {
SDValue Tmp;
- switch (CFP->getValueType(0).getSimpleVT()) {
+ switch (CFP->getValueType(0).getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unknown FP type");
- case EVT::f80: // We don't do this for these yet.
- case EVT::f128:
- case EVT::ppcf128:
+ case MVT::f80: // We don't do this for these yet.
+ case MVT::f128:
+ case MVT::ppcf128:
break;
- case EVT::f32:
- if (((TLI.isTypeLegal(EVT::i32) || !LegalTypes) && !LegalOperations &&
+ case MVT::f32:
+ if (((TLI.isTypeLegal(MVT::i32) || !LegalTypes) && !LegalOperations &&
!ST->isVolatile()) ||
- TLI.isOperationLegalOrCustom(ISD::STORE, EVT::i32)) {
+ TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
- bitcastToAPInt().getZExtValue(), EVT::i32);
+ bitcastToAPInt().getZExtValue(), MVT::i32);
return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
Ptr, ST->getSrcValue(),
ST->getSrcValueOffset(), ST->isVolatile(),
ST->getAlignment());
}
break;
- case EVT::f64:
- if (((TLI.isTypeLegal(EVT::i64) || !LegalTypes) && !LegalOperations &&
+ case MVT::f64:
+ if (((TLI.isTypeLegal(MVT::i64) || !LegalTypes) && !LegalOperations &&
!ST->isVolatile()) ||
- TLI.isOperationLegalOrCustom(ISD::STORE, EVT::i64)) {
+ TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) {
Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
- getZExtValue(), EVT::i64);
+ getZExtValue(), MVT::i64);
return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
Ptr, ST->getSrcValue(),
ST->getSrcValueOffset(), ST->isVolatile(),
ST->getAlignment());
} else if (!ST->isVolatile() &&
- TLI.isOperationLegalOrCustom(ISD::STORE, EVT::i32)) {
+ TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
// Many FP stores are not made apparent until after legalize, e.g. for
// argument passing. Since this is so common, custom legalize the
// 64-bit integer store into two 32-bit stores.
uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
- SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, EVT::i32);
- SDValue Hi = DAG.getConstant(Val >> 32, EVT::i32);
+ SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
+ SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32);
if (TLI.isBigEndian()) std::swap(Lo, Hi);
int SVOffset = ST->getSrcValueOffset();
SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi,
Ptr, ST->getSrcValue(),
SVOffset, isVolatile, Alignment);
- return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), EVT::Other,
+ return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
St0, St1);
}
// Create token to keep both nodes around.
SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
- EVT::Other, Chain, ReplStore);
+ MVT::Other, Chain, ReplStore);
// Don't add users to work list.
return CombineTo(N, Token, false);
Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
N2.getValueType(), SCC);
} else {
- SCC = DAG.getSetCC(N0.getDebugLoc(), EVT::i1, N0, N1, CC);
+ SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC);
Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
N2.getValueType(), SCC);
}
}
// Construct a custom tailored token factor.
- SDValue NewChain = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), EVT::Other,
+ SDValue NewChain = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
&Aliases[0], Aliases.size());
// Make sure the old chain gets cleaned up.
index f4edc1a30fb2f7f540f4f7b6cab8ce7a320e98f6..cf5b90c900a8ed13ff28beaba2c28b653dd505d9 100644 (file)
// Ignore illegal types. We must do this before looking up the value
// in ValueMap because Arguments are given virtual registers regardless
// of whether FastISel can handle them.
- EVT::SimpleValueType VT = RealVT.getSimpleVT();
+ MVT VT = RealVT.getSimpleVT();
if (!TLI.isTypeLegal(VT)) {
- // Promote EVT::i1 to a legal type though, because it's common and easy.
- if (VT == EVT::i1)
+ // Promote MVT::i1 to a legal type though, because it's common and easy.
+ if (VT == MVT::i1)
VT = TLI.getTypeToTransformTo(VT).getSimpleVT();
else
return 0;
///
bool FastISel::SelectBinaryOp(User *I, ISD::NodeType ISDOpcode) {
EVT VT = EVT::getEVT(I->getType(), /*HandleUnknown=*/true);
- if (VT == EVT::Other || !VT.isSimple())
+ if (VT == MVT::Other || !VT.isSimple())
// Unhandled type. Halt "fast" selection and bail.
return false;
// under the assumption that i64 won't be used if the target doesn't
// support it.
if (!TLI.isTypeLegal(VT)) {
- // EVT::i1 is special. Allow AND, OR, or XOR because they
+ // MVT::i1 is special. Allow AND, OR, or XOR because they
// don't require additional zeroing, which makes them easy.
- if (VT == EVT::i1 &&
+ if (VT == MVT::i1 &&
(ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
ISDOpcode == ISD::XOR))
VT = TLI.getTypeToTransformTo(VT);
return false;
const Type *Ty = I->getOperand(0)->getType();
- EVT::SimpleValueType VT = TLI.getPointerTy();
+ MVT VT = TLI.getPointerTy();
for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end();
OI != E; ++OI) {
Value *Idx = *OI;
default: break;
case TargetLowering::Expand: {
EVT VT = (IID == Intrinsic::eh_selector_i32 ?
- EVT::i32 : EVT::i64);
+ MVT::i32 : MVT::i64);
if (MMI) {
if (MBB->isLandingPad())
EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
EVT DstVT = TLI.getValueType(I->getType());
- if (SrcVT == EVT::Other || !SrcVT.isSimple() ||
- DstVT == EVT::Other || !DstVT.isSimple())
+ if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
+ DstVT == MVT::Other || !DstVT.isSimple())
// Unhandled type. Halt "fast" selection and bail.
return false;
// it may be i1 if we're doing a truncate because that's
// easy and somewhat common.
if (!TLI.isTypeLegal(DstVT))
- if (DstVT != EVT::i1 || Opcode != ISD::TRUNCATE)
+ if (DstVT != MVT::i1 || Opcode != ISD::TRUNCATE)
// Unhandled type. Halt "fast" selection and bail.
return false;
// it may be i1 if we're doing zero-extension because that's
// easy and somewhat common.
if (!TLI.isTypeLegal(SrcVT))
- if (SrcVT != EVT::i1 || Opcode != ISD::ZERO_EXTEND)
+ if (SrcVT != MVT::i1 || Opcode != ISD::ZERO_EXTEND)
// Unhandled type. Halt "fast" selection and bail.
return false;
return false;
// If the operand is i1, arrange for the high bits in the register to be zero.
- if (SrcVT == EVT::i1) {
+ if (SrcVT == MVT::i1) {
SrcVT = TLI.getTypeToTransformTo(SrcVT);
InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg);
if (!InputReg)
return false;
}
// If the result is i1, truncate to the target's type for i1 first.
- if (DstVT == EVT::i1)
+ if (DstVT == MVT::i1)
DstVT = TLI.getTypeToTransformTo(DstVT);
unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
EVT DstVT = TLI.getValueType(I->getType());
- if (SrcVT == EVT::Other || !SrcVT.isSimple() ||
- DstVT == EVT::Other || !DstVT.isSimple() ||
+ if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
+ DstVT == MVT::Other || !DstVT.isSimple() ||
!TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
// Unhandled type. Halt "fast" selection and bail.
return false;
FastISel::~FastISel() {}
-unsigned FastISel::FastEmit_(EVT::SimpleValueType, EVT::SimpleValueType,
+unsigned FastISel::FastEmit_(MVT, MVT,
ISD::NodeType) {
return 0;
}
-unsigned FastISel::FastEmit_r(EVT::SimpleValueType, EVT::SimpleValueType,
+unsigned FastISel::FastEmit_r(MVT, MVT,
ISD::NodeType, unsigned /*Op0*/) {
return 0;
}
-unsigned FastISel::FastEmit_rr(EVT::SimpleValueType, EVT::SimpleValueType,
+unsigned FastISel::FastEmit_rr(MVT, MVT,
ISD::NodeType, unsigned /*Op0*/,
unsigned /*Op0*/) {
return 0;
}
-unsigned FastISel::FastEmit_i(EVT::SimpleValueType, EVT::SimpleValueType,
- ISD::NodeType, uint64_t /*Imm*/) {
+unsigned FastISel::FastEmit_i(MVT, MVT, ISD::NodeType, uint64_t /*Imm*/) {
return 0;
}
-unsigned FastISel::FastEmit_f(EVT::SimpleValueType, EVT::SimpleValueType,
+unsigned FastISel::FastEmit_f(MVT, MVT,
ISD::NodeType, ConstantFP * /*FPImm*/) {
return 0;
}
-unsigned FastISel::FastEmit_ri(EVT::SimpleValueType, EVT::SimpleValueType,
+unsigned FastISel::FastEmit_ri(MVT, MVT,
ISD::NodeType, unsigned /*Op0*/,
uint64_t /*Imm*/) {
return 0;
}
-unsigned FastISel::FastEmit_rf(EVT::SimpleValueType, EVT::SimpleValueType,
+unsigned FastISel::FastEmit_rf(MVT, MVT,
ISD::NodeType, unsigned /*Op0*/,
ConstantFP * /*FPImm*/) {
return 0;
}
-unsigned FastISel::FastEmit_rri(EVT::SimpleValueType, EVT::SimpleValueType,
+unsigned FastISel::FastEmit_rri(MVT, MVT,
ISD::NodeType,
unsigned /*Op0*/, unsigned /*Op1*/,
uint64_t /*Imm*/) {
/// to emit an instruction with an immediate operand using FastEmit_ri.
/// If that fails, it materializes the immediate into a register and try
/// FastEmit_rr instead.
-unsigned FastISel::FastEmit_ri_(EVT::SimpleValueType VT, ISD::NodeType Opcode,
+unsigned FastISel::FastEmit_ri_(MVT VT, ISD::NodeType Opcode,
unsigned Op0, uint64_t Imm,
- EVT::SimpleValueType ImmType) {
+ MVT ImmType) {
// First check if immediate type is legal. If not, we can't use the ri form.
unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm);
if (ResultReg != 0)
/// to emit an instruction with a floating-point immediate operand using
/// FastEmit_rf. If that fails, it materializes the immediate into a register
/// and try FastEmit_rr instead.
-unsigned FastISel::FastEmit_rf_(EVT::SimpleValueType VT, ISD::NodeType Opcode,
+unsigned FastISel::FastEmit_rf_(MVT VT, ISD::NodeType Opcode,
unsigned Op0, ConstantFP *FPImm,
- EVT::SimpleValueType ImmType) {
+ MVT ImmType) {
// First check if immediate type is legal. If not, we can't use the rf form.
unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm);
if (ResultReg != 0)
return ResultReg;
}
-unsigned FastISel::FastEmitInst_extractsubreg(EVT::SimpleValueType RetVT,
+unsigned FastISel::FastEmitInst_extractsubreg(MVT RetVT,
unsigned Op0, uint32_t Idx) {
const TargetRegisterClass* RC = MRI.getRegClass(Op0);
/// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
/// with all but the least significant bit set to zero.
-unsigned FastISel::FastEmitZExtFromI1(EVT::SimpleValueType VT, unsigned Op) {
+unsigned FastISel::FastEmitZExtFromI1(MVT VT, unsigned Op) {
return FastEmit_ri(VT, VT, ISD::AND, Op, 1);
}
index de445ed261c8cfdc8f384456bd145b12b4831f93..cc63de37742fc5e66ad899bf118a7a63e9e06ce1 100644 (file)
CodeGenOpt::Level ol)
: TLI(dag.getTargetLoweringInfo()), DAG(dag), OptLevel(ol),
ValueTypeActions(TLI.getValueTypeActions()) {
- assert(EVT::LAST_VALUETYPE <= EVT::MAX_ALLOWED_VALUETYPE &&
+ assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
"Too many value types for ValueTypeActions to hold!");
}
// The chain is usually at the end.
SDValue TheChain(Node, Node->getNumValues()-1);
- if (TheChain.getValueType() != EVT::Other) {
+ if (TheChain.getValueType() != MVT::Other) {
// Sometimes it's at the beginning.
TheChain = SDValue(Node, 0);
- if (TheChain.getValueType() != EVT::Other) {
+ if (TheChain.getValueType() != MVT::Other) {
// Otherwise, hunt for it.
for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
- if (Node->getValueType(i) == EVT::Other) {
+ if (Node->getValueType(i) == MVT::Other) {
TheChain = SDValue(Node, i);
break;
}
// Otherwise, we walked into a node without a chain.
- if (TheChain.getValueType() != EVT::Other)
+ if (TheChain.getValueType() != MVT::Other)
return 0;
}
}
assert(Node && "Didn't find callseq_start for a call??");
if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
- assert(Node->getOperand(0).getValueType() == EVT::Other &&
+ assert(Node->getOperand(0).getValueType() == MVT::Other &&
"Node doesn't have a token chain argument!");
return FindCallStartFromCallEnd(Node->getOperand(0).getNode());
}
EVT VT = CFP->getValueType(0);
ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
if (!UseCP) {
- assert((VT == EVT::f64 || VT == EVT::f32) && "Invalid type expansion");
+ assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
- (VT == EVT::f64) ? EVT::i64 : EVT::i32);
+ (VT == MVT::f64) ? MVT::i64 : MVT::i32);
}
EVT OrigVT = VT;
EVT SVT = VT;
- while (SVT != EVT::f32) {
- SVT = (EVT::SimpleValueType)(SVT.getSimpleVT() - 1);
+ while (SVT != MVT::f32) {
+ SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) &&
// Only do this if the target has a native EXTLOAD instruction from
// smaller type.
MemVT, ST->isVolatile(),
MinAlign(ST->getAlignment(), Offset)));
// The order of the stores doesn't matter - say it with a TokenFactor.
- return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &Stores[0],
+ return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
Stores.size());
}
}
"Unaligned store of unknown type.");
// Get the half-size VT
EVT NewStoredVT =
- (EVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1);
+ (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT().SimpleTy - 1);
int NumBits = NewStoredVT.getSizeInBits();
int IncrementSize = NumBits / 8;
ST->getSrcValue(), SVOffset + IncrementSize,
NewStoredVT, ST->isVolatile(), Alignment);
- return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Store1, Store2);
+ return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
}
/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
NULL, 0, MemVT));
// The order of the stores doesn't matter - say it with a TokenFactor.
- SDValue TF = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &Stores[0],
+ SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
Stores.size());
// Finally, perform the original load only redirected to the stack slot.
SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
- SDValue TF = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo.getValue(1),
+ SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
Hi.getValue(1));
SDValue Ops[] = { Result, TF };
bool isVolatile = ST->isVolatile();
DebugLoc dl = ST->getDebugLoc();
if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
- if (CFP->getValueType(0) == EVT::f32 &&
- getTypeAction(EVT::i32) == Legal) {
+ if (CFP->getValueType(0) == MVT::f32 &&
+ getTypeAction(MVT::i32) == Legal) {
Tmp3 = DAG.getConstant(CFP->getValueAPF().
bitcastToAPInt().zextOrTrunc(32),
- EVT::i32);
+ MVT::i32);
return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
SVOffset, isVolatile, Alignment);
- } else if (CFP->getValueType(0) == EVT::f64) {
+ } else if (CFP->getValueType(0) == MVT::f64) {
// If this target supports 64-bit registers, do a single 64-bit store.
- if (getTypeAction(EVT::i64) == Legal) {
+ if (getTypeAction(MVT::i64) == Legal) {
Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
- zextOrTrunc(64), EVT::i64);
+ zextOrTrunc(64), MVT::i64);
return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
SVOffset, isVolatile, Alignment);
- } else if (getTypeAction(EVT::i32) == Legal && !ST->isVolatile()) {
+ } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
// Otherwise, if the target supports 32-bit registers, use 2 32-bit
// stores. If the target supports neither 32- nor 64-bits, this
// xform is certainly not worth it.
const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
- SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), EVT::i32);
- SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), EVT::i32);
+ SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
+ SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
if (TLI.isBigEndian()) std::swap(Lo, Hi);
Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(),
Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
isVolatile, MinAlign(Alignment, 4U));
- return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo, Hi);
+ return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
}
}
}
case ISD::INTRINSIC_VOID:
case ISD::VAARG:
case ISD::STACKSAVE:
- Action = TLI.getOperationAction(Node->getOpcode(), EVT::Other);
+ Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
break;
case ISD::SINT_TO_FP:
case ISD::UINT_TO_FP:
case ISD::BR_CC:
case ISD::BRCOND:
// Branches tweak the chain to include LastCALLSEQ_END
- Ops[0] = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Ops[0],
+ Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0],
LastCALLSEQ_END);
Ops[0] = LegalizeOp(Ops[0]);
LastCALLSEQ_END = DAG.getEntryNode();
// Merge in the last call, to ensure that this call start after the last
// call ended.
if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
- Tmp1 = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
Tmp1, LastCALLSEQ_END);
Tmp1 = LegalizeOp(Tmp1);
}
Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
// Do not try to legalize the target-specific arguments (#1+), except for
// an optional flag input.
- if (Node->getOperand(Node->getNumOperands()-1).getValueType() != EVT::Flag){
+ if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
if (Tmp1 != Node->getOperand(0)) {
SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
Ops[0] = Tmp1;
// tells the optimizers that those bits are undefined. It would be
// nice to have an effective generic way of getting these benefits...
// Until such a way is found, don't insist on promoting i1 here.
- (SrcVT != EVT::i1 ||
- TLI.getLoadExtAction(ExtType, EVT::i1) == TargetLowering::Promote)) {
+ (SrcVT != MVT::i1 ||
+ TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
// Promote to a byte-sized load if not loading an integral number of
// bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
unsigned NewWidth = SrcVT.getStoreSizeInBits();
// Build a factor node to remember that this load is independent of the
// other one.
- Ch = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo.getValue(1),
+ Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
Hi.getValue(1));
// Move the top bits to the right place.
// Build a factor node to remember that this load is independent of the
// other one.
- Ch = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo.getValue(1),
+ Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
Hi.getValue(1));
// Move the top bits to the right place.
break;
case TargetLowering::Expand:
// f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
- if (SrcVT == EVT::f32 && Node->getValueType(0) == EVT::f64) {
+ if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
LD->getSrcValueOffset(),
LD->isVolatile(), LD->getAlignment());
}
// The order of the stores doesn't matter.
- Result = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo, Hi);
+ Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
} else {
if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
Tmp2 != ST->getBasePtr())
SDValue StoreChain;
if (!Stores.empty()) // Not all undef elements?
- StoreChain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&Stores[0], Stores.size());
else
StoreChain = DAG.getEntryNode();
DebugLoc dl = Node->getDebugLoc();
SDValue Tmp1 = Node->getOperand(0);
SDValue Tmp2 = Node->getOperand(1);
- assert((Tmp2.getValueType() == EVT::f32 ||
- Tmp2.getValueType() == EVT::f64) &&
+ assert((Tmp2.getValueType() == MVT::f32 ||
+ Tmp2.getValueType() == MVT::f64) &&
"Ugly special-cased code!");
// Get the sign bit of the RHS.
SDValue SignBit;
- EVT IVT = Tmp2.getValueType() == EVT::f64 ? EVT::i64 : EVT::i32;
+ EVT IVT = Tmp2.getValueType() == MVT::f64 ? MVT::i64 : MVT::i32;
if (isTypeLegal(IVT)) {
SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, IVT, Tmp2);
} else {
assert(isTypeLegal(TLI.getPointerTy()) &&
- (TLI.getPointerTy() == EVT::i32 ||
- TLI.getPointerTy() == EVT::i64) &&
+ (TLI.getPointerTy() == MVT::i32 ||
+ TLI.getPointerTy() == MVT::i64) &&
"Legal type for load?!");
SDValue StackPtr = DAG.CreateStackTemporary(Tmp2.getValueType());
SDValue StorePtr = StackPtr, LoadPtr = StackPtr;
SDValue Ch =
DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StorePtr, NULL, 0);
- if (Tmp2.getValueType() == EVT::f64 && TLI.isLittleEndian())
+ if (Tmp2.getValueType() == MVT::f64 && TLI.isLittleEndian())
LoadPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(),
LoadPtr, DAG.getIntPtrConstant(4));
SignBit = DAG.getExtLoad(ISD::SEXTLOAD, dl, TLI.getPointerTy(),
- Ch, LoadPtr, NULL, 0, EVT::i32);
+ Ch, LoadPtr, NULL, 0, MVT::i32);
}
SignBit =
DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()),
DebugLoc dl = Node->getDebugLoc();
DwarfWriter *DW = DAG.getDwarfWriter();
bool useDEBUG_LOC = TLI.isOperationLegalOrCustom(ISD::DEBUG_LOC,
- EVT::Other);
- bool useLABEL = TLI.isOperationLegalOrCustom(ISD::DBG_LABEL, EVT::Other);
+ MVT::Other);
+ bool useLABEL = TLI.isOperationLegalOrCustom(ISD::DBG_LABEL, MVT::Other);
const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node);
GlobalVariable *CU_GV = cast<GlobalVariable>(DSP->getCompileUnit());
// A bit self-referential to have DebugLoc on Debug_Loc nodes, but it
// won't hurt anything.
if (useDEBUG_LOC) {
- return DAG.getNode(ISD::DEBUG_LOC, dl, EVT::Other, Node->getOperand(0),
- DAG.getConstant(Line, EVT::i32),
- DAG.getConstant(Col, EVT::i32),
+ return DAG.getNode(ISD::DEBUG_LOC, dl, MVT::Other, Node->getOperand(0),
+ DAG.getConstant(Line, MVT::i32),
+ DAG.getConstant(Col, MVT::i32),
DAG.getSrcValue(CU.getGV()));
} else {
unsigned ID = DW->RecordSourceLine(Line, Col, CU);
RTLIB::Libcall Call_F80,
RTLIB::Libcall Call_PPCF128) {
RTLIB::Libcall LC;
- switch (Node->getValueType(0).getSimpleVT()) {
+ switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unexpected request for libcall!");
- case EVT::f32: LC = Call_F32; break;
- case EVT::f64: LC = Call_F64; break;
- case EVT::f80: LC = Call_F80; break;
- case EVT::ppcf128: LC = Call_PPCF128; break;
+ case MVT::f32: LC = Call_F32; break;
+ case MVT::f64: LC = Call_F64; break;
+ case MVT::f80: LC = Call_F80; break;
+ case MVT::ppcf128: LC = Call_PPCF128; break;
}
return ExpandLibCall(LC, Node, false);
}
RTLIB::Libcall Call_I64,
RTLIB::Libcall Call_I128) {
RTLIB::Libcall LC;
- switch (Node->getValueType(0).getSimpleVT()) {
+ switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unexpected request for libcall!");
- case EVT::i16: LC = Call_I16; break;
- case EVT::i32: LC = Call_I32; break;
- case EVT::i64: LC = Call_I64; break;
- case EVT::i128: LC = Call_I128; break;
+ case MVT::i16: LC = Call_I16; break;
+ case MVT::i32: LC = Call_I32; break;
+ case MVT::i64: LC = Call_I64; break;
+ case MVT::i128: LC = Call_I128; break;
}
return ExpandLibCall(LC, Node, isSigned);
}
SDValue Op0,
EVT DestVT,
DebugLoc dl) {
- if (Op0.getValueType() == EVT::i32) {
+ if (Op0.getValueType() == MVT::i32) {
// simple 32-bit [signed|unsigned] integer to float/double expansion
// Get the stack frame index of a 8 byte buffer.
- SDValue StackSlot = DAG.CreateStackTemporary(EVT::f64);
+ SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
// word offset constant for Hi/Lo address computation
SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
SDValue Op0Mapped;
if (isSigned) {
// constant used to invert sign bit (signed to unsigned mapping)
- SDValue SignBit = DAG.getConstant(0x80000000u, EVT::i32);
- Op0Mapped = DAG.getNode(ISD::XOR, dl, EVT::i32, Op0, SignBit);
+ SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
+ Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
} else {
Op0Mapped = Op0;
}
SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
Op0Mapped, Lo, NULL, 0);
// initial hi portion of constructed double
- SDValue InitialHi = DAG.getConstant(0x43300000u, EVT::i32);
+ SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
// store the hi of the constructed double - biased exponent
SDValue Store2=DAG.getStore(Store1, dl, InitialHi, Hi, NULL, 0);
// load the constructed double
- SDValue Load = DAG.getLoad(EVT::f64, dl, Store2, StackSlot, NULL, 0);
+ SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, NULL, 0);
// FP constant to bias correct the final result
SDValue Bias = DAG.getConstantFP(isSigned ?
BitsToDouble(0x4330000080000000ULL) :
BitsToDouble(0x4330000000000000ULL),
- EVT::f64);
+ MVT::f64);
// subtract the bias
- SDValue Sub = DAG.getNode(ISD::FSUB, dl, EVT::f64, Load, Bias);
+ SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
// final result
SDValue Result;
// handle final rounding
- if (DestVT == EVT::f64) {
+ if (DestVT == MVT::f64) {
// do nothing
Result = Sub;
- } else if (DestVT.bitsLT(EVT::f64)) {
+ } else if (DestVT.bitsLT(MVT::f64)) {
Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
DAG.getIntPtrConstant(0));
- } else if (DestVT.bitsGT(EVT::f64)) {
+ } else if (DestVT.bitsGT(MVT::f64)) {
Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
}
return Result;
// as a negative number. To counteract this, the dynamic code adds an
// offset depending on the data type.
uint64_t FF;
- switch (Op0.getValueType().getSimpleVT()) {
+ switch (Op0.getValueType().getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unsupported integer type!");
- case EVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
- case EVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
- case EVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
- case EVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
+ case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
+ case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
+ case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
+ case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
}
if (TLI.isLittleEndian()) FF <<= 32;
Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
Alignment = std::min(Alignment, 4u);
SDValue FudgeInReg;
- if (DestVT == EVT::f32)
- FudgeInReg = DAG.getLoad(EVT::f32, dl, DAG.getEntryNode(), CPIdx,
+ if (DestVT == MVT::f32)
+ FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
PseudoSourceValue::getConstantPool(), 0,
false, Alignment);
else {
LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
DAG.getEntryNode(), CPIdx,
PseudoSourceValue::getConstantPool(), 0,
- EVT::f32, false, Alignment));
+ MVT::f32, false, Alignment));
}
return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
// Scan for the appropriate larger type to use.
while (1) {
- NewInTy = (EVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
+ NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
assert(NewInTy.isInteger() && "Ran out of possibilities!");
// If the target supports SINT_TO_FP of this type, use it.
// Scan for the appropriate larger type to use.
while (1) {
- NewOutTy = (EVT::SimpleValueType)(NewOutTy.getSimpleVT()+1);
+ NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
assert(NewOutTy.isInteger() && "Ran out of possibilities!");
if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
EVT VT = Op.getValueType();
EVT SHVT = TLI.getShiftAmountTy();
SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
- switch (VT.getSimpleVT()) {
+ switch (VT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unhandled Expand type in BSWAP!");
- case EVT::i16:
+ case MVT::i16:
Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
- case EVT::i32:
+ case MVT::i32:
Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
- case EVT::i64:
+ case MVT::i64:
Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
TLI.getPICJumpTableRelocBase(Table, DAG));
}
- Tmp1 = DAG.getNode(ISD::BRIND, dl, EVT::Other, LD.getValue(1), Addr);
+ Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
Results.push_back(Tmp1);
break;
}
Tmp1 = Node->getOperand(0);
Tmp2 = Node->getOperand(1);
if (Tmp2.getOpcode() == ISD::SETCC) {
- Tmp1 = DAG.getNode(ISD::BR_CC, dl, EVT::Other,
+ Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
Tmp1, Tmp2.getOperand(2),
Tmp2.getOperand(0), Tmp2.getOperand(1),
Node->getOperand(2));
} else {
- Tmp1 = DAG.getNode(ISD::BR_CC, dl, EVT::Other, Tmp1,
+ Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
DAG.getCondCode(ISD::SETNE), Tmp2,
DAG.getConstant(0, Tmp2.getValueType()),
Node->getOperand(2));
diff --git a/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
index ebaf2fb4cc7191664b58fb6adbf1e9d52312d4c9..95927a0f9b71a7e0bed81c340f6d665501ddaadb 100644 (file)
RTLIB::Libcall Call_F80,
RTLIB::Libcall Call_PPCF128) {
return
- VT == EVT::f32 ? Call_F32 :
- VT == EVT::f64 ? Call_F64 :
- VT == EVT::f80 ? Call_F80 :
- VT == EVT::ppcf128 ? Call_PPCF128 :
+ VT == MVT::f32 ? Call_F32 :
+ VT == MVT::f64 ? Call_F64 :
+ VT == MVT::f80 ? Call_F80 :
+ VT == MVT::ppcf128 ? Call_PPCF128 :
RTLIB::UNKNOWN_LIBCALL;
}
}
SDValue DAGTypeLegalizer::SoftenFloatRes_FPOWI(SDNode *N) {
- assert(N->getOperand(1).getValueType() == EVT::i32 &&
+ assert(N->getOperand(1).getValueType() == MVT::i32 &&
"Unsupported power type!");
EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)), N->getOperand(1) };
// a larger type, eg: i8 -> fp. Even if it is legal, no libcall may exactly
// match. Look for an appropriate libcall.
RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
- for (unsigned t = EVT::FIRST_INTEGER_VALUETYPE;
- t <= EVT::LAST_INTEGER_VALUETYPE && LC == RTLIB::UNKNOWN_LIBCALL; ++t) {
- NVT = (EVT::SimpleValueType)t;
+ for (unsigned t = MVT::FIRST_INTEGER_VALUETYPE;
+ t <= MVT::LAST_INTEGER_VALUETYPE && LC == RTLIB::UNKNOWN_LIBCALL; ++t) {
+ NVT = (MVT::SimpleValueType)t;
// The source needs to big enough to hold the operand.
if (NVT.bitsGE(SVT))
LC = Signed ? RTLIB::getSINTTOFP(NVT, RVT):RTLIB::getUINTTOFP (NVT, RVT);
SDValue RHSInt = GetSoftenedFloat(NewRHS);
EVT VT = NewLHS.getValueType();
- assert((VT == EVT::f32 || VT == EVT::f64) && "Unsupported setcc type!");
+ assert((VT == MVT::f32 || VT == MVT::f64) && "Unsupported setcc type!");
// Expand into one or more soft-fp libcall(s).
RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
switch (CCCode) {
case ISD::SETEQ:
case ISD::SETOEQ:
- LC1 = (VT == EVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
+ LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
break;
case ISD::SETNE:
case ISD::SETUNE:
- LC1 = (VT == EVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
+ LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
break;
case ISD::SETGE:
case ISD::SETOGE:
- LC1 = (VT == EVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
+ LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
break;
case ISD::SETLT:
case ISD::SETOLT:
- LC1 = (VT == EVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
+ LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
break;
case ISD::SETLE:
case ISD::SETOLE:
- LC1 = (VT == EVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
+ LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
break;
case ISD::SETGT:
case ISD::SETOGT:
- LC1 = (VT == EVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
+ LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
break;
case ISD::SETUO:
- LC1 = (VT == EVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
+ LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
break;
case ISD::SETO:
- LC1 = (VT == EVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
+ LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
break;
default:
- LC1 = (VT == EVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
+ LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
switch (CCCode) {
case ISD::SETONE:
// SETONE = SETOLT | SETOGT
- LC1 = (VT == EVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
+ LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
// Fallthrough
case ISD::SETUGT:
- LC2 = (VT == EVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
+ LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
break;
case ISD::SETUGE:
- LC2 = (VT == EVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
+ LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
break;
case ISD::SETULT:
- LC2 = (VT == EVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
+ LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
break;
case ISD::SETULE:
- LC2 = (VT == EVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
+ LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
break;
case ISD::SETUEQ:
- LC2 = (VT == EVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
+ LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
break;
default: assert(false && "Do not know how to soften this setcc!");
}
}
- EVT RetVT = EVT::i32; // FIXME: is this the correct return type?
+ EVT RetVT = MVT::i32; // FIXME: is this the correct return type?
SDValue Ops[2] = { LHSInt, RHSInt };
NewLHS = MakeLibCall(LC1, RetVT, Ops, 2, false/*sign irrelevant*/, dl);
NewRHS = DAG.getConstant(0, RetVT);
void DAGTypeLegalizer::ExpandFloatRes_FABS(SDNode *N, SDValue &Lo,
SDValue &Hi) {
- assert(N->getValueType(0) == EVT::ppcf128 &&
+ assert(N->getValueType(0) == MVT::ppcf128 &&
"Logic only correct for ppcf128!");
DebugLoc dl = N->getDebugLoc();
SDValue Tmp;
void DAGTypeLegalizer::ExpandFloatRes_XINT_TO_FP(SDNode *N, SDValue &Lo,
SDValue &Hi) {
- assert(N->getValueType(0) == EVT::ppcf128 && "Unsupported XINT_TO_FP!");
+ assert(N->getValueType(0) == MVT::ppcf128 && "Unsupported XINT_TO_FP!");
EVT VT = N->getValueType(0);
EVT NVT = TLI.getTypeToTransformTo(VT);
SDValue Src = N->getOperand(0);
// First do an SINT_TO_FP, whether the original was signed or unsigned.
// When promoting partial word types to i32 we must honor the signedness,
// though.
- if (SrcVT.bitsLE(EVT::i32)) {
+ if (SrcVT.bitsLE(MVT::i32)) {
// The integer can be represented exactly in an f64.
Src = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl,
- EVT::i32, Src);
+ MVT::i32, Src);
Lo = DAG.getConstantFP(APFloat(APInt(NVT.getSizeInBits(), 0)), NVT);
Hi = DAG.getNode(ISD::SINT_TO_FP, dl, NVT, Src);
} else {
RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
- if (SrcVT.bitsLE(EVT::i64)) {
+ if (SrcVT.bitsLE(MVT::i64)) {
Src = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl,
- EVT::i64, Src);
+ MVT::i64, Src);
LC = RTLIB::SINTTOFP_I64_PPCF128;
- } else if (SrcVT.bitsLE(EVT::i128)) {
- Src = DAG.getNode(ISD::SIGN_EXTEND, dl, EVT::i128, Src);
+ } else if (SrcVT.bitsLE(MVT::i128)) {
+ Src = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i128, Src);
LC = RTLIB::SINTTOFP_I128_PPCF128;
}
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XINT_TO_FP!");
static const uint64_t TwoE128[] = { 0x47f0000000000000LL, 0 };
const uint64_t *Parts = 0;
- switch (SrcVT.getSimpleVT()) {
+ switch (SrcVT.getSimpleVT().SimpleTy) {
default:
assert(false && "Unsupported UINT_TO_FP!");
- case EVT::i32:
+ case MVT::i32:
Parts = TwoE32;
break;
- case EVT::i64:
+ case MVT::i64:
Parts = TwoE64;
break;
- case EVT::i128:
+ case MVT::i128:
Parts = TwoE128;
break;
}
Lo = DAG.getNode(ISD::FADD, dl, VT, Hi,
DAG.getConstantFP(APFloat(APInt(128, 2, Parts)),
- EVT::ppcf128));
+ MVT::ppcf128));
Lo = DAG.getNode(ISD::SELECT_CC, dl, VT, Src, DAG.getConstant(0, SrcVT),
Lo, Hi, DAG.getCondCode(ISD::SETLT));
GetPairElements(Lo, Lo, Hi);
GetExpandedFloat(NewRHS, RHSLo, RHSHi);
EVT VT = NewLHS.getValueType();
- assert(VT == EVT::ppcf128 && "Unsupported setcc type!");
+ assert(VT == MVT::ppcf128 && "Unsupported setcc type!");
// FIXME: This generated code sucks. We want to generate
// FCMPU crN, hi1, hi2
}
SDValue DAGTypeLegalizer::ExpandFloatOp_FP_ROUND(SDNode *N) {
- assert(N->getOperand(0).getValueType() == EVT::ppcf128 &&
+ assert(N->getOperand(0).getValueType() == MVT::ppcf128 &&
"Logic only correct for ppcf128!");
SDValue Lo, Hi;
GetExpandedFloat(N->getOperand(0), Lo, Hi);
// Expand ppcf128 to i32 by hand for the benefit of llvm-gcc bootstrap on
// PPC (the libcall is not available). FIXME: Do this in a less hacky way.
- if (RVT == EVT::i32) {
- assert(N->getOperand(0).getValueType() == EVT::ppcf128 &&
+ if (RVT == MVT::i32) {
+ assert(N->getOperand(0).getValueType() == MVT::ppcf128 &&
"Logic only correct for ppcf128!");
- SDValue Res = DAG.getNode(ISD::FP_ROUND_INREG, dl, EVT::ppcf128,
- N->getOperand(0), DAG.getValueType(EVT::f64));
- Res = DAG.getNode(ISD::FP_ROUND, dl, EVT::f64, Res,
+ SDValue Res = DAG.getNode(ISD::FP_ROUND_INREG, dl, MVT::ppcf128,
+ N->getOperand(0), DAG.getValueType(MVT::f64));
+ Res = DAG.getNode(ISD::FP_ROUND, dl, MVT::f64, Res,
DAG.getIntPtrConstant(1));
- return DAG.getNode(ISD::FP_TO_SINT, dl, EVT::i32, Res);
+ return DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Res);
}
RTLIB::Libcall LC = RTLIB::getFPTOSINT(N->getOperand(0).getValueType(), RVT);
// Expand ppcf128 to i32 by hand for the benefit of llvm-gcc bootstrap on
// PPC (the libcall is not available). FIXME: Do this in a less hacky way.
- if (RVT == EVT::i32) {
- assert(N->getOperand(0).getValueType() == EVT::ppcf128 &&
+ if (RVT == MVT::i32) {
+ assert(N->getOperand(0).getValueType() == MVT::ppcf128 &&
"Logic only correct for ppcf128!");
const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
APFloat APF = APFloat(APInt(128, 2, TwoE31));
- SDValue Tmp = DAG.getConstantFP(APF, EVT::ppcf128);
+ SDValue Tmp = DAG.getConstantFP(APF, MVT::ppcf128);
// X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
// FIXME: generated code sucks.
- return DAG.getNode(ISD::SELECT_CC, dl, EVT::i32, N->getOperand(0), Tmp,
- DAG.getNode(ISD::ADD, dl, EVT::i32,
- DAG.getNode(ISD::FP_TO_SINT, dl, EVT::i32,
+ return DAG.getNode(ISD::SELECT_CC, dl, MVT::i32, N->getOperand(0), Tmp,
+ DAG.getNode(ISD::ADD, dl, MVT::i32,
+ DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32,
DAG.getNode(ISD::FSUB, dl,
- EVT::ppcf128,
+ MVT::ppcf128,
N->getOperand(0),
Tmp)),
- DAG.getConstant(0x80000000, EVT::i32)),
+ DAG.getConstant(0x80000000, MVT::i32)),
DAG.getNode(ISD::FP_TO_SINT, dl,
- EVT::i32, N->getOperand(0)),
+ MVT::i32, N->getOperand(0)),
DAG.getCondCode(ISD::SETGE));
}
diff --git a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index b1b2ae3e5cda0de54cc5a578750cfcaba8e8d724..3d7143259323ac84d22c24d8669cd1f0b53ddd74 100644 (file)
assert(OpNo == 1 && "only know how to promote condition");
// Promote all the way up to the canonical SetCC type.
- EVT SVT = TLI.getSetCCResultType(EVT::Other);
+ EVT SVT = TLI.getSetCCResultType(MVT::Other);
SDValue Cond = PromoteTargetBoolean(N->getOperand(1), SVT);
// The chain (Op#0) and basic block destination (Op#2) are always legal types.
NewOps[0] = N->getOperand(0);
for (unsigned i = 1; i < array_lengthof(NewOps); ++i) {
SDValue Flag = GetPromotedInteger(N->getOperand(i));
- NewOps[i] = DAG.getZeroExtendInReg(Flag, dl, EVT::i1);
+ NewOps[i] = DAG.getZeroExtendInReg(Flag, dl, MVT::i1);
}
return DAG.UpdateNodeOperands(SDValue (N, 0), NewOps,
array_lengthof(NewOps));
TLI.isOperationLegalOrCustom(ISD::ADDC,
TLI.getTypeToExpandTo(NVT))) {
// Emit this X << 1 as X+X.
- SDVTList VTList = DAG.getVTList(NVT, EVT::Flag);
+ SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
SDValue LoOps[2] = { InL, InL };
Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
// Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
// them. TODO: Teach operation legalization how to expand unsupported
// ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
- // a carry of type EVT::Flag, but there doesn't seem to be any way to
+ // a carry of type MVT::Flag, but there doesn't seem to be any way to
// generate a value of this type in the expanded code sequence.
bool hasCarry =
TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
TLI.getTypeToExpandTo(NVT));
if (hasCarry) {
- SDVTList VTList = DAG.getVTList(NVT, EVT::Flag);
+ SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
if (N->getOpcode() == ISD::ADD) {
Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
HiOps[2] = Lo.getValue(1);
DebugLoc dl = N->getDebugLoc();
GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
- SDVTList VTList = DAG.getVTList(LHSL.getValueType(), EVT::Flag);
+ SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
SDValue LoOps[2] = { LHSL, RHSL };
SDValue HiOps[3] = { LHSH, RHSH };
DebugLoc dl = N->getDebugLoc();
GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
- SDVTList VTList = DAG.getVTList(LHSL.getValueType(), EVT::Flag);
+ SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
SDValue HiOps[3] = { LHSH, RHSH };
// Build a factor node to remember that this load is independent of the
// other one.
- Ch = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo.getValue(1),
+ Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
Hi.getValue(1));
} else {
// Big-endian - high bits are at low addresses. Favor aligned loads at
// Build a factor node to remember that this load is independent of the
// other one.
- Ch = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo.getValue(1),
+ Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
Hi.getValue(1));
if (ExcessBits < NVT.getSizeInBits()) {
// If nothing else, we can make a libcall.
RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
- if (VT == EVT::i16)
+ if (VT == MVT::i16)
LC = RTLIB::MUL_I16;
- else if (VT == EVT::i32)
+ else if (VT == MVT::i32)
LC = RTLIB::MUL_I32;
- else if (VT == EVT::i64)
+ else if (VT == MVT::i64)
LC = RTLIB::MUL_I64;
- else if (VT == EVT::i128)
+ else if (VT == MVT::i128)
LC = RTLIB::MUL_I128;
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
DebugLoc dl = N->getDebugLoc();
RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
- if (VT == EVT::i16)
+ if (VT == MVT::i16)
LC = RTLIB::SDIV_I16;
- else if (VT == EVT::i32)
+ else if (VT == MVT::i32)
LC = RTLIB::SDIV_I32;
- else if (VT == EVT::i64)
+ else if (VT == MVT::i64)
LC = RTLIB::SDIV_I64;
- else if (VT == EVT::i128)
+ else if (VT == MVT::i128)
LC = RTLIB::SDIV_I128;
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
bool isSigned;
if (N->getOpcode() == ISD::SHL) {
isSigned = false; /*sign irrelevant*/
- if (VT == EVT::i16)
+ if (VT == MVT::i16)
LC = RTLIB::SHL_I16;
- else if (VT == EVT::i32)
+ else if (VT == MVT::i32)
LC = RTLIB::SHL_I32;
- else if (VT == EVT::i64)
+ else if (VT == MVT::i64)
LC = RTLIB::SHL_I64;
- else if (VT == EVT::i128)
+ else if (VT == MVT::i128)
LC = RTLIB::SHL_I128;
} else if (N->getOpcode() == ISD::SRL) {
isSigned = false;
- if (VT == EVT::i16)
+ if (VT == MVT::i16)
LC = RTLIB::SRL_I16;
- else if (VT == EVT::i32)
+ else if (VT == MVT::i32)
LC = RTLIB::SRL_I32;
- else if (VT == EVT::i64)
+ else if (VT == MVT::i64)
LC = RTLIB::SRL_I64;
- else if (VT == EVT::i128)
+ else if (VT == MVT::i128)
LC = RTLIB::SRL_I128;
} else {
assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
isSigned = true;
- if (VT == EVT::i16)
+ if (VT == MVT::i16)
LC = RTLIB::SRA_I16;
- else if (VT == EVT::i32)
+ else if (VT == MVT::i32)
LC = RTLIB::SRA_I32;
- else if (VT == EVT::i64)
+ else if (VT == MVT::i64)
LC = RTLIB::SRA_I64;
- else if (VT == EVT::i128)
+ else if (VT == MVT::i128)
LC = RTLIB::SRA_I128;
}
DebugLoc dl = N->getDebugLoc();
RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
- if (VT == EVT::i16)
+ if (VT == MVT::i16)
LC = RTLIB::SREM_I16;
- else if (VT == EVT::i32)
+ else if (VT == MVT::i32)
LC = RTLIB::SREM_I32;
- else if (VT == EVT::i64)
+ else if (VT == MVT::i64)
LC = RTLIB::SREM_I64;
- else if (VT == EVT::i128)
+ else if (VT == MVT::i128)
LC = RTLIB::SREM_I128;
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
DebugLoc dl = N->getDebugLoc();
RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
- if (VT == EVT::i16)
+ if (VT == MVT::i16)
LC = RTLIB::UDIV_I16;
- else if (VT == EVT::i32)
+ else if (VT == MVT::i32)
LC = RTLIB::UDIV_I32;
- else if (VT == EVT::i64)
+ else if (VT == MVT::i64)
LC = RTLIB::UDIV_I64;
- else if (VT == EVT::i128)
+ else if (VT == MVT::i128)
LC = RTLIB::UDIV_I128;
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
DebugLoc dl = N->getDebugLoc();
RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
- if (VT == EVT::i16)
+ if (VT == MVT::i16)
LC = RTLIB::UREM_I16;
- else if (VT == EVT::i32)
+ else if (VT == MVT::i32)
LC = RTLIB::UREM_I32;
- else if (VT == EVT::i64)
+ else if (VT == MVT::i64)
LC = RTLIB::UREM_I64;
- else if (VT == EVT::i128)
+ else if (VT == MVT::i128)
LC = RTLIB::UREM_I128;
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getSrcValue(),
SVOffset+IncrementSize, NEVT,
isVolatile, MinAlign(Alignment, IncrementSize));
- return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo, Hi);
+ return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
} else {
// Big-endian - high bits are at low addresses. Favor aligned stores at
// the cost of some bit-fiddling.
SVOffset+IncrementSize,
EVT::getIntegerVT(ExcessBits),
isVolatile, MinAlign(Alignment, IncrementSize));
- return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo, Hi);
+ return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
}
}
const uint64_t F32TwoE128 = 0x7F800000ULL;
APInt FF(32, 0);
- if (SrcVT == EVT::i32)
+ if (SrcVT == MVT::i32)
FF = APInt(32, F32TwoE32);
- else if (SrcVT == EVT::i64)
+ else if (SrcVT == MVT::i64)
FF = APInt(32, F32TwoE64);
- else if (SrcVT == EVT::i128)
+ else if (SrcVT == MVT::i128)
FF = APInt(32, F32TwoE128);
else
assert(false && "Unsupported UINT_TO_FP!");
// Load the value out, extending it from f32 to the destination float type.
// FIXME: Avoid the extend by constructing the right constant pool?
SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(),
- FudgePtr, NULL, 0, EVT::f32,
+ FudgePtr, NULL, 0, MVT::f32,
false, Alignment);
return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge);
}
index 8801ceec9005376083b9e07a2f0cf17294e3e8fc..195b9f258cb444c44a44d4fed3cc53b3c6d534df 100644 (file)
explicit DAGTypeLegalizer(SelectionDAG &dag)
: TLI(dag.getTargetLoweringInfo()), DAG(dag),
ValueTypeActions(TLI.getValueTypeActions()) {
- assert(EVT::LAST_VALUETYPE <= EVT::MAX_ALLOWED_VALUETYPE &&
+ assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
"Too many value types for ValueTypeActions to hold!");
}
diff --git a/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp b/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
index 8533866a075dbd1e159ea21f093cb5ae1e20d211..0760c6326fc3cd44f3a74118b348b8e69efd4362 100644 (file)
// Build a factor node to remember that this load is independent of the
// other one.
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo.getValue(1),
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
Hi.getValue(1));
// Handle endianness of the load.
SVOffset + IncrementSize,
isVolatile, MinAlign(Alignment, IncrementSize));
- return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo, Hi);
+ return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
}
diff --git a/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
index aa647fde1b1a42d8c8b759d8a2f340a472afaf8f..ca194305d9898a7ac246f3e1d38dfc2369198932 100644 (file)
Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
OperandEltVT,
Operand,
- DAG.getConstant(i, EVT::i32));
+ DAG.getConstant(i, MVT::i32));
} else {
// A scalar operand; just use it as is.
Operands[j] = Operand;
diff --git a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index a10d167579db85efb711d7af4f587700f9037820..1600b900d0dd2e6a2c1471b522c0a191fd217739 100644 (file)
DebugLoc DL = N->getDebugLoc();
// Turn it into a scalar SETCC.
- return DAG.getNode(ISD::SETCC, DL, EVT::i1, LHS, RHS, N->getOperand(2));
+ return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
}
SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
if (TLI.getBooleanContents() !=
TargetLowering::ZeroOrNegativeOneBooleanContent)
Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, SVT, Res,
- DAG.getValueType(EVT::i1));
+ DAG.getValueType(MVT::i1));
// Truncate to the final type.
return DAG.getNode(ISD::TRUNCATE, DL, NVT, Res);
}
// The SETCC result type is smaller than the vector element type.
- // If the SetCC result is not sign-extended, chop it down to EVT::i1.
+ // If the SetCC result is not sign-extended, chop it down to MVT::i1.
if (TLI.getBooleanContents() !=
TargetLowering::ZeroOrNegativeOneBooleanContent)
- Res = DAG.getNode(ISD::TRUNCATE, DL, EVT::i1, Res);
+ Res = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Res);
// Sign extend to the final type.
return DAG.getNode(ISD::SIGN_EXTEND, DL, NVT, Res);
}
// Build a factor node to remember that this load is independent of the
// other one.
- Ch = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo.getValue(1),
+ Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
Hi.getValue(1));
// Legalized the chain result - switch anything that used the old chain to
Hi = DAG.getStore(Ch, dl, Hi, Ptr, N->getSrcValue(), SVOffset+IncrementSize,
isVol, MinAlign(Alignment, IncrementSize));
- return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo, Hi);
+ return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
}
if (LdChain.size() == 1)
NewChain = LdChain[0];
else
- NewChain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &LdChain[0],
+ NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &LdChain[0],
LdChain.size());
// Modified the chain - switch anything that used the old chain to use
return StChain[0];
else
return DAG.getNode(ISD::TokenFactor, dl,
- EVT::Other,&StChain[0],StChain.size());
+ MVT::Other,&StChain[0],StChain.size());
}
//===----------------------------------------------------------------------===//
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
index ee83f068e17f25b502b5d57a8777376dc48bdd70..fda1610b983bc8ac24e6fc20c496f161e29fd2bf 100644 (file)
bool TryUnfold = false;
for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
EVT VT = N->getValueType(i);
- if (VT == EVT::Flag)
+ if (VT == MVT::Flag)
return NULL;
- else if (VT == EVT::Other)
+ else if (VT == MVT::Other)
TryUnfold = true;
}
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
const SDValue &Op = N->getOperand(i);
EVT VT = Op.getNode()->getValueType(Op.getResNo());
- if (VT == EVT::Flag)
+ if (VT == MVT::Flag)
return NULL;
}
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index 5c7b8499e6c462976e6b462219a351288003bec6..26da246c412af2f72ceb381ab0229f5691662946 100644 (file)
bool TryUnfold = false;
for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
EVT VT = N->getValueType(i);
- if (VT == EVT::Flag)
+ if (VT == MVT::Flag)
return NULL;
- else if (VT == EVT::Other)
+ else if (VT == MVT::Other)
TryUnfold = true;
}
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
const SDValue &Op = N->getOperand(i);
EVT VT = Op.getNode()->getValueType(Op.getResNo());
- if (VT == EVT::Flag)
+ if (VT == MVT::Flag)
return NULL;
}
if (Node->getOpcode() == ISD::INLINEASM) {
// Inline asm can clobber physical defs.
unsigned NumOps = Node->getNumOperands();
- if (Node->getOperand(NumOps-1).getValueType() == EVT::Flag)
+ if (Node->getOperand(NumOps-1).getValueType() == MVT::Flag)
--NumOps; // Ignore the flag operand.
for (unsigned i = 2; i != NumOps;) {
return false;
for (unsigned i = NumDefs, e = N->getNumValues(); i != e; ++i) {
EVT VT = N->getValueType(i);
- if (VT == EVT::Flag || VT == EVT::Other)
+ if (VT == MVT::Flag || VT == MVT::Other)
continue;
if (!N->hasAnyUseOfValue(i))
continue;
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
index 4d2882a884e54f0c84cf9e2dfc530f12f2f5f4b0..0b0aa269b6f641cf7445c0490e7bb0a6471002ba 100644 (file)
// Scan up to find flagged preds.
SDNode *N = NI;
while (N->getNumOperands() &&
- N->getOperand(N->getNumOperands()-1).getValueType() == EVT::Flag) {
+ N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) {
N = N->getOperand(N->getNumOperands()-1).getNode();
assert(N->getNodeId() == -1 && "Node already inserted!");
N->setNodeId(NodeSUnit->NodeNum);
// Scan down to find any flagged succs.
N = NI;
- while (N->getValueType(N->getNumValues()-1) == EVT::Flag) {
+ while (N->getValueType(N->getNumValues()-1) == MVT::Flag) {
SDValue FlagVal(N, N->getNumValues()-1);
// There are either zero or one users of the Flag result.
if (OpSU == SU) continue; // In the same group.
EVT OpVT = N->getOperand(i).getValueType();
- assert(OpVT != EVT::Flag && "Flagged nodes should be in same sunit!");
- bool isChain = OpVT == EVT::Other;
+ assert(OpVT != MVT::Flag && "Flagged nodes should be in same sunit!");
+ bool isChain = OpVT == MVT::Other;
unsigned PhysReg = 0;
int Cost = 1;
/// not go into the resulting MachineInstr).
unsigned ScheduleDAGSDNodes::CountResults(SDNode *Node) {
unsigned N = Node->getNumValues();
- while (N && Node->getValueType(N - 1) == EVT::Flag)
+ while (N && Node->getValueType(N - 1) == MVT::Flag)
--N;
- if (N && Node->getValueType(N - 1) == EVT::Other)
+ if (N && Node->getValueType(N - 1) == MVT::Other)
--N; // Skip over chain result.
return N;
}
/// operand
unsigned ScheduleDAGSDNodes::ComputeMemOperandsEnd(SDNode *Node) {
unsigned N = Node->getNumOperands();
- while (N && Node->getOperand(N - 1).getValueType() == EVT::Flag)
+ while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag)
--N;
- if (N && Node->getOperand(N - 1).getValueType() == EVT::Other)
+ if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
--N; // Ignore chain if it exists.
return N;
}
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
index d8736a12adad4be0ef8e5431d2db55755ef260a5..12b5d143f8f25efb1abdc14262bf2f1308832ca4 100644 (file)
if (Op.getNode() != Node || Op.getResNo() != ResNo)
continue;
EVT VT = Node->getValueType(Op.getResNo());
- if (VT == EVT::Other || VT == EVT::Flag)
+ if (VT == MVT::Other || VT == MVT::Flag)
continue;
Match = false;
if (User->isMachineOpcode()) {
unsigned IIOpNum,
const TargetInstrDesc *II,
DenseMap<SDValue, unsigned> &VRBaseMap) {
- assert(Op.getValueType() != EVT::Other &&
- Op.getValueType() != EVT::Flag &&
+ assert(Op.getValueType() != MVT::Other &&
+ Op.getValueType() != MVT::Flag &&
"Chain and flag operands should occur at end of operand list!");
// Get/emit the operand.
unsigned VReg = getVR(Op, VRBaseMap);
MI->addOperand(MachineOperand::CreateES(ES->getSymbol(), 0,
ES->getTargetFlags()));
} else {
- assert(Op.getValueType() != EVT::Other &&
- Op.getValueType() != EVT::Flag &&
+ assert(Op.getValueType() != MVT::Other &&
+ Op.getValueType() != MVT::Flag &&
"Chain and flag operands should occur at end of operand list!");
AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap);
}
}
case ISD::INLINEASM: {
unsigned NumOps = Node->getNumOperands();
- if (Node->getOperand(NumOps-1).getValueType() == EVT::Flag)
+ if (Node->getOperand(NumOps-1).getValueType() == MVT::Flag)
--NumOps; // Ignore the flag operand.
// Create the inline asm machine instruction.
index afb5d948776dff9f99a8e7018942d46c17681dd5..5b5558ab97af5d11f297b493c9a61a618f822095 100644 (file)
}
static const fltSemantics *EVTToAPFloatSemantics(EVT VT) {
- switch (VT.getSimpleVT()) {
+ switch (VT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unknown FP format");
- case EVT::f32: return &APFloat::IEEEsingle;
- case EVT::f64: return &APFloat::IEEEdouble;
- case EVT::f80: return &APFloat::x87DoubleExtended;
- case EVT::f128: return &APFloat::IEEEquad;
- case EVT::ppcf128: return &APFloat::PPCDoubleDouble;
+ case MVT::f32: return &APFloat::IEEEsingle;
+ case MVT::f64: return &APFloat::IEEEdouble;
+ case MVT::f80: return &APFloat::x87DoubleExtended;
+ case MVT::f128: return &APFloat::IEEEquad;
+ case MVT::ppcf128: return &APFloat::PPCDoubleDouble;
}
}
assert(VT.isFloatingPoint() && "Can only convert between FP types");
// PPC long double cannot be converted to any other type.
- if (VT == EVT::ppcf128 ||
+ if (VT == MVT::ppcf128 ||
&Val.getSemantics() == &APFloat::PPCDoubleDouble)
return false;
/// doNotCSE - Return true if CSE should not be performed for this node.
static bool doNotCSE(SDNode *N) {
- if (N->getValueType(0) == EVT::Flag)
+ if (N->getValueType(0) == MVT::Flag)
return true; // Never CSE anything that produces a flag.
switch (N->getOpcode()) {
// Check that remaining values produced are not flags.
for (unsigned i = 1, e = N->getNumValues(); i != e; ++i)
- if (N->getValueType(i) == EVT::Flag)
+ if (N->getValueType(i) == MVT::Flag)
return true; // Never CSE anything that produces a flag.
return false;
if (VT.isExtended()) {
Erased = ExtendedValueTypeNodes.erase(VT);
} else {
- Erased = ValueTypeNodes[VT.getSimpleVT()] != 0;
- ValueTypeNodes[VT.getSimpleVT()] = 0;
+ Erased = ValueTypeNodes[VT.getSimpleVT().SimpleTy] != 0;
+ ValueTypeNodes[VT.getSimpleVT().SimpleTy] = 0;
}
break;
}
// Verify that the node was actually in one of the CSE maps, unless it has a
// flag result (which cannot be CSE'd) or is one of the special cases that are
// not subject to CSE.
- if (!Erased && N->getValueType(N->getNumValues()-1) != EVT::Flag &&
+ if (!Erased && N->getValueType(N->getNumValues()-1) != MVT::Flag &&
!N->isMachineOpcode() && !doNotCSE(N)) {
N->dump(this);
cerr << "\n";
/// given type.
///
unsigned SelectionDAG::getEVTAlignment(EVT VT) const {
- const Type *Ty = VT == EVT::iPTR ?
+ const Type *Ty = VT == MVT::iPTR ?
PointerType::get(Type::Int8Ty, 0) :
VT.getTypeForEVT();
SelectionDAG::SelectionDAG(TargetLowering &tli, FunctionLoweringInfo &fli)
: TLI(tli), FLI(fli), DW(0),
EntryNode(ISD::EntryToken, DebugLoc::getUnknownLoc(),
- getVTList(EVT::Other)), Root(getEntryNode()) {
+ getVTList(MVT::Other)), Root(getEntryNode()) {
AllNodes.push_back(&EntryNode);
}
@@ -950,7 +950,7 @@ SDValue SelectionDAG::getConstantFP(const ConstantFP& V, EVT VT, bool isTarget){
SDValue SelectionDAG::getConstantFP(double Val, EVT VT, bool isTarget) {
EVT EltVT =
VT.isVector() ? VT.getVectorElementType() : VT;
- if (EltVT==EVT::f32)
+ if (EltVT==MVT::f32)
return getConstantFP(APFloat((float)Val), VT, isTarget);
else
return getConstantFP(APFloat(Val), VT, isTarget);
SDValue SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) {
FoldingSetNodeID ID;
- AddNodeIDNode(ID, ISD::BasicBlock, getVTList(EVT::Other), 0, 0);
+ AddNodeIDNode(ID, ISD::BasicBlock, getVTList(MVT::Other), 0, 0);
ID.AddPointer(MBB);
void *IP = 0;
if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
}
SDValue SelectionDAG::getValueType(EVT VT) {
- if (VT.isSimple() && (unsigned)VT.getSimpleVT() >= ValueTypeNodes.size())
- ValueTypeNodes.resize(VT.getSimpleVT()+1);
+ if (VT.isSimple() && (unsigned)VT.getSimpleVT().SimpleTy >=
+ ValueTypeNodes.size())
+ ValueTypeNodes.resize(VT.getSimpleVT().SimpleTy+1);
SDNode *&N = VT.isExtended() ?
- ExtendedValueTypeNodes[VT] : ValueTypeNodes[VT.getSimpleVT()];
+ ExtendedValueTypeNodes[VT] : ValueTypeNodes[VT.getSimpleVT().SimpleTy];
if (N) return SDValue(N, 0);
N = NodeAllocator.Allocate<VTSDNode>();
unsigned LabelID) {
FoldingSetNodeID ID;
SDValue Ops[] = { Root };
- AddNodeIDNode(ID, Opcode, getVTList(EVT::Other), &Ops[0], 1);
+ AddNodeIDNode(ID, Opcode, getVTList(MVT::Other), &Ops[0], 1);
ID.AddInteger(LabelID);
void *IP = 0;
if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
"SrcValue is not a pointer?");
FoldingSetNodeID ID;
- AddNodeIDNode(ID, ISD::SRCVALUE, getVTList(EVT::Other), 0, 0);
+ AddNodeIDNode(ID, ISD::SRCVALUE, getVTList(MVT::Other), 0, 0);
ID.AddPointer(V);
void *IP = 0;
#endif
FoldingSetNodeID ID;
- AddNodeIDNode(ID, ISD::MEMOPERAND, getVTList(EVT::Other), 0, 0);
+ AddNodeIDNode(ID, ISD::MEMOPERAND, getVTList(MVT::Other), 0, 0);
MO.Profile(ID);
void *IP = 0;
if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.getNode())) {
// No compile time operations on this type yet.
- if (N1C->getValueType(0) == EVT::ppcf128)
+ if (N1C->getValueType(0) == MVT::ppcf128)
return SDValue();
APFloat::cmpResult R = N1C->getValueAPF().compare(N2C->getValueAPF());
case ISD::SINT_TO_FP: {
const uint64_t zero[] = {0, 0};
// No compile time operations on this type.
- if (VT==EVT::ppcf128)
+ if (VT==MVT::ppcf128)
break;
APFloat apf = APFloat(APInt(BitWidth, 2, zero));
(void)apf.convertFromAPInt(Val,
return getConstantFP(apf, VT);
}
case ISD::BIT_CONVERT:
- if (VT == EVT::f32 && C->getValueType(0) == EVT::i32)
+ if (VT == MVT::f32 && C->getValueType(0) == MVT::i32)
return getConstantFP(Val.bitsToFloat(), VT);
- else if (VT == EVT::f64 && C->getValueType(0) == EVT::i64)
+ else if (VT == MVT::f64 && C->getValueType(0) == MVT::i64)
return getConstantFP(Val.bitsToDouble(), VT);
break;
case ISD::BSWAP:
// Constant fold unary operations with a floating point constant operand.
if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Operand.getNode())) {
APFloat V = C->getValueAPF(); // make copy
- if (VT != EVT::ppcf128 && Operand.getValueType() != EVT::ppcf128) {
+ if (VT != MVT::ppcf128 && Operand.getValueType() != MVT::ppcf128) {
switch (Opcode) {
case ISD::FNEG:
V.changeSign();
return getConstant(api, VT);
}
case ISD::BIT_CONVERT:
- if (VT == EVT::i32 && C->getValueType(0) == EVT::f32)
+ if (VT == MVT::i32 && C->getValueType(0) == MVT::f32)
return getConstant((uint32_t)V.bitcastToAPInt().getZExtValue(), VT);
- else if (VT == EVT::i64 && C->getValueType(0) == EVT::f64)
+ else if (VT == MVT::i64 && C->getValueType(0) == MVT::f64)
return getConstant(V.bitcastToAPInt().getZExtValue(), VT);
break;
}
SDNode *N;
SDVTList VTs = getVTList(VT);
- if (VT != EVT::Flag) { // Don't CSE flag producing nodes
+ if (VT != MVT::Flag) { // Don't CSE flag producing nodes
FoldingSetNodeID ID;
SDValue Ops[1] = { Operand };
AddNodeIDNode(ID, Opcode, VTs, Ops, 1);
switch (Opcode) {
default: break;
case ISD::TokenFactor:
- assert(VT == EVT::Other && N1.getValueType() == EVT::Other &&
- N2.getValueType() == EVT::Other && "Invalid token factor!");
+ assert(VT == MVT::Other && N1.getValueType() == MVT::Other &&
+ N2.getValueType() == MVT::Other && "Invalid token factor!");
// Fold trivial token factors.
if (N1.getOpcode() == ISD::EntryToken) return N2;
if (N2.getOpcode() == ISD::EntryToken) return N1;
// Always fold shifts of i1 values so the code generator doesn't need to
// handle them. Since we know the size of the shift has to be less than the
// size of the value, the shift/rotate count is guaranteed to be zero.
- if (VT == EVT::i1)
+ if (VT == MVT::i1)
return N1;
break;
case ISD::FP_ROUND_INREG: {
// Cannonicalize constant to RHS if commutative
std::swap(N1CFP, N2CFP);
std::swap(N1, N2);
- } else if (N2CFP && VT != EVT::ppcf128) {
+ } else if (N2CFP && VT != MVT::ppcf128) {
APFloat V1 = N1CFP->getValueAPF(), V2 = N2CFP->getValueAPF();
APFloat::opStatus s;
switch (Opcode) {
// Memoize this node if possible.
SDNode *N;
SDVTList VTs = getVTList(VT);
- if (VT != EVT::Flag) {
+ if (VT != MVT::Flag) {
SDValue Ops[] = { N1, N2 };
FoldingSetNodeID ID;
AddNodeIDNode(ID, Opcode, VTs, Ops, 2);
case ISD::BRCOND:
if (N2C) {
if (N2C->getZExtValue()) // Unconditional branch
- return getNode(ISD::BR, DL, EVT::Other, N1, N3);
+ return getNode(ISD::BR, DL, MVT::Other, N1, N3);
else
return N1; // Never-taken branch
}
// Memoize node if it doesn't produce a flag.
SDNode *N;
SDVTList VTs = getVTList(VT);
- if (VT != EVT::Flag) {
+ if (VT != MVT::Flag) {
SDValue Ops[] = { N1, N2, N3 };
FoldingSetNodeID ID;
AddNodeIDNode(ID, Opcode, VTs, Ops, 3);
ArgChains.push_back(SDValue(L, 1));
// Build a tokenfactor for all the chains.
- return getNode(ISD::TokenFactor, Chain.getDebugLoc(), EVT::Other,
+ return getNode(ISD::TokenFactor, Chain.getDebugLoc(), MVT::Other,
&ArgChains[0], ArgChains.size());
}
if (VT.isInteger())
return DAG.getConstant(0, VT);
unsigned NumElts = VT.getVectorNumElements();
- EVT EltVT = (VT.getVectorElementType() == EVT::f32) ? EVT::i32 : EVT::i64;
+ EVT EltVT = (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64;
return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
DAG.getConstant(0, EVT::getVectorVT(EltVT, NumElts)));
}
bool isSrcConst = isa<ConstantSDNode>(Src);
bool AllowUnalign = TLI.allowsUnalignedMemoryAccesses();
EVT VT = TLI.getOptimalMemOpType(Size, Align, isSrcConst, isSrcStr, DAG);
- if (VT != EVT::iAny) {
+ if (VT != MVT::iAny) {
unsigned NewAlign = (unsigned)
TLI.getTargetData()->getABITypeAlignment(VT.getTypeForEVT());
// If source is a string constant, this will require an unaligned load.
if (Dst.getOpcode() != ISD::FrameIndex) {
// Can't change destination alignment. It requires a unaligned store.
if (AllowUnalign)
- VT = EVT::iAny;
+ VT = MVT::iAny;
} else {
int FI = cast<FrameIndexSDNode>(Dst)->getIndex();
MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
if (MFI->isFixedObjectIndex(FI)) {
// Can't change destination alignment. It requires a unaligned store.
if (AllowUnalign)
- VT = EVT::iAny;
+ VT = MVT::iAny;
} else {
// Give the stack frame object a larger alignment if needed.
if (MFI->getObjectAlignment(FI) < NewAlign)
}
}
- if (VT == EVT::iAny) {
+ if (VT == MVT::iAny) {
if (AllowUnalign) {
- VT = EVT::i64;
+ VT = MVT::i64;
} else {
switch (Align & 7) {
- case 0: VT = EVT::i64; break;
- case 4: VT = EVT::i32; break;
- case 2: VT = EVT::i16; break;
- default: VT = EVT::i8; break;
+ case 0: VT = MVT::i64; break;
+ case 4: VT = MVT::i32; break;
+ case 2: VT = MVT::i16; break;
+ default: VT = MVT::i8; break;
}
}
- EVT LVT = EVT::i64;
+ EVT LVT = MVT::i64;
while (!TLI.isTypeLegal(LVT))
- LVT = (EVT::SimpleValueType)(LVT.getSimpleVT() - 1);
+ LVT = (MVT::SimpleValueType)(LVT.getSimpleVT().SimpleTy - 1);
assert(LVT.isInteger());
if (VT.bitsGT(LVT))
while (VTSize > Size) {
// For now, only use non-vector load / store's for the left-over pieces.
if (VT.isVector()) {
- VT = EVT::i64;
+ VT = MVT::i64;
while (!TLI.isTypeLegal(VT))
- VT = (EVT::SimpleValueType)(VT.getSimpleVT() - 1);
+ VT = (MVT::SimpleValueType)(VT.getSimpleVT().SimpleTy - 1);
VTSize = VT.getSizeInBits() / 8;
} else {
// This can result in a type that is not legal on the target, e.g.
// 1 or 2 bytes on PPC.
- VT = (EVT::SimpleValueType)(VT.getSimpleVT() - 1);
+ VT = (MVT::SimpleValueType)(VT.getSimpleVT().SimpleTy - 1);
VTSize >>= 1;
}
}
DstOff += VTSize;
}
- return DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&OutChains[0], OutChains.size());
}
LoadChains.push_back(Value.getValue(1));
SrcOff += VTSize;
}
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&LoadChains[0], LoadChains.size());
OutChains.clear();
for (unsigned i = 0; i < NumMemOps; i++) {
DstOff += VTSize;
}
- return DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&OutChains[0], OutChains.size());
}
DstOff += VTSize;
}
- return DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&OutChains[0], OutChains.size());
}
Entry.Node = Dst; Entry.Ty = IntPtrTy;
Args.push_back(Entry);
// Extend or truncate the argument to be an i32 value for the call.
- if (Src.getValueType().bitsGT(EVT::i32))
- Src = getNode(ISD::TRUNCATE, dl, EVT::i32, Src);
+ if (Src.getValueType().bitsGT(MVT::i32))
+ Src = getNode(ISD::TRUNCATE, dl, MVT::i32, Src);
else
- Src = getNode(ISD::ZERO_EXTEND, dl, EVT::i32, Src);
+ Src = getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Src);
Entry.Node = Src; Entry.Ty = Type::Int32Ty; Entry.isSExt = true;
Args.push_back(Entry);
Entry.Node = Size; Entry.Ty = IntPtrTy; Entry.isSExt = false;
if (Alignment == 0) // Ensure that codegen never sees alignment 0
Alignment = getEVTAlignment(MemVT);
- SDVTList VTs = getVTList(VT, EVT::Other);
+ SDVTList VTs = getVTList(VT, MVT::Other);
FoldingSetNodeID ID;
ID.AddInteger(MemVT.getRawBits());
SDValue Ops[] = {Chain, Ptr, Cmp, Swp};
if (Alignment == 0) // Ensure that codegen never sees alignment 0
Alignment = getEVTAlignment(MemVT);
- SDVTList VTs = getVTList(VT, EVT::Other);
+ SDVTList VTs = getVTList(VT, MVT::Other);
FoldingSetNodeID ID;
ID.AddInteger(MemVT.getRawBits());
SDValue Ops[] = {Chain, Ptr, Val};
@@ -3600,7 +3601,7 @@ SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, SDVTList VTList,
bool ReadMem, bool WriteMem) {
// Memoize the node unless it returns a flag.
MemIntrinsicSDNode *N;
- if (VTList.VTs[VTList.NumVTs-1] != EVT::Flag) {
+ if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) {
FoldingSetNodeID ID;
AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps);
void *IP = 0;
"Unindexed load with an offset!");
SDVTList VTs = Indexed ?
- getVTList(VT, Ptr.getValueType(), EVT::Other) : getVTList(VT, EVT::Other);
+ getVTList(VT, Ptr.getValueType(), MVT::Other) : getVTList(VT, MVT::Other);
SDValue Ops[] = { Chain, Ptr, Offset };
FoldingSetNodeID ID;
AddNodeIDNode(ID, ISD::LOAD, VTs, Ops, 3);
if (Alignment == 0) // Ensure that codegen never sees alignment 0
Alignment = getEVTAlignment(VT);
- SDVTList VTs = getVTList(EVT::Other);
+ SDVTList VTs = getVTList(MVT::Other);
SDValue Undef = getUNDEF(Ptr.getValueType());
SDValue Ops[] = { Chain, Val, Ptr, Undef };
FoldingSetNodeID ID;
if (Alignment == 0) // Ensure that codegen never sees alignment 0
Alignment = getEVTAlignment(VT);
- SDVTList VTs = getVTList(EVT::Other);
+ SDVTList VTs = getVTList(MVT::Other);
SDValue Undef = getUNDEF(Ptr.getValueType());
SDValue Ops[] = { Chain, Val, Ptr, Undef };
FoldingSetNodeID ID;
StoreSDNode *ST = cast<StoreSDNode>(OrigStore);
assert(ST->getOffset().getOpcode() == ISD::UNDEF &&
"Store is already a indexed store!");
- SDVTList VTs = getVTList(Base.getValueType(), EVT::Other);
+ SDVTList VTs = getVTList(Base.getValueType(), MVT::Other);
SDValue Ops[] = { ST->getChain(), ST->getValue(), Base, Offset };
FoldingSetNodeID ID;
AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
SDValue Chain, SDValue Ptr,
SDValue SV) {
SDValue Ops[] = { Chain, Ptr, SV };
- return getNode(ISD::VAARG, dl, getVTList(VT, EVT::Other), Ops, 3);
+ return getNode(ISD::VAARG, dl, getVTList(VT, MVT::Other), Ops, 3);
}
SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, EVT VT,
SDNode *N;
SDVTList VTs = getVTList(VT);
- if (VT != EVT::Flag) {
+ if (VT != MVT::Flag) {
FoldingSetNodeID ID;
AddNodeIDNode(ID, Opcode, VTs, Ops, NumOps);
void *IP = 0;
case ISD::SRL_PARTS:
case ISD::SHL_PARTS:
if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG &&
- cast<VTSDNode>(N3.getOperand(1))->getVT() != EVT::i1)
+ cast<VTSDNode>(N3.getOperand(1))->getVT() != MVT::i1)
return getNode(Opcode, DL, VT, N1, N2, N3.getOperand(0));
else if (N3.getOpcode() == ISD::AND)
if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) {
// Memoize the node unless it returns a flag.
SDNode *N;
- if (VTList.VTs[VTList.NumVTs-1] != EVT::Flag) {
+ if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) {
FoldingSetNodeID ID;
AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps);
void *IP = 0;
unsigned NumOps) {
// If an identical node already exists, use it.
void *IP = 0;
- if (VTs.VTs[VTs.NumVTs-1] != EVT::Flag) {
+ if (VTs.VTs[VTs.NumVTs-1] != MVT::Flag) {
FoldingSetNodeID ID;
AddNodeIDNode(ID, Opc, VTs, Ops, NumOps);
if (SDNode *ON = CSEMap.FindNodeOrInsertPos(ID, IP))
/// else return NULL.
SDNode *SelectionDAG::getNodeIfExists(unsigned Opcode, SDVTList VTList,
const SDValue *Ops, unsigned NumOps) {
- if (VTList.VTs[VTList.NumVTs-1] != EVT::Flag) {
+ if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) {
FoldingSetNodeID ID;
AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps);
void *IP = 0;
}
static ManagedStatic<std::set<EVT, EVT::compareRawBits> > EVTs;
-static EVT VTs[EVT::LAST_VALUETYPE];
+static EVT VTs[MVT::LAST_VALUETYPE];
static ManagedStatic<sys::SmartMutex<true> > VTMutex;
/// getValueTypeList - Return a pointer to the specified value type.
if (VT.isExtended()) {
return &(*EVTs->insert(VT).first);
} else {
- VTs[VT.getSimpleVT()] = VT;
- return &VTs[VT.getSimpleVT()];
+ VTs[VT.getSimpleVT().SimpleTy] = VT;
+ return &VTs[VT.getSimpleVT().SimpleTy];
}
}
for (unsigned i = 0, e = getNumValues(); i != e; ++i) {
if (i) OS << ",";
- if (getValueType(i) == EVT::Other)
+ if (getValueType(i) == MVT::Other)
OS << "ch";
else
OS << getValueType(i).getEVTString();
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
index 1d02bffb61a0d216620d51898615b457c60f0859..4662fb06ef0bf2992cbbbb916646e59f870e7e23 100644 (file)
ValueVT, &Ops[0], NumIntermediates);
} else if (PartVT.isFloatingPoint()) {
// FP split into multiple FP parts (for ppcf128)
- assert(ValueVT == EVT(EVT::ppcf128) && PartVT == EVT(EVT::f64) &&
+ assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) &&
"Unexpected split");
SDValue Lo, Hi;
- Lo = DAG.getNode(ISD::BIT_CONVERT, dl, EVT(EVT::f64), Parts[0]);
- Hi = DAG.getNode(ISD::BIT_CONVERT, dl, EVT(EVT::f64), Parts[1]);
+ Lo = DAG.getNode(ISD::BIT_CONVERT, dl, EVT(MVT::f64), Parts[0]);
+ Hi = DAG.getNode(ISD::BIT_CONVERT, dl, EVT(MVT::f64), Parts[1]);
if (TLI.isBigEndian())
std::swap(Lo, Hi);
Val = DAG.getNode(ISD::BUILD_PAIR, dl, ValueVT, Lo, Hi);
}
// Otherwise, we have to make a token factor node.
- SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), EVT::Other,
+ SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
&PendingLoads[0], PendingLoads.size());
PendingLoads.clear();
DAG.setRoot(Root);
PendingExports.push_back(Root);
}
- Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), EVT::Other,
+ Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
&PendingExports[0],
PendingExports.size());
PendingExports.clear();
// conventions. The frontend should mark functions whose return values
// require promoting with signext or zeroext attributes.
if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
- EVT MinVT = TLI.getRegisterType(EVT::i32);
+ EVT MinVT = TLI.getRegisterType(MVT::i32);
if (VT.bitsLT(MinVT))
VT = MinVT;
}
Outs, getCurDebugLoc(), DAG);
// Verify that the target's LowerReturn behaved as expected.
- assert(Chain.getNode() && Chain.getValueType() == EVT::Other &&
+ assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
"LowerReturn didn't return a valid chain!");
// Update the DAG with the new chain value resulting from return lowering.
// If this is not a fall-through branch, emit the branch.
if (Succ0MBB != NextBlock)
DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
- EVT::Other, getControlRoot(),
+ MVT::Other, getControlRoot(),
DAG.getBasicBlock(Succ0MBB)));
return;
}
SDValue True = DAG.getConstant(1, CondLHS.getValueType());
Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
} else
- Cond = DAG.getSetCC(dl, EVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
+ Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
} else {
assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
EVT VT = CmpOp.getValueType();
if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
- Cond = DAG.getSetCC(dl, EVT::i1, CmpOp, DAG.getConstant(High, VT),
+ Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
ISD::SETLE);
} else {
SDValue SUB = DAG.getNode(ISD::SUB, dl,
VT, CmpOp, DAG.getConstant(Low, VT));
- Cond = DAG.getSetCC(dl, EVT::i1, SUB,
+ Cond = DAG.getSetCC(dl, MVT::i1, SUB,
DAG.getConstant(High-Low, VT), ISD::SETULE);
}
}
Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
}
SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
- EVT::Other, getControlRoot(), Cond,
+ MVT::Other, getControlRoot(), Cond,
DAG.getBasicBlock(CB.TrueBB));
// If the branch was constant folded, fix up the CFG.
if (CB.FalseBB == NextBlock)
DAG.setRoot(BrCond);
else
- DAG.setRoot(DAG.getNode(ISD::BR, dl, EVT::Other, BrCond,
+ DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
DAG.getBasicBlock(CB.FalseBB)));
}
}
JT.Reg, PTy);
SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
DAG.setRoot(DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
- EVT::Other, Index.getValue(1),
+ MVT::Other, Index.getValue(1),
Table, Index));
}
NextBlock = BBI;
SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
- EVT::Other, CopyTo, CMP,
+ MVT::Other, CopyTo, CMP,
DAG.getBasicBlock(JT.Default));
if (JT.MBB == NextBlock)
DAG.setRoot(BrCond);
else
- DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), EVT::Other, BrCond,
+ DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
DAG.getBasicBlock(JT.MBB)));
}
CurMBB->addSuccessor(MBB);
SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
- EVT::Other, CopyTo, RangeCmp,
+ MVT::Other, CopyTo, RangeCmp,
DAG.getBasicBlock(B.Default));
if (MBB == NextBlock)
DAG.setRoot(BrRange);
else
- DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), EVT::Other, CopyTo,
+ DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
DAG.getBasicBlock(MBB)));
}
CurMBB->addSuccessor(NextMBB);
SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
- EVT::Other, getControlRoot(),
+ MVT::Other, getControlRoot(),
AndCmp, DAG.getBasicBlock(B.TargetBB));
// Set NextBlock to be the MBB immediately after the current one, if any.
if (NextMBB == NextBlock)
DAG.setRoot(BrAnd);
else
- DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), EVT::Other, BrAnd,
+ DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
DAG.getBasicBlock(NextMBB)));
}
// Drop into normal successor.
DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
- EVT::Other, getControlRoot(),
+ MVT::Other, getControlRoot(),
DAG.getBasicBlock(Return)));
}
static inline bool areJTsAllowed(const TargetLowering &TLI) {
return !DisableJumpTables &&
- (TLI.isOperationLegalOrCustom(ISD::BR_JT, EVT::Other) ||
- TLI.isOperationLegalOrCustom(ISD::BRIND, EVT::Other));
+ (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
+ TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
}
static APInt ComputeRange(const APInt &First, const APInt &Last) {
CurMBB->addSuccessor(Default);
if (Default != NextBlock)
DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
- EVT::Other, getControlRoot(),
+ MVT::Other, getControlRoot(),
DAG.getBasicBlock(Default)));
return;
}
if (PtrBits < 64) {
OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
TLI.getPointerTy(),
- DAG.getConstant(Offs, EVT::i64));
+ DAG.getConstant(Offs, MVT::i64));
} else
OffsVal = DAG.getIntPtrConstant(Offs);
N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
- SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), EVT::Other);
+ SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
VTs, Ops, 3);
setValue(&I, DSA);
if (!ConstantMemory) {
SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
- EVT::Other,
+ MVT::Other,
&Chains[0], NumValues);
if (isVolatile)
DAG.setRoot(Chain);
isVolatile, Alignment);
DAG.setRoot(DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
- EVT::Other, &Chains[0], NumValues));
+ MVT::Other, &Chains[0], NumValues));
}
/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
}
#endif // NDEBUG
if (HasChain)
- ValueVTs.push_back(EVT::Other);
+ ValueVTs.push_back(MVT::Other);
SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
/// where Op is the hexidecimal representation of floating point value.
static SDValue
GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
- SDValue t1 = DAG.getNode(ISD::AND, dl, EVT::i32, Op,
- DAG.getConstant(0x007fffff, EVT::i32));
- SDValue t2 = DAG.getNode(ISD::OR, dl, EVT::i32, t1,
- DAG.getConstant(0x3f800000, EVT::i32));
- return DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, t2);
+ SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
+ DAG.getConstant(0x007fffff, MVT::i32));
+ SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
+ DAG.getConstant(0x3f800000, MVT::i32));
+ return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t2);
}
/// GetExponent - Get the exponent:
static SDValue
GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
DebugLoc dl) {
- SDValue t0 = DAG.getNode(ISD::AND, dl, EVT::i32, Op,
- DAG.getConstant(0x7f800000, EVT::i32));
- SDValue t1 = DAG.getNode(ISD::SRL, dl, EVT::i32, t0,
+ SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
+ DAG.getConstant(0x7f800000, MVT::i32));
+ SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
DAG.getConstant(23, TLI.getPointerTy()));
- SDValue t2 = DAG.getNode(ISD::SUB, dl, EVT::i32, t1,
- DAG.getConstant(127, EVT::i32));
- return DAG.getNode(ISD::SINT_TO_FP, dl, EVT::f32, t2);
+ SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
+ DAG.getConstant(127, MVT::i32));
+ return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
}
/// getF32Constant - Get 32-bit floating point constant.
static SDValue
getF32Constant(SelectionDAG &DAG, unsigned Flt) {
- return DAG.getConstantFP(APFloat(APInt(32, Flt)), EVT::f32);
+ return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
}
/// Inlined utility function to implement binary input atomic intrinsics for
SDValue Op1 = getValue(I.getOperand(1));
SDValue Op2 = getValue(I.getOperand(2));
- SDVTList VTs = DAG.getVTList(Op1.getValueType(), EVT::i1);
+ SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
SDValue Result = DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2);
setValue(&I, Result);
SDValue result;
DebugLoc dl = getCurDebugLoc();
- if (getValue(I.getOperand(1)).getValueType() == EVT::f32 &&
+ if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
SDValue Op = getValue(I.getOperand(1));
//
// #define LOG2OFe 1.4426950f
// IntegerPartOfX = ((int32_t)(X * LOG2OFe));
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, Op,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
getF32Constant(DAG, 0x3fb8aa3b));
- SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, EVT::i32, t0);
+ SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
// FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
- SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, EVT::f32, IntegerPartOfX);
- SDValue X = DAG.getNode(ISD::FSUB, dl, EVT::f32, t0, t1);
+ SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
+ SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
// IntegerPartOfX <<= 23;
- IntegerPartOfX = DAG.getNode(ISD::SHL, dl, EVT::i32, IntegerPartOfX,
+ IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
DAG.getConstant(23, TLI.getPointerTy()));
if (LimitFloatPrecision <= 6) {
// (0.735607626f + 0.252464424f * x) * x;
//
// error 0.0144103317, which is 6 bits
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
getF32Constant(DAG, 0x3e814304));
- SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
getF32Constant(DAG, 0x3f3c50c8));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
getF32Constant(DAG, 0x3f7f5e7e));
- SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,EVT::i32, t5);
+ SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t5);
// Add the exponent into the result in integer domain.
- SDValue t6 = DAG.getNode(ISD::ADD, dl, EVT::i32,
+ SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
TwoToFracPartOfX, IntegerPartOfX);
- result = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, t6);
+ result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t6);
} else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
// For floating-point precision of 12:
//
// (0.224338339f + 0.792043434e-1f * x) * x) * x;
//
// 0.000107046256 error, which is 13 to 14 bits
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
getF32Constant(DAG, 0x3da235e3));
- SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
getF32Constant(DAG, 0x3e65b8f3));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
getF32Constant(DAG, 0x3f324b07));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
- SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
+ SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
getF32Constant(DAG, 0x3f7ff8fd));
- SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,EVT::i32, t7);
+ SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t7);
// Add the exponent into the result in integer domain.
- SDValue t8 = DAG.getNode(ISD::ADD, dl, EVT::i32,
+ SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
TwoToFracPartOfX, IntegerPartOfX);
- result = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, t8);
+ result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t8);
} else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
// For floating-point precision of 18:
//
// (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
//
// error 2.47208000*10^(-7), which is better than 18 bits
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
getF32Constant(DAG, 0x3924b03e));
- SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
getF32Constant(DAG, 0x3ab24b87));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
getF32Constant(DAG, 0x3c1d8c17));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
- SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
+ SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
getF32Constant(DAG, 0x3d634a1d));
- SDValue t8 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t7, X);
- SDValue t9 = DAG.getNode(ISD::FADD, dl, EVT::f32, t8,
+ SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
+ SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
getF32Constant(DAG, 0x3e75fe14));
- SDValue t10 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t9, X);
- SDValue t11 = DAG.getNode(ISD::FADD, dl, EVT::f32, t10,
+ SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
+ SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
getF32Constant(DAG, 0x3f317234));
- SDValue t12 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t11, X);
- SDValue t13 = DAG.getNode(ISD::FADD, dl, EVT::f32, t12,
+ SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
+ SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
getF32Constant(DAG, 0x3f800000));
SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,
- EVT::i32, t13);
+ MVT::i32, t13);
// Add the exponent into the result in integer domain.
- SDValue t14 = DAG.getNode(ISD::ADD, dl, EVT::i32,
+ SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
TwoToFracPartOfX, IntegerPartOfX);
- result = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, t14);
+ result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t14);
}
} else {
// No special expansion.
SDValue result;
DebugLoc dl = getCurDebugLoc();
- if (getValue(I.getOperand(1)).getValueType() == EVT::f32 &&
+ if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
SDValue Op = getValue(I.getOperand(1));
- SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, Op);
+ SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
// Scale the exponent by log(2) [0.69314718f].
SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
- SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, EVT::f32, Exp,
+ SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
getF32Constant(DAG, 0x3f317218));
// Get the significand and build it into a floating-point number with
// (1.4034025f - 0.23903021f * x) * x;
//
// error 0.0034276066, which is better than 8 bits
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
getF32Constant(DAG, 0xbe74c456));
- SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0,
+ SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
getF32Constant(DAG, 0x3fb3a2b1));
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
- SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
+ SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
getF32Constant(DAG, 0x3f949a29));
result = DAG.getNode(ISD::FADD, dl,
- EVT::f32, LogOfExponent, LogOfMantissa);
+ MVT::f32, LogOfExponent, LogOfMantissa);
} else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
// For floating-point precision of 12:
//
// (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
//
// error 0.000061011436, which is 14 bits
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
getF32Constant(DAG, 0xbd67b6d6));
- SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0,
+ SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
getF32Constant(DAG, 0x3ee4f4b8));
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
- SDValue t3 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
+ SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
getF32Constant(DAG, 0x3fbc278b));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
getF32Constant(DAG, 0x40348e95));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
- SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
+ SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
getF32Constant(DAG, 0x3fdef31a));
result = DAG.getNode(ISD::FADD, dl,
- EVT::f32, LogOfExponent, LogOfMantissa);
+ MVT::f32, LogOfExponent, LogOfMantissa);
} else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
// For floating-point precision of 18:
//
// (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
//
// error 0.0000023660568, which is better than 18 bits
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
getF32Constant(DAG, 0xbc91e5ac));
- SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0,
+ SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
getF32Constant(DAG, 0x3e4350aa));
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
- SDValue t3 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
+ SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
getF32Constant(DAG, 0x3f60d3e3));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
getF32Constant(DAG, 0x4011cdf0));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
- SDValue t7 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
+ SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
getF32Constant(DAG, 0x406cfd1c));
- SDValue t8 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t7, X);
- SDValue t9 = DAG.getNode(ISD::FADD, dl, EVT::f32, t8,
+ SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
+ SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
getF32Constant(DAG, 0x408797cb));
- SDValue t10 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t9, X);
- SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t10,
+ SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
+ SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
getF32Constant(DAG, 0x4006dcab));
result = DAG.getNode(ISD::FADD, dl,
- EVT::f32, LogOfExponent, LogOfMantissa);
+ MVT::f32, LogOfExponent, LogOfMantissa);
}
} else {
// No special expansion.
SDValue result;
DebugLoc dl = getCurDebugLoc();
- if (getValue(I.getOperand(1)).getValueType() == EVT::f32 &&
+ if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
SDValue Op = getValue(I.getOperand(1));
- SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, Op);
+ SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
// Get the exponent.
SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
// Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
//
// error 0.0049451742, which is more than 7 bits
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
getF32Constant(DAG, 0xbeb08fe0));
- SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0,
+ SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
getF32Constant(DAG, 0x40019463));
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
- SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
+ SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
getF32Constant(DAG, 0x3fd6633d));
result = DAG.getNode(ISD::FADD, dl,
- EVT::f32, LogOfExponent, Log2ofMantissa);
+ MVT::f32, LogOfExponent, Log2ofMantissa);
} else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
// For floating-point precision of 12:
//
// (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
//
// error 0.0000876136000, which is better than 13 bits
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
getF32Constant(DAG, 0xbda7262e));
- SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0,
+ SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
getF32Constant(DAG, 0x3f25280b));
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
- SDValue t3 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
+ SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
getF32Constant(DAG, 0x4007b923));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
getF32Constant(DAG, 0x40823e2f));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
- SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
+ SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
getF32Constant(DAG, 0x4020d29c));
result = DAG.getNode(ISD::FADD, dl,
- EVT::f32, LogOfExponent, Log2ofMantissa);
+ MVT::f32, LogOfExponent, Log2ofMantissa);
} else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
// For floating-point precision of 18:
//
// 0.25691327e-1f * x) * x) * x) * x) * x) * x;
//
// error 0.0000018516, which is better than 18 bits
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
getF32Constant(DAG, 0xbcd2769e));
- SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0,
+ SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
getF32Constant(DAG, 0x3e8ce0b9));
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
- SDValue t3 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
+ SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
getF32Constant(DAG, 0x3fa22ae7));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
getF32Constant(DAG, 0x40525723));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
- SDValue t7 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
+ SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
getF32Constant(DAG, 0x40aaf200));
- SDValue t8 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t7, X);
- SDValue t9 = DAG.getNode(ISD::FADD, dl, EVT::f32, t8,
+ SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
+ SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
getF32Constant(DAG, 0x40c39dad));
- SDValue t10 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t9, X);
- SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t10,
+ SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
+ SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
getF32Constant(DAG, 0x4042902c));
result = DAG.getNode(ISD::FADD, dl,
- EVT::f32, LogOfExponent, Log2ofMantissa);
+ MVT::f32, LogOfExponent, Log2ofMantissa);
}
} else {
// No special expansion.
SDValue result;
DebugLoc dl = getCurDebugLoc();
- if (getValue(I.getOperand(1)).getValueType() == EVT::f32 &&
+ if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
SDValue Op = getValue(I.getOperand(1));
- SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, Op);
+ SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
// Scale the exponent by log10(2) [0.30102999f].
SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
- SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, EVT::f32, Exp,
+ SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
getF32Constant(DAG, 0x3e9a209a));
// Get the significand and build it into a floating-point number with
// (0.60948995f - 0.10380950f * x) * x;
//
// error 0.0014886165, which is 6 bits
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
getF32Constant(DAG, 0xbdd49a13));
- SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0,
+ SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
getF32Constant(DAG, 0x3f1c0789));
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
- SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
+ SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
getF32Constant(DAG, 0x3f011300));
result = DAG.getNode(ISD::FADD, dl,
- EVT::f32, LogOfExponent, Log10ofMantissa);
+ MVT::f32, LogOfExponent, Log10ofMantissa);
} else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
// For floating-point precision of 12:
//
// (-0.31664806f + 0.47637168e-1f * x) * x) * x;
//
// error 0.00019228036, which is better than 12 bits
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
getF32Constant(DAG, 0x3d431f31));
- SDValue t1 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t0,
+ SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
getF32Constant(DAG, 0x3ea21fb2));
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
- SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
getF32Constant(DAG, 0x3f6ae232));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
- SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+ SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
getF32Constant(DAG, 0x3f25f7c3));
result = DAG.getNode(ISD::FADD, dl,
- EVT::f32, LogOfExponent, Log10ofMantissa);
+ MVT::f32, LogOfExponent, Log10ofMantissa);
} else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
// For floating-point precision of 18:
//
// (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
//
// error 0.0000037995730, which is better than 18 bits
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
getF32Constant(DAG, 0x3c5d51ce));
- SDValue t1 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t0,
+ SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
getF32Constant(DAG, 0x3e00685a));
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
- SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
getF32Constant(DAG, 0x3efb6798));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
getF32Constant(DAG, 0x3f88d192));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
- SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
+ SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
getF32Constant(DAG, 0x3fc4316c));
- SDValue t8 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t7, X);
- SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t8,
+ SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
+ SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
getF32Constant(DAG, 0x3f57ce70));
result = DAG.getNode(ISD::FADD, dl,
- EVT::f32, LogOfExponent, Log10ofMantissa);
+ MVT::f32, LogOfExponent, Log10ofMantissa);
}
} else {
// No special expansion.
SDValue result;
DebugLoc dl = getCurDebugLoc();
- if (getValue(I.getOperand(1)).getValueType() == EVT::f32 &&
+ if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
SDValue Op = getValue(I.getOperand(1));
- SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, EVT::i32, Op);
+ SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
// FractionalPartOfX = x - (float)IntegerPartOfX;
- SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, EVT::f32, IntegerPartOfX);
- SDValue X = DAG.getNode(ISD::FSUB, dl, EVT::f32, Op, t1);
+ SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
+ SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
// IntegerPartOfX <<= 23;
- IntegerPartOfX = DAG.getNode(ISD::SHL, dl, EVT::i32, IntegerPartOfX,
+ IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
DAG.getConstant(23, TLI.getPointerTy()));
if (LimitFloatPrecision <= 6) {
// (0.735607626f + 0.252464424f * x) * x;
//
// error 0.0144103317, which is 6 bits
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
getF32Constant(DAG, 0x3e814304));
- SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
getF32Constant(DAG, 0x3f3c50c8));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
getF32Constant(DAG, 0x3f7f5e7e));
- SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, t5);
+ SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
SDValue TwoToFractionalPartOfX =
- DAG.getNode(ISD::ADD, dl, EVT::i32, t6, IntegerPartOfX);
+ DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
result = DAG.getNode(ISD::BIT_CONVERT, dl,
- EVT::f32, TwoToFractionalPartOfX);
+ MVT::f32, TwoToFractionalPartOfX);
} else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
// For floating-point precision of 12:
//
// (0.224338339f + 0.792043434e-1f * x) * x) * x;
//
// error 0.000107046256, which is 13 to 14 bits
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
getF32Constant(DAG, 0x3da235e3));
- SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
getF32Constant(DAG, 0x3e65b8f3));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
getF32Constant(DAG, 0x3f324b07));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
- SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
+ SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
getF32Constant(DAG, 0x3f7ff8fd));
- SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, t7);
+ SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
SDValue TwoToFractionalPartOfX =
- DAG.getNode(ISD::ADD, dl, EVT::i32, t8, IntegerPartOfX);
+ DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
result = DAG.getNode(ISD::BIT_CONVERT, dl,
- EVT::f32, TwoToFractionalPartOfX);
+ MVT::f32, TwoToFractionalPartOfX);
} else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
// For floating-point precision of 18:
//
// (0.961591928e-2f +
// (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
// error 2.47208000*10^(-7), which is better than 18 bits
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
getF32Constant(DAG, 0x3924b03e));
- SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
getF32Constant(DAG, 0x3ab24b87));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
getF32Constant(DAG, 0x3c1d8c17));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
- SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
+ SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
getF32Constant(DAG, 0x3d634a1d));
- SDValue t8 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t7, X);
- SDValue t9 = DAG.getNode(ISD::FADD, dl, EVT::f32, t8,
+ SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
+ SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
getF32Constant(DAG, 0x3e75fe14));
- SDValue t10 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t9, X);
- SDValue t11 = DAG.getNode(ISD::FADD, dl, EVT::f32, t10,
+ SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
+ SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
getF32Constant(DAG, 0x3f317234));
- SDValue t12 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t11, X);
- SDValue t13 = DAG.getNode(ISD::FADD, dl, EVT::f32, t12,
+ SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
+ SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
getF32Constant(DAG, 0x3f800000));
- SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, t13);
+ SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
SDValue TwoToFractionalPartOfX =
- DAG.getNode(ISD::ADD, dl, EVT::i32, t14, IntegerPartOfX);
+ DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
result = DAG.getNode(ISD::BIT_CONVERT, dl,
- EVT::f32, TwoToFractionalPartOfX);
+ MVT::f32, TwoToFractionalPartOfX);
}
} else {
// No special expansion.
DebugLoc dl = getCurDebugLoc();
bool IsExp10 = false;
- if (getValue(Val).getValueType() == EVT::f32 &&
- getValue(I.getOperand(2)).getValueType() == EVT::f32 &&
+ if (getValue(Val).getValueType() == MVT::f32 &&
+ getValue(I.getOperand(2)).getValueType() == MVT::f32 &&
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
//
// #define LOG2OF10 3.3219281f
// IntegerPartOfX = (int32_t)(x * LOG2OF10);
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, Op,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
getF32Constant(DAG, 0x40549a78));
- SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, EVT::i32, t0);
+ SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
// FractionalPartOfX = x - (float)IntegerPartOfX;
- SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, EVT::f32, IntegerPartOfX);
- SDValue X = DAG.getNode(ISD::FSUB, dl, EVT::f32, t0, t1);
+ SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
+ SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
// IntegerPartOfX <<= 23;
- IntegerPartOfX = DAG.getNode(ISD::SHL, dl, EVT::i32, IntegerPartOfX,
+ IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
DAG.getConstant(23, TLI.getPointerTy()));
if (LimitFloatPrecision <= 6) {
// (0.735607626f + 0.252464424f * x) * x;
//
// error 0.0144103317, which is 6 bits
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
getF32Constant(DAG, 0x3e814304));
- SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
getF32Constant(DAG, 0x3f3c50c8));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
getF32Constant(DAG, 0x3f7f5e7e));
- SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, t5);
+ SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
SDValue TwoToFractionalPartOfX =
- DAG.getNode(ISD::ADD, dl, EVT::i32, t6, IntegerPartOfX);
+ DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
result = DAG.getNode(ISD::BIT_CONVERT, dl,
- EVT::f32, TwoToFractionalPartOfX);
+ MVT::f32, TwoToFractionalPartOfX);
} else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
// For floating-point precision of 12:
//
// (0.224338339f + 0.792043434e-1f * x) * x) * x;
//
// error 0.000107046256, which is 13 to 14 bits
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
getF32Constant(DAG, 0x3da235e3));
- SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
getF32Constant(DAG, 0x3e65b8f3));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
getF32Constant(DAG, 0x3f324b07));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
- SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
+ SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
getF32Constant(DAG, 0x3f7ff8fd));
- SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, t7);
+ SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
SDValue TwoToFractionalPartOfX =
- DAG.getNode(ISD::ADD, dl, EVT::i32, t8, IntegerPartOfX);
+ DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
result = DAG.getNode(ISD::BIT_CONVERT, dl,
- EVT::f32, TwoToFractionalPartOfX);
+ MVT::f32, TwoToFractionalPartOfX);
} else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
// For floating-point precision of 18:
//
// (0.961591928e-2f +
// (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
// error 2.47208000*10^(-7), which is better than 18 bits
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
getF32Constant(DAG, 0x3924b03e));
- SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
getF32Constant(DAG, 0x3ab24b87));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
getF32Constant(DAG, 0x3c1d8c17));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
- SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
+ SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
getF32Constant(DAG, 0x3d634a1d));
- SDValue t8 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t7, X);
- SDValue t9 = DAG.getNode(ISD::FADD, dl, EVT::f32, t8,
+ SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
+ SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
getF32Constant(DAG, 0x3e75fe14));
- SDValue t10 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t9, X);
- SDValue t11 = DAG.getNode(ISD::FADD, dl, EVT::f32, t10,
+ SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
+ SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
getF32Constant(DAG, 0x3f317234));
- SDValue t12 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t11, X);
- SDValue t13 = DAG.getNode(ISD::FADD, dl, EVT::f32, t12,
+ SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
+ SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
getF32Constant(DAG, 0x3f800000));
- SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, t13);
+ SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
SDValue TwoToFractionalPartOfX =
- DAG.getNode(ISD::ADD, dl, EVT::i32, t14, IntegerPartOfX);
+ DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
result = DAG.getNode(ISD::BIT_CONVERT, dl,
- EVT::f32, TwoToFractionalPartOfX);
+ MVT::f32, TwoToFractionalPartOfX);
}
} else {
// No special expansion.
return 0;
Value *Variable = DI.getVariable();
- DAG.setRoot(DAG.getNode(ISD::DECLARE, dl, EVT::Other, getRoot(),
+ DAG.setRoot(DAG.getNode(ISD::DECLARE, dl, MVT::Other, getRoot(),
getValue(DI.getAddress()), getValue(Variable)));
return 0;
}
case Intrinsic::eh_exception: {
// Insert the EXCEPTIONADDR instruction.
assert(CurMBB->isLandingPad() &&"Call to eh.exception not in landing pad!");
- SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), EVT::Other);
+ SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
SDValue Ops[1];
Ops[0] = DAG.getRoot();
SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
case Intrinsic::eh_selector_i64: {
MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
EVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
- EVT::i32 : EVT::i64);
+ MVT::i32 : MVT::i64);
if (MMI) {
if (CurMBB->isLandingPad())
}
// Insert the EHSELECTION instruction.
- SDVTList VTs = DAG.getVTList(VT, EVT::Other);
+ SDVTList VTs = DAG.getVTList(VT, MVT::Other);
SDValue Ops[2];
Ops[0] = getValue(I.getOperand(1));
Ops[1] = getRoot();
case Intrinsic::eh_typeid_for_i64: {
MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
EVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
- EVT::i32 : EVT::i64);
+ MVT::i32 : MVT::i64);
if (MMI) {
// Find the type id for the given typeinfo.
if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
MMI->setCallsEHReturn(true);
DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
- EVT::Other,
+ MVT::Other,
getControlRoot(),
getValue(I.getOperand(1)),
getValue(I.getOperand(2))));
return 0;
case Intrinsic::pcmarker: {
SDValue Tmp = getValue(I.getOperand(1));
- DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, EVT::Other, getRoot(), Tmp));
+ DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
return 0;
}
case Intrinsic::readcyclecounter: {
SDValue Op = getRoot();
SDValue Tmp = DAG.getNode(ISD::READCYCLECOUNTER, dl,
- DAG.getVTList(EVT::i64, EVT::Other),
+ DAG.getVTList(MVT::i64, MVT::Other),
&Op, 1);
setValue(&I, Tmp);
DAG.setRoot(Tmp.getValue(1));
case Intrinsic::stacksave: {
SDValue Op = getRoot();
SDValue Tmp = DAG.getNode(ISD::STACKSAVE, dl,
- DAG.getVTList(TLI.getPointerTy(), EVT::Other), &Op, 1);
+ DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
setValue(&I, Tmp);
DAG.setRoot(Tmp.getValue(1));
return 0;
}
case Intrinsic::stackrestore: {
SDValue Tmp = getValue(I.getOperand(1));
- DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, EVT::Other, getRoot(), Tmp));
+ DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Tmp));
return 0;
}
case Intrinsic::stackprotector: {
Ops[5] = DAG.getSrcValue(F);
SDValue Tmp = DAG.getNode(ISD::TRAMPOLINE, dl,
- DAG.getVTList(TLI.getPointerTy(), EVT::Other),
+ DAG.getVTList(TLI.getPointerTy(), MVT::Other),
Ops, 6);
setValue(&I, Tmp);
return 0;
case Intrinsic::flt_rounds: {
- setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, EVT::i32));
+ setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
return 0;
}
case Intrinsic::trap: {
- DAG.setRoot(DAG.getNode(ISD::TRAP, dl,EVT::Other, getRoot()));
+ DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
return 0;
}
Ops[1] = getValue(I.getOperand(1));
Ops[2] = getValue(I.getOperand(2));
Ops[3] = getValue(I.getOperand(3));
- DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, EVT::Other, &Ops[0], 4));
+ DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, MVT::Other, &Ops[0], 4));
return 0;
}
for (int x = 1; x < 6; ++x)
Ops[x] = getValue(I.getOperand(x));
- DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, EVT::Other, &Ops[0], 6));
+ DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6));
return 0;
}
case Intrinsic::atomic_cmp_swap: {
// FIXME: We capture more information than the dag can represent. For
// now, just use the tightest assertzext/assertsext possible.
bool isSExt = true;
- EVT FromVT(EVT::Other);
+ EVT FromVT(MVT::Other);
if (NumSignBits == RegSize)
- isSExt = true, FromVT = EVT::i1; // ASSERT SEXT 1
+ isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
else if (NumZeroBits >= RegSize-1)
- isSExt = false, FromVT = EVT::i1; // ASSERT ZEXT 1
+ isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
else if (NumSignBits > RegSize-8)
- isSExt = true, FromVT = EVT::i8; // ASSERT SEXT 8
+ isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
else if (NumZeroBits >= RegSize-8)
- isSExt = false, FromVT = EVT::i8; // ASSERT ZEXT 8
+ isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
else if (NumSignBits > RegSize-16)
- isSExt = true, FromVT = EVT::i16; // ASSERT SEXT 16
+ isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
else if (NumZeroBits >= RegSize-16)
- isSExt = false, FromVT = EVT::i16; // ASSERT ZEXT 16
+ isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
else if (NumSignBits > RegSize-32)
- isSExt = true, FromVT = EVT::i32; // ASSERT SEXT 32
+ isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
else if (NumZeroBits >= RegSize-32)
- isSExt = false, FromVT = EVT::i32; // ASSERT ZEXT 32
+ isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
- if (FromVT != EVT::Other) {
+ if (FromVT != MVT::Other) {
P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
RegisterVT, P, DAG.getValueType(FromVT));
// = op c3, ..., f2
Chain = Chains[NumRegs-1];
else
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &Chains[0], NumRegs);
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
}
/// AddInlineAsmOperands - Add this value to the specified inlineasm node
isAllocatableRegister(unsigned Reg, MachineFunction &MF,
const TargetLowering &TLI,
const TargetRegisterInfo *TRI) {
- EVT FoundVT = EVT::Other;
+ EVT FoundVT = MVT::Other;
const TargetRegisterClass *FoundRC = 0;
for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
E = TRI->regclass_end(); RCI != E; ++RCI) {
- EVT ThisVT = EVT::Other;
+ EVT ThisVT = MVT::Other;
const TargetRegisterClass *RC = *RCI;
// If none of the the value types for this register class are valid, we
// If we have already found this register in a different register class,
// choose the one with the largest VT specified. For example, on
// PowerPC, we favor f64 register classes over f32.
- if (FoundVT == EVT::Other || FoundVT.bitsLT(*I)) {
+ if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
ThisVT = *I;
break;
}
}
}
- if (ThisVT == EVT::Other) continue;
+ if (ThisVT == MVT::Other) continue;
// NOTE: This isn't ideal. In particular, this might allocate the
// frame pointer in functions that need it (due to them not being taken
/// getCallOperandValEVT - Return the EVT of the Value* that this operand
/// corresponds to. If there is no Value* for this operand, it returns
- /// EVT::Other.
+ /// MVT::Other.
EVT getCallOperandValEVT(const TargetLowering &TLI,
const TargetData *TD) const {
- if (CallOperandVal == 0) return EVT::Other;
+ if (CallOperandVal == 0) return MVT::Other;
if (isa<BasicBlock>(CallOperandVal))
return TLI.getPointerTy();
OpInfo.ConstraintVT);
unsigned NumRegs = 1;
- if (OpInfo.ConstraintVT != EVT::Other) {
+ if (OpInfo.ConstraintVT != MVT::Other) {
// If this is a FP input in an integer register (or visa versa) insert a bit
// cast of the input value. More generally, handle any case where the input
// value disagrees with the register class we plan to stick this in.
// assign it now.
if (unsigned AssignedReg = PhysReg.first) {
const TargetRegisterClass *RC = PhysReg.second;
- if (OpInfo.ConstraintVT == EVT::Other)
+ if (OpInfo.ConstraintVT == MVT::Other)
ValueVT = *RC->vt_begin();
// Get the actual register value type. This is important, because the user
// for this reference.
if (const TargetRegisterClass *RC = PhysReg.second) {
RegVT = *RC->vt_begin();
- if (OpInfo.ConstraintVT == EVT::Other)
+ if (OpInfo.ConstraintVT == MVT::Other)
ValueVT = RegVT;
// Create the appropriate number of virtual registers.
ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
- EVT OpVT = EVT::Other;
+ EVT OpVT = MVT::Other;
// Compute the value type for each operand.
switch (OpInfo.Type) {
std::vector<SDValue> AsmNodeOperands;
AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
AsmNodeOperands.push_back(
- DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), EVT::Other));
+ DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
// Loop over all of the inputs, copying the operand values into the
if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
- DAG.getVTList(EVT::Other, EVT::Flag),
+ DAG.getVTList(MVT::Other, MVT::Flag),
&AsmNodeOperands[0], AsmNodeOperands.size());
Flag = Chain.getValue(1);
getValue(StoresToEmit[i].second),
StoresToEmit[i].second, 0));
if (!OutChains.empty())
- Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), EVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
&OutChains[0], OutChains.size());
DAG.setRoot(Chain);
}
uint64_t ElementSize = TD->getTypeAllocSize(I.getType()->getElementType());
if (ElementSize != 1) {
// Src is always 32-bits, make sure the constant fits.
- assert(Src.getValueType() == EVT::i32);
+ assert(Src.getValueType() == MVT::i32);
ElementSize = (uint32_t)ElementSize;
Src = DAG.getNode(ISD::MUL, getCurDebugLoc(), Src.getValueType(),
Src, DAG.getConstant(ElementSize, Src.getValueType()));
void SelectionDAGLowering::visitVAStart(CallInst &I) {
DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
- EVT::Other, getRoot(),
+ MVT::Other, getRoot(),
getValue(I.getOperand(1)),
DAG.getSrcValue(I.getOperand(1))));
}
void SelectionDAGLowering::visitVAEnd(CallInst &I) {
DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
- EVT::Other, getRoot(),
+ MVT::Other, getRoot(),
getValue(I.getOperand(1)),
DAG.getSrcValue(I.getOperand(1))));
}
void SelectionDAGLowering::visitVACopy(CallInst &I) {
DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
- EVT::Other, getRoot(),
+ MVT::Other, getRoot(),
getValue(I.getOperand(1)),
getValue(I.getOperand(2)),
DAG.getSrcValue(I.getOperand(1)),
Outs, Ins, dl, DAG, InVals);
// Verify that the target's LowerCall behaved as expected.
- assert(Chain.getNode() && Chain.getValueType() == EVT::Other &&
+ assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
"LowerCall didn't return a valid chain!");
assert((!isTailCall || InVals.empty()) &&
"LowerCall emitted a return value for a tail call!");
dl, DAG, InVals);
// Verify that the target's LowerFormalArguments behaved as expected.
- assert(NewRoot.getNode() && NewRoot.getValueType() == EVT::Other &&
+ assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
"LowerFormalArguments didn't return a valid chain!");
assert(InVals.size() == Ins.size() &&
"LowerFormalArguments didn't emit the correct number of values!");
// use CreateRegForValue to create registers, so it always creates
// exactly one register for each non-void instruction.
EVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
- if (VT == EVT::Other || !TLI.isTypeLegal(VT)) {
- // Promote EVT::i1.
- if (VT == EVT::i1)
+ if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {
+ // Promote MVT::i1.
+ if (VT == MVT::i1)
VT = TLI.getTypeToTransformTo(VT);
else {
SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 97bb3b3ef9c5614e042ee5d768f58e4e83ddb044..3d1327f13e6ebd6b9114f037da6596f356e02cf2 100644 (file)
// Otherwise, add all chain operands to the worklist.
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
- if (N->getOperand(i).getValueType() == EVT::Other)
+ if (N->getOperand(i).getValueType() == MVT::Other)
Worklist.push_back(N->getOperand(i).getNode());
// If this is a CopyToReg with a vreg dest, process it.
Ops.push_back(InOps[1]); // input asm string.
unsigned i = 2, e = InOps.size();
- if (InOps[e-1].getValueType() == EVT::Flag)
+ if (InOps[e-1].getValueType() == MVT::Flag)
--e; // Don't process a flag operand if it is here.
while (i != e) {
// a cycle in the scheduling graph.
EVT VT = Root->getValueType(Root->getNumValues()-1);
- while (VT == EVT::Flag) {
+ while (VT == MVT::Flag) {
SDNode *FU = findFlagUse(Root);
if (FU == NULL)
break;
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
index ef451103617164784a919e2bd3f9973db31befe3..3b1100bb419c9651a8ad7e0579620a197fe57d8d 100644 (file)
static std::string getEdgeAttributes(const void *Node, EdgeIter EI) {
SDValue Op = EI.getNode()->getOperand(EI.getOperand());
EVT VT = Op.getValueType();
- if (VT == EVT::Flag)
+ if (VT == MVT::Flag)
return "color=red,style=bold";
- else if (VT == EVT::Other)
+ else if (VT == MVT::Other)
return "color=blue,style=dashed";
return "";
}
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index c7ddf0adb972b8c3945ac5ee096ddc3f589f6bae..958851f082d8e12c48ad183343ab2cd0aa724eec 100644 (file)
/// getFPEXT - Return the FPEXT_*_* value for the given types, or
/// UNKNOWN_LIBCALL if there is none.
RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
- if (OpVT == EVT::f32) {
- if (RetVT == EVT::f64)
+ if (OpVT == MVT::f32) {
+ if (RetVT == MVT::f64)
return FPEXT_F32_F64;
}
return UNKNOWN_LIBCALL;
/// getFPROUND - Return the FPROUND_*_* value for the given types, or
/// UNKNOWN_LIBCALL if there is none.
RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
- if (RetVT == EVT::f32) {
- if (OpVT == EVT::f64)
+ if (RetVT == MVT::f32) {
+ if (OpVT == MVT::f64)
return FPROUND_F64_F32;
- if (OpVT == EVT::f80)
+ if (OpVT == MVT::f80)
return FPROUND_F80_F32;
- if (OpVT == EVT::ppcf128)
+ if (OpVT == MVT::ppcf128)
return FPROUND_PPCF128_F32;
- } else if (RetVT == EVT::f64) {
- if (OpVT == EVT::f80)
+ } else if (RetVT == MVT::f64) {
+ if (OpVT == MVT::f80)
return FPROUND_F80_F64;
- if (OpVT == EVT::ppcf128)
+ if (OpVT == MVT::ppcf128)
return FPROUND_PPCF128_F64;
}
return UNKNOWN_LIBCALL;
/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
/// UNKNOWN_LIBCALL if there is none.
RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
- if (OpVT == EVT::f32) {
- if (RetVT == EVT::i8)
+ if (OpVT == MVT::f32) {
+ if (RetVT == MVT::i8)
return FPTOSINT_F32_I8;
- if (RetVT == EVT::i16)
+ if (RetVT == MVT::i16)
return FPTOSINT_F32_I16;
- if (RetVT == EVT::i32)
+ if (RetVT == MVT::i32)
return FPTOSINT_F32_I32;
- if (RetVT == EVT::i64)
+ if (RetVT == MVT::i64)
return FPTOSINT_F32_I64;
- if (RetVT == EVT::i128)
+ if (RetVT == MVT::i128)
return FPTOSINT_F32_I128;
- } else if (OpVT == EVT::f64) {
- if (RetVT == EVT::i32)
+ } else if (OpVT == MVT::f64) {
+ if (RetVT == MVT::i32)
return FPTOSINT_F64_I32;
- if (RetVT == EVT::i64)
+ if (RetVT == MVT::i64)
return FPTOSINT_F64_I64;
- if (RetVT == EVT::i128)
+ if (RetVT == MVT::i128)
return FPTOSINT_F64_I128;
- } else if (OpVT == EVT::f80) {
- if (RetVT == EVT::i32)
+ } else if (OpVT == MVT::f80) {
+ if (RetVT == MVT::i32)
return FPTOSINT_F80_I32;
- if (RetVT == EVT::i64)
+ if (RetVT == MVT::i64)
return FPTOSINT_F80_I64;
- if (RetVT == EVT::i128)
+ if (RetVT == MVT::i128)
return FPTOSINT_F80_I128;
- } else if (OpVT == EVT::ppcf128) {
- if (RetVT == EVT::i32)
+ } else if (OpVT == MVT::ppcf128) {
+ if (RetVT == MVT::i32)
return FPTOSINT_PPCF128_I32;
- if (RetVT == EVT::i64)
+ if (RetVT == MVT::i64)
return FPTOSINT_PPCF128_I64;
- if (RetVT == EVT::i128)
+ if (RetVT == MVT::i128)
return FPTOSINT_PPCF128_I128;
}
return UNKNOWN_LIBCALL;
/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
/// UNKNOWN_LIBCALL if there is none.
RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
- if (OpVT == EVT::f32) {
- if (RetVT == EVT::i8)
+ if (OpVT == MVT::f32) {
+ if (RetVT == MVT::i8)
return FPTOUINT_F32_I8;
- if (RetVT == EVT::i16)
+ if (RetVT == MVT::i16)
return FPTOUINT_F32_I16;
- if (RetVT == EVT::i32)
+ if (RetVT == MVT::i32)
return FPTOUINT_F32_I32;
- if (RetVT == EVT::i64)
+ if (RetVT == MVT::i64)
return FPTOUINT_F32_I64;
- if (RetVT == EVT::i128)
+ if (RetVT == MVT::i128)
return FPTOUINT_F32_I128;
- } else if (OpVT == EVT::f64) {
- if (RetVT == EVT::i32)
+ } else if (OpVT == MVT::f64) {
+ if (RetVT == MVT::i32)
return FPTOUINT_F64_I32;
- if (RetVT == EVT::i64)
+ if (RetVT == MVT::i64)
return FPTOUINT_F64_I64;
- if (RetVT == EVT::i128)
+ if (RetVT == MVT::i128)
return FPTOUINT_F64_I128;
- } else if (OpVT == EVT::f80) {
- if (RetVT == EVT::i32)
+ } else if (OpVT == MVT::f80) {
+ if (RetVT == MVT::i32)
return FPTOUINT_F80_I32;
- if (RetVT == EVT::i64)
+ if (RetVT == MVT::i64)
return FPTOUINT_F80_I64;
- if (RetVT == EVT::i128)
+ if (RetVT == MVT::i128)
return FPTOUINT_F80_I128;
- } else if (OpVT == EVT::ppcf128) {
- if (RetVT == EVT::i32)
+ } else if (OpVT == MVT::ppcf128) {
+ if (RetVT == MVT::i32)
return FPTOUINT_PPCF128_I32;
- if (RetVT == EVT::i64)
+ if (RetVT == MVT::i64)
return FPTOUINT_PPCF128_I64;
- if (RetVT == EVT::i128)
+ if (RetVT == MVT::i128)
return FPTOUINT_PPCF128_I128;
}
return UNKNOWN_LIBCALL;
/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
/// UNKNOWN_LIBCALL if there is none.
RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
- if (OpVT == EVT::i32) {
- if (RetVT == EVT::f32)
+ if (OpVT == MVT::i32) {
+ if (RetVT == MVT::f32)
return SINTTOFP_I32_F32;
- else if (RetVT == EVT::f64)
+ else if (RetVT == MVT::f64)
return SINTTOFP_I32_F64;
- else if (RetVT == EVT::f80)
+ else if (RetVT == MVT::f80)
return SINTTOFP_I32_F80;
- else if (RetVT == EVT::ppcf128)
+ else if (RetVT == MVT::ppcf128)
return SINTTOFP_I32_PPCF128;
- } else if (OpVT == EVT::i64) {
- if (RetVT == EVT::f32)
+ } else if (OpVT == MVT::i64) {
+ if (RetVT == MVT::f32)
return SINTTOFP_I64_F32;
- else if (RetVT == EVT::f64)
+ else if (RetVT == MVT::f64)
return SINTTOFP_I64_F64;
- else if (RetVT == EVT::f80)
+ else if (RetVT == MVT::f80)
return SINTTOFP_I64_F80;
- else if (RetVT == EVT::ppcf128)
+ else if (RetVT == MVT::ppcf128)
return SINTTOFP_I64_PPCF128;
- } else if (OpVT == EVT::i128) {
- if (RetVT == EVT::f32)
+ } else if (OpVT == MVT::i128) {
+ if (RetVT == MVT::f32)
return SINTTOFP_I128_F32;
- else if (RetVT == EVT::f64)
+ else if (RetVT == MVT::f64)
return SINTTOFP_I128_F64;
- else if (RetVT == EVT::f80)
+ else if (RetVT == MVT::f80)
return SINTTOFP_I128_F80;
- else if (RetVT == EVT::ppcf128)
+ else if (RetVT == MVT::ppcf128)
return SINTTOFP_I128_PPCF128;
}
return UNKNOWN_LIBCALL;
/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
/// UNKNOWN_LIBCALL if there is none.
RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
- if (OpVT == EVT::i32) {
- if (RetVT == EVT::f32)
+ if (OpVT == MVT::i32) {
+ if (RetVT == MVT::f32)
return UINTTOFP_I32_F32;
- else if (RetVT == EVT::f64)
+ else if (RetVT == MVT::f64)
return UINTTOFP_I32_F64;
- else if (RetVT == EVT::f80)
+ else if (RetVT == MVT::f80)
return UINTTOFP_I32_F80;
- else if (RetVT == EVT::ppcf128)
+ else if (RetVT == MVT::ppcf128)
return UINTTOFP_I32_PPCF128;
- } else if (OpVT == EVT::i64) {
- if (RetVT == EVT::f32)
+ } else if (OpVT == MVT::i64) {
+ if (RetVT == MVT::f32)
return UINTTOFP_I64_F32;
- else if (RetVT == EVT::f64)
+ else if (RetVT == MVT::f64)
return UINTTOFP_I64_F64;
- else if (RetVT == EVT::f80)
+ else if (RetVT == MVT::f80)
return UINTTOFP_I64_F80;
- else if (RetVT == EVT::ppcf128)
+ else if (RetVT == MVT::ppcf128)
return UINTTOFP_I64_PPCF128;
- } else if (OpVT == EVT::i128) {
- if (RetVT == EVT::f32)
+ } else if (OpVT == MVT::i128) {
+ if (RetVT == MVT::f32)
return UINTTOFP_I128_F32;
- else if (RetVT == EVT::f64)
+ else if (RetVT == MVT::f64)
return UINTTOFP_I128_F64;
- else if (RetVT == EVT::f80)
+ else if (RetVT == MVT::f80)
return UINTTOFP_I128_F80;
- else if (RetVT == EVT::ppcf128)
+ else if (RetVT == MVT::ppcf128)
return UINTTOFP_I128_PPCF128;
}
return UNKNOWN_LIBCALL;
@@ -456,48 +456,49 @@ TargetLowering::TargetLowering(TargetMachine &tm,TargetLoweringObjectFile *tlof)
memset(CondCodeActions, 0, sizeof(CondCodeActions));
// Set default actions for various operations.
- for (unsigned VT = 0; VT != (unsigned)EVT::LAST_VALUETYPE; ++VT) {
+ for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
// Default all indexed load / store to expand.
for (unsigned IM = (unsigned)ISD::PRE_INC;
IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
- setIndexedLoadAction(IM, (EVT::SimpleValueType)VT, Expand);
- setIndexedStoreAction(IM, (EVT::SimpleValueType)VT, Expand);
+ setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
+ setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
}
// These operations default to expand.
- setOperationAction(ISD::FGETSIGN, (EVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::CONCAT_VECTORS, (EVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
}
// Most targets ignore the @llvm.prefetch intrinsic.
- setOperationAction(ISD::PREFETCH, EVT::Other, Expand);
+ setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
// ConstantFP nodes default to expand. Targets can either change this to
// Legal, in which case all fp constants are legal, or use addLegalFPImmediate
// to optimize expansions for certain constants.
- setOperationAction(ISD::ConstantFP, EVT::f32, Expand);
- setOperationAction(ISD::ConstantFP, EVT::f64, Expand);
- setOperationAction(ISD::ConstantFP, EVT::f80, Expand);
+ setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
+ setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
+ setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
// These library functions default to expand.
- setOperationAction(ISD::FLOG , EVT::f64, Expand);
- setOperationAction(ISD::FLOG2, EVT::f64, Expand);
- setOperationAction(ISD::FLOG10,EVT::f64, Expand);
- setOperationAction(ISD::FEXP , EVT::f64, Expand);
- setOperationAction(ISD::FEXP2, EVT::f64, Expand);
- setOperationAction(ISD::FLOG , EVT::f32, Expand);
- setOperationAction(ISD::FLOG2, EVT::f32, Expand);
- setOperationAction(ISD::FLOG10,EVT::f32, Expand);
- setOperationAction(ISD::FEXP , EVT::f32, Expand);
- setOperationAction(ISD::FEXP2, EVT::f32, Expand);
+ setOperationAction(ISD::FLOG , MVT::f64, Expand);
+ setOperationAction(ISD::FLOG2, MVT::f64, Expand);
+ setOperationAction(ISD::FLOG10,MVT::f64, Expand);
+ setOperationAction(ISD::FEXP , MVT::f64, Expand);
+ setOperationAction(ISD::FEXP2, MVT::f64, Expand);
+ setOperationAction(ISD::FLOG , MVT::f32, Expand);
+ setOperationAction(ISD::FLOG2, MVT::f32, Expand);
+ setOperationAction(ISD::FLOG10,MVT::f32, Expand);
+ setOperationAction(ISD::FEXP , MVT::f32, Expand);
+ setOperationAction(ISD::FEXP2, MVT::f32, Expand);
// Default ISD::TRAP to expand (which turns it into abort).
- setOperationAction(ISD::TRAP, EVT::Other, Expand);
+ setOperationAction(ISD::TRAP, MVT::Other, Expand);
IsLittleEndian = TD->isLittleEndian();
UsesGlobalOffsetTable = false;
- ShiftAmountTy = PointerTy = getValueType(TD->getIntPtrType()).getSimpleVT();
- memset(RegClassForVT, 0,EVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
+ ShiftAmountTy = PointerTy =
+ getValueType(TD->getIntPtrType()).getSimpleVT().SimpleTy;
+ memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
allowUnalignedMemoryAccesses = false;
@@ -524,7 +525,7 @@ TargetLowering::TargetLowering(TargetMachine &tm,TargetLoweringObjectFile *tlof)
// Tell Legalize whether the assembler supports DEBUG_LOC.
const TargetAsmInfo *TASM = TM.getTargetAsmInfo();
if (!TASM || !TASM->hasDotLocAndDotFile())
- setOperationAction(ISD::DEBUG_LOC, EVT::Other, Expand);
+ setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
}
TargetLowering::~TargetLowering() {
/// computeRegisterProperties - Once all of the register classes are added,
/// this allows us to compute derived properties we expose.
void TargetLowering::computeRegisterProperties() {
- assert(EVT::LAST_VALUETYPE <= EVT::MAX_ALLOWED_VALUETYPE &&
+ assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
"Too many value types for ValueTypeActions to hold!");
// Everything defaults to needing one register.
- for (unsigned i = 0; i != EVT::LAST_VALUETYPE; ++i) {
+ for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
NumRegistersForVT[i] = 1;
- RegisterTypeForVT[i] = TransformToType[i] = (EVT::SimpleValueType)i;
+ RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
}
// ...except isVoid, which doesn't need any registers.
- NumRegistersForVT[EVT::isVoid] = 0;
+ NumRegistersForVT[MVT::isVoid] = 0;
// Find the largest integer register class.
- unsigned LargestIntReg = EVT::LAST_INTEGER_VALUETYPE;
+ unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
- assert(LargestIntReg != EVT::i1 && "No integer registers defined!");
+ assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
// Every integer value type larger than this largest register takes twice as
// many registers to represent as the previous ValueType.
for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) {
- EVT EVT = (EVT::SimpleValueType)ExpandedReg;
+ EVT EVT = (MVT::SimpleValueType)ExpandedReg;
if (!EVT.isInteger())
break;
NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
- RegisterTypeForVT[ExpandedReg] = (EVT::SimpleValueType)LargestIntReg;
- TransformToType[ExpandedReg] = (EVT::SimpleValueType)(ExpandedReg - 1);
+ RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
+ TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
ValueTypeActions.setTypeAction(EVT, Expand);
}
// register to see which ones need promotion.
unsigned LegalIntReg = LargestIntReg;
for (unsigned IntReg = LargestIntReg - 1;
- IntReg >= (unsigned)EVT::i1; --IntReg) {
- EVT IVT = (EVT::SimpleValueType)IntReg;
+ IntReg >= (unsigned)MVT::i1; --IntReg) {
+ EVT IVT = (MVT::SimpleValueType)IntReg;
if (isTypeLegal(IVT)) {
LegalIntReg = IntReg;
} else {
RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
- (EVT::SimpleValueType)LegalIntReg;
+ (MVT::SimpleValueType)LegalIntReg;
ValueTypeActions.setTypeAction(IVT, Promote);
}
}
// ppcf128 type is really two f64's.
- if (!isTypeLegal(EVT::ppcf128)) {
- NumRegistersForVT[EVT::ppcf128] = 2*NumRegistersForVT[EVT::f64];
- RegisterTypeForVT[EVT::ppcf128] = EVT::f64;
- TransformToType[EVT::ppcf128] = EVT::f64;
- ValueTypeActions.setTypeAction(EVT::ppcf128, Expand);
+ if (!isTypeLegal(MVT::ppcf128)) {
+ NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
+ RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
+ TransformToType[MVT::ppcf128] = MVT::f64;
+ ValueTypeActions.setTypeAction(MVT::ppcf128, Expand);
}
// Decide how to handle f64. If the target does not have native f64 support,
// expand it to i64 and we will be generating soft float library calls.
- if (!isTypeLegal(EVT::f64)) {
- NumRegistersForVT[EVT::f64] = NumRegistersForVT[EVT::i64];
- RegisterTypeForVT[EVT::f64] = RegisterTypeForVT[EVT::i64];
- TransformToType[EVT::f64] = EVT::i64;
- ValueTypeActions.setTypeAction(EVT::f64, Expand);
+ if (!isTypeLegal(MVT::f64)) {
+ NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
+ RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
+ TransformToType[MVT::f64] = MVT::i64;
+ ValueTypeActions.setTypeAction(MVT::f64, Expand);
}
// Decide how to handle f32. If the target does not have native support for
// f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
- if (!isTypeLegal(EVT::f32)) {
- if (isTypeLegal(EVT::f64)) {
- NumRegistersForVT[EVT::f32] = NumRegistersForVT[EVT::f64];
- RegisterTypeForVT[EVT::f32] = RegisterTypeForVT[EVT::f64];
- TransformToType[EVT::f32] = EVT::f64;
- ValueTypeActions.setTypeAction(EVT::f32, Promote);
+ if (!isTypeLegal(MVT::f32)) {
+ if (isTypeLegal(MVT::f64)) {
+ NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
+ RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
+ TransformToType[MVT::f32] = MVT::f64;
+ ValueTypeActions.setTypeAction(MVT::f32, Promote);
} else {
- NumRegistersForVT[EVT::f32] = NumRegistersForVT[EVT::i32];
- RegisterTypeForVT[EVT::f32] = RegisterTypeForVT[EVT::i32];
- TransformToType[EVT::f32] = EVT::i32;
- ValueTypeActions.setTypeAction(EVT::f32, Expand);
+ NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
+ RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
+ TransformToType[MVT::f32] = MVT::i32;
+ ValueTypeActions.setTypeAction(MVT::f32, Expand);
}
}
// Loop over all of the vector value types to see which need transformations.
- for (unsigned i = EVT::FIRST_VECTOR_VALUETYPE;
- i <= (unsigned)EVT::LAST_VECTOR_VALUETYPE; ++i) {
- EVT VT = (EVT::SimpleValueType)i;
+ for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
+ i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
+ EVT VT = (MVT::SimpleValueType)i;
if (!isTypeLegal(VT)) {
EVT IntermediateVT, RegisterVT;
unsigned NumIntermediates;
bool IsLegalWiderType = false;
EVT EltVT = VT.getVectorElementType();
unsigned NElts = VT.getVectorNumElements();
- for (unsigned nVT = i+1; nVT <= EVT::LAST_VECTOR_VALUETYPE; ++nVT) {
- EVT SVT = (EVT::SimpleValueType)nVT;
+ for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
+ EVT SVT = (MVT::SimpleValueType)nVT;
if (isTypeLegal(SVT) && SVT.getVectorElementType() == EltVT &&
SVT.getVectorNumElements() > NElts) {
TransformToType[i] = SVT;
EVT NVT = VT.getPow2VectorType();
if (NVT == VT) {
// Type is already a power of 2. The default action is to split.
- TransformToType[i] = EVT::Other;
+ TransformToType[i] = MVT::Other;
ValueTypeActions.setTypeAction(VT, Expand);
} else {
TransformToType[i] = NVT;
}
-EVT::SimpleValueType TargetLowering::getSetCCResultType(EVT VT) const {
- return getValueType(TD->getIntPtrType()).getSimpleVT();
+MVT::SimpleValueType TargetLowering::getSetCCResultType(EVT VT) const {
+ return getValueType(TD->getIntPtrType()).getSimpleVT().SimpleTy;
}
/// getVectorTypeBreakdown - Vector types are broken down into some number of
-/// legal first class types. For example, EVT::v8f32 maps to 2 EVT::v4f32
-/// with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack.
-/// Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86.
+/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
+/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
+/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
///
/// This method returns the number of registers needed, and the VT for each
/// register. It also returns the VT and quantity of the intermediate values
/// getWidenVectorType: given a vector type, returns the type to widen to
/// (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
-/// If there is no vector type that we want to widen to, returns EVT::Other
+/// If there is no vector type that we want to widen to, returns MVT::Other
/// When and where to widen is target dependent based on the cost of
/// scalarizing vs using the wider vector type.
EVT TargetLowering::getWidenVectorType(EVT VT) const {
return VT;
// Default is not to widen until moved to LegalizeTypes
- return EVT::Other;
+ return MVT::Other;
}
/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
// If this is an FP->Int bitcast and if the sign bit is the only thing that
// is demanded, turn this into a FGETSIGN.
if (NewMask == EVT::getIntegerVTSignBit(Op.getValueType()) &&
- EVT::isFloatingPoint(Op.getOperand(0).getValueType()) &&
- !EVT::isVector(Op.getOperand(0).getValueType())) {
+ MVT::isFloatingPoint(Op.getOperand(0).getValueType()) &&
+ !MVT::isVector(Op.getOperand(0).getValueType())) {
// Only do this xform if FGETSIGN is valid or if before legalize.
if (!TLO.AfterLegalize ||
isOperationLegal(ISD::FGETSIGN, Op.getValueType())) {
// Fold away ALL boolean setcc's.
SDValue Temp;
- if (N0.getValueType() == EVT::i1 && foldBooleans) {
+ if (N0.getValueType() == MVT::i1 && foldBooleans) {
switch (Cond) {
default: llvm_unreachable("Unknown integer setcc!");
case ISD::SETEQ: // X == Y -> ~(X^Y)
- Temp = DAG.getNode(ISD::XOR, dl, EVT::i1, N0, N1);
- N0 = DAG.getNOT(dl, Temp, EVT::i1);
+ Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
+ N0 = DAG.getNOT(dl, Temp, MVT::i1);
if (!DCI.isCalledByLegalizer())
DCI.AddToWorklist(Temp.getNode());
break;
case ISD::SETNE: // X != Y --> (X^Y)
- N0 = DAG.getNode(ISD::XOR, dl, EVT::i1, N0, N1);
+ N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
break;
case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
- Temp = DAG.getNOT(dl, N0, EVT::i1);
- N0 = DAG.getNode(ISD::AND, dl, EVT::i1, N1, Temp);
+ Temp = DAG.getNOT(dl, N0, MVT::i1);
+ N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
if (!DCI.isCalledByLegalizer())
DCI.AddToWorklist(Temp.getNode());
break;
case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
- Temp = DAG.getNOT(dl, N1, EVT::i1);
- N0 = DAG.getNode(ISD::AND, dl, EVT::i1, N0, Temp);
+ Temp = DAG.getNOT(dl, N1, MVT::i1);
+ N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
if (!DCI.isCalledByLegalizer())
DCI.AddToWorklist(Temp.getNode());
break;
case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
- Temp = DAG.getNOT(dl, N0, EVT::i1);
- N0 = DAG.getNode(ISD::OR, dl, EVT::i1, N1, Temp);
+ Temp = DAG.getNOT(dl, N0, MVT::i1);
+ N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
if (!DCI.isCalledByLegalizer())
DCI.AddToWorklist(Temp.getNode());
break;
case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
- Temp = DAG.getNOT(dl, N1, EVT::i1);
- N0 = DAG.getNode(ISD::OR, dl, EVT::i1, N0, Temp);
+ Temp = DAG.getNOT(dl, N1, MVT::i1);
+ N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
break;
}
- if (VT != EVT::i1) {
+ if (VT != MVT::i1) {
if (!DCI.isCalledByLegalizer())
DCI.AddToWorklist(N0.getNode());
// FIXME: If running after legalize, we probably can't do this.
// now; without this it would get ZExt'd later in
// ScheduleDAGSDNodes::EmitNode, which is very generic.
Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
- EVT::i64));
+ MVT::i64));
return;
}
}
index d236945f534b879fdf1676f1c7dc00d128428e92..b2173c6ca5da7ac95b436264765301b98df9dbb1 100644 (file)
/// getI32Imm - Return a target constant with the specified value, of type i32.
inline SDValue getI32Imm(unsigned Imm) {
- return CurDAG->getTargetConstant(Imm, EVT::i32);
+ return CurDAG->getTargetConstant(Imm, MVT::i32);
}
SDNode *Select(SDValue Op);
BaseReg = N.getOperand(0);
unsigned ShImmVal = 0;
if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
- ShReg = CurDAG->getRegister(0, EVT::i32);
+ ShReg = CurDAG->getRegister(0, MVT::i32);
ShImmVal = RHS->getZExtValue() & 31;
} else {
ShReg = N.getOperand(1);
}
Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
- EVT::i32);
+ MVT::i32);
return true;
}
Base = Offset = N.getOperand(0);
Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
ARM_AM::lsl),
- EVT::i32);
+ MVT::i32);
return true;
}
}
} else if (N.getOpcode() == ARMISD::Wrapper) {
Base = N.getOperand(0);
}
- Offset = CurDAG->getRegister(0, EVT::i32);
+ Offset = CurDAG->getRegister(0, MVT::i32);
Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
ARM_AM::no_shift),
- EVT::i32);
+ MVT::i32);
return true;
}
int FI = cast<FrameIndexSDNode>(Base)->getIndex();
Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
}
- Offset = CurDAG->getRegister(0, EVT::i32);
+ Offset = CurDAG->getRegister(0, MVT::i32);
ARM_AM::AddrOpc AddSub = ARM_AM::add;
if (RHSC < 0) {
}
Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
ARM_AM::no_shift),
- EVT::i32);
+ MVT::i32);
return true;
}
}
}
Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
- EVT::i32);
+ MVT::i32);
return true;
}
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
int Val = (int)C->getZExtValue();
if (Val >= 0 && Val < 0x1000) { // 12 bits.
- Offset = CurDAG->getRegister(0, EVT::i32);
+ Offset = CurDAG->getRegister(0, MVT::i32);
Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
ARM_AM::no_shift),
- EVT::i32);
+ MVT::i32);
return true;
}
}
}
Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
- EVT::i32);
+ MVT::i32);
return true;
}
// X - C is canonicalize to X + -C, no need to handle it here.
Base = N.getOperand(0);
Offset = N.getOperand(1);
- Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),EVT::i32);
+ Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
return true;
}
int FI = cast<FrameIndexSDNode>(N)->getIndex();
Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
}
- Offset = CurDAG->getRegister(0, EVT::i32);
- Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),EVT::i32);
+ Offset = CurDAG->getRegister(0, MVT::i32);
+ Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
return true;
}
int FI = cast<FrameIndexSDNode>(Base)->getIndex();
Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
}
- Offset = CurDAG->getRegister(0, EVT::i32);
+ Offset = CurDAG->getRegister(0, MVT::i32);
ARM_AM::AddrOpc AddSub = ARM_AM::add;
if (RHSC < 0) {
AddSub = ARM_AM::sub;
RHSC = - RHSC;
}
- Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),EVT::i32);
+ Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
return true;
}
}
Base = N.getOperand(0);
Offset = N.getOperand(1);
- Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), EVT::i32);
+ Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
return true;
}
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
int Val = (int)C->getZExtValue();
if (Val >= 0 && Val < 256) {
- Offset = CurDAG->getRegister(0, EVT::i32);
- Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), EVT::i32);
+ Offset = CurDAG->getRegister(0, MVT::i32);
+ Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
return true;
}
}
Offset = N;
- Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), EVT::i32);
+ Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
return true;
}
bool ARMDAGToDAGISel::SelectAddrMode4(SDValue Op, SDValue N,
SDValue &Addr, SDValue &Mode) {
Addr = N;
- Mode = CurDAG->getTargetConstant(0, EVT::i32);
+ Mode = CurDAG->getTargetConstant(0, MVT::i32);
return true;
}
Base = N.getOperand(0);
}
Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
- EVT::i32);
+ MVT::i32);
return true;
}
RHSC = - RHSC;
}
Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
- EVT::i32);
+ MVT::i32);
return true;
}
}
Base = N;
Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
- EVT::i32);
+ MVT::i32);
return true;
}
SDValue &Opc) {
Addr = N;
// The optional writeback is handled in ARMLoadStoreOpt.
- Update = CurDAG->getRegister(0, EVT::i32);
- Opc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(false), EVT::i32);
+ Update = CurDAG->getRegister(0, MVT::i32);
+ Opc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(false), MVT::i32);
return true;
}
Offset = N.getOperand(0);
SDValue N1 = N.getOperand(1);
Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
- EVT::i32);
+ MVT::i32);
return true;
}
return false;
if (N.getOpcode() != ISD::ADD) {
Base = (N.getOpcode() == ARMISD::Wrapper) ? N.getOperand(0) : N;
- Offset = CurDAG->getRegister(0, EVT::i32);
- OffImm = CurDAG->getTargetConstant(0, EVT::i32);
+ Offset = CurDAG->getRegister(0, MVT::i32);
+ OffImm = CurDAG->getTargetConstant(0, MVT::i32);
return true;
}
if ((LHSR && LHSR->getReg() == ARM::SP) ||
(RHSR && RHSR->getReg() == ARM::SP)) {
Base = N;
- Offset = CurDAG->getRegister(0, EVT::i32);
- OffImm = CurDAG->getTargetConstant(0, EVT::i32);
+ Offset = CurDAG->getRegister(0, MVT::i32);
+ OffImm = CurDAG->getTargetConstant(0, MVT::i32);
return true;
}
RHSC /= Scale;
if (RHSC >= 0 && RHSC < 32) {
Base = N.getOperand(0);
- Offset = CurDAG->getRegister(0, EVT::i32);
- OffImm = CurDAG->getTargetConstant(RHSC, EVT::i32);
+ Offset = CurDAG->getRegister(0, MVT::i32);
+ OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
return true;
}
}
Base = N.getOperand(0);
Offset = N.getOperand(1);
- OffImm = CurDAG->getTargetConstant(0, EVT::i32);
+ OffImm = CurDAG->getTargetConstant(0, MVT::i32);
return true;
}
if (N.getOpcode() == ISD::FrameIndex) {
int FI = cast<FrameIndexSDNode>(N)->getIndex();
Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
- OffImm = CurDAG->getTargetConstant(0, EVT::i32);
+ OffImm = CurDAG->getTargetConstant(0, MVT::i32);
return true;
}
int FI = cast<FrameIndexSDNode>(Base)->getIndex();
Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
}
- OffImm = CurDAG->getTargetConstant(RHSC, EVT::i32);
+ OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
return true;
}
}
// Match frame index...
int FI = cast<FrameIndexSDNode>(N)->getIndex();
Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
- OffImm = CurDAG->getTargetConstant(0, EVT::i32);
+ OffImm = CurDAG->getTargetConstant(0, MVT::i32);
return true;
} else if (N.getOpcode() == ARMISD::Wrapper) {
Base = N.getOperand(0);
return false; // We want to select t2LDRpci instead.
} else
Base = N;
- OffImm = CurDAG->getTargetConstant(0, EVT::i32);
+ OffImm = CurDAG->getTargetConstant(0, MVT::i32);
return true;
}
int FI = cast<FrameIndexSDNode>(Base)->getIndex();
Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
}
- OffImm = CurDAG->getTargetConstant(RHSC, EVT::i32);
+ OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
return true;
}
}
// Base only.
Base = N;
- OffImm = CurDAG->getTargetConstant(0, EVT::i32);
+ OffImm = CurDAG->getTargetConstant(0, MVT::i32);
return true;
}
int FI = cast<FrameIndexSDNode>(Base)->getIndex();
Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
}
- OffImm = CurDAG->getTargetConstant(RHSC, EVT::i32);
+ OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
return true;
}
}
int RHSC = (int)RHS->getZExtValue();
if (RHSC >= 0 && RHSC < 0x100) { // 8 bits.
OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
- ? CurDAG->getTargetConstant(RHSC, EVT::i32)
- : CurDAG->getTargetConstant(-RHSC, EVT::i32);
+ ? CurDAG->getTargetConstant(RHSC, MVT::i32)
+ : CurDAG->getTargetConstant(-RHSC, MVT::i32);
return true;
}
}
if (((RHSC & 0x3) == 0) &&
((RHSC >= 0 && RHSC < 0x400) || (RHSC < 0 && RHSC > -0x400))) { // 8 bits.
Base = N.getOperand(0);
- OffImm = CurDAG->getTargetConstant(RHSC, EVT::i32);
+ OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
return true;
}
}
int RHSC = (int)RHS->getZExtValue();
if (((RHSC & 0x3) == 0) && (RHSC >= 0 && RHSC < 0x400)) { // 8 bits.
Base = N.getOperand(0);
- OffImm = CurDAG->getTargetConstant(-RHSC, EVT::i32);
+ OffImm = CurDAG->getTargetConstant(-RHSC, MVT::i32);
return true;
}
}
}
}
- ShImm = CurDAG->getTargetConstant(ShAmt, EVT::i32);
+ ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);
return true;
}
/// getAL - Returns a ARMCC::AL immediate node.
static inline SDValue getAL(SelectionDAG *CurDAG) {
- return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, EVT::i32);
+ return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
}
SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDValue Op) {
bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
unsigned Opcode = 0;
bool Match = false;
- if (LoadedVT == EVT::i32 &&
+ if (LoadedVT == MVT::i32 &&
SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST;
Match = true;
- } else if (LoadedVT == EVT::i16 &&
+ } else if (LoadedVT == MVT::i16 &&
SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
Match = true;
Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
: (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
- } else if (LoadedVT == EVT::i8 || LoadedVT == EVT::i1) {
+ } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
if (LD->getExtensionType() == ISD::SEXTLOAD) {
if (SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
Match = true;
SDValue Chain = LD->getChain();
SDValue Base = LD->getBasePtr();
SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
- CurDAG->getRegister(0, EVT::i32), Chain };
- return CurDAG->getTargetNode(Opcode, Op.getDebugLoc(), EVT::i32, EVT::i32,
- EVT::Other, Ops, 6);
+ CurDAG->getRegister(0, MVT::i32), Chain };
+ return CurDAG->getTargetNode(Opcode, Op.getDebugLoc(), MVT::i32, MVT::i32,
+ MVT::Other, Ops, 6);
}
return NULL;
unsigned Opcode = 0;
bool Match = false;
if (SelectT2AddrModeImm8Offset(Op, LD->getOffset(), Offset)) {
- switch (LoadedVT.getSimpleVT()) {
- case EVT::i32:
+ switch (LoadedVT.getSimpleVT().SimpleTy) {
+ case MVT::i32:
Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
break;
- case EVT::i16:
+ case MVT::i16:
if (isSExtLd)
Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
else
Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
break;
- case EVT::i8:
- case EVT::i1:
+ case MVT::i8:
+ case MVT::i1:
if (isSExtLd)
Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
else
SDValue Chain = LD->getChain();
SDValue Base = LD->getBasePtr();
SDValue Ops[]= { Base, Offset, getAL(CurDAG),
- CurDAG->getRegister(0, EVT::i32), Chain };
- return CurDAG->getTargetNode(Opcode, Op.getDebugLoc(), EVT::i32, EVT::i32,
- EVT::Other, Ops, 5);
+ CurDAG->getRegister(0, MVT::i32), Chain };
+ return CurDAG->getTargetNode(Opcode, Op.getDebugLoc(), MVT::i32, MVT::i32,
+ MVT::Other, Ops, 5);
}
return NULL;
SDValue Chain = Op.getOperand(0);
SDValue Size = Op.getOperand(1);
SDValue Align = Op.getOperand(2);
- SDValue SP = CurDAG->getRegister(ARM::SP, EVT::i32);
+ SDValue SP = CurDAG->getRegister(ARM::SP, MVT::i32);
int32_t AlignVal = cast<ConstantSDNode>(Align)->getSExtValue();
if (AlignVal < 0)
// We need to align the stack. Use Thumb1 tAND which is the only thumb
// tSUBspi - immediate is between 0 ... 508 inclusive.
if (C <= 508 && ((C & 3) == 0))
// FIXME: tSUBspi encode scale 4 implicitly.
- return CurDAG->SelectNodeTo(N, ARM::tSUBspi_, VT, EVT::Other, SP,
- CurDAG->getTargetConstant(C/4, EVT::i32),
+ return CurDAG->SelectNodeTo(N, ARM::tSUBspi_, VT, MVT::Other, SP,
+ CurDAG->getTargetConstant(C/4, MVT::i32),
Chain);
if (Subtarget->isThumb1Only()) {
// should have negated the size operand already. FIXME: We can't insert
// new target independent node at this stage so we are forced to negate
// it earlier. Is there a better solution?
- return CurDAG->SelectNodeTo(N, ARM::tADDspr_, VT, EVT::Other, SP, Size,
+ return CurDAG->SelectNodeTo(N, ARM::tADDspr_, VT, MVT::Other, SP, Size,
Chain);
} else if (Subtarget->isThumb2()) {
if (isC && Predicate_t2_so_imm(Size.getNode())) {
// t2SUBrSPi
- SDValue Ops[] = { SP, CurDAG->getTargetConstant(C, EVT::i32), Chain };
- return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPi_, VT, EVT::Other, Ops, 3);
+ SDValue Ops[] = { SP, CurDAG->getTargetConstant(C, MVT::i32), Chain };
+ return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPi_, VT, MVT::Other, Ops, 3);
} else if (isC && Predicate_imm0_4095(Size.getNode())) {
// t2SUBrSPi12
- SDValue Ops[] = { SP, CurDAG->getTargetConstant(C, EVT::i32), Chain };
- return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPi12_, VT, EVT::Other, Ops, 3);
+ SDValue Ops[] = { SP, CurDAG->getTargetConstant(C, MVT::i32), Chain };
+ return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPi12_, VT, MVT::Other, Ops, 3);
} else {
// t2SUBrSPs
SDValue Ops[] = { SP, Size,
getI32Imm(ARM_AM::getSORegOpc(ARM_AM::lsl,0)), Chain };
- return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPs_, VT, EVT::Other, Ops, 4);
+ return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPs_, VT, MVT::Other, Ops, 4);
}
}
SDNode *ResNode;
if (Subtarget->isThumb1Only()) {
- SDValue Pred = CurDAG->getTargetConstant(0xEULL, EVT::i32);
- SDValue PredReg = CurDAG->getRegister(0, EVT::i32);
+ SDValue Pred = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
- ResNode = CurDAG->getTargetNode(ARM::tLDRcp, dl, EVT::i32, EVT::Other,
+ ResNode = CurDAG->getTargetNode(ARM::tLDRcp, dl, MVT::i32, MVT::Other,
Ops, 4);
} else {
SDValue Ops[] = {
CPIdx,
- CurDAG->getRegister(0, EVT::i32),
- CurDAG->getTargetConstant(0, EVT::i32),
+ CurDAG->getRegister(0, MVT::i32),
+ CurDAG->getTargetConstant(0, MVT::i32),
getAL(CurDAG),
- CurDAG->getRegister(0, EVT::i32),
+ CurDAG->getRegister(0, MVT::i32),
CurDAG->getEntryNode()
};
- ResNode=CurDAG->getTargetNode(ARM::LDRcp, dl, EVT::i32, EVT::Other,
+ ResNode=CurDAG->getTargetNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
Ops, 6);
}
ReplaceUses(Op, SDValue(ResNode, 0));
int FI = cast<FrameIndexSDNode>(N)->getIndex();
SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
if (Subtarget->isThumb1Only()) {
- return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, EVT::i32, TFI,
- CurDAG->getTargetConstant(0, EVT::i32));
+ return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI,
+ CurDAG->getTargetConstant(0, MVT::i32));
} else {
unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
ARM::t2ADDri : ARM::ADDri);
- SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, EVT::i32),
- getAL(CurDAG), CurDAG->getRegister(0, EVT::i32),
- CurDAG->getRegister(0, EVT::i32) };
- return CurDAG->SelectNodeTo(N, Opc, EVT::i32, Ops, 5);
+ SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
+ getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
+ CurDAG->getRegister(0, MVT::i32) };
+ return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
}
}
case ARMISD::DYN_ALLOC:
break;
SDValue V = Op.getOperand(0);
ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
- SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, EVT::i32);
- SDValue Reg0 = CurDAG->getRegister(0, EVT::i32);
+ SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
+ SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
if (Subtarget->isThumb()) {
SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
- return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, EVT::i32, Ops, 6);
+ return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6);
} else {
SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
- return CurDAG->SelectNodeTo(N, ARM::ADDrs, EVT::i32, Ops, 7);
+ return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 7);
}
}
if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
break;
SDValue V = Op.getOperand(0);
ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
- SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, EVT::i32);
- SDValue Reg0 = CurDAG->getRegister(0, EVT::i32);
+ SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
+ SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
if (Subtarget->isThumb()) {
SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0 };
- return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, EVT::i32, Ops, 5);
+ return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 5);
} else {
SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
- return CurDAG->SelectNodeTo(N, ARM::RSBrs, EVT::i32, Ops, 7);
+ return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 7);
}
}
}
break;
case ARMISD::FMRRD:
- return CurDAG->getTargetNode(ARM::FMRRD, dl, EVT::i32, EVT::i32,
+ return CurDAG->getTargetNode(ARM::FMRRD, dl, MVT::i32, MVT::i32,
Op.getOperand(0), getAL(CurDAG),
- CurDAG->getRegister(0, EVT::i32));
+ CurDAG->getRegister(0, MVT::i32));
case ISD::UMUL_LOHI: {
if (Subtarget->isThumb1Only())
break;
if (Subtarget->isThumb()) {
SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
- getAL(CurDAG), CurDAG->getRegister(0, EVT::i32),
- CurDAG->getRegister(0, EVT::i32) };
- return CurDAG->getTargetNode(ARM::t2UMULL, dl, EVT::i32, EVT::i32, Ops,4);
+ getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
+ CurDAG->getRegister(0, MVT::i32) };
+ return CurDAG->getTargetNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32, Ops,4);
} else {
SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
- getAL(CurDAG), CurDAG->getRegister(0, EVT::i32),
- CurDAG->getRegister(0, EVT::i32) };
- return CurDAG->getTargetNode(ARM::UMULL, dl, EVT::i32, EVT::i32, Ops, 5);
+ getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
+ CurDAG->getRegister(0, MVT::i32) };
+ return CurDAG->getTargetNode(ARM::UMULL, dl, MVT::i32, MVT::i32, Ops, 5);
}
}
case ISD::SMUL_LOHI: {
break;
if (Subtarget->isThumb()) {
SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
- getAL(CurDAG), CurDAG->getRegister(0, EVT::i32) };
- return CurDAG->getTargetNode(ARM::t2SMULL, dl, EVT::i32, EVT::i32, Ops,4);
+ getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
+ return CurDAG->getTargetNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32, Ops,4);
} else {
SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
- getAL(CurDAG), CurDAG->getRegister(0, EVT::i32),
- CurDAG->getRegister(0, EVT::i32) };
- return CurDAG->getTargetNode(ARM::SMULL, dl, EVT::i32, EVT::i32, Ops, 5);
+ getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
+ CurDAG->getRegister(0, MVT::i32) };
+ return CurDAG->getTargetNode(ARM::SMULL, dl, MVT::i32, MVT::i32, Ops, 5);
}
}
case ISD::LOAD: {
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
cast<ConstantSDNode>(N2)->getZExtValue()),
- EVT::i32);
+ MVT::i32);
SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
- SDNode *ResNode = CurDAG->getTargetNode(Opc, dl, EVT::Other,
- EVT::Flag, Ops, 5);
+ SDNode *ResNode = CurDAG->getTargetNode(Opc, dl, MVT::Other,
+ MVT::Flag, Ops, 5);
Chain = SDValue(ResNode, 0);
if (Op.getNode()->getNumValues() == 2) {
InFlag = SDValue(ResNode, 1);
assert(N2.getOpcode() == ISD::Constant);
assert(N3.getOpcode() == ISD::Register);
- if (!Subtarget->isThumb1Only() && VT == EVT::i32) {
+ if (!Subtarget->isThumb1Only() && VT == MVT::i32) {
// Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
// Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
// Pattern complexity = 18 cost = 1 size = 0
break;
}
SDValue SOShImm =
- CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), EVT::i32);
+ CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
cast<ConstantSDNode>(N2)->getZExtValue()),
- EVT::i32);
+ MVT::i32);
SDValue Ops[] = { N0, CPTmp0, SOShImm, Tmp2, N3, InFlag };
- return CurDAG->SelectNodeTo(Op.getNode(), Opc, EVT::i32,Ops, 6);
+ return CurDAG->SelectNodeTo(Op.getNode(), Opc, MVT::i32,Ops, 6);
}
} else {
if (SelectShifterOperandReg(Op, N1, CPTmp0, CPTmp1, CPTmp2)) {
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
cast<ConstantSDNode>(N2)->getZExtValue()),
- EVT::i32);
+ MVT::i32);
SDValue Ops[] = { N0, CPTmp0, CPTmp1, CPTmp2, Tmp2, N3, InFlag };
return CurDAG->SelectNodeTo(Op.getNode(),
- ARM::MOVCCs, EVT::i32, Ops, 7);
+ ARM::MOVCCs, MVT::i32, Ops, 7);
}
}
if (Predicate_t2_so_imm(N3.getNode())) {
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned)
cast<ConstantSDNode>(N1)->getZExtValue()),
- EVT::i32);
+ MVT::i32);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
cast<ConstantSDNode>(N2)->getZExtValue()),
- EVT::i32);
+ MVT::i32);
SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
return CurDAG->SelectNodeTo(Op.getNode(),
- ARM::t2MOVCCi, EVT::i32, Ops, 5);
+ ARM::t2MOVCCi, MVT::i32, Ops, 5);
}
} else {
if (Predicate_so_imm(N3.getNode())) {
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned)
cast<ConstantSDNode>(N1)->getZExtValue()),
- EVT::i32);
+ MVT::i32);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
cast<ConstantSDNode>(N2)->getZExtValue()),
- EVT::i32);
+ MVT::i32);
SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
return CurDAG->SelectNodeTo(Op.getNode(),
- ARM::MOVCCi, EVT::i32, Ops, 5);
+ ARM::MOVCCi, MVT::i32, Ops, 5);
}
}
}
// Also FCPYScc and FCPYDcc.
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
cast<ConstantSDNode>(N2)->getZExtValue()),
- EVT::i32);
+ MVT::i32);
SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
unsigned Opc = 0;
- switch (VT.getSimpleVT()) {
+ switch (VT.getSimpleVT().SimpleTy) {
default: assert(false && "Illegal conditional move type!");
break;
- case EVT::i32:
+ case MVT::i32:
Opc = Subtarget->isThumb()
? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr)
: ARM::MOVCCr;
break;
- case EVT::f32:
+ case MVT::f32:
Opc = ARM::FCPYScc;
break;
- case EVT::f64:
+ case MVT::f64:
Opc = ARM::FCPYDcc;
break;
}
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
cast<ConstantSDNode>(N2)->getZExtValue()),
- EVT::i32);
+ MVT::i32);
SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
unsigned Opc = 0;
- switch (VT.getSimpleVT()) {
+ switch (VT.getSimpleVT().SimpleTy) {
default: assert(false && "Illegal conditional move type!");
break;
- case EVT::f32:
+ case MVT::f32:
Opc = ARM::FNEGScc;
break;
- case EVT::f64:
+ case MVT::f64:
Opc = ARM::FNEGDcc;
break;
}
SDValue Tmp2 = CurDAG->getTargetGlobalAddress(GV, TLI.getPointerTy());
SDValue Ops[] = { Tmp1, Tmp2, Chain };
return CurDAG->getTargetNode(TargetInstrInfo::DECLARE, dl,
- EVT::Other, Ops, 3);
+ MVT::Other, Ops, 3);
}
case ISD::VECTOR_SHUFFLE: {
EVT HalfVT;
unsigned Opc = 0;
- switch (VT.getVectorElementType().getSimpleVT()) {
+ switch (VT.getVectorElementType().getSimpleVT().SimpleTy) {
default: llvm_unreachable("unhandled VDUP splat type");
- case EVT::i8: Opc = ARM::VDUPLN8q; HalfVT = EVT::v8i8; break;
- case EVT::i16: Opc = ARM::VDUPLN16q; HalfVT = EVT::v4i16; break;
- case EVT::i32: Opc = ARM::VDUPLN32q; HalfVT = EVT::v2i32; break;
- case EVT::f32: Opc = ARM::VDUPLNfq; HalfVT = EVT::v2f32; break;
+ case MVT::i8: Opc = ARM::VDUPLN8q; HalfVT = MVT::v8i8; break;
+ case MVT::i16: Opc = ARM::VDUPLN16q; HalfVT = MVT::v4i16; break;
+ case MVT::i32: Opc = ARM::VDUPLN32q; HalfVT = MVT::v2i32; break;
+ case MVT::f32: Opc = ARM::VDUPLNfq; HalfVT = MVT::v2f32; break;
}
// The source operand needs to be changed to a subreg of the original
// 128-bit operand, and the lane number needs to be adjusted accordingly.
unsigned NumElts = VT.getVectorNumElements() / 2;
unsigned SRVal = (LaneVal < NumElts ? arm_dsubreg_0 : arm_dsubreg_1);
- SDValue SR = CurDAG->getTargetConstant(SRVal, EVT::i32);
- SDValue NewLane = CurDAG->getTargetConstant(LaneVal % NumElts, EVT::i32);
+ SDValue SR = CurDAG->getTargetConstant(SRVal, MVT::i32);
+ SDValue NewLane = CurDAG->getTargetConstant(LaneVal % NumElts, MVT::i32);
SDNode *SubReg = CurDAG->getTargetNode(TargetInstrInfo::EXTRACT_SUBREG,
dl, HalfVT, N->getOperand(0), SR);
return CurDAG->SelectNodeTo(N, Opc, VT, SDValue(SubReg, 0), NewLane);
return NULL;
unsigned Opc = 0;
EVT VT = Op.getValueType();
- switch (VT.getSimpleVT()) {
+ switch (VT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("unhandled VLD2D type");
- case EVT::v8i8: Opc = ARM::VLD2d8; break;
- case EVT::v4i16: Opc = ARM::VLD2d16; break;
- case EVT::v2f32:
- case EVT::v2i32: Opc = ARM::VLD2d32; break;
+ case MVT::v8i8: Opc = ARM::VLD2d8; break;
+ case MVT::v4i16: Opc = ARM::VLD2d16; break;
+ case MVT::v2f32:
+ case MVT::v2i32: Opc = ARM::VLD2d32; break;
}
const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc };
- return CurDAG->getTargetNode(Opc, dl, VT, VT, EVT::Other, Ops, 3);
+ return CurDAG->getTargetNode(Opc, dl, VT, VT, MVT::Other, Ops, 3);
}
case ARMISD::VLD3D: {
return NULL;
unsigned Opc = 0;
EVT VT = Op.getValueType();
- switch (VT.getSimpleVT()) {
+ switch (VT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("unhandled VLD3D type");
- case EVT::v8i8: Opc = ARM::VLD3d8; break;
- case EVT::v4i16: Opc = ARM::VLD3d16; break;
- case EVT::v2f32:
- case EVT::v2i32: Opc = ARM::VLD3d32; break;
+ case MVT::v8i8: Opc = ARM::VLD3d8; break;
+ case MVT::v4i16: Opc = ARM::VLD3d16; break;
+ case MVT::v2f32:
+ case MVT::v2i32: Opc = ARM::VLD3d32; break;
}
const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc };
- return CurDAG->getTargetNode(Opc, dl, VT, VT, VT, EVT::Other, Ops, 3);
+ return CurDAG->getTargetNode(Opc, dl, VT, VT, VT, MVT::Other, Ops, 3);
}
case ARMISD::VLD4D: {
return NULL;
unsigned Opc = 0;
EVT VT = Op.getValueType();
- switch (VT.getSimpleVT()) {
+ switch (VT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("unhandled VLD4D type");
- case EVT::v8i8: Opc = ARM::VLD4d8; break;
- case EVT::v4i16: Opc = ARM::VLD4d16; break;
- case EVT::v2f32:
- case EVT::v2i32: Opc = ARM::VLD4d32; break;
+ case MVT::v8i8: Opc = ARM::VLD4d8; break;
+ case MVT::v4i16: Opc = ARM::VLD4d16; break;
+ case MVT::v2f32:
+ case MVT::v2i32: Opc = ARM::VLD4d32; break;
}
const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc };
std::vector<EVT> ResTys(4, VT);
- ResTys.push_back(EVT::Other);
+ ResTys.push_back(MVT::Other);
return CurDAG->getTargetNode(Opc, dl, ResTys, Ops, 3);
}
if (!SelectAddrMode6(Op, N->getOperand(1), MemAddr, MemUpdate, MemOpc))
return NULL;
unsigned Opc = 0;
- switch (N->getOperand(2).getValueType().getSimpleVT()) {
+ switch (N->getOperand(2).getValueType().getSimpleVT().SimpleTy) {
default: llvm_unreachable("unhandled VST2D type");
- case EVT::v8i8: Opc = ARM::VST2d8; break;
- case EVT::v4i16: Opc = ARM::VST2d16; break;
- case EVT::v2f32:
- case EVT::v2i32: Opc = ARM::VST2d32; break;
+ case MVT::v8i8: Opc = ARM::VST2d8; break;
+ case MVT::v4i16: Opc = ARM::VST2d16; break;
+ case MVT::v2f32:
+ case MVT::v2i32: Opc = ARM::VST2d32; break;
}
const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
N->getOperand(2), N->getOperand(3) };
- return CurDAG->getTargetNode(Opc, dl, EVT::Other, Ops, 5);
+ return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 5);
}
case ARMISD::VST3D: {
if (!SelectAddrMode6(Op, N->getOperand(1), MemAddr, MemUpdate, MemOpc))
return NULL;
unsigned Opc = 0;
- switch (N->getOperand(2).getValueType().getSimpleVT()) {
+ switch (N->getOperand(2).getValueType().getSimpleVT().SimpleTy) {
default: llvm_unreachable("unhandled VST3D type");
- case EVT::v8i8: Opc = ARM::VST3d8; break;
- case EVT::v4i16: Opc = ARM::VST3d16; break;
- case EVT::v2f32:
- case EVT::v2i32: Opc = ARM::VST3d32; break;
+ case MVT::v8i8: Opc = ARM::VST3d8; break;
+ case MVT::v4i16: Opc = ARM::VST3d16; break;
+ case MVT::v2f32:
+ case MVT::v2i32: Opc = ARM::VST3d32; break;
}
const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
N->getOperand(2), N->getOperand(3),
N->getOperand(4) };
- return CurDAG->getTargetNode(Opc, dl, EVT::Other, Ops, 6);
+ return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 6);
}
case ARMISD::VST4D: {
if (!SelectAddrMode6(Op, N->getOperand(1), MemAddr, MemUpdate, MemOpc))
return NULL;
unsigned Opc = 0;
- switch (N->getOperand(2).getValueType().getSimpleVT()) {
+ switch (N->getOperand(2).getValueType().getSimpleVT().SimpleTy) {
default: llvm_unreachable("unhandled VST4D type");
- case EVT::v8i8: Opc = ARM::VST4d8; break;
- case EVT::v4i16: Opc = ARM::VST4d16; break;
- case EVT::v2f32:
- case EVT::v2i32: Opc = ARM::VST4d32; break;
+ case MVT::v8i8: Opc = ARM::VST4d8; break;
+ case MVT::v4i16: Opc = ARM::VST4d16; break;
+ case MVT::v2f32:
+ case MVT::v2i32: Opc = ARM::VST4d32; break;
}
const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
N->getOperand(2), N->getOperand(3),
N->getOperand(4), N->getOperand(5) };
- return CurDAG->getTargetNode(Opc, dl, EVT::Other, Ops, 7);
+ return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 7);
}
case ISD::INTRINSIC_WO_CHAIN: {
default: break;
case Intrinsic::arm_neon_vtrn:
- switch (VT.getSimpleVT()) {
+ switch (VT.getSimpleVT().SimpleTy) {
default: return NULL;
- case EVT::v8i8: Opc = ARM::VTRNd8; break;
- case EVT::v4i16: Opc = ARM::VTRNd16; break;
- case EVT::v2f32:
- case EVT::v2i32: Opc = ARM::VTRNd32; break;
- case EVT::v16i8: Opc = ARM::VTRNq8; break;
- case EVT::v8i16: Opc = ARM::VTRNq16; break;
- case EVT::v4f32:
- case EVT::v4i32: Opc = ARM::VTRNq32; break;
+ case MVT::v8i8: Opc = ARM::VTRNd8; break;
+ case MVT::v4i16: Opc = ARM::VTRNd16; break;
+ case MVT::v2f32:
+ case MVT::v2i32: Opc = ARM::VTRNd32; break;
+ case MVT::v16i8: Opc = ARM::VTRNq8; break;
+ case MVT::v8i16: Opc = ARM::VTRNq16; break;
+ case MVT::v4f32:
+ case MVT::v4i32: Opc = ARM::VTRNq32; break;
}
return CurDAG->getTargetNode(Opc, dl, VT, VT, N->getOperand(1),
N->getOperand(2));
case Intrinsic::arm_neon_vuzp:
- switch (VT.getSimpleVT()) {
+ switch (VT.getSimpleVT().SimpleTy) {
default: return NULL;
- case EVT::v8i8: Opc = ARM::VUZPd8; break;
- case EVT::v4i16: Opc = ARM::VUZPd16; break;
- case EVT::v2f32:
- case EVT::v2i32: Opc = ARM::VUZPd32; break;
- case EVT::v16i8: Opc = ARM::VUZPq8; break;
- case EVT::v8i16: Opc = ARM::VUZPq16; break;
- case EVT::v4f32:
- case EVT::v4i32: Opc = ARM::VUZPq32; break;
+ case MVT::v8i8: Opc = ARM::VUZPd8; break;
+ case MVT::v4i16: Opc = ARM::VUZPd16; break;
+ case MVT::v2f32:
+ case MVT::v2i32: Opc = ARM::VUZPd32; break;
+ case MVT::v16i8: Opc = ARM::VUZPq8; break;
+ case MVT::v8i16: Opc = ARM::VUZPq16; break;
+ case MVT::v4f32:
+ case MVT::v4i32: Opc = ARM::VUZPq32; break;
}
return CurDAG->getTargetNode(Opc, dl, VT, VT, N->getOperand(1),
N->getOperand(2));
case Intrinsic::arm_neon_vzip:
- switch (VT.getSimpleVT()) {
+ switch (VT.getSimpleVT().SimpleTy) {
default: return NULL;
- case EVT::v8i8: Opc = ARM::VZIPd8; break;
- case EVT::v4i16: Opc = ARM::VZIPd16; break;
- case EVT::v2f32:
- case EVT::v2i32: Opc = ARM::VZIPd32; break;
- case EVT::v16i8: Opc = ARM::VZIPq8; break;
- case EVT::v8i16: Opc = ARM::VZIPq16; break;
- case EVT::v4f32:
- case EVT::v4i32: Opc = ARM::VZIPq32; break;
+ case MVT::v8i8: Opc = ARM::VZIPd8; break;
+ case MVT::v4i16: Opc = ARM::VZIPd16; break;
+ case MVT::v2f32:
+ case MVT::v2i32: Opc = ARM::VZIPd32; break;
+ case MVT::v16i8: Opc = ARM::VZIPq8; break;
+ case MVT::v8i16: Opc = ARM::VZIPq16; break;
+ case MVT::v4f32:
+ case MVT::v4i32: Opc = ARM::VZIPq32; break;
}
return CurDAG->getTargetNode(Opc, dl, VT, VT, N->getOperand(1),
N->getOperand(2));
index 316a6df93a90ccc6d19e7f417609d67f659cf266..921c604759bfd60b4c87338b377781fe73d247e8 100644 (file)
}
EVT ElemTy = VT.getVectorElementType();
- if (ElemTy != EVT::i64 && ElemTy != EVT::f64)
+ if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom);
- if (ElemTy == EVT::i8 || ElemTy == EVT::i16)
+ if (ElemTy == MVT::i8 || ElemTy == MVT::i16)
setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
void ARMTargetLowering::addDRTypeForNEON(EVT VT) {
addRegisterClass(VT, ARM::DPRRegisterClass);
- addTypeForNEON(VT, EVT::f64, EVT::v2i32);
+ addTypeForNEON(VT, MVT::f64, MVT::v2i32);
}
void ARMTargetLowering::addQRTypeForNEON(EVT VT) {
addRegisterClass(VT, ARM::QPRRegisterClass);
- addTypeForNEON(VT, EVT::v2f64, EVT::v4i32);
+ addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
}
static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
setLibcallName(RTLIB::SRA_I128, 0);
if (Subtarget->isThumb1Only())
- addRegisterClass(EVT::i32, ARM::tGPRRegisterClass);
+ addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
else
- addRegisterClass(EVT::i32, ARM::GPRRegisterClass);
+ addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
- addRegisterClass(EVT::f32, ARM::SPRRegisterClass);
- addRegisterClass(EVT::f64, ARM::DPRRegisterClass);
+ addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
+ addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
- setTruncStoreAction(EVT::f64, EVT::f32, Expand);
+ setTruncStoreAction(MVT::f64, MVT::f32, Expand);
}
if (Subtarget->hasNEON()) {
- addDRTypeForNEON(EVT::v2f32);
- addDRTypeForNEON(EVT::v8i8);
- addDRTypeForNEON(EVT::v4i16);
- addDRTypeForNEON(EVT::v2i32);
- addDRTypeForNEON(EVT::v1i64);
-
- addQRTypeForNEON(EVT::v4f32);
- addQRTypeForNEON(EVT::v2f64);
- addQRTypeForNEON(EVT::v16i8);
- addQRTypeForNEON(EVT::v8i16);
- addQRTypeForNEON(EVT::v4i32);
- addQRTypeForNEON(EVT::v2i64);
+ addDRTypeForNEON(MVT::v2f32);
+ addDRTypeForNEON(MVT::v8i8);
+ addDRTypeForNEON(MVT::v4i16);
+ addDRTypeForNEON(MVT::v2i32);
+ addDRTypeForNEON(MVT::v1i64);
+
+ addQRTypeForNEON(MVT::v4f32);
+ addQRTypeForNEON(MVT::v2f64);
+ addQRTypeForNEON(MVT::v16i8);
+ addQRTypeForNEON(MVT::v8i16);
+ addQRTypeForNEON(MVT::v4i32);
+ addQRTypeForNEON(MVT::v2i64);
setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
setTargetDAGCombine(ISD::SHL);
computeRegisterProperties();
// ARM does not have f32 extending load.
- setLoadExtAction(ISD::EXTLOAD, EVT::f32, Expand);
+ setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
// ARM does not have i1 sign extending load.
- setLoadExtAction(ISD::SEXTLOAD, EVT::i1, Promote);
+ setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
// ARM supports all 4 flavors of integer indexed load / store.
if (!Subtarget->isThumb1Only()) {
for (unsigned im = (unsigned)ISD::PRE_INC;
im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
- setIndexedLoadAction(im, EVT::i1, Legal);
- setIndexedLoadAction(im, EVT::i8, Legal);
- setIndexedLoadAction(im, EVT::i16, Legal);
- setIndexedLoadAction(im, EVT::i32, Legal);
- setIndexedStoreAction(im, EVT::i1, Legal);
- setIndexedStoreAction(im, EVT::i8, Legal);
- setIndexedStoreAction(im, EVT::i16, Legal);
- setIndexedStoreAction(im, EVT::i32, Legal);
+ setIndexedLoadAction(im, MVT::i1, Legal);
+ setIndexedLoadAction(im, MVT::i8, Legal);
+ setIndexedLoadAction(im, MVT::i16, Legal);
+ setIndexedLoadAction(im, MVT::i32, Legal);
+ setIndexedStoreAction(im, MVT::i1, Legal);
+ setIndexedStoreAction(im, MVT::i8, Legal);
+ setIndexedStoreAction(im, MVT::i16, Legal);
+ setIndexedStoreAction(im, MVT::i32, Legal);
}
}
// i64 operation support.
if (Subtarget->isThumb1Only()) {
- setOperationAction(ISD::MUL, EVT::i64, Expand);
- setOperationAction(ISD::MULHU, EVT::i32, Expand);
- setOperationAction(ISD::MULHS, EVT::i32, Expand);
- setOperationAction(ISD::UMUL_LOHI, EVT::i32, Expand);
- setOperationAction(ISD::SMUL_LOHI, EVT::i32, Expand);
+ setOperationAction(ISD::MUL, MVT::i64, Expand);
+ setOperationAction(ISD::MULHU, MVT::i32, Expand);
+ setOperationAction(ISD::MULHS, MVT::i32, Expand);
+ setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
+ setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
} else {
- setOperationAction(ISD::MUL, EVT::i64, Expand);
- setOperationAction(ISD::MULHU, EVT::i32, Expand);
+ setOperationAction(ISD::MUL, MVT::i64, Expand);
+ setOperationAction(ISD::MULHU, MVT::i32, Expand);
if (!Subtarget->hasV6Ops())
- setOperationAction(ISD::MULHS, EVT::i32, Expand);
+ setOperationAction(ISD::MULHS, MVT::i32, Expand);
}
- setOperationAction(ISD::SHL_PARTS, EVT::i32, Expand);
- setOperationAction(ISD::SRA_PARTS, EVT::i32, Expand);
- setOperationAction(ISD::SRL_PARTS, EVT::i32, Expand);
- setOperationAction(ISD::SRL, EVT::i64, Custom);
- setOperationAction(ISD::SRA, EVT::i64, Custom);
+ setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
+ setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
+ setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
+ setOperationAction(ISD::SRL, MVT::i64, Custom);
+ setOperationAction(ISD::SRA, MVT::i64, Custom);
// ARM does not have ROTL.
- setOperationAction(ISD::ROTL, EVT::i32, Expand);
- setOperationAction(ISD::CTTZ, EVT::i32, Expand);
- setOperationAction(ISD::CTPOP, EVT::i32, Expand);
+ setOperationAction(ISD::ROTL, MVT::i32, Expand);
+ setOperationAction(ISD::CTTZ, MVT::i32, Expand);
+ setOperationAction(ISD::CTPOP, MVT::i32, Expand);
if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
- setOperationAction(ISD::CTLZ, EVT::i32, Expand);
+ setOperationAction(ISD::CTLZ, MVT::i32, Expand);
// Only ARMv6 has BSWAP.
if (!Subtarget->hasV6Ops())
- setOperationAction(ISD::BSWAP, EVT::i32, Expand);
+ setOperationAction(ISD::BSWAP, MVT::i32, Expand);
// These are expanded into libcalls.
- setOperationAction(ISD::SDIV, EVT::i32, Expand);
- setOperationAction(ISD::UDIV, EVT::i32, Expand);
- setOperationAction(ISD::SREM, EVT::i32, Expand);
- setOperationAction(ISD::UREM, EVT::i32, Expand);
- setOperationAction(ISD::SDIVREM, EVT::i32, Expand);
- setOperationAction(ISD::UDIVREM, EVT::i32, Expand);
+ setOperationAction(ISD::SDIV, MVT::i32, Expand);
+ setOperationAction(ISD::UDIV, MVT::i32, Expand);
+ setOperationAction(ISD::SREM, MVT::i32, Expand);
+ setOperationAction(ISD::UREM, MVT::i32, Expand);
+ setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
+ setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
// Support label based line numbers.
- setOperationAction(ISD::DBG_STOPPOINT, EVT::Other, Expand);
- setOperationAction(ISD::DEBUG_LOC, EVT::Other, Expand);
+ setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
+ setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
- setOperationAction(ISD::GlobalAddress, EVT::i32, Custom);
- setOperationAction(ISD::ConstantPool, EVT::i32, Custom);
- setOperationAction(ISD::GLOBAL_OFFSET_TABLE, EVT::i32, Custom);
- setOperationAction(ISD::GlobalTLSAddress, EVT::i32, Custom);
+ setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
+ setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
+ setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
+ setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
// Use the default implementation.
- setOperationAction(ISD::VASTART, EVT::Other, Custom);
- setOperationAction(ISD::VAARG, EVT::Other, Expand);
- setOperationAction(ISD::VACOPY, EVT::Other, Expand);
- setOperationAction(ISD::VAEND, EVT::Other, Expand);
- setOperationAction(ISD::STACKSAVE, EVT::Other, Expand);
- setOperationAction(ISD::STACKRESTORE, EVT::Other, Expand);
+ setOperationAction(ISD::VASTART, MVT::Other, Custom);
+ setOperationAction(ISD::VAARG, MVT::Other, Expand);
+ setOperationAction(ISD::VACOPY, MVT::Other, Expand);
+ setOperationAction(ISD::VAEND, MVT::Other, Expand);
+ setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
+ setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
if (Subtarget->isThumb())
- setOperationAction(ISD::DYNAMIC_STACKALLOC, EVT::i32, Custom);
+ setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
else
- setOperationAction(ISD::DYNAMIC_STACKALLOC, EVT::i32, Expand);
- setOperationAction(ISD::MEMBARRIER, EVT::Other, Expand);
+ setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
+ setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
if (!Subtarget->hasV6Ops() && !Subtarget->isThumb2()) {
- setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i16, Expand);
- setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i8, Expand);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
}
- setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i1, Expand);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only())
// Turn f64->i64 into FMRRD, i64 -> f64 to FMDRR iff target supports vfp2.
- setOperationAction(ISD::BIT_CONVERT, EVT::i64, Custom);
+ setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
// We want to custom lower some of our intrinsics.
- setOperationAction(ISD::INTRINSIC_WO_CHAIN, EVT::Other, Custom);
- setOperationAction(ISD::INTRINSIC_W_CHAIN, EVT::Other, Custom);
- setOperationAction(ISD::INTRINSIC_VOID, EVT::Other, Custom);
-
- setOperationAction(ISD::SETCC, EVT::i32, Expand);
- setOperationAction(ISD::SETCC, EVT::f32, Expand);
- setOperationAction(ISD::SETCC, EVT::f64, Expand);
- setOperationAction(ISD::SELECT, EVT::i32, Expand);
- setOperationAction(ISD::SELECT, EVT::f32, Expand);
- setOperationAction(ISD::SELECT, EVT::f64, Expand);
- setOperationAction(ISD::SELECT_CC, EVT::i32, Custom);
- setOperationAction(ISD::SELECT_CC, EVT::f32, Custom);
- setOperationAction(ISD::SELECT_CC, EVT::f64, Custom);
-
- setOperationAction(ISD::BRCOND, EVT::Other, Expand);
- setOperationAction(ISD::BR_CC, EVT::i32, Custom);
- setOperationAction(ISD::BR_CC, EVT::f32, Custom);
- setOperationAction(ISD::BR_CC, EVT::f64, Custom);
- setOperationAction(ISD::BR_JT, EVT::Other, Custom);
+ setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
+ setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
+ setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
+
+ setOperationAction(ISD::SETCC, MVT::i32, Expand);
+ setOperationAction(ISD::SETCC, MVT::f32, Expand);
+ setOperationAction(ISD::SETCC, MVT::f64, Expand);
+ setOperationAction(ISD::SELECT, MVT::i32, Expand);
+ setOperationAction(ISD::SELECT, MVT::f32, Expand);
+ setOperationAction(ISD::SELECT, MVT::f64, Expand);
+ setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
+ setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
+ setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
+
+ setOperationAction(ISD::BRCOND, MVT::Other, Expand);
+ setOperationAction(ISD::BR_CC, MVT::i32, Custom);
+ setOperationAction(ISD::BR_CC, MVT::f32, Custom);
+ setOperationAction(ISD::BR_CC, MVT::f64, Custom);
+ setOperationAction(ISD::BR_JT, MVT::Other, Custom);
// We don't support sin/cos/fmod/copysign/pow
- setOperationAction(ISD::FSIN, EVT::f64, Expand);
- setOperationAction(ISD::FSIN, EVT::f32, Expand);
- setOperationAction(ISD::FCOS, EVT::f32, Expand);
- setOperationAction(ISD::FCOS, EVT::f64, Expand);
- setOperationAction(ISD::FREM, EVT::f64, Expand);
- setOperationAction(ISD::FREM, EVT::f32, Expand);
+ setOperationAction(ISD::FSIN, MVT::f64, Expand);
+ setOperationAction(ISD::FSIN, MVT::f32, Expand);
+ setOperationAction(ISD::FCOS, MVT::f32, Expand);
+ setOperationAction(ISD::FCOS, MVT::f64, Expand);
+ setOperationAction(ISD::FREM, MVT::f64, Expand);
+ setOperationAction(ISD::FREM, MVT::f32, Expand);
if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
- setOperationAction(ISD::FCOPYSIGN, EVT::f64, Custom);
- setOperationAction(ISD::FCOPYSIGN, EVT::f32, Custom);
+ setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
+ setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
}
- setOperationAction(ISD::FPOW, EVT::f64, Expand);
- setOperationAction(ISD::FPOW, EVT::f32, Expand);
+ setOperationAction(ISD::FPOW, MVT::f64, Expand);
+ setOperationAction(ISD::FPOW, MVT::f32, Expand);
// int <-> fp are custom expanded into bit_convert + ARMISD ops.
if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
- setOperationAction(ISD::SINT_TO_FP, EVT::i32, Custom);
- setOperationAction(ISD::UINT_TO_FP, EVT::i32, Custom);
- setOperationAction(ISD::FP_TO_UINT, EVT::i32, Custom);
- setOperationAction(ISD::FP_TO_SINT, EVT::i32, Custom);
+ setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
+ setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
+ setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
+ setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
}
// We have target-specific dag combine patterns for the following nodes:
CCState &State) {
if (!f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
return false;
- if (LocVT == EVT::v2f64 &&
+ if (LocVT == MVT::v2f64 &&
!f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
return false;
return true; // we handled it
CCState &State) {
if (!f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
return false;
- if (LocVT == EVT::v2f64 &&
+ if (LocVT == MVT::v2f64 &&
!f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
return false;
return true; // we handled it
CCState &State) {
if (!f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
return false;
- if (LocVT == EVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
+ if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
return false;
return true; // we handled it
}
SDValue Val;
if (VA.needsCustom()) {
// Handle f64 or half of a v2f64.
- SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), EVT::i32,
+ SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
InFlag);
Chain = Lo.getValue(1);
InFlag = Lo.getValue(2);
VA = RVLocs[++i]; // skip ahead to next loc
- SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), EVT::i32,
+ SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
InFlag);
Chain = Hi.getValue(1);
InFlag = Hi.getValue(2);
- Val = DAG.getNode(ARMISD::FMDRR, dl, EVT::f64, Lo, Hi);
+ Val = DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi);
- if (VA.getLocVT() == EVT::v2f64) {
- SDValue Vec = DAG.getNode(ISD::UNDEF, dl, EVT::v2f64);
- Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, EVT::v2f64, Vec, Val,
- DAG.getConstant(0, EVT::i32));
+ if (VA.getLocVT() == MVT::v2f64) {
+ SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
+ Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
+ DAG.getConstant(0, MVT::i32));
VA = RVLocs[++i]; // skip ahead to next loc
- Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), EVT::i32, InFlag);
+ Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
Chain = Lo.getValue(1);
InFlag = Lo.getValue(2);
VA = RVLocs[++i]; // skip ahead to next loc
- Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), EVT::i32, InFlag);
+ Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
Chain = Hi.getValue(1);
InFlag = Hi.getValue(2);
- Val = DAG.getNode(ARMISD::FMDRR, dl, EVT::f64, Lo, Hi);
- Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, EVT::v2f64, Vec, Val,
- DAG.getConstant(1, EVT::i32));
+ Val = DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi);
+ Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
+ DAG.getConstant(1, MVT::i32));
}
} else {
Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
DebugLoc dl) {
- SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), EVT::i32);
+ SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
/*AlwaysInline=*/false, NULL, 0, NULL, 0);
}
ISD::ArgFlagsTy Flags) {
SDValue fmrrd = DAG.getNode(ARMISD::FMRRD, dl,
- DAG.getVTList(EVT::i32, EVT::i32), Arg);
+ DAG.getVTList(MVT::i32, MVT::i32), Arg);
RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
if (NextVA.isRegLoc())
// These operations are automatically eliminated by the prolog/epilog pass
Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
- SDValue StackPtr = DAG.getRegister(ARM::SP, EVT::i32);
+ SDValue StackPtr = DAG.getRegister(ARM::SP, MVT::i32);
RegsToPassVector RegsToPass;
SmallVector<SDValue, 8> MemOpChains;
// f64 and v2f64 might be passed in i32 pairs and must be split into pieces
if (VA.needsCustom()) {
- if (VA.getLocVT() == EVT::v2f64) {
- SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::f64, Arg,
- DAG.getConstant(0, EVT::i32));
- SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::f64, Arg,
- DAG.getConstant(1, EVT::i32));
+ if (VA.getLocVT() == MVT::v2f64) {
+ SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
+ DAG.getConstant(0, MVT::i32));
+ SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
+ DAG.getConstant(1, MVT::i32));
PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
}
if (!MemOpChains.empty())
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&MemOpChains[0], MemOpChains.size());
// Build a sequence of copy-to-reg nodes chained together with token chain
ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
ARMCP::CPStub, 4);
SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
- CPAddr = DAG.getNode(ARMISD::Wrapper, dl, EVT::i32, CPAddr);
+ CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
Callee = DAG.getLoad(getPointerTy(), dl,
DAG.getEntryNode(), CPAddr, NULL, 0);
- SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, EVT::i32);
+ SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
getPointerTy(), Callee, PICLabel);
} else
ARMConstantPoolValue *CPV = new ARMConstantPoolValue(Sym, ARMPCLabelIndex,
ARMCP::CPStub, 4);
SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
- CPAddr = DAG.getNode(ARMISD::Wrapper, dl, EVT::i32, CPAddr);
+ CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
Callee = DAG.getLoad(getPointerTy(), dl,
DAG.getEntryNode(), CPAddr, NULL, 0);
- SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, EVT::i32);
+ SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
getPointerTy(), Callee, PICLabel);
} else
}
if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb1Only()) {
// implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK
- Chain = DAG.getCopyToReg(Chain, dl, ARM::LR, DAG.getUNDEF(EVT::i32),InFlag);
+ Chain = DAG.getCopyToReg(Chain, dl, ARM::LR, DAG.getUNDEF(MVT::i32),InFlag);
InFlag = Chain.getValue(1);
}
if (InFlag.getNode())
Ops.push_back(InFlag);
// Returns a chain and a flag for retval copy to use.
- Chain = DAG.getNode(CallOpc, dl, DAG.getVTList(EVT::Other, EVT::Flag),
+ Chain = DAG.getNode(CallOpc, dl, DAG.getVTList(MVT::Other, MVT::Flag),
&Ops[0], Ops.size());
InFlag = Chain.getValue(1);
}
if (VA.needsCustom()) {
- if (VA.getLocVT() == EVT::v2f64) {
+ if (VA.getLocVT() == MVT::v2f64) {
// Extract the first half and return it in two registers.
- SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::f64, Arg,
- DAG.getConstant(0, EVT::i32));
+ SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
+ DAG.getConstant(0, MVT::i32));
SDValue HalfGPRs = DAG.getNode(ARMISD::FMRRD, dl,
- DAG.getVTList(EVT::i32, EVT::i32), Half);
+ DAG.getVTList(MVT::i32, MVT::i32), Half);
Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
Flag = Chain.getValue(1);
VA = RVLocs[++i]; // skip ahead to next loc
// Extract the 2nd half and fall through to handle it as an f64 value.
- Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::f64, Arg,
- DAG.getConstant(1, EVT::i32));
+ Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
+ DAG.getConstant(1, MVT::i32));
}
// Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
// available.
SDValue fmrrd = DAG.getNode(ARMISD::FMRRD, dl,
- DAG.getVTList(EVT::i32, EVT::i32), &Arg, 1);
+ DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
Flag = Chain.getValue(1);
VA = RVLocs[++i]; // skip ahead to next loc
SDValue result;
if (Flag.getNode())
- result = DAG.getNode(ARMISD::RET_FLAG, dl, EVT::Other, Chain, Flag);
+ result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
else // Return Void
- result = DAG.getNode(ARMISD::RET_FLAG, dl, EVT::Other, Chain);
+ result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
return result;
}
else
Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
CP->getAlignment());
- return DAG.getNode(ARMISD::Wrapper, dl, EVT::i32, Res);
+ return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
}
// Lower ISD::GlobalTLSAddress using the "general dynamic" model
new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
PCAdj, "tlsgd", true);
SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
- Argument = DAG.getNode(ARMISD::Wrapper, dl, EVT::i32, Argument);
+ Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument, NULL, 0);
SDValue Chain = Argument.getValue(1);
- SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, EVT::i32);
+ SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
// call __tls_get_addr.
new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
PCAdj, "gottpoff", true);
Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
- Offset = DAG.getNode(ARMISD::Wrapper, dl, EVT::i32, Offset);
+ Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
Chain = Offset.getValue(1);
- SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, EVT::i32);
+ SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
ARMConstantPoolValue *CPV =
new ARMConstantPoolValue(GV, ARMCP::CPValue, "tpoff");
Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
- Offset = DAG.getNode(ARMISD::Wrapper, dl, EVT::i32, Offset);
+ Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
}
ARMConstantPoolValue *CPV =
new ARMConstantPoolValue(GV, ARMCP::CPValue, UseGOTOFF ? "GOTOFF":"GOT");
SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
- CPAddr = DAG.getNode(ARMISD::Wrapper, dl, EVT::i32, CPAddr);
+ CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
CPAddr, NULL, 0);
SDValue Chain = Result.getValue(1);
return Result;
} else {
SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
- CPAddr = DAG.getNode(ARMISD::Wrapper, dl, EVT::i32, CPAddr);
+ CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
}
}
Kind, PCAdj);
CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
}
- CPAddr = DAG.getNode(ARMISD::Wrapper, dl, EVT::i32, CPAddr);
+ CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
SDValue Chain = Result.getValue(1);
if (RelocM == Reloc::PIC_) {
- SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, EVT::i32);
+ SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
}
if (IsIndirect)
ARMPCLabelIndex,
ARMCP::CPValue, PCAdj);
SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
- CPAddr = DAG.getNode(ARMISD::Wrapper, dl, EVT::i32, CPAddr);
+ CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
- SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, EVT::i32);
+ SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
}
Ops.push_back(Node->getOperand(2));
for (unsigned N = 0; N < NumVecs; ++N)
Ops.push_back(Node->getOperand(N + 3));
- return DAG.getNode(Opcode, dl, EVT::Other, Ops.data(), Ops.size());
+ return DAG.getNode(Opcode, dl, MVT::Other, Ops.data(), Ops.size());
}
SDValue
ARMConstantPoolValue *CPV =
new ARMConstantPoolValue(LSDAName.c_str(), ARMPCLabelIndex, Kind, PCAdj);
CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
- CPAddr = DAG.getNode(ARMISD::Wrapper, dl, EVT::i32, CPAddr);
+ CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
SDValue Result =
DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
SDValue Chain = Result.getValue(1);
if (RelocM == Reloc::PIC_) {
- SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, EVT::i32);
+ SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
}
return Result;
}
case Intrinsic::eh_sjlj_setjmp:
- return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, EVT::i32, Op.getOperand(1));
+ return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(1));
}
}
Size = DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, VT), Size);
}
- SDVTList VTList = DAG.getVTList(VT, EVT::Other);
+ SDVTList VTList = DAG.getVTList(VT, MVT::Other);
SDValue Ops1[] = { Chain, Size, Align };
SDValue Res = DAG.getNode(ARMISD::DYN_ALLOC, dl, VTList, Ops1, 3);
Chain = Res.getValue(1);
// Transform the arguments stored in physical registers into virtual ones.
unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
- SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, EVT::i32);
+ SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
SDValue ArgValue2;
if (NextVA.isMemLoc()) {
@@ -1505,13 +1505,13 @@ ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
// Create load node to retrieve arguments from the stack.
SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
- ArgValue2 = DAG.getLoad(EVT::i32, dl, Root, FIN, NULL, 0);
+ ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN, NULL, 0);
} else {
Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
- ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, EVT::i32);
+ ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
}
- return DAG.getNode(ARMISD::FMDRR, dl, EVT::f64, ArgValue, ArgValue2);
+ return DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, ArgValue, ArgValue2);
}
SDValue
if (VA.needsCustom()) {
// f64 and vector types are split up into multiple registers or
// combinations of registers and stack slots.
- RegVT = EVT::i32;
+ RegVT = MVT::i32;
- if (VA.getLocVT() == EVT::v2f64) {
+ if (VA.getLocVT() == MVT::v2f64) {
SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
Chain, DAG, dl);
VA = ArgLocs[++i]; // skip ahead to next loc
SDValue ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
Chain, DAG, dl);
- ArgValue = DAG.getNode(ISD::UNDEF, dl, EVT::v2f64);
- ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, EVT::v2f64,
+ ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
+ ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
- ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, EVT::v2f64,
+ ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
} else
ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
} else {
TargetRegisterClass *RC;
- if (RegVT == EVT::f32)
+ if (RegVT == MVT::f32)
RC = ARM::SPRRegisterClass;
- else if (RegVT == EVT::f64)
+ else if (RegVT == MVT::f64)
RC = ARM::DPRRegisterClass;
- else if (RegVT == EVT::v2f64)
+ else if (RegVT == MVT::v2f64)
RC = ARM::QPRRegisterClass;
- else if (RegVT == EVT::i32)
+ else if (RegVT == MVT::i32)
RC = (AFI->isThumb1OnlyFunction() ?
ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
else
// sanity check
assert(VA.isMemLoc());
- assert(VA.getValVT() != EVT::i64 && "i64 should already be lowered");
+ assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset());
RC = ARM::GPRRegisterClass;
unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC);
- SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, EVT::i32);
+ SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
MemOps.push_back(Store);
FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
DAG.getConstant(4, getPointerTy()));
}
if (!MemOps.empty())
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&MemOps[0], MemOps.size());
} else
// This will point to the next argument passed via stack.
case ISD::SETGE:
if (isLegalCmpImmediate(C-1, isThumb1Only)) {
CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
- RHS = DAG.getConstant(C-1, EVT::i32);
+ RHS = DAG.getConstant(C-1, MVT::i32);
}
break;
case ISD::SETULT:
case ISD::SETUGE:
if (C > 0 && isLegalCmpImmediate(C-1, isThumb1Only)) {
CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
- RHS = DAG.getConstant(C-1, EVT::i32);
+ RHS = DAG.getConstant(C-1, MVT::i32);
}
break;
case ISD::SETLE:
case ISD::SETGT:
if (isLegalCmpImmediate(C+1, isThumb1Only)) {
CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
- RHS = DAG.getConstant(C+1, EVT::i32);
+ RHS = DAG.getConstant(C+1, MVT::i32);
}
break;
case ISD::SETULE:
case ISD::SETUGT:
if (C < 0xffffffff && isLegalCmpImmediate(C+1, isThumb1Only)) {
CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
- RHS = DAG.getConstant(C+1, EVT::i32);
+ RHS = DAG.getConstant(C+1, MVT::i32);
}
break;
}
CompareType = ARMISD::CMPZ;
break;
}
- ARMCC = DAG.getConstant(CondCode, EVT::i32);
- return DAG.getNode(CompareType, dl, EVT::Flag, LHS, RHS);
+ ARMCC = DAG.getConstant(CondCode, MVT::i32);
+ return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS);
}
/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
DebugLoc dl) {
SDValue Cmp;
if (!isFloatingPointZero(RHS))
- Cmp = DAG.getNode(ARMISD::CMPFP, dl, EVT::Flag, LHS, RHS);
+ Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS);
else
- Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, EVT::Flag, LHS);
- return DAG.getNode(ARMISD::FMSTAT, dl, EVT::Flag, Cmp);
+ Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Flag, LHS);
+ return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Flag, Cmp);
}
static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
SDValue FalseVal = Op.getOperand(3);
DebugLoc dl = Op.getDebugLoc();
- if (LHS.getValueType() == EVT::i32) {
+ if (LHS.getValueType() == MVT::i32) {
SDValue ARMCC;
- SDValue CCR = DAG.getRegister(ARM::CPSR, EVT::i32);
+ SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb1Only(), dl);
return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC, CCR,Cmp);
}
if (FPCCToARMCC(CC, CondCode, CondCode2))
std::swap(TrueVal, FalseVal);
- SDValue ARMCC = DAG.getConstant(CondCode, EVT::i32);
- SDValue CCR = DAG.getRegister(ARM::CPSR, EVT::i32);
+ SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
+ SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
ARMCC, CCR, Cmp);
if (CondCode2 != ARMCC::AL) {
- SDValue ARMCC2 = DAG.getConstant(CondCode2, EVT::i32);
+ SDValue ARMCC2 = DAG.getConstant(CondCode2, MVT::i32);
// FIXME: Needs another CMP because flag can have but one use.
SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
Result = DAG.getNode(ARMISD::CMOV, dl, VT,
SDValue Dest = Op.getOperand(4);
DebugLoc dl = Op.getDebugLoc();
- if (LHS.getValueType() == EVT::i32) {
+ if (LHS.getValueType() == MVT::i32) {
SDValue ARMCC;
- SDValue CCR = DAG.getRegister(ARM::CPSR, EVT::i32);
+ SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb1Only(), dl);
- return DAG.getNode(ARMISD::BRCOND, dl, EVT::Other,
+ return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
Chain, Dest, ARMCC, CCR,Cmp);
}
- assert(LHS.getValueType() == EVT::f32 || LHS.getValueType() == EVT::f64);
+ assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
ARMCC::CondCodes CondCode, CondCode2;
if (FPCCToARMCC(CC, CondCode, CondCode2))
// Swap the LHS/RHS of the comparison if needed.
std::swap(LHS, RHS);
SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
- SDValue ARMCC = DAG.getConstant(CondCode, EVT::i32);
- SDValue CCR = DAG.getRegister(ARM::CPSR, EVT::i32);
- SDVTList VTList = DAG.getVTList(EVT::Other, EVT::Flag);
+ SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
+ SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
+ SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
SDValue Ops[] = { Chain, Dest, ARMCC, CCR, Cmp };
SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
if (CondCode2 != ARMCC::AL) {
- ARMCC = DAG.getConstant(CondCode2, EVT::i32);
+ ARMCC = DAG.getConstant(CondCode2, MVT::i32);
SDValue Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) };
Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
}
ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
- Table = DAG.getNode(ARMISD::WrapperJT, dl, EVT::i32, JTI, UId);
+ Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
if (Subtarget->isThumb2()) {
// which does another jump to the destination. This also makes it easier
// to translate it to TBB / TBH later.
// FIXME: This might not work if the function is extremely large.
- return DAG.getNode(ARMISD::BR2_JT, dl, EVT::Other, Chain,
+ return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
Addr, Op.getOperand(2), JTI, UId);
}
if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
- Addr = DAG.getLoad((EVT)EVT::i32, dl, Chain, Addr, NULL, 0);
+ Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr, NULL, 0);
Chain = Addr.getValue(1);
Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
- return DAG.getNode(ARMISD::BR_JT, dl, EVT::Other, Chain, Addr, JTI, UId);
+ return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
} else {
Addr = DAG.getLoad(PTy, dl, Chain, Addr, NULL, 0);
Chain = Addr.getValue(1);
- return DAG.getNode(ARMISD::BR_JT, dl, EVT::Other, Chain, Addr, JTI, UId);
+ return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
}
}
DebugLoc dl = Op.getDebugLoc();
unsigned Opc =
Op.getOpcode() == ISD::FP_TO_SINT ? ARMISD::FTOSI : ARMISD::FTOUI;
- Op = DAG.getNode(Opc, dl, EVT::f32, Op.getOperand(0));
- return DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, Op);
+ Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
+ return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
}
static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
unsigned Opc =
Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF;
- Op = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, Op.getOperand(0));
+ Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0));
return DAG.getNode(Opc, dl, VT, Op);
}
EVT SrcVT = Tmp1.getValueType();
SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0);
SDValue Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG, dl);
- SDValue ARMCC = DAG.getConstant(ARMCC::LT, EVT::i32);
- SDValue CCR = DAG.getRegister(ARM::CPSR, EVT::i32);
+ SDValue ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32);
+ SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp);
}
unsigned BytesLeft = SizeVal & 3;
unsigned NumMemOps = SizeVal >> 2;
unsigned EmittedNumMemOps = 0;
- EVT VT = EVT::i32;
+ EVT VT = MVT::i32;
unsigned VTSize = 4;
unsigned i = 0;
const unsigned MAX_LOADS_IN_LDM = 6;
for (i = 0;
i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
Loads[i] = DAG.getLoad(VT, dl, Chain,
- DAG.getNode(ISD::ADD, dl, EVT::i32, Src,
- DAG.getConstant(SrcOff, EVT::i32)),
+ DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
+ DAG.getConstant(SrcOff, MVT::i32)),
SrcSV, SrcSVOff + SrcOff);
TFOps[i] = Loads[i].getValue(1);
SrcOff += VTSize;
}
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &TFOps[0], i);
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
for (i = 0;
i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
- DAG.getNode(ISD::ADD, dl, EVT::i32, Dst,
- DAG.getConstant(DstOff, EVT::i32)),
+ DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
+ DAG.getConstant(DstOff, MVT::i32)),
DstSV, DstSVOff + DstOff);
DstOff += VTSize;
}
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &TFOps[0], i);
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
EmittedNumMemOps += i;
}
i = 0;
while (BytesLeft) {
if (BytesLeft >= 2) {
- VT = EVT::i16;
+ VT = MVT::i16;
VTSize = 2;
} else {
- VT = EVT::i8;
+ VT = MVT::i8;
VTSize = 1;
}
Loads[i] = DAG.getLoad(VT, dl, Chain,
- DAG.getNode(ISD::ADD, dl, EVT::i32, Src,
- DAG.getConstant(SrcOff, EVT::i32)),
+ DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
+ DAG.getConstant(SrcOff, MVT::i32)),
SrcSV, SrcSVOff + SrcOff);
TFOps[i] = Loads[i].getValue(1);
++i;
SrcOff += VTSize;
BytesLeft -= VTSize;
}
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &TFOps[0], i);
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
i = 0;
BytesLeft = BytesLeftSave;
while (BytesLeft) {
if (BytesLeft >= 2) {
- VT = EVT::i16;
+ VT = MVT::i16;
VTSize = 2;
} else {
- VT = EVT::i8;
+ VT = MVT::i8;
VTSize = 1;
}
TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
- DAG.getNode(ISD::ADD, dl, EVT::i32, Dst,
- DAG.getConstant(DstOff, EVT::i32)),
+ DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
+ DAG.getConstant(DstOff, MVT::i32)),
DstSV, DstSVOff + DstOff);
++i;
DstOff += VTSize;
BytesLeft -= VTSize;
}
- return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &TFOps[0], i);
+ return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
}
static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
SDValue Op = N->getOperand(0);
DebugLoc dl = N->getDebugLoc();
- if (N->getValueType(0) == EVT::f64) {
+ if (N->getValueType(0) == MVT::f64) {
// Turn i64->f64 into FMDRR.
- SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32, Op,
- DAG.getConstant(0, EVT::i32));
- SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32, Op,
- DAG.getConstant(1, EVT::i32));
- return DAG.getNode(ARMISD::FMDRR, dl, EVT::f64, Lo, Hi);
+ SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
+ DAG.getConstant(0, MVT::i32));
+ SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
+ DAG.getConstant(1, MVT::i32));
+ return DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi);
}
// Turn f64->i64 into FMRRD.
SDValue Cvt = DAG.getNode(ARMISD::FMRRD, dl,
- DAG.getVTList(EVT::i32, EVT::i32), &Op, 1);
+ DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
// Merge the pieces into a single i64 value.
- return DAG.getNode(ISD::BUILD_PAIR, dl, EVT::i64, Cvt, Cvt.getValue(1));
+ return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
}
/// getZeroVector - Returns a vector of specified type with all zero elements.
// the future, always build zero vectors as <4 x i32> or <2 x i32> bitcasted
// to their dest type. This ensures they get CSE'd.
SDValue Vec;
- SDValue Cst = DAG.getTargetConstant(0, EVT::i32);
+ SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
if (VT.getSizeInBits() == 64)
- Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v2i32, Cst, Cst);
+ Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
else
- Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32, Cst, Cst, Cst, Cst);
+ Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
}
// Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
// type. This ensures they get CSE'd.
SDValue Vec;
- SDValue Cst = DAG.getTargetConstant(~0U, EVT::i32);
+ SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
if (VT.getSizeInBits() == 64)
- Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v2i32, Cst, Cst);
+ Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
else
- Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32, Cst, Cst, Cst, Cst);
+ Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
}
// Left shifts translate directly to the vshiftu intrinsic.
if (N->getOpcode() == ISD::SHL)
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
- DAG.getConstant(Intrinsic::arm_neon_vshiftu, EVT::i32),
+ DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
N->getOperand(0), N->getOperand(1));
assert((N->getOpcode() == ISD::SRA ||
Intrinsic::arm_neon_vshifts :
Intrinsic::arm_neon_vshiftu);
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
- DAG.getConstant(vshiftInt, EVT::i32),
+ DAG.getConstant(vshiftInt, MVT::i32),
N->getOperand(0), NegatedCount);
}
- assert(VT == EVT::i64 &&
+ assert(VT == MVT::i64 &&
(N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
"Unknown shift to lower!");
if (ST->isThumb1Only()) return SDValue();
// Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
- SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32, N->getOperand(0),
- DAG.getConstant(0, EVT::i32));
- SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32, N->getOperand(0),
- DAG.getConstant(1, EVT::i32));
+ SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
+ DAG.getConstant(0, MVT::i32));
+ SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
+ DAG.getConstant(1, MVT::i32));
// First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
// captures the result into a carry flag.
unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
- Hi = DAG.getNode(Opc, dl, DAG.getVTList(EVT::i32, EVT::Flag), &Hi, 1);
+ Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
// The low part is an ARMISD::RRX operand, which shifts the carry in.
- Lo = DAG.getNode(ARMISD::RRX, dl, EVT::i32, Lo, Hi.getValue(1));
+ Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
// Merge the pieces into a single i64 value.
- return DAG.getNode(ISD::BUILD_PAIR, dl, EVT::i64, Lo, Hi);
+ return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
}
static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
case 8:
// Any 1-byte value is OK.
assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
- return DAG.getTargetConstant(SplatBits, EVT::i8);
+ return DAG.getTargetConstant(SplatBits, MVT::i8);
case 16:
// NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
if ((SplatBits & ~0xff) == 0 ||
(SplatBits & ~0xff00) == 0)
- return DAG.getTargetConstant(SplatBits, EVT::i16);
+ return DAG.getTargetConstant(SplatBits, MVT::i16);
break;
case 32:
(SplatBits & ~0xff00) == 0 ||
(SplatBits & ~0xff0000) == 0 ||
(SplatBits & ~0xff000000) == 0)
- return DAG.getTargetConstant(SplatBits, EVT::i32);
+ return DAG.getTargetConstant(SplatBits, MVT::i32);
if ((SplatBits & ~0xffff) == 0 &&
((SplatBits | SplatUndef) & 0xff) == 0xff)
- return DAG.getTargetConstant(SplatBits | 0xff, EVT::i32);
+ return DAG.getTargetConstant(SplatBits | 0xff, MVT::i32);
if ((SplatBits & ~0xffffff) == 0 &&
((SplatBits | SplatUndef) & 0xffff) == 0xffff)
- return DAG.getTargetConstant(SplatBits | 0xffff, EVT::i32);
+ return DAG.getTargetConstant(SplatBits | 0xffff, MVT::i32);
// Note: there are a few 32-bit splat values (specifically: 00ffff00,
// ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
return SDValue();
BitMask <<= 8;
}
- return DAG.getTargetConstant(Val, EVT::i64);
+ return DAG.getTargetConstant(Val, MVT::i64);
}
default:
@@ -2364,19 +2364,19 @@ static SDValue BuildSplat(SDValue Val, EVT VT, SelectionDAG &DAG, DebugLoc dl) {
EVT CanonicalVT;
if (VT.is64BitVector()) {
switch (Val.getValueType().getSizeInBits()) {
- case 8: CanonicalVT = EVT::v8i8; break;
- case 16: CanonicalVT = EVT::v4i16; break;
- case 32: CanonicalVT = EVT::v2i32; break;
- case 64: CanonicalVT = EVT::v1i64; break;
+ case 8: CanonicalVT = MVT::v8i8; break;
+ case 16: CanonicalVT = MVT::v4i16; break;
+ case 32: CanonicalVT = MVT::v2i32; break;
+ case 64: CanonicalVT = MVT::v1i64; break;
default: llvm_unreachable("unexpected splat element type"); break;
}
} else {
assert(VT.is128BitVector() && "unknown splat vector size");
switch (Val.getValueType().getSizeInBits()) {
- case 8: CanonicalVT = EVT::v16i8; break;
- case 16: CanonicalVT = EVT::v8i16; break;
- case 32: CanonicalVT = EVT::v4i32; break;
- case 64: CanonicalVT = EVT::v2i64; break;
+ case 8: CanonicalVT = MVT::v16i8; break;
+ case 16: CanonicalVT = MVT::v8i16; break;
+ case 32: CanonicalVT = MVT::v4i32; break;
+ case 64: CanonicalVT = MVT::v2i64; break;
default: llvm_unreachable("unexpected splat element type"); break;
}
}
static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
EVT VT = Op.getValueType();
DebugLoc dl = Op.getDebugLoc();
- assert((VT == EVT::i8 || VT == EVT::i16) &&
+ assert((VT == MVT::i8 || VT == MVT::i16) &&
"unexpected type for custom-lowering vector extract");
SDValue Vec = Op.getOperand(0);
SDValue Lane = Op.getOperand(1);
- Op = DAG.getNode(ARMISD::VGETLANEu, dl, EVT::i32, Vec, Lane);
- Op = DAG.getNode(ISD::AssertZext, dl, EVT::i32, Op, DAG.getValueType(VT));
+ Op = DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
+ Op = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Op, DAG.getValueType(VT));
return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
}
assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
"unexpected CONCAT_VECTORS");
DebugLoc dl = Op.getDebugLoc();
- SDValue Val = DAG.getUNDEF(EVT::v2f64);
+ SDValue Val = DAG.getUNDEF(MVT::v2f64);
SDValue Op0 = Op.getOperand(0);
SDValue Op1 = Op.getOperand(1);
if (Op0.getOpcode() != ISD::UNDEF)
- Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, EVT::v2f64, Val,
- DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f64, Op0),
+ Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
+ DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op0),
DAG.getIntPtrConstant(0));
if (Op1.getOpcode() != ISD::UNDEF)
- Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, EVT::v2f64, Val,
- DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f64, Op1),
+ Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
+ DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op1),
DAG.getIntPtrConstant(1));
return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Val);
}
}
return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
- N->getOperand(1), DAG.getConstant(Cnt, EVT::i32));
+ N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
}
case Intrinsic::arm_neon_vshiftins: {
return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
N->getOperand(1), N->getOperand(2),
- DAG.getConstant(Cnt, EVT::i32));
+ DAG.getConstant(Cnt, MVT::i32));
}
case Intrinsic::arm_neon_vqrshifts:
case ISD::SHL:
if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
- DAG.getConstant(Cnt, EVT::i32));
+ DAG.getConstant(Cnt, MVT::i32));
break;
case ISD::SRA:
unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
ARMISD::VSHRs : ARMISD::VSHRu);
return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
- DAG.getConstant(Cnt, EVT::i32));
+ DAG.getConstant(Cnt, MVT::i32));
}
}
return SDValue();
EVT EltVT = N0.getValueType();
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
- if (VT == EVT::i32 &&
- (EltVT == EVT::i8 || EltVT == EVT::i16) &&
+ if (VT == MVT::i32 &&
+ (EltVT == MVT::i8 || EltVT == MVT::i16) &&
TLI.isTypeLegal(Vec.getValueType())) {
unsigned Opc = 0;
return false;
unsigned Scale = 1;
- switch (VT.getSimpleVT()) {
+ switch (VT.getSimpleVT().SimpleTy) {
default: return false;
- case EVT::i1:
- case EVT::i8:
+ case MVT::i1:
+ case MVT::i8:
// Scale == 1;
break;
- case EVT::i16:
+ case MVT::i16:
// Scale == 2;
Scale = 2;
break;
- case EVT::i32:
+ case MVT::i32:
// Scale == 4;
Scale = 4;
break;
if (V < 0)
V = - V;
- switch (VT.getSimpleVT()) {
+ switch (VT.getSimpleVT().SimpleTy) {
default: return false;
- case EVT::i1:
- case EVT::i8:
- case EVT::i32:
+ case MVT::i1:
+ case MVT::i8:
+ case MVT::i32:
// +- imm12
return V == (V & ((1LL << 12) - 1));
- case EVT::i16:
+ case MVT::i16:
// +- imm8
return V == (V & ((1LL << 8) - 1));
- case EVT::f32:
- case EVT::f64:
+ case MVT::f32:
+ case MVT::f64:
if (!Subtarget->hasVFP2())
return false;
if ((V & 3) != 0)
return false;
int Scale = AM.Scale;
- switch (VT.getSimpleVT()) {
+ switch (VT.getSimpleVT().SimpleTy) {
default: return false;
- case EVT::i1:
- case EVT::i8:
- case EVT::i32:
- case EVT::i64:
+ case MVT::i1:
+ case MVT::i8:
+ case MVT::i32:
+ case MVT::i64:
// This assumes i64 is legalized to a pair of i32. If not (i.e.
// ldrd / strd are used, then its address mode is same as i16.
// r + r
return true;
// r + r << imm
return isPowerOf2_32(Scale & ~1);
- case EVT::i16:
+ case MVT::i16:
// r + r
if (((unsigned)AM.HasBaseReg + Scale) <= 2)
return true;
return false;
- case EVT::isVoid:
+ case MVT::isVoid:
// Note, we allow "void" uses (basically, uses that aren't loads or
// stores), because arm allows folding a scale into many arithmetic
// operations. This should be made more precise and revisited later.
if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
return false;
- if (VT == EVT::i16 || ((VT == EVT::i8 || VT == EVT::i1) && isSEXTLoad)) {
+ if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
// AddressingMode 3
Base = Ptr->getOperand(0);
if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
isInc = (Ptr->getOpcode() == ISD::ADD);
Offset = Ptr->getOperand(1);
return true;
- } else if (VT == EVT::i32 || VT == EVT::i8 || VT == EVT::i1) {
+ } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
// AddressingMode 2
if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
int RHSC = (int)RHS->getZExtValue();
@@ -3420,9 +3420,9 @@ ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
case 'r':
return std::make_pair(0U, ARM::GPRRegisterClass);
case 'w':
- if (VT == EVT::f32)
+ if (VT == MVT::f32)
return std::make_pair(0U, ARM::SPRRegisterClass);
- if (VT == EVT::f64)
+ if (VT == MVT::f64)
return std::make_pair(0U, ARM::DPRRegisterClass);
break;
}
ARM::R8, ARM::R9, ARM::R10, ARM::R11,
ARM::R12, ARM::LR, 0);
case 'w':
- if (VT == EVT::f32)
+ if (VT == MVT::f32)
return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
ARM::S4, ARM::S5, ARM::S6, ARM::S7,
ARM::S8, ARM::S9, ARM::S10, ARM::S11,
ARM::S20,ARM::S21,ARM::S22,ARM::S23,
ARM::S24,ARM::S25,ARM::S26,ARM::S27,
ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
- if (VT == EVT::f64)
+ if (VT == MVT::f64)
return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
ARM::D4, ARM::D5, ARM::D6, ARM::D7,
ARM::D8, ARM::D9, ARM::D10,ARM::D11,
index 4a2ce4be78cf616fb8da54519b2463981a9eed7e..b197082b6b5038dfa79cac47c94839d061bb752b 100644 (file)
// so_imm_neg_XFORM - Return a so_imm value packed into the format described for
// so_imm_neg def below.
def so_imm_neg_XFORM : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(-(int)N->getZExtValue(), EVT::i32);
+ return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
}]>;
// so_imm_not_XFORM - Return a so_imm value packed into the format described for
// so_imm_not def below.
def so_imm_not_XFORM : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(~(int)N->getZExtValue(), EVT::i32);
+ return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
}]>;
// rot_imm predicate - True if the 32-bit immediate is equal to 8, 16, or 24.
def so_imm2part_1 : SDNodeXForm<imm, [{
unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue());
- return CurDAG->getTargetConstant(V, EVT::i32);
+ return CurDAG->getTargetConstant(V, MVT::i32);
}]>;
def so_imm2part_2 : SDNodeXForm<imm, [{
unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue());
- return CurDAG->getTargetConstant(V, EVT::i32);
+ return CurDAG->getTargetConstant(V, MVT::i32);
}]>;
index 53283e84ead47e35ffe6d00f8e3f58d8864dbf7c..32baec5f0739c144a0b4461307f30caffeb29465 100644 (file)
// Extract D sub-registers of Q registers.
// (arm_dsubreg_0 is 5; arm_dsubreg_1 is 6)
def DSubReg_i8_reg : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(5 + N->getZExtValue() / 8, EVT::i32);
+ return CurDAG->getTargetConstant(5 + N->getZExtValue() / 8, MVT::i32);
}]>;
def DSubReg_i16_reg : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(5 + N->getZExtValue() / 4, EVT::i32);
+ return CurDAG->getTargetConstant(5 + N->getZExtValue() / 4, MVT::i32);
}]>;
def DSubReg_i32_reg : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(5 + N->getZExtValue() / 2, EVT::i32);
+ return CurDAG->getTargetConstant(5 + N->getZExtValue() / 2, MVT::i32);
}]>;
def DSubReg_f64_reg : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(5 + N->getZExtValue(), EVT::i32);
+ return CurDAG->getTargetConstant(5 + N->getZExtValue(), MVT::i32);
}]>;
// Extract S sub-registers of Q registers.
// (arm_ssubreg_0 is 1; arm_ssubreg_1 is 2; etc.)
def SSubReg_f32_reg : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(1 + N->getZExtValue(), EVT::i32);
+ return CurDAG->getTargetConstant(1 + N->getZExtValue(), MVT::i32);
}]>;
// Translate lane numbers from Q registers to D subregs.
def SubReg_i8_lane : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(N->getZExtValue() & 7, EVT::i32);
+ return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
}]>;
def SubReg_i16_lane : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(N->getZExtValue() & 3, EVT::i32);
+ return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
}]>;
def SubReg_i32_lane : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(N->getZExtValue() & 1, EVT::i32);
+ return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
}]>;
//===----------------------------------------------------------------------===//
def SHUFFLE_get_splat_lane : SDNodeXForm<vector_shuffle, [{
ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
- return CurDAG->getTargetConstant(SVOp->getSplatIndex(), EVT::i32);
+ return CurDAG->getTargetConstant(SVOp->getSplatIndex(), MVT::i32);
}]>;
def splat_lane : PatFrag<(ops node:$lhs, node:$rhs),
index 7d27af2df1aee4eef06cd1c564021b5422a8d96c..25dbddf0e235a749d1cb0684cf7cc97eaa943519 100644 (file)
[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
def imm_neg_XFORM : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(-(int)N->getZExtValue(), EVT::i32);
+ return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
}]>;
def imm_comp_XFORM : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), EVT::i32);
+ return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
}]>;
def thumb_immshifted_val : SDNodeXForm<imm, [{
unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
- return CurDAG->getTargetConstant(V, EVT::i32);
+ return CurDAG->getTargetConstant(V, MVT::i32);
}]>;
def thumb_immshifted_shamt : SDNodeXForm<imm, [{
unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
- return CurDAG->getTargetConstant(V, EVT::i32);
+ return CurDAG->getTargetConstant(V, MVT::i32);
}]>;
// Define Thumb specific addressing modes.
index 31b8488afeab001b3ba18c87a302b0a9773f8e24..ab64b1b82feced12720e73005de1ef793d5531bb 100644 (file)
// t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), EVT::i32);
+ return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
}]>;
// t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(-((int)N->getZExtValue()), EVT::i32);
+ return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
}]>;
// t2_so_imm - Match a 32-bit immediate operand, which is an
/// Split a 32-bit immediate into two 16 bit parts.
def t2_lo16 : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() & 0xffff,
- EVT::i32);
+ MVT::i32);
}]>;
def t2_hi16 : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, EVT::i32);
+ return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
}]>;
def t2_lo16AllZero : PatLeaf<(i32 imm), [{
index c45c261d5a5bdc7fcfdbf59ba9367e986e0df529..6eae904c16e2c115a510c1aa7e891c9964c5b9a7 100644 (file)
/// Code Generation virtual methods...
const TargetRegisterClass *
- getPhysicalRegisterRegClass(unsigned Reg, EVT VT = EVT::Other) const;
+ getPhysicalRegisterRegClass(unsigned Reg, EVT VT = MVT::Other) const;
bool requiresRegisterScavenging(const MachineFunction &MF) const;
index d4b4e93210f4d61febd68ccc46a1e94fe541d5b4..c72e0f0481511be6f148b15a33bce77105c5873e 100644 (file)
/// getI64Imm - Return a target constant with the specified value, of type
/// i64.
inline SDValue getI64Imm(int64_t Imm) {
- return CurDAG->getTargetConstant(Imm, EVT::i64);
+ return CurDAG->getTargetConstant(Imm, MVT::i64);
}
// Select - Convert the specified operand from a target-independent to a
case ISD::FrameIndex: {
int FI = cast<FrameIndexSDNode>(N)->getIndex();
- return CurDAG->SelectNodeTo(N, Alpha::LDA, EVT::i64,
- CurDAG->getTargetFrameIndex(FI, EVT::i32),
+ return CurDAG->SelectNodeTo(N, Alpha::LDA, MVT::i64,
+ CurDAG->getTargetFrameIndex(FI, MVT::i32),
getI64Imm(0));
}
case ISD::GLOBAL_OFFSET_TABLE:
Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R27, N0,
Chain.getValue(1));
SDNode *CNode =
- CurDAG->getTargetNode(Alpha::JSRs, dl, EVT::Other, EVT::Flag,
+ CurDAG->getTargetNode(Alpha::JSRs, dl, MVT::Other, MVT::Flag,
Chain, Chain.getValue(1));
- Chain = CurDAG->getCopyFromReg(Chain, dl, Alpha::R27, EVT::i64,
+ Chain = CurDAG->getCopyFromReg(Chain, dl, Alpha::R27, MVT::i64,
SDValue(CNode, 1));
- return CurDAG->SelectNodeTo(N, Alpha::BISr, EVT::i64, Chain, Chain);
+ return CurDAG->SelectNodeTo(N, Alpha::BISr, MVT::i64, Chain, Chain);
}
case ISD::READCYCLECOUNTER: {
SDValue Chain = N->getOperand(0);
- return CurDAG->getTargetNode(Alpha::RPCC, dl, EVT::i64, EVT::Other,
+ return CurDAG->getTargetNode(Alpha::RPCC, dl, MVT::i64, MVT::Other,
Chain);
}
if (uval == 0) {
SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
- Alpha::R31, EVT::i64);
+ Alpha::R31, MVT::i64);
ReplaceUses(Op, Result);
return NULL;
}
break; //(zext (LDAH (LDA)))
//Else use the constant pool
ConstantInt *C = ConstantInt::get(Type::Int64Ty, uval);
- SDValue CPI = CurDAG->getTargetConstantPool(C, EVT::i64);
- SDNode *Tmp = CurDAG->getTargetNode(Alpha::LDAHr, dl, EVT::i64, CPI,
+ SDValue CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
+ SDNode *Tmp = CurDAG->getTargetNode(Alpha::LDAHr, dl, MVT::i64, CPI,
SDValue(getGlobalBaseReg(), 0));
- return CurDAG->SelectNodeTo(N, Alpha::LDQr, EVT::i64, EVT::Other,
+ return CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other,
CPI, SDValue(Tmp, 0), CurDAG->getEntryNode());
}
case ISD::TargetConstantFP:
case ISD::ConstantFP: {
ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
- bool isDouble = N->getValueType(0) == EVT::f64;
- EVT T = isDouble ? EVT::f64 : EVT::f32;
+ bool isDouble = N->getValueType(0) == MVT::f64;
+ EVT T = isDouble ? MVT::f64 : MVT::f32;
if (CN->getValueAPF().isPosZero()) {
return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYST : Alpha::CPYSS,
T, CurDAG->getRegister(Alpha::F31, T),
};
SDValue tmp1 = N->getOperand(rev?1:0);
SDValue tmp2 = N->getOperand(rev?0:1);
- SDNode *cmp = CurDAG->getTargetNode(Opc, dl, EVT::f64, tmp1, tmp2);
+ SDNode *cmp = CurDAG->getTargetNode(Opc, dl, MVT::f64, tmp1, tmp2);
if (inv)
cmp = CurDAG->getTargetNode(Alpha::CMPTEQ, dl,
- EVT::f64, SDValue(cmp, 0),
- CurDAG->getRegister(Alpha::F31, EVT::f64));
+ MVT::f64, SDValue(cmp, 0),
+ CurDAG->getRegister(Alpha::F31, MVT::f64));
switch(CC) {
case ISD::SETUEQ: case ISD::SETULT: case ISD::SETULE:
case ISD::SETUNE: case ISD::SETUGT: case ISD::SETUGE:
{
- SDNode* cmp2 = CurDAG->getTargetNode(Alpha::CMPTUN, dl, EVT::f64,
+ SDNode* cmp2 = CurDAG->getTargetNode(Alpha::CMPTUN, dl, MVT::f64,
tmp1, tmp2);
- cmp = CurDAG->getTargetNode(Alpha::ADDT, dl, EVT::f64,
+ cmp = CurDAG->getTargetNode(Alpha::ADDT, dl, MVT::f64,
SDValue(cmp2, 0), SDValue(cmp, 0));
break;
}
}
SDNode* LD = CurDAG->getTargetNode(Alpha::FTOIT, dl,
- EVT::i64, SDValue(cmp, 0));
- return CurDAG->getTargetNode(Alpha::CMPULT, dl, EVT::i64,
- CurDAG->getRegister(Alpha::R31, EVT::i64),
+ MVT::i64, SDValue(cmp, 0));
+ return CurDAG->getTargetNode(Alpha::CMPULT, dl, MVT::i64,
+ CurDAG->getRegister(Alpha::R31, MVT::i64),
SDValue(LD,0));
}
break;
if (get_zapImm(mask)) {
SDValue Z =
- SDValue(CurDAG->getTargetNode(Alpha::ZAPNOTi, dl, EVT::i64,
+ SDValue(CurDAG->getTargetNode(Alpha::ZAPNOTi, dl, MVT::i64,
N->getOperand(0).getOperand(0),
getI64Imm(get_zapImm(mask))), 0);
- return CurDAG->getTargetNode(Alpha::SRLr, dl, EVT::i64, Z,
+ return CurDAG->getTargetNode(Alpha::SRLr, dl, MVT::i64, Z,
getI64Imm(sval));
}
}
SDValue GOT = SDValue(getGlobalBaseReg(), 0);
Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R29, GOT, InFlag);
InFlag = Chain.getValue(1);
- Chain = SDValue(CurDAG->getTargetNode(Alpha::BSR, dl, EVT::Other,
- EVT::Flag, Addr.getOperand(0),
+ Chain = SDValue(CurDAG->getTargetNode(Alpha::BSR, dl, MVT::Other,
+ MVT::Flag, Addr.getOperand(0),
Chain, InFlag), 0);
} else {
Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R27, Addr, InFlag);
InFlag = Chain.getValue(1);
- Chain = SDValue(CurDAG->getTargetNode(Alpha::JSR, dl, EVT::Other,
- EVT::Flag, Chain, InFlag), 0);
+ Chain = SDValue(CurDAG->getTargetNode(Alpha::JSR, dl, MVT::Other,
+ MVT::Flag, Chain, InFlag), 0);
}
InFlag = Chain.getValue(1);
index 1033753ec7cbe032dfb0e9be34cf3e82e7fa4d14..42f269d9cc81d694538e990016012f74643dd579 100644 (file)
: TargetLowering(TM, new TargetLoweringObjectFileELF()) {
// Set up the TargetLowering object.
//I am having problems with shr n i8 1
- setShiftAmountType(EVT::i64);
+ setShiftAmountType(MVT::i64);
setBooleanContents(ZeroOrOneBooleanContent);
setUsesGlobalOffsetTable(true);
- addRegisterClass(EVT::i64, Alpha::GPRCRegisterClass);
- addRegisterClass(EVT::f64, Alpha::F8RCRegisterClass);
- addRegisterClass(EVT::f32, Alpha::F4RCRegisterClass);
+ addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass);
+ addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass);
+ addRegisterClass(MVT::f32, Alpha::F4RCRegisterClass);
// We want to custom lower some of our intrinsics.
- setOperationAction(ISD::INTRINSIC_WO_CHAIN, EVT::Other, Custom);
+ setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
- setLoadExtAction(ISD::EXTLOAD, EVT::i1, Promote);
- setLoadExtAction(ISD::EXTLOAD, EVT::f32, Expand);
+ setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
+ setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
- setLoadExtAction(ISD::ZEXTLOAD, EVT::i1, Promote);
- setLoadExtAction(ISD::ZEXTLOAD, EVT::i32, Expand);
+ setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
+ setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Expand);
- setLoadExtAction(ISD::SEXTLOAD, EVT::i1, Promote);
- setLoadExtAction(ISD::SEXTLOAD, EVT::i8, Expand);
- setLoadExtAction(ISD::SEXTLOAD, EVT::i16, Expand);
+ setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
+ setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
+ setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
- setTruncStoreAction(EVT::f64, EVT::f32, Expand);
+ setTruncStoreAction(MVT::f64, MVT::f32, Expand);
- // setOperationAction(ISD::BRIND, EVT::Other, Expand);
- setOperationAction(ISD::BR_JT, EVT::Other, Expand);
- setOperationAction(ISD::BR_CC, EVT::Other, Expand);
- setOperationAction(ISD::SELECT_CC, EVT::Other, Expand);
+ // setOperationAction(ISD::BRIND, MVT::Other, Expand);
+ setOperationAction(ISD::BR_JT, MVT::Other, Expand);
+ setOperationAction(ISD::BR_CC, MVT::Other, Expand);
+ setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
- setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i1, Expand);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
- setOperationAction(ISD::FREM, EVT::f32, Expand);
- setOperationAction(ISD::FREM, EVT::f64, Expand);
+ setOperationAction(ISD::FREM, MVT::f32, Expand);
+ setOperationAction(ISD::FREM, MVT::f64, Expand);
- setOperationAction(ISD::UINT_TO_FP, EVT::i64, Expand);
- setOperationAction(ISD::SINT_TO_FP, EVT::i64, Custom);
- setOperationAction(ISD::FP_TO_UINT, EVT::i64, Expand);
- setOperationAction(ISD::FP_TO_SINT, EVT::i64, Custom);
+ setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
+ setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
+ setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
+ setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
if (!TM.getSubtarget<AlphaSubtarget>().hasCT()) {
- setOperationAction(ISD::CTPOP , EVT::i64 , Expand);
- setOperationAction(ISD::CTTZ , EVT::i64 , Expand);
- setOperationAction(ISD::CTLZ , EVT::i64 , Expand);
+ setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
+ setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
+ setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
}
- setOperationAction(ISD::BSWAP , EVT::i64, Expand);
- setOperationAction(ISD::ROTL , EVT::i64, Expand);
- setOperationAction(ISD::ROTR , EVT::i64, Expand);
+ setOperationAction(ISD::BSWAP , MVT::i64, Expand);
+ setOperationAction(ISD::ROTL , MVT::i64, Expand);
+ setOperationAction(ISD::ROTR , MVT::i64, Expand);
- setOperationAction(ISD::SREM , EVT::i64, Custom);
- setOperationAction(ISD::UREM , EVT::i64, Custom);
- setOperationAction(ISD::SDIV , EVT::i64, Custom);
- setOperationAction(ISD::UDIV , EVT::i64, Custom);
+ setOperationAction(ISD::SREM , MVT::i64, Custom);
+ setOperationAction(ISD::UREM , MVT::i64, Custom);
+ setOperationAction(ISD::SDIV , MVT::i64, Custom);
+ setOperationAction(ISD::UDIV , MVT::i64, Custom);
- setOperationAction(ISD::ADDC , EVT::i64, Expand);
- setOperationAction(ISD::ADDE , EVT::i64, Expand);
- setOperationAction(ISD::SUBC , EVT::i64, Expand);
- setOperationAction(ISD::SUBE , EVT::i64, Expand);
+ setOperationAction(ISD::ADDC , MVT::i64, Expand);
+ setOperationAction(ISD::ADDE , MVT::i64, Expand);
+ setOperationAction(ISD::SUBC , MVT::i64, Expand);
+ setOperationAction(ISD::SUBE , MVT::i64, Expand);
- setOperationAction(ISD::UMUL_LOHI, EVT::i64, Expand);
- setOperationAction(ISD::SMUL_LOHI, EVT::i64, Expand);
+ setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
+ setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
- setOperationAction(ISD::SRL_PARTS, EVT::i64, Custom);
- setOperationAction(ISD::SRA_PARTS, EVT::i64, Expand);
- setOperationAction(ISD::SHL_PARTS, EVT::i64, Expand);
+ setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
+ setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
+ setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
// We don't support sin/cos/sqrt/pow
- setOperationAction(ISD::FSIN , EVT::f64, Expand);
- setOperationAction(ISD::FCOS , EVT::f64, Expand);
- setOperationAction(ISD::FSIN , EVT::f32, Expand);
- setOperationAction(ISD::FCOS , EVT::f32, Expand);
+ setOperationAction(ISD::FSIN , MVT::f64, Expand);
+ setOperationAction(ISD::FCOS , MVT::f64, Expand);
+ setOperationAction(ISD::FSIN , MVT::f32, Expand);
+ setOperationAction(ISD::FCOS , MVT::f32, Expand);
- setOperationAction(ISD::FSQRT, EVT::f64, Expand);
- setOperationAction(ISD::FSQRT, EVT::f32, Expand);
+ setOperationAction(ISD::FSQRT, MVT::f64, Expand);
+ setOperationAction(ISD::FSQRT, MVT::f32, Expand);
- setOperationAction(ISD::FPOW , EVT::f32, Expand);
- setOperationAction(ISD::FPOW , EVT::f64, Expand);
+ setOperationAction(ISD::FPOW , MVT::f32, Expand);
+ setOperationAction(ISD::FPOW , MVT::f64, Expand);
- setOperationAction(ISD::SETCC, EVT::f32, Promote);
+ setOperationAction(ISD::SETCC, MVT::f32, Promote);
- setOperationAction(ISD::BIT_CONVERT, EVT::f32, Promote);
+ setOperationAction(ISD::BIT_CONVERT, MVT::f32, Promote);
// We don't have line number support yet.
- setOperationAction(ISD::DBG_STOPPOINT, EVT::Other, Expand);
- setOperationAction(ISD::DEBUG_LOC, EVT::Other, Expand);
- setOperationAction(ISD::DBG_LABEL, EVT::Other, Expand);
- setOperationAction(ISD::EH_LABEL, EVT::Other, Expand);
+ setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
+ setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
+ setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
+ setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
// Not implemented yet.
- setOperationAction(ISD::STACKSAVE, EVT::Other, Expand);
- setOperationAction(ISD::STACKRESTORE, EVT::Other, Expand);
- setOperationAction(ISD::DYNAMIC_STACKALLOC, EVT::i64, Expand);
+ setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
+ setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
+ setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
// We want to legalize GlobalAddress and ConstantPool and
// ExternalSymbols nodes into the appropriate instructions to
// materialize the address.
- setOperationAction(ISD::GlobalAddress, EVT::i64, Custom);
- setOperationAction(ISD::ConstantPool, EVT::i64, Custom);
- setOperationAction(ISD::ExternalSymbol, EVT::i64, Custom);
- setOperationAction(ISD::GlobalTLSAddress, EVT::i64, Custom);
+ setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
+ setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
+ setOperationAction(ISD::ExternalSymbol, MVT::i64, Custom);
+ setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
- setOperationAction(ISD::VASTART, EVT::Other, Custom);
- setOperationAction(ISD::VAEND, EVT::Other, Expand);
- setOperationAction(ISD::VACOPY, EVT::Other, Custom);
- setOperationAction(ISD::VAARG, EVT::Other, Custom);
- setOperationAction(ISD::VAARG, EVT::i32, Custom);
+ setOperationAction(ISD::VASTART, MVT::Other, Custom);
+ setOperationAction(ISD::VAEND, MVT::Other, Expand);
+ setOperationAction(ISD::VACOPY, MVT::Other, Custom);
+ setOperationAction(ISD::VAARG, MVT::Other, Custom);
+ setOperationAction(ISD::VAARG, MVT::i32, Custom);
- setOperationAction(ISD::JumpTable, EVT::i64, Custom);
- setOperationAction(ISD::JumpTable, EVT::i32, Custom);
+ setOperationAction(ISD::JumpTable, MVT::i64, Custom);
+ setOperationAction(ISD::JumpTable, MVT::i32, Custom);
setStackPointerRegisterToSaveRestore(Alpha::R30);
computeRegisterProperties();
}
-EVT::SimpleValueType AlphaTargetLowering::getSetCCResultType(EVT VT) const {
- return EVT::i64;
+MVT::SimpleValueType AlphaTargetLowering::getSetCCResultType(EVT VT) const {
+ return MVT::i64;
}
const char *AlphaTargetLowering::getTargetNodeName(unsigned Opcode) const {
// FIXME there isn't really any debug info here
DebugLoc dl = Op.getDebugLoc();
- SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, EVT::i64, JTI,
- DAG.getGLOBAL_OFFSET_TABLE(EVT::i64));
- SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, EVT::i64, JTI, Hi);
+ SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, MVT::i64, JTI,
+ DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
+ SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, MVT::i64, JTI, Hi);
return Lo;
}
assert(VA.isMemLoc());
if (StackPtr.getNode() == 0)
- StackPtr = DAG.getCopyFromReg(Chain, dl, Alpha::R30, EVT::i64);
+ StackPtr = DAG.getCopyFromReg(Chain, dl, Alpha::R30, MVT::i64);
SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
StackPtr,
// Transform all store nodes into one single node because all store nodes are
// independent of each other.
if (!MemOpChains.empty())
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&MemOpChains[0], MemOpChains.size());
// Build a sequence of copy-to-reg nodes chained together with token chain and
}
// Returns a chain & a flag for retval copy to use.
- SDVTList NodeTys = DAG.getVTList(EVT::Other, EVT::Flag);
+ SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
SmallVector<SDValue, 8> Ops;
Ops.push_back(Chain);
Ops.push_back(Callee);
SDValue ArgVal;
if (ArgNo < 6) {
- switch (ObjectVT.getSimpleVT()) {
+ switch (ObjectVT.getSimpleVT().SimpleTy) {
default:
assert(false && "Invalid value type!");
- case EVT::f64:
+ case MVT::f64:
args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
&Alpha::F8RCRegClass);
ArgVal = DAG.getCopyFromReg(Chain, dl, args_float[ArgNo], ObjectVT);
break;
- case EVT::f32:
+ case MVT::f32:
args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
&Alpha::F4RCRegClass);
ArgVal = DAG.getCopyFromReg(Chain, dl, args_float[ArgNo], ObjectVT);
break;
- case EVT::i64:
+ case MVT::i64:
args_int[ArgNo] = AddLiveIn(MF, args_int[ArgNo],
&Alpha::GPRCRegClass);
- ArgVal = DAG.getCopyFromReg(Chain, dl, args_int[ArgNo], EVT::i64);
+ ArgVal = DAG.getCopyFromReg(Chain, dl, args_int[ArgNo], MVT::i64);
break;
}
} else { //more args
// Create the SelectionDAG nodes corresponding to a load
//from this parameter
- SDValue FIN = DAG.getFrameIndex(FI, EVT::i64);
+ SDValue FIN = DAG.getFrameIndex(FI, MVT::i64);
ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, NULL, 0);
}
InVals.push_back(ArgVal);
for (int i = 0; i < 6; ++i) {
if (TargetRegisterInfo::isPhysicalRegister(args_int[i]))
args_int[i] = AddLiveIn(MF, args_int[i], &Alpha::GPRCRegClass);
- SDValue argt = DAG.getCopyFromReg(Chain, dl, args_int[i], EVT::i64);
+ SDValue argt = DAG.getCopyFromReg(Chain, dl, args_int[i], MVT::i64);
int FI = MFI->CreateFixedObject(8, -8 * (6 - i));
if (i == 0) VarArgsBase = FI;
- SDValue SDFI = DAG.getFrameIndex(FI, EVT::i64);
+ SDValue SDFI = DAG.getFrameIndex(FI, MVT::i64);
LS.push_back(DAG.getStore(Chain, dl, argt, SDFI, NULL, 0));
if (TargetRegisterInfo::isPhysicalRegister(args_float[i]))
args_float[i] = AddLiveIn(MF, args_float[i], &Alpha::F8RCRegClass);
- argt = DAG.getCopyFromReg(Chain, dl, args_float[i], EVT::f64);
+ argt = DAG.getCopyFromReg(Chain, dl, args_float[i], MVT::f64);
FI = MFI->CreateFixedObject(8, - 8 * (12 - i));
- SDFI = DAG.getFrameIndex(FI, EVT::i64);
+ SDFI = DAG.getFrameIndex(FI, MVT::i64);
LS.push_back(DAG.getStore(Chain, dl, argt, SDFI, NULL, 0));
}
//Set up a token factor with all the stack traffic
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &LS[0], LS.size());
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &LS[0], LS.size());
}
return Chain;
SDValue Copy = DAG.getCopyToReg(Chain, dl, Alpha::R26,
DAG.getNode(AlphaISD::GlobalRetAddr,
DebugLoc::getUnknownLoc(),
- EVT::i64),
+ MVT::i64),
SDValue());
switch (Outs.size()) {
default:
}
}
return DAG.getNode(AlphaISD::RET_FLAG, dl,
- EVT::Other, Copy, Copy.getValue(1));
+ MVT::Other, Copy, Copy.getValue(1));
}
void AlphaTargetLowering::LowerVAARG(SDNode *N, SDValue &Chain,
const Value *VAListS = cast<SrcValueSDNode>(N->getOperand(2))->getValue();
DebugLoc dl = N->getDebugLoc();
- SDValue Base = DAG.getLoad(EVT::i64, dl, Chain, VAListP, VAListS, 0);
- SDValue Tmp = DAG.getNode(ISD::ADD, dl, EVT::i64, VAListP,
- DAG.getConstant(8, EVT::i64));
- SDValue Offset = DAG.getExtLoad(ISD::SEXTLOAD, dl, EVT::i64, Base.getValue(1),
- Tmp, NULL, 0, EVT::i32);
- DataPtr = DAG.getNode(ISD::ADD, dl, EVT::i64, Base, Offset);
+ SDValue Base = DAG.getLoad(MVT::i64, dl, Chain, VAListP, VAListS, 0);
+ SDValue Tmp = DAG.getNode(ISD::ADD, dl, MVT::i64, VAListP,
+ DAG.getConstant(8, MVT::i64));
+ SDValue Offset = DAG.getExtLoad(ISD::SEXTLOAD, dl, MVT::i64, Base.getValue(1),
+ Tmp, NULL, 0, MVT::i32);
+ DataPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Base, Offset);
if (N->getValueType(0).isFloatingPoint())
{
//if fp && Offset < 6*8, then subtract 6*8 from DataPtr
- SDValue FPDataPtr = DAG.getNode(ISD::SUB, dl, EVT::i64, DataPtr,
- DAG.getConstant(8*6, EVT::i64));
- SDValue CC = DAG.getSetCC(dl, EVT::i64, Offset,
- DAG.getConstant(8*6, EVT::i64), ISD::SETLT);
- DataPtr = DAG.getNode(ISD::SELECT, dl, EVT::i64, CC, FPDataPtr, DataPtr);
+ SDValue FPDataPtr = DAG.getNode(ISD::SUB, dl, MVT::i64, DataPtr,
+ DAG.getConstant(8*6, MVT::i64));
+ SDValue CC = DAG.getSetCC(dl, MVT::i64, Offset,
+ DAG.getConstant(8*6, MVT::i64), ISD::SETLT);
+ DataPtr = DAG.getNode(ISD::SELECT, dl, MVT::i64, CC, FPDataPtr, DataPtr);
}
- SDValue NewOffset = DAG.getNode(ISD::ADD, dl, EVT::i64, Offset,
- DAG.getConstant(8, EVT::i64));
+ SDValue NewOffset = DAG.getNode(ISD::ADD, dl, MVT::i64, Offset,
+ DAG.getConstant(8, MVT::i64));
Chain = DAG.getTruncStore(Offset.getValue(1), dl, NewOffset, Tmp, NULL, 0,
- EVT::i32);
+ MVT::i32);
}
/// LowerOperation - Provide custom lowering hooks for some operations.
switch (IntNo) {
default: break; // Don't custom lower most intrinsics.
case Intrinsic::alpha_umulh:
- return DAG.getNode(ISD::MULHU, dl, EVT::i64,
+ return DAG.getNode(ISD::MULHU, dl, MVT::i64,
Op.getOperand(1), Op.getOperand(2));
}
}
SDValue ShOpLo = Op.getOperand(0);
SDValue ShOpHi = Op.getOperand(1);
SDValue ShAmt = Op.getOperand(2);
- SDValue bm = DAG.getNode(ISD::SUB, dl, EVT::i64,
- DAG.getConstant(64, EVT::i64), ShAmt);
- SDValue BMCC = DAG.getSetCC(dl, EVT::i64, bm,
- DAG.getConstant(0, EVT::i64), ISD::SETLE);
+ SDValue bm = DAG.getNode(ISD::SUB, dl, MVT::i64,
+ DAG.getConstant(64, MVT::i64), ShAmt);
+ SDValue BMCC = DAG.getSetCC(dl, MVT::i64, bm,
+ DAG.getConstant(0, MVT::i64), ISD::SETLE);
// if 64 - shAmt <= 0
- SDValue Hi_Neg = DAG.getConstant(0, EVT::i64);
- SDValue ShAmt_Neg = DAG.getNode(ISD::SUB, dl, EVT::i64,
- DAG.getConstant(0, EVT::i64), bm);
- SDValue Lo_Neg = DAG.getNode(ISD::SRL, dl, EVT::i64, ShOpHi, ShAmt_Neg);
+ SDValue Hi_Neg = DAG.getConstant(0, MVT::i64);
+ SDValue ShAmt_Neg = DAG.getNode(ISD::SUB, dl, MVT::i64,
+ DAG.getConstant(0, MVT::i64), bm);
+ SDValue Lo_Neg = DAG.getNode(ISD::SRL, dl, MVT::i64, ShOpHi, ShAmt_Neg);
// else
- SDValue carries = DAG.getNode(ISD::SHL, dl, EVT::i64, ShOpHi, bm);
- SDValue Hi_Pos = DAG.getNode(ISD::SRL, dl, EVT::i64, ShOpHi, ShAmt);
- SDValue Lo_Pos = DAG.getNode(ISD::SRL, dl, EVT::i64, ShOpLo, ShAmt);
- Lo_Pos = DAG.getNode(ISD::OR, dl, EVT::i64, Lo_Pos, carries);
+ SDValue carries = DAG.getNode(ISD::SHL, dl, MVT::i64, ShOpHi, bm);
+ SDValue Hi_Pos = DAG.getNode(ISD::SRL, dl, MVT::i64, ShOpHi, ShAmt);
+ SDValue Lo_Pos = DAG.getNode(ISD::SRL, dl, MVT::i64, ShOpLo, ShAmt);
+ Lo_Pos = DAG.getNode(ISD::OR, dl, MVT::i64, Lo_Pos, carries);
// Merge
- SDValue Hi = DAG.getNode(ISD::SELECT, dl, EVT::i64, BMCC, Hi_Neg, Hi_Pos);
- SDValue Lo = DAG.getNode(ISD::SELECT, dl, EVT::i64, BMCC, Lo_Neg, Lo_Pos);
+ SDValue Hi = DAG.getNode(ISD::SELECT, dl, MVT::i64, BMCC, Hi_Neg, Hi_Pos);
+ SDValue Lo = DAG.getNode(ISD::SELECT, dl, MVT::i64, BMCC, Lo_Neg, Lo_Pos);
SDValue Ops[2] = { Lo, Hi };
return DAG.getMergeValues(Ops, 2, dl);
}
case ISD::SINT_TO_FP: {
- assert(Op.getOperand(0).getValueType() == EVT::i64 &&
+ assert(Op.getOperand(0).getValueType() == MVT::i64 &&
"Unhandled SINT_TO_FP type in custom expander!");
SDValue LD;
- bool isDouble = Op.getValueType() == EVT::f64;
- LD = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f64, Op.getOperand(0));
+ bool isDouble = Op.getValueType() == MVT::f64;
+ LD = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op.getOperand(0));
SDValue FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_, dl,
- isDouble?EVT::f64:EVT::f32, LD);
+ isDouble?MVT::f64:MVT::f32, LD);
return FP;
}
case ISD::FP_TO_SINT: {
- bool isDouble = Op.getOperand(0).getValueType() == EVT::f64;
+ bool isDouble = Op.getOperand(0).getValueType() == MVT::f64;
SDValue src = Op.getOperand(0);
if (!isDouble) //Promote
- src = DAG.getNode(ISD::FP_EXTEND, dl, EVT::f64, src);
+ src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, src);
- src = DAG.getNode(AlphaISD::CVTTQ_, dl, EVT::f64, src);
+ src = DAG.getNode(AlphaISD::CVTTQ_, dl, MVT::f64, src);
- return DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i64, src);
+ return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, src);
}
case ISD::ConstantPool: {
ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
Constant *C = CP->getConstVal();
- SDValue CPI = DAG.getTargetConstantPool(C, EVT::i64, CP->getAlignment());
+ SDValue CPI = DAG.getTargetConstantPool(C, MVT::i64, CP->getAlignment());
// FIXME there isn't really any debug info here
- SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, EVT::i64, CPI,
- DAG.getGLOBAL_OFFSET_TABLE(EVT::i64));
- SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, EVT::i64, CPI, Hi);
+ SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, MVT::i64, CPI,
+ DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
+ SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, MVT::i64, CPI, Hi);
return Lo;
}
case ISD::GlobalTLSAddress:
case ISD::GlobalAddress: {
GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
GlobalValue *GV = GSDN->getGlobal();
- SDValue GA = DAG.getTargetGlobalAddress(GV, EVT::i64, GSDN->getOffset());
+ SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i64, GSDN->getOffset());
// FIXME there isn't really any debug info here
// if (!GV->hasWeakLinkage() && !GV->isDeclaration() && !GV->hasLinkOnceLinkage()) {
if (GV->hasLocalLinkage()) {
- SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, EVT::i64, GA,
- DAG.getGLOBAL_OFFSET_TABLE(EVT::i64));
- SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, EVT::i64, GA, Hi);
+ SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, MVT::i64, GA,
+ DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
+ SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, MVT::i64, GA, Hi);
return Lo;
} else
- return DAG.getNode(AlphaISD::RelLit, dl, EVT::i64, GA,
- DAG.getGLOBAL_OFFSET_TABLE(EVT::i64));
+ return DAG.getNode(AlphaISD::RelLit, dl, MVT::i64, GA,
+ DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
}
case ISD::ExternalSymbol: {
- return DAG.getNode(AlphaISD::RelLit, dl, EVT::i64,
+ return DAG.getNode(AlphaISD::RelLit, dl, MVT::i64,
DAG.getTargetExternalSymbol(cast<ExternalSymbolSDNode>(Op)
- ->getSymbol(), EVT::i64),
- DAG.getGLOBAL_OFFSET_TABLE(EVT::i64));
+ ->getSymbol(), MVT::i64),
+ DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
}
case ISD::UREM:
}
SDValue Tmp1 = Op.getOperand(0),
Tmp2 = Op.getOperand(1),
- Addr = DAG.getExternalSymbol(opstr, EVT::i64);
- return DAG.getNode(AlphaISD::DivCall, dl, EVT::i64, Addr, Tmp1, Tmp2);
+ Addr = DAG.getExternalSymbol(opstr, MVT::i64);
+ return DAG.getNode(AlphaISD::DivCall, dl, MVT::i64, Addr, Tmp1, Tmp2);
}
break;
LowerVAARG(Op.getNode(), Chain, DataPtr, DAG);
SDValue Result;
- if (Op.getValueType() == EVT::i32)
- Result = DAG.getExtLoad(ISD::SEXTLOAD, dl, EVT::i64, Chain, DataPtr,
- NULL, 0, EVT::i32);
+ if (Op.getValueType() == MVT::i32)
+ Result = DAG.getExtLoad(ISD::SEXTLOAD, dl, MVT::i64, Chain, DataPtr,
+ NULL, 0, MVT::i32);
else
Result = DAG.getLoad(Op.getValueType(), dl, Chain, DataPtr, NULL, 0);
return Result;
SDValue Val = DAG.getLoad(getPointerTy(), dl, Chain, SrcP, SrcS, 0);
SDValue Result = DAG.getStore(Val.getValue(1), dl, Val, DestP, DestS, 0);
- SDValue NP = DAG.getNode(ISD::ADD, dl, EVT::i64, SrcP,
- DAG.getConstant(8, EVT::i64));
- Val = DAG.getExtLoad(ISD::SEXTLOAD, dl, EVT::i64, Result,
- NP, NULL,0, EVT::i32);
- SDValue NPD = DAG.getNode(ISD::ADD, dl, EVT::i64, DestP,
- DAG.getConstant(8, EVT::i64));
- return DAG.getTruncStore(Val.getValue(1), dl, Val, NPD, NULL, 0, EVT::i32);
+ SDValue NP = DAG.getNode(ISD::ADD, dl, MVT::i64, SrcP,
+ DAG.getConstant(8, MVT::i64));
+ Val = DAG.getExtLoad(ISD::SEXTLOAD, dl, MVT::i64, Result,
+ NP, NULL,0, MVT::i32);
+ SDValue NPD = DAG.getNode(ISD::ADD, dl, MVT::i64, DestP,
+ DAG.getConstant(8, MVT::i64));
+ return DAG.getTruncStore(Val.getValue(1), dl, Val, NPD, NULL, 0, MVT::i32);
}
case ISD::VASTART: {
SDValue Chain = Op.getOperand(0);
const Value *VAListS = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
// vastart stores the address of the VarArgsBase and VarArgsOffset
- SDValue FR = DAG.getFrameIndex(VarArgsBase, EVT::i64);
+ SDValue FR = DAG.getFrameIndex(VarArgsBase, MVT::i64);
SDValue S1 = DAG.getStore(Chain, dl, FR, VAListP, VAListS, 0);
- SDValue SA2 = DAG.getNode(ISD::ADD, dl, EVT::i64, VAListP,
- DAG.getConstant(8, EVT::i64));
- return DAG.getTruncStore(S1, dl, DAG.getConstant(VarArgsOffset, EVT::i64),
- SA2, NULL, 0, EVT::i32);
+ SDValue SA2 = DAG.getNode(ISD::ADD, dl, MVT::i64, VAListP,
+ DAG.getConstant(8, MVT::i64));
+ return DAG.getTruncStore(S1, dl, DAG.getConstant(VarArgsOffset, MVT::i64),
+ SA2, NULL, 0, MVT::i32);
}
case ISD::RETURNADDR:
return DAG.getNode(AlphaISD::GlobalRetAddr, DebugLoc::getUnknownLoc(),
- EVT::i64);
+ MVT::i64);
//FIXME: implement
case ISD::FRAMEADDR: break;
}
SmallVectorImpl<SDValue>&Results,
SelectionDAG &DAG) {
DebugLoc dl = N->getDebugLoc();
- assert(N->getValueType(0) == EVT::i32 &&
+ assert(N->getValueType(0) == MVT::i32 &&
N->getOpcode() == ISD::VAARG &&
"Unknown node to custom promote!");
index f18d6fa4e22e877f93074c641c4183c8a4afd9f3..8edc791c088b9b7e7c3c0155319ff7a903edae88 100644 (file)
explicit AlphaTargetLowering(TargetMachine &TM);
/// getSetCCResultType - Get the SETCC result ValueType
- virtual EVT::SimpleValueType getSetCCResultType(EVT VT) const;
+ virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const;
/// LowerOperation - Provide custom lowering hooks for some operations.
///
diff --git a/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp b/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp
index 3bf8fc5b47da804aab9a3e4bfad76abb851e9172..062b22abe6e183f2c1041c2181a5acc837e6e1fd 100644 (file)
// Selects to ADDpp FI, 0 which in turn will become ADDimm7 SP, imm or ADDpp
// SP, Px
int FI = cast<FrameIndexSDNode>(N)->getIndex();
- SDValue TFI = CurDAG->getTargetFrameIndex(FI, EVT::i32);
- return CurDAG->SelectNodeTo(N, BF::ADDpp, EVT::i32, TFI,
- CurDAG->getTargetConstant(0, EVT::i32));
+ SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i32);
+ return CurDAG->SelectNodeTo(N, BF::ADDpp, MVT::i32, TFI,
+ CurDAG->getTargetConstant(0, MVT::i32));
}
}
SDValue &Offset) {
FrameIndexSDNode *FIN = 0;
if ((FIN = dyn_cast<FrameIndexSDNode>(Addr))) {
- Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), EVT::i32);
- Offset = CurDAG->getTargetConstant(0, EVT::i32);
+ Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
+ Offset = CurDAG->getTargetConstant(0, MVT::i32);
return true;
}
if (Addr.getOpcode() == ISD::ADD) {
(CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) &&
(CN->getSExtValue() % 4 == 0 && CN->getSExtValue() >= 0)) {
// Constant positive word offset from frame index
- Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), EVT::i32);
- Offset = CurDAG->getTargetConstant(CN->getSExtValue(), EVT::i32);
+ Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
+ Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32);
return true;
}
}
SDNode *Copy =
DAG.getTargetNode(TargetInstrInfo::COPY_TO_REGCLASS,
NI->getDebugLoc(),
- EVT::i32,
+ MVT::i32,
UI.getUse().get(),
- DAG.getTargetConstant(BF::DRegClassID, EVT::i32));
+ DAG.getTargetConstant(BF::DRegClassID, MVT::i32));
UpdateNodeOperand(DAG, *UI, UI.getOperandNo(), SDValue(Copy, 0));
}
}
diff --git a/lib/Target/Blackfin/BlackfinISelLowering.cpp b/lib/Target/Blackfin/BlackfinISelLowering.cpp
index f40d9585c02cb1bee940e4496a64ac9b05578117..678d6e3e61b5704c48892580d9716062a6e4197c 100644 (file)
BlackfinTargetLowering::BlackfinTargetLowering(TargetMachine &TM)
: TargetLowering(TM, new TargetLoweringObjectFileELF()) {
- setShiftAmountType(EVT::i16);
+ setShiftAmountType(MVT::i16);
setBooleanContents(ZeroOrOneBooleanContent);
setStackPointerRegisterToSaveRestore(BF::SP);
setIntDivIsCheap(false);
// Set up the legal register classes.
- addRegisterClass(EVT::i32, BF::DRegisterClass);
- addRegisterClass(EVT::i16, BF::D16RegisterClass);
+ addRegisterClass(MVT::i32, BF::DRegisterClass);
+ addRegisterClass(MVT::i16, BF::D16RegisterClass);
computeRegisterProperties();
// Blackfin doesn't have i1 loads or stores
- setLoadExtAction(ISD::EXTLOAD, EVT::i1, Promote);
- setLoadExtAction(ISD::ZEXTLOAD, EVT::i1, Promote);
- setLoadExtAction(ISD::SEXTLOAD, EVT::i1, Promote);
+ setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
+ setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
+ setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
- setOperationAction(ISD::GlobalAddress, EVT::i32, Custom);
- setOperationAction(ISD::JumpTable, EVT::i32, Custom);
+ setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
+ setOperationAction(ISD::JumpTable, MVT::i32, Custom);
- setOperationAction(ISD::SELECT_CC, EVT::Other, Expand);
- setOperationAction(ISD::BR_JT, EVT::Other, Expand);
- setOperationAction(ISD::BR_CC, EVT::Other, Expand);
+ setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
+ setOperationAction(ISD::BR_JT, MVT::Other, Expand);
+ setOperationAction(ISD::BR_CC, MVT::Other, Expand);
// i16 registers don't do much
- setOperationAction(ISD::AND, EVT::i16, Promote);
- setOperationAction(ISD::OR, EVT::i16, Promote);
- setOperationAction(ISD::XOR, EVT::i16, Promote);
- setOperationAction(ISD::CTPOP, EVT::i16, Promote);
+ setOperationAction(ISD::AND, MVT::i16, Promote);
+ setOperationAction(ISD::OR, MVT::i16, Promote);
+ setOperationAction(ISD::XOR, MVT::i16, Promote);
+ setOperationAction(ISD::CTPOP, MVT::i16, Promote);
// The expansion of CTLZ/CTTZ uses AND/OR, so we might as well promote
// immediately.
- setOperationAction(ISD::CTLZ, EVT::i16, Promote);
- setOperationAction(ISD::CTTZ, EVT::i16, Promote);
- setOperationAction(ISD::SETCC, EVT::i16, Promote);
+ setOperationAction(ISD::CTLZ, MVT::i16, Promote);
+ setOperationAction(ISD::CTTZ, MVT::i16, Promote);
+ setOperationAction(ISD::SETCC, MVT::i16, Promote);
// Blackfin has no division
- setOperationAction(ISD::SDIV, EVT::i16, Expand);
- setOperationAction(ISD::SDIV, EVT::i32, Expand);
- setOperationAction(ISD::SDIVREM, EVT::i16, Expand);
- setOperationAction(ISD::SDIVREM, EVT::i32, Expand);
- setOperationAction(ISD::SREM, EVT::i16, Expand);
- setOperationAction(ISD::SREM, EVT::i32, Expand);
- setOperationAction(ISD::UDIV, EVT::i16, Expand);
- setOperationAction(ISD::UDIV, EVT::i32, Expand);
- setOperationAction(ISD::UDIVREM, EVT::i16, Expand);
- setOperationAction(ISD::UDIVREM, EVT::i32, Expand);
- setOperationAction(ISD::UREM, EVT::i16, Expand);
- setOperationAction(ISD::UREM, EVT::i32, Expand);
-
- setOperationAction(ISD::SMUL_LOHI, EVT::i32, Expand);
- setOperationAction(ISD::UMUL_LOHI, EVT::i32, Expand);
- setOperationAction(ISD::MULHU, EVT::i32, Expand);
- setOperationAction(ISD::MULHS, EVT::i32, Expand);
+ setOperationAction(ISD::SDIV, MVT::i16, Expand);
+ setOperationAction(ISD::SDIV, MVT::i32, Expand);
+ setOperationAction(ISD::SDIVREM, MVT::i16, Expand);
+ setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
+ setOperationAction(ISD::SREM, MVT::i16, Expand);
+ setOperationAction(ISD::SREM, MVT::i32, Expand);
+ setOperationAction(ISD::UDIV, MVT::i16, Expand);
+ setOperationAction(ISD::UDIV, MVT::i32, Expand);
+ setOperationAction(ISD::UDIVREM, MVT::i16, Expand);
+ setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
+ setOperationAction(ISD::UREM, MVT::i16, Expand);
+ setOperationAction(ISD::UREM, MVT::i32, Expand);
+
+ setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
+ setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
+ setOperationAction(ISD::MULHU, MVT::i32, Expand);
+ setOperationAction(ISD::MULHS, MVT::i32, Expand);
// No carry-in operations.
- setOperationAction(ISD::ADDE, EVT::i32, Custom);
- setOperationAction(ISD::SUBE, EVT::i32, Custom);
+ setOperationAction(ISD::ADDE, MVT::i32, Custom);
+ setOperationAction(ISD::SUBE, MVT::i32, Custom);
// Blackfin has no intrinsics for these particular operations.
- setOperationAction(ISD::MEMBARRIER, EVT::Other, Expand);
- setOperationAction(ISD::BSWAP, EVT::i32, Expand);
+ setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
+ setOperationAction(ISD::BSWAP, MVT::i32, Expand);
- setOperationAction(ISD::SHL_PARTS, EVT::i32, Expand);
- setOperationAction(ISD::SRA_PARTS, EVT::i32, Expand);
- setOperationAction(ISD::SRL_PARTS, EVT::i32, Expand);
+ setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
+ setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
+ setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
- setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i1, Expand);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
// i32 has native CTPOP, but not CTLZ/CTTZ
- setOperationAction(ISD::CTLZ, EVT::i32, Expand);
- setOperationAction(ISD::CTTZ, EVT::i32, Expand);
+ setOperationAction(ISD::CTLZ, MVT::i32, Expand);
+ setOperationAction(ISD::CTTZ, MVT::i32, Expand);
// READCYCLECOUNTER needs special type legalization.
- setOperationAction(ISD::READCYCLECOUNTER, EVT::i64, Custom);
+ setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
// We don't have line number support yet.
- setOperationAction(ISD::DBG_STOPPOINT, EVT::Other, Expand);
- setOperationAction(ISD::DEBUG_LOC, EVT::Other, Expand);
- setOperationAction(ISD::DBG_LABEL, EVT::Other, Expand);
- setOperationAction(ISD::EH_LABEL, EVT::Other, Expand);
- setOperationAction(ISD::DECLARE, EVT::Other, Expand);
+ setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
+ setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
+ setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
+ setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
+ setOperationAction(ISD::DECLARE, MVT::Other, Expand);
// Use the default implementation.
- setOperationAction(ISD::VACOPY, EVT::Other, Expand);
- setOperationAction(ISD::VAEND, EVT::Other, Expand);
- setOperationAction(ISD::STACKSAVE, EVT::Other, Expand);
- setOperationAction(ISD::STACKRESTORE, EVT::Other, Expand);
+ setOperationAction(ISD::VACOPY, MVT::Other, Expand);
+ setOperationAction(ISD::VAEND, MVT::Other, Expand);
+ setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
+ setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
}
const char *BlackfinTargetLowering::getTargetNodeName(unsigned Opcode) const {
@@ -137,10 +137,10 @@ const char *BlackfinTargetLowering::getTargetNodeName(unsigned Opcode) const {
}
}
-EVT::SimpleValueType BlackfinTargetLowering::getSetCCResultType(EVT VT) const {
+MVT::SimpleValueType BlackfinTargetLowering::getSetCCResultType(EVT VT) const {
// SETCC always sets the CC register. Technically that is an i1 register, but
// that type is not legal, so we treat it as an i32 register.
- return EVT::i32;
+ return MVT::i32;
}
SDValue BlackfinTargetLowering::LowerGlobalAddress(SDValue Op,
DebugLoc DL = Op.getDebugLoc();
GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
- Op = DAG.getTargetGlobalAddress(GV, EVT::i32);
- return DAG.getNode(BFISD::Wrapper, DL, EVT::i32, Op);
+ Op = DAG.getTargetGlobalAddress(GV, MVT::i32);
+ return DAG.getNode(BFISD::Wrapper, DL, MVT::i32, Op);
}
SDValue BlackfinTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
DebugLoc DL = Op.getDebugLoc();
int JTI = cast<JumpTableSDNode>(Op)->getIndex();
- Op = DAG.getTargetJumpTable(JTI, EVT::i32);
- return DAG.getNode(BFISD::Wrapper, DL, EVT::i32, Op);
+ Op = DAG.getTargetJumpTable(JTI, MVT::i32);
+ return DAG.getNode(BFISD::Wrapper, DL, MVT::i32, Op);
}
SDValue
assert(VA.isMemLoc() && "CCValAssign must be RegLoc or MemLoc");
unsigned ObjSize = VA.getLocVT().getStoreSizeInBits()/8;
int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset());
- SDValue FIN = DAG.getFrameIndex(FI, EVT::i32);
+ SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, NULL, 0));
}
}
}
if (Flag.getNode()) {
- return DAG.getNode(BFISD::RET_FLAG, dl, EVT::Other, Chain, Flag);
+ return DAG.getNode(BFISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
} else {
- return DAG.getNode(BFISD::RET_FLAG, dl, EVT::Other, Chain);
+ return DAG.getNode(BFISD::RET_FLAG, dl, MVT::Other, Chain);
}
}
assert(VA.isMemLoc() && "CCValAssign must be RegLoc or MemLoc");
int Offset = VA.getLocMemOffset();
assert(Offset%4 == 0 && "Unaligned LocMemOffset");
- assert(VA.getLocVT()==EVT::i32 && "Illegal CCValAssign type");
- SDValue SPN = DAG.getCopyFromReg(Chain, dl, BF::SP, EVT::i32);
+ assert(VA.getLocVT()==MVT::i32 && "Illegal CCValAssign type");
+ SDValue SPN = DAG.getCopyFromReg(Chain, dl, BF::SP, MVT::i32);
SDValue OffsetN = DAG.getIntPtrConstant(Offset);
- OffsetN = DAG.getNode(ISD::ADD, dl, EVT::i32, SPN, OffsetN);
+ OffsetN = DAG.getNode(ISD::ADD, dl, MVT::i32, SPN, OffsetN);
MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, OffsetN,
PseudoSourceValue::getStack(),
Offset));
// Transform all store nodes into one single node because
// all store nodes are independent of each other.
if (!MemOpChains.empty())
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&MemOpChains[0], MemOpChains.size());
// Build a sequence of copy-to-reg nodes chained together with token
// turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
// Likewise ExternalSymbol -> TargetExternalSymbol.
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
- Callee = DAG.getTargetGlobalAddress(G->getGlobal(), EVT::i32);
+ Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
- Callee = DAG.getTargetExternalSymbol(E->getSymbol(), EVT::i32);
+ Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
std::vector<EVT> NodeTys;
- NodeTys.push_back(EVT::Other); // Returns a chain
- NodeTys.push_back(EVT::Flag); // Returns a flag for retval copy to use.
+ NodeTys.push_back(MVT::Other); // Returns a chain
+ NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
SDValue Ops[] = { Chain, Callee, InFlag };
Chain = DAG.getNode(BFISD::CALL, dl, NodeTys, Ops,
InFlag.getNode() ? 3 : 2);
unsigned Opcode = Op.getOpcode()==ISD::ADDE ? BF::ADD : BF::SUB;
// zext incoming carry flag in AC0 to 32 bits
- SDNode* CarryIn = DAG.getTargetNode(BF::MOVE_cc_ac0, dl, EVT::i32,
+ SDNode* CarryIn = DAG.getTargetNode(BF::MOVE_cc_ac0, dl, MVT::i32,
/* flag= */ Op.getOperand(2));
- CarryIn = DAG.getTargetNode(BF::MOVECC_zext, dl, EVT::i32,
+ CarryIn = DAG.getTargetNode(BF::MOVECC_zext, dl, MVT::i32,
SDValue(CarryIn, 0));
// Add operands, produce sum and carry flag
- SDNode *Sum = DAG.getTargetNode(Opcode, dl, EVT::i32, EVT::Flag,
+ SDNode *Sum = DAG.getTargetNode(Opcode, dl, MVT::i32, MVT::Flag,
Op.getOperand(0), Op.getOperand(1));
// Store intermediate carry from Sum
- SDNode* Carry1 = DAG.getTargetNode(BF::MOVE_cc_ac0, dl, EVT::i32,
+ SDNode* Carry1 = DAG.getTargetNode(BF::MOVE_cc_ac0, dl, MVT::i32,
/* flag= */ SDValue(Sum, 1));
// Add incoming carry, again producing an output flag
- Sum = DAG.getTargetNode(Opcode, dl, EVT::i32, EVT::Flag,
+ Sum = DAG.getTargetNode(Opcode, dl, MVT::i32, MVT::Flag,
SDValue(Sum, 0), SDValue(CarryIn, 0));
// Update AC0 with the intermediate carry, producing a flag.
- SDNode *CarryOut = DAG.getTargetNode(BF::OR_ac0_cc, dl, EVT::Flag,
+ SDNode *CarryOut = DAG.getTargetNode(BF::OR_ac0_cc, dl, MVT::Flag,
SDValue(Carry1, 0));
// Compose (i32, flag) pair
// CYCLES2. Reading CYCLES will latch the value of CYCLES2, so we must read
// CYCLES2 last.
SDValue TheChain = N->getOperand(0);
- SDValue lo = DAG.getCopyFromReg(TheChain, dl, BF::CYCLES, EVT::i32);
- SDValue hi = DAG.getCopyFromReg(lo.getValue(1), dl, BF::CYCLES2, EVT::i32);
+ SDValue lo = DAG.getCopyFromReg(TheChain, dl, BF::CYCLES, MVT::i32);
+ SDValue hi = DAG.getCopyFromReg(lo.getValue(1), dl, BF::CYCLES2, MVT::i32);
// Use a buildpair to merge the two 32-bit values into a 64-bit one.
- Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, EVT::i64, lo, hi));
+ Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, lo, hi));
// Outgoing chain. If we were to use the chain from lo instead, it would be
// possible to entirely eliminate the CYCLES2 read in (i32 (trunc
// readcyclecounter)). Unfortunately this could possibly delay the CYCLES2
switch (Constraint[0]) {
// Standard constraints
case 'r':
- return Pair(0U, VT == EVT::i16 ? D16RegisterClass : DPRegisterClass);
+ return Pair(0U, VT == MVT::i16 ? D16RegisterClass : DPRegisterClass);
// Blackfin-specific constraints
case 'a': return Pair(0U, PRegisterClass);
diff --git a/lib/Target/Blackfin/BlackfinISelLowering.h b/lib/Target/Blackfin/BlackfinISelLowering.h
index 1cbb98d1cc4942be96358e81428ab6d83c9b6e2d..be0c0ec216530c4b817ce2762aa9b21ccfa8feb6 100644 (file)
int VarArgsFrameOffset; // Frame offset to start of varargs area.
public:
BlackfinTargetLowering(TargetMachine &TM);
- virtual EVT::SimpleValueType getSetCCResultType(EVT VT) const;
+ virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const;
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
virtual void ReplaceNodeResults(SDNode *N,
SmallVectorImpl<SDValue> &Results,
index 6fc34a8c66979302b5203c8c8103c20865b92e67..b0a2cc13c4cb72a61c9050dfa262ca7d76c8d0d4 100644 (file)
def trailingZeros_xform : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(N->getAPIntValue().countTrailingZeros(),
- EVT::i32);
+ MVT::i32);
}]>;
def trailingOnes_xform : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(N->getAPIntValue().countTrailingOnes(),
- EVT::i32);
+ MVT::i32);
}]>;
def LO16 : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant((unsigned short)N->getZExtValue(), EVT::i16);
+ return CurDAG->getTargetConstant((unsigned short)N->getZExtValue(), MVT::i16);
}]>;
def HI16 : SDNodeXForm<imm, [{
// Transformation function: shift the immediate value down into the low bits.
- return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 16, EVT::i16);
+ return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 16, MVT::i16);
}]>;
//===----------------------------------------------------------------------===//
diff --git a/lib/Target/Blackfin/BlackfinRegisterInfo.cpp b/lib/Target/Blackfin/BlackfinRegisterInfo.cpp
index b8fc6acf828478692861052be0163cd3ee12134f..1b3dfece7a73e47fe42420047642eee51b3db292 100644 (file)
for (regclass_iterator I = regclass_begin(), E = regclass_end();
I != E; ++I) {
const TargetRegisterClass* RC = *I;
- if ((VT == EVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
+ if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
(!BestRC || RC->getNumRegs() < BestRC->getNumRegs()))
BestRC = RC;
}
index dd7009f2005c5d61a127f93237b88c59dc4d85c8..9ae67223db7cb0152280e55b917fa0a8154b52ee 100644 (file)
{
EVT vt = CN->getValueType(0);
Imm = (short) CN->getZExtValue();
- if (vt.getSimpleVT() >= EVT::i1 && vt.getSimpleVT() <= EVT::i16) {
+ if (vt.getSimpleVT() >= MVT::i1 && vt.getSimpleVT() <= MVT::i16) {
return true;
- } else if (vt == EVT::i32) {
+ } else if (vt == MVT::i32) {
int32_t i_val = (int32_t) CN->getZExtValue();
short s_val = (short) i_val;
return i_val == s_val;
isFPS16Immediate(ConstantFPSDNode *FPN, short &Imm)
{
EVT vt = FPN->getValueType(0);
- if (vt == EVT::f32) {
+ if (vt == MVT::f32) {
int val = FloatToBits(FPN->getValueAPF().convertToFloat());
int sval = (int) ((val << 16) >> 16);
Imm = (short) val;
};
const valtype_map_s valtype_map[] = {
- { EVT::i8, SPU::ORBIr8, true, SPU::LRr8 },
- { EVT::i16, SPU::ORHIr16, true, SPU::LRr16 },
- { EVT::i32, SPU::ORIr32, true, SPU::LRr32 },
- { EVT::i64, SPU::ORr64, false, SPU::LRr64 },
- { EVT::f32, SPU::ORf32, false, SPU::LRf32 },
- { EVT::f64, SPU::ORf64, false, SPU::LRf64 },
+ { MVT::i8, SPU::ORBIr8, true, SPU::LRr8 },
+ { MVT::i16, SPU::ORHIr16, true, SPU::LRr16 },
+ { MVT::i32, SPU::ORIr32, true, SPU::LRr32 },
+ { MVT::i64, SPU::ORr64, false, SPU::LRr64 },
+ { MVT::f32, SPU::ORf32, false, SPU::LRf32 },
+ { MVT::f64, SPU::ORf64, false, SPU::LRf64 },
// vector types... (sigh!)
- { EVT::v16i8, 0, false, SPU::LRv16i8 },
- { EVT::v8i16, 0, false, SPU::LRv8i16 },
- { EVT::v4i32, 0, false, SPU::LRv4i32 },
- { EVT::v2i64, 0, false, SPU::LRv2i64 },
- { EVT::v4f32, 0, false, SPU::LRv4f32 },
- { EVT::v2f64, 0, false, SPU::LRv2f64 }
+ { MVT::v16i8, 0, false, SPU::LRv16i8 },
+ { MVT::v8i16, 0, false, SPU::LRv8i16 },
+ { MVT::v4i32, 0, false, SPU::LRv4i32 },
+ { MVT::v2i64, 0, false, SPU::LRv2i64 },
+ { MVT::v4f32, 0, false, SPU::LRv4f32 },
+ { MVT::v2f64, 0, false, SPU::LRv2f64 }
};
const size_t n_valtype_map = sizeof(valtype_map) / sizeof(valtype_map[0]);
// Create the shuffle mask for "rotating" the borrow up one register slot
// once the borrow is generated.
- ShufBytes.push_back(DAG.getConstant(0x04050607, EVT::i32));
- ShufBytes.push_back(DAG.getConstant(0x80808080, EVT::i32));
- ShufBytes.push_back(DAG.getConstant(0x0c0d0e0f, EVT::i32));
- ShufBytes.push_back(DAG.getConstant(0x80808080, EVT::i32));
+ ShufBytes.push_back(DAG.getConstant(0x04050607, MVT::i32));
+ ShufBytes.push_back(DAG.getConstant(0x80808080, MVT::i32));
+ ShufBytes.push_back(DAG.getConstant(0x0c0d0e0f, MVT::i32));
+ ShufBytes.push_back(DAG.getConstant(0x80808080, MVT::i32));
- return DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32,
+ return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
&ShufBytes[0], ShufBytes.size());
}
// Create the shuffle mask for "rotating" the borrow up one register slot
// once the borrow is generated.
- ShufBytes.push_back(DAG.getConstant(0x04050607, EVT::i32));
- ShufBytes.push_back(DAG.getConstant(0xc0c0c0c0, EVT::i32));
- ShufBytes.push_back(DAG.getConstant(0x0c0d0e0f, EVT::i32));
- ShufBytes.push_back(DAG.getConstant(0xc0c0c0c0, EVT::i32));
+ ShufBytes.push_back(DAG.getConstant(0x04050607, MVT::i32));
+ ShufBytes.push_back(DAG.getConstant(0xc0c0c0c0, MVT::i32));
+ ShufBytes.push_back(DAG.getConstant(0x0c0d0e0f, MVT::i32));
+ ShufBytes.push_back(DAG.getConstant(0xc0c0c0c0, MVT::i32));
- return DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32,
+ return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
&ShufBytes[0], ShufBytes.size());
}
/// getI32Imm - Return a target constant with the specified value, of type
/// i32.
inline SDValue getI32Imm(uint32_t Imm) {
- return CurDAG->getTargetConstant(Imm, EVT::i32);
+ return CurDAG->getTargetConstant(Imm, MVT::i32);
}
/// getI64Imm - Return a target constant with the specified value, of type
/// i64.
inline SDValue getI64Imm(uint64_t Imm) {
- return CurDAG->getTargetConstant(Imm, EVT::i64);
+ return CurDAG->getTargetConstant(Imm, MVT::i64);
}
/// getSmallIPtrImm - Return a target constant of pointer type.
// Check to see if this vector can be represented as a CellSPU immediate
// constant by invoking all of the instruction selection predicates:
- if (((vecVT == EVT::v8i16) &&
- (SPU::get_vec_i16imm(bvNode, *CurDAG, EVT::i16).getNode() != 0)) ||
- ((vecVT == EVT::v4i32) &&
- ((SPU::get_vec_i16imm(bvNode, *CurDAG, EVT::i32).getNode() != 0) ||
- (SPU::get_ILHUvec_imm(bvNode, *CurDAG, EVT::i32).getNode() != 0) ||
- (SPU::get_vec_u18imm(bvNode, *CurDAG, EVT::i32).getNode() != 0) ||
+ if (((vecVT == MVT::v8i16) &&
+ (SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i16).getNode() != 0)) ||
+ ((vecVT == MVT::v4i32) &&
+ ((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
+ (SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
+ (SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
(SPU::get_v4i32_imm(bvNode, *CurDAG).getNode() != 0))) ||
- ((vecVT == EVT::v2i64) &&
- ((SPU::get_vec_i16imm(bvNode, *CurDAG, EVT::i64).getNode() != 0) ||
- (SPU::get_ILHUvec_imm(bvNode, *CurDAG, EVT::i64).getNode() != 0) ||
- (SPU::get_vec_u18imm(bvNode, *CurDAG, EVT::i64).getNode() != 0))))
+ ((vecVT == MVT::v2i64) &&
+ ((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i64).getNode() != 0) ||
+ (SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i64).getNode() != 0) ||
+ (SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i64).getNode() != 0))))
return Select(build_vec);
// No, need to emit a constant pool spill:
SPUDAGToDAGISel::SelectAFormAddr(SDValue Op, SDValue N, SDValue &Base,
SDValue &Index) {
// These match the addr256k operand type:
- EVT OffsVT = EVT::i16;
+ EVT OffsVT = MVT::i16;
SDValue Zero = CurDAG->getTargetConstant(0, OffsVT);
switch (N.getOpcode()) {
TFI, Imm0), 0);
n_ops = 2;
}
- } else if (Opc == ISD::Constant && OpVT == EVT::i64) {
+ } else if (Opc == ISD::Constant && OpVT == MVT::i64) {
// Catch the i64 constants that end up here. Note: The backend doesn't
// attempt to legalize the constant (it's useless because DAGCombiner
// will insert 64-bit constants and we can't stop it).
return SelectI64Constant(Op, OpVT, Op.getDebugLoc());
} else if ((Opc == ISD::ZERO_EXTEND || Opc == ISD::ANY_EXTEND)
- && OpVT == EVT::i64) {
+ && OpVT == MVT::i64) {
SDValue Op0 = Op.getOperand(0);
EVT Op0VT = Op0.getValueType();
EVT Op0VecVT = EVT::getVectorVT(Op0VT, (128 / Op0VT.getSizeInBits()));
EVT OpVecVT = EVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
SDValue shufMask;
- switch (Op0VT.getSimpleVT()) {
+ switch (Op0VT.getSimpleVT().SimpleTy) {
default:
llvm_report_error("CellSPU Select: Unhandled zero/any extend EVT");
/*NOTREACHED*/
- case EVT::i32:
- shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32,
- CurDAG->getConstant(0x80808080, EVT::i32),
- CurDAG->getConstant(0x00010203, EVT::i32),
- CurDAG->getConstant(0x80808080, EVT::i32),
- CurDAG->getConstant(0x08090a0b, EVT::i32));
+ case MVT::i32:
+ shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
+ CurDAG->getConstant(0x80808080, MVT::i32),
+ CurDAG->getConstant(0x00010203, MVT::i32),
+ CurDAG->getConstant(0x80808080, MVT::i32),
+ CurDAG->getConstant(0x08090a0b, MVT::i32));
break;
- case EVT::i16:
- shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32,
- CurDAG->getConstant(0x80808080, EVT::i32),
- CurDAG->getConstant(0x80800203, EVT::i32),
- CurDAG->getConstant(0x80808080, EVT::i32),
- CurDAG->getConstant(0x80800a0b, EVT::i32));
+ case MVT::i16:
+ shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
+ CurDAG->getConstant(0x80808080, MVT::i32),
+ CurDAG->getConstant(0x80800203, MVT::i32),
+ CurDAG->getConstant(0x80808080, MVT::i32),
+ CurDAG->getConstant(0x80800a0b, MVT::i32));
break;
- case EVT::i8:
- shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32,
- CurDAG->getConstant(0x80808080, EVT::i32),
- CurDAG->getConstant(0x80808003, EVT::i32),
- CurDAG->getConstant(0x80808080, EVT::i32),
- CurDAG->getConstant(0x8080800b, EVT::i32));
+ case MVT::i8:
+ shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
+ CurDAG->getConstant(0x80808080, MVT::i32),
+ CurDAG->getConstant(0x80808003, MVT::i32),
+ CurDAG->getConstant(0x80808080, MVT::i32),
+ CurDAG->getConstant(0x8080800b, MVT::i32));
break;
}
SelectCode(CurDAG->getNode(ISD::BIT_CONVERT, dl, OpVecVT, zextShuffle));
return SelectCode(CurDAG->getNode(SPUISD::VEC2PREFSLOT, dl, OpVT,
zextShuffle));
- } else if (Opc == ISD::ADD && (OpVT == EVT::i64 || OpVT == EVT::v2i64)) {
+ } else if (Opc == ISD::ADD && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
SDNode *CGLoad =
emitBuildVector(getCarryGenerateShufMask(*CurDAG, dl));
return SelectCode(CurDAG->getNode(SPUISD::ADD64_MARKER, dl, OpVT,
Op.getOperand(0), Op.getOperand(1),
SDValue(CGLoad, 0)));
- } else if (Opc == ISD::SUB && (OpVT == EVT::i64 || OpVT == EVT::v2i64)) {
+ } else if (Opc == ISD::SUB && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
SDNode *CGLoad =
emitBuildVector(getBorrowGenerateShufMask(*CurDAG, dl));
return SelectCode(CurDAG->getNode(SPUISD::SUB64_MARKER, dl, OpVT,
Op.getOperand(0), Op.getOperand(1),
SDValue(CGLoad, 0)));
- } else if (Opc == ISD::MUL && (OpVT == EVT::i64 || OpVT == EVT::v2i64)) {
+ } else if (Opc == ISD::MUL && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
SDNode *CGLoad =
emitBuildVector(getCarryGenerateShufMask(*CurDAG, dl));
} else if (Opc == ISD::TRUNCATE) {
SDValue Op0 = Op.getOperand(0);
if ((Op0.getOpcode() == ISD::SRA || Op0.getOpcode() == ISD::SRL)
- && OpVT == EVT::i32
- && Op0.getValueType() == EVT::i64) {
+ && OpVT == MVT::i32
+ && Op0.getValueType() == MVT::i64) {
// Catch (truncate:i32 ([sra|srl]:i64 arg, c), where c >= 32
//
// Take advantage of the fact that the upper 32 bits are in the
shift_amt -= 32;
if (shift_amt > 0) {
// Take care of the additional shift, if present:
- SDValue shift = CurDAG->getTargetConstant(shift_amt, EVT::i32);
+ SDValue shift = CurDAG->getTargetConstant(shift_amt, MVT::i32);
unsigned Opc = SPU::ROTMAIr32_i32;
if (Op0.getOpcode() == ISD::SRL)
}
}
} else if (Opc == ISD::SHL) {
- if (OpVT == EVT::i64) {
+ if (OpVT == MVT::i64) {
return SelectSHLi64(Op, OpVT);
}
} else if (Opc == ISD::SRL) {
- if (OpVT == EVT::i64) {
+ if (OpVT == MVT::i64) {
return SelectSRLi64(Op, OpVT);
}
} else if (Opc == ISD::SRA) {
- if (OpVT == EVT::i64) {
+ if (OpVT == MVT::i64) {
return SelectSRAi64(Op, OpVT);
}
} else if (Opc == ISD::FNEG
- && (OpVT == EVT::f64 || OpVT == EVT::v2f64)) {
+ && (OpVT == MVT::f64 || OpVT == MVT::v2f64)) {
DebugLoc dl = Op.getDebugLoc();
// Check if the pattern is a special form of DFNMS:
// (fneg (fsub (fmul R64FP:$rA, R64FP:$rB), R64FP:$rC))
SDValue Op00 = Op0.getOperand(0);
if (Op00.getOpcode() == ISD::FMUL) {
unsigned Opc = SPU::DFNMSf64;
- if (OpVT == EVT::v2f64)
+ if (OpVT == MVT::v2f64)
Opc = SPU::DFNMSv2f64;
return CurDAG->getTargetNode(Opc, dl, OpVT,
}
}
- SDValue negConst = CurDAG->getConstant(0x8000000000000000ULL, EVT::i64);
+ SDValue negConst = CurDAG->getConstant(0x8000000000000000ULL, MVT::i64);
SDNode *signMask = 0;
unsigned Opc = SPU::XORfneg64;
- if (OpVT == EVT::f64) {
- signMask = SelectI64Constant(negConst, EVT::i64, dl);
- } else if (OpVT == EVT::v2f64) {
+ if (OpVT == MVT::f64) {
+ signMask = SelectI64Constant(negConst, MVT::i64, dl);
+ } else if (OpVT == MVT::v2f64) {
Opc = SPU::XORfnegvec;
signMask = emitBuildVector(CurDAG->getNode(ISD::BUILD_VECTOR, dl,
- EVT::v2i64,
+ MVT::v2i64,
negConst, negConst));
}
return CurDAG->getTargetNode(Opc, dl, OpVT,
Op.getOperand(0), SDValue(signMask, 0));
} else if (Opc == ISD::FABS) {
- if (OpVT == EVT::f64) {
- SDNode *signMask = SelectI64Constant(0x7fffffffffffffffULL, EVT::i64, dl);
+ if (OpVT == MVT::f64) {
+ SDNode *signMask = SelectI64Constant(0x7fffffffffffffffULL, MVT::i64, dl);
return CurDAG->getTargetNode(SPU::ANDfabs64, dl, OpVT,
Op.getOperand(0), SDValue(signMask, 0));
- } else if (OpVT == EVT::v2f64) {
- SDValue absConst = CurDAG->getConstant(0x7fffffffffffffffULL, EVT::i64);
- SDValue absVec = CurDAG->getNode(ISD::BUILD_VECTOR, dl, EVT::v2i64,
+ } else if (OpVT == MVT::v2f64) {
+ SDValue absConst = CurDAG->getConstant(0x7fffffffffffffffULL, MVT::i64);
+ SDValue absVec = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64,
absConst, absConst);
SDNode *signMask = emitBuildVector(absVec);
return CurDAG->getTargetNode(SPU::ANDfabsvec, dl, OpVT,
if (vtm->ldresult_imm) {
SDValue Zero = CurDAG->getTargetConstant(0, VT);
- Result = CurDAG->getTargetNode(Opc, dl, VT, EVT::Other, Arg, Zero, Chain);
+ Result = CurDAG->getTargetNode(Opc, dl, VT, MVT::Other, Arg, Zero, Chain);
} else {
- Result = CurDAG->getTargetNode(Opc, dl, VT, EVT::Other, Arg, Arg, Chain);
+ Result = CurDAG->getTargetNode(Opc, dl, VT, MVT::Other, Arg, Arg, Chain);
}
return Result;
DebugLoc dl = Op.getDebugLoc();
VecOp0 = CurDAG->getTargetNode(SPU::ORv2i64_i64, dl, VecVT, Op0);
- SelMaskVal = CurDAG->getTargetConstant(0xff00ULL, EVT::i16);
+ SelMaskVal = CurDAG->getTargetConstant(0xff00ULL, MVT::i16);
SelMask = CurDAG->getTargetNode(SPU::FSMBIv2i64, dl, VecVT, SelMaskVal);
ZeroFill = CurDAG->getTargetNode(SPU::ILv2i64, dl, VecVT,
CurDAG->getTargetConstant(0, OpVT));
SDValue SignRotAmt = CurDAG->getTargetConstant(31, ShiftAmtVT);
SDNode *SignRot =
- CurDAG->getTargetNode(SPU::ROTMAIv2i64_i32, dl, EVT::v2i64,
+ CurDAG->getTargetNode(SPU::ROTMAIv2i64_i32, dl, MVT::v2i64,
SDValue(VecOp0, 0), SignRotAmt);
SDNode *UpperHalfSign =
- CurDAG->getTargetNode(SPU::ORi32_v4i32, dl, EVT::i32, SDValue(SignRot, 0));
+ CurDAG->getTargetNode(SPU::ORi32_v4i32, dl, MVT::i32, SDValue(SignRot, 0));
SDNode *UpperHalfSignMask =
CurDAG->getTargetNode(SPU::FSM64r32, dl, VecVT, SDValue(UpperHalfSign, 0));
SDNode *UpperLowerMask =
CurDAG->getTargetNode(SPU::FSMBIv2i64, dl, VecVT,
- CurDAG->getTargetConstant(0xff00ULL, EVT::i16));
+ CurDAG->getTargetConstant(0xff00ULL, MVT::i16));
SDNode *UpperLowerSelect =
CurDAG->getTargetNode(SPU::SELBv2i64, dl, VecVT,
SDValue(UpperHalfSignMask, 0),
index 5c80324011c7aaf5f887c831e9ad368297c7422d..04a0eec9eb5ffda921d8a9efda389b36d95cfaad 100644 (file)
};
const valtype_map_s valtype_map[] = {
- { EVT::i1, 3 },
- { EVT::i8, 3 },
- { EVT::i16, 2 },
- { EVT::i32, 0 },
- { EVT::f32, 0 },
- { EVT::i64, 0 },
- { EVT::f64, 0 },
- { EVT::i128, 0 }
+ { MVT::i1, 3 },
+ { MVT::i8, 3 },
+ { MVT::i16, 2 },
+ { MVT::i32, 0 },
+ { MVT::f32, 0 },
+ { MVT::i64, 0 },
+ { MVT::f64, 0 },
+ { MVT::i128, 0 }
};
const size_t n_valtype_map = sizeof(valtype_map) / sizeof(valtype_map[0]);
setLibcallName(RTLIB::DIV_F64, "__fast_divdf3");
// Set up the SPU's register classes:
- addRegisterClass(EVT::i8, SPU::R8CRegisterClass);
- addRegisterClass(EVT::i16, SPU::R16CRegisterClass);
- addRegisterClass(EVT::i32, SPU::R32CRegisterClass);
- addRegisterClass(EVT::i64, SPU::R64CRegisterClass);
- addRegisterClass(EVT::f32, SPU::R32FPRegisterClass);
- addRegisterClass(EVT::f64, SPU::R64FPRegisterClass);
- addRegisterClass(EVT::i128, SPU::GPRCRegisterClass);
+ addRegisterClass(MVT::i8, SPU::R8CRegisterClass);
+ addRegisterClass(MVT::i16, SPU::R16CRegisterClass);
+ addRegisterClass(MVT::i32, SPU::R32CRegisterClass);
+ addRegisterClass(MVT::i64, SPU::R64CRegisterClass);
+ addRegisterClass(MVT::f32, SPU::R32FPRegisterClass);
+ addRegisterClass(MVT::f64, SPU::R64FPRegisterClass);
+ addRegisterClass(MVT::i128, SPU::GPRCRegisterClass);
// SPU has no sign or zero extended loads for i1, i8, i16:
- setLoadExtAction(ISD::EXTLOAD, EVT::i1, Promote);
- setLoadExtAction(ISD::SEXTLOAD, EVT::i1, Promote);
- setLoadExtAction(ISD::ZEXTLOAD, EVT::i1, Promote);
+ setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
+ setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
+ setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
- setLoadExtAction(ISD::EXTLOAD, EVT::f32, Expand);
- setLoadExtAction(ISD::EXTLOAD, EVT::f64, Expand);
+ setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
+ setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
- setTruncStoreAction(EVT::i128, EVT::i64, Expand);
- setTruncStoreAction(EVT::i128, EVT::i32, Expand);
- setTruncStoreAction(EVT::i128, EVT::i16, Expand);
- setTruncStoreAction(EVT::i128, EVT::i8, Expand);
+ setTruncStoreAction(MVT::i128, MVT::i64, Expand);
+ setTruncStoreAction(MVT::i128, MVT::i32, Expand);
+ setTruncStoreAction(MVT::i128, MVT::i16, Expand);
+ setTruncStoreAction(MVT::i128, MVT::i8, Expand);
- setTruncStoreAction(EVT::f64, EVT::f32, Expand);
+ setTruncStoreAction(MVT::f64, MVT::f32, Expand);
// SPU constant load actions are custom lowered:
- setOperationAction(ISD::ConstantFP, EVT::f32, Legal);
- setOperationAction(ISD::ConstantFP, EVT::f64, Custom);
+ setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
+ setOperationAction(ISD::ConstantFP, MVT::f64, Custom);
// SPU's loads and stores have to be custom lowered:
- for (unsigned sctype = (unsigned) EVT::i8; sctype < (unsigned) EVT::i128;
+ for (unsigned sctype = (unsigned) MVT::i8; sctype < (unsigned) MVT::i128;
++sctype) {
- EVT::SimpleValueType VT = (EVT::SimpleValueType)sctype;
+ MVT::SimpleValueType VT = (MVT::SimpleValueType)sctype;
setOperationAction(ISD::LOAD, VT, Custom);
setOperationAction(ISD::STORE, VT, Custom);
setLoadExtAction(ISD::ZEXTLOAD, VT, Custom);
setLoadExtAction(ISD::SEXTLOAD, VT, Custom);
- for (unsigned stype = sctype - 1; stype >= (unsigned) EVT::i8; --stype) {
- EVT::SimpleValueType StoreVT = (EVT::SimpleValueType) stype;
+ for (unsigned stype = sctype - 1; stype >= (unsigned) MVT::i8; --stype) {
+ MVT::SimpleValueType StoreVT = (MVT::SimpleValueType) stype;
setTruncStoreAction(VT, StoreVT, Expand);
}
}
- for (unsigned sctype = (unsigned) EVT::f32; sctype < (unsigned) EVT::f64;
+ for (unsigned sctype = (unsigned) MVT::f32; sctype < (unsigned) MVT::f64;
++sctype) {
- EVT::SimpleValueType VT = (EVT::SimpleValueType) sctype;
+ MVT::SimpleValueType VT = (MVT::SimpleValueType) sctype;
setOperationAction(ISD::LOAD, VT, Custom);
setOperationAction(ISD::STORE, VT, Custom);
- for (unsigned stype = sctype - 1; stype >= (unsigned) EVT::f32; --stype) {
- EVT::SimpleValueType StoreVT = (EVT::SimpleValueType) stype;
+ for (unsigned stype = sctype - 1; stype >= (unsigned) MVT::f32; --stype) {
+ MVT::SimpleValueType StoreVT = (MVT::SimpleValueType) stype;
setTruncStoreAction(VT, StoreVT, Expand);
}
}
// Expand the jumptable branches
- setOperationAction(ISD::BR_JT, EVT::Other, Expand);
- setOperationAction(ISD::BR_CC, EVT::Other, Expand);
+ setOperationAction(ISD::BR_JT, MVT::Other, Expand);
+ setOperationAction(ISD::BR_CC, MVT::Other, Expand);
// Custom lower SELECT_CC for most cases, but expand by default
- setOperationAction(ISD::SELECT_CC, EVT::Other, Expand);
- setOperationAction(ISD::SELECT_CC, EVT::i8, Custom);
- setOperationAction(ISD::SELECT_CC, EVT::i16, Custom);
- setOperationAction(ISD::SELECT_CC, EVT::i32, Custom);
- setOperationAction(ISD::SELECT_CC, EVT::i64, Custom);
+ setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
+ setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
+ setOperationAction(ISD::SELECT_CC, MVT::i16, Custom);
+ setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
+ setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
// SPU has no intrinsics for these particular operations:
- setOperationAction(ISD::MEMBARRIER, EVT::Other, Expand);
+ setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
// SPU has no division/remainder instructions
- setOperationAction(ISD::SREM, EVT::i8, Expand);
- setOperationAction(ISD::UREM, EVT::i8, Expand);
- setOperationAction(ISD::SDIV, EVT::i8, Expand);
- setOperationAction(ISD::UDIV, EVT::i8, Expand);
- setOperationAction(ISD::SDIVREM, EVT::i8, Expand);
- setOperationAction(ISD::UDIVREM, EVT::i8, Expand);
- setOperationAction(ISD::SREM, EVT::i16, Expand);
- setOperationAction(ISD::UREM, EVT::i16, Expand);
- setOperationAction(ISD::SDIV, EVT::i16, Expand);
- setOperationAction(ISD::UDIV, EVT::i16, Expand);
- setOperationAction(ISD::SDIVREM, EVT::i16, Expand);
- setOperationAction(ISD::UDIVREM, EVT::i16, Expand);
- setOperationAction(ISD::SREM, EVT::i32, Expand);
- setOperationAction(ISD::UREM, EVT::i32, Expand);
- setOperationAction(ISD::SDIV, EVT::i32, Expand);
- setOperationAction(ISD::UDIV, EVT::i32, Expand);
- setOperationAction(ISD::SDIVREM, EVT::i32, Expand);
- setOperationAction(ISD::UDIVREM, EVT::i32, Expand);
- setOperationAction(ISD::SREM, EVT::i64, Expand);
- setOperationAction(ISD::UREM, EVT::i64, Expand);
- setOperationAction(ISD::SDIV, EVT::i64, Expand);
- setOperationAction(ISD::UDIV, EVT::i64, Expand);
- setOperationAction(ISD::SDIVREM, EVT::i64, Expand);
- setOperationAction(ISD::UDIVREM, EVT::i64, Expand);
- setOperationAction(ISD::SREM, EVT::i128, Expand);
- setOperationAction(ISD::UREM, EVT::i128, Expand);
- setOperationAction(ISD::SDIV, EVT::i128, Expand);
- setOperationAction(ISD::UDIV, EVT::i128, Expand);
- setOperationAction(ISD::SDIVREM, EVT::i128, Expand);
- setOperationAction(ISD::UDIVREM, EVT::i128, Expand);
+ setOperationAction(ISD::SREM, MVT::i8, Expand);
+ setOperationAction(ISD::UREM, MVT::i8, Expand);
+ setOperationAction(ISD::SDIV, MVT::i8, Expand);
+ setOperationAction(ISD::UDIV, MVT::i8, Expand);
+ setOperationAction(ISD::SDIVREM, MVT::i8, Expand);
+ setOperationAction(ISD::UDIVREM, MVT::i8, Expand);
+ setOperationAction(ISD::SREM, MVT::i16, Expand);
+ setOperationAction(ISD::UREM, MVT::i16, Expand);
+ setOperationAction(ISD::SDIV, MVT::i16, Expand);
+ setOperationAction(ISD::UDIV, MVT::i16, Expand);
+ setOperationAction(ISD::SDIVREM, MVT::i16, Expand);
+ setOperationAction(ISD::UDIVREM, MVT::i16, Expand);
+ setOperationAction(ISD::SREM, MVT::i32, Expand);
+ setOperationAction(ISD::UREM, MVT::i32, Expand);
+ setOperationAction(ISD::SDIV, MVT::i32, Expand);
+ setOperationAction(ISD::UDIV, MVT::i32, Expand);
+ setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
+ setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
+ setOperationAction(ISD::SREM, MVT::i64, Expand);
+ setOperationAction(ISD::UREM, MVT::i64, Expand);
+ setOperationAction(ISD::SDIV, MVT::i64, Expand);
+ setOperationAction(ISD::UDIV, MVT::i64, Expand);
+ setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
+ setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
+ setOperationAction(ISD::SREM, MVT::i128, Expand);
+ setOperationAction(ISD::UREM, MVT::i128, Expand);
+ setOperationAction(ISD::SDIV, MVT::i128, Expand);
+ setOperationAction(ISD::UDIV, MVT::i128, Expand);
+ setOperationAction(ISD::SDIVREM, MVT::i128, Expand);
+ setOperationAction(ISD::UDIVREM, MVT::i128, Expand);
// We don't support sin/cos/sqrt/fmod
- setOperationAction(ISD::FSIN , EVT::f64, Expand);
- setOperationAction(ISD::FCOS , EVT::f64, Expand);
- setOperationAction(ISD::FREM , EVT::f64, Expand);
- setOperationAction(ISD::FSIN , EVT::f32, Expand);
- setOperationAction(ISD::FCOS , EVT::f32, Expand);
- setOperationAction(ISD::FREM , EVT::f32, Expand);
+ setOperationAction(ISD::FSIN , MVT::f64, Expand);
+ setOperationAction(ISD::FCOS , MVT::f64, Expand);
+ setOperationAction(ISD::FREM , MVT::f64, Expand);
+ setOperationAction(ISD::FSIN , MVT::f32, Expand);
+ setOperationAction(ISD::FCOS , MVT::f32, Expand);
+ setOperationAction(ISD::FREM , MVT::f32, Expand);
// Expand fsqrt to the appropriate libcall (NOTE: should use h/w fsqrt
// for f32!)
- setOperationAction(ISD::FSQRT, EVT::f64, Expand);
- setOperationAction(ISD::FSQRT, EVT::f32, Expand);
+ setOperationAction(ISD::FSQRT, MVT::f64, Expand);
+ setOperationAction(ISD::FSQRT, MVT::f32, Expand);
- setOperationAction(ISD::FCOPYSIGN, EVT::f64, Expand);
- setOperationAction(ISD::FCOPYSIGN, EVT::f32, Expand);
+ setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
+ setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
// SPU can do rotate right and left, so legalize it... but customize for i8
// because instructions don't exist.
// FIXME: Change from "expand" to appropriate type once ROTR is supported in
// .td files.
- setOperationAction(ISD::ROTR, EVT::i32, Expand /*Legal*/);
- setOperationAction(ISD::ROTR, EVT::i16, Expand /*Legal*/);
- setOperationAction(ISD::ROTR, EVT::i8, Expand /*Custom*/);
+ setOperationAction(ISD::ROTR, MVT::i32, Expand /*Legal*/);
+ setOperationAction(ISD::ROTR, MVT::i16, Expand /*Legal*/);
+ setOperationAction(ISD::ROTR, MVT::i8, Expand /*Custom*/);
- setOperationAction(ISD::ROTL, EVT::i32, Legal);
- setOperationAction(ISD::ROTL, EVT::i16, Legal);
- setOperationAction(ISD::ROTL, EVT::i8, Custom);
+ setOperationAction(ISD::ROTL, MVT::i32, Legal);
+ setOperationAction(ISD::ROTL, MVT::i16, Legal);
+ setOperationAction(ISD::ROTL, MVT::i8, Custom);
// SPU has no native version of shift left/right for i8
- setOperationAction(ISD::SHL, EVT::i8, Custom);
- setOperationAction(ISD::SRL, EVT::i8, Custom);
- setOperationAction(ISD::SRA, EVT::i8, Custom);
+ setOperationAction(ISD::SHL, MVT::i8, Custom);
+ setOperationAction(ISD::SRL, MVT::i8, Custom);
+ setOperationAction(ISD::SRA, MVT::i8, Custom);
// Make these operations legal and handle them during instruction selection:
- setOperationAction(ISD::SHL, EVT::i64, Legal);
- setOperationAction(ISD::SRL, EVT::i64, Legal);
- setOperationAction(ISD::SRA, EVT::i64, Legal);
+ setOperationAction(ISD::SHL, MVT::i64, Legal);
+ setOperationAction(ISD::SRL, MVT::i64, Legal);
+ setOperationAction(ISD::SRA, MVT::i64, Legal);
// Custom lower i8, i32 and i64 multiplications
- setOperationAction(ISD::MUL, EVT::i8, Custom);
- setOperationAction(ISD::MUL, EVT::i32, Legal);
- setOperationAction(ISD::MUL, EVT::i64, Legal);
+ setOperationAction(ISD::MUL, MVT::i8, Custom);
+ setOperationAction(ISD::MUL, MVT::i32, Legal);
+ setOperationAction(ISD::MUL, MVT::i64, Legal);
// Expand double-width multiplication
// FIXME: It would probably be reasonable to support some of these operations
- setOperationAction(ISD::UMUL_LOHI, EVT::i8, Expand);
- setOperationAction(ISD::SMUL_LOHI, EVT::i8, Expand);
- setOperationAction(ISD::MULHU, EVT::i8, Expand);
- setOperationAction(ISD::MULHS, EVT::i8, Expand);
- setOperationAction(ISD::UMUL_LOHI, EVT::i16, Expand);
- setOperationAction(ISD::SMUL_LOHI, EVT::i16, Expand);
- setOperationAction(ISD::MULHU, EVT::i16, Expand);
- setOperationAction(ISD::MULHS, EVT::i16, Expand);
- setOperationAction(ISD::UMUL_LOHI, EVT::i32, Expand);
- setOperationAction(ISD::SMUL_LOHI, EVT::i32, Expand);
- setOperationAction(ISD::MULHU, EVT::i32, Expand);
- setOperationAction(ISD::MULHS, EVT::i32, Expand);
- setOperationAction(ISD::UMUL_LOHI, EVT::i64, Expand);
- setOperationAction(ISD::SMUL_LOHI, EVT::i64, Expand);
- setOperationAction(ISD::MULHU, EVT::i64, Expand);
- setOperationAction(ISD::MULHS, EVT::i64, Expand);
+ setOperationAction(ISD::UMUL_LOHI, MVT::i8, Expand);
+ setOperationAction(ISD::SMUL_LOHI, MVT::i8, Expand);
+ setOperationAction(ISD::MULHU, MVT::i8, Expand);
+ setOperationAction(ISD::MULHS, MVT::i8, Expand);
+ setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand);
+ setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand);
+ setOperationAction(ISD::MULHU, MVT::i16, Expand);
+ setOperationAction(ISD::MULHS, MVT::i16, Expand);
+ setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
+ setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
+ setOperationAction(ISD::MULHU, MVT::i32, Expand);
+ setOperationAction(ISD::MULHS, MVT::i32, Expand);
+ setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
+ setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
+ setOperationAction(ISD::MULHU, MVT::i64, Expand);
+ setOperationAction(ISD::MULHS, MVT::i64, Expand);
// Need to custom handle (some) common i8, i64 math ops
- setOperationAction(ISD::ADD, EVT::i8, Custom);
- setOperationAction(ISD::ADD, EVT::i64, Legal);
- setOperationAction(ISD::SUB, EVT::i8, Custom);
- setOperationAction(ISD::SUB, EVT::i64, Legal);
+ setOperationAction(ISD::ADD, MVT::i8, Custom);
+ setOperationAction(ISD::ADD, MVT::i64, Legal);
+ setOperationAction(ISD::SUB, MVT::i8, Custom);
+ setOperationAction(ISD::SUB, MVT::i64, Legal);
// SPU does not have BSWAP. It does have i32 support CTLZ.
// CTPOP has to be custom lowered.
- setOperationAction(ISD::BSWAP, EVT::i32, Expand);
- setOperationAction(ISD::BSWAP, EVT::i64, Expand);
-
- setOperationAction(ISD::CTPOP, EVT::i8, Custom);
- setOperationAction(ISD::CTPOP, EVT::i16, Custom);
- setOperationAction(ISD::CTPOP, EVT::i32, Custom);
- setOperationAction(ISD::CTPOP, EVT::i64, Custom);
- setOperationAction(ISD::CTPOP, EVT::i128, Expand);
-
- setOperationAction(ISD::CTTZ , EVT::i8, Expand);
- setOperationAction(ISD::CTTZ , EVT::i16, Expand);
- setOperationAction(ISD::CTTZ , EVT::i32, Expand);
- setOperationAction(ISD::CTTZ , EVT::i64, Expand);
- setOperationAction(ISD::CTTZ , EVT::i128, Expand);
-
- setOperationAction(ISD::CTLZ , EVT::i8, Promote);
- setOperationAction(ISD::CTLZ , EVT::i16, Promote);
- setOperationAction(ISD::CTLZ , EVT::i32, Legal);
- setOperationAction(ISD::CTLZ , EVT::i64, Expand);
- setOperationAction(ISD::CTLZ , EVT::i128, Expand);
+ setOperationAction(ISD::BSWAP, MVT::i32, Expand);
+ setOperationAction(ISD::BSWAP, MVT::i64, Expand);
+
+ setOperationAction(ISD::CTPOP, MVT::i8, Custom);
+ setOperationAction(ISD::CTPOP, MVT::i16, Custom);
+ setOperationAction(ISD::CTPOP, MVT::i32, Custom);
+ setOperationAction(ISD::CTPOP, MVT::i64, Custom);
+ setOperationAction(ISD::CTPOP, MVT::i128, Expand);
+
+ setOperationAction(ISD::CTTZ , MVT::i8, Expand);
+ setOperationAction(ISD::CTTZ , MVT::i16, Expand);
+ setOperationAction(ISD::CTTZ , MVT::i32, Expand);
+ setOperationAction(ISD::CTTZ , MVT::i64, Expand);
+ setOperationAction(ISD::CTTZ , MVT::i128, Expand);
+
+ setOperationAction(ISD::CTLZ , MVT::i8, Promote);
+ setOperationAction(ISD::CTLZ , MVT::i16, Promote);
+ setOperationAction(ISD::CTLZ , MVT::i32, Legal);
+ setOperationAction(ISD::CTLZ , MVT::i64, Expand);
+ setOperationAction(ISD::CTLZ , MVT::i128, Expand);
// SPU has a version of select that implements (a&~c)|(b&c), just like
// select ought to work:
- setOperationAction(ISD::SELECT, EVT::i8, Legal);
- setOperationAction(ISD::SELECT, EVT::i16, Legal);
- setOperationAction(ISD::SELECT, EVT::i32, Legal);
- setOperationAction(ISD::SELECT, EVT::i64, Legal);
+ setOperationAction(ISD::SELECT, MVT::i8, Legal);
+ setOperationAction(ISD::SELECT, MVT::i16, Legal);
+ setOperationAction(ISD::SELECT, MVT::i32, Legal);
+ setOperationAction(ISD::SELECT, MVT::i64, Legal);
- setOperationAction(ISD::SETCC, EVT::i8, Legal);
- setOperationAction(ISD::SETCC, EVT::i16, Legal);
- setOperationAction(ISD::SETCC, EVT::i32, Legal);
- setOperationAction(ISD::SETCC, EVT::i64, Legal);
- setOperationAction(ISD::SETCC, EVT::f64, Custom);
+ setOperationAction(ISD::SETCC, MVT::i8, Legal);
+ setOperationAction(ISD::SETCC, MVT::i16, Legal);
+ setOperationAction(ISD::SETCC, MVT::i32, Legal);
+ setOperationAction(ISD::SETCC, MVT::i64, Legal);
+ setOperationAction(ISD::SETCC, MVT::f64, Custom);
// Custom lower i128 -> i64 truncates
- setOperationAction(ISD::TRUNCATE, EVT::i64, Custom);
+ setOperationAction(ISD::TRUNCATE, MVT::i64, Custom);
- setOperationAction(ISD::FP_TO_SINT, EVT::i8, Promote);
- setOperationAction(ISD::FP_TO_UINT, EVT::i8, Promote);
- setOperationAction(ISD::FP_TO_SINT, EVT::i16, Promote);
- setOperationAction(ISD::FP_TO_UINT, EVT::i16, Promote);
+ setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote);
+ setOperationAction(ISD::FP_TO_UINT, MVT::i8, Promote);
+ setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
+ setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote);
// SPU has a legal FP -> signed INT instruction for f32, but for f64, need
// to expand to a libcall, hence the custom lowering:
- setOperationAction(ISD::FP_TO_SINT, EVT::i32, Custom);
- setOperationAction(ISD::FP_TO_UINT, EVT::i32, Custom);
- setOperationAction(ISD::FP_TO_SINT, EVT::i64, Expand);
- setOperationAction(ISD::FP_TO_UINT, EVT::i64, Expand);
- setOperationAction(ISD::FP_TO_SINT, EVT::i128, Expand);
- setOperationAction(ISD::FP_TO_UINT, EVT::i128, Expand);
+ setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
+ setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
+ setOperationAction(ISD::FP_TO_SINT, MVT::i64, Expand);
+ setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
+ setOperationAction(ISD::FP_TO_SINT, MVT::i128, Expand);
+ setOperationAction(ISD::FP_TO_UINT, MVT::i128, Expand);
// FDIV on SPU requires custom lowering
- setOperationAction(ISD::FDIV, EVT::f64, Expand); // to libcall
+ setOperationAction(ISD::FDIV, MVT::f64, Expand); // to libcall
// SPU has [U|S]INT_TO_FP for f32->i32, but not for f64->i32, f64->i64:
- setOperationAction(ISD::SINT_TO_FP, EVT::i32, Custom);
- setOperationAction(ISD::SINT_TO_FP, EVT::i16, Promote);
- setOperationAction(ISD::SINT_TO_FP, EVT::i8, Promote);
- setOperationAction(ISD::UINT_TO_FP, EVT::i32, Custom);
- setOperationAction(ISD::UINT_TO_FP, EVT::i16, Promote);
- setOperationAction(ISD::UINT_TO_FP, EVT::i8, Promote);
- setOperationAction(ISD::SINT_TO_FP, EVT::i64, Custom);
- setOperationAction(ISD::UINT_TO_FP, EVT::i64, Custom);
-
- setOperationAction(ISD::BIT_CONVERT, EVT::i32, Legal);
- setOperationAction(ISD::BIT_CONVERT, EVT::f32, Legal);
- setOperationAction(ISD::BIT_CONVERT, EVT::i64, Legal);
- setOperationAction(ISD::BIT_CONVERT, EVT::f64, Legal);
+ setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
+ setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote);
+ setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote);
+ setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
+ setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote);
+ setOperationAction(ISD::UINT_TO_FP, MVT::i8, Promote);
+ setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
+ setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
+
+ setOperationAction(ISD::BIT_CONVERT, MVT::i32, Legal);
+ setOperationAction(ISD::BIT_CONVERT, MVT::f32, Legal);
+ setOperationAction(ISD::BIT_CONVERT, MVT::i64, Legal);
+ setOperationAction(ISD::BIT_CONVERT, MVT::f64, Legal);
// We cannot sextinreg(i1). Expand to shifts.
- setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i1, Expand);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
// Support label based line numbers.
- setOperationAction(ISD::DBG_STOPPOINT, EVT::Other, Expand);
- setOperationAction(ISD::DEBUG_LOC, EVT::Other, Expand);
+ setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
+ setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
// We want to legalize GlobalAddress and ConstantPool nodes into the
// appropriate instructions to materialize the address.
- for (unsigned sctype = (unsigned) EVT::i8; sctype < (unsigned) EVT::f128;
+ for (unsigned sctype = (unsigned) MVT::i8; sctype < (unsigned) MVT::f128;
++sctype) {
- EVT::SimpleValueType VT = (EVT::SimpleValueType)sctype;
+ MVT::SimpleValueType VT = (MVT::SimpleValueType)sctype;
setOperationAction(ISD::GlobalAddress, VT, Custom);
setOperationAction(ISD::ConstantPool, VT, Custom);
}
// VASTART needs to be custom lowered to use the VarArgsFrameIndex
- setOperationAction(ISD::VASTART , EVT::Other, Custom);
+ setOperationAction(ISD::VASTART , MVT::Other, Custom);
// Use the default implementation.
- setOperationAction(ISD::VAARG , EVT::Other, Expand);
- setOperationAction(ISD::VACOPY , EVT::Other, Expand);
- setOperationAction(ISD::VAEND , EVT::Other, Expand);
- setOperationAction(ISD::STACKSAVE , EVT::Other, Expand);
- setOperationAction(ISD::STACKRESTORE , EVT::Other, Expand);
- setOperationAction(ISD::DYNAMIC_STACKALLOC, EVT::i32 , Expand);
- setOperationAction(ISD::DYNAMIC_STACKALLOC, EVT::i64 , Expand);
+ setOperationAction(ISD::VAARG , MVT::Other, Expand);
+ setOperationAction(ISD::VACOPY , MVT::Other, Expand);
+ setOperationAction(ISD::VAEND , MVT::Other, Expand);
+ setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
+ setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
+ setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
+ setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Expand);
// Cell SPU has instructions for converting between i64 and fp.
- setOperationAction(ISD::FP_TO_SINT, EVT::i64, Custom);
- setOperationAction(ISD::SINT_TO_FP, EVT::i64, Custom);
+ setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
+ setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
// To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
- setOperationAction(ISD::FP_TO_UINT, EVT::i32, Promote);
+ setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote);
// BUILD_PAIR can't be handled natively, and should be expanded to shl/or
- setOperationAction(ISD::BUILD_PAIR, EVT::i64, Expand);
+ setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
// First set operation action for all vector types to expand. Then we
// will selectively turn on ones that can be effectively codegen'd.
- addRegisterClass(EVT::v16i8, SPU::VECREGRegisterClass);
- addRegisterClass(EVT::v8i16, SPU::VECREGRegisterClass);
- addRegisterClass(EVT::v4i32, SPU::VECREGRegisterClass);
- addRegisterClass(EVT::v2i64, SPU::VECREGRegisterClass);
- addRegisterClass(EVT::v4f32, SPU::VECREGRegisterClass);
- addRegisterClass(EVT::v2f64, SPU::VECREGRegisterClass);
+ addRegisterClass(MVT::v16i8, SPU::VECREGRegisterClass);
+ addRegisterClass(MVT::v8i16, SPU::VECREGRegisterClass);
+ addRegisterClass(MVT::v4i32, SPU::VECREGRegisterClass);
+ addRegisterClass(MVT::v2i64, SPU::VECREGRegisterClass);
+ addRegisterClass(MVT::v4f32, SPU::VECREGRegisterClass);
+ addRegisterClass(MVT::v2f64, SPU::VECREGRegisterClass);
// "Odd size" vector classes that we're willing to support:
- addRegisterClass(EVT::v2i32, SPU::VECREGRegisterClass);
+ addRegisterClass(MVT::v2i32, SPU::VECREGRegisterClass);
- for (unsigned i = (unsigned)EVT::FIRST_VECTOR_VALUETYPE;
- i <= (unsigned)EVT::LAST_VECTOR_VALUETYPE; ++i) {
- EVT::SimpleValueType VT = (EVT::SimpleValueType)i;
+ for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
+ i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
+ MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
// add/sub are legal for all supported vector VT's.
setOperationAction(ISD::ADD, VT, Legal);
setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
}
- setOperationAction(ISD::AND, EVT::v16i8, Custom);
- setOperationAction(ISD::OR, EVT::v16i8, Custom);
- setOperationAction(ISD::XOR, EVT::v16i8, Custom);
- setOperationAction(ISD::SCALAR_TO_VECTOR, EVT::v4f32, Custom);
+ setOperationAction(ISD::AND, MVT::v16i8, Custom);
+ setOperationAction(ISD::OR, MVT::v16i8, Custom);
+ setOperationAction(ISD::XOR, MVT::v16i8, Custom);
+ setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
- setOperationAction(ISD::FDIV, EVT::v4f32, Legal);
+ setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
- setShiftAmountType(EVT::i32);
+ setShiftAmountType(MVT::i32);
setBooleanContents(ZeroOrNegativeOneBooleanContent);
setStackPointerRegisterToSaveRestore(SPU::R1);
// Return the Cell SPU's SETCC result type
//===----------------------------------------------------------------------===//
-EVT::SimpleValueType SPUTargetLowering::getSetCCResultType(EVT VT) const {
+MVT::SimpleValueType SPUTargetLowering::getSetCCResultType(EVT VT) const {
// i16 and i32 are valid SETCC result types
- return ((VT == EVT::i8 || VT == EVT::i16 || VT == EVT::i32) ?
- VT.getSimpleVT() :
- EVT::i32);
+ return ((VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) ?
+ VT.getSimpleVT().SimpleTy :
+ MVT::i32);
}
//===----------------------------------------------------------------------===//
within a 16-byte block, we have to rotate to extract the requested element.
For extending loads, we also want to ensure that the following sequence is
- emitted, e.g. for EVT::f32 extending load to EVT::f64:
+ emitted, e.g. for MVT::f32 extending load to MVT::f64:
\verbatim
%1 v16i8,ch = load
if (rotamt < 0)
rotamt += 16;
- rotate = DAG.getConstant(rotamt, EVT::i16);
+ rotate = DAG.getConstant(rotamt, MVT::i16);
// Simplify the base pointer for this case:
basePtr = basePtr.getOperand(0);
int64_t rotamt = -vtm->prefslot_byte;
if (rotamt < 0)
rotamt += 16;
- rotate = DAG.getConstant(rotamt, EVT::i16);
+ rotate = DAG.getConstant(rotamt, MVT::i16);
} else {
// Offset the rotate amount by the basePtr and the preferred slot
// byte offset
}
// Re-emit as a v16i8 vector load
- result = DAG.getLoad(EVT::v16i8, dl, the_chain, basePtr,
+ result = DAG.getLoad(MVT::v16i8, dl, the_chain, basePtr,
LN->getSrcValue(), LN->getSrcValueOffset(),
LN->isVolatile(), 16);
the_chain = result.getValue(1);
// Rotate into the preferred slot:
- result = DAG.getNode(SPUISD::ROTBYTES_LEFT, dl, EVT::v16i8,
+ result = DAG.getNode(SPUISD::ROTBYTES_LEFT, dl, MVT::v16i8,
result.getValue(0), rotate);
// Convert the loaded v16i8 vector to the appropriate vector type
result = DAG.getNode(NewOpc, dl, OutVT, result);
}
- SDVTList retvts = DAG.getVTList(OutVT, EVT::Other);
+ SDVTList retvts = DAG.getVTList(OutVT, MVT::Other);
SDValue retops[2] = {
result,
the_chain
}
// Re-emit as a v16i8 vector load
- alignLoadVec = DAG.getLoad(EVT::v16i8, dl, the_chain, basePtr,
+ alignLoadVec = DAG.getLoad(MVT::v16i8, dl, the_chain, basePtr,
SN->getSrcValue(), SN->getSrcValueOffset(),
SN->isVolatile(), 16);
result = DAG.getNode(SPUISD::SHUFB, dl, vecVT,
vectorizeOp, alignLoadVec,
DAG.getNode(ISD::BIT_CONVERT, dl,
- EVT::v4i32, insertEltOp));
+ MVT::v4i32, insertEltOp));
result = DAG.getStore(the_chain, dl, result, basePtr,
LN->getSrcValue(), LN->getSrcValueOffset(),
// FIXME there is no actual debug info here
DebugLoc dl = Op.getDebugLoc();
- if (VT == EVT::f64) {
+ if (VT == MVT::f64) {
ConstantFPSDNode *FP = cast<ConstantFPSDNode>(Op.getNode());
assert((FP != 0) &&
"LowerConstantFP: Node is not ConstantFPSDNode");
uint64_t dbits = DoubleToBits(FP->getValueAPF().convertToDouble());
- SDValue T = DAG.getConstant(dbits, EVT::i64);
- SDValue Tvec = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v2i64, T, T);
+ SDValue T = DAG.getConstant(dbits, MVT::i64);
+ SDValue Tvec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, T, T);
return DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT,
- DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v2f64, Tvec));
+ DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Tvec));
}
return SDValue();
if (ArgRegIdx < NumArgRegs) {
const TargetRegisterClass *ArgRegClass;
- switch (ObjectVT.getSimpleVT()) {
+ switch (ObjectVT.getSimpleVT().SimpleTy) {
default: {
std::string msg;
raw_string_ostream Msg(msg);
<< ObjectVT.getEVTString();
llvm_report_error(Msg.str());
}
- case EVT::i8:
+ case MVT::i8:
ArgRegClass = &SPU::R8CRegClass;
break;
- case EVT::i16:
+ case MVT::i16:
ArgRegClass = &SPU::R16CRegClass;
break;
- case EVT::i32:
+ case MVT::i32:
ArgRegClass = &SPU::R32CRegClass;
break;
- case EVT::i64:
+ case MVT::i64:
ArgRegClass = &SPU::R64CRegClass;
break;
- case EVT::i128:
+ case MVT::i128:
ArgRegClass = &SPU::GPRCRegClass;
break;
- case EVT::f32:
+ case MVT::f32:
ArgRegClass = &SPU::R32FPRegClass;
break;
- case EVT::f64:
+ case MVT::f64:
ArgRegClass = &SPU::R64FPRegClass;
break;
- case EVT::v2f64:
- case EVT::v4f32:
- case EVT::v2i64:
- case EVT::v4i32:
- case EVT::v8i16:
- case EVT::v16i8:
+ case MVT::v2f64:
+ case MVT::v4f32:
+ case MVT::v2i64:
+ case MVT::v4i32:
+ case MVT::v8i16:
+ case MVT::v16i8:
ArgRegClass = &SPU::VECREGRegClass;
break;
}
for (; ArgRegIdx != NumArgRegs; ++ArgRegIdx) {
VarArgsFrameIndex = MFI->CreateFixedObject(StackSlotSize, ArgOffset);
SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
- SDValue ArgVal = DAG.getRegister(ArgRegs[ArgRegIdx], EVT::v16i8);
+ SDValue ArgVal = DAG.getRegister(ArgRegs[ArgRegIdx], MVT::v16i8);
SDValue Store = DAG.getStore(Chain, dl, ArgVal, FIN, NULL, 0);
Chain = Store.getOperand(0);
MemOps.push_back(Store);
ArgOffset += StackSlotSize;
}
if (!MemOps.empty())
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&MemOps[0], MemOps.size());
}
(Addr << 14 >> 14) != Addr)
return 0; // Top 14 bits have to be sext of immediate.
- return DAG.getConstant((int)C->getZExtValue() >> 2, EVT::i32).getNode();
+ return DAG.getConstant((int)C->getZExtValue() >> 2, MVT::i32).getNode();
}
SDValue
// Set up a copy of the stack pointer for use loading and storing any
// arguments that may not fit in the registers available for argument
// passing.
- SDValue StackPtr = DAG.getRegister(SPU::R1, EVT::i32);
+ SDValue StackPtr = DAG.getRegister(SPU::R1, MVT::i32);
// Figure out which arguments are going to go in registers, and which in
// memory.
SDValue PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
- switch (Arg.getValueType().getSimpleVT()) {
+ switch (Arg.getValueType().getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unexpected ValueType for argument!");
- case EVT::i8:
- case EVT::i16:
- case EVT::i32:
- case EVT::i64:
- case EVT::i128:
+ case MVT::i8:
+ case MVT::i16:
+ case MVT::i32:
+ case MVT::i64:
+ case MVT::i128:
if (ArgRegIdx != NumArgRegs) {
RegsToPass.push_back(std::make_pair(ArgRegs[ArgRegIdx++], Arg));
} else {
ArgOffset += StackSlotSize;
}
break;
- case EVT::f32:
- case EVT::f64:
+ case MVT::f32:
+ case MVT::f64:
if (ArgRegIdx != NumArgRegs) {
RegsToPass.push_back(std::make_pair(ArgRegs[ArgRegIdx++], Arg));
} else {
ArgOffset += StackSlotSize;
}
break;
- case EVT::v2i64:
- case EVT::v2f64:
- case EVT::v4f32:
- case EVT::v4i32:
- case EVT::v8i16:
- case EVT::v16i8:
+ case MVT::v2i64:
+ case MVT::v2f64:
+ case MVT::v4f32:
+ case MVT::v4i32:
+ case MVT::v8i16:
+ case MVT::v16i8:
if (ArgRegIdx != NumArgRegs) {
RegsToPass.push_back(std::make_pair(ArgRegs[ArgRegIdx++], Arg));
} else {
if (!MemOpChains.empty()) {
// Adjust the stack pointer for the stack arguments.
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&MemOpChains[0], MemOpChains.size());
}
if (InFlag.getNode())
Ops.push_back(InFlag);
// Returns a chain and a flag for retval copy to use.
- Chain = DAG.getNode(CallOpc, dl, DAG.getVTList(EVT::Other, EVT::Flag),
+ Chain = DAG.getNode(CallOpc, dl, DAG.getVTList(MVT::Other, MVT::Flag),
&Ops[0], Ops.size());
InFlag = Chain.getValue(1);
return Chain;
// If the call has results, copy the values out of the ret val registers.
- switch (Ins[0].VT.getSimpleVT()) {
+ switch (Ins[0].VT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unexpected ret value!");
- case EVT::Other: break;
- case EVT::i32:
- if (Ins.size() > 1 && Ins[1].VT == EVT::i32) {
+ case MVT::Other: break;
+ case MVT::i32:
+ if (Ins.size() > 1 && Ins[1].VT == MVT::i32) {
Chain = DAG.getCopyFromReg(Chain, dl, SPU::R4,
- EVT::i32, InFlag).getValue(1);
+ MVT::i32, InFlag).getValue(1);
InVals.push_back(Chain.getValue(0));
- Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, EVT::i32,
+ Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, MVT::i32,
Chain.getValue(2)).getValue(1);
InVals.push_back(Chain.getValue(0));
} else {
- Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, EVT::i32,
+ Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, MVT::i32,
InFlag).getValue(1);
InVals.push_back(Chain.getValue(0));
}
break;
- case EVT::i64:
- Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, EVT::i64,
+ case MVT::i64:
+ Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, MVT::i64,
InFlag).getValue(1);
InVals.push_back(Chain.getValue(0));
break;
- case EVT::i128:
- Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, EVT::i128,
+ case MVT::i128:
+ Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, MVT::i128,
InFlag).getValue(1);
InVals.push_back(Chain.getValue(0));
break;
- case EVT::f32:
- case EVT::f64:
+ case MVT::f32:
+ case MVT::f64:
Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, Ins[0].VT,
InFlag).getValue(1);
InVals.push_back(Chain.getValue(0));
break;
- case EVT::v2f64:
- case EVT::v2i64:
- case EVT::v4f32:
- case EVT::v4i32:
- case EVT::v8i16:
- case EVT::v16i8:
+ case MVT::v2f64:
+ case MVT::v2i64:
+ case MVT::v4f32:
+ case MVT::v4i32:
+ case MVT::v8i16:
+ case MVT::v16i8:
Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, Ins[0].VT,
InFlag).getValue(1);
InVals.push_back(Chain.getValue(0));
}
if (Flag.getNode())
- return DAG.getNode(SPUISD::RET_FLAG, dl, EVT::Other, Chain, Flag);
+ return DAG.getNode(SPUISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
else
- return DAG.getNode(SPUISD::RET_FLAG, dl, EVT::Other, Chain);
+ return DAG.getNode(SPUISD::RET_FLAG, dl, MVT::Other, Chain);
}
EVT ValueType) {
if (ConstantSDNode *CN = getVecImm(N)) {
uint64_t Value = CN->getZExtValue();
- if (ValueType == EVT::i64) {
+ if (ValueType == MVT::i64) {
uint64_t UValue = CN->getZExtValue();
uint32_t upper = uint32_t(UValue >> 32);
uint32_t lower = uint32_t(UValue);
EVT ValueType) {
if (ConstantSDNode *CN = getVecImm(N)) {
int64_t Value = CN->getSExtValue();
- if (ValueType == EVT::i64) {
+ if (ValueType == MVT::i64) {
uint64_t UValue = CN->getZExtValue();
uint32_t upper = uint32_t(UValue >> 32);
uint32_t lower = uint32_t(UValue);
EVT ValueType) {
if (ConstantSDNode *CN = getVecImm(N)) {
int64_t Value = CN->getSExtValue();
- if (ValueType == EVT::i64) {
+ if (ValueType == MVT::i64) {
uint64_t UValue = CN->getZExtValue();
uint32_t upper = uint32_t(UValue >> 32);
uint32_t lower = uint32_t(UValue);
EVT ValueType) {
if (ConstantSDNode *CN = getVecImm(N)) {
int Value = (int) CN->getZExtValue();
- if (ValueType == EVT::i16
+ if (ValueType == MVT::i16
&& Value <= 0xffff /* truncated from uint64_t */
&& ((short) Value >> 8) == ((short) Value & 0xff))
return DAG.getTargetConstant(Value & 0xff, ValueType);
- else if (ValueType == EVT::i8
+ else if (ValueType == MVT::i8
&& (Value & 0xff) == Value)
return DAG.getTargetConstant(Value, ValueType);
}
EVT ValueType) {
if (ConstantSDNode *CN = getVecImm(N)) {
uint64_t Value = CN->getZExtValue();
- if ((ValueType == EVT::i32
+ if ((ValueType == MVT::i32
&& ((unsigned) Value & 0xffff0000) == (unsigned) Value)
- || (ValueType == EVT::i64 && (Value & 0xffff0000) == Value))
+ || (ValueType == MVT::i64 && (Value & 0xffff0000) == Value))
return DAG.getTargetConstant(Value >> 16, ValueType);
}
/// get_v4i32_imm - Catch-all for general 32-bit constant vectors
SDValue SPU::get_v4i32_imm(SDNode *N, SelectionDAG &DAG) {
if (ConstantSDNode *CN = getVecImm(N)) {
- return DAG.getTargetConstant((unsigned) CN->getZExtValue(), EVT::i32);
+ return DAG.getTargetConstant((unsigned) CN->getZExtValue(), MVT::i32);
}
return SDValue();
/// get_v4i32_imm - Catch-all for general 64-bit constant vectors
SDValue SPU::get_v2i64_imm(SDNode *N, SelectionDAG &DAG) {
if (ConstantSDNode *CN = getVecImm(N)) {
- return DAG.getTargetConstant((unsigned) CN->getZExtValue(), EVT::i64);
+ return DAG.getTargetConstant((unsigned) CN->getZExtValue(), MVT::i64);
}
return SDValue();
uint64_t SplatBits = APSplatBits.getZExtValue();
- switch (VT.getSimpleVT()) {
+ switch (VT.getSimpleVT().SimpleTy) {
default: {
std::string msg;
raw_string_ostream Msg(msg);
llvm_report_error(Msg.str());
/*NOTREACHED*/
}
- case EVT::v4f32: {
+ case MVT::v4f32: {
uint32_t Value32 = uint32_t(SplatBits);
assert(SplatBitSize == 32
&& "LowerBUILD_VECTOR: Unexpected floating point vector element.");
// NOTE: pretend the constant is an integer. LLVM won't load FP constants
- SDValue T = DAG.getConstant(Value32, EVT::i32);
- return DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v4f32,
- DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32, T,T,T,T));
+ SDValue T = DAG.getConstant(Value32, MVT::i32);
+ return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32,
+ DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, T,T,T,T));
break;
}
- case EVT::v2f64: {
+ case MVT::v2f64: {
uint64_t f64val = uint64_t(SplatBits);
assert(SplatBitSize == 64
&& "LowerBUILD_VECTOR: 64-bit float vector size > 8 bytes.");
// NOTE: pretend the constant is an integer. LLVM won't load FP constants
- SDValue T = DAG.getConstant(f64val, EVT::i64);
- return DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v2f64,
- DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v2i64, T, T));
+ SDValue T = DAG.getConstant(f64val, MVT::i64);
+ return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64,
+ DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, T, T));
break;
}
- case EVT::v16i8: {
+ case MVT::v16i8: {
// 8-bit constants have to be expanded to 16-bits
unsigned short Value16 = SplatBits /* | (SplatBits << 8) */;
SmallVector<SDValue, 8> Ops;
- Ops.assign(8, DAG.getConstant(Value16, EVT::i16));
+ Ops.assign(8, DAG.getConstant(Value16, MVT::i16));
return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
- DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v8i16, &Ops[0], Ops.size()));
+ DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i16, &Ops[0], Ops.size()));
}
- case EVT::v8i16: {
+ case MVT::v8i16: {
unsigned short Value16 = SplatBits;
SDValue T = DAG.getConstant(Value16, EltVT);
SmallVector<SDValue, 8> Ops;
Ops.assign(8, T);
return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
}
- case EVT::v4i32: {
+ case MVT::v4i32: {
SDValue T = DAG.getConstant(unsigned(SplatBits), VT.getVectorElementType());
return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, T, T, T, T);
}
- case EVT::v2i32: {
+ case MVT::v2i32: {
SDValue T = DAG.getConstant(unsigned(SplatBits), VT.getVectorElementType());
return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, T, T);
}
- case EVT::v2i64: {
+ case MVT::v2i64: {
return SPU::LowerV2I64Splat(VT, DAG, SplatBits, dl);
}
}
if (upper == lower) {
// Magic constant that can be matched by IL, ILA, et. al.
- SDValue Val = DAG.getTargetConstant(upper, EVT::i32);
+ SDValue Val = DAG.getTargetConstant(upper, MVT::i32);
return DAG.getNode(ISD::BIT_CONVERT, dl, OpVT,
- DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32,
+ DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
Val, Val, Val, Val));
} else {
bool upper_special, lower_special;
// Both upper and lower are special, lower to a constant pool load:
if (lower_special && upper_special) {
- SDValue SplatValCN = DAG.getConstant(SplatVal, EVT::i64);
- return DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v2i64,
+ SDValue SplatValCN = DAG.getConstant(SplatVal, MVT::i64);
+ return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64,
SplatValCN, SplatValCN);
}
// Create lower vector if not a special pattern
if (!lower_special) {
- SDValue LO32C = DAG.getConstant(lower, EVT::i32);
+ SDValue LO32C = DAG.getConstant(lower, MVT::i32);
LO32 = DAG.getNode(ISD::BIT_CONVERT, dl, OpVT,
- DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32,
+ DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
LO32C, LO32C, LO32C, LO32C));
}
// Create upper vector if not a special pattern
if (!upper_special) {
- SDValue HI32C = DAG.getConstant(upper, EVT::i32);
+ SDValue HI32C = DAG.getConstant(upper, MVT::i32);
HI32 = DAG.getNode(ISD::BIT_CONVERT, dl, OpVT,
- DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32,
+ DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
HI32C, HI32C, HI32C, HI32C));
}
val |= i * 4 + j + ((i & 1) * 16);
}
- ShufBytes.push_back(DAG.getConstant(val, EVT::i32));
+ ShufBytes.push_back(DAG.getConstant(val, MVT::i32));
}
return DAG.getNode(SPUISD::SHUFB, dl, OpVT, HI32, LO32,
- DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32,
+ DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
&ShufBytes[0], ShufBytes.size()));
}
}
bool monotonic = true;
bool rotate = true;
- if (EltVT == EVT::i8) {
+ if (EltVT == MVT::i8) {
V2EltIdx0 = 16;
- } else if (EltVT == EVT::i16) {
+ } else if (EltVT == MVT::i16) {
V2EltIdx0 = 8;
- } else if (EltVT == EVT::i32 || EltVT == EVT::f32) {
+ } else if (EltVT == MVT::i32 || EltVT == MVT::f32) {
V2EltIdx0 = 4;
- } else if (EltVT == EVT::i64 || EltVT == EVT::f64) {
+ } else if (EltVT == MVT::i64 || EltVT == MVT::f64) {
V2EltIdx0 = 2;
} else
llvm_unreachable("Unhandled vector type in LowerVECTOR_SHUFFLE");
DAG.getCopyToReg(DAG.getEntryNode(), dl, VReg, DAG.getConstant(0, PtrVT));
// Copy register's contents as index in SHUFFLE_MASK:
SDValue ShufMaskOp =
- DAG.getNode(SPUISD::SHUFFLE_MASK, dl, EVT::v4i32,
- DAG.getTargetConstant(V2Elt, EVT::i32),
+ DAG.getNode(SPUISD::SHUFFLE_MASK, dl, MVT::v4i32,
+ DAG.getTargetConstant(V2Elt, MVT::i32),
DAG.getCopyFromReg(InitTempReg, dl, VReg, PtrVT));
// Use shuffle mask in SHUFB synthetic instruction:
return DAG.getNode(SPUISD::SHUFB, dl, V1.getValueType(), V2, V1,
int rotamt = (MaxElts - V0Elt) * EltVT.getSizeInBits()/8;
return DAG.getNode(SPUISD::ROTBYTES_LEFT, dl, V1.getValueType(),
- V1, DAG.getConstant(rotamt, EVT::i16));
+ V1, DAG.getConstant(rotamt, MVT::i16));
} else {
// Convert the SHUFFLE_VECTOR mask's input element units to the
// actual bytes.
unsigned SrcElt = SVN->getMaskElt(i) < 0 ? 0 : SVN->getMaskElt(i);
for (unsigned j = 0; j < BytesPerElement; ++j)
- ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,EVT::i8));
+ ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,MVT::i8));
}
- SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v16i8,
+ SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
&ResultMask[0], ResultMask.size());
return DAG.getNode(SPUISD::SHUFB, dl, V1.getValueType(), V1, V2, VPermMask);
}
size_t n_copies;
// Create a constant vector:
- switch (Op.getValueType().getSimpleVT()) {
+ switch (Op.getValueType().getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unexpected constant value type in "
"LowerSCALAR_TO_VECTOR");
- case EVT::v16i8: n_copies = 16; VT = EVT::i8; break;
- case EVT::v8i16: n_copies = 8; VT = EVT::i16; break;
- case EVT::v4i32: n_copies = 4; VT = EVT::i32; break;
- case EVT::v4f32: n_copies = 4; VT = EVT::f32; break;
- case EVT::v2i64: n_copies = 2; VT = EVT::i64; break;
- case EVT::v2f64: n_copies = 2; VT = EVT::f64; break;
+ case MVT::v16i8: n_copies = 16; VT = MVT::i8; break;
+ case MVT::v8i16: n_copies = 8; VT = MVT::i16; break;
+ case MVT::v4i32: n_copies = 4; VT = MVT::i32; break;
+ case MVT::v4f32: n_copies = 4; VT = MVT::f32; break;
+ case MVT::v2i64: n_copies = 2; VT = MVT::i64; break;
+ case MVT::v2f64: n_copies = 2; VT = MVT::f64; break;
}
SDValue CValue = DAG.getConstant(CN->getZExtValue(), VT);
&ConstVecValues[0], ConstVecValues.size());
} else {
// Otherwise, copy the value from one register to another:
- switch (Op0.getValueType().getSimpleVT()) {
+ switch (Op0.getValueType().getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unexpected value type in LowerSCALAR_TO_VECTOR");
- case EVT::i8:
- case EVT::i16:
- case EVT::i32:
- case EVT::i64:
- case EVT::f32:
- case EVT::f64:
+ case MVT::i8:
+ case MVT::i16:
+ case MVT::i32:
+ case MVT::i64:
+ case MVT::f32:
+ case MVT::f64:
return DAG.getNode(SPUISD::PREFSLOT2VEC, dl, Op.getValueType(), Op0, Op0);
}
}
int EltNo = (int) C->getZExtValue();
// sanity checks:
- if (VT == EVT::i8 && EltNo >= 16)
+ if (VT == MVT::i8 && EltNo >= 16)
llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i8 extraction slot > 15");
- else if (VT == EVT::i16 && EltNo >= 8)
+ else if (VT == MVT::i16 && EltNo >= 8)
llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i16 extraction slot > 7");
- else if (VT == EVT::i32 && EltNo >= 4)
+ else if (VT == MVT::i32 && EltNo >= 4)
llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i32 extraction slot > 4");
- else if (VT == EVT::i64 && EltNo >= 2)
+ else if (VT == MVT::i64 && EltNo >= 2)
llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i64 extraction slot > 2");
- if (EltNo == 0 && (VT == EVT::i32 || VT == EVT::i64)) {
+ if (EltNo == 0 && (VT == MVT::i32 || VT == MVT::i64)) {
// i32 and i64: Element 0 is the preferred slot
return DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT, N);
}
int prefslot_begin = -1, prefslot_end = -1;
int elt_byte = EltNo * VT.getSizeInBits() / 8;
- switch (VT.getSimpleVT()) {
+ switch (VT.getSimpleVT().SimpleTy) {
default:
assert(false && "Invalid value type!");
- case EVT::i8: {
+ case MVT::i8: {
prefslot_begin = prefslot_end = 3;
break;
}
- case EVT::i16: {
+ case MVT::i16: {
prefslot_begin = 2; prefslot_end = 3;
break;
}
- case EVT::i32:
- case EVT::f32: {
+ case MVT::i32:
+ case MVT::f32: {
prefslot_begin = 0; prefslot_end = 3;
break;
}
- case EVT::i64:
- case EVT::f64: {
+ case MVT::i64:
+ case MVT::f64: {
prefslot_begin = 0; prefslot_end = 7;
break;
}
(ShufBytes[bidx+1] << 16) |
(ShufBytes[bidx+2] << 8) |
ShufBytes[bidx+3]);
- ShufMask[i] = DAG.getConstant(bits, EVT::i32);
+ ShufMask[i] = DAG.getConstant(bits, MVT::i32);
}
SDValue ShufMaskVec =
- DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32,
+ DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
&ShufMask[0], sizeof(ShufMask)/sizeof(ShufMask[0]));
retval = DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT,
}
// Make life easier by making sure the index is zero-extended to i32
- if (Elt.getValueType() != EVT::i32)
- Elt = DAG.getNode(ISD::ZERO_EXTEND, dl, EVT::i32, Elt);
+ if (Elt.getValueType() != MVT::i32)
+ Elt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Elt);
// Scale the index to a bit/byte shift quantity
APInt scaleFactor =
if (scaleShift > 0) {
// Scale the shift factor:
- Elt = DAG.getNode(ISD::SHL, dl, EVT::i32, Elt,
- DAG.getConstant(scaleShift, EVT::i32));
+ Elt = DAG.getNode(ISD::SHL, dl, MVT::i32, Elt,
+ DAG.getConstant(scaleShift, MVT::i32));
}
vecShift = DAG.getNode(SPUISD::SHLQUAD_L_BYTES, dl, VecVT, N, Elt);
// consistency with the notion of a unified register set)
SDValue replicate;
- switch (VT.getSimpleVT()) {
+ switch (VT.getSimpleVT().SimpleTy) {
default:
llvm_report_error("LowerEXTRACT_VECTOR_ELT(varable): Unhandled vector"
"type");
/*NOTREACHED*/
- case EVT::i8: {
- SDValue factor = DAG.getConstant(0x00000000, EVT::i32);
- replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32,
+ case MVT::i8: {
+ SDValue factor = DAG.getConstant(0x00000000, MVT::i32);
+ replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
factor, factor, factor, factor);
break;
}
- case EVT::i16: {
- SDValue factor = DAG.getConstant(0x00010001, EVT::i32);
- replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32,
+ case MVT::i16: {
+ SDValue factor = DAG.getConstant(0x00010001, MVT::i32);
+ replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
factor, factor, factor, factor);
break;
}
- case EVT::i32:
- case EVT::f32: {
- SDValue factor = DAG.getConstant(0x00010203, EVT::i32);
- replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32,
+ case MVT::i32:
+ case MVT::f32: {
+ SDValue factor = DAG.getConstant(0x00010203, MVT::i32);
+ replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
factor, factor, factor, factor);
break;
}
- case EVT::i64:
- case EVT::f64: {
- SDValue loFactor = DAG.getConstant(0x00010203, EVT::i32);
- SDValue hiFactor = DAG.getConstant(0x04050607, EVT::i32);
- replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32,
+ case MVT::i64:
+ case MVT::f64: {
+ SDValue loFactor = DAG.getConstant(0x00010203, MVT::i32);
+ SDValue hiFactor = DAG.getConstant(0x04050607, MVT::i32);
+ replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
loFactor, hiFactor, loFactor, hiFactor);
break;
}
DAG.getNode(SPUISD::SHUFB, dl, VT,
DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, ValOp),
VecOp,
- DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v4i32, ShufMask));
+ DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, ShufMask));
return result;
}
DebugLoc dl = Op.getDebugLoc();
EVT ShiftVT = TLI.getShiftAmountTy();
- assert(Op.getValueType() == EVT::i8);
+ assert(Op.getValueType() == MVT::i8);
switch (Opc) {
default:
llvm_unreachable("Unhandled i8 math operator");
// 8-bit addition: Promote the arguments up to 16-bits and truncate
// the result:
SDValue N1 = Op.getOperand(1);
- N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, EVT::i16, N0);
- N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, EVT::i16, N1);
- return DAG.getNode(ISD::TRUNCATE, dl, EVT::i8,
- DAG.getNode(Opc, dl, EVT::i16, N0, N1));
+ N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N0);
+ N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N1);
+ return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8,
+ DAG.getNode(Opc, dl, MVT::i16, N0, N1));
}
// 8-bit subtraction: Promote the arguments up to 16-bits and truncate
// the result:
SDValue N1 = Op.getOperand(1);
- N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, EVT::i16, N0);
- N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, EVT::i16, N1);
- return DAG.getNode(ISD::TRUNCATE, dl, EVT::i8,
- DAG.getNode(Opc, dl, EVT::i16, N0, N1));
+ N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N0);
+ N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N1);
+ return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8,
+ DAG.getNode(Opc, dl, MVT::i16, N0, N1));
}
case ISD::ROTR:
case ISD::ROTL: {
SDValue N1 = Op.getOperand(1);
EVT N1VT = N1.getValueType();
- N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, EVT::i16, N0);
+ N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, N0);
if (!N1VT.bitsEq(ShiftVT)) {
unsigned N1Opc = N1.getValueType().bitsLT(ShiftVT)
? ISD::ZERO_EXTEND
// Replicate lower 8-bits into upper 8:
SDValue ExpandArg =
- DAG.getNode(ISD::OR, dl, EVT::i16, N0,
- DAG.getNode(ISD::SHL, dl, EVT::i16,
- N0, DAG.getConstant(8, EVT::i32)));
+ DAG.getNode(ISD::OR, dl, MVT::i16, N0,
+ DAG.getNode(ISD::SHL, dl, MVT::i16,
+ N0, DAG.getConstant(8, MVT::i32)));
// Truncate back down to i8
- return DAG.getNode(ISD::TRUNCATE, dl, EVT::i8,
- DAG.getNode(Opc, dl, EVT::i16, ExpandArg, N1));
+ return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8,
+ DAG.getNode(Opc, dl, MVT::i16, ExpandArg, N1));
}
case ISD::SRL:
case ISD::SHL: {
SDValue N1 = Op.getOperand(1);
EVT N1VT = N1.getValueType();
- N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, EVT::i16, N0);
+ N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, N0);
if (!N1VT.bitsEq(ShiftVT)) {
unsigned N1Opc = ISD::ZERO_EXTEND;
N1 = DAG.getNode(N1Opc, dl, ShiftVT, N1);
}
- return DAG.getNode(ISD::TRUNCATE, dl, EVT::i8,
- DAG.getNode(Opc, dl, EVT::i16, N0, N1));
+ return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8,
+ DAG.getNode(Opc, dl, MVT::i16, N0, N1));
}
case ISD::SRA: {
SDValue N1 = Op.getOperand(1);
EVT N1VT = N1.getValueType();
- N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, EVT::i16, N0);
+ N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N0);
if (!N1VT.bitsEq(ShiftVT)) {
unsigned N1Opc = ISD::SIGN_EXTEND;
N1 = DAG.getNode(N1Opc, dl, ShiftVT, N1);
}
- return DAG.getNode(ISD::TRUNCATE, dl, EVT::i8,
- DAG.getNode(Opc, dl, EVT::i16, N0, N1));
+ return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8,
+ DAG.getNode(Opc, dl, MVT::i16, N0, N1));
}
case ISD::MUL: {
SDValue N1 = Op.getOperand(1);
- N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, EVT::i16, N0);
- N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, EVT::i16, N1);
- return DAG.getNode(ISD::TRUNCATE, dl, EVT::i8,
- DAG.getNode(Opc, dl, EVT::i16, N0, N1));
+ N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N0);
+ N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N1);
+ return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8,
+ DAG.getNode(Opc, dl, MVT::i16, N0, N1));
break;
}
}
HasAnyUndefs, minSplatBits)
&& minSplatBits <= SplatBitSize) {
uint64_t SplatBits = APSplatBits.getZExtValue();
- SDValue tc = DAG.getTargetConstant(SplatBits & 0xff, EVT::i8);
+ SDValue tc = DAG.getTargetConstant(SplatBits & 0xff, MVT::i8);
SmallVector<SDValue, 16> tcVec;
tcVec.assign(16, tc);
EVT vecVT = EVT::getVectorVT(VT, (128 / VT.getSizeInBits()));
DebugLoc dl = Op.getDebugLoc();
- switch (VT.getSimpleVT()) {
+ switch (VT.getSimpleVT().SimpleTy) {
default:
assert(false && "Invalid value type!");
- case EVT::i8: {
+ case MVT::i8: {
SDValue N = Op.getOperand(0);
- SDValue Elt0 = DAG.getConstant(0, EVT::i32);
+ SDValue Elt0 = DAG.getConstant(0, MVT::i32);
SDValue Promote = DAG.getNode(SPUISD::PREFSLOT2VEC, dl, vecVT, N, N);
SDValue CNTB = DAG.getNode(SPUISD::CNTB, dl, vecVT, Promote);
- return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::i8, CNTB, Elt0);
+ return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i8, CNTB, Elt0);
}
- case EVT::i16: {
+ case MVT::i16: {
MachineFunction &MF = DAG.getMachineFunction();
MachineRegisterInfo &RegInfo = MF.getRegInfo();
unsigned CNTB_reg = RegInfo.createVirtualRegister(&SPU::R16CRegClass);
SDValue N = Op.getOperand(0);
- SDValue Elt0 = DAG.getConstant(0, EVT::i16);
- SDValue Mask0 = DAG.getConstant(0x0f, EVT::i16);
- SDValue Shift1 = DAG.getConstant(8, EVT::i32);
+ SDValue Elt0 = DAG.getConstant(0, MVT::i16);
+ SDValue Mask0 = DAG.getConstant(0x0f, MVT::i16);
+ SDValue Shift1 = DAG.getConstant(8, MVT::i32);
SDValue Promote = DAG.getNode(SPUISD::PREFSLOT2VEC, dl, vecVT, N, N);
SDValue CNTB = DAG.getNode(SPUISD::CNTB, dl, vecVT, Promote);
// CNTB_result becomes the chain to which all of the virtual registers
// CNTB_reg, SUM1_reg become associated:
SDValue CNTB_result =
- DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::i16, CNTB, Elt0);
+ DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, CNTB, Elt0);
SDValue CNTB_rescopy =
DAG.getCopyToReg(CNTB_result, dl, CNTB_reg, CNTB_result);
- SDValue Tmp1 = DAG.getCopyFromReg(CNTB_rescopy, dl, CNTB_reg, EVT::i16);
+ SDValue Tmp1 = DAG.getCopyFromReg(CNTB_rescopy, dl, CNTB_reg, MVT::i16);
- return DAG.getNode(ISD::AND, dl, EVT::i16,
- DAG.getNode(ISD::ADD, dl, EVT::i16,
- DAG.getNode(ISD::SRL, dl, EVT::i16,
+ return DAG.getNode(ISD::AND, dl, MVT::i16,
+ DAG.getNode(ISD::ADD, dl, MVT::i16,
+ DAG.getNode(ISD::SRL, dl, MVT::i16,
Tmp1, Shift1),
Tmp1),
Mask0);
}
- case EVT::i32: {
+ case MVT::i32: {
MachineFunction &MF = DAG.getMachineFunction();
MachineRegisterInfo &RegInfo = MF.getRegInfo();
unsigned SUM1_reg = RegInfo.createVirtualRegister(&SPU::R32CRegClass);
SDValue N = Op.getOperand(0);
- SDValue Elt0 = DAG.getConstant(0, EVT::i32);
- SDValue Mask0 = DAG.getConstant(0xff, EVT::i32);
- SDValue Shift1 = DAG.getConstant(16, EVT::i32);
- SDValue Shift2 = DAG.getConstant(8, EVT::i32);
+ SDValue Elt0 = DAG.getConstant(0, MVT::i32);
+ SDValue Mask0 = DAG.getConstant(0xff, MVT::i32);
+ SDValue Shift1 = DAG.getConstant(16, MVT::i32);
+ SDValue Shift2 = DAG.getConstant(8, MVT::i32);
SDValue Promote = DAG.getNode(SPUISD::PREFSLOT2VEC, dl, vecVT, N, N);
SDValue CNTB = DAG.getNode(SPUISD::CNTB, dl, vecVT, Promote);
// CNTB_result becomes the chain to which all of the virtual registers
// CNTB_reg, SUM1_reg become associated:
SDValue CNTB_result =
- DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::i32, CNTB, Elt0);
+ DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, CNTB, Elt0);
SDValue CNTB_rescopy =
DAG.getCopyToReg(CNTB_result, dl, CNTB_reg, CNTB_result);
SDValue Comp1 =
- DAG.getNode(ISD::SRL, dl, EVT::i32,
- DAG.getCopyFromReg(CNTB_rescopy, dl, CNTB_reg, EVT::i32),
+ DAG.getNode(ISD::SRL, dl, MVT::i32,
+ DAG.getCopyFromReg(CNTB_rescopy, dl, CNTB_reg, MVT::i32),
Shift1);
SDValue Sum1 =
- DAG.getNode(ISD::ADD, dl, EVT::i32, Comp1,
- DAG.getCopyFromReg(CNTB_rescopy, dl, CNTB_reg, EVT::i32));
+ DAG.getNode(ISD::ADD, dl, MVT::i32, Comp1,
+ DAG.getCopyFromReg(CNTB_rescopy, dl, CNTB_reg, MVT::i32));
SDValue Sum1_rescopy =
DAG.getCopyToReg(CNTB_result, dl, SUM1_reg, Sum1);
SDValue Comp2 =
- DAG.getNode(ISD::SRL, dl, EVT::i32,
- DAG.getCopyFromReg(Sum1_rescopy, dl, SUM1_reg, EVT::i32),
+ DAG.getNode(ISD::SRL, dl, MVT::i32,
+ DAG.getCopyFromReg(Sum1_rescopy, dl, SUM1_reg, MVT::i32),
Shift2);
SDValue Sum2 =
- DAG.getNode(ISD::ADD, dl, EVT::i32, Comp2,
- DAG.getCopyFromReg(Sum1_rescopy, dl, SUM1_reg, EVT::i32));
+ DAG.getNode(ISD::ADD, dl, MVT::i32, Comp2,
+ DAG.getCopyFromReg(Sum1_rescopy, dl, SUM1_reg, MVT::i32));
- return DAG.getNode(ISD::AND, dl, EVT::i32, Sum2, Mask0);
+ return DAG.getNode(ISD::AND, dl, MVT::i32, Sum2, Mask0);
}
- case EVT::i64:
+ case MVT::i64:
break;
}
SDValue Op0 = Op.getOperand(0);
EVT Op0VT = Op0.getValueType();
- if ((OpVT == EVT::i32 && Op0VT == EVT::f64)
- || OpVT == EVT::i64) {
+ if ((OpVT == MVT::i32 && Op0VT == MVT::f64)
+ || OpVT == MVT::i64) {
// Convert f32 / f64 to i32 / i64 via libcall.
RTLIB::Libcall LC =
(Op.getOpcode() == ISD::FP_TO_SINT)
SDValue Op0 = Op.getOperand(0);
EVT Op0VT = Op0.getValueType();
- if ((OpVT == EVT::f64 && Op0VT == EVT::i32)
- || Op0VT == EVT::i64) {
+ if ((OpVT == MVT::f64 && Op0VT == MVT::i32)
+ || Op0VT == MVT::i64) {
// Convert i32, i64 to f64 via libcall:
RTLIB::Libcall LC =
(Op.getOpcode() == ISD::SINT_TO_FP)
//! Lower ISD::SETCC
/*!
- This handles EVT::f64 (double floating point) condition lowering
+ This handles MVT::f64 (double floating point) condition lowering
*/
static SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG,
const TargetLowering &TLI) {
SDValue lhs = Op.getOperand(0);
SDValue rhs = Op.getOperand(1);
EVT lhsVT = lhs.getValueType();
- assert(lhsVT == EVT::f64 && "LowerSETCC: type other than EVT::64\n");
+ assert(lhsVT == MVT::f64 && "LowerSETCC: type other than MVT::64\n");
EVT ccResultVT = TLI.getSetCCResultType(lhs.getValueType());
APInt ccResultOnes = APInt::getAllOnesValue(ccResultVT.getSizeInBits());
- EVT IntVT(EVT::i64);
+ EVT IntVT(MVT::i64);
// Take advantage of the fact that (truncate (sra arg, 32)) is efficiently
// selected to a NOP:
SDValue i64lhs = DAG.getNode(ISD::BIT_CONVERT, dl, IntVT, lhs);
SDValue lhsHi32 =
- DAG.getNode(ISD::TRUNCATE, dl, EVT::i32,
+ DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
DAG.getNode(ISD::SRL, dl, IntVT,
- i64lhs, DAG.getConstant(32, EVT::i32)));
+ i64lhs, DAG.getConstant(32, MVT::i32)));
SDValue lhsHi32abs =
- DAG.getNode(ISD::AND, dl, EVT::i32,
- lhsHi32, DAG.getConstant(0x7fffffff, EVT::i32));
+ DAG.getNode(ISD::AND, dl, MVT::i32,
+ lhsHi32, DAG.getConstant(0x7fffffff, MVT::i32));
SDValue lhsLo32 =
- DAG.getNode(ISD::TRUNCATE, dl, EVT::i32, i64lhs);
+ DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, i64lhs);
// SETO and SETUO only use the lhs operand:
if (CC->get() == ISD::SETO) {
return DAG.getNode(ISD::AND, dl, ccResultVT,
DAG.getSetCC(dl, ccResultVT,
lhsHi32abs,
- DAG.getConstant(0x7ff00000, EVT::i32),
+ DAG.getConstant(0x7ff00000, MVT::i32),
ISD::SETGE),
DAG.getSetCC(dl, ccResultVT,
lhsLo32,
- DAG.getConstant(0, EVT::i32),
+ DAG.getConstant(0, MVT::i32),
ISD::SETGT));
}
SDValue i64rhs = DAG.getNode(ISD::BIT_CONVERT, dl, IntVT, rhs);
SDValue rhsHi32 =
- DAG.getNode(ISD::TRUNCATE, dl, EVT::i32,
+ DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
DAG.getNode(ISD::SRL, dl, IntVT,
- i64rhs, DAG.getConstant(32, EVT::i32)));
+ i64rhs, DAG.getConstant(32, MVT::i32)));
// If a value is negative, subtract from the sign magnitude constant:
SDValue signMag2TC = DAG.getConstant(0x8000000000000000ULL, IntVT);
// Convert the sign-magnitude representation into 2's complement:
SDValue lhsSelectMask = DAG.getNode(ISD::SRA, dl, ccResultVT,
- lhsHi32, DAG.getConstant(31, EVT::i32));
+ lhsHi32, DAG.getConstant(31, MVT::i32));
SDValue lhsSignMag2TC = DAG.getNode(ISD::SUB, dl, IntVT, signMag2TC, i64lhs);
SDValue lhsSelect =
DAG.getNode(ISD::SELECT, dl, IntVT,
lhsSelectMask, lhsSignMag2TC, i64lhs);
SDValue rhsSelectMask = DAG.getNode(ISD::SRA, dl, ccResultVT,
- rhsHi32, DAG.getConstant(31, EVT::i32));
+ rhsHi32, DAG.getConstant(31, MVT::i32));
SDValue rhsSignMag2TC = DAG.getNode(ISD::SUB, dl, IntVT, signMag2TC, i64rhs);
SDValue rhsSelect =
DAG.getNode(ISD::SELECT, dl, IntVT,
if ((CC->get() & 0x8) == 0) {
// Ordered comparison:
SDValue lhsNaN = DAG.getSetCC(dl, ccResultVT,
- lhs, DAG.getConstantFP(0.0, EVT::f64),
+ lhs, DAG.getConstantFP(0.0, MVT::f64),
ISD::SETO);
SDValue rhsNaN = DAG.getSetCC(dl, ccResultVT,
- rhs, DAG.getConstantFP(0.0, EVT::f64),
+ rhs, DAG.getConstantFP(0.0, MVT::f64),
ISD::SETO);
SDValue ordered = DAG.getNode(ISD::AND, dl, ccResultVT, lhsNaN, rhsNaN);
{
// Type to truncate to
EVT VT = Op.getValueType();
- EVT::SimpleValueType simpleVT = VT.getSimpleVT();
+ MVT simpleVT = VT.getSimpleVT();
EVT VecVT = EVT::getVectorVT(VT, (128 / VT.getSizeInBits()));
DebugLoc dl = Op.getDebugLoc();
SDValue Op0 = Op.getOperand(0);
EVT Op0VT = Op0.getValueType();
- if (Op0VT.getSimpleVT() == EVT::i128 && simpleVT == EVT::i64) {
+ if (Op0VT.getSimpleVT() == MVT::i128 && simpleVT == MVT::i64) {
// Create shuffle mask, least significant doubleword of quadword
unsigned maskHigh = 0x08090a0b;
unsigned maskLow = 0x0c0d0e0f;
// Use a shuffle to perform the truncation
- SDValue shufMask = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32,
- DAG.getConstant(maskHigh, EVT::i32),
- DAG.getConstant(maskLow, EVT::i32),
- DAG.getConstant(maskHigh, EVT::i32),
- DAG.getConstant(maskLow, EVT::i32));
+ SDValue shufMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
+ DAG.getConstant(maskHigh, MVT::i32),
+ DAG.getConstant(maskLow, MVT::i32),
+ DAG.getConstant(maskHigh, MVT::i32),
+ DAG.getConstant(maskLow, MVT::i32));
SDValue truncShuffle = DAG.getNode(SPUISD::SHUFB, dl, VecVT,
Op0, Op0, shufMask);
case ISD::SRL:
case ISD::SHL:
case ISD::SRA: {
- if (VT == EVT::i8)
+ if (VT == MVT::i8)
return LowerI8Math(Op, DAG, Opc, *this);
break;
}
// Vector and i8 multiply:
case ISD::MUL:
- if (VT == EVT::i8)
+ if (VT == MVT::i8)
return LowerI8Math(Op, DAG, Opc, *this);
case ISD::CTPOP:
@@ -2945,13 +2945,13 @@ SPUTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
switch (Constraint[0]) {
case 'b': // R1-R31
case 'r': // R0-R31
- if (VT == EVT::i64)
+ if (VT == MVT::i64)
return std::make_pair(0U, SPU::R64CRegisterClass);
return std::make_pair(0U, SPU::R32CRegisterClass);
case 'f':
- if (VT == EVT::f32)
+ if (VT == MVT::f32)
return std::make_pair(0U, SPU::R32FPRegisterClass);
- else if (VT == EVT::f64)
+ else if (VT == MVT::f64)
return std::make_pair(0U, SPU::R64FPRegisterClass);
break;
case 'v':
case ISD::SETCC: {
EVT VT = Op.getValueType();
- if (VT != EVT::i8 && VT != EVT::i16 && VT != EVT::i32) {
- VT = EVT::i32;
+ if (VT != MVT::i8 && VT != MVT::i16 && VT != MVT::i32) {
+ VT = MVT::i32;
}
return VT.getSizeInBits();
}
index 07811e4f33eb43117f6688927df1c651a57f1bc0..b0a118a2a822b84a7e9aa99c59e9d961da7d1b89 100644 (file)
virtual const char *getTargetNodeName(unsigned Opcode) const;
/// getSetCCResultType - Return the ValueType for ISD::SETCC
- virtual EVT::SimpleValueType getSetCCResultType(EVT VT) const;
+ virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const;
//! Custom lowering hooks
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
index 4db8e86ec1d6acbfca8b13b22a288bcf0573102b..802628f8996550ecdc0f57cb2f61a0d0087ea10b 100644 (file)
def lo16 : PatLeaf<(imm), [{
// lo16 predicate - returns true if the immediate has all zeros in the
// low order bits and is a 32-bit constant:
- if (N->getValueType(0) == EVT::i32) {
+ if (N->getValueType(0) == MVT::i32) {
uint32_t val = N->getZExtValue();
return ((val & 0x0000ffff) == val);
}
def hi16 : PatLeaf<(imm), [{
// hi16 predicate - returns true if the immediate has all zeros in the
// low order bits and is a 32-bit constant:
- if (N->getValueType(0) == EVT::i32) {
+ if (N->getValueType(0) == MVT::i32) {
uint32_t val = uint32_t(N->getZExtValue());
return ((val & 0xffff0000) == val);
- } else if (N->getValueType(0) == EVT::i64) {
+ } else if (N->getValueType(0) == MVT::i64) {
uint64_t val = N->getZExtValue();
return ((val & 0xffff0000ULL) == val);
}
// Does the SFP constant only have upp 16 bits set?
def hi16_f32 : PatLeaf<(fpimm), [{
- if (N->getValueType(0) == EVT::f32) {
+ if (N->getValueType(0) == MVT::f32) {
uint32_t val = FloatToBits(N->getValueAPF().convertToFloat());
return ((val & 0xffff0000) == val);
}
// Does the SFP constant fit into 18 bits?
def fpimm18 : PatLeaf<(fpimm), [{
- if (N->getValueType(0) == EVT::f32) {
+ if (N->getValueType(0) == MVT::f32) {
uint32_t Value = FloatToBits(N->getValueAPF().convertToFloat());
return ((Value & ((1 << 19) - 1)) == Value);
}
// immediate constant load for v16i8 vectors. N.B.: The incoming constant has
// to be a 16-bit quantity with the upper and lower bytes equal (e.g., 0x2a2a).
def v16i8SExt8Imm_xform: SDNodeXForm<build_vector, [{
- return SPU::get_vec_i8imm(N, *CurDAG, EVT::i8);
+ return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8);
}]>;
// v16i8SExt8Imm: Predicate test for 8-bit sign extended immediate constant
// incoming constant being a 16-bit quantity, where the upper and lower bytes
// are EXACTLY the same (e.g., 0x2a2a)
def v16i8SExt8Imm: PatLeaf<(build_vector), [{
- return SPU::get_vec_i8imm(N, *CurDAG, EVT::i8).getNode() != 0;
+ return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8).getNode() != 0;
}], v16i8SExt8Imm_xform>;
// v16i8U8Imm_xform function: convert build_vector to unsigned 8-bit
// immediate constant load for v16i8 vectors. N.B.: The incoming constant has
// to be a 16-bit quantity with the upper and lower bytes equal (e.g., 0x2a2a).
def v16i8U8Imm_xform: SDNodeXForm<build_vector, [{
- return SPU::get_vec_i8imm(N, *CurDAG, EVT::i8);
+ return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8);
}]>;
// v16i8U8Imm: Predicate test for unsigned 8-bit immediate constant
// incoming constant being a 16-bit quantity, where the upper and lower bytes
// are EXACTLY the same (e.g., 0x2a2a)
def v16i8U8Imm: PatLeaf<(build_vector), [{
- return SPU::get_vec_i8imm(N, *CurDAG, EVT::i8).getNode() != 0;
+ return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8).getNode() != 0;
}], v16i8U8Imm_xform>;
// v8i16SExt8Imm_xform function: convert build_vector to 8-bit sign extended
// immediate constant load for v8i16 vectors.
def v8i16SExt8Imm_xform: SDNodeXForm<build_vector, [{
- return SPU::get_vec_i8imm(N, *CurDAG, EVT::i16);
+ return SPU::get_vec_i8imm(N, *CurDAG, MVT::i16);
}]>;
// v8i16SExt8Imm: Predicate test for 8-bit sign extended immediate constant
// load, works in conjunction with its transform function.
def v8i16SExt8Imm: PatLeaf<(build_vector), [{
- return SPU::get_vec_i8imm(N, *CurDAG, EVT::i16).getNode() != 0;
+ return SPU::get_vec_i8imm(N, *CurDAG, MVT::i16).getNode() != 0;
}], v8i16SExt8Imm_xform>;
// v8i16SExt10Imm_xform function: convert build_vector to 16-bit sign extended
// immediate constant load for v8i16 vectors.
def v8i16SExt10Imm_xform: SDNodeXForm<build_vector, [{
- return SPU::get_vec_i10imm(N, *CurDAG, EVT::i16);
+ return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16);
}]>;
// v8i16SExt10Imm: Predicate test for 16-bit sign extended immediate constant
// load, works in conjunction with its transform function.
def v8i16SExt10Imm: PatLeaf<(build_vector), [{
- return SPU::get_vec_i10imm(N, *CurDAG, EVT::i16).getNode() != 0;
+ return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16).getNode() != 0;
}], v8i16SExt10Imm_xform>;
// v8i16Uns10Imm_xform function: convert build_vector to 16-bit unsigned
// immediate constant load for v8i16 vectors.
def v8i16Uns10Imm_xform: SDNodeXForm<build_vector, [{
- return SPU::get_vec_i10imm(N, *CurDAG, EVT::i16);
+ return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16);
}]>;
// v8i16Uns10Imm: Predicate test for 16-bit unsigned immediate constant
// load, works in conjunction with its transform function.
def v8i16Uns10Imm: PatLeaf<(build_vector), [{
- return SPU::get_vec_i10imm(N, *CurDAG, EVT::i16).getNode() != 0;
+ return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16).getNode() != 0;
}], v8i16Uns10Imm_xform>;
// v8i16SExt16Imm_xform function: convert build_vector to 16-bit sign extended
// immediate constant load for v8i16 vectors.
def v8i16Uns16Imm_xform: SDNodeXForm<build_vector, [{
- return SPU::get_vec_i16imm(N, *CurDAG, EVT::i16);
+ return SPU::get_vec_i16imm(N, *CurDAG, MVT::i16);
}]>;
// v8i16SExt16Imm: Predicate test for 16-bit sign extended immediate constant
// load, works in conjunction with its transform function.
def v8i16SExt16Imm: PatLeaf<(build_vector), [{
- return SPU::get_vec_i16imm(N, *CurDAG, EVT::i16).getNode() != 0;
+ return SPU::get_vec_i16imm(N, *CurDAG, MVT::i16).getNode() != 0;
}], v8i16Uns16Imm_xform>;
// v4i32SExt10Imm_xform function: convert build_vector to 10-bit sign extended
// immediate constant load for v4i32 vectors.
def v4i32SExt10Imm_xform: SDNodeXForm<build_vector, [{
- return SPU::get_vec_i10imm(N, *CurDAG, EVT::i32);
+ return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32);
}]>;
// v4i32SExt10Imm: Predicate test for 10-bit sign extended immediate constant
// load, works in conjunction with its transform function.
def v4i32SExt10Imm: PatLeaf<(build_vector), [{
- return SPU::get_vec_i10imm(N, *CurDAG, EVT::i32).getNode() != 0;
+ return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32).getNode() != 0;
}], v4i32SExt10Imm_xform>;
// v4i32Uns10Imm_xform function: convert build_vector to 10-bit unsigned
// immediate constant load for v4i32 vectors.
def v4i32Uns10Imm_xform: SDNodeXForm<build_vector, [{
- return SPU::get_vec_i10imm(N, *CurDAG, EVT::i32);
+ return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32);
}]>;
// v4i32Uns10Imm: Predicate test for 10-bit unsigned immediate constant
// load, works in conjunction with its transform function.
def v4i32Uns10Imm: PatLeaf<(build_vector), [{
- return SPU::get_vec_i10imm(N, *CurDAG, EVT::i32).getNode() != 0;
+ return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32).getNode() != 0;
}], v4i32Uns10Imm_xform>;
// v4i32SExt16Imm_xform function: convert build_vector to 16-bit sign extended
// immediate constant load for v4i32 vectors.
def v4i32SExt16Imm_xform: SDNodeXForm<build_vector, [{
- return SPU::get_vec_i16imm(N, *CurDAG, EVT::i32);
+ return SPU::get_vec_i16imm(N, *CurDAG, MVT::i32);
}]>;
// v4i32SExt16Imm: Predicate test for 16-bit sign extended immediate constant
// load, works in conjunction with its transform function.
def v4i32SExt16Imm: PatLeaf<(build_vector), [{
- return SPU::get_vec_i16imm(N, *CurDAG, EVT::i32).getNode() != 0;
+ return SPU::get_vec_i16imm(N, *CurDAG, MVT::i32).getNode() != 0;
}], v4i32SExt16Imm_xform>;
// v4i32Uns18Imm_xform function: convert build_vector to 18-bit unsigned
// immediate constant load for v4i32 vectors.
def v4i32Uns18Imm_xform: SDNodeXForm<build_vector, [{
- return SPU::get_vec_u18imm(N, *CurDAG, EVT::i32);
+ return SPU::get_vec_u18imm(N, *CurDAG, MVT::i32);
}]>;
// v4i32Uns18Imm: Predicate test for 18-bit unsigned immediate constant load,
// works in conjunction with its transform function.
def v4i32Uns18Imm: PatLeaf<(build_vector), [{
- return SPU::get_vec_u18imm(N, *CurDAG, EVT::i32).getNode() != 0;
+ return SPU::get_vec_u18imm(N, *CurDAG, MVT::i32).getNode() != 0;
}], v4i32Uns18Imm_xform>;
// ILHUvec_get_imm xform function: convert build_vector to ILHUvec imm constant
// load.
def ILHUvec_get_imm: SDNodeXForm<build_vector, [{
- return SPU::get_ILHUvec_imm(N, *CurDAG, EVT::i32);
+ return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i32);
}]>;
/// immILHUvec: Predicate test for a ILHU constant vector.
def immILHUvec: PatLeaf<(build_vector), [{
- return SPU::get_ILHUvec_imm(N, *CurDAG, EVT::i32).getNode() != 0;
+ return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i32).getNode() != 0;
}], ILHUvec_get_imm>;
// Catch-all for any other i32 vector constants
// v2i64SExt10Imm_xform function: convert build_vector to 10-bit sign extended
// immediate constant load for v2i64 vectors.
def v2i64SExt10Imm_xform: SDNodeXForm<build_vector, [{
- return SPU::get_vec_i10imm(N, *CurDAG, EVT::i64);
+ return SPU::get_vec_i10imm(N, *CurDAG, MVT::i64);
}]>;
// v2i64SExt10Imm: Predicate test for 10-bit sign extended immediate constant
// load, works in conjunction with its transform function.
def v2i64SExt10Imm: PatLeaf<(build_vector), [{
- return SPU::get_vec_i10imm(N, *CurDAG, EVT::i64).getNode() != 0;
+ return SPU::get_vec_i10imm(N, *CurDAG, MVT::i64).getNode() != 0;
}], v2i64SExt10Imm_xform>;
// v2i64SExt16Imm_xform function: convert build_vector to 16-bit sign extended
// immediate constant load for v2i64 vectors.
def v2i64SExt16Imm_xform: SDNodeXForm<build_vector, [{
- return SPU::get_vec_i16imm(N, *CurDAG, EVT::i64);
+ return SPU::get_vec_i16imm(N, *CurDAG, MVT::i64);
}]>;
// v2i64SExt16Imm: Predicate test for 16-bit sign extended immediate constant
// load, works in conjunction with its transform function.
def v2i64SExt16Imm: PatLeaf<(build_vector), [{
- return SPU::get_vec_i16imm(N, *CurDAG, EVT::i64).getNode() != 0;
+ return SPU::get_vec_i16imm(N, *CurDAG, MVT::i64).getNode() != 0;
}], v2i64SExt16Imm_xform>;
// v2i64Uns18Imm_xform function: convert build_vector to 18-bit unsigned
// immediate constant load for v2i64 vectors.
def v2i64Uns18Imm_xform: SDNodeXForm<build_vector, [{
- return SPU::get_vec_u18imm(N, *CurDAG, EVT::i64);
+ return SPU::get_vec_u18imm(N, *CurDAG, MVT::i64);
}]>;
// v2i64Uns18Imm: Predicate test for 18-bit unsigned immediate constant load,
// works in conjunction with its transform function.
def v2i64Uns18Imm: PatLeaf<(build_vector), [{
- return SPU::get_vec_u18imm(N, *CurDAG, EVT::i64).getNode() != 0;
+ return SPU::get_vec_u18imm(N, *CurDAG, MVT::i64).getNode() != 0;
}], v2i64Uns18Imm_xform>;
/// immILHUvec: Predicate test for a ILHU constant vector.
def immILHUvec_i64: PatLeaf<(build_vector), [{
- return SPU::get_ILHUvec_imm(N, *CurDAG, EVT::i64).getNode() != 0;
+ return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i64).getNode() != 0;
}], ILHUvec_get_imm>;
// Catch-all for any other i32 vector constants
index bb3439b1ae1cd701a2dc607b1b8821dc23618bd2..6dd3b2a2548550f651b70dfdd469079bd25c4b2c 100644 (file)
SDValue &Base, SDValue &Disp) {
// Try to match frame address first.
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
- Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), EVT::i16);
- Disp = CurDAG->getTargetConstant(0, EVT::i16);
+ Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i16);
+ Disp = CurDAG->getTargetConstant(0, MVT::i16);
return true;
}
if (((CVal << 48) >> 48) == CVal) {
SDValue N0 = Addr.getOperand(0);
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N0))
- Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), EVT::i16);
+ Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i16);
else
Base = N0;
- Disp = CurDAG->getTargetConstant(CVal, EVT::i16);
+ Disp = CurDAG->getTargetConstant(CVal, MVT::i16);
return true;
}
}
SDValue N0 = Addr.getOperand(0);
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
Base = CurDAG->getTargetGlobalAddress(G->getGlobal(),
- EVT::i16, G->getOffset());
- Disp = CurDAG->getTargetConstant(0, EVT::i16);
+ MVT::i16, G->getOffset());
+ Disp = CurDAG->getTargetConstant(0, MVT::i16);
return true;
} else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(N0)) {
- Base = CurDAG->getTargetExternalSymbol(E->getSymbol(), EVT::i16);
- Disp = CurDAG->getTargetConstant(0, EVT::i16);
+ Base = CurDAG->getTargetExternalSymbol(E->getSymbol(), MVT::i16);
+ Disp = CurDAG->getTargetConstant(0, MVT::i16);
}
break;
};
Base = Addr;
- Disp = CurDAG->getTargetConstant(0, EVT::i16);
+ Disp = CurDAG->getTargetConstant(0, MVT::i16);
return true;
}
switch (Node->getOpcode()) {
default: break;
case ISD::FrameIndex: {
- assert(Op.getValueType() == EVT::i16);
+ assert(Op.getValueType() == MVT::i16);
int FI = cast<FrameIndexSDNode>(Node)->getIndex();
- SDValue TFI = CurDAG->getTargetFrameIndex(FI, EVT::i16);
+ SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i16);
if (Node->hasOneUse())
- return CurDAG->SelectNodeTo(Node, MSP430::ADD16ri, EVT::i16,
- TFI, CurDAG->getTargetConstant(0, EVT::i16));
- return CurDAG->getTargetNode(MSP430::ADD16ri, dl, EVT::i16,
- TFI, CurDAG->getTargetConstant(0, EVT::i16));
+ return CurDAG->SelectNodeTo(Node, MSP430::ADD16ri, MVT::i16,
+ TFI, CurDAG->getTargetConstant(0, MVT::i16));
+ return CurDAG->getTargetNode(MSP430::ADD16ri, dl, MVT::i16,
+ TFI, CurDAG->getTargetConstant(0, MVT::i16));
}
}
index a5c4e9ffc5644cad0d85ea32f6ce019d7902d79c..6758b45a333b0cd1e1ae383f8fc0be09f7f3d226 100644 (file)
Subtarget(*tm.getSubtargetImpl()), TM(tm) {
// Set up the register classes.
- addRegisterClass(EVT::i8, MSP430::GR8RegisterClass);
- addRegisterClass(EVT::i16, MSP430::GR16RegisterClass);
+ addRegisterClass(MVT::i8, MSP430::GR8RegisterClass);
+ addRegisterClass(MVT::i16, MSP430::GR16RegisterClass);
// Compute derived properties from the register classes
computeRegisterProperties();
// Even if we have only 1 bit shift here, we can perform
// shifts of the whole bitwidth 1 bit per step.
- setShiftAmountType(EVT::i8);
+ setShiftAmountType(MVT::i8);
setStackPointerRegisterToSaveRestore(MSP430::SPW);
setBooleanContents(ZeroOrOneBooleanContent);
setSchedulingPreference(SchedulingForLatency);
- setLoadExtAction(ISD::EXTLOAD, EVT::i1, Promote);
- setLoadExtAction(ISD::SEXTLOAD, EVT::i1, Promote);
- setLoadExtAction(ISD::ZEXTLOAD, EVT::i1, Promote);
- setLoadExtAction(ISD::SEXTLOAD, EVT::i8, Expand);
- setLoadExtAction(ISD::SEXTLOAD, EVT::i16, Expand);
+ setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
+ setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
+ setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
+ setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
+ setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
// We don't have any truncstores
- setTruncStoreAction(EVT::i16, EVT::i8, Expand);
-
- setOperationAction(ISD::SRA, EVT::i8, Custom);
- setOperationAction(ISD::SHL, EVT::i8, Custom);
- setOperationAction(ISD::SRL, EVT::i8, Custom);
- setOperationAction(ISD::SRA, EVT::i16, Custom);
- setOperationAction(ISD::SHL, EVT::i16, Custom);
- setOperationAction(ISD::SRL, EVT::i16, Custom);
- setOperationAction(ISD::ROTL, EVT::i8, Expand);
- setOperationAction(ISD::ROTR, EVT::i8, Expand);
- setOperationAction(ISD::ROTL, EVT::i16, Expand);
- setOperationAction(ISD::ROTR, EVT::i16, Expand);
- setOperationAction(ISD::GlobalAddress, EVT::i16, Custom);
- setOperationAction(ISD::ExternalSymbol, EVT::i16, Custom);
- setOperationAction(ISD::BR_JT, EVT::Other, Expand);
- setOperationAction(ISD::BRIND, EVT::Other, Expand);
- setOperationAction(ISD::BR_CC, EVT::i8, Custom);
- setOperationAction(ISD::BR_CC, EVT::i16, Custom);
- setOperationAction(ISD::BRCOND, EVT::Other, Expand);
- setOperationAction(ISD::SETCC, EVT::i8, Expand);
- setOperationAction(ISD::SETCC, EVT::i16, Expand);
- setOperationAction(ISD::SELECT, EVT::i8, Expand);
- setOperationAction(ISD::SELECT, EVT::i16, Expand);
- setOperationAction(ISD::SELECT_CC, EVT::i8, Custom);
- setOperationAction(ISD::SELECT_CC, EVT::i16, Custom);
- setOperationAction(ISD::SIGN_EXTEND, EVT::i16, Custom);
-
- setOperationAction(ISD::CTTZ, EVT::i8, Expand);
- setOperationAction(ISD::CTTZ, EVT::i16, Expand);
- setOperationAction(ISD::CTLZ, EVT::i8, Expand);
- setOperationAction(ISD::CTLZ, EVT::i16, Expand);
- setOperationAction(ISD::CTPOP, EVT::i8, Expand);
- setOperationAction(ISD::CTPOP, EVT::i16, Expand);
-
- setOperationAction(ISD::SHL_PARTS, EVT::i8, Expand);
- setOperationAction(ISD::SHL_PARTS, EVT::i16, Expand);
- setOperationAction(ISD::SRL_PARTS, EVT::i8, Expand);
- setOperationAction(ISD::SRL_PARTS, EVT::i16, Expand);
- setOperationAction(ISD::SRA_PARTS, EVT::i8, Expand);
- setOperationAction(ISD::SRA_PARTS, EVT::i16, Expand);
-
- setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i1, Expand);
+ setTruncStoreAction(MVT::i16, MVT::i8, Expand);
+
+ setOperationAction(ISD::SRA, MVT::i8, Custom);
+ setOperationAction(ISD::SHL, MVT::i8, Custom);
+ setOperationAction(ISD::SRL, MVT::i8, Custom);
+ setOperationAction(ISD::SRA, MVT::i16, Custom);
+ setOperationAction(ISD::SHL, MVT::i16, Custom);
+ setOperationAction(ISD::SRL, MVT::i16, Custom);
+ setOperationAction(ISD::ROTL, MVT::i8, Expand);
+ setOperationAction(ISD::ROTR, MVT::i8, Expand);
+ setOperationAction(ISD::ROTL, MVT::i16, Expand);
+ setOperationAction(ISD::ROTR, MVT::i16, Expand);
+ setOperationAction(ISD::GlobalAddress, MVT::i16, Custom);
+ setOperationAction(ISD::ExternalSymbol, MVT::i16, Custom);
+ setOperationAction(ISD::BR_JT, MVT::Other, Expand);
+ setOperationAction(ISD::BRIND, MVT::Other, Expand);
+ setOperationAction(ISD::BR_CC, MVT::i8, Custom);
+ setOperationAction(ISD::BR_CC, MVT::i16, Custom);
+ setOperationAction(ISD::BRCOND, MVT::Other, Expand);
+ setOperationAction(ISD::SETCC, MVT::i8, Expand);
+ setOperationAction(ISD::SETCC, MVT::i16, Expand);
+ setOperationAction(ISD::SELECT, MVT::i8, Expand);
+ setOperationAction(ISD::SELECT, MVT::i16, Expand);
+ setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
+ setOperationAction(ISD::SELECT_CC, MVT::i16, Custom);
+ setOperationAction(ISD::SIGN_EXTEND, MVT::i16, Custom);
+
+ setOperationAction(ISD::CTTZ, MVT::i8, Expand);
+ setOperationAction(ISD::CTTZ, MVT::i16, Expand);
+ setOperationAction(ISD::CTLZ, MVT::i8, Expand);
+ setOperationAction(ISD::CTLZ, MVT::i16, Expand);
+ setOperationAction(ISD::CTPOP, MVT::i8, Expand);
+ setOperationAction(ISD::CTPOP, MVT::i16, Expand);
+
+ setOperationAction(ISD::SHL_PARTS, MVT::i8, Expand);
+ setOperationAction(ISD::SHL_PARTS, MVT::i16, Expand);
+ setOperationAction(ISD::SRL_PARTS, MVT::i8, Expand);
+ setOperationAction(ISD::SRL_PARTS, MVT::i16, Expand);
+ setOperationAction(ISD::SRA_PARTS, MVT::i8, Expand);
+ setOperationAction(ISD::SRA_PARTS, MVT::i16, Expand);
+
+ setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
// FIXME: Implement efficiently multiplication by a constant
- setOperationAction(ISD::MUL, EVT::i16, Expand);
- setOperationAction(ISD::MULHS, EVT::i16, Expand);
- setOperationAction(ISD::MULHU, EVT::i16, Expand);
- setOperationAction(ISD::SMUL_LOHI, EVT::i16, Expand);
- setOperationAction(ISD::UMUL_LOHI, EVT::i16, Expand);
-
- setOperationAction(ISD::UDIV, EVT::i16, Expand);
- setOperationAction(ISD::UDIVREM, EVT::i16, Expand);
- setOperationAction(ISD::UREM, EVT::i16, Expand);
- setOperationAction(ISD::SDIV, EVT::i16, Expand);
- setOperationAction(ISD::SDIVREM, EVT::i16, Expand);
- setOperationAction(ISD::SREM, EVT::i16, Expand);
+ setOperationAction(ISD::MUL, MVT::i16, Expand);
+ setOperationAction(ISD::MULHS, MVT::i16, Expand);
+ setOperationAction(ISD::MULHU, MVT::i16, Expand);
+ setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand);
+ setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand);
+
+ setOperationAction(ISD::UDIV, MVT::i16, Expand);
+ setOperationAction(ISD::UDIVREM, MVT::i16, Expand);
+ setOperationAction(ISD::UREM, MVT::i16, Expand);
+ setOperationAction(ISD::SDIV, MVT::i16, Expand);
+ setOperationAction(ISD::SDIVREM, MVT::i16, Expand);
+ setOperationAction(ISD::SREM, MVT::i16, Expand);
}
SDValue MSP430TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
if (VA.isRegLoc()) {
// Arguments passed in registers
EVT RegVT = VA.getLocVT();
- switch (RegVT.getSimpleVT()) {
+ switch (RegVT.getSimpleVT().SimpleTy) {
default:
{
#ifndef NDEBUG
cerr << "LowerFormalArguments Unhandled argument type: "
- << RegVT.getSimpleVT() << "\n";
+ << RegVT.getSimpleVT().SimpleTy << "\n";
#endif
llvm_unreachable(0);
}
- case EVT::i16:
+ case MVT::i16:
unsigned VReg =
RegInfo.createVirtualRegister(MSP430::GR16RegisterClass);
RegInfo.addLiveIn(VA.getLocReg(), VReg);
unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
if (ObjSize > 2) {
cerr << "LowerFormalArguments Unhandled argument type: "
- << VA.getLocVT().getSimpleVT()
+ << VA.getLocVT().getSimpleVT().SimpleTy
<< "\n";
}
// Create the frame index object for this incoming parameter...
// Create the SelectionDAG nodes corresponding to a load
//from this parameter
- SDValue FIN = DAG.getFrameIndex(FI, EVT::i16);
+ SDValue FIN = DAG.getFrameIndex(FI, MVT::i16);
InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
PseudoSourceValue::getFixedStack(FI), 0));
}
}
if (Flag.getNode())
- return DAG.getNode(MSP430ISD::RET_FLAG, dl, EVT::Other, Chain, Flag);
+ return DAG.getNode(MSP430ISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
// Return Void
- return DAG.getNode(MSP430ISD::RET_FLAG, dl, EVT::Other, Chain);
+ return DAG.getNode(MSP430ISD::RET_FLAG, dl, MVT::Other, Chain);
}
/// LowerCCCCallTo - functions arguments are copied from virtual regs to
// Transform all store nodes into one single node because all store nodes are
// independent of each other.
if (!MemOpChains.empty())
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&MemOpChains[0], MemOpChains.size());
// Build a sequence of copy-to-reg nodes chained together with token chain and
// turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
// Likewise ExternalSymbol -> TargetExternalSymbol.
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
- Callee = DAG.getTargetGlobalAddress(G->getGlobal(), EVT::i16);
+ Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i16);
else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
- Callee = DAG.getTargetExternalSymbol(E->getSymbol(), EVT::i16);
+ Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16);
// Returns a chain & a flag for retval copy to use.
- SDVTList NodeTys = DAG.getVTList(EVT::Other, EVT::Flag);
+ SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
SmallVector<SDValue, 8> Ops;
Ops.push_back(Chain);
Ops.push_back(Callee);
break;
}
- return DAG.getNode(MSP430ISD::CMP, dl, EVT::Flag, LHS, RHS);
+ return DAG.getNode(MSP430ISD::CMP, dl, MVT::Flag, LHS, RHS);
}
return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(),
Chain,
- Dest, DAG.getConstant(TargetCC, EVT::i8),
+ Dest, DAG.getConstant(TargetCC, MVT::i8),
Flag);
}
unsigned TargetCC = MSP430::COND_INVALID;
SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
- SDVTList VTs = DAG.getVTList(Op.getValueType(), EVT::Flag);
+ SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
SmallVector<SDValue, 4> Ops;
Ops.push_back(TrueV);
Ops.push_back(FalseV);
- Ops.push_back(DAG.getConstant(TargetCC, EVT::i8));
+ Ops.push_back(DAG.getConstant(TargetCC, MVT::i8));
Ops.push_back(Flag);
return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size());
EVT VT = Op.getValueType();
DebugLoc dl = Op.getDebugLoc();
- assert(VT == EVT::i16 && "Only support i16 for now!");
+ assert(VT == MVT::i16 && "Only support i16 for now!");
return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT,
DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val),
index b03f7859c79ff81be66d0b34d2c548386e9498d4..bdf9aa473b4a7fc4d35cded4211b538a216267dd 100644 (file)
// getI32Imm - Return a target constant with the specified
// value, of type i32.
inline SDValue getI32Imm(unsigned Imm) {
- return CurDAG->getTargetConstant(Imm, EVT::i32);
+ return CurDAG->getTargetConstant(Imm, MVT::i32);
}
{
// if Address is FI, get the TargetFrameIndex.
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
- Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), EVT::i32);
- Offset = CurDAG->getTargetConstant(0, EVT::i32);
+ Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
+ Offset = CurDAG->getTargetConstant(0, MVT::i32);
return true;
}
if (TM.getRelocationModel() == Reloc::PIC_) {
if ((Addr.getOpcode() == ISD::TargetGlobalAddress) ||
(Addr.getOpcode() == ISD::TargetJumpTable)){
- Base = CurDAG->getRegister(Mips::GP, EVT::i32);
+ Base = CurDAG->getRegister(Mips::GP, MVT::i32);
Offset = Addr;
return true;
}
// If the first operand is a FI, get the TargetFI Node
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
(Addr.getOperand(0))) {
- Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), EVT::i32);
+ Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
} else {
Base = Addr.getOperand(0);
}
- Offset = CurDAG->getTargetConstant(CN->getZExtValue(), EVT::i32);
+ Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
return true;
}
}
}
Base = Addr;
- Offset = CurDAG->getTargetConstant(0, EVT::i32);
+ Offset = CurDAG->getTargetConstant(0, MVT::i32);
return true;
}
SDNode *AddCarry = CurDAG->getTargetNode(Mips::ADDu, dl, VT,
SDValue(Carry,0), RHS);
- return CurDAG->SelectNodeTo(N.getNode(), MOp, VT, EVT::Flag,
+ return CurDAG->SelectNodeTo(N.getNode(), MOp, VT, MVT::Flag,
LHS, SDValue(AddCarry,0));
}
else
Op = (Opcode == ISD::UDIVREM ? Mips::DIVu : Mips::DIV);
- SDNode *Node = CurDAG->getTargetNode(Op, dl, EVT::Flag, Op1, Op2);
+ SDNode *Node = CurDAG->getTargetNode(Op, dl, MVT::Flag, Op1, Op2);
SDValue InFlag = SDValue(Node, 0);
- SDNode *Lo = CurDAG->getTargetNode(Mips::MFLO, dl, EVT::i32,
- EVT::Flag, InFlag);
+ SDNode *Lo = CurDAG->getTargetNode(Mips::MFLO, dl, MVT::i32,
+ MVT::Flag, InFlag);
InFlag = SDValue(Lo,1);
- SDNode *Hi = CurDAG->getTargetNode(Mips::MFHI, dl, EVT::i32, InFlag);
+ SDNode *Hi = CurDAG->getTargetNode(Mips::MFHI, dl, MVT::i32, InFlag);
if (!N.getValue(0).use_empty())
ReplaceUses(N.getValue(0), SDValue(Lo,0));
unsigned MulOp = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT);
SDNode *MulNode = CurDAG->getTargetNode(MulOp, dl,
- EVT::Flag, MulOp1, MulOp2);
+ MVT::Flag, MulOp1, MulOp2);
SDValue InFlag = SDValue(MulNode, 0);
if (MulOp == ISD::MUL)
- return CurDAG->getTargetNode(Mips::MFLO, dl, EVT::i32, InFlag);
+ return CurDAG->getTargetNode(Mips::MFLO, dl, MVT::i32, InFlag);
else
- return CurDAG->getTargetNode(Mips::MFHI, dl, EVT::i32, InFlag);
+ return CurDAG->getTargetNode(Mips::MFHI, dl, MVT::i32, InFlag);
}
/// Div/Rem operations
Op = (Opcode == ISD::SREM ? Mips::DIV : Mips::DIVu);
MOp = Mips::MFHI;
}
- SDNode *Node = CurDAG->getTargetNode(Op, dl, EVT::Flag, Op1, Op2);
+ SDNode *Node = CurDAG->getTargetNode(Op, dl, MVT::Flag, Op1, Op2);
SDValue InFlag = SDValue(Node, 0);
- return CurDAG->getTargetNode(MOp, dl, EVT::i32, InFlag);
+ return CurDAG->getTargetNode(MOp, dl, MVT::i32, InFlag);
}
// Get target GOT address.
//bool isCodeLarge = (TM.getCodeModel() == CodeModel::Large);
SDValue Chain = Node->getOperand(0);
SDValue Callee = Node->getOperand(1);
- SDValue T9Reg = CurDAG->getRegister(Mips::T9, EVT::i32);
+ SDValue T9Reg = CurDAG->getRegister(Mips::T9, MVT::i32);
SDValue InFlag(0, 0);
if ( (isa<GlobalAddressSDNode>(Callee)) ||
(isa<ExternalSymbolSDNode>(Callee)) )
{
/// Direct call for global addresses and external symbols
- SDValue GPReg = CurDAG->getRegister(Mips::GP, EVT::i32);
+ SDValue GPReg = CurDAG->getRegister(Mips::GP, MVT::i32);
// Use load to get GOT target
SDValue Ops[] = { Callee, GPReg, Chain };
- SDValue Load = SDValue(CurDAG->getTargetNode(Mips::LW, dl, EVT::i32,
- EVT::Other, Ops, 3), 0);
+ SDValue Load = SDValue(CurDAG->getTargetNode(Mips::LW, dl, MVT::i32,
+ MVT::Other, Ops, 3), 0);
Chain = Load.getValue(1);
// Call target must be on T9
Chain = CurDAG->getCopyToReg(Chain, dl, T9Reg, Callee, InFlag);
// Emit Jump and Link Register
- SDNode *ResNode = CurDAG->getTargetNode(Mips::JALR, dl, EVT::Other,
- EVT::Flag, T9Reg, Chain);
+ SDNode *ResNode = CurDAG->getTargetNode(Mips::JALR, dl, MVT::Other,
+ MVT::Flag, T9Reg, Chain);
Chain = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
ReplaceUses(SDValue(Node, 0), Chain);
index 005827266d63cb5fad18be6dafe9bd034c54473e..b05de6d3136370968074142be70bc295cfe85b1e 100644 (file)
setUsesGlobalOffsetTable(true);
// Set up the register classes
- addRegisterClass(EVT::i32, Mips::CPURegsRegisterClass);
- addRegisterClass(EVT::f32, Mips::FGR32RegisterClass);
+ addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
+ addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
// When dealing with single precision only, use libcalls
if (!Subtarget->isSingleFloat())
if (!Subtarget->isFP64bit())
- addRegisterClass(EVT::f64, Mips::AFGR64RegisterClass);
+ addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
// Legal fp constants
addLegalFPImmediate(APFloat(+0.0f));
// Load extented operations for i1 types must be promoted
- setLoadExtAction(ISD::EXTLOAD, EVT::i1, Promote);
- setLoadExtAction(ISD::ZEXTLOAD, EVT::i1, Promote);
- setLoadExtAction(ISD::SEXTLOAD, EVT::i1, Promote);
+ setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
+ setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
+ setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
// MIPS doesn't have extending float->double load/store
- setLoadExtAction(ISD::EXTLOAD, EVT::f32, Expand);
- setTruncStoreAction(EVT::f64, EVT::f32, Expand);
+ setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
+ setTruncStoreAction(MVT::f64, MVT::f32, Expand);
// Used by legalize types to correctly generate the setcc result.
// Without this, every float setcc comes with a AND/OR with the result,
// we don't want this, since the fpcmp result goes to a flag register,
// which is used implicitly by brcond and select operations.
- AddPromotedToType(ISD::SETCC, EVT::i1, EVT::i32);
+ AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
// Mips Custom Operations
- setOperationAction(ISD::GlobalAddress, EVT::i32, Custom);
- setOperationAction(ISD::GlobalTLSAddress, EVT::i32, Custom);
- setOperationAction(ISD::JumpTable, EVT::i32, Custom);
- setOperationAction(ISD::ConstantPool, EVT::i32, Custom);
- setOperationAction(ISD::SELECT, EVT::f32, Custom);
- setOperationAction(ISD::SELECT, EVT::f64, Custom);
- setOperationAction(ISD::SELECT, EVT::i32, Custom);
- setOperationAction(ISD::SETCC, EVT::f32, Custom);
- setOperationAction(ISD::SETCC, EVT::f64, Custom);
- setOperationAction(ISD::BRCOND, EVT::Other, Custom);
- setOperationAction(ISD::DYNAMIC_STACKALLOC, EVT::i32, Custom);
- setOperationAction(ISD::FP_TO_SINT, EVT::i32, Custom);
+ setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
+ setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
+ setOperationAction(ISD::JumpTable, MVT::i32, Custom);
+ setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
+ setOperationAction(ISD::SELECT, MVT::f32, Custom);
+ setOperationAction(ISD::SELECT, MVT::f64, Custom);
+ setOperationAction(ISD::SELECT, MVT::i32, Custom);
+ setOperationAction(ISD::SETCC, MVT::f32, Custom);
+ setOperationAction(ISD::SETCC, MVT::f64, Custom);
+ setOperationAction(ISD::BRCOND, MVT::Other, Custom);
+ setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
+ setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
// We custom lower AND/OR to handle the case where the DAG contain 'ands/ors'
// with operands comming from setcc fp comparions. This is necessary since
// the result from these setcc are in a flag registers (FCR31).
- setOperationAction(ISD::AND, EVT::i32, Custom);
- setOperationAction(ISD::OR, EVT::i32, Custom);
+ setOperationAction(ISD::AND, MVT::i32, Custom);
+ setOperationAction(ISD::OR, MVT::i32, Custom);
// Operations not directly supported by Mips.
- setOperationAction(ISD::BR_JT, EVT::Other, Expand);
- setOperationAction(ISD::BR_CC, EVT::Other, Expand);
- setOperationAction(ISD::SELECT_CC, EVT::Other, Expand);
- setOperationAction(ISD::UINT_TO_FP, EVT::i32, Expand);
- setOperationAction(ISD::FP_TO_UINT, EVT::i32, Expand);
- setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i1, Expand);
- setOperationAction(ISD::CTPOP, EVT::i32, Expand);
- setOperationAction(ISD::CTTZ, EVT::i32, Expand);
- setOperationAction(ISD::ROTL, EVT::i32, Expand);
- setOperationAction(ISD::ROTR, EVT::i32, Expand);
- setOperationAction(ISD::SHL_PARTS, EVT::i32, Expand);
- setOperationAction(ISD::SRA_PARTS, EVT::i32, Expand);
- setOperationAction(ISD::SRL_PARTS, EVT::i32, Expand);
- setOperationAction(ISD::FCOPYSIGN, EVT::f32, Expand);
- setOperationAction(ISD::FCOPYSIGN, EVT::f64, Expand);
- setOperationAction(ISD::FSIN, EVT::f32, Expand);
- setOperationAction(ISD::FCOS, EVT::f32, Expand);
- setOperationAction(ISD::FPOWI, EVT::f32, Expand);
- setOperationAction(ISD::FPOW, EVT::f32, Expand);
- setOperationAction(ISD::FLOG, EVT::f32, Expand);
- setOperationAction(ISD::FLOG2, EVT::f32, Expand);
- setOperationAction(ISD::FLOG10, EVT::f32, Expand);
- setOperationAction(ISD::FEXP, EVT::f32, Expand);
+ setOperationAction(ISD::BR_JT, MVT::Other, Expand);
+ setOperationAction(ISD::BR_CC, MVT::Other, Expand);
+ setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
+ setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
+ setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
+ setOperationAction(ISD::CTPOP, MVT::i32, Expand);
+ setOperationAction(ISD::CTTZ, MVT::i32, Expand);
+ setOperationAction(ISD::ROTL, MVT::i32, Expand);
+ setOperationAction(ISD::ROTR, MVT::i32, Expand);
+ setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
+ setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
+ setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
+ setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
+ setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
+ setOperationAction(ISD::FSIN, MVT::f32, Expand);
+ setOperationAction(ISD::FCOS, MVT::f32, Expand);
+ setOperationAction(ISD::FPOWI, MVT::f32, Expand);
+ setOperationAction(ISD::FPOW, MVT::f32, Expand);
+ setOperationAction(ISD::FLOG, MVT::f32, Expand);
+ setOperationAction(ISD::FLOG2, MVT::f32, Expand);
+ setOperationAction(ISD::FLOG10, MVT::f32, Expand);
+ setOperationAction(ISD::FEXP, MVT::f32, Expand);
// We don't have line number support yet.
- setOperationAction(ISD::DBG_STOPPOINT, EVT::Other, Expand);
- setOperationAction(ISD::DEBUG_LOC, EVT::Other, Expand);
- setOperationAction(ISD::DBG_LABEL, EVT::Other, Expand);
- setOperationAction(ISD::EH_LABEL, EVT::Other, Expand);
+ setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
+ setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
+ setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
+ setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
// Use the default for now
- setOperationAction(ISD::STACKSAVE, EVT::Other, Expand);
- setOperationAction(ISD::STACKRESTORE, EVT::Other, Expand);
- setOperationAction(ISD::MEMBARRIER, EVT::Other, Expand);
+ setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
+ setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
+ setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
if (Subtarget->isSingleFloat())
- setOperationAction(ISD::SELECT_CC, EVT::f64, Expand);
+ setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
if (!Subtarget->hasSEInReg()) {
- setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i8, Expand);
- setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i16, Expand);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
}
if (!Subtarget->hasBitCount())
- setOperationAction(ISD::CTLZ, EVT::i32, Expand);
+ setOperationAction(ISD::CTLZ, MVT::i32, Expand);
if (!Subtarget->hasSwap())
- setOperationAction(ISD::BSWAP, EVT::i32, Expand);
+ setOperationAction(ISD::BSWAP, MVT::i32, Expand);
setStackPointerRegisterToSaveRestore(Mips::SP);
computeRegisterProperties();
}
-EVT::SimpleValueType MipsTargetLowering::getSetCCResultType(EVT VT) const {
- return EVT::i32;
+MVT::SimpleValueType MipsTargetLowering::getSetCCResultType(EVT VT) const {
+ return MVT::i32;
}
/// getFunctionAlignment - Return the Log2 alignment of this function.
SDValue Src = Op.getOperand(0);
// Set the condition register
- SDValue CondReg = DAG.getCopyFromReg(Chain, dl, CCReg, EVT::i32);
+ SDValue CondReg = DAG.getCopyFromReg(Chain, dl, CCReg, MVT::i32);
CondReg = DAG.getCopyToReg(Chain, dl, Mips::AT, CondReg);
- CondReg = DAG.getCopyFromReg(CondReg, dl, Mips::AT, EVT::i32);
+ CondReg = DAG.getCopyFromReg(CondReg, dl, Mips::AT, MVT::i32);
- SDValue Cst = DAG.getConstant(3, EVT::i32);
- SDValue Or = DAG.getNode(ISD::OR, dl, EVT::i32, CondReg, Cst);
- Cst = DAG.getConstant(2, EVT::i32);
- SDValue Xor = DAG.getNode(ISD::XOR, dl, EVT::i32, Or, Cst);
+ SDValue Cst = DAG.getConstant(3, MVT::i32);
+ SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i32, CondReg, Cst);
+ Cst = DAG.getConstant(2, MVT::i32);
+ SDValue Xor = DAG.getNode(ISD::XOR, dl, MVT::i32, Or, Cst);
SDValue InFlag(0, 0);
CondReg = DAG.getCopyToReg(Chain, dl, Mips::FCR31, Xor, InFlag);
// Emit the round instruction and bit convert to integer
- SDValue Trunc = DAG.getNode(MipsISD::FPRound, dl, EVT::f32,
+ SDValue Trunc = DAG.getNode(MipsISD::FPRound, dl, MVT::f32,
Src, CondReg.getValue(1));
- SDValue BitCvt = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, Trunc);
+ SDValue BitCvt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Trunc);
return BitCvt;
}
DebugLoc dl = Op.getDebugLoc();
// Get a reference from Mips stack pointer
- SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, Mips::SP, EVT::i32);
+ SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, Mips::SP, MVT::i32);
// Subtract the dynamic size from the actual stack size to
// obtain the new stack size.
- SDValue Sub = DAG.getNode(ISD::SUB, dl, EVT::i32, StackPointer, Size);
+ SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size);
// The Sub result contains the new stack start address, so it
// must be placed in the stack pointer register.
if (LHS.getOpcode() != MipsISD::FPCmp || RHS.getOpcode() != MipsISD::FPCmp)
return Op;
- SDValue True = DAG.getConstant(1, EVT::i32);
- SDValue False = DAG.getConstant(0, EVT::i32);
+ SDValue True = DAG.getConstant(1, MVT::i32);
+ SDValue False = DAG.getConstant(0, MVT::i32);
SDValue LSEL = DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
LHS, True, False, LHS.getOperand(2));
SDValue RSEL = DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
RHS, True, False, RHS.getOperand(2));
- return DAG.getNode(Op.getOpcode(), dl, EVT::i32, LSEL, RSEL);
+ return DAG.getNode(Op.getOpcode(), dl, MVT::i32, LSEL, RSEL);
}
SDValue MipsTargetLowering::
SDValue CCNode = CondRes.getOperand(2);
Mips::CondCode CC =
(Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
- SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), EVT::i32);
+ SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode,
Dest, CondRes);
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
return DAG.getNode(MipsISD::FPCmp, dl, Op.getValueType(), LHS, RHS,
- DAG.getConstant(FPCondCCodeToFCC(CC), EVT::i32));
+ DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
}
SDValue MipsTargetLowering::
// FIXME there isn't actually debug info here
DebugLoc dl = Op.getDebugLoc();
GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
- SDValue GA = DAG.getTargetGlobalAddress(GV, EVT::i32);
+ SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
// %hi/%lo relocation
- SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, EVT::i32, GA);
- SDValue Lo = DAG.getNode(MipsISD::Lo, dl, EVT::i32, GA);
- return DAG.getNode(ISD::ADD, dl, EVT::i32, HiPart, Lo);
+ SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, GA);
+ SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA);
+ return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
} else { // Abicall relocations, TODO: make this cleaner.
- SDValue ResNode = DAG.getLoad(EVT::i32, dl,
+ SDValue ResNode = DAG.getLoad(MVT::i32, dl,
DAG.getEntryNode(), GA, NULL, 0);
// On functions and global targets not internal linked only
// a load from got/GP is necessary for PIC to work.
if (!GV->hasLocalLinkage() || isa<Function>(GV))
return ResNode;
- SDValue Lo = DAG.getNode(MipsISD::Lo, dl, EVT::i32, GA);
- return DAG.getNode(ISD::ADD, dl, EVT::i32, ResNode, Lo);
+ SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA);
+ return DAG.getNode(ISD::ADD, dl, MVT::i32, ResNode, Lo);
}
llvm_unreachable("Dont know how to handle GlobalAddress");
SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
- SDVTList VTs = DAG.getVTList(EVT::i32);
+ SDVTList VTs = DAG.getVTList(MVT::i32);
SDValue Ops[] = { JTI };
HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, Ops, 1);
} else // Emit Load from Global Pointer
- HiPart = DAG.getLoad(EVT::i32, dl, DAG.getEntryNode(), JTI, NULL, 0);
+ HiPart = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), JTI, NULL, 0);
- SDValue Lo = DAG.getNode(MipsISD::Lo, dl, EVT::i32, JTI);
- ResNode = DAG.getNode(ISD::ADD, dl, EVT::i32, HiPart, Lo);
+ SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, JTI);
+ ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
return ResNode;
}
SDValue ResNode;
ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
Constant *C = N->getConstVal();
- SDValue CP = DAG.getTargetConstantPool(C, EVT::i32, N->getAlignment());
+ SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment());
// FIXME there isn't actually debug info here
DebugLoc dl = Op.getDebugLoc();
// hacking it. This feature should come soon so we can uncomment the
// stuff below.
//if (IsInSmallSection(C->getType())) {
- // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, EVT::i32, CP);
- // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(EVT::i32);
- // ResNode = DAG.getNode(ISD::ADD, EVT::i32, GOT, GPRelNode);
+ // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
+ // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
+ // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
//} else { // %hi/%lo relocation
- SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, EVT::i32, CP);
- SDValue Lo = DAG.getNode(MipsISD::Lo, dl, EVT::i32, CP);
- ResNode = DAG.getNode(ISD::ADD, dl, EVT::i32, HiPart, Lo);
+ SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CP);
+ SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CP);
+ ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
//}
return ResNode;
bool IntRegUsed = (IntRegs[UnallocIntReg] != (unsigned (Mips::A0)));
// Promote i8 and i16
- if (LocVT == EVT::i8 || LocVT == EVT::i16) {
- LocVT = EVT::i32;
+ if (LocVT == MVT::i8 || LocVT == MVT::i16) {
+ LocVT = MVT::i32;
if (ArgFlags.isSExt())
LocInfo = CCValAssign::SExt;
else if (ArgFlags.isZExt())
LocInfo = CCValAssign::AExt;
}
- if (ValVT == EVT::i32 || (ValVT == EVT::f32 && IntRegUsed)) {
+ if (ValVT == MVT::i32 || (ValVT == MVT::f32 && IntRegUsed)) {
Reg = State.AllocateReg(IntRegs, IntRegsSize);
IntRegUsed = true;
- LocVT = EVT::i32;
+ LocVT = MVT::i32;
}
if (ValVT.isFloatingPoint() && !IntRegUsed) {
- if (ValVT == EVT::f32)
+ if (ValVT == MVT::f32)
Reg = State.AllocateReg(F32Regs, FloatRegsSize);
else
Reg = State.AllocateReg(F64Regs, FloatRegsSize);
}
- if (ValVT == EVT::f64 && IntRegUsed) {
+ if (ValVT == MVT::f64 && IntRegUsed) {
if (UnallocIntReg != IntRegsSize) {
// If we hit register A3 as the first not allocated, we must
// mark it as allocated (shadow) and use the stack instead.
for (;UnallocIntReg < IntRegsSize; ++UnallocIntReg)
State.AllocateReg(UnallocIntReg);
}
- LocVT = EVT::i32;
+ LocVT = MVT::i32;
}
if (!Reg) {
// To meet O32 ABI, Mips must always allocate 16 bytes on
// the stack (even if less than 4 are used as arguments)
if (Subtarget->isABI_O32()) {
- int VTsize = EVT(EVT::i32).getSizeInBits()/8;
+ int VTsize = EVT(MVT::i32).getSizeInBits()/8;
MFI->CreateFixedObject(VTsize, (VTsize*3));
CCInfo.AnalyzeCallOperands(Outs, CC_MipsO32);
} else
default: llvm_unreachable("Unknown loc info!");
case CCValAssign::Full:
if (Subtarget->isABI_O32() && VA.isRegLoc()) {
- if (VA.getValVT() == EVT::f32 && VA.getLocVT() == EVT::i32)
- Arg = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, Arg);
- if (VA.getValVT() == EVT::f64 && VA.getLocVT() == EVT::i32) {
- Arg = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i64, Arg);
- SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32, Arg,
+ if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i32)
+ Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Arg);
+ if (VA.getValVT() == MVT::f64 && VA.getLocVT() == MVT::i32) {
+ Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
+ SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg,
DAG.getConstant(0, getPointerTy()));
- SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32, Arg,
+ SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg,
DAG.getConstant(1, getPointerTy()));
RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo));
RegsToPass.push_back(std::make_pair(VA.getLocReg()+1, Hi));
// Transform all store nodes into one single node because all store
// nodes are independent of each other.
if (!MemOpChains.empty())
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&MemOpChains[0], MemOpChains.size());
// Build a sequence of copy-to-reg nodes chained together with token
// = Chain, Callee, Reg#1, Reg#2, ...
//
// Returns a chain & a flag for retval copy to use.
- SDVTList NodeTys = DAG.getVTList(EVT::Other, EVT::Flag);
+ SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
SmallVector<SDValue, 8> Ops;
Ops.push_back(Chain);
Ops.push_back(Callee);
// Reload GP value.
FI = MipsFI->getGPFI();
SDValue FIN = DAG.getFrameIndex(FI,getPointerTy());
- SDValue GPLoad = DAG.getLoad(EVT::i32, dl, Chain, FIN, NULL, 0);
+ SDValue GPLoad = DAG.getLoad(MVT::i32, dl, Chain, FIN, NULL, 0);
Chain = GPLoad.getValue(1);
- Chain = DAG.getCopyToReg(Chain, dl, DAG.getRegister(Mips::GP, EVT::i32),
+ Chain = DAG.getCopyToReg(Chain, dl, DAG.getRegister(Mips::GP, MVT::i32),
GPLoad, SDValue(0,0));
InFlag = Chain.getValue(1);
}
EVT RegVT = VA.getLocVT();
TargetRegisterClass *RC = 0;
- if (RegVT == EVT::i32)
+ if (RegVT == MVT::i32)
RC = Mips::CPURegsRegisterClass;
- else if (RegVT == EVT::f32)
+ else if (RegVT == MVT::f32)
RC = Mips::FGR32RegisterClass;
- else if (RegVT == EVT::f64) {
+ else if (RegVT == MVT::f64) {
if (!Subtarget->isSingleFloat())
RC = Mips::AFGR64RegisterClass;
} else
// Handle O32 ABI cases: i32->f32 and (i32,i32)->f64
if (Subtarget->isABI_O32()) {
- if (RegVT == EVT::i32 && VA.getValVT() == EVT::f32)
- ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, ArgValue);
- if (RegVT == EVT::i32 && VA.getValVT() == EVT::f64) {
+ if (RegVT == MVT::i32 && VA.getValVT() == MVT::f32)
+ ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue);
+ if (RegVT == MVT::i32 && VA.getValVT() == MVT::f64) {
unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(),
VA.getLocReg()+1, RC);
SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT);
- SDValue Hi = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, ArgValue);
- SDValue Lo = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, ArgValue2);
- ArgValue = DAG.getNode(ISD::BUILD_PAIR, dl, EVT::f64, Lo, Hi);
+ SDValue Hi = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue);
+ SDValue Lo = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue2);
+ ArgValue = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::f64, Lo, Hi);
}
}
if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
unsigned Reg = MipsFI->getSRetReturnReg();
if (!Reg) {
- Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(EVT::i32));
+ Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
MipsFI->setSRetReturnReg(Reg);
}
SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Copy, Chain);
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
}
return Chain;
// Return on Mips is always a "jr $ra"
if (Flag.getNode())
- return DAG.getNode(MipsISD::Ret, dl, EVT::Other,
- Chain, DAG.getRegister(Mips::RA, EVT::i32), Flag);
+ return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
+ Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
else // Return Void
- return DAG.getNode(MipsISD::Ret, dl, EVT::Other,
- Chain, DAG.getRegister(Mips::RA, EVT::i32));
+ return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
+ Chain, DAG.getRegister(Mips::RA, MVT::i32));
}
//===----------------------------------------------------------------------===//
case 'r':
return std::make_pair(0U, Mips::CPURegsRegisterClass);
case 'f':
- if (VT == EVT::f32)
+ if (VT == MVT::f32)
return std::make_pair(0U, Mips::FGR32RegisterClass);
- if (VT == EVT::f64)
+ if (VT == MVT::f64)
if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
return std::make_pair(0U, Mips::AFGR64RegisterClass);
}
Mips::T8, 0);
case 'f':
- if (VT == EVT::f32) {
+ if (VT == MVT::f32) {
if (Subtarget->isSingleFloat())
return make_vector<unsigned>(Mips::F2, Mips::F3, Mips::F4, Mips::F5,
Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11,
Mips::F28, Mips::F30, 0);
}
- if (VT == EVT::f64)
+ if (VT == MVT::f64)
if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
return make_vector<unsigned>(Mips::D1, Mips::D2, Mips::D3, Mips::D4,
Mips::D5, Mips::D10, Mips::D11, Mips::D12, Mips::D13,
index 667356ac683e259a9cc6c37b32aaf56ca9aa8028..656abe58404e408eea4d06e7dcf4ca4c74759918 100644 (file)
virtual const char *getTargetNodeName(unsigned Opcode) const;
/// getSetCCResultType - get the ISD::SETCC result ValueType
- EVT::SimpleValueType getSetCCResultType(EVT VT) const;
+ MVT::SimpleValueType getSetCCResultType(EVT VT) const;
/// getFunctionAlignment - Return the Log2 alignment of this function.
virtual unsigned getFunctionAlignment(const Function *F) const;
index 53d6d613a9ee4fd393afdc5f28430d3b087dd8a8..b9276fe495ebd712fd1a4f90046fc657d2b34111 100644 (file)
// Node immediate fits as 16-bit sign extended on target immediate.
// e.g. addi, andi
def immSExt16 : PatLeaf<(imm), [{
- if (N->getValueType(0) == EVT::i32)
+ if (N->getValueType(0) == MVT::i32)
return (int32_t)N->getZExtValue() == (short)N->getZExtValue();
else
return (int64_t)N->getZExtValue() == (short)N->getZExtValue();
// immediate are caught.
// e.g. addiu, sltiu
def immZExt16 : PatLeaf<(imm), [{
- if (N->getValueType(0) == EVT::i32)
+ if (N->getValueType(0) == MVT::i32)
return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
else
return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
index 2b40d9fe8938bc36ff200ce6d06d3308ed6b21b8..35f8f7c8323139a8b15a0a5d26a1e38f149682b3 100644 (file)
Subtarget = &TM.getSubtarget<PIC16Subtarget>();
- addRegisterClass(EVT::i8, PIC16::GPRRegisterClass);
+ addRegisterClass(MVT::i8, PIC16::GPRRegisterClass);
- setShiftAmountType(EVT::i8);
+ setShiftAmountType(MVT::i8);
// Std lib call names
setLibcallName(RTLIB::COS_F32, getStdLibCallName(RTLIB::COS_F32));
setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
- setOperationAction(ISD::GlobalAddress, EVT::i16, Custom);
- setOperationAction(ISD::ExternalSymbol, EVT::i16, Custom);
+ setOperationAction(ISD::GlobalAddress, MVT::i16, Custom);
+ setOperationAction(ISD::ExternalSymbol, MVT::i16, Custom);
- setOperationAction(ISD::LOAD, EVT::i8, Legal);
- setOperationAction(ISD::LOAD, EVT::i16, Custom);
- setOperationAction(ISD::LOAD, EVT::i32, Custom);
+ setOperationAction(ISD::LOAD, MVT::i8, Legal);
+ setOperationAction(ISD::LOAD, MVT::i16, Custom);
+ setOperationAction(ISD::LOAD, MVT::i32, Custom);
- setOperationAction(ISD::STORE, EVT::i8, Legal);
- setOperationAction(ISD::STORE, EVT::i16, Custom);
- setOperationAction(ISD::STORE, EVT::i32, Custom);
- setOperationAction(ISD::STORE, EVT::i64, Custom);
+ setOperationAction(ISD::STORE, MVT::i8, Legal);
+ setOperationAction(ISD::STORE, MVT::i16, Custom);
+ setOperationAction(ISD::STORE, MVT::i32, Custom);
+ setOperationAction(ISD::STORE, MVT::i64, Custom);
- setOperationAction(ISD::ADDE, EVT::i8, Custom);
- setOperationAction(ISD::ADDC, EVT::i8, Custom);
- setOperationAction(ISD::SUBE, EVT::i8, Custom);
- setOperationAction(ISD::SUBC, EVT::i8, Custom);
- setOperationAction(ISD::SUB, EVT::i8, Custom);
- setOperationAction(ISD::ADD, EVT::i8, Custom);
- setOperationAction(ISD::ADD, EVT::i16, Custom);
+ setOperationAction(ISD::ADDE, MVT::i8, Custom);
+ setOperationAction(ISD::ADDC, MVT::i8, Custom);
+ setOperationAction(ISD::SUBE, MVT::i8, Custom);
+ setOperationAction(ISD::SUBC, MVT::i8, Custom);
+ setOperationAction(ISD::SUB, MVT::i8, Custom);
+ setOperationAction(ISD::ADD, MVT::i8, Custom);
+ setOperationAction(ISD::ADD, MVT::i16, Custom);
- setOperationAction(ISD::OR, EVT::i8, Custom);
- setOperationAction(ISD::AND, EVT::i8, Custom);
- setOperationAction(ISD::XOR, EVT::i8, Custom);
+ setOperationAction(ISD::OR, MVT::i8, Custom);
+ setOperationAction(ISD::AND, MVT::i8, Custom);
+ setOperationAction(ISD::XOR, MVT::i8, Custom);
- setOperationAction(ISD::FrameIndex, EVT::i16, Custom);
+ setOperationAction(ISD::FrameIndex, MVT::i16, Custom);
- setOperationAction(ISD::MUL, EVT::i8, Custom);
+ setOperationAction(ISD::MUL, MVT::i8, Custom);
- setOperationAction(ISD::SMUL_LOHI, EVT::i8, Expand);
- setOperationAction(ISD::UMUL_LOHI, EVT::i8, Expand);
- setOperationAction(ISD::MULHU, EVT::i8, Expand);
- setOperationAction(ISD::MULHS, EVT::i8, Expand);
+ setOperationAction(ISD::SMUL_LOHI, MVT::i8, Expand);
+ setOperationAction(ISD::UMUL_LOHI, MVT::i8, Expand);
+ setOperationAction(ISD::MULHU, MVT::i8, Expand);
+ setOperationAction(ISD::MULHS, MVT::i8, Expand);
- setOperationAction(ISD::SRA, EVT::i8, Custom);
- setOperationAction(ISD::SHL, EVT::i8, Custom);
- setOperationAction(ISD::SRL, EVT::i8, Custom);
+ setOperationAction(ISD::SRA, MVT::i8, Custom);
+ setOperationAction(ISD::SHL, MVT::i8, Custom);
+ setOperationAction(ISD::SRL, MVT::i8, Custom);
- setOperationAction(ISD::ROTL, EVT::i8, Expand);
- setOperationAction(ISD::ROTR, EVT::i8, Expand);
+ setOperationAction(ISD::ROTL, MVT::i8, Expand);
+ setOperationAction(ISD::ROTR, MVT::i8, Expand);
- setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i1, Expand);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
// PIC16 does not support shift parts
- setOperationAction(ISD::SRA_PARTS, EVT::i8, Expand);
- setOperationAction(ISD::SHL_PARTS, EVT::i8, Expand);
- setOperationAction(ISD::SRL_PARTS, EVT::i8, Expand);
+ setOperationAction(ISD::SRA_PARTS, MVT::i8, Expand);
+ setOperationAction(ISD::SHL_PARTS, MVT::i8, Expand);
+ setOperationAction(ISD::SRL_PARTS, MVT::i8, Expand);
// PIC16 does not have a SETCC, expand it to SELECT_CC.
- setOperationAction(ISD::SETCC, EVT::i8, Expand);
- setOperationAction(ISD::SELECT, EVT::i8, Expand);
- setOperationAction(ISD::BRCOND, EVT::Other, Expand);
- setOperationAction(ISD::BRIND, EVT::Other, Expand);
+ setOperationAction(ISD::SETCC, MVT::i8, Expand);
+ setOperationAction(ISD::SELECT, MVT::i8, Expand);
+ setOperationAction(ISD::BRCOND, MVT::Other, Expand);
+ setOperationAction(ISD::BRIND, MVT::Other, Expand);
- setOperationAction(ISD::SELECT_CC, EVT::i8, Custom);
- setOperationAction(ISD::BR_CC, EVT::i8, Custom);
+ setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
+ setOperationAction(ISD::BR_CC, MVT::i8, Custom);
- //setOperationAction(ISD::TRUNCATE, EVT::i16, Custom);
- setTruncStoreAction(EVT::i16, EVT::i8, Custom);
+ //setOperationAction(ISD::TRUNCATE, MVT::i16, Custom);
+ setTruncStoreAction(MVT::i16, MVT::i8, Custom);
// Now deduce the information based on the above mentioned
// actions
// Flag is the last value of the node.
SDValue Flag = Op.getValue(Op.getNode()->getNumValues() - 1);
- assert (Flag.getValueType() == EVT::Flag
+ assert (Flag.getValueType() == MVT::Flag
&& "Node does not have an out Flag");
return Flag;
// If the last value returned in Flag then the chain is
// second last value returned.
- if (Chain.getValueType() == EVT::Flag)
+ if (Chain.getValueType() == MVT::Flag)
Chain = Op.getValue(Op.getNode()->getNumValues() - 2);
// All nodes may not produce a chain. Therefore following assert
// verifies that the node is returning a chain only.
- assert (Chain.getValueType() == EVT::Other
+ assert (Chain.getValueType() == MVT::Other
&& "Node does not have a chain");
return Chain;
Results.push_back(N);
}
-EVT::SimpleValueType
+MVT::SimpleValueType
PIC16TargetLowering::getSetCCResultType(EVT ValType) const {
- return EVT::i8;
+ return MVT::i8;
}
/// The type legalizer framework of generating legalizer can generate libcalls
Args.push_back(Entry);
}
- SDValue Callee = DAG.getExternalSymbol(getPIC16LibcallName(Call), EVT::i16);
+ SDValue Callee = DAG.getExternalSymbol(getPIC16LibcallName(Call), MVT::i16);
const Type *RetTy = RetVT.getTypeForEVT();
std::pair<SDValue,SDValue> CallInfo =
SDValue PIC16TargetLowering::ExpandFrameIndex(SDNode *N, SelectionDAG &DAG) {
- // Currently handling FrameIndex of size EVT::i16 only
+ // Currently handling FrameIndex of size MVT::i16 only
// One example of this scenario is when return value is written on
// FrameIndex#0
- if (N->getValueType(0) != EVT::i16)
+ if (N->getValueType(0) != MVT::i16)
return SDValue();
// Expand the FrameIndex into ExternalSymbol and a Constant node
int FrameOffset;
SDValue FI = SDValue(N,0);
LegalizeFrameIndex(FI, DAG, ES, FrameOffset);
- SDValue Offset = DAG.getConstant(FrameOffset, EVT::i8);
- SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, EVT::i8, ES, Offset);
- SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, EVT::i8, ES, Offset);
+ SDValue Offset = DAG.getConstant(FrameOffset, MVT::i8);
+ SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, MVT::i8, ES, Offset);
+ SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, MVT::i8, ES, Offset);
return DAG.getNode(ISD::BUILD_PAIR, dl, N->getValueType(0), Lo, Hi);
}
SDValue PtrLo, PtrHi;
LegalizeAddress(Ptr, DAG, PtrLo, PtrHi, StoreOffset, dl);
- if (ValueType == EVT::i8) {
- return DAG.getNode (PIC16ISD::PIC16Store, dl, EVT::Other, Chain, Src,
+ if (ValueType == MVT::i8) {
+ return DAG.getNode (PIC16ISD::PIC16Store, dl, MVT::Other, Chain, Src,
PtrLo, PtrHi,
- DAG.getConstant (0 + StoreOffset, EVT::i8));
+ DAG.getConstant (0 + StoreOffset, MVT::i8));
}
- else if (ValueType == EVT::i16) {
+ else if (ValueType == MVT::i16) {
// Get the Lo and Hi parts from MERGE_VALUE or BUILD_PAIR.
SDValue SrcLo, SrcHi;
GetExpandedParts(Src, DAG, SrcLo, SrcHi);
ChainLo = Chain.getOperand(0);
ChainHi = Chain.getOperand(1);
}
- SDValue Store1 = DAG.getNode(PIC16ISD::PIC16Store, dl, EVT::Other,
+ SDValue Store1 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other,
ChainLo,
SrcLo, PtrLo, PtrHi,
- DAG.getConstant (0 + StoreOffset, EVT::i8));
+ DAG.getConstant (0 + StoreOffset, MVT::i8));
- SDValue Store2 = DAG.getNode(PIC16ISD::PIC16Store, dl, EVT::Other, ChainHi,
+ SDValue Store2 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainHi,
SrcHi, PtrLo, PtrHi,
- DAG.getConstant (1 + StoreOffset, EVT::i8));
+ DAG.getConstant (1 + StoreOffset, MVT::i8));
- return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, getChain(Store1),
+ return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, getChain(Store1),
getChain(Store2));
}
- else if (ValueType == EVT::i32) {
+ else if (ValueType == MVT::i32) {
// Get the Lo and Hi parts from MERGE_VALUE or BUILD_PAIR.
SDValue SrcLo, SrcHi;
GetExpandedParts(Src, DAG, SrcLo, SrcHi);
ChainHi1 = ChainHi.getOperand(0);
ChainHi2 = ChainHi.getOperand(1);
}
- SDValue Store1 = DAG.getNode(PIC16ISD::PIC16Store, dl, EVT::Other,
+ SDValue Store1 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other,
ChainLo1,
SrcLo1, PtrLo, PtrHi,
- DAG.getConstant (0 + StoreOffset, EVT::i8));
+ DAG.getConstant (0 + StoreOffset, MVT::i8));
- SDValue Store2 = DAG.getNode(PIC16ISD::PIC16Store, dl, EVT::Other, ChainLo2,
+ SDValue Store2 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainLo2,
SrcLo2, PtrLo, PtrHi,
- DAG.getConstant (1 + StoreOffset, EVT::i8));
+ DAG.getConstant (1 + StoreOffset, MVT::i8));
- SDValue Store3 = DAG.getNode(PIC16ISD::PIC16Store, dl, EVT::Other, ChainHi1,
+ SDValue Store3 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainHi1,
SrcHi1, PtrLo, PtrHi,
- DAG.getConstant (2 + StoreOffset, EVT::i8));
+ DAG.getConstant (2 + StoreOffset, MVT::i8));
- SDValue Store4 = DAG.getNode(PIC16ISD::PIC16Store, dl, EVT::Other, ChainHi2,
+ SDValue Store4 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainHi2,
SrcHi2, PtrLo, PtrHi,
- DAG.getConstant (3 + StoreOffset, EVT::i8));
+ DAG.getConstant (3 + StoreOffset, MVT::i8));
- SDValue RetLo = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ SDValue RetLo = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
getChain(Store1), getChain(Store2));
- SDValue RetHi = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ SDValue RetHi = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
getChain(Store3), getChain(Store4));
- return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, RetLo, RetHi);
+ return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, RetLo, RetHi);
- } else if (ValueType == EVT::i64) {
+ } else if (ValueType == MVT::i64) {
SDValue SrcLo, SrcHi;
GetExpandedParts(Src, DAG, SrcLo, SrcHi);
SDValue ChainLo = Chain, ChainHi = Chain;
SDValue Store2 = DAG.getStore(ChainHi, dl, SrcHi, Ptr, NULL,
1 + StoreOffset);
- return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Store1,
+ return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1,
Store2);
} else {
assert (0 && "value type not supported");
@@ -627,12 +627,12 @@ SDValue PIC16TargetLowering::ExpandExternalSymbol(SDNode *N, SelectionDAG &DAG)
// FIXME there isn't really debug info here
DebugLoc dl = ES->getDebugLoc();
- SDValue TES = DAG.getTargetExternalSymbol(ES->getSymbol(), EVT::i8);
- SDValue Offset = DAG.getConstant(0, EVT::i8);
- SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, EVT::i8, TES, Offset);
- SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, EVT::i8, TES, Offset);
+ SDValue TES = DAG.getTargetExternalSymbol(ES->getSymbol(), MVT::i8);
+ SDValue Offset = DAG.getConstant(0, MVT::i8);
+ SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, MVT::i8, TES, Offset);
+ SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, MVT::i8, TES, Offset);
- return DAG.getNode(ISD::BUILD_PAIR, dl, EVT::i16, Lo, Hi);
+ return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16, Lo, Hi);
}
// ExpandGlobalAddress -
@@ -641,14 +641,14 @@ SDValue PIC16TargetLowering::ExpandGlobalAddress(SDNode *N, SelectionDAG &DAG) {
// FIXME there isn't really debug info here
DebugLoc dl = G->getDebugLoc();
- SDValue TGA = DAG.getTargetGlobalAddress(G->getGlobal(), EVT::i8,
+ SDValue TGA = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i8,
G->getOffset());
- SDValue Offset = DAG.getConstant(0, EVT::i8);
- SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, EVT::i8, TGA, Offset);
- SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, EVT::i8, TGA, Offset);
+ SDValue Offset = DAG.getConstant(0, MVT::i8);
+ SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, MVT::i8, TGA, Offset);
+ SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, MVT::i8, TGA, Offset);
- return DAG.getNode(ISD::BUILD_PAIR, dl, EVT::i16, Lo, Hi);
+ return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16, Lo, Hi);
}
bool PIC16TargetLowering::isDirectAddress(const SDValue &Op) {
// Extract the lo component.
Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, NewVT, Op,
- DAG.getConstant(0, EVT::i8));
+ DAG.getConstant(0, MVT::i8));
// extract the hi component
Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, NewVT, Op,
- DAG.getConstant(1, EVT::i8));
+ DAG.getConstant(1, MVT::i8));
}
// Legalize FrameIndex into ExternalSymbol and offset.
const char *tmpName;
if (FIndex < ReservedFrameCount) {
tmpName = createESName(PAN::getFrameLabel(Name));
- ES = DAG.getTargetExternalSymbol(tmpName, EVT::i8);
+ ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
Offset = 0;
for (unsigned i=0; i<FIndex ; ++i) {
Offset += MFI->getObjectSize(i);
} else {
// FrameIndex has been made for some temporary storage
tmpName = createESName(PAN::getTempdataLabel(Name));
- ES = DAG.getTargetExternalSymbol(tmpName, EVT::i8);
+ ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
Offset = GetTmpOffsetForFI(FIndex, MFI->getObjectSize(FIndex));
}
// then treat it as direct address.
// One example for such case is storing and loading
// from function frame during a call
- if (Ptr.getValueType() == EVT::i8) {
+ if (Ptr.getValueType() == MVT::i8) {
switch (Ptr.getOpcode()) {
case ISD::TargetExternalSymbol:
Lo = Ptr;
- Hi = DAG.getConstant(1, EVT::i8);
+ Hi = DAG.getConstant(1, MVT::i8);
return;
}
}
int FrameOffset;
if (TFI.getOpcode() == ISD::TargetFrameIndex) {
LegalizeFrameIndex(TFI, DAG, Lo, FrameOffset);
- Hi = DAG.getConstant(1, EVT::i8);
+ Hi = DAG.getConstant(1, MVT::i8);
Offset += FrameOffset;
return;
} else if (TFI.getOpcode() == ISD::TargetExternalSymbol) {
// FrameIndex has already been expanded.
// Now just make use of its expansion
Lo = TFI;
- Hi = DAG.getConstant(1, EVT::i8);
+ Hi = DAG.getConstant(1, MVT::i8);
SDValue FOffset = Ptr.getOperand(0).getOperand(1);
assert (FOffset.getOpcode() == ISD::Constant &&
"Invalid operand of PIC16ISD::Lo");
// signifies that banksel needs to generated for it. Value 0 for
// the constant signifies that banksel does not need to be generated
// for it. Mark it as 1 now and optimize later.
- Hi = DAG.getConstant(1, EVT::i8);
+ Hi = DAG.getConstant(1, MVT::i8);
return;
}
GetExpandedParts(Ptr, DAG, Lo, Hi);
// Put the hi and lo parts into FSR.
- Lo = DAG.getNode(PIC16ISD::MTLO, dl, EVT::i8, Lo);
- Hi = DAG.getNode(PIC16ISD::MTHI, dl, EVT::i8, Hi);
+ Lo = DAG.getNode(PIC16ISD::MTLO, dl, MVT::i8, Lo);
+ Hi = DAG.getNode(PIC16ISD::MTHI, dl, MVT::i8, Hi);
return;
}
if(ISD::isNON_EXTLoad(N)) {
for (iter=0; iter<NumLoads ; ++iter) {
// Add the pointer offset if any
- Offset = DAG.getConstant(iter + LoadOffset, EVT::i8);
- Tys = DAG.getVTList(EVT::i8, EVT::Other);
+ Offset = DAG.getConstant(iter + LoadOffset, MVT::i8);
+ Tys = DAG.getVTList(MVT::i8, MVT::Other);
Load = DAG.getNode(PIC16ISD::PIC16Load, dl, Tys, Chain, PtrLo, PtrHi,
Offset);
PICLoads.push_back(Load);
// i.e. without any extension
EVT MemVT = LD->getMemoryVT();
unsigned MemBytes = MemVT.getSizeInBits() / 8;
- // if EVT::i1 is extended to EVT::i8 then MemBytes will be zero
+ // if MVT::i1 is extended to MVT::i8 then MemBytes will be zero
// So set it to one
if (MemBytes == 0) MemBytes = 1;
unsigned ExtdBytes = VT.getSizeInBits() / 8;
- Offset = DAG.getConstant(LoadOffset, EVT::i8);
+ Offset = DAG.getConstant(LoadOffset, MVT::i8);
- Tys = DAG.getVTList(EVT::i8, EVT::Other);
+ Tys = DAG.getVTList(MVT::i8, MVT::Other);
// For MemBytes generate PIC16Load with proper offset
for (iter=0; iter < MemBytes; ++iter) {
// Add the pointer offset if any
- Offset = DAG.getConstant(iter + LoadOffset, EVT::i8);
+ Offset = DAG.getConstant(iter + LoadOffset, MVT::i8);
Load = DAG.getNode(PIC16ISD::PIC16Load, dl, Tys, Chain, PtrLo, PtrHi,
Offset);
PICLoads.push_back(Load);
if (ISD::isSEXTLoad(N)) {
// For all ExtdBytes use the Right Shifted(Arithmetic) Value of the
// highest MemByte
- SDValue SRA = DAG.getNode(ISD::SRA, dl, EVT::i8, Load,
- DAG.getConstant(7, EVT::i8));
+ SDValue SRA = DAG.getNode(ISD::SRA, dl, MVT::i8, Load,
+ DAG.getConstant(7, MVT::i8));
for (iter=MemBytes; iter<ExtdBytes; ++iter) {
PICLoads.push_back(SRA);
}
} else if (ISD::isZEXTLoad(N) || ISD::isEXTLoad(N)) {
//} else if (ISD::isZEXTLoad(N)) {
// ZeroExtendedLoad -- For all ExtdBytes use constant 0
- SDValue ConstZero = DAG.getConstant(0, EVT::i8);
+ SDValue ConstZero = DAG.getConstant(0, MVT::i8);
for (iter=MemBytes; iter<ExtdBytes; ++iter) {
PICLoads.push_back(ConstZero);
}
}
SDValue BP;
- if (VT == EVT::i8) {
+ if (VT == MVT::i8) {
// Operand of Load is illegal -- Load itself is legal
return PICLoads[0];
}
- else if (VT == EVT::i16) {
+ else if (VT == MVT::i16) {
BP = DAG.getNode(ISD::BUILD_PAIR, dl, VT, PICLoads[0], PICLoads[1]);
- if (MemVT == EVT::i8)
+ if (MemVT == MVT::i8)
Chain = getChain(PICLoads[0]);
else
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
getChain(PICLoads[0]), getChain(PICLoads[1]));
- } else if (VT == EVT::i32) {
+ } else if (VT == MVT::i32) {
SDValue BPs[2];
- BPs[0] = DAG.getNode(ISD::BUILD_PAIR, dl, EVT::i16,
+ BPs[0] = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16,
PICLoads[0], PICLoads[1]);
- BPs[1] = DAG.getNode(ISD::BUILD_PAIR, dl, EVT::i16,
+ BPs[1] = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16,
PICLoads[2], PICLoads[3]);
BP = DAG.getNode(ISD::BUILD_PAIR, dl, VT, BPs[0], BPs[1]);
- if (MemVT == EVT::i8)
+ if (MemVT == MVT::i8)
Chain = getChain(PICLoads[0]);
- else if (MemVT == EVT::i16)
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ else if (MemVT == MVT::i16)
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
getChain(PICLoads[0]), getChain(PICLoads[1]));
else {
SDValue Chains[2];
- Chains[0] = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ Chains[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
getChain(PICLoads[0]), getChain(PICLoads[1]));
- Chains[1] = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ Chains[1] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
getChain(PICLoads[2]), getChain(PICLoads[3]));
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
Chains[0], Chains[1]);
}
}
- Tys = DAG.getVTList(VT, EVT::Other);
+ Tys = DAG.getVTList(VT, MVT::Other);
return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, BP, Chain);
}
SDValue PIC16TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
// We should have handled larger operands in type legalizer itself.
- assert (Op.getValueType() == EVT::i8 && "illegal shift to lower");
+ assert (Op.getValueType() == MVT::i8 && "illegal shift to lower");
SDNode *N = Op.getNode();
SDValue Value = N->getOperand(0);
SDValue PIC16TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) {
// We should have handled larger operands in type legalizer itself.
- assert (Op.getValueType() == EVT::i8 && "illegal multiply to lower");
+ assert (Op.getValueType() == MVT::i8 && "illegal multiply to lower");
SDNode *N = Op.getNode();
SmallVector<SDValue, 2> Ops(2);
SDValue PIC16TargetLowering::ConvertToMemOperand(SDValue Op,
SelectionDAG &DAG,
DebugLoc dl) {
- assert (Op.getValueType() == EVT::i8
+ assert (Op.getValueType() == MVT::i8
&& "illegal value type to store on stack.");
MachineFunction &MF = DAG.getMachineFunction();
// Get a stack slot index and convert to es.
int FI = MF.getFrameInfo()->CreateStackObject(1, 1);
const char *tmpName = createESName(PAN::getTempdataLabel(FuncName));
- SDValue ES = DAG.getTargetExternalSymbol(tmpName, EVT::i8);
+ SDValue ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
// Store the value to ES.
- SDValue Store = DAG.getNode (PIC16ISD::PIC16Store, dl, EVT::Other,
+ SDValue Store = DAG.getNode (PIC16ISD::PIC16Store, dl, MVT::Other,
DAG.getEntryNode(),
Op, ES,
- DAG.getConstant (1, EVT::i8), // Banksel.
+ DAG.getConstant (1, MVT::i8), // Banksel.
DAG.getConstant (GetTmpOffsetForFI(FI, 1),
- EVT::i8));
+ MVT::i8));
// Load the value from ES.
- SDVTList Tys = DAG.getVTList(EVT::i8, EVT::Other);
+ SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other);
SDValue Load = DAG.getNode(PIC16ISD::PIC16Load, dl, Tys, Store,
- ES, DAG.getConstant (1, EVT::i8),
+ ES, DAG.getConstant (1, MVT::i8),
DAG.getConstant (GetTmpOffsetForFI(FI, 1),
- EVT::i8));
+ MVT::i8));
return Load.getValue(0);
}
return Chain;
std::vector<SDValue> Ops;
- SDVTList Tys = DAG.getVTList(EVT::Other, EVT::Flag);
+ SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
SDValue Arg, StoreRet;
// For PIC16 ABI the arguments come after the return value.
Ops.push_back(Arg);
Ops.push_back(DataAddr_Lo);
Ops.push_back(DataAddr_Hi);
- Ops.push_back(DAG.getConstant(ArgOffset, EVT::i8));
+ Ops.push_back(DAG.getConstant(ArgOffset, MVT::i8));
Ops.push_back(InFlag);
StoreRet = DAG.getNode (PIC16ISD::PIC16StWF, dl, Tys, &Ops[0], Ops.size());
SDValue StoreRet;
std::vector<SDValue> Ops;
- SDVTList Tys = DAG.getVTList(EVT::Other, EVT::Flag);
+ SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
for (unsigned i=0, Offset = 0; i<NumOps; i++) {
// Get the argument
Arg = Outs[i].Val;
Ops.push_back(Arg);
Ops.push_back(PtrLo);
Ops.push_back(PtrHi);
- Ops.push_back(DAG.getConstant(StoreOffset, EVT::i8));
+ Ops.push_back(DAG.getConstant(StoreOffset, MVT::i8));
Ops.push_back(InFlag);
StoreRet = DAG.getNode (PIC16ISD::PIC16StWF, dl, Tys, &Ops[0], Ops.size());
// Call has something to return
SDValue LoadRet;
- SDVTList Tys = DAG.getVTList(EVT::i8, EVT::Other, EVT::Flag);
+ SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other, MVT::Flag);
for(unsigned i=0;i<RetVals;i++) {
LoadRet = DAG.getNode(PIC16ISD::PIC16LdWF, dl, Tys, Chain, DataAddr_Lo,
- DataAddr_Hi, DAG.getConstant(i, EVT::i8),
+ DataAddr_Hi, DAG.getConstant(i, MVT::i8),
InFlag);
InFlag = getOutFlag(LoadRet);
Chain = getChain(LoadRet);
unsigned LdOffset;
LegalizeAddress(RetLabel, DAG, LdLo, LdHi, LdOffset, dl);
- SDVTList Tys = DAG.getVTList(EVT::i8, EVT::Other, EVT::Flag);
+ SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other, MVT::Flag);
SDValue LoadRet;
for(unsigned i=0, Offset=0;i<RetVals;i++) {
LoadRet = DAG.getNode(PIC16ISD::PIC16LdWF, dl, Tys, Chain, LdLo, LdHi,
- DAG.getConstant(LdOffset + Offset, EVT::i8),
+ DAG.getConstant(LdOffset + Offset, MVT::i8),
InFlag);
InFlag = getOutFlag(LoadRet);
std::string FuncName = F->getName();
const char *tmpName = createESName(PAN::getFrameLabel(FuncName));
- SDVTList VTs = DAG.getVTList (EVT::i8, EVT::Other);
- SDValue ES = DAG.getTargetExternalSymbol(tmpName, EVT::i8);
- SDValue BS = DAG.getConstant(1, EVT::i8);
+ SDVTList VTs = DAG.getVTList (MVT::i8, MVT::Other);
+ SDValue ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
+ SDValue BS = DAG.getConstant(1, MVT::i8);
SDValue RetVal;
for(unsigned i=0;i<NumRet; ++i) {
RetVal = Outs[i].Val;
- Chain = DAG.getNode (PIC16ISD::PIC16Store, dl, EVT::Other, Chain, RetVal,
+ Chain = DAG.getNode (PIC16ISD::PIC16Store, dl, MVT::Other, Chain, RetVal,
ES, BS,
- DAG.getConstant (i, EVT::i8));
+ DAG.getConstant (i, MVT::i8));
}
- return DAG.getNode(PIC16ISD::RET, dl, EVT::Other, Chain);
+ return DAG.getNode(PIC16ISD::RET, dl, MVT::Other, Chain);
}
void PIC16TargetLowering::
SelectionDAG &DAG) {
assert (Callee.getOpcode() == PIC16ISD::PIC16Connect
&& "Don't know what to do of such callee!!");
- SDValue ZeroOperand = DAG.getConstant(0, EVT::i8);
+ SDValue ZeroOperand = DAG.getConstant(0, MVT::i8);
SDValue SeqStart = DAG.getCALLSEQ_START(Chain, ZeroOperand);
Chain = getChain(SeqStart);
SDValue OperFlag = getOutFlag(SeqStart); // To manage the data dependency
SDValue Hi = Callee.getOperand(1);
SDValue Data_Lo, Data_Hi;
- SDVTList Tys = DAG.getVTList(EVT::i8, EVT::Other, EVT::Flag);
+ SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other, MVT::Flag);
// Subtract 2 from Address to get the Lower part of DataAddress.
- SDVTList VTList = DAG.getVTList(EVT::i8, EVT::Flag);
+ SDVTList VTList = DAG.getVTList(MVT::i8, MVT::Flag);
Data_Lo = DAG.getNode(ISD::SUBC, dl, VTList, Lo,
- DAG.getConstant(2, EVT::i8));
- SDValue Ops[3] = { Hi, DAG.getConstant(0, EVT::i8), Data_Lo.getValue(1)};
+ DAG.getConstant(2, MVT::i8));
+ SDValue Ops[3] = { Hi, DAG.getConstant(0, MVT::i8), Data_Lo.getValue(1)};
Data_Hi = DAG.getNode(ISD::SUBE, dl, VTList, Ops, 3);
- SDValue PCLATH = DAG.getNode(PIC16ISD::MTPCLATH, dl, EVT::i8, Data_Hi);
- Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, EVT::i8, Data_Lo, PCLATH);
+ SDValue PCLATH = DAG.getNode(PIC16ISD::MTPCLATH, dl, MVT::i8, Data_Hi);
+ Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, MVT::i8, Data_Lo, PCLATH);
SDValue Call = DAG.getNode(PIC16ISD::CALLW, dl, Tys, Chain, Callee,
OperFlag);
Chain = getChain(Call);
OperFlag = getOutFlag(SeqEnd);
// Low part of Data Address
- DataAddr_Lo = DAG.getNode(PIC16ISD::MTLO, dl, EVT::i8, Call, OperFlag);
+ DataAddr_Lo = DAG.getNode(PIC16ISD::MTLO, dl, MVT::i8, Call, OperFlag);
// Make the second call.
SeqStart = DAG.getCALLSEQ_START(Chain, ZeroOperand);
// Subtract 1 from Address to get high part of data address.
Data_Lo = DAG.getNode(ISD::SUBC, dl, VTList, Lo,
- DAG.getConstant(1, EVT::i8));
- SDValue HiOps[3] = { Hi, DAG.getConstant(0, EVT::i8), Data_Lo.getValue(1)};
+ DAG.getConstant(1, MVT::i8));
+ SDValue HiOps[3] = { Hi, DAG.getConstant(0, MVT::i8), Data_Lo.getValue(1)};
Data_Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
- PCLATH = DAG.getNode(PIC16ISD::MTPCLATH, dl, EVT::i8, Data_Hi);
+ PCLATH = DAG.getNode(PIC16ISD::MTPCLATH, dl, MVT::i8, Data_Hi);
// Use new Lo to make another CALLW
- Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, EVT::i8, Data_Lo, PCLATH);
+ Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, MVT::i8, Data_Lo, PCLATH);
Call = DAG.getNode(PIC16ISD::CALLW, dl, Tys, Chain, Callee, OperFlag);
Chain = getChain(Call);
OperFlag = getOutFlag(Call);
Chain = getChain(SeqEnd);
OperFlag = getOutFlag(SeqEnd);
// Hi part of Data Address
- DataAddr_Hi = DAG.getNode(PIC16ISD::MTHI, dl, EVT::i8, Call, OperFlag);
+ DataAddr_Hi = DAG.getNode(PIC16ISD::MTHI, dl, MVT::i8, Call, OperFlag);
}
SDValue
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) {
- assert(Callee.getValueType() == EVT::i16 &&
+ assert(Callee.getValueType() == MVT::i16 &&
"Don't know how to legalize this call node!!!");
// The flag to track if this is a direct or indirect call.
// Indirect addresses. Get the hi and lo parts of ptr.
GetExpandedParts(Callee, DAG, Lo, Hi);
// Connect Lo and Hi parts of the callee with the PIC16Connect
- Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, EVT::i8, Lo, Hi);
+ Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, MVT::i8, Lo, Hi);
// Read DataAddress only if we have to pass arguments or
// read return value.
GetDataAddress(dl, Callee, Chain, DataAddr_Lo, DataAddr_Hi, DAG);
}
- SDValue ZeroOperand = DAG.getConstant(0, EVT::i8);
+ SDValue ZeroOperand = DAG.getConstant(0, MVT::i8);
// Start the call sequence.
// Carring the Constant 0 along the CALLSEQSTART
// Considering the GlobalAddressNode case here.
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
GlobalValue *GV = G->getGlobal();
- Callee = DAG.getTargetGlobalAddress(GV, EVT::i8);
+ Callee = DAG.getTargetGlobalAddress(GV, MVT::i8);
Name = G->getGlobal()->getName();
} else {// Considering the ExternalSymbol case here
ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Callee);
- Callee = DAG.getTargetExternalSymbol(ES->getSymbol(), EVT::i8);
+ Callee = DAG.getTargetExternalSymbol(ES->getSymbol(), MVT::i8);
Name = ES->getSymbol();
}
// Label for argument passing
const char *argFrame = createESName(PAN::getArgsLabel(Name));
- ArgLabel = DAG.getTargetExternalSymbol(argFrame, EVT::i8);
+ ArgLabel = DAG.getTargetExternalSymbol(argFrame, MVT::i8);
// Label for reading return value
const char *retName = createESName(PAN::getRetvalLabel(Name));
- RetLabel = DAG.getTargetExternalSymbol(retName, EVT::i8);
+ RetLabel = DAG.getTargetExternalSymbol(retName, MVT::i8);
} else {
// if indirect call
SDValue CodeAddr_Lo = Callee.getOperand(0);
SDValue CodeAddr_Hi = Callee.getOperand(1);
- /*CodeAddr_Lo = DAG.getNode(ISD::ADD, dl, EVT::i8, CodeAddr_Lo,
- DAG.getConstant(2, EVT::i8));*/
+ /*CodeAddr_Lo = DAG.getNode(ISD::ADD, dl, MVT::i8, CodeAddr_Lo,
+ DAG.getConstant(2, MVT::i8));*/
// move Hi part in PCLATH
- CodeAddr_Hi = DAG.getNode(PIC16ISD::MTPCLATH, dl, EVT::i8, CodeAddr_Hi);
- Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, EVT::i8, CodeAddr_Lo,
+ CodeAddr_Hi = DAG.getNode(PIC16ISD::MTPCLATH, dl, MVT::i8, CodeAddr_Hi);
+ Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, MVT::i8, CodeAddr_Lo,
CodeAddr_Hi);
}
OperFlag = getOutFlag(CallArgs);
}
- SDVTList Tys = DAG.getVTList(EVT::Other, EVT::Flag);
+ SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
SDValue PICCall = DAG.getNode(PIC16ISD::CALL, dl, Tys, Chain, Callee,
OperFlag);
Chain = getChain(PICCall);
DebugLoc dl = Op.getDebugLoc();
// We should have handled larger operands in type legalizer itself.
- assert (Op.getValueType() == EVT::i8 && "illegal Op to lower");
+ assert (Op.getValueType() == MVT::i8 && "illegal Op to lower");
unsigned MemOp = 1;
if (NeedToConvertToMemOp(Op, MemOp)) {
// Put one value on stack.
SDValue NewVal = ConvertToMemOperand (Op.getOperand(MemOp), DAG, dl);
- return DAG.getNode(Op.getOpcode(), dl, EVT::i8, Op.getOperand(MemOp ^ 1),
+ return DAG.getNode(Op.getOpcode(), dl, MVT::i8, Op.getOperand(MemOp ^ 1),
NewVal);
}
else {
// that affects carry.
SDValue PIC16TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) {
// We should have handled larger operands in type legalizer itself.
- assert (Op.getValueType() == EVT::i8 && "illegal add to lower");
+ assert (Op.getValueType() == MVT::i8 && "illegal add to lower");
DebugLoc dl = Op.getDebugLoc();
unsigned MemOp = 1;
if (NeedToConvertToMemOp(Op, MemOp)) {
SDValue NewVal = ConvertToMemOperand (Op.getOperand(MemOp), DAG, dl);
// ADDC and ADDE produce two results.
- SDVTList Tys = DAG.getVTList(EVT::i8, EVT::Flag);
+ SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Flag);
// ADDE has three operands, the last one is the carry bit.
if (Op.getOpcode() == ISD::ADDE)
NewVal);
// ADD it is. It produces only one result.
else
- return DAG.getNode(Op.getOpcode(), dl, EVT::i8, Op.getOperand(MemOp ^ 1),
+ return DAG.getNode(Op.getOpcode(), dl, MVT::i8, Op.getOperand(MemOp ^ 1),
NewVal);
}
else
SDValue PIC16TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) {
DebugLoc dl = Op.getDebugLoc();
// We should have handled larger operands in type legalizer itself.
- assert (Op.getValueType() == EVT::i8 && "illegal sub to lower");
+ assert (Op.getValueType() == MVT::i8 && "illegal sub to lower");
// Nothing to do if the first operand is already a direct load and it has
// only one use.
// Put first operand on stack.
SDValue NewVal = ConvertToMemOperand (Op.getOperand(0), DAG, dl);
- SDVTList Tys = DAG.getVTList(EVT::i8, EVT::Flag);
+ SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Flag);
switch (Op.getOpcode()) {
default:
assert (0 && "Opcode unknown.");
return DAG.getNode(Op.getOpcode(), dl, Tys, NewVal, Op.getOperand(1));
break;
case ISD::SUB:
- return DAG.getNode(Op.getOpcode(), dl, EVT::i8, NewVal, Op.getOperand(1));
+ return DAG.getNode(Op.getOpcode(), dl, MVT::i8, NewVal, Op.getOperand(1));
break;
}
}
// Create the <fname>.args external symbol.
const char *tmpName = createESName(PAN::getArgsLabel(FuncName));
- SDValue ES = DAG.getTargetExternalSymbol(tmpName, EVT::i8);
+ SDValue ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
// Load arg values from the label + offset.
- SDVTList VTs = DAG.getVTList (EVT::i8, EVT::Other);
- SDValue BS = DAG.getConstant(1, EVT::i8);
+ SDVTList VTs = DAG.getVTList (MVT::i8, MVT::Other);
+ SDValue BS = DAG.getConstant(1, MVT::i8);
for (unsigned i = 0; i < NumArgVals ; ++i) {
- SDValue Offset = DAG.getConstant(i, EVT::i8);
+ SDValue Offset = DAG.getConstant(i, MVT::i8);
SDValue PICLoad = DAG.getNode(PIC16ISD::PIC16LdArg, dl, VTs, Chain, ES, BS,
Offset);
Chain = getChain(PICLoad);
}
}
- PIC16CC = DAG.getConstant(CondCode, EVT::i8);
+ PIC16CC = DAG.getConstant(CondCode, MVT::i8);
// These are signed comparisons.
- SDValue Mask = DAG.getConstant(128, EVT::i8);
+ SDValue Mask = DAG.getConstant(128, MVT::i8);
if (isSignedComparison(CondCode)) {
- LHS = DAG.getNode (ISD::XOR, dl, EVT::i8, LHS, Mask);
- RHS = DAG.getNode (ISD::XOR, dl, EVT::i8, RHS, Mask);
+ LHS = DAG.getNode (ISD::XOR, dl, MVT::i8, LHS, Mask);
+ RHS = DAG.getNode (ISD::XOR, dl, MVT::i8, RHS, Mask);
}
- SDVTList VTs = DAG.getVTList (EVT::i8, EVT::Flag);
+ SDVTList VTs = DAG.getVTList (MVT::i8, MVT::Flag);
// We can use a subtract operation to set the condition codes. But
// we need to put one operand in memory if required.
// Nothing to do if the first operand is already a valid type (direct load
SDValue PIC16CC;
SDValue Cmp = getPIC16Cmp(LHS, RHS, ORIGCC, PIC16CC, DAG, dl);
- return DAG.getNode(PIC16ISD::BRCOND, dl, EVT::Other, Chain, Dest, PIC16CC,
+ return DAG.getNode(PIC16ISD::BRCOND, dl, MVT::Other, Chain, Dest, PIC16CC,
Cmp.getValue(1));
}
index 4d44d6df8bdf5700812669129c9b3432df9335c6..aee39f0ae378334bb481424576c685be84546903 100644 (file)
/// DAG node.
virtual const char *getTargetNodeName(unsigned Opcode) const;
/// getSetCCResultType - Return the ISD::SETCC ValueType
- virtual EVT::SimpleValueType getSetCCResultType(EVT ValType) const;
+ virtual MVT::SimpleValueType getSetCCResultType(EVT ValType) const;
SDValue LowerShift(SDValue Op, SelectionDAG &DAG);
SDValue LowerMUL(SDValue Op, SelectionDAG &DAG);
SDValue LowerADD(SDValue Op, SelectionDAG &DAG);
index 77f1b12cfa5ebae97f2115383f990e5daba73f8b..f9e620aa3088fe2a64b68b159148f52499342473 100644 (file)
/// getI32Imm - Return a target constant with the specified value, of type
/// i32.
inline SDValue getI32Imm(unsigned Imm) {
- return CurDAG->getTargetConstant(Imm, EVT::i32);
+ return CurDAG->getTargetConstant(Imm, MVT::i32);
}
/// getI64Imm - Return a target constant with the specified value, of type
/// i64.
inline SDValue getI64Imm(uint64_t Imm) {
- return CurDAG->getTargetConstant(Imm, EVT::i64);
+ return CurDAG->getTargetConstant(Imm, MVT::i64);
}
/// getSmallIPtrImm - Return a target constant of pointer type.
MachineBasicBlock::iterator MBBI = FirstMBB.begin();
DebugLoc dl = DebugLoc::getUnknownLoc();
- if (PPCLowering.getPointerTy() == EVT::i32) {
+ if (PPCLowering.getPointerTy() == MVT::i32) {
GlobalBaseReg = RegInfo->createVirtualRegister(PPC::GPRCRegisterClass);
BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR), PPC::LR);
BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
return false;
Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
- if (N->getValueType(0) == EVT::i32)
+ if (N->getValueType(0) == MVT::i32)
return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
else
return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
/// isInt32Immediate - This method tests to see if the node is a 32-bit constant
/// operand. If so Imm will receive the 32-bit value.
static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
- if (N->getOpcode() == ISD::Constant && N->getValueType(0) == EVT::i32) {
+ if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
Imm = cast<ConstantSDNode>(N)->getZExtValue();
return true;
}
/// isInt64Immediate - This method tests to see if the node is a 64-bit constant
/// operand. If so Imm will receive the 64-bit value.
static bool isInt64Immediate(SDNode *N, uint64_t &Imm) {
- if (N->getOpcode() == ISD::Constant && N->getValueType(0) == EVT::i64) {
+ if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) {
Imm = cast<ConstantSDNode>(N)->getZExtValue();
return true;
}
unsigned &MB, unsigned &ME) {
// Don't even go down this path for i64, since different logic will be
// necessary for rldicl/rldicr/rldimi.
- if (N->getValueType(0) != EVT::i32)
+ if (N->getValueType(0) != MVT::i32)
return false;
unsigned Shift = 32;
SH &= 31;
SDValue Ops[] = { Tmp3, Op1, getI32Imm(SH), getI32Imm(MB),
getI32Imm(ME) };
- return CurDAG->getTargetNode(PPC::RLWIMI, dl, EVT::i32, Ops, 5);
+ return CurDAG->getTargetNode(PPC::RLWIMI, dl, MVT::i32, Ops, 5);
}
}
return 0;
// Always select the LHS.
unsigned Opc;
- if (LHS.getValueType() == EVT::i32) {
+ if (LHS.getValueType() == MVT::i32) {
unsigned Imm;
if (CC == ISD::SETEQ || CC == ISD::SETNE) {
if (isInt32Immediate(RHS, Imm)) {
// SETEQ/SETNE comparison with 16-bit immediate, fold it.
if (isUInt16(Imm))
- return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, dl, EVT::i32, LHS,
+ return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, dl, MVT::i32, LHS,
getI32Imm(Imm & 0xFFFF)), 0);
// If this is a 16-bit signed immediate, fold it.
if (isInt16((int)Imm))
- return SDValue(CurDAG->getTargetNode(PPC::CMPWI, dl, EVT::i32, LHS,
+ return SDValue(CurDAG->getTargetNode(PPC::CMPWI, dl, MVT::i32, LHS,
getI32Imm(Imm & 0xFFFF)), 0);
// For non-equality comparisons, the default code would materialize the
// xoris r0,r3,0x1234
// cmplwi cr0,r0,0x5678
// beq cr0,L6
- SDValue Xor(CurDAG->getTargetNode(PPC::XORIS, dl, EVT::i32, LHS,
+ SDValue Xor(CurDAG->getTargetNode(PPC::XORIS, dl, MVT::i32, LHS,
getI32Imm(Imm >> 16)), 0);
- return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, dl, EVT::i32, Xor,
+ return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, dl, MVT::i32, Xor,
getI32Imm(Imm & 0xFFFF)), 0);
}
Opc = PPC::CMPLW;
} else if (ISD::isUnsignedIntSetCC(CC)) {
if (isInt32Immediate(RHS, Imm) && isUInt16(Imm))
- return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, dl, EVT::i32, LHS,
+ return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, dl, MVT::i32, LHS,
getI32Imm(Imm & 0xFFFF)), 0);
Opc = PPC::CMPLW;
} else {
short SImm;
if (isIntS16Immediate(RHS, SImm))
- return SDValue(CurDAG->getTargetNode(PPC::CMPWI, dl, EVT::i32, LHS,
+ return SDValue(CurDAG->getTargetNode(PPC::CMPWI, dl, MVT::i32, LHS,
getI32Imm((int)SImm & 0xFFFF)),
0);
Opc = PPC::CMPW;
}
- } else if (LHS.getValueType() == EVT::i64) {
+ } else if (LHS.getValueType() == MVT::i64) {
uint64_t Imm;
if (CC == ISD::SETEQ || CC == ISD::SETNE) {
if (isInt64Immediate(RHS.getNode(), Imm)) {
// SETEQ/SETNE comparison with 16-bit immediate, fold it.
if (isUInt16(Imm))
- return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, dl, EVT::i64, LHS,
+ return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, dl, MVT::i64, LHS,
getI32Imm(Imm & 0xFFFF)), 0);
// If this is a 16-bit signed immediate, fold it.
if (isInt16(Imm))
- return SDValue(CurDAG->getTargetNode(PPC::CMPDI, dl, EVT::i64, LHS,
+ return SDValue(CurDAG->getTargetNode(PPC::CMPDI, dl, MVT::i64, LHS,
getI32Imm(Imm & 0xFFFF)), 0);
// For non-equality comparisons, the default code would materialize the
// cmpldi cr0,r0,0x5678
// beq cr0,L6
if (isUInt32(Imm)) {
- SDValue Xor(CurDAG->getTargetNode(PPC::XORIS8, dl, EVT::i64, LHS,
+ SDValue Xor(CurDAG->getTargetNode(PPC::XORIS8, dl, MVT::i64, LHS,
getI64Imm(Imm >> 16)), 0);
- return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, dl, EVT::i64, Xor,
+ return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, dl, MVT::i64, Xor,
getI64Imm(Imm & 0xFFFF)), 0);
}
}
Opc = PPC::CMPLD;
} else if (ISD::isUnsignedIntSetCC(CC)) {
if (isInt64Immediate(RHS.getNode(), Imm) && isUInt16(Imm))
- return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, dl, EVT::i64, LHS,
+ return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, dl, MVT::i64, LHS,
getI64Imm(Imm & 0xFFFF)), 0);
Opc = PPC::CMPLD;
} else {
short SImm;
if (isIntS16Immediate(RHS, SImm))
- return SDValue(CurDAG->getTargetNode(PPC::CMPDI, dl, EVT::i64, LHS,
+ return SDValue(CurDAG->getTargetNode(PPC::CMPDI, dl, MVT::i64, LHS,
getI64Imm(SImm & 0xFFFF)),
0);
Opc = PPC::CMPD;
}
- } else if (LHS.getValueType() == EVT::f32) {
+ } else if (LHS.getValueType() == MVT::f32) {
Opc = PPC::FCMPUS;
} else {
- assert(LHS.getValueType() == EVT::f64 && "Unknown vt!");
+ assert(LHS.getValueType() == MVT::f64 && "Unknown vt!");
Opc = PPC::FCMPUD;
}
- return SDValue(CurDAG->getTargetNode(Opc, dl, EVT::i32, LHS, RHS), 0);
+ return SDValue(CurDAG->getTargetNode(Opc, dl, MVT::i32, LHS, RHS), 0);
}
static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) {
switch (CC) {
default: break;
case ISD::SETEQ: {
- Op = SDValue(CurDAG->getTargetNode(PPC::CNTLZW, dl, EVT::i32, Op), 0);
+ Op = SDValue(CurDAG->getTargetNode(PPC::CNTLZW, dl, MVT::i32, Op), 0);
SDValue Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) };
- return CurDAG->SelectNodeTo(N, PPC::RLWINM, EVT::i32, Ops, 4);
+ return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
}
case ISD::SETNE: {
SDValue AD =
- SDValue(CurDAG->getTargetNode(PPC::ADDIC, dl, EVT::i32, EVT::Flag,
+ SDValue(CurDAG->getTargetNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag,
Op, getI32Imm(~0U)), 0);
- return CurDAG->SelectNodeTo(N, PPC::SUBFE, EVT::i32, AD, Op,
+ return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op,
AD.getValue(1));
}
case ISD::SETLT: {
SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
- return CurDAG->SelectNodeTo(N, PPC::RLWINM, EVT::i32, Ops, 4);
+ return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
}
case ISD::SETGT: {
SDValue T =
- SDValue(CurDAG->getTargetNode(PPC::NEG, dl, EVT::i32, Op), 0);
- T = SDValue(CurDAG->getTargetNode(PPC::ANDC, dl, EVT::i32, T, Op), 0);
+ SDValue(CurDAG->getTargetNode(PPC::NEG, dl, MVT::i32, Op), 0);
+ T = SDValue(CurDAG->getTargetNode(PPC::ANDC, dl, MVT::i32, T, Op), 0);
SDValue Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
- return CurDAG->SelectNodeTo(N, PPC::RLWINM, EVT::i32, Ops, 4);
+ return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
}
}
} else if (Imm == ~0U) { // setcc op, -1
switch (CC) {
default: break;
case ISD::SETEQ:
- Op = SDValue(CurDAG->getTargetNode(PPC::ADDIC, dl, EVT::i32, EVT::Flag,
+ Op = SDValue(CurDAG->getTargetNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag,
Op, getI32Imm(1)), 0);
- return CurDAG->SelectNodeTo(N, PPC::ADDZE, EVT::i32,
+ return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
SDValue(CurDAG->getTargetNode(PPC::LI, dl,
- EVT::i32,
+ MVT::i32,
getI32Imm(0)), 0),
Op.getValue(1));
case ISD::SETNE: {
- Op = SDValue(CurDAG->getTargetNode(PPC::NOR, dl, EVT::i32, Op, Op), 0);
- SDNode *AD = CurDAG->getTargetNode(PPC::ADDIC, dl, EVT::i32, EVT::Flag,
+ Op = SDValue(CurDAG->getTargetNode(PPC::NOR, dl, MVT::i32, Op, Op), 0);
+ SDNode *AD = CurDAG->getTargetNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag,
Op, getI32Imm(~0U));
- return CurDAG->SelectNodeTo(N, PPC::SUBFE, EVT::i32, SDValue(AD, 0),
+ return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(AD, 0),
Op, SDValue(AD, 1));
}
case ISD::SETLT: {
- SDValue AD = SDValue(CurDAG->getTargetNode(PPC::ADDI, dl, EVT::i32, Op,
+ SDValue AD = SDValue(CurDAG->getTargetNode(PPC::ADDI, dl, MVT::i32, Op,
getI32Imm(1)), 0);
- SDValue AN = SDValue(CurDAG->getTargetNode(PPC::AND, dl, EVT::i32, AD,
+ SDValue AN = SDValue(CurDAG->getTargetNode(PPC::AND, dl, MVT::i32, AD,
Op), 0);
SDValue Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
- return CurDAG->SelectNodeTo(N, PPC::RLWINM, EVT::i32, Ops, 4);
+ return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
}
case ISD::SETGT: {
SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
- Op = SDValue(CurDAG->getTargetNode(PPC::RLWINM, dl, EVT::i32, Ops, 4),
+ Op = SDValue(CurDAG->getTargetNode(PPC::RLWINM, dl, MVT::i32, Ops, 4),
0);
- return CurDAG->SelectNodeTo(N, PPC::XORI, EVT::i32, Op,
+ return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op,
getI32Imm(1));
}
}
SDValue IntCR;
// Force the ccreg into CR7.
- SDValue CR7Reg = CurDAG->getRegister(PPC::CR7, EVT::i32);
+ SDValue CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
SDValue InFlag(0, 0); // Null incoming flag value.
CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, CR7Reg, CCReg,
InFlag).getValue(1);
if (PPCSubTarget.isGigaProcessor() && OtherCondIdx == -1)
- IntCR = SDValue(CurDAG->getTargetNode(PPC::MFOCRF, dl, EVT::i32, CR7Reg,
+ IntCR = SDValue(CurDAG->getTargetNode(PPC::MFOCRF, dl, MVT::i32, CR7Reg,
CCReg), 0);
else
- IntCR = SDValue(CurDAG->getTargetNode(PPC::MFCR, dl, EVT::i32, CCReg), 0);
+ IntCR = SDValue(CurDAG->getTargetNode(PPC::MFCR, dl, MVT::i32, CCReg), 0);
SDValue Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31),
getI32Imm(31), getI32Imm(31) };
if (OtherCondIdx == -1 && !Inv)
- return CurDAG->SelectNodeTo(N, PPC::RLWINM, EVT::i32, Ops, 4);
+ return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
// Get the specified bit.
SDValue Tmp =
- SDValue(CurDAG->getTargetNode(PPC::RLWINM, dl, EVT::i32, Ops, 4), 0);
+ SDValue(CurDAG->getTargetNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), 0);
if (Inv) {
assert(OtherCondIdx == -1 && "Can't have split plus negation");
- return CurDAG->SelectNodeTo(N, PPC::XORI, EVT::i32, Tmp, getI32Imm(1));
+ return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
}
// Otherwise, we have to turn an operation like SETONE -> SETOLT | SETOGT.
// Get the other bit of the comparison.
Ops[1] = getI32Imm((32-(3-OtherCondIdx)) & 31);
SDValue OtherCond =
- SDValue(CurDAG->getTargetNode(PPC::RLWINM, dl, EVT::i32, Ops, 4), 0);
+ SDValue(CurDAG->getTargetNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), 0);
- return CurDAG->SelectNodeTo(N, PPC::OR, EVT::i32, Tmp, OtherCond);
+ return CurDAG->SelectNodeTo(N, PPC::OR, MVT::i32, Tmp, OtherCond);
}
default: break;
case ISD::Constant: {
- if (N->getValueType(0) == EVT::i64) {
+ if (N->getValueType(0) == MVT::i64) {
// Get 64 bit value.
int64_t Imm = cast<ConstantSDNode>(N)->getZExtValue();
// Assume no remaining bits.
// Simple value.
if (isInt16(Imm)) {
// Just the Lo bits.
- Result = CurDAG->getTargetNode(PPC::LI8, dl, EVT::i64, getI32Imm(Lo));
+ Result = CurDAG->getTargetNode(PPC::LI8, dl, MVT::i64, getI32Imm(Lo));
} else if (Lo) {
// Handle the Hi bits.
unsigned OpC = Hi ? PPC::LIS8 : PPC::LI8;
- Result = CurDAG->getTargetNode(OpC, dl, EVT::i64, getI32Imm(Hi));
+ Result = CurDAG->getTargetNode(OpC, dl, MVT::i64, getI32Imm(Hi));
// And Lo bits.
- Result = CurDAG->getTargetNode(PPC::ORI8, dl, EVT::i64,
+ Result = CurDAG->getTargetNode(PPC::ORI8, dl, MVT::i64,
SDValue(Result, 0), getI32Imm(Lo));
} else {
// Just the Hi bits.
- Result = CurDAG->getTargetNode(PPC::LIS8, dl, EVT::i64, getI32Imm(Hi));
+ Result = CurDAG->getTargetNode(PPC::LIS8, dl, MVT::i64, getI32Imm(Hi));
}
// If no shift, we're done.
// Shift for next step if the upper 32-bits were not zero.
if (Imm) {
- Result = CurDAG->getTargetNode(PPC::RLDICR, dl, EVT::i64,
+ Result = CurDAG->getTargetNode(PPC::RLDICR, dl, MVT::i64,
SDValue(Result, 0),
getI32Imm(Shift), getI32Imm(63 - Shift));
}
// Add in the last bits as required.
if ((Hi = (Remainder >> 16) & 0xFFFF)) {
- Result = CurDAG->getTargetNode(PPC::ORIS8, dl, EVT::i64,
+ Result = CurDAG->getTargetNode(PPC::ORIS8, dl, MVT::i64,
SDValue(Result, 0), getI32Imm(Hi));
}
if ((Lo = Remainder & 0xFFFF)) {
- Result = CurDAG->getTargetNode(PPC::ORI8, dl, EVT::i64,
+ Result = CurDAG->getTargetNode(PPC::ORI8, dl, MVT::i64,
SDValue(Result, 0), getI32Imm(Lo));
}
case ISD::FrameIndex: {
int FI = cast<FrameIndexSDNode>(N)->getIndex();
SDValue TFI = CurDAG->getTargetFrameIndex(FI, Op.getValueType());
- unsigned Opc = Op.getValueType() == EVT::i32 ? PPC::ADDI : PPC::ADDI8;
+ unsigned Opc = Op.getValueType() == MVT::i32 ? PPC::ADDI : PPC::ADDI8;
if (N->hasOneUse())
return CurDAG->SelectNodeTo(N, Opc, Op.getValueType(), TFI,
getSmallIPtrImm(0));
SDValue InFlag = N->getOperand(1);
// Use MFOCRF if supported.
if (PPCSubTarget.isGigaProcessor())
- return CurDAG->getTargetNode(PPC::MFOCRF, dl, EVT::i32,
+ return CurDAG->getTargetNode(PPC::MFOCRF, dl, MVT::i32,
N->getOperand(0), InFlag);
else
- return CurDAG->getTargetNode(PPC::MFCR, dl, EVT::i32, InFlag);
+ return CurDAG->getTargetNode(PPC::MFCR, dl, MVT::i32, InFlag);
}
case ISD::SDIV: {
SDValue N0 = N->getOperand(0);
if ((signed)Imm > 0 && isPowerOf2_32(Imm)) {
SDNode *Op =
- CurDAG->getTargetNode(PPC::SRAWI, dl, EVT::i32, EVT::Flag,
+ CurDAG->getTargetNode(PPC::SRAWI, dl, MVT::i32, MVT::Flag,
N0, getI32Imm(Log2_32(Imm)));
- return CurDAG->SelectNodeTo(N, PPC::ADDZE, EVT::i32,
+ return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
SDValue(Op, 0), SDValue(Op, 1));
} else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) {
SDNode *Op =
- CurDAG->getTargetNode(PPC::SRAWI, dl, EVT::i32, EVT::Flag,
+ CurDAG->getTargetNode(PPC::SRAWI, dl, MVT::i32, MVT::Flag,
N0, getI32Imm(Log2_32(-Imm)));
SDValue PT =
- SDValue(CurDAG->getTargetNode(PPC::ADDZE, dl, EVT::i32,
+ SDValue(CurDAG->getTargetNode(PPC::ADDZE, dl, MVT::i32,
SDValue(Op, 0), SDValue(Op, 1)),
0);
- return CurDAG->SelectNodeTo(N, PPC::NEG, EVT::i32, PT);
+ return CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT);
}
}
unsigned Opcode;
bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
- if (LD->getValueType(0) != EVT::i64) {
+ if (LD->getValueType(0) != MVT::i64) {
// Handle PPC32 integer and normal FP loads.
- assert((!isSExt || LoadedVT == EVT::i16) && "Invalid sext update load");
- switch (LoadedVT.getSimpleVT()) {
+ assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
+ switch (LoadedVT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("Invalid PPC load type!");
- case EVT::f64: Opcode = PPC::LFDU; break;
- case EVT::f32: Opcode = PPC::LFSU; break;
- case EVT::i32: Opcode = PPC::LWZU; break;
- case EVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break;
- case EVT::i1:
- case EVT::i8: Opcode = PPC::LBZU; break;
+ case MVT::f64: Opcode = PPC::LFDU; break;
+ case MVT::f32: Opcode = PPC::LFSU; break;
+ case MVT::i32: Opcode = PPC::LWZU; break;
+ case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break;
+ case MVT::i1:
+ case MVT::i8: Opcode = PPC::LBZU; break;
}
} else {
- assert(LD->getValueType(0) == EVT::i64 && "Unknown load result type!");
- assert((!isSExt || LoadedVT == EVT::i16) && "Invalid sext update load");
- switch (LoadedVT.getSimpleVT()) {
+ assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
+ assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
+ switch (LoadedVT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("Invalid PPC load type!");
- case EVT::i64: Opcode = PPC::LDU; break;
- case EVT::i32: Opcode = PPC::LWZU8; break;
- case EVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break;
- case EVT::i1:
- case EVT::i8: Opcode = PPC::LBZU8; break;
+ case MVT::i64: Opcode = PPC::LDU; break;
+ case MVT::i32: Opcode = PPC::LWZU8; break;
+ case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break;
+ case MVT::i1:
+ case MVT::i8: Opcode = PPC::LBZU8; break;
}
}
// FIXME: PPC64
return CurDAG->getTargetNode(Opcode, dl, LD->getValueType(0),
PPCLowering.getPointerTy(),
- EVT::Other, Ops, 3);
+ MVT::Other, Ops, 3);
} else {
llvm_unreachable("R+R preindex loads not supported yet!");
}
isRotateAndMask(N->getOperand(0).getNode(), Imm, false, SH, MB, ME)) {
SDValue Val = N->getOperand(0).getOperand(0);
SDValue Ops[] = { Val, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
- return CurDAG->SelectNodeTo(N, PPC::RLWINM, EVT::i32, Ops, 4);
+ return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
}
// If this is just a masked value where the input is not handled above, and
// is not a rotate-left (handled by a pattern in the .td file), emit rlwinm
N->getOperand(0).getOpcode() != ISD::ROTL) {
SDValue Val = N->getOperand(0);
SDValue Ops[] = { Val, getI32Imm(0), getI32Imm(MB), getI32Imm(ME) };
- return CurDAG->SelectNodeTo(N, PPC::RLWINM, EVT::i32, Ops, 4);
+ return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
}
// AND X, 0 -> 0, not "rlwinm 32".
if (isInt32Immediate(N->getOperand(1), Imm) && (Imm == 0)) {
SDValue Ops[] = { N->getOperand(0).getOperand(0),
N->getOperand(0).getOperand(1),
getI32Imm(0), getI32Imm(MB),getI32Imm(ME) };
- return CurDAG->getTargetNode(PPC::RLWIMI, dl, EVT::i32, Ops, 5);
+ return CurDAG->getTargetNode(PPC::RLWIMI, dl, MVT::i32, Ops, 5);
}
}
break;
}
case ISD::OR:
- if (N->getValueType(0) == EVT::i32)
+ if (N->getValueType(0) == MVT::i32)
if (SDNode *I = SelectBitfieldInsert(N))
return I;
isRotateAndMask(N, Imm, true, SH, MB, ME)) {
SDValue Ops[] = { N->getOperand(0).getOperand(0),
getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
- return CurDAG->SelectNodeTo(N, PPC::RLWINM, EVT::i32, Ops, 4);
+ return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
}
// Other cases are autogenerated.
isRotateAndMask(N, Imm, true, SH, MB, ME)) {
SDValue Ops[] = { N->getOperand(0).getOperand(0),
getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
- return CurDAG->SelectNodeTo(N, PPC::RLWINM, EVT::i32, Ops, 4);
+ return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
}
// Other cases are autogenerated.
if (N1C->isNullValue() && N3C->isNullValue() &&
N2C->getZExtValue() == 1ULL && CC == ISD::SETNE &&
// FIXME: Implement this optzn for PPC64.
- N->getValueType(0) == EVT::i32) {
+ N->getValueType(0) == MVT::i32) {
SDNode *Tmp =
- CurDAG->getTargetNode(PPC::ADDIC, dl, EVT::i32, EVT::Flag,
+ CurDAG->getTargetNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag,
N->getOperand(0), getI32Imm(~0U));
- return CurDAG->SelectNodeTo(N, PPC::SUBFE, EVT::i32,
+ return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32,
SDValue(Tmp, 0), N->getOperand(0),
SDValue(Tmp, 1));
}
unsigned BROpc = getPredicateForSetCC(CC);
unsigned SelectCCOp;
- if (N->getValueType(0) == EVT::i32)
+ if (N->getValueType(0) == MVT::i32)
SelectCCOp = PPC::SELECT_CC_I4;
- else if (N->getValueType(0) == EVT::i64)
+ else if (N->getValueType(0) == MVT::i64)
SelectCCOp = PPC::SELECT_CC_I8;
- else if (N->getValueType(0) == EVT::f32)
+ else if (N->getValueType(0) == MVT::f32)
SelectCCOp = PPC::SELECT_CC_F4;
- else if (N->getValueType(0) == EVT::f64)
+ else if (N->getValueType(0) == MVT::f64)
SelectCCOp = PPC::SELECT_CC_F8;
else
SelectCCOp = PPC::SELECT_CC_VRRC;
getI32Imm(cast<ConstantSDNode>(N->getOperand(1))->getZExtValue());
SDValue Ops[] = { Pred, N->getOperand(2), N->getOperand(3),
N->getOperand(0), N->getOperand(4) };
- return CurDAG->SelectNodeTo(N, PPC::BCC, EVT::Other, Ops, 5);
+ return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 5);
}
case ISD::BR_CC: {
ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl);
SDValue Ops[] = { getI32Imm(getPredicateForSetCC(CC)), CondCode,
N->getOperand(4), N->getOperand(0) };
- return CurDAG->SelectNodeTo(N, PPC::BCC, EVT::Other, Ops, 4);
+ return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 4);
}
case ISD::BRIND: {
// FIXME: Should custom lower this.
SDValue Chain = N->getOperand(0);
SDValue Target = N->getOperand(1);
- unsigned Opc = Target.getValueType() == EVT::i32 ? PPC::MTCTR : PPC::MTCTR8;
- Chain = SDValue(CurDAG->getTargetNode(Opc, dl, EVT::Other, Target,
+ unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8;
+ Chain = SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Other, Target,
Chain), 0);
- return CurDAG->SelectNodeTo(N, PPC::BCTR, EVT::Other, Chain);
+ return CurDAG->SelectNodeTo(N, PPC::BCTR, MVT::Other, Chain);
}
case ISD::DECLARE: {
SDValue Chain = N->getOperand(0);
SDValue Tmp1 = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
SDValue Tmp2 = CurDAG->getTargetGlobalAddress(GV, TLI.getPointerTy());
return CurDAG->SelectNodeTo(N, TargetInstrInfo::DECLARE,
- EVT::Other, Tmp1, Tmp2, Chain);
+ MVT::Other, Tmp1, Tmp2, Chain);
}
}
index 0debf67c87b7db2c778d2189d3759c4d4cb4e109..caeba447ce43b874e991f0073f6ea37efd48bdde 100644 (file)
setUseUnderscoreLongJmp(true);
// Set up the register classes.
- addRegisterClass(EVT::i32, PPC::GPRCRegisterClass);
- addRegisterClass(EVT::f32, PPC::F4RCRegisterClass);
- addRegisterClass(EVT::f64, PPC::F8RCRegisterClass);
+ addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
+ addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
+ addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
// PowerPC has an i16 but no i8 (or i1) SEXTLOAD
- setLoadExtAction(ISD::SEXTLOAD, EVT::i1, Promote);
- setLoadExtAction(ISD::SEXTLOAD, EVT::i8, Expand);
+ setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
+ setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
- setTruncStoreAction(EVT::f64, EVT::f32, Expand);
+ setTruncStoreAction(MVT::f64, MVT::f32, Expand);
// PowerPC has pre-inc load and store's.
- setIndexedLoadAction(ISD::PRE_INC, EVT::i1, Legal);
- setIndexedLoadAction(ISD::PRE_INC, EVT::i8, Legal);
- setIndexedLoadAction(ISD::PRE_INC, EVT::i16, Legal);
- setIndexedLoadAction(ISD::PRE_INC, EVT::i32, Legal);
- setIndexedLoadAction(ISD::PRE_INC, EVT::i64, Legal);
- setIndexedStoreAction(ISD::PRE_INC, EVT::i1, Legal);
- setIndexedStoreAction(ISD::PRE_INC, EVT::i8, Legal);
- setIndexedStoreAction(ISD::PRE_INC, EVT::i16, Legal);
- setIndexedStoreAction(ISD::PRE_INC, EVT::i32, Legal);
- setIndexedStoreAction(ISD::PRE_INC, EVT::i64, Legal);
+ setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
+ setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
+ setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
+ setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
+ setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
+ setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
+ setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
+ setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
+ setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
+ setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
// This is used in the ppcf128->int sequence. Note it has different semantics
// from FP_ROUND: that rounds to nearest, this rounds to zero.
- setOperationAction(ISD::FP_ROUND_INREG, EVT::ppcf128, Custom);
+ setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
// PowerPC has no SREM/UREM instructions
- setOperationAction(ISD::SREM, EVT::i32, Expand);
- setOperationAction(ISD::UREM, EVT::i32, Expand);
- setOperationAction(ISD::SREM, EVT::i64, Expand);
- setOperationAction(ISD::UREM, EVT::i64, Expand);
+ setOperationAction(ISD::SREM, MVT::i32, Expand);
+ setOperationAction(ISD::UREM, MVT::i32, Expand);
+ setOperationAction(ISD::SREM, MVT::i64, Expand);
+ setOperationAction(ISD::UREM, MVT::i64, Expand);
// Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
- setOperationAction(ISD::UMUL_LOHI, EVT::i32, Expand);
- setOperationAction(ISD::SMUL_LOHI, EVT::i32, Expand);
- setOperationAction(ISD::UMUL_LOHI, EVT::i64, Expand);
- setOperationAction(ISD::SMUL_LOHI, EVT::i64, Expand);
- setOperationAction(ISD::UDIVREM, EVT::i32, Expand);
- setOperationAction(ISD::SDIVREM, EVT::i32, Expand);
- setOperationAction(ISD::UDIVREM, EVT::i64, Expand);
- setOperationAction(ISD::SDIVREM, EVT::i64, Expand);
+ setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
+ setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
+ setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
+ setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
+ setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
+ setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
+ setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
+ setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
// We don't support sin/cos/sqrt/fmod/pow
- setOperationAction(ISD::FSIN , EVT::f64, Expand);
- setOperationAction(ISD::FCOS , EVT::f64, Expand);
- setOperationAction(ISD::FREM , EVT::f64, Expand);
- setOperationAction(ISD::FPOW , EVT::f64, Expand);
- setOperationAction(ISD::FSIN , EVT::f32, Expand);
- setOperationAction(ISD::FCOS , EVT::f32, Expand);
- setOperationAction(ISD::FREM , EVT::f32, Expand);
- setOperationAction(ISD::FPOW , EVT::f32, Expand);
+ setOperationAction(ISD::FSIN , MVT::f64, Expand);
+ setOperationAction(ISD::FCOS , MVT::f64, Expand);
+ setOperationAction(ISD::FREM , MVT::f64, Expand);
+ setOperationAction(ISD::FPOW , MVT::f64, Expand);
+ setOperationAction(ISD::FSIN , MVT::f32, Expand);
+ setOperationAction(ISD::FCOS , MVT::f32, Expand);
+ setOperationAction(ISD::FREM , MVT::f32, Expand);
+ setOperationAction(ISD::FPOW , MVT::f32, Expand);
- setOperationAction(ISD::FLT_ROUNDS_, EVT::i32, Custom);
+ setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
// If we're enabling GP optimizations, use hardware square root
if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
- setOperationAction(ISD::FSQRT, EVT::f64, Expand);
- setOperationAction(ISD::FSQRT, EVT::f32, Expand);
+ setOperationAction(ISD::FSQRT, MVT::f64, Expand);
+ setOperationAction(ISD::FSQRT, MVT::f32, Expand);
}
- setOperationAction(ISD::FCOPYSIGN, EVT::f64, Expand);
- setOperationAction(ISD::FCOPYSIGN, EVT::f32, Expand);
+ setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
+ setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
// PowerPC does not have BSWAP, CTPOP or CTTZ
- setOperationAction(ISD::BSWAP, EVT::i32 , Expand);
- setOperationAction(ISD::CTPOP, EVT::i32 , Expand);
- setOperationAction(ISD::CTTZ , EVT::i32 , Expand);
- setOperationAction(ISD::BSWAP, EVT::i64 , Expand);
- setOperationAction(ISD::CTPOP, EVT::i64 , Expand);
- setOperationAction(ISD::CTTZ , EVT::i64 , Expand);
+ setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
+ setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
+ setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
+ setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
+ setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
+ setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
// PowerPC does not have ROTR
- setOperationAction(ISD::ROTR, EVT::i32 , Expand);
- setOperationAction(ISD::ROTR, EVT::i64 , Expand);
+ setOperationAction(ISD::ROTR, MVT::i32 , Expand);
+ setOperationAction(ISD::ROTR, MVT::i64 , Expand);
// PowerPC does not have Select
- setOperationAction(ISD::SELECT, EVT::i32, Expand);
- setOperationAction(ISD::SELECT, EVT::i64, Expand);
- setOperationAction(ISD::SELECT, EVT::f32, Expand);
- setOperationAction(ISD::SELECT, EVT::f64, Expand);
+ setOperationAction(ISD::SELECT, MVT::i32, Expand);
+ setOperationAction(ISD::SELECT, MVT::i64, Expand);
+ setOperationAction(ISD::SELECT, MVT::f32, Expand);
+ setOperationAction(ISD::SELECT, MVT::f64, Expand);
// PowerPC wants to turn select_cc of FP into fsel when possible.
- setOperationAction(ISD::SELECT_CC, EVT::f32, Custom);
- setOperationAction(ISD::SELECT_CC, EVT::f64, Custom);
+ setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
+ setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
// PowerPC wants to optimize integer setcc a bit
- setOperationAction(ISD::SETCC, EVT::i32, Custom);
+ setOperationAction(ISD::SETCC, MVT::i32, Custom);
// PowerPC does not have BRCOND which requires SetCC
- setOperationAction(ISD::BRCOND, EVT::Other, Expand);
+ setOperationAction(ISD::BRCOND, MVT::Other, Expand);
- setOperationAction(ISD::BR_JT, EVT::Other, Expand);
+ setOperationAction(ISD::BR_JT, MVT::Other, Expand);
// PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
- setOperationAction(ISD::FP_TO_SINT, EVT::i32, Custom);
+ setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
// PowerPC does not have [U|S]INT_TO_FP
- setOperationAction(ISD::SINT_TO_FP, EVT::i32, Expand);
- setOperationAction(ISD::UINT_TO_FP, EVT::i32, Expand);
+ setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
+ setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
- setOperationAction(ISD::BIT_CONVERT, EVT::f32, Expand);
- setOperationAction(ISD::BIT_CONVERT, EVT::i32, Expand);
- setOperationAction(ISD::BIT_CONVERT, EVT::i64, Expand);
- setOperationAction(ISD::BIT_CONVERT, EVT::f64, Expand);
+ setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
+ setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
+ setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand);
+ setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand);
// We cannot sextinreg(i1). Expand to shifts.
- setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i1, Expand);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
// Support label based line numbers.
- setOperationAction(ISD::DBG_STOPPOINT, EVT::Other, Expand);
- setOperationAction(ISD::DEBUG_LOC, EVT::Other, Expand);
+ setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
+ setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
- setOperationAction(ISD::EXCEPTIONADDR, EVT::i64, Expand);
- setOperationAction(ISD::EHSELECTION, EVT::i64, Expand);
- setOperationAction(ISD::EXCEPTIONADDR, EVT::i32, Expand);
- setOperationAction(ISD::EHSELECTION, EVT::i32, Expand);
+ setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
+ setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
+ setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
+ setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
// We want to legalize GlobalAddress and ConstantPool nodes into the
// appropriate instructions to materialize the address.
- setOperationAction(ISD::GlobalAddress, EVT::i32, Custom);
- setOperationAction(ISD::GlobalTLSAddress, EVT::i32, Custom);
- setOperationAction(ISD::ConstantPool, EVT::i32, Custom);
- setOperationAction(ISD::JumpTable, EVT::i32, Custom);
- setOperationAction(ISD::GlobalAddress, EVT::i64, Custom);
- setOperationAction(ISD::GlobalTLSAddress, EVT::i64, Custom);
- setOperationAction(ISD::ConstantPool, EVT::i64, Custom);
- setOperationAction(ISD::JumpTable, EVT::i64, Custom);
+ setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
+ setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
+ setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
+ setOperationAction(ISD::JumpTable, MVT::i32, Custom);
+ setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
+ setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
+ setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
+ setOperationAction(ISD::JumpTable, MVT::i64, Custom);
// TRAP is legal.
- setOperationAction(ISD::TRAP, EVT::Other, Legal);
+ setOperationAction(ISD::TRAP, MVT::Other, Legal);
// TRAMPOLINE is custom lowered.
- setOperationAction(ISD::TRAMPOLINE, EVT::Other, Custom);
+ setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
// VASTART needs to be custom lowered to use the VarArgsFrameIndex
- setOperationAction(ISD::VASTART , EVT::Other, Custom);
+ setOperationAction(ISD::VASTART , MVT::Other, Custom);
// VAARG is custom lowered with the SVR4 ABI
if (TM.getSubtarget<PPCSubtarget>().isSVR4ABI())
- setOperationAction(ISD::VAARG, EVT::Other, Custom);
+ setOperationAction(ISD::VAARG, MVT::Other, Custom);
else
- setOperationAction(ISD::VAARG, EVT::Other, Expand);
+ setOperationAction(ISD::VAARG, MVT::Other, Expand);
// Use the default implementation.
- setOperationAction(ISD::VACOPY , EVT::Other, Expand);
- setOperationAction(ISD::VAEND , EVT::Other, Expand);
- setOperationAction(ISD::STACKSAVE , EVT::Other, Expand);
- setOperationAction(ISD::STACKRESTORE , EVT::Other, Custom);
- setOperationAction(ISD::DYNAMIC_STACKALLOC, EVT::i32 , Custom);
- setOperationAction(ISD::DYNAMIC_STACKALLOC, EVT::i64 , Custom);
+ setOperationAction(ISD::VACOPY , MVT::Other, Expand);
+ setOperationAction(ISD::VAEND , MVT::Other, Expand);
+ setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
+ setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
+ setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
+ setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
// We want to custom lower some of our intrinsics.
- setOperationAction(ISD::INTRINSIC_WO_CHAIN, EVT::Other, Custom);
+ setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
// Comparisons that require checking two conditions.
- setCondCodeAction(ISD::SETULT, EVT::f32, Expand);
- setCondCodeAction(ISD::SETULT, EVT::f64, Expand);
- setCondCodeAction(ISD::SETUGT, EVT::f32, Expand);
- setCondCodeAction(ISD::SETUGT, EVT::f64, Expand);
- setCondCodeAction(ISD::SETUEQ, EVT::f32, Expand);
- setCondCodeAction(ISD::SETUEQ, EVT::f64, Expand);
- setCondCodeAction(ISD::SETOGE, EVT::f32, Expand);
- setCondCodeAction(ISD::SETOGE, EVT::f64, Expand);
- setCondCodeAction(ISD::SETOLE, EVT::f32, Expand);
- setCondCodeAction(ISD::SETOLE, EVT::f64, Expand);
- setCondCodeAction(ISD::SETONE, EVT::f32, Expand);
- setCondCodeAction(ISD::SETONE, EVT::f64, Expand);
+ setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
+ setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
+ setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
+ setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
+ setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
+ setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
+ setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
+ setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
+ setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
+ setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
+ setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
+ setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
// They also have instructions for converting between i64 and fp.
- setOperationAction(ISD::FP_TO_SINT, EVT::i64, Custom);
- setOperationAction(ISD::FP_TO_UINT, EVT::i64, Expand);
- setOperationAction(ISD::SINT_TO_FP, EVT::i64, Custom);
- setOperationAction(ISD::UINT_TO_FP, EVT::i64, Expand);
+ setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
+ setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
+ setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
+ setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
// This is just the low 32 bits of a (signed) fp->i64 conversion.
// We cannot do this with Promote because i64 is not a legal type.
- setOperationAction(ISD::FP_TO_UINT, EVT::i32, Custom);
+ setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
// FIXME: disable this lowered code. This generates 64-bit register values,
// and we don't model the fact that the top part is clobbered by calls. We
// need to flag these together so that the value isn't live across a call.
- //setOperationAction(ISD::SINT_TO_FP, EVT::i32, Custom);
+ //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
} else {
// PowerPC does not have FP_TO_UINT on 32-bit implementations.
- setOperationAction(ISD::FP_TO_UINT, EVT::i32, Expand);
+ setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
}
if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) {
// 64-bit PowerPC implementations can support i64 types directly
- addRegisterClass(EVT::i64, PPC::G8RCRegisterClass);
+ addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
// BUILD_PAIR can't be handled natively, and should be expanded to shl/or
- setOperationAction(ISD::BUILD_PAIR, EVT::i64, Expand);
+ setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
// 64-bit PowerPC wants to expand i128 shifts itself.
- setOperationAction(ISD::SHL_PARTS, EVT::i64, Custom);
- setOperationAction(ISD::SRA_PARTS, EVT::i64, Custom);
- setOperationAction(ISD::SRL_PARTS, EVT::i64, Custom);
+ setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
+ setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
+ setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
} else {
// 32-bit PowerPC wants to expand i64 shifts itself.
- setOperationAction(ISD::SHL_PARTS, EVT::i32, Custom);
- setOperationAction(ISD::SRA_PARTS, EVT::i32, Custom);
- setOperationAction(ISD::SRL_PARTS, EVT::i32, Custom);
+ setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
+ setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
+ setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
}
if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
// First set operation action for all vector types to expand. Then we
// will selectively turn on ones that can be effectively codegen'd.
- for (unsigned i = (unsigned)EVT::FIRST_VECTOR_VALUETYPE;
- i <= (unsigned)EVT::LAST_VECTOR_VALUETYPE; ++i) {
- EVT::SimpleValueType VT = (EVT::SimpleValueType)i;
+ for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
+ i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
+ MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
// add/sub are legal for all supported vector VT's.
setOperationAction(ISD::ADD , VT, Legal);
// We promote all shuffles to v16i8.
setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
- AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, EVT::v16i8);
+ AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
// We promote all non-typed operations to v4i32.
setOperationAction(ISD::AND , VT, Promote);
- AddPromotedToType (ISD::AND , VT, EVT::v4i32);
+ AddPromotedToType (ISD::AND , VT, MVT::v4i32);
setOperationAction(ISD::OR , VT, Promote);
- AddPromotedToType (ISD::OR , VT, EVT::v4i32);
+ AddPromotedToType (ISD::OR , VT, MVT::v4i32);
setOperationAction(ISD::XOR , VT, Promote);
- AddPromotedToType (ISD::XOR , VT, EVT::v4i32);
+ AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
setOperationAction(ISD::LOAD , VT, Promote);
- AddPromotedToType (ISD::LOAD , VT, EVT::v4i32);
+ AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
setOperationAction(ISD::SELECT, VT, Promote);
- AddPromotedToType (ISD::SELECT, VT, EVT::v4i32);
+ AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
setOperationAction(ISD::STORE, VT, Promote);
- AddPromotedToType (ISD::STORE, VT, EVT::v4i32);
+ AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
// No other operations are legal.
setOperationAction(ISD::MUL , VT, Expand);
// We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
// with merges, splats, etc.
- setOperationAction(ISD::VECTOR_SHUFFLE, EVT::v16i8, Custom);
-
- setOperationAction(ISD::AND , EVT::v4i32, Legal);
- setOperationAction(ISD::OR , EVT::v4i32, Legal);
- setOperationAction(ISD::XOR , EVT::v4i32, Legal);
- setOperationAction(ISD::LOAD , EVT::v4i32, Legal);
- setOperationAction(ISD::SELECT, EVT::v4i32, Expand);
- setOperationAction(ISD::STORE , EVT::v4i32, Legal);
-
- addRegisterClass(EVT::v4f32, PPC::VRRCRegisterClass);
- addRegisterClass(EVT::v4i32, PPC::VRRCRegisterClass);
- addRegisterClass(EVT::v8i16, PPC::VRRCRegisterClass);
- addRegisterClass(EVT::v16i8, PPC::VRRCRegisterClass);
-
- setOperationAction(ISD::MUL, EVT::v4f32, Legal);
- setOperationAction(ISD::MUL, EVT::v4i32, Custom);
- setOperationAction(ISD::MUL, EVT::v8i16, Custom);
- setOperationAction(ISD::MUL, EVT::v16i8, Custom);
-
- setOperationAction(ISD::SCALAR_TO_VECTOR, EVT::v4f32, Custom);
- setOperationAction(ISD::SCALAR_TO_VECTOR, EVT::v4i32, Custom);
-
- setOperationAction(ISD::BUILD_VECTOR, EVT::v16i8, Custom);
- setOperationAction(ISD::BUILD_VECTOR, EVT::v8i16, Custom);
- setOperationAction(ISD::BUILD_VECTOR, EVT::v4i32, Custom);
- setOperationAction(ISD::BUILD_VECTOR, EVT::v4f32, Custom);
+ setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
+
+ setOperationAction(ISD::AND , MVT::v4i32, Legal);
+ setOperationAction(ISD::OR , MVT::v4i32, Legal);
+ setOperationAction(ISD::XOR , MVT::v4i32, Legal);
+ setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
+ setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
+ setOperationAction(ISD::STORE , MVT::v4i32, Legal);
+
+ addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
+ addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
+ addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
+ addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
+
+ setOperationAction(ISD::MUL, MVT::v4f32, Legal);
+ setOperationAction(ISD::MUL, MVT::v4i32, Custom);
+ setOperationAction(ISD::MUL, MVT::v8i16, Custom);
+ setOperationAction(ISD::MUL, MVT::v16i8, Custom);
+
+ setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
+ setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
+
+ setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
+ setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
+ setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
+ setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
}
- setShiftAmountType(EVT::i32);
+ setShiftAmountType(MVT::i32);
setBooleanContents(ZeroOrOneBooleanContent);
if (TM.getSubtarget<PPCSubtarget>().isPPC64()) {
}
}
-EVT::SimpleValueType PPCTargetLowering::getSetCCResultType(EVT VT) const {
- return EVT::i32;
+MVT::SimpleValueType PPCTargetLowering::getSetCCResultType(EVT VT) const {
+ return MVT::i32;
}
/// getFunctionAlignment - Return the Log2 alignment of this function.
///
static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
unsigned LHSStart, unsigned RHSStart) {
- assert(N->getValueType(0) == EVT::v16i8 &&
+ assert(N->getValueType(0) == MVT::v16i8 &&
"PPC only supports shuffles by bytes!");
assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
"Unsupported merge size!");
/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
/// amount, otherwise return -1.
int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
- assert(N->getValueType(0) == EVT::v16i8 &&
+ assert(N->getValueType(0) == MVT::v16i8 &&
"PPC only supports shuffles by bytes!");
ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
/// specifies a splat of a single element that is suitable for input to
/// VSPLTB/VSPLTH/VSPLTW.
bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
- assert(N->getValueType(0) == EVT::v16i8 &&
+ assert(N->getValueType(0) == MVT::v16i8 &&
(EltSize == 1 || EltSize == 2 || EltSize == 4));
// This is a splat operation if each element of the permute is the same, and
@@ -694,17 +694,17 @@ SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
// Finally, check the least significant entry.
if (LeadingZero) {
if (UniquedVals[Multiple-1].getNode() == 0)
- return DAG.getTargetConstant(0, EVT::i32); // 0,0,0,undef
+ return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
if (Val < 16)
- return DAG.getTargetConstant(Val, EVT::i32); // 0,0,0,4 -> vspltisw(4)
+ return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
}
if (LeadingOnes) {
if (UniquedVals[Multiple-1].getNode() == 0)
- return DAG.getTargetConstant(~0U, EVT::i32); // -1,-1,-1,undef
+ return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
- return DAG.getTargetConstant(Val, EVT::i32);
+ return DAG.getTargetConstant(Val, MVT::i32);
}
return SDValue();
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
Value = CN->getZExtValue();
} else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
- assert(CN->getValueType(0) == EVT::f32 && "Only one legal FP vector type!");
+ assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
Value = FloatToBits(CN->getValueAPF().convertToFloat());
}
// Finally, if this value fits in a 5 bit sext field, return it
if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
- return DAG.getTargetConstant(MaskVal, EVT::i32);
+ return DAG.getTargetConstant(MaskVal, MVT::i32);
return SDValue();
}
return false;
Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
- if (N->getValueType(0) == EVT::i32)
+ if (N->getValueType(0) == MVT::i32)
return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
else
return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
if (N.getOpcode() == ISD::ADD) {
short imm = 0;
if (isIntS16Immediate(N.getOperand(1), imm)) {
- Disp = DAG.getTargetConstant((int)imm & 0xFFFF, EVT::i32);
+ Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
} else {
// If all of the bits are known zero on the LHS or RHS, the add won't
// carry.
Base = N.getOperand(0);
- Disp = DAG.getTargetConstant((int)imm & 0xFFFF, EVT::i32);
+ Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
return true;
}
}
}
// Handle 32-bit sext immediates with LIS + addr mode.
- if (CN->getValueType(0) == EVT::i32 ||
+ if (CN->getValueType(0) == MVT::i32 ||
(int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
int Addr = (int)CN->getZExtValue();
// Otherwise, break this down into an LIS + disp.
- Disp = DAG.getTargetConstant((short)Addr, EVT::i32);
+ Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
- Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, EVT::i32);
- unsigned Opc = CN->getValueType(0) == EVT::i32 ? PPC::LIS : PPC::LIS8;
+ Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
+ unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
Base = SDValue(DAG.getTargetNode(Opc, dl, CN->getValueType(0), Base), 0);
return true;
}
if (N.getOpcode() == ISD::ADD) {
short imm = 0;
if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
- Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, EVT::i32);
+ Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
} else {
// If all of the bits are known zero on the LHS or RHS, the add won't
// carry.
Base = N.getOperand(0);
- Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, EVT::i32);
+ Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
return true;
}
}
}
// Fold the low-part of 32-bit absolute addresses into addr mode.
- if (CN->getValueType(0) == EVT::i32 ||
+ if (CN->getValueType(0) == MVT::i32 ||
(int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
int Addr = (int)CN->getZExtValue();
// Otherwise, break this down into an LIS + disp.
- Disp = DAG.getTargetConstant((short)Addr >> 2, EVT::i32);
- Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, EVT::i32);
- unsigned Opc = CN->getValueType(0) == EVT::i32 ? PPC::LIS : PPC::LIS8;
+ Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
+ Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32);
+ unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
Base = SDValue(DAG.getTargetNode(Opc, dl, CN->getValueType(0), Base),0);
return true;
}
// TODO: Check reg+reg first.
// LDU/STU use reg+imm*4, others use reg+imm.
- if (VT != EVT::i64) {
+ if (VT != MVT::i64) {
// reg + imm
if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
return false;
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
// PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
// sext i32 to i64 when addr mode is r+i.
- if (LD->getValueType(0) == EVT::i64 && LD->getMemoryVT() == EVT::i32 &&
+ if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
LD->getExtensionType() == ISD::SEXTLOAD &&
isa<ConstantSDNode>(Offset))
return false;
if (C->isNullValue() && CC == ISD::SETEQ) {
EVT VT = Op.getOperand(0).getValueType();
SDValue Zext = Op.getOperand(0);
- if (VT.bitsLT(EVT::i32)) {
- VT = EVT::i32;
+ if (VT.bitsLT(MVT::i32)) {
+ VT = MVT::i32;
Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
}
unsigned Log2b = Log2_32(VT.getSizeInBits());
SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
- DAG.getConstant(Log2b, EVT::i32));
- return DAG.getNode(ISD::TRUNCATE, dl, EVT::i32, Scc);
+ DAG.getConstant(Log2b, MVT::i32));
+ return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
}
// Leave comparisons against 0 and -1 alone for now, since they're usually
// optimized. FIXME: revisit this when we can custom lower all setcc
DebugLoc dl = Op.getDebugLoc();
EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
- bool isPPC64 = (PtrVT == EVT::i64);
+ bool isPPC64 = (PtrVT == MVT::i64);
const Type *IntPtrTy =
DAG.getTargetLoweringInfo().getTargetData()->getIntPtrType();
// TrampSize == (isPPC64 ? 48 : 40);
Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
- isPPC64 ? EVT::i64 : EVT::i32);
+ isPPC64 ? MVT::i64 : MVT::i32);
Args.push_back(Entry);
Entry.Node = FPtr; Args.push_back(Entry);
// } va_list[1];
- SDValue ArgGPR = DAG.getConstant(VarArgsNumGPR, EVT::i32);
- SDValue ArgFPR = DAG.getConstant(VarArgsNumFPR, EVT::i32);
+ SDValue ArgGPR = DAG.getConstant(VarArgsNumGPR, MVT::i32);
+ SDValue ArgFPR = DAG.getConstant(VarArgsNumFPR, MVT::i32);
EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
// Store first byte : number of int regs
SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
- Op.getOperand(1), SV, 0, EVT::i8);
+ Op.getOperand(1), SV, 0, MVT::i8);
uint64_t nextOffset = FPROffset;
SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
ConstFPROffset);
// Store second byte : number of float regs
SDValue secondStore =
- DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr, SV, nextOffset, EVT::i8);
+ DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr, SV, nextOffset, MVT::i8);
nextOffset += StackOffset;
nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
TargetRegisterClass *RC;
EVT ValVT = VA.getValVT();
- switch (ValVT.getSimpleVT()) {
+ switch (ValVT.getSimpleVT().SimpleTy) {
default:
llvm_unreachable("ValVT not supported by formal arguments Lowering");
- case EVT::i32:
+ case MVT::i32:
RC = PPC::GPRCRegisterClass;
break;
- case EVT::f32:
+ case MVT::f32:
RC = PPC::F4RCRegisterClass;
break;
- case EVT::f64:
+ case MVT::f64:
RC = PPC::F8RCRegisterClass;
break;
- case EVT::v16i8:
- case EVT::v8i16:
- case EVT::v4i32:
- case EVT::v4f32:
+ case MVT::v16i8:
+ case MVT::v8i16:
+ case MVT::v4i32:
+ case MVT::v4f32:
RC = PPC::VRRCRegisterClass;
break;
}
// Make room for NumGPArgRegs and NumFPArgRegs.
int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
- NumFPArgRegs * EVT(EVT::f64).getSizeInBits()/8;
+ NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
VarArgsStackOffset = MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
CCInfo.getNextStackOffset());
// on the stack.
unsigned FPRIndex = 0;
for (FPRIndex = 0; FPRIndex != VarArgsNumFPR; ++FPRIndex) {
- SDValue Val = DAG.getRegister(FPArgRegs[FPRIndex], EVT::f64);
+ SDValue Val = DAG.getRegister(FPArgRegs[FPRIndex], MVT::f64);
SDValue Store = DAG.getStore(Chain, dl, Val, FIN, NULL, 0);
MemOps.push_back(Store);
// Increment the address by eight for the next argument to store
- SDValue PtrOff = DAG.getConstant(EVT(EVT::f64).getSizeInBits()/8,
+ SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
PtrVT);
FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
}
for (; FPRIndex != NumFPArgRegs; ++FPRIndex) {
unsigned VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
- SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, EVT::f64);
+ SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
MemOps.push_back(Store);
// Increment the address by eight for the next argument to store
- SDValue PtrOff = DAG.getConstant(EVT(EVT::f64).getSizeInBits()/8,
+ SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
PtrVT);
FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
}
if (!MemOps.empty())
Chain = DAG.getNode(ISD::TokenFactor, dl,
- EVT::Other, &MemOps[0], MemOps.size());
+ MVT::Other, &MemOps[0], MemOps.size());
return Chain;
}
MachineFrameInfo *MFI = MF.getFrameInfo();
EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
- bool isPPC64 = PtrVT == EVT::i64;
+ bool isPPC64 = PtrVT == MVT::i64;
// Potential tail calls could cause overwriting of argument stack slots.
bool isImmutable = !(PerformTailCallOpt && (CallConv==CallingConv::Fast));
unsigned PtrByteSize = isPPC64 ? 8 : 4;
continue;
}
- switch(ObjectVT.getSimpleVT()) {
+ switch(ObjectVT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unhandled argument type!");
- case EVT::i32:
- case EVT::f32:
+ case MVT::i32:
+ case MVT::f32:
VecArgOffset += isPPC64 ? 8 : 4;
break;
- case EVT::i64: // PPC64
- case EVT::f64:
+ case MVT::i64: // PPC64
+ case MVT::f64:
VecArgOffset += 8;
break;
- case EVT::v4f32:
- case EVT::v4i32:
- case EVT::v8i16:
- case EVT::v16i8:
+ case MVT::v4f32:
+ case MVT::v4i32:
+ case MVT::v8i16:
+ case MVT::v16i8:
// Nothing to do, we're only looking at Nonvector args here.
break;
}
unsigned CurArgOffset = ArgOffset;
// Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
- if (ObjectVT==EVT::v4f32 || ObjectVT==EVT::v4i32 ||
- ObjectVT==EVT::v8i16 || ObjectVT==EVT::v16i8) {
+ if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
+ ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
if (isVarArg || isPPC64) {
MinReservedArea = ((MinReservedArea+15)/16)*16;
MinReservedArea += CalculateStackSlotSize(ObjectVT,
unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
- NULL, 0, ObjSize==1 ? EVT::i8 : EVT::i16 );
+ NULL, 0, ObjSize==1 ? MVT::i8 : MVT::i16 );
MemOps.push_back(Store);
++GPR_idx;
}
continue;
}
- switch (ObjectVT.getSimpleVT()) {
+ switch (ObjectVT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unhandled argument type!");
- case EVT::i32:
+ case MVT::i32:
if (!isPPC64) {
if (GPR_idx != Num_GPR_Regs) {
unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
- ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, EVT::i32);
+ ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
++GPR_idx;
} else {
needsLoad = true;
break;
}
// FALLTHROUGH
- case EVT::i64: // PPC64
+ case MVT::i64: // PPC64
if (GPR_idx != Num_GPR_Regs) {
unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
- ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, EVT::i64);
+ ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
- if (ObjectVT == EVT::i32) {
+ if (ObjectVT == MVT::i32) {
// PPC64 passes i8, i16, and i32 values in i64 registers. Promote
- // value to EVT::i64 and then truncate to the correct register size.
+ // value to MVT::i64 and then truncate to the correct register size.
if (Flags.isSExt())
- ArgVal = DAG.getNode(ISD::AssertSext, dl, EVT::i64, ArgVal,
+ ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
DAG.getValueType(ObjectVT));
else if (Flags.isZExt())
- ArgVal = DAG.getNode(ISD::AssertZext, dl, EVT::i64, ArgVal,
+ ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
DAG.getValueType(ObjectVT));
- ArgVal = DAG.getNode(ISD::TRUNCATE, dl, EVT::i32, ArgVal);
+ ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
}
++GPR_idx;
ArgOffset += 8;
break;
- case EVT::f32:
- case EVT::f64:
+ case MVT::f32:
+ case MVT::f64:
// Every 4 bytes of argument space consumes one of the GPRs available for
// argument passing.
if (GPR_idx != Num_GPR_Regs) {
if (FPR_idx != Num_FPR_Regs) {
unsigned VReg;
- if (ObjectVT == EVT::f32)
+ if (ObjectVT == MVT::f32)
VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
else
VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
// All FP arguments reserve stack space in the Darwin ABI.
ArgOffset += isPPC64 ? 8 : ObjSize;
break;
- case EVT::v4f32:
- case EVT::v4i32:
- case EVT::v8i16:
- case EVT::v16i8:
+ case MVT::v4f32:
+ case MVT::v4i32:
+ case MVT::v8i16:
+ case MVT::v16i8:
// Note that vector arguments in registers don't reserve stack space,
// except in varargs functions.
if (VR_idx != Num_VR_Regs) {
if (!MemOps.empty())
Chain = DAG.getNode(ISD::TokenFactor, dl,
- EVT::Other, &MemOps[0], MemOps.size());
+ MVT::Other, &MemOps[0], MemOps.size());
return Chain;
}
ISD::ArgFlagsTy Flags = Outs[i].Flags;
EVT ArgVT = Arg.getValueType();
// Varargs Altivec parameters are padded to a 16 byte boundary.
- if (ArgVT==EVT::v4f32 || ArgVT==EVT::v4i32 ||
- ArgVT==EVT::v8i16 || ArgVT==EVT::v16i8) {
+ if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
+ ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) {
if (!isVarArg && !isPPC64) {
// Non-varargs Altivec parameters go after all the non-Altivec
// parameters; handle those later so we know how much padding we need.
isDarwinABI);
int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
NewRetAddrLoc);
- EVT VT = isPPC64 ? EVT::i64 : EVT::i32;
+ EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
PseudoSourceValue::getFixedStack(NewRetAddr), 0);
@@ -2284,7 +2284,7 @@ CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
int Offset = ArgOffset + SPDiff;
uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset);
- EVT VT = isPPC64 ? EVT::i64 : EVT::i32;
+ EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
SDValue FIN = DAG.getFrameIndex(FI, VT);
TailCallArgumentInfo Info;
Info.Arg = Arg;
DebugLoc dl) {
if (SPDiff) {
// Load the LR and FP stack slot for later adjusting.
- EVT VT = PPCSubTarget.isPPC64() ? EVT::i64 : EVT::i32;
+ EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
LROpOut = getReturnAddrFrameIndex(DAG);
LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, NULL, 0);
Chain = SDValue(LROpOut.getNode(), 1);
CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
DebugLoc dl) {
- SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), EVT::i32);
+ SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
false, NULL, 0, NULL, 0);
}
if (isVector) {
SDValue StackPtr;
if (isPPC64)
- StackPtr = DAG.getRegister(PPC::X1, EVT::i64);
+ StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
else
- StackPtr = DAG.getRegister(PPC::R1, EVT::i32);
+ StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
DAG.getConstant(ArgOffset, PtrVT));
}
StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
MemOpChains2, dl);
if (!MemOpChains2.empty())
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&MemOpChains2[0], MemOpChains2.size());
// Store the return address to the appropriate stack slot.
SmallVector<SDValue, 8> &Ops, std::vector<EVT> &NodeTys,
bool isSVR4ABI) {
EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
- NodeTys.push_back(EVT::Other); // Returns a chain
- NodeTys.push_back(EVT::Flag); // Returns a flag for retval copy to use.
+ NodeTys.push_back(MVT::Other); // Returns a chain
+ NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
unsigned CallOpc = isSVR4ABI ? PPCISD::CALL_SVR4 : PPCISD::CALL_Darwin;
InFlag = Chain.getValue(1);
NodeTys.clear();
- NodeTys.push_back(EVT::Other);
- NodeTys.push_back(EVT::Flag);
+ NodeTys.push_back(MVT::Other);
+ NodeTys.push_back(MVT::Flag);
Ops.push_back(Chain);
CallOpc = isSVR4ABI ? PPCISD::BCTRL_SVR4 : PPCISD::BCTRL_Darwin;
Callee.setNode(0);
}
// If this is a tail call add stack pointer delta.
if (isTailCall)
- Ops.push_back(DAG.getConstant(SPDiff, EVT::i32));
+ Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
// Add argument registers to the end of the list so that they are known live
// into the call.
@@ -2522,7 +2522,7 @@ PPCTargetLowering::FinishCall(unsigned CallConv, DebugLoc dl, bool isTailCall,
isa<ConstantSDNode>(Callee)) &&
"Expecting an global address, external symbol, absolute value or register");
- return DAG.getNode(PPCISD::TC_RETURN, dl, EVT::Other, &Ops[0], Ops.size());
+ return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Ops[0], Ops.size());
}
Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
// Set up a copy of the stack pointer for use loading and storing any
// arguments that may not fit in the registers available for argument
// passing.
- SDValue StackPtr = DAG.getRegister(PPC::R1, EVT::i32);
+ SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
}
if (!MemOpChains.empty())
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&MemOpChains[0], MemOpChains.size());
// Build a sequence of copy-to-reg nodes chained together with token chain
// Set CR6 to true if this is a vararg call.
if (isVarArg) {
- SDValue SetCR(DAG.getTargetNode(PPC::CRSET, dl, EVT::i32), 0);
+ SDValue SetCR(DAG.getTargetNode(PPC::CRSET, dl, MVT::i32), 0);
Chain = DAG.getCopyToReg(Chain, dl, PPC::CR1EQ, SetCR, InFlag);
InFlag = Chain.getValue(1);
}
unsigned NumOps = Outs.size();
EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
- bool isPPC64 = PtrVT == EVT::i64;
+ bool isPPC64 = PtrVT == MVT::i64;
unsigned PtrByteSize = isPPC64 ? 8 : 4;
MachineFunction &MF = DAG.getMachineFunction();
// passing.
SDValue StackPtr;
if (isPPC64)
- StackPtr = DAG.getRegister(PPC::X1, EVT::i64);
+ StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
else
- StackPtr = DAG.getRegister(PPC::R1, EVT::i32);
+ StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
// Figure out which arguments are going to go in registers, and which in
// memory. Also, if this is a vararg function, floating point operations
PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
// On PPC64, promote integers to 64-bit values.
- if (isPPC64 && Arg.getValueType() == EVT::i32) {
+ if (isPPC64 && Arg.getValueType() == MVT::i32) {
// FIXME: Should this use ANY_EXTEND if neither sext nor zext?
unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
- Arg = DAG.getNode(ExtOp, dl, EVT::i64, Arg);
+ Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
}
// FIXME memcpy is used way more than necessary. Correctness first.
if (Size==1 || Size==2) {
// Very small objects are passed right-justified.
// Everything else is passed left-justified.
- EVT VT = (Size==1) ? EVT::i8 : EVT::i16;
+ EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
if (GPR_idx != NumGPRs) {
SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
NULL, 0, VT);
continue;
}
- switch (Arg.getValueType().getSimpleVT()) {
+ switch (Arg.getValueType().getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unexpected ValueType for argument!");
- case EVT::i32:
- case EVT::i64:
+ case MVT::i32:
+ case MVT::i64:
if (GPR_idx != NumGPRs) {
RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
} else {
}
ArgOffset += PtrByteSize;
break;
- case EVT::f32:
- case EVT::f64:
+ case MVT::f32:
+ case MVT::f64:
if (FPR_idx != NumFPRs) {
RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
MemOpChains.push_back(Load.getValue(1));
RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
}
- if (GPR_idx != NumGPRs && Arg.getValueType() == EVT::f64 && !isPPC64){
+ if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, NULL, 0);
// GPRs.
if (GPR_idx != NumGPRs)
++GPR_idx;
- if (GPR_idx != NumGPRs && Arg.getValueType() == EVT::f64 &&
+ if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
!isPPC64) // PPC64 has 64-bit GPR's obviously :)
++GPR_idx;
}
if (isPPC64)
ArgOffset += 8;
else
- ArgOffset += Arg.getValueType() == EVT::f32 ? 4 : 8;
+ ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
break;
- case EVT::v4f32:
- case EVT::v4i32:
- case EVT::v8i16:
- case EVT::v16i8:
+ case MVT::v4f32:
+ case MVT::v4i32:
+ case MVT::v8i16:
+ case MVT::v16i8:
if (isVarArg) {
// These go aligned on the stack, or in the corresponding R registers
// when within range. The Darwin PPC ABI doc claims they also go in
SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0);
MemOpChains.push_back(Store);
if (VR_idx != NumVRs) {
- SDValue Load = DAG.getLoad(EVT::v4f32, dl, Store, PtrOff, NULL, 0);
+ SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff, NULL, 0);
MemOpChains.push_back(Load.getValue(1));
RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
}
for (unsigned i = 0; i != NumOps; ++i) {
SDValue Arg = Outs[i].Val;
EVT ArgType = Arg.getValueType();
- if (ArgType==EVT::v4f32 || ArgType==EVT::v4i32 ||
- ArgType==EVT::v8i16 || ArgType==EVT::v16i8) {
+ if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
+ ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
if (++j > NumVRs) {
SDValue PtrOff;
// We are emitting Altivec params in order.
}
if (!MemOpChains.empty())
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&MemOpChains[0], MemOpChains.size());
// Build a sequence of copy-to-reg nodes chained together with token chain
}
if (Flag.getNode())
- return DAG.getNode(PPCISD::RET_FLAG, dl, EVT::Other, Chain, Flag);
+ return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
else
- return DAG.getNode(PPCISD::RET_FLAG, dl, EVT::Other, Chain);
+ return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain);
}
SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
SDValue FPSIdx = getFramePointerFrameIndex(DAG);
// Build a DYNALLOC node.
SDValue Ops[3] = { Chain, NegSize, FPSIdx };
- SDVTList VTs = DAG.getVTList(PtrVT, EVT::Other);
+ SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3);
}
std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
case ISD::SETOGE:
case ISD::SETGE:
- if (LHS.getValueType() == EVT::f32) // Comparison is always 64-bits
- LHS = DAG.getNode(ISD::FP_EXTEND, dl, EVT::f64, LHS);
+ if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
+ LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
case ISD::SETUGT:
case ISD::SETGT:
std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
case ISD::SETOLE:
case ISD::SETLE:
- if (LHS.getValueType() == EVT::f32) // Comparison is always 64-bits
- LHS = DAG.getNode(ISD::FP_EXTEND, dl, EVT::f64, LHS);
+ if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
+ LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
return DAG.getNode(PPCISD::FSEL, dl, ResVT,
- DAG.getNode(ISD::FNEG, dl, EVT::f64, LHS), TV, FV);
+ DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
}
SDValue Cmp;
case ISD::SETULT:
case ISD::SETLT:
Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
- if (Cmp.getValueType() == EVT::f32) // Comparison is always 64-bits
- Cmp = DAG.getNode(ISD::FP_EXTEND, dl, EVT::f64, Cmp);
+ if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
+ Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
case ISD::SETOGE:
case ISD::SETGE:
Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
- if (Cmp.getValueType() == EVT::f32) // Comparison is always 64-bits
- Cmp = DAG.getNode(ISD::FP_EXTEND, dl, EVT::f64, Cmp);
+ if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
+ Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
case ISD::SETUGT:
case ISD::SETGT:
Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
- if (Cmp.getValueType() == EVT::f32) // Comparison is always 64-bits
- Cmp = DAG.getNode(ISD::FP_EXTEND, dl, EVT::f64, Cmp);
+ if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
+ Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
case ISD::SETOLE:
case ISD::SETLE:
Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
- if (Cmp.getValueType() == EVT::f32) // Comparison is always 64-bits
- Cmp = DAG.getNode(ISD::FP_EXTEND, dl, EVT::f64, Cmp);
+ if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
+ Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
}
return Op;
DebugLoc dl) {
assert(Op.getOperand(0).getValueType().isFloatingPoint());
SDValue Src = Op.getOperand(0);
- if (Src.getValueType() == EVT::f32)
- Src = DAG.getNode(ISD::FP_EXTEND, dl, EVT::f64, Src);
+ if (Src.getValueType() == MVT::f32)
+ Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
SDValue Tmp;
- switch (Op.getValueType().getSimpleVT()) {
+ switch (Op.getValueType().getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
- case EVT::i32:
+ case MVT::i32:
Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
PPCISD::FCTIDZ,
- dl, EVT::f64, Src);
+ dl, MVT::f64, Src);
break;
- case EVT::i64:
- Tmp = DAG.getNode(PPCISD::FCTIDZ, dl, EVT::f64, Src);
+ case MVT::i64:
+ Tmp = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Src);
break;
}
// Convert the FP value to an int value through memory.
- SDValue FIPtr = DAG.CreateStackTemporary(EVT::f64);
+ SDValue FIPtr = DAG.CreateStackTemporary(MVT::f64);
// Emit a store to the stack slot.
SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr, NULL, 0);
// Result is a load from the stack slot. If loading 4 bytes, make sure to
// add in a bias.
- if (Op.getValueType() == EVT::i32)
+ if (Op.getValueType() == MVT::i32)
FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
DAG.getConstant(4, FIPtr.getValueType()));
return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, NULL, 0);
SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
DebugLoc dl = Op.getDebugLoc();
// Don't handle ppc_fp128 here; let it be lowered to a libcall.
- if (Op.getValueType() != EVT::f32 && Op.getValueType() != EVT::f64)
+ if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
return SDValue();
- if (Op.getOperand(0).getValueType() == EVT::i64) {
+ if (Op.getOperand(0).getValueType() == MVT::i64) {
SDValue Bits = DAG.getNode(ISD::BIT_CONVERT, dl,
- EVT::f64, Op.getOperand(0));
- SDValue FP = DAG.getNode(PPCISD::FCFID, dl, EVT::f64, Bits);
- if (Op.getValueType() == EVT::f32)
+ MVT::f64, Op.getOperand(0));
+ SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Bits);
+ if (Op.getValueType() == MVT::f32)
FP = DAG.getNode(ISD::FP_ROUND, dl,
- EVT::f32, FP, DAG.getIntPtrConstant(0));
+ MVT::f32, FP, DAG.getIntPtrConstant(0));
return FP;
}
- assert(Op.getOperand(0).getValueType() == EVT::i32 &&
+ assert(Op.getOperand(0).getValueType() == MVT::i32 &&
"Unhandled SINT_TO_FP type in custom expander!");
// Since we only generate this in 64-bit mode, we can take advantage of
// 64-bit registers. In particular, sign extend the input value into the
EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
- SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, dl, EVT::i32,
+ SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, dl, MVT::i32,
Op.getOperand(0));
// STD the extended value into the stack slot.
MachineMemOperand MO(PseudoSourceValue::getFixedStack(FrameIdx),
MachineMemOperand::MOStore, 0, 8, 8);
- SDValue Store = DAG.getNode(PPCISD::STD_32, dl, EVT::Other,
+ SDValue Store = DAG.getNode(PPCISD::STD_32, dl, MVT::Other,
DAG.getEntryNode(), Ext64, FIdx,
DAG.getMemOperand(MO));
// Load the value as a double.
- SDValue Ld = DAG.getLoad(EVT::f64, dl, Store, FIdx, NULL, 0);
+ SDValue Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx, NULL, 0);
// FCFID it and return it.
- SDValue FP = DAG.getNode(PPCISD::FCFID, dl, EVT::f64, Ld);
- if (Op.getValueType() == EVT::f32)
- FP = DAG.getNode(ISD::FP_ROUND, dl, EVT::f32, FP, DAG.getIntPtrConstant(0));
+ SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Ld);
+ if (Op.getValueType() == MVT::f32)
+ FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
return FP;
}
SDValue MFFSreg, InFlag;
// Save FP Control Word to register
- NodeTys.push_back(EVT::f64); // return register
- NodeTys.push_back(EVT::Flag); // unused in this context
+ NodeTys.push_back(MVT::f64); // return register
+ NodeTys.push_back(MVT::Flag); // unused in this context
SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
// Save FP register to stack slot
@@ -3431,22 +3431,22 @@ SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
// Load FP Control Word from low 32 bits of stack slot.
SDValue Four = DAG.getConstant(4, PtrVT);
SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
- SDValue CWD = DAG.getLoad(EVT::i32, dl, Store, Addr, NULL, 0);
+ SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, NULL, 0);
// Transform as necessary
SDValue CWD1 =
- DAG.getNode(ISD::AND, dl, EVT::i32,
- CWD, DAG.getConstant(3, EVT::i32));
+ DAG.getNode(ISD::AND, dl, MVT::i32,
+ CWD, DAG.getConstant(3, MVT::i32));
SDValue CWD2 =
- DAG.getNode(ISD::SRL, dl, EVT::i32,
- DAG.getNode(ISD::AND, dl, EVT::i32,
- DAG.getNode(ISD::XOR, dl, EVT::i32,
- CWD, DAG.getConstant(3, EVT::i32)),
- DAG.getConstant(3, EVT::i32)),
- DAG.getConstant(1, EVT::i32));
+ DAG.getNode(ISD::SRL, dl, MVT::i32,
+ DAG.getNode(ISD::AND, dl, MVT::i32,
+ DAG.getNode(ISD::XOR, dl, MVT::i32,
+ CWD, DAG.getConstant(3, MVT::i32)),
+ DAG.getConstant(3, MVT::i32)),
+ DAG.getConstant(1, MVT::i32));
SDValue RetVal =
- DAG.getNode(ISD::XOR, dl, EVT::i32, CWD1, CWD2);
+ DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
return DAG.getNode((VT.getSizeInBits() < 16 ?
ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
static const EVT VTys[] = { // canonical VT to use for each size.
- EVT::v16i8, EVT::v8i16, EVT::Other, EVT::v4i32
+ MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
};
- EVT ReqVT = VT != EVT::Other ? VT : VTys[SplatSize-1];
+ EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
// Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
if (Val == -1)
EVT CanonicalVT = VTys[SplatSize-1];
// Build a canonical splat for this value.
- SDValue Elt = DAG.getConstant(Val, EVT::i32);
+ SDValue Elt = DAG.getConstant(Val, MVT::i32);
SmallVector<SDValue, 8> Ops;
Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT,
/// specified intrinsic ID.
static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
SelectionDAG &DAG, DebugLoc dl,
- EVT DestVT = EVT::Other) {
- if (DestVT == EVT::Other) DestVT = LHS.getValueType();
+ EVT DestVT = MVT::Other) {
+ if (DestVT == MVT::Other) DestVT = LHS.getValueType();
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
- DAG.getConstant(IID, EVT::i32), LHS, RHS);
+ DAG.getConstant(IID, MVT::i32), LHS, RHS);
}
/// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
/// specified intrinsic ID.
static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
SDValue Op2, SelectionDAG &DAG,
- DebugLoc dl, EVT DestVT = EVT::Other) {
- if (DestVT == EVT::Other) DestVT = Op0.getValueType();
+ DebugLoc dl, EVT DestVT = MVT::Other) {
+ if (DestVT == MVT::Other) DestVT = Op0.getValueType();
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
- DAG.getConstant(IID, EVT::i32), Op0, Op1, Op2);
+ DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
}
static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
EVT VT, SelectionDAG &DAG, DebugLoc dl) {
// Force LHS/RHS to be the right type.
- LHS = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v16i8, LHS);
- RHS = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v16i8, RHS);
+ LHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, LHS);
+ RHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, RHS);
int Ops[16];
for (unsigned i = 0; i != 16; ++i)
Ops[i] = i + Amt;
- SDValue T = DAG.getVectorShuffle(EVT::v16i8, dl, LHS, RHS, Ops);
+ SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, T);
}
// All zeros?
if (SplatBits == 0) {
// Canonicalize all zero vectors to be v4i32.
- if (Op.getValueType() != EVT::v4i32 || HasAnyUndefs) {
- SDValue Z = DAG.getConstant(0, EVT::i32);
- Z = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32, Z, Z, Z, Z);
+ if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
+ SDValue Z = DAG.getConstant(0, MVT::i32);
+ Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
Op = DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Z);
}
return Op;
// If this value is in the range [-32,30] and is even, use:
// tmp = VSPLTI[bhw], result = add tmp, tmp
if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
- SDValue Res = BuildSplatI(SextVal >> 1, SplatSize, EVT::Other, DAG, dl);
+ SDValue Res = BuildSplatI(SextVal >> 1, SplatSize, MVT::Other, DAG, dl);
Res = DAG.getNode(ISD::ADD, dl, Res.getValueType(), Res, Res);
return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
}
@@ -3663,14 +3663,14 @@ SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
// for fneg/fabs.
if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
// Make -1 and vspltisw -1:
- SDValue OnesV = BuildSplatI(-1, 4, EVT::v4i32, DAG, dl);
+ SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
// Make the VSLW intrinsic, computing 0x8000_0000.
SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
OnesV, DAG, dl);
// xor by OnesV to invert it.
- Res = DAG.getNode(ISD::XOR, dl, EVT::v4i32, Res, OnesV);
+ Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
}
// vsplti + shl self.
if (SextVal == (i << (int)TypeShiftAmt)) {
- SDValue Res = BuildSplatI(i, SplatSize, EVT::Other, DAG, dl);
+ SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
static const unsigned IIDs[] = { // Intrinsic to use for each size.
Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
Intrinsic::ppc_altivec_vslw
// vsplti + srl self.
if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
- SDValue Res = BuildSplatI(i, SplatSize, EVT::Other, DAG, dl);
+ SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
static const unsigned IIDs[] = { // Intrinsic to use for each size.
Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
Intrinsic::ppc_altivec_vsrw
// vsplti + sra self.
if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
- SDValue Res = BuildSplatI(i, SplatSize, EVT::Other, DAG, dl);
+ SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
static const unsigned IIDs[] = { // Intrinsic to use for each size.
Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
Intrinsic::ppc_altivec_vsraw
// vsplti + rol self.
if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
- SDValue Res = BuildSplatI(i, SplatSize, EVT::Other, DAG, dl);
+ SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
static const unsigned IIDs[] = { // Intrinsic to use for each size.
Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
Intrinsic::ppc_altivec_vrlw
@@ -3736,17 +3736,17 @@ SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
// t = vsplti c, result = vsldoi t, t, 1
if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) {
- SDValue T = BuildSplatI(i, SplatSize, EVT::v16i8, DAG, dl);
+ SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
}
// t = vsplti c, result = vsldoi t, t, 2
if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) {
- SDValue T = BuildSplatI(i, SplatSize, EVT::v16i8, DAG, dl);
+ SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
}
// t = vsplti c, result = vsldoi t, t, 3
if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) {
- SDValue T = BuildSplatI(i, SplatSize, EVT::v16i8, DAG, dl);
+ SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
}
}
@@ -3755,15 +3755,15 @@ SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
// Odd, in range [17,31]: (vsplti C)-(vsplti -16).
if (SextVal >= 0 && SextVal <= 31) {
- SDValue LHS = BuildSplatI(SextVal-16, SplatSize, EVT::Other, DAG, dl);
- SDValue RHS = BuildSplatI(-16, SplatSize, EVT::Other, DAG, dl);
+ SDValue LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG, dl);
+ SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);
LHS = DAG.getNode(ISD::SUB, dl, LHS.getValueType(), LHS, RHS);
return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), LHS);
}
// Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
if (SextVal >= -31 && SextVal <= 0) {
- SDValue LHS = BuildSplatI(SextVal+16, SplatSize, EVT::Other, DAG, dl);
- SDValue RHS = BuildSplatI(-16, SplatSize, EVT::Other, DAG, dl);
+ SDValue LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG, dl);
+ SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);
LHS = DAG.getNode(ISD::ADD, dl, LHS.getValueType(), LHS, RHS);
return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), LHS);
}
return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
}
EVT VT = OpLHS.getValueType();
- OpLHS = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v16i8, OpLHS);
- OpRHS = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v16i8, OpRHS);
- SDValue T = DAG.getVectorShuffle(EVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
+ OpLHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OpLHS);
+ OpRHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OpRHS);
+ SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, T);
}
for (unsigned j = 0; j != BytesPerElement; ++j)
ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
- EVT::i32));
+ MVT::i32));
}
- SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v16i8,
+ SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
&ResultMask[0], ResultMask.size());
return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask);
}
if (!isDot) {
SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
Op.getOperand(1), Op.getOperand(2),
- DAG.getConstant(CompareOpc, EVT::i32));
+ DAG.getConstant(CompareOpc, MVT::i32));
return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Tmp);
}
SDValue Ops[] = {
Op.getOperand(2), // LHS
Op.getOperand(3), // RHS
- DAG.getConstant(CompareOpc, EVT::i32)
+ DAG.getConstant(CompareOpc, MVT::i32)
};
std::vector<EVT> VTs;
VTs.push_back(Op.getOperand(2).getValueType());
- VTs.push_back(EVT::Flag);
+ VTs.push_back(MVT::Flag);
SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
// Now that we have the comparison, emit a copy from the CR to a GPR.
// This is flagged to the above dot comparison.
- SDValue Flags = DAG.getNode(PPCISD::MFCR, dl, EVT::i32,
- DAG.getRegister(PPC::CR6, EVT::i32),
+ SDValue Flags = DAG.getNode(PPCISD::MFCR, dl, MVT::i32,
+ DAG.getRegister(PPC::CR6, MVT::i32),
CompNode.getValue(1));
// Unpack the result based on how the target uses it.
}
// Shift the bit into the low position.
- Flags = DAG.getNode(ISD::SRL, dl, EVT::i32, Flags,
- DAG.getConstant(8-(3-BitNo), EVT::i32));
+ Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
+ DAG.getConstant(8-(3-BitNo), MVT::i32));
// Isolate the bit.
- Flags = DAG.getNode(ISD::AND, dl, EVT::i32, Flags,
- DAG.getConstant(1, EVT::i32));
+ Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
+ DAG.getConstant(1, MVT::i32));
// If we are supposed to, toggle the bit.
if (InvertBit)
- Flags = DAG.getNode(ISD::XOR, dl, EVT::i32, Flags,
- DAG.getConstant(1, EVT::i32));
+ Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
+ DAG.getConstant(1, MVT::i32));
return Flags;
}
SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) {
DebugLoc dl = Op.getDebugLoc();
- if (Op.getValueType() == EVT::v4i32) {
+ if (Op.getValueType() == MVT::v4i32) {
SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
- SDValue Zero = BuildSplatI( 0, 1, EVT::v4i32, DAG, dl);
- SDValue Neg16 = BuildSplatI(-16, 4, EVT::v4i32, DAG, dl);//+16 as shift amt.
+ SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
+ SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
SDValue RHSSwap = // = vrlw RHS, 16
BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
// Shrinkify inputs to v8i16.
- LHS = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v8i16, LHS);
- RHS = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v8i16, RHS);
- RHSSwap = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v8i16, RHSSwap);
+ LHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, LHS);
+ RHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, RHS);
+ RHSSwap = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, RHSSwap);
// Low parts multiplied together, generating 32-bit results (we ignore the
// top parts).
SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
- LHS, RHS, DAG, dl, EVT::v4i32);
+ LHS, RHS, DAG, dl, MVT::v4i32);
SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
- LHS, RHSSwap, Zero, DAG, dl, EVT::v4i32);
+ LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
// Shift the high parts up 16 bits.
HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
Neg16, DAG, dl);
- return DAG.getNode(ISD::ADD, dl, EVT::v4i32, LoProd, HiProd);
- } else if (Op.getValueType() == EVT::v8i16) {
+ return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
+ } else if (Op.getValueType() == MVT::v8i16) {
SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
- SDValue Zero = BuildSplatI(0, 1, EVT::v8i16, DAG, dl);
+ SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
LHS, RHS, Zero, DAG, dl);
- } else if (Op.getValueType() == EVT::v16i8) {
+ } else if (Op.getValueType() == MVT::v16i8) {
SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
// Multiply the even 8-bit parts, producing 16-bit sums.
SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
- LHS, RHS, DAG, dl, EVT::v8i16);
- EvenParts = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v16i8, EvenParts);
+ LHS, RHS, DAG, dl, MVT::v8i16);
+ EvenParts = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, EvenParts);
// Multiply the odd 8-bit parts, producing 16-bit sums.
SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
- LHS, RHS, DAG, dl, EVT::v8i16);
- OddParts = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v16i8, OddParts);
+ LHS, RHS, DAG, dl, MVT::v8i16);
+ OddParts = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OddParts);
// Merge the results together.
int Ops[16];
Ops[i*2 ] = 2*i+1;
Ops[i*2+1] = 2*i+1+16;
}
- return DAG.getVectorShuffle(EVT::v16i8, dl, EvenParts, OddParts, Ops);
+ return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
} else {
llvm_unreachable("Unknown mul to lower!");
}
assert(false && "Do not know how to custom type legalize this operation!");
return;
case ISD::FP_ROUND_INREG: {
- assert(N->getValueType(0) == EVT::ppcf128);
- assert(N->getOperand(0).getValueType() == EVT::ppcf128);
+ assert(N->getValueType(0) == MVT::ppcf128);
+ assert(N->getOperand(0).getValueType() == MVT::ppcf128);
SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
- EVT::f64, N->getOperand(0),
+ MVT::f64, N->getOperand(0),
DAG.getIntPtrConstant(0));
SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
- EVT::f64, N->getOperand(0),
+ MVT::f64, N->getOperand(0),
DAG.getIntPtrConstant(1));
// This sequence changes FPSCR to do round-to-zero, adds the two halves
std::vector<EVT> NodeTys;
SDValue Ops[4], Result, MFFSreg, InFlag, FPreg;
- NodeTys.push_back(EVT::f64); // Return register
- NodeTys.push_back(EVT::Flag); // Returns a flag for later insns
+ NodeTys.push_back(MVT::f64); // Return register
+ NodeTys.push_back(MVT::Flag); // Returns a flag for later insns
Result = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
MFFSreg = Result.getValue(0);
InFlag = Result.getValue(1);
NodeTys.clear();
- NodeTys.push_back(EVT::Flag); // Returns a flag
- Ops[0] = DAG.getConstant(31, EVT::i32);
+ NodeTys.push_back(MVT::Flag); // Returns a flag
+ Ops[0] = DAG.getConstant(31, MVT::i32);
Ops[1] = InFlag;
Result = DAG.getNode(PPCISD::MTFSB1, dl, NodeTys, Ops, 2);
InFlag = Result.getValue(0);
NodeTys.clear();
- NodeTys.push_back(EVT::Flag); // Returns a flag
- Ops[0] = DAG.getConstant(30, EVT::i32);
+ NodeTys.push_back(MVT::Flag); // Returns a flag
+ Ops[0] = DAG.getConstant(30, MVT::i32);
Ops[1] = InFlag;
Result = DAG.getNode(PPCISD::MTFSB0, dl, NodeTys, Ops, 2);
InFlag = Result.getValue(0);
NodeTys.clear();
- NodeTys.push_back(EVT::f64); // result of add
- NodeTys.push_back(EVT::Flag); // Returns a flag
+ NodeTys.push_back(MVT::f64); // result of add
+ NodeTys.push_back(MVT::Flag); // Returns a flag
Ops[0] = Lo;
Ops[1] = Hi;
Ops[2] = InFlag;
InFlag = Result.getValue(1);
NodeTys.clear();
- NodeTys.push_back(EVT::f64);
- Ops[0] = DAG.getConstant(1, EVT::i32);
+ NodeTys.push_back(MVT::f64);
+ Ops[0] = DAG.getConstant(1, MVT::i32);
Ops[1] = MFFSreg;
Ops[2] = FPreg;
Ops[3] = InFlag;
// We know the low half is about to be thrown away, so just use something
// convenient.
- Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, EVT::ppcf128,
+ Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
FPreg, FPreg));
return;
}
// Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
// We allow the src/dst to be either f32/f64, but the intermediate
// type must be i64.
- if (N->getOperand(0).getValueType() == EVT::i64 &&
- N->getOperand(0).getOperand(0).getValueType() != EVT::ppcf128) {
+ if (N->getOperand(0).getValueType() == MVT::i64 &&
+ N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
SDValue Val = N->getOperand(0).getOperand(0);
- if (Val.getValueType() == EVT::f32) {
- Val = DAG.getNode(ISD::FP_EXTEND, dl, EVT::f64, Val);
+ if (Val.getValueType() == MVT::f32) {
+ Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
DCI.AddToWorklist(Val.getNode());
}
- Val = DAG.getNode(PPCISD::FCTIDZ, dl, EVT::f64, Val);
+ Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
DCI.AddToWorklist(Val.getNode());
- Val = DAG.getNode(PPCISD::FCFID, dl, EVT::f64, Val);
+ Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
DCI.AddToWorklist(Val.getNode());
- if (N->getValueType(0) == EVT::f32) {
- Val = DAG.getNode(ISD::FP_ROUND, dl, EVT::f32, Val,
+ if (N->getValueType(0) == MVT::f32) {
+ Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
DAG.getIntPtrConstant(0));
DCI.AddToWorklist(Val.getNode());
}
return Val;
- } else if (N->getOperand(0).getValueType() == EVT::i32) {
+ } else if (N->getOperand(0).getValueType() == MVT::i32) {
// If the intermediate type is i32, we can avoid the load/store here
// too.
}
if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
!cast<StoreSDNode>(N)->isTruncatingStore() &&
N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
- N->getOperand(1).getValueType() == EVT::i32 &&
- N->getOperand(1).getOperand(0).getValueType() != EVT::ppcf128) {
+ N->getOperand(1).getValueType() == MVT::i32 &&
+ N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
SDValue Val = N->getOperand(1).getOperand(0);
- if (Val.getValueType() == EVT::f32) {
- Val = DAG.getNode(ISD::FP_EXTEND, dl, EVT::f64, Val);
+ if (Val.getValueType() == MVT::f32) {
+ Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
DCI.AddToWorklist(Val.getNode());
}
- Val = DAG.getNode(PPCISD::FCTIWZ, dl, EVT::f64, Val);
+ Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
DCI.AddToWorklist(Val.getNode());
- Val = DAG.getNode(PPCISD::STFIWX, dl, EVT::Other, N->getOperand(0), Val,
+ Val = DAG.getNode(PPCISD::STFIWX, dl, MVT::Other, N->getOperand(0), Val,
N->getOperand(2), N->getOperand(3));
DCI.AddToWorklist(Val.getNode());
return Val;
// Turn STORE (BSWAP) -> sthbrx/stwbrx.
if (N->getOperand(1).getOpcode() == ISD::BSWAP &&
N->getOperand(1).getNode()->hasOneUse() &&
- (N->getOperand(1).getValueType() == EVT::i32 ||
- N->getOperand(1).getValueType() == EVT::i16)) {
+ (N->getOperand(1).getValueType() == MVT::i32 ||
+ N->getOperand(1).getValueType() == MVT::i16)) {
SDValue BSwapOp = N->getOperand(1).getOperand(0);
// Do an any-extend to 32-bits if this is a half-word input.
- if (BSwapOp.getValueType() == EVT::i16)
- BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, EVT::i32, BSwapOp);
+ if (BSwapOp.getValueType() == MVT::i16)
+ BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
- return DAG.getNode(PPCISD::STBRX, dl, EVT::Other, N->getOperand(0),
+ return DAG.getNode(PPCISD::STBRX, dl, MVT::Other, N->getOperand(0),
BSwapOp, N->getOperand(2), N->getOperand(3),
DAG.getValueType(N->getOperand(1).getValueType()));
}
// Turn BSWAP (LOAD) -> lhbrx/lwbrx.
if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
N->getOperand(0).hasOneUse() &&
- (N->getValueType(0) == EVT::i32 || N->getValueType(0) == EVT::i16)) {
+ (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) {
SDValue Load = N->getOperand(0);
LoadSDNode *LD = cast<LoadSDNode>(Load);
// Create the byte-swapping load.
std::vector<EVT> VTs;
- VTs.push_back(EVT::i32);
- VTs.push_back(EVT::Other);
+ VTs.push_back(MVT::i32);
+ VTs.push_back(MVT::Other);
SDValue MO = DAG.getMemOperand(LD->getMemOperand());
SDValue Ops[] = {
LD->getChain(), // Chain
// If this is an i16 load, insert the truncate.
SDValue ResVal = BSLoad;
- if (N->getValueType(0) == EVT::i16)
- ResVal = DAG.getNode(ISD::TRUNCATE, dl, EVT::i16, BSLoad);
+ if (N->getValueType(0) == MVT::i16)
+ ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
// First, combine the bswap away. This makes the value produced by the
// load dead.
if (CC == ISD::SETEQ) // Cond never true, remove branch.
return N->getOperand(0);
// Always !=, turn it into an unconditional branch.
- return DAG.getNode(ISD::BR, dl, EVT::Other,
+ return DAG.getNode(ISD::BR, dl, MVT::Other,
N->getOperand(0), N->getOperand(4));
}
SDValue Ops[] = {
LHS.getOperand(2), // LHS of compare
LHS.getOperand(3), // RHS of compare
- DAG.getConstant(CompareOpc, EVT::i32)
+ DAG.getConstant(CompareOpc, MVT::i32)
};
VTs.push_back(LHS.getOperand(2).getValueType());
- VTs.push_back(EVT::Flag);
+ VTs.push_back(MVT::Flag);
SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
// Unpack the result based on how the target uses it.
break;
}
- return DAG.getNode(PPCISD::COND_BRANCH, dl, EVT::Other, N->getOperand(0),
- DAG.getConstant(CompOpc, EVT::i32),
- DAG.getRegister(PPC::CR6, EVT::i32),
+ return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
+ DAG.getConstant(CompOpc, MVT::i32),
+ DAG.getRegister(PPC::CR6, MVT::i32),
N->getOperand(4), CompNode.getValue(1));
}
break;
default: break;
case PPCISD::LBRX: {
// lhbrx is known to have the top bits cleared out.
- if (cast<VTSDNode>(Op.getOperand(3))->getVT() == EVT::i16)
+ if (cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::i16)
KnownZero = 0xFFFF0000;
break;
}
@@ -5141,13 +5141,13 @@ PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
switch (Constraint[0]) {
case 'b': // R1-R31
case 'r': // R0-R31
- if (VT == EVT::i64 && PPCSubTarget.isPPC64())
+ if (VT == MVT::i64 && PPCSubTarget.isPPC64())
return std::make_pair(0U, PPC::G8RCRegisterClass);
return std::make_pair(0U, PPC::GPRCRegisterClass);
case 'f':
- if (VT == EVT::f32)
+ if (VT == MVT::f32)
return std::make_pair(0U, PPC::F4RCRegisterClass);
- else if (VT == EVT::f64)
+ else if (VT == MVT::f64)
return std::make_pair(0U, PPC::F8RCRegisterClass);
break;
case 'v':
return SDValue();
EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
- bool isPPC64 = PtrVT == EVT::i64;
+ bool isPPC64 = PtrVT == MVT::i64;
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo *MFI = MF.getFrameInfo();
if (isPPC64)
return DAG.getCopyFromReg(DAG.getEntryNode(), dl, is31 ? PPC::X31 : PPC::X1,
- EVT::i64);
+ MVT::i64);
else
return DAG.getCopyFromReg(DAG.getEntryNode(), dl, is31 ? PPC::R31 : PPC::R1,
- EVT::i32);
+ MVT::i32);
}
bool
bool isSrcConst, bool isSrcStr,
SelectionDAG &DAG) const {
if (this->PPCSubTarget.isPPC64()) {
- return EVT::i64;
+ return MVT::i64;
} else {
- return EVT::i32;
+ return MVT::i32;
}
}
index 9d8687bade90e36396112e475bb50a4c9b488a84..7830e0f08d8fea3211de417b948231353f9918a8 100644 (file)
virtual const char *getTargetNodeName(unsigned Opcode) const;
/// getSetCCResultType - Return the ISD::SETCC ValueType
- virtual EVT::SimpleValueType getSetCCResultType(EVT VT) const;
+ virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const;
/// getPreIndexedAddressParts - returns true by value, base pointer and
/// offset pointer and addressing mode by reference if the node's address
index e0e84667c0862838a96ac341536aa6b4d80f559d..759cdf0a4863e6d137f02c6393b1adfe04be5fa6 100644 (file)
def maskimm32 : PatLeaf<(imm), [{
// maskImm predicate - True if immediate is a run of ones.
unsigned mb, me;
- if (N->getValueType(0) == EVT::i32)
+ if (N->getValueType(0) == MVT::i32)
return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
else
return false;
def immSExt16 : PatLeaf<(imm), [{
// immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
// field. Used by instructions like 'addi'.
- if (N->getValueType(0) == EVT::i32)
+ if (N->getValueType(0) == MVT::i32)
return (int32_t)N->getZExtValue() == (short)N->getZExtValue();
else
return (int64_t)N->getZExtValue() == (short)N->getZExtValue();
// immediate are set. Used by instructions like 'addis'. Identical to
// imm16ShiftedZExt in 32-bit mode.
if (N->getZExtValue() & 0xFFFF) return false;
- if (N->getValueType(0) == EVT::i32)
+ if (N->getValueType(0) == MVT::i32)
return true;
// For 64-bit, make sure it is sext right.
return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
index 3aefa303aa28f537dc3fe77c45c6afb7823a7fa8..e1b9b59b4095fcb8887e55077382a4e5b05241fb 100644 (file)
bool SparcDAGToDAGISel::SelectADDRri(SDValue Op, SDValue Addr,
SDValue &Base, SDValue &Offset) {
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
- Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), EVT::i32);
- Offset = CurDAG->getTargetConstant(0, EVT::i32);
+ Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
+ Offset = CurDAG->getTargetConstant(0, MVT::i32);
return true;
}
if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
if (FrameIndexSDNode *FIN =
dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
// Constant offset from frame ref.
- Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), EVT::i32);
+ Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
} else {
Base = Addr.getOperand(0);
}
- Offset = CurDAG->getTargetConstant(CN->getZExtValue(), EVT::i32);
+ Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
return true;
}
}
}
}
Base = Addr;
- Offset = CurDAG->getTargetConstant(0, EVT::i32);
+ Offset = CurDAG->getTargetConstant(0, MVT::i32);
return true;
}
}
R1 = Addr;
- R2 = CurDAG->getRegister(SP::G0, EVT::i32);
+ R2 = CurDAG->getRegister(SP::G0, MVT::i32);
return true;
}
// Set the Y register to the high-part.
SDValue TopPart;
if (N->getOpcode() == ISD::SDIV) {
- TopPart = SDValue(CurDAG->getTargetNode(SP::SRAri, dl, EVT::i32, DivLHS,
- CurDAG->getTargetConstant(31, EVT::i32)), 0);
+ TopPart = SDValue(CurDAG->getTargetNode(SP::SRAri, dl, MVT::i32, DivLHS,
+ CurDAG->getTargetConstant(31, MVT::i32)), 0);
} else {
- TopPart = CurDAG->getRegister(SP::G0, EVT::i32);
+ TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
}
- TopPart = SDValue(CurDAG->getTargetNode(SP::WRYrr, dl, EVT::Flag, TopPart,
- CurDAG->getRegister(SP::G0, EVT::i32)), 0);
+ TopPart = SDValue(CurDAG->getTargetNode(SP::WRYrr, dl, MVT::Flag, TopPart,
+ CurDAG->getRegister(SP::G0, MVT::i32)), 0);
// FIXME: Handle div by immediate.
unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
- return CurDAG->SelectNodeTo(N, Opcode, EVT::i32, DivLHS, DivRHS,
+ return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS,
TopPart);
}
case ISD::MULHU:
SDValue MulLHS = N->getOperand(0);
SDValue MulRHS = N->getOperand(1);
unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
- SDNode *Mul = CurDAG->getTargetNode(Opcode, dl, EVT::i32, EVT::Flag,
+ SDNode *Mul = CurDAG->getTargetNode(Opcode, dl, MVT::i32, MVT::Flag,
MulLHS, MulRHS);
// The high part is in the Y register.
- return CurDAG->SelectNodeTo(N, SP::RDY, EVT::i32, SDValue(Mul, 1));
+ return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDValue(Mul, 1));
return NULL;
}
}
index 959d41ab8b858cdc9b7096289523c6a5a8487a01..ebb9806bfaa1ab9407d6e9e08379849132868399 100644 (file)
}
if (Flag.getNode())
- return DAG.getNode(SPISD::RET_FLAG, dl, EVT::Other, Chain, Flag);
- return DAG.getNode(SPISD::RET_FLAG, dl, EVT::Other, Chain);
+ return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
+ return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain);
}
/// LowerFormalArguments - V8 uses a very simple ABI, where all values are
// FIXME: We ignore the register assignments of AnalyzeFormalArguments
// because it doesn't know how to split a double into two i32 registers.
EVT ObjectVT = VA.getValVT();
- switch (ObjectVT.getSimpleVT()) {
+ switch (ObjectVT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unhandled argument type!");
- case EVT::i1:
- case EVT::i8:
- case EVT::i16:
- case EVT::i32:
+ case MVT::i1:
+ case MVT::i8:
+ case MVT::i16:
+ case MVT::i32:
if (!Ins[i].Used) { // Argument is dead.
if (CurArgReg < ArgRegEnd) ++CurArgReg;
InVals.push_back(DAG.getUNDEF(ObjectVT));
} else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
MF.getRegInfo().addLiveIn(*CurArgReg++, VReg);
- SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, EVT::i32);
- if (ObjectVT != EVT::i32) {
+ SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
+ if (ObjectVT != MVT::i32) {
unsigned AssertOp = ISD::AssertSext;
- Arg = DAG.getNode(AssertOp, dl, EVT::i32, Arg,
+ Arg = DAG.getNode(AssertOp, dl, MVT::i32, Arg,
DAG.getValueType(ObjectVT));
Arg = DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, Arg);
}
InVals.push_back(Arg);
} else {
int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
- SDValue FIPtr = DAG.getFrameIndex(FrameIdx, EVT::i32);
+ SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
SDValue Load;
- if (ObjectVT == EVT::i32) {
- Load = DAG.getLoad(EVT::i32, dl, Chain, FIPtr, NULL, 0);
+ if (ObjectVT == MVT::i32) {
+ Load = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, NULL, 0);
} else {
ISD::LoadExtType LoadOp = ISD::SEXTLOAD;
// Sparc is big endian, so add an offset based on the ObjectVT.
unsigned Offset = 4-std::max(1U, ObjectVT.getSizeInBits()/8);
- FIPtr = DAG.getNode(ISD::ADD, dl, EVT::i32, FIPtr,
- DAG.getConstant(Offset, EVT::i32));
- Load = DAG.getExtLoad(LoadOp, dl, EVT::i32, Chain, FIPtr,
+ FIPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIPtr,
+ DAG.getConstant(Offset, MVT::i32));
+ Load = DAG.getExtLoad(LoadOp, dl, MVT::i32, Chain, FIPtr,
NULL, 0, ObjectVT);
Load = DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, Load);
}
ArgOffset += 4;
break;
- case EVT::f32:
+ case MVT::f32:
if (!Ins[i].Used) { // Argument is dead.
if (CurArgReg < ArgRegEnd) ++CurArgReg;
InVals.push_back(DAG.getUNDEF(ObjectVT));
// FP value is passed in an integer register.
unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
MF.getRegInfo().addLiveIn(*CurArgReg++, VReg);
- SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, EVT::i32);
+ SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
- Arg = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, Arg);
+ Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Arg);
InVals.push_back(Arg);
} else {
int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
- SDValue FIPtr = DAG.getFrameIndex(FrameIdx, EVT::i32);
- SDValue Load = DAG.getLoad(EVT::f32, dl, Chain, FIPtr, NULL, 0);
+ SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
+ SDValue Load = DAG.getLoad(MVT::f32, dl, Chain, FIPtr, NULL, 0);
InVals.push_back(Load);
}
ArgOffset += 4;
break;
- case EVT::i64:
- case EVT::f64:
+ case MVT::i64:
+ case MVT::f64:
if (!Ins[i].Used) { // Argument is dead.
if (CurArgReg < ArgRegEnd) ++CurArgReg;
if (CurArgReg < ArgRegEnd) ++CurArgReg;
if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
MF.getRegInfo().addLiveIn(*CurArgReg++, VRegHi);
- HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, EVT::i32);
+ HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, MVT::i32);
} else {
int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
- SDValue FIPtr = DAG.getFrameIndex(FrameIdx, EVT::i32);
- HiVal = DAG.getLoad(EVT::i32, dl, Chain, FIPtr, NULL, 0);
+ SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
+ HiVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, NULL, 0);
}
SDValue LoVal;
if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
unsigned VRegLo = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
MF.getRegInfo().addLiveIn(*CurArgReg++, VRegLo);
- LoVal = DAG.getCopyFromReg(Chain, dl, VRegLo, EVT::i32);
+ LoVal = DAG.getCopyFromReg(Chain, dl, VRegLo, MVT::i32);
} else {
int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4);
- SDValue FIPtr = DAG.getFrameIndex(FrameIdx, EVT::i32);
- LoVal = DAG.getLoad(EVT::i32, dl, Chain, FIPtr, NULL, 0);
+ SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
+ LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, NULL, 0);
}
// Compose the two halves together into an i64 unit.
SDValue WholeValue =
- DAG.getNode(ISD::BUILD_PAIR, dl, EVT::i64, LoVal, HiVal);
+ DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
// If we want a double, do a bit convert.
- if (ObjectVT == EVT::f64)
- WholeValue = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f64, WholeValue);
+ if (ObjectVT == MVT::f64)
+ WholeValue = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, WholeValue);
InVals.push_back(WholeValue);
}
for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
- SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, EVT::i32);
+ SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32);
int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
- SDValue FIPtr = DAG.getFrameIndex(FrameIdx, EVT::i32);
+ SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
OutChains.push_back(DAG.getStore(DAG.getRoot(), dl, Arg, FIPtr, NULL, 0));
ArgOffset += 4;
if (!OutChains.empty()) {
OutChains.push_back(Chain);
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&OutChains[0], OutChains.size());
}
}
// Count the size of the outgoing arguments.
unsigned ArgsSize = 0;
for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
- switch (Outs[i].Val.getValueType().getSimpleVT()) {
+ switch (Outs[i].Val.getValueType().getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unknown value type!");
- case EVT::i1:
- case EVT::i8:
- case EVT::i16:
- case EVT::i32:
- case EVT::f32:
+ case MVT::i1:
+ case MVT::i8:
+ case MVT::i16:
+ case MVT::i32:
+ case MVT::f32:
ArgsSize += 4;
break;
- case EVT::i64:
- case EVT::f64:
+ case MVT::i64:
+ case MVT::f64:
ArgsSize += 8;
break;
}
assert(VA.isMemLoc());
// Create a store off the stack pointer for this argument.
- SDValue StackPtr = DAG.getRegister(SP::O6, EVT::i32);
+ SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
// FIXME: VERIFY THAT 68 IS RIGHT.
SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+68);
- PtrOff = DAG.getNode(ISD::ADD, EVT::i32, StackPtr, PtrOff);
+ PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
}
EVT ObjectVT = Val.getValueType();
SDValue ValToStore(0, 0);
unsigned ObjSize;
- switch (ObjectVT.getSimpleVT()) {
+ switch (ObjectVT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unhandled argument type!");
- case EVT::i32:
+ case MVT::i32:
ObjSize = 4;
if (RegsToPass.size() >= 6) {
RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Val));
}
break;
- case EVT::f32:
+ case MVT::f32:
ObjSize = 4;
if (RegsToPass.size() >= 6) {
ValToStore = Val;
} else {
// Convert this to a FP value in an int reg.
- Val = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, Val);
+ Val = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Val);
RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Val));
}
break;
- case EVT::f64: {
+ case MVT::f64: {
ObjSize = 8;
if (RegsToPass.size() >= 6) {
ValToStore = Val; // Whole thing is passed in memory.
// Break into top and bottom parts by storing to the stack and loading
// out the parts as integers. Top part goes in a reg.
- SDValue StackPtr = DAG.CreateStackTemporary(EVT::f64, EVT::i32);
+ SDValue StackPtr = DAG.CreateStackTemporary(MVT::f64, MVT::i32);
SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
Val, StackPtr, NULL, 0);
// Sparc is big-endian, so the high part comes first.
- SDValue Hi = DAG.getLoad(EVT::i32, dl, Store, StackPtr, NULL, 0, 0);
+ SDValue Hi = DAG.getLoad(MVT::i32, dl, Store, StackPtr, NULL, 0, 0);
// Increment the pointer to the other half.
StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
DAG.getIntPtrConstant(4));
// Load the low part.
- SDValue Lo = DAG.getLoad(EVT::i32, dl, Store, StackPtr, NULL, 0, 0);
+ SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr, NULL, 0, 0);
RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Hi));
}
break;
}
- case EVT::i64: {
+ case MVT::i64: {
ObjSize = 8;
if (RegsToPass.size() >= 6) {
ValToStore = Val; // Whole thing is passed in memory.
}
// Split the value into top and bottom part. Top part goes in a reg.
- SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32, Val,
- DAG.getConstant(1, EVT::i32));
- SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32, Val,
- DAG.getConstant(0, EVT::i32));
+ SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Val,
+ DAG.getConstant(1, MVT::i32));
+ SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Val,
+ DAG.getConstant(0, MVT::i32));
RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Hi));
if (RegsToPass.size() >= 6) {
}
if (ValToStore.getNode()) {
- SDValue StackPtr = DAG.getRegister(SP::O6, EVT::i32);
- SDValue PtrOff = DAG.getConstant(ArgOffset, EVT::i32);
- PtrOff = DAG.getNode(ISD::ADD, dl, EVT::i32, StackPtr, PtrOff);
+ SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
+ SDValue PtrOff = DAG.getConstant(ArgOffset, MVT::i32);
+ PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
MemOpChains.push_back(DAG.getStore(Chain, dl, ValToStore,
PtrOff, NULL, 0));
}
// Emit all stores, make sure the occur before any copies into physregs.
if (!MemOpChains.empty())
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&MemOpChains[0], MemOpChains.size());
// Build a sequence of copy-to-reg nodes chained together with token
// turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
// Likewise ExternalSymbol -> TargetExternalSymbol.
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
- Callee = DAG.getTargetGlobalAddress(G->getGlobal(), EVT::i32);
+ Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
- Callee = DAG.getTargetExternalSymbol(E->getSymbol(), EVT::i32);
+ Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
std::vector<EVT> NodeTys;
- NodeTys.push_back(EVT::Other); // Returns a chain
- NodeTys.push_back(EVT::Flag); // Returns a flag for retval copy to use.
+ NodeTys.push_back(MVT::Other); // Returns a chain
+ NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
SDValue Ops[] = { Chain, Callee, InFlag };
Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, Ops, InFlag.getNode() ? 3 : 2);
InFlag = Chain.getValue(1);
: TargetLowering(TM, new TargetLoweringObjectFileELF()) {
// Set up the register classes.
- addRegisterClass(EVT::i32, SP::IntRegsRegisterClass);
- addRegisterClass(EVT::f32, SP::FPRegsRegisterClass);
- addRegisterClass(EVT::f64, SP::DFPRegsRegisterClass);
+ addRegisterClass(MVT::i32, SP::IntRegsRegisterClass);
+ addRegisterClass(MVT::f32, SP::FPRegsRegisterClass);
+ addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass);
// Turn FP extload into load/fextend
- setLoadExtAction(ISD::EXTLOAD, EVT::f32, Expand);
+ setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
// Sparc doesn't have i1 sign extending load
- setLoadExtAction(ISD::SEXTLOAD, EVT::i1, Promote);
+ setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
// Turn FP truncstore into trunc + store.
- setTruncStoreAction(EVT::f64, EVT::f32, Expand);
+ setTruncStoreAction(MVT::f64, MVT::f32, Expand);
// Custom legalize GlobalAddress nodes into LO/HI parts.
- setOperationAction(ISD::GlobalAddress, EVT::i32, Custom);
- setOperationAction(ISD::GlobalTLSAddress, EVT::i32, Custom);
- setOperationAction(ISD::ConstantPool , EVT::i32, Custom);
+ setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
+ setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
+ setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
// Sparc doesn't have sext_inreg, replace them with shl/sra
- setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i16, Expand);
- setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i8 , Expand);
- setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i1 , Expand);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
// Sparc has no REM or DIVREM operations.
- setOperationAction(ISD::UREM, EVT::i32, Expand);
- setOperationAction(ISD::SREM, EVT::i32, Expand);
- setOperationAction(ISD::SDIVREM, EVT::i32, Expand);
- setOperationAction(ISD::UDIVREM, EVT::i32, Expand);
+ setOperationAction(ISD::UREM, MVT::i32, Expand);
+ setOperationAction(ISD::SREM, MVT::i32, Expand);
+ setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
+ setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
// Custom expand fp<->sint
- setOperationAction(ISD::FP_TO_SINT, EVT::i32, Custom);
- setOperationAction(ISD::SINT_TO_FP, EVT::i32, Custom);
+ setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
+ setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
// Expand fp<->uint
- setOperationAction(ISD::FP_TO_UINT, EVT::i32, Expand);
- setOperationAction(ISD::UINT_TO_FP, EVT::i32, Expand);
+ setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
+ setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
- setOperationAction(ISD::BIT_CONVERT, EVT::f32, Expand);
- setOperationAction(ISD::BIT_CONVERT, EVT::i32, Expand);
+ setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
+ setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
// Sparc has no select or setcc: expand to SELECT_CC.
- setOperationAction(ISD::SELECT, EVT::i32, Expand);
- setOperationAction(ISD::SELECT, EVT::f32, Expand);
- setOperationAction(ISD::SELECT, EVT::f64, Expand);
- setOperationAction(ISD::SETCC, EVT::i32, Expand);
- setOperationAction(ISD::SETCC, EVT::f32, Expand);
- setOperationAction(ISD::SETCC, EVT::f64, Expand);
+ setOperationAction(ISD::SELECT, MVT::i32, Expand);
+ setOperationAction(ISD::SELECT, MVT::f32, Expand);
+ setOperationAction(ISD::SELECT, MVT::f64, Expand);
+ setOperationAction(ISD::SETCC, MVT::i32, Expand);
+ setOperationAction(ISD::SETCC, MVT::f32, Expand);
+ setOperationAction(ISD::SETCC, MVT::f64, Expand);
// Sparc doesn't have BRCOND either, it has BR_CC.
- setOperationAction(ISD::BRCOND, EVT::Other, Expand);
- setOperationAction(ISD::BRIND, EVT::Other, Expand);
- setOperationAction(ISD::BR_JT, EVT::Other, Expand);
- setOperationAction(ISD::BR_CC, EVT::i32, Custom);
- setOperationAction(ISD::BR_CC, EVT::f32, Custom);
- setOperationAction(ISD::BR_CC, EVT::f64, Custom);
+ setOperationAction(ISD::BRCOND, MVT::Other, Expand);
+ setOperationAction(ISD::BRIND, MVT::Other, Expand);
+ setOperationAction(ISD::BR_JT, MVT::Other, Expand);
+ setOperationAction(ISD::BR_CC, MVT::i32, Custom);
+ setOperationAction(ISD::BR_CC, MVT::f32, Custom);
+ setOperationAction(ISD::BR_CC, MVT::f64, Custom);
- setOperationAction(ISD::SELECT_CC, EVT::i32, Custom);
- setOperationAction(ISD::SELECT_CC, EVT::f32, Custom);
- setOperationAction(ISD::SELECT_CC, EVT::f64, Custom);
+ setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
+ setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
+ setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
// SPARC has no intrinsics for these particular operations.
- setOperationAction(ISD::MEMBARRIER, EVT::Other, Expand);
-
- setOperationAction(ISD::FSIN , EVT::f64, Expand);
- setOperationAction(ISD::FCOS , EVT::f64, Expand);
- setOperationAction(ISD::FREM , EVT::f64, Expand);
- setOperationAction(ISD::FSIN , EVT::f32, Expand);
- setOperationAction(ISD::FCOS , EVT::f32, Expand);
- setOperationAction(ISD::FREM , EVT::f32, Expand);
- setOperationAction(ISD::CTPOP, EVT::i32, Expand);
- setOperationAction(ISD::CTTZ , EVT::i32, Expand);
- setOperationAction(ISD::CTLZ , EVT::i32, Expand);
- setOperationAction(ISD::ROTL , EVT::i32, Expand);
- setOperationAction(ISD::ROTR , EVT::i32, Expand);
- setOperationAction(ISD::BSWAP, EVT::i32, Expand);
- setOperationAction(ISD::FCOPYSIGN, EVT::f64, Expand);
- setOperationAction(ISD::FCOPYSIGN, EVT::f32, Expand);
- setOperationAction(ISD::FPOW , EVT::f64, Expand);
- setOperationAction(ISD::FPOW , EVT::f32, Expand);
-
- setOperationAction(ISD::SHL_PARTS, EVT::i32, Expand);
- setOperationAction(ISD::SRA_PARTS, EVT::i32, Expand);
- setOperationAction(ISD::SRL_PARTS, EVT::i32, Expand);
+ setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
+
+ setOperationAction(ISD::FSIN , MVT::f64, Expand);
+ setOperationAction(ISD::FCOS , MVT::f64, Expand);
+ setOperationAction(ISD::FREM , MVT::f64, Expand);
+ setOperationAction(ISD::FSIN , MVT::f32, Expand);
+ setOperationAction(ISD::FCOS , MVT::f32, Expand);
+ setOperationAction(ISD::FREM , MVT::f32, Expand);
+ setOperationAction(ISD::CTPOP, MVT::i32, Expand);
+ setOperationAction(ISD::CTTZ , MVT::i32, Expand);
+ setOperationAction(ISD::CTLZ , MVT::i32, Expand);
+ setOperationAction(ISD::ROTL , MVT::i32, Expand);
+ setOperationAction(ISD::ROTR , MVT::i32, Expand);
+ setOperationAction(ISD::BSWAP, MVT::i32, Expand);
+ setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
+ setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
+ setOperationAction(ISD::FPOW , MVT::f64, Expand);
+ setOperationAction(ISD::FPOW , MVT::f32, Expand);
+
+ setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
+ setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
+ setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
// FIXME: Sparc provides these multiplies, but we don't have them yet.
- setOperationAction(ISD::UMUL_LOHI, EVT::i32, Expand);
- setOperationAction(ISD::SMUL_LOHI, EVT::i32, Expand);
+ setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
+ setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
// We don't have line number support yet.
- setOperationAction(ISD::DBG_STOPPOINT, EVT::Other, Expand);
- setOperationAction(ISD::DEBUG_LOC, EVT::Other, Expand);
- setOperationAction(ISD::DBG_LABEL, EVT::Other, Expand);
- setOperationAction(ISD::EH_LABEL, EVT::Other, Expand);
+ setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
+ setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
+ setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
+ setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
// VASTART needs to be custom lowered to use the VarArgsFrameIndex.
- setOperationAction(ISD::VASTART , EVT::Other, Custom);
+ setOperationAction(ISD::VASTART , MVT::Other, Custom);
// VAARG needs to be lowered to not do unaligned accesses for doubles.
- setOperationAction(ISD::VAARG , EVT::Other, Custom);
+ setOperationAction(ISD::VAARG , MVT::Other, Custom);
// Use the default implementation.
- setOperationAction(ISD::VACOPY , EVT::Other, Expand);
- setOperationAction(ISD::VAEND , EVT::Other, Expand);
- setOperationAction(ISD::STACKSAVE , EVT::Other, Expand);
- setOperationAction(ISD::STACKRESTORE , EVT::Other, Expand);
- setOperationAction(ISD::DYNAMIC_STACKALLOC, EVT::i32 , Custom);
+ setOperationAction(ISD::VACOPY , MVT::Other, Expand);
+ setOperationAction(ISD::VAEND , MVT::Other, Expand);
+ setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
+ setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
+ setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
// No debug info support yet.
- setOperationAction(ISD::DBG_STOPPOINT, EVT::Other, Expand);
- setOperationAction(ISD::DBG_LABEL, EVT::Other, Expand);
- setOperationAction(ISD::EH_LABEL, EVT::Other, Expand);
- setOperationAction(ISD::DECLARE, EVT::Other, Expand);
+ setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
+ setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
+ setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
+ setOperationAction(ISD::DECLARE, MVT::Other, Expand);
setStackPointerRegisterToSaveRestore(SP::O6);
if (TM.getSubtarget<SparcSubtarget>().isV9())
- setOperationAction(ISD::CTPOP, EVT::i32, Legal);
+ setOperationAction(ISD::CTPOP, MVT::i32, Legal);
computeRegisterProperties();
}
GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
// FIXME there isn't really any debug info here
DebugLoc dl = Op.getDebugLoc();
- SDValue GA = DAG.getTargetGlobalAddress(GV, EVT::i32);
- SDValue Hi = DAG.getNode(SPISD::Hi, dl, EVT::i32, GA);
- SDValue Lo = DAG.getNode(SPISD::Lo, dl, EVT::i32, GA);
- return DAG.getNode(ISD::ADD, dl, EVT::i32, Lo, Hi);
+ SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
+ SDValue Hi = DAG.getNode(SPISD::Hi, dl, MVT::i32, GA);
+ SDValue Lo = DAG.getNode(SPISD::Lo, dl, MVT::i32, GA);
+ return DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi);
}
static SDValue LowerCONSTANTPOOL(SDValue Op, SelectionDAG &DAG) {
// FIXME there isn't really any debug info here
DebugLoc dl = Op.getDebugLoc();
Constant *C = N->getConstVal();
- SDValue CP = DAG.getTargetConstantPool(C, EVT::i32, N->getAlignment());
- SDValue Hi = DAG.getNode(SPISD::Hi, dl, EVT::i32, CP);
- SDValue Lo = DAG.getNode(SPISD::Lo, dl, EVT::i32, CP);
- return DAG.getNode(ISD::ADD, dl, EVT::i32, Lo, Hi);
+ SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment());
+ SDValue Hi = DAG.getNode(SPISD::Hi, dl, MVT::i32, CP);
+ SDValue Lo = DAG.getNode(SPISD::Lo, dl, MVT::i32, CP);
+ return DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi);
}
static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
DebugLoc dl = Op.getDebugLoc();
// Convert the fp value to integer in an FP register.
- assert(Op.getValueType() == EVT::i32);
- Op = DAG.getNode(SPISD::FTOI, dl, EVT::f32, Op.getOperand(0));
- return DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, Op);
+ assert(Op.getValueType() == MVT::i32);
+ Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0));
+ return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
}
static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
DebugLoc dl = Op.getDebugLoc();
- assert(Op.getOperand(0).getValueType() == EVT::i32);
- SDValue Tmp = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, Op.getOperand(0));
+ assert(Op.getOperand(0).getValueType() == MVT::i32);
+ SDValue Tmp = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0));
// Convert the int value to FP in an FP register.
return DAG.getNode(SPISD::ITOF, dl, Op.getValueType(), Tmp);
}
// Get the condition flag.
SDValue CompareFlag;
- if (LHS.getValueType() == EVT::i32) {
+ if (LHS.getValueType() == MVT::i32) {
std::vector<EVT> VTs;
- VTs.push_back(EVT::i32);
- VTs.push_back(EVT::Flag);
+ VTs.push_back(MVT::i32);
+ VTs.push_back(MVT::Flag);
SDValue Ops[2] = { LHS, RHS };
CompareFlag = DAG.getNode(SPISD::CMPICC, dl, VTs, Ops, 2).getValue(1);
if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
Opc = SPISD::BRICC;
} else {
- CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, EVT::Flag, LHS, RHS);
+ CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Flag, LHS, RHS);
if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
Opc = SPISD::BRFCC;
}
- return DAG.getNode(Opc, dl, EVT::Other, Chain, Dest,
- DAG.getConstant(SPCC, EVT::i32), CompareFlag);
+ return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest,
+ DAG.getConstant(SPCC, MVT::i32), CompareFlag);
}
static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
LookThroughSetCC(LHS, RHS, CC, SPCC);
SDValue CompareFlag;
- if (LHS.getValueType() == EVT::i32) {
+ if (LHS.getValueType() == MVT::i32) {
std::vector<EVT> VTs;
VTs.push_back(LHS.getValueType()); // subcc returns a value
- VTs.push_back(EVT::Flag);
+ VTs.push_back(MVT::Flag);
SDValue Ops[2] = { LHS, RHS };
CompareFlag = DAG.getNode(SPISD::CMPICC, dl, VTs, Ops, 2).getValue(1);
Opc = SPISD::SELECT_ICC;
if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
} else {
- CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, EVT::Flag, LHS, RHS);
+ CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Flag, LHS, RHS);
Opc = SPISD::SELECT_FCC;
if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
}
return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal,
- DAG.getConstant(SPCC, EVT::i32), CompareFlag);
+ DAG.getConstant(SPCC, MVT::i32), CompareFlag);
}
static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
// vastart just stores the address of the VarArgsFrameIndex slot into the
// memory location argument.
DebugLoc dl = Op.getDebugLoc();
- SDValue Offset = DAG.getNode(ISD::ADD, dl, EVT::i32,
- DAG.getRegister(SP::I6, EVT::i32),
+ SDValue Offset = DAG.getNode(ISD::ADD, dl, MVT::i32,
+ DAG.getRegister(SP::I6, MVT::i32),
DAG.getConstant(TLI.getVarArgsFrameOffset(),
- EVT::i32));
+ MVT::i32));
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
return DAG.getStore(Op.getOperand(0), dl, Offset, Op.getOperand(1), SV, 0);
}
SDValue VAListPtr = Node->getOperand(1);
const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
DebugLoc dl = Node->getDebugLoc();
- SDValue VAList = DAG.getLoad(EVT::i32, dl, InChain, VAListPtr, SV, 0);
+ SDValue VAList = DAG.getLoad(MVT::i32, dl, InChain, VAListPtr, SV, 0);
// Increment the pointer, VAList, to the next vaarg
- SDValue NextPtr = DAG.getNode(ISD::ADD, dl, EVT::i32, VAList,
+ SDValue NextPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, VAList,
DAG.getConstant(VT.getSizeInBits()/8,
- EVT::i32));
+ MVT::i32));
// Store the incremented VAList to the legalized pointer
InChain = DAG.getStore(VAList.getValue(1), dl, NextPtr,
VAListPtr, SV, 0);
// Load the actual argument out of the pointer VAList, unless this is an
// f64 load.
- if (VT != EVT::f64)
+ if (VT != MVT::f64)
return DAG.getLoad(VT, dl, InChain, VAList, NULL, 0);
// Otherwise, load it as i64, then do a bitconvert.
- SDValue V = DAG.getLoad(EVT::i64, dl, InChain, VAList, NULL, 0);
+ SDValue V = DAG.getLoad(MVT::i64, dl, InChain, VAList, NULL, 0);
// Bit-Convert the value to f64.
SDValue Ops[2] = {
- DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f64, V),
+ DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, V),
V.getValue(1)
};
return DAG.getMergeValues(Ops, 2, dl);
DebugLoc dl = Op.getDebugLoc();
unsigned SPReg = SP::O6;
- SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, EVT::i32);
- SDValue NewSP = DAG.getNode(ISD::SUB, dl, EVT::i32, SP, Size); // Value
+ SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, MVT::i32);
+ SDValue NewSP = DAG.getNode(ISD::SUB, dl, MVT::i32, SP, Size); // Value
Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP); // Output chain
// The resultant pointer is actually 16 words from the bottom of the stack,
// to provide a register spill area.
- SDValue NewVal = DAG.getNode(ISD::ADD, dl, EVT::i32, NewSP,
- DAG.getConstant(96, EVT::i32));
+ SDValue NewVal = DAG.getNode(ISD::ADD, dl, MVT::i32, NewSP,
+ DAG.getConstant(96, MVT::i32));
SDValue Ops[2] = { NewVal, Chain };
return DAG.getMergeValues(Ops, 2, dl);
}
index 3f61cb35600edd75c843855f459e0f06292eee4c..8ecc5889c7bcfdce8a73cefebd03a8a2c2c64d45 100644 (file)
def LO10 : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 1023,
- EVT::i32);
+ MVT::i32);
}]>;
def HI22 : SDNodeXForm<imm, [{
// Transformation function: shift the immediate value down into the low bits.
- return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, EVT::i32);
+ return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, MVT::i32);
}]>;
def SETHIimm : PatLeaf<(imm), [{
diff --git a/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
index a8357a135381e1f4c6c6b390617e112efb399ffc..11d13062a9d77b7bc65b4ceb6992c91d6a2a32af 100644 (file)
/// getI8Imm - Return a target constant with the specified value, of type
/// i8.
inline SDValue getI8Imm(uint64_t Imm) {
- return CurDAG->getTargetConstant(Imm, EVT::i8);
+ return CurDAG->getTargetConstant(Imm, MVT::i8);
}
/// getI16Imm - Return a target constant with the specified value, of type
/// i16.
inline SDValue getI16Imm(uint64_t Imm) {
- return CurDAG->getTargetConstant(Imm, EVT::i16);
+ return CurDAG->getTargetConstant(Imm, MVT::i16);
}
/// getI32Imm - Return a target constant with the specified value, of type
/// i32.
inline SDValue getI32Imm(uint64_t Imm) {
- return CurDAG->getTargetConstant(Imm, EVT::i32);
+ return CurDAG->getTargetConstant(Imm, MVT::i32);
}
// Include the pieces autogenerated from the target description.
Base = AM.Base.Reg;
else
Base = CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, TLI.getPointerTy());
- Disp = CurDAG->getTargetConstant(AM.Disp, EVT::i64);
+ Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i64);
}
void SystemZDAGToDAGISel::getAddressOperands(const SystemZRRIAddressMode &AM,
EVT ResVT;
bool is32Bit = false;
- switch (NVT.getSimpleVT()) {
+ switch (NVT.getSimpleVT().SimpleTy) {
default: assert(0 && "Unsupported VT!");
- case EVT::i32:
+ case MVT::i32:
Opc = SystemZ::SDIVREM32r; MOpc = SystemZ::SDIVREM32m;
- ResVT = EVT::v2i64;
+ ResVT = MVT::v2i64;
is32Bit = true;
break;
- case EVT::i64:
+ case MVT::i64:
Opc = SystemZ::SDIVREM64r; MOpc = SystemZ::SDIVREM64m;
- ResVT = EVT::v2i64;
+ ResVT = MVT::v2i64;
break;
}
// Prepare the dividend
SDNode *Dividend;
if (is32Bit)
- Dividend = CurDAG->getTargetNode(SystemZ::MOVSX64rr32, dl, EVT::i64, N0);
+ Dividend = CurDAG->getTargetNode(SystemZ::MOVSX64rr32, dl, MVT::i64, N0);
else
Dividend = N0.getNode();
Dividend =
CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, ResVT,
SDValue(Tmp, 0), SDValue(Dividend, 0),
- CurDAG->getTargetConstant(subreg_odd, EVT::i32));
+ CurDAG->getTargetConstant(subreg_odd, MVT::i32));
SDNode *Result;
SDValue DivVal = SDValue(Dividend, 0);
dl, NVT,
SDValue(Result, 0),
CurDAG->getTargetConstant(SubRegIdx,
- EVT::i32));
+ MVT::i32));
ReplaceUses(Op.getValue(0), SDValue(Div, 0));
#ifndef NDEBUG
dl, NVT,
SDValue(Result, 0),
CurDAG->getTargetConstant(SubRegIdx,
- EVT::i32));
+ MVT::i32));
ReplaceUses(Op.getValue(1), SDValue(Rem, 0));
#ifndef NDEBUG
EVT ResVT;
bool is32Bit = false;
- switch (NVT.getSimpleVT()) {
+ switch (NVT.getSimpleVT().SimpleTy) {
default: assert(0 && "Unsupported VT!");
- case EVT::i32:
+ case MVT::i32:
Opc = SystemZ::UDIVREM32r; MOpc = SystemZ::UDIVREM32m;
ClrOpc = SystemZ::MOV64Pr0_even;
- ResVT = EVT::v2i32;
+ ResVT = MVT::v2i32;
is32Bit = true;
break;
- case EVT::i64:
+ case MVT::i64:
Opc = SystemZ::UDIVREM64r; MOpc = SystemZ::UDIVREM64m;
ClrOpc = SystemZ::MOV128r0_even;
- ResVT = EVT::v2i64;
+ ResVT = MVT::v2i64;
break;
}
Dividend =
CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, ResVT,
SDValue(Tmp, 0), SDValue(Dividend, 0),
- CurDAG->getTargetConstant(SubRegIdx, EVT::i32));
+ CurDAG->getTargetConstant(SubRegIdx, MVT::i32));
}
// Zero out even subreg
dl, NVT,
SDValue(Result, 0),
CurDAG->getTargetConstant(SubRegIdx,
- EVT::i32));
+ MVT::i32));
ReplaceUses(Op.getValue(0), SDValue(Div, 0));
#ifndef NDEBUG
DOUT << std::string(Indent-2, ' ') << "=> ";
dl, NVT,
SDValue(Result, 0),
CurDAG->getTargetConstant(SubRegIdx,
- EVT::i32));
+ MVT::i32));
ReplaceUses(Op.getValue(1), SDValue(Rem, 0));
#ifndef NDEBUG
DOUT << std::string(Indent-2, ' ') << "=> ";
diff --git a/lib/Target/SystemZ/SystemZISelLowering.cpp b/lib/Target/SystemZ/SystemZISelLowering.cpp
index 6ffb434bbf2cc5b2133e597bef09936ca4095318..279e22b653310f6d4e3500b86472cf95fda0d4f0 100644 (file)
RegInfo = TM.getRegisterInfo();
// Set up the register classes.
- addRegisterClass(EVT::i32, SystemZ::GR32RegisterClass);
- addRegisterClass(EVT::i64, SystemZ::GR64RegisterClass);
- addRegisterClass(EVT::v2i32,SystemZ::GR64PRegisterClass);
- addRegisterClass(EVT::v2i64,SystemZ::GR128RegisterClass);
+ addRegisterClass(MVT::i32, SystemZ::GR32RegisterClass);
+ addRegisterClass(MVT::i64, SystemZ::GR64RegisterClass);
+ addRegisterClass(MVT::v2i32,SystemZ::GR64PRegisterClass);
+ addRegisterClass(MVT::v2i64,SystemZ::GR128RegisterClass);
if (!UseSoftFloat) {
- addRegisterClass(EVT::f32, SystemZ::FP32RegisterClass);
- addRegisterClass(EVT::f64, SystemZ::FP64RegisterClass);
+ addRegisterClass(MVT::f32, SystemZ::FP32RegisterClass);
+ addRegisterClass(MVT::f64, SystemZ::FP64RegisterClass);
addLegalFPImmediate(APFloat(+0.0)); // lzer
addLegalFPImmediate(APFloat(+0.0f)); // lzdr
computeRegisterProperties();
// Set shifts properties
- setShiftAmountType(EVT::i64);
+ setShiftAmountType(MVT::i64);
// Provide all sorts of operation actions
- setLoadExtAction(ISD::SEXTLOAD, EVT::i1, Promote);
- setLoadExtAction(ISD::ZEXTLOAD, EVT::i1, Promote);
- setLoadExtAction(ISD::EXTLOAD, EVT::i1, Promote);
+ setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
+ setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
+ setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
- setLoadExtAction(ISD::SEXTLOAD, EVT::f32, Expand);
- setLoadExtAction(ISD::ZEXTLOAD, EVT::f32, Expand);
- setLoadExtAction(ISD::EXTLOAD, EVT::f32, Expand);
+ setLoadExtAction(ISD::SEXTLOAD, MVT::f32, Expand);
+ setLoadExtAction(ISD::ZEXTLOAD, MVT::f32, Expand);
+ setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
- setLoadExtAction(ISD::SEXTLOAD, EVT::f64, Expand);
- setLoadExtAction(ISD::ZEXTLOAD, EVT::f64, Expand);
- setLoadExtAction(ISD::EXTLOAD, EVT::f64, Expand);
+ setLoadExtAction(ISD::SEXTLOAD, MVT::f64, Expand);
+ setLoadExtAction(ISD::ZEXTLOAD, MVT::f64, Expand);
+ setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
setStackPointerRegisterToSaveRestore(SystemZ::R15D);
setSchedulingPreference(SchedulingForLatency);
setBooleanContents(ZeroOrOneBooleanContent);
- setOperationAction(ISD::BR_JT, EVT::Other, Expand);
- setOperationAction(ISD::BRCOND, EVT::Other, Expand);
- setOperationAction(ISD::BR_CC, EVT::i32, Custom);
- setOperationAction(ISD::BR_CC, EVT::i64, Custom);
- setOperationAction(ISD::BR_CC, EVT::f32, Custom);
- setOperationAction(ISD::BR_CC, EVT::f64, Custom);
- setOperationAction(ISD::ConstantPool, EVT::i32, Custom);
- setOperationAction(ISD::ConstantPool, EVT::i64, Custom);
- setOperationAction(ISD::GlobalAddress, EVT::i64, Custom);
- setOperationAction(ISD::JumpTable, EVT::i64, Custom);
- setOperationAction(ISD::DYNAMIC_STACKALLOC, EVT::i64, Expand);
-
- setOperationAction(ISD::SDIV, EVT::i32, Expand);
- setOperationAction(ISD::UDIV, EVT::i32, Expand);
- setOperationAction(ISD::SDIV, EVT::i64, Expand);
- setOperationAction(ISD::UDIV, EVT::i64, Expand);
- setOperationAction(ISD::SREM, EVT::i32, Expand);
- setOperationAction(ISD::UREM, EVT::i32, Expand);
- setOperationAction(ISD::SREM, EVT::i64, Expand);
- setOperationAction(ISD::UREM, EVT::i64, Expand);
-
- setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i1, Expand);
-
- setOperationAction(ISD::CTPOP, EVT::i32, Expand);
- setOperationAction(ISD::CTPOP, EVT::i64, Expand);
- setOperationAction(ISD::CTTZ, EVT::i32, Expand);
- setOperationAction(ISD::CTTZ, EVT::i64, Expand);
- setOperationAction(ISD::CTLZ, EVT::i32, Promote);
- setOperationAction(ISD::CTLZ, EVT::i64, Legal);
+ setOperationAction(ISD::BR_JT, MVT::Other, Expand);
+ setOperationAction(ISD::BRCOND, MVT::Other, Expand);
+ setOperationAction(ISD::BR_CC, MVT::i32, Custom);
+ setOperationAction(ISD::BR_CC, MVT::i64, Custom);
+ setOperationAction(ISD::BR_CC, MVT::f32, Custom);
+ setOperationAction(ISD::BR_CC, MVT::f64, Custom);
+ setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
+ setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
+ setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
+ setOperationAction(ISD::JumpTable, MVT::i64, Custom);
+ setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
+
+ setOperationAction(ISD::SDIV, MVT::i32, Expand);
+ setOperationAction(ISD::UDIV, MVT::i32, Expand);
+ setOperationAction(ISD::SDIV, MVT::i64, Expand);
+ setOperationAction(ISD::UDIV, MVT::i64, Expand);
+ setOperationAction(ISD::SREM, MVT::i32, Expand);
+ setOperationAction(ISD::UREM, MVT::i32, Expand);
+ setOperationAction(ISD::SREM, MVT::i64, Expand);
+ setOperationAction(ISD::UREM, MVT::i64, Expand);
+
+ setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
+
+ setOperationAction(ISD::CTPOP, MVT::i32, Expand);
+ setOperationAction(ISD::CTPOP, MVT::i64, Expand);
+ setOperationAction(ISD::CTTZ, MVT::i32, Expand);
+ setOperationAction(ISD::CTTZ, MVT::i64, Expand);
+ setOperationAction(ISD::CTLZ, MVT::i32, Promote);
+ setOperationAction(ISD::CTLZ, MVT::i64, Legal);
// FIXME: Can we lower these 2 efficiently?
- setOperationAction(ISD::SETCC, EVT::i32, Expand);
- setOperationAction(ISD::SETCC, EVT::i64, Expand);
- setOperationAction(ISD::SETCC, EVT::f32, Expand);
- setOperationAction(ISD::SETCC, EVT::f64, Expand);
- setOperationAction(ISD::SELECT, EVT::i32, Expand);
- setOperationAction(ISD::SELECT, EVT::i64, Expand);
- setOperationAction(ISD::SELECT, EVT::f32, Expand);
- setOperationAction(ISD::SELECT, EVT::f64, Expand);
- setOperationAction(ISD::SELECT_CC, EVT::i32, Custom);
- setOperationAction(ISD::SELECT_CC, EVT::i64, Custom);
- setOperationAction(ISD::SELECT_CC, EVT::f32, Custom);
- setOperationAction(ISD::SELECT_CC, EVT::f64, Custom);
+ setOperationAction(ISD::SETCC, MVT::i32, Expand);
+ setOperationAction(ISD::SETCC, MVT::i64, Expand);
+ setOperationAction(ISD::SETCC, MVT::f32, Expand);
+ setOperationAction(ISD::SETCC, MVT::f64, Expand);
+ setOperationAction(ISD::SELECT, MVT::i32, Expand);
+ setOperationAction(ISD::SELECT, MVT::i64, Expand);
+ setOperationAction(ISD::SELECT, MVT::f32, Expand);
+ setOperationAction(ISD::SELECT, MVT::f64, Expand);
+ setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
+ setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
+ setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
+ setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
// Funny enough: we don't have 64-bit signed versions of these stuff, but have
// unsigned.
- setOperationAction(ISD::MULHS, EVT::i64, Expand);
- setOperationAction(ISD::SMUL_LOHI, EVT::i64, Expand);
+ setOperationAction(ISD::MULHS, MVT::i64, Expand);
+ setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
// Lower some FP stuff
- setOperationAction(ISD::FSIN, EVT::f32, Expand);
- setOperationAction(ISD::FSIN, EVT::f64, Expand);
- setOperationAction(ISD::FCOS, EVT::f32, Expand);
- setOperationAction(ISD::FCOS, EVT::f64, Expand);
- setOperationAction(ISD::FREM, EVT::f32, Expand);
- setOperationAction(ISD::FREM, EVT::f64, Expand);
+ setOperationAction(ISD::FSIN, MVT::f32, Expand);
+ setOperationAction(ISD::FSIN, MVT::f64, Expand);
+ setOperationAction(ISD::FCOS, MVT::f32, Expand);
+ setOperationAction(ISD::FCOS, MVT::f64, Expand);
+ setOperationAction(ISD::FREM, MVT::f32, Expand);
+ setOperationAction(ISD::FREM, MVT::f64, Expand);
// We have only 64-bit bitconverts
- setOperationAction(ISD::BIT_CONVERT, EVT::f32, Expand);
- setOperationAction(ISD::BIT_CONVERT, EVT::i32, Expand);
+ setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
+ setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
- setOperationAction(ISD::UINT_TO_FP, EVT::i32, Expand);
- setOperationAction(ISD::UINT_TO_FP, EVT::i64, Expand);
- setOperationAction(ISD::FP_TO_UINT, EVT::i32, Expand);
- setOperationAction(ISD::FP_TO_UINT, EVT::i64, Expand);
+ setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
+ setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
+ setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
+ setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
- setTruncStoreAction(EVT::f64, EVT::f32, Expand);
+ setTruncStoreAction(MVT::f64, MVT::f32, Expand);
}
SDValue SystemZTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
if (VA.isRegLoc()) {
// Arguments passed in registers
TargetRegisterClass *RC;
- switch (LocVT.getSimpleVT()) {
+ switch (LocVT.getSimpleVT().SimpleTy) {
default:
#ifndef NDEBUG
cerr << "LowerFormalArguments Unhandled argument type: "
- << LocVT.getSimpleVT()
+ << LocVT.getSimpleVT().SimpleTy
<< "\n";
#endif
llvm_unreachable(0);
- case EVT::i64:
+ case MVT::i64:
RC = SystemZ::GR64RegisterClass;
break;
- case EVT::f32:
+ case MVT::f32:
RC = SystemZ::FP32RegisterClass;
break;
- case EVT::f64:
+ case MVT::f64:
RC = SystemZ::FP64RegisterClass;
break;
}
// Transform all store nodes into one single node because all store nodes are
// independent of each other.
if (!MemOpChains.empty())
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&MemOpChains[0], MemOpChains.size());
// Build a sequence of copy-to-reg nodes chained together with token chain and
Callee = DAG.getTargetExternalSymbol(E->getSymbol(), getPointerTy());
// Returns a chain & a flag for retval copy to use.
- SDVTList NodeTys = DAG.getVTList(EVT::Other, EVT::Flag);
+ SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
SmallVector<SDValue, 8> Ops;
Ops.push_back(Chain);
Ops.push_back(Callee);
}
if (Flag.getNode())
- return DAG.getNode(SystemZISD::RET_FLAG, dl, EVT::Other, Chain, Flag);
+ return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
// Return Void
- return DAG.getNode(SystemZISD::RET_FLAG, dl, EVT::Other, Chain);
+ return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain);
}
SDValue SystemZTargetLowering::EmitCmp(SDValue LHS, SDValue RHS,
break;
}
- SystemZCC = DAG.getConstant(TCC, EVT::i32);
+ SystemZCC = DAG.getConstant(TCC, MVT::i32);
DebugLoc dl = LHS.getDebugLoc();
return DAG.getNode((isUnsigned ? SystemZISD::UCMP : SystemZISD::CMP),
- dl, EVT::Flag, LHS, RHS);
+ dl, MVT::Flag, LHS, RHS);
}
SDValue SystemZCC;
SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG);
- SDVTList VTs = DAG.getVTList(Op.getValueType(), EVT::Flag);
+ SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
SmallVector<SDValue, 4> Ops;
Ops.push_back(TrueV);
Ops.push_back(FalseV);
index 0ee48c3ebafbc13c1922303013e3ef406a475a6a..156cace9c3746e8a857efee9154bb4937a708120 100644 (file)
def immSExt16 : PatLeaf<(imm), [{
// immSExt16 predicate - true if the immediate fits in a 16-bit sign extended
// field.
- if (N->getValueType(0) == EVT::i64) {
+ if (N->getValueType(0) == MVT::i64) {
uint64_t val = N->getZExtValue();
return ((int64_t)val == (int16_t)val);
- } else if (N->getValueType(0) == EVT::i32) {
+ } else if (N->getValueType(0) == MVT::i32) {
uint32_t val = N->getZExtValue();
return ((int32_t)val == (int16_t)val);
}
index b649fca67dc5c1e7658c51598a0dbe0bdcfb05a1..902ee0c04d8ab04aca2044ab5c6d546e1e255fa5 100644 (file)
const TargetRegisterClass* BestRC = 0;
for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I){
const TargetRegisterClass* RC = *I;
- if ((VT == EVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
+ if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
(!BestRC || BestRC->hasSuperClass(RC)))
BestRC = RC;
}
diff --git a/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp b/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
index 1d8d7a72959f865a14a02b35c79a5c66413cf39f..860d5005672a1bdc8fdbf70f4b7b5cd24fae2be5 100644 (file)
unsigned Reg = MO.getReg();
if (Modifier && strncmp(Modifier, "subreg", strlen("subreg")) == 0) {
EVT VT = (strcmp(Modifier+6,"64") == 0) ?
- EVT::i64 : ((strcmp(Modifier+6, "32") == 0) ? EVT::i32 :
- ((strcmp(Modifier+6,"16") == 0) ? EVT::i16 : EVT::i8));
+ MVT::i64 : ((strcmp(Modifier+6, "32") == 0) ? MVT::i32 :
+ ((strcmp(Modifier+6,"16") == 0) ? MVT::i16 : MVT::i8));
Reg = getX86SubSuperRegister(Reg, VT);
}
O << TRI->getAsmName(Reg);
@@ -573,19 +573,19 @@ bool X86ATTAsmPrinter::printAsmMRegister(const MachineOperand &MO, char Mode) {
switch (Mode) {
default: return true; // Unknown mode.
case 'b': // Print QImode register
- Reg = getX86SubSuperRegister(Reg, EVT::i8);
+ Reg = getX86SubSuperRegister(Reg, MVT::i8);
break;
case 'h': // Print QImode high register
- Reg = getX86SubSuperRegister(Reg, EVT::i8, true);
+ Reg = getX86SubSuperRegister(Reg, MVT::i8, true);
break;
case 'w': // Print HImode register
- Reg = getX86SubSuperRegister(Reg, EVT::i16);
+ Reg = getX86SubSuperRegister(Reg, MVT::i16);
break;
case 'k': // Print SImode register
- Reg = getX86SubSuperRegister(Reg, EVT::i32);
+ Reg = getX86SubSuperRegister(Reg, MVT::i32);
break;
case 'q': // Print DImode register
- Reg = getX86SubSuperRegister(Reg, EVT::i64);
+ Reg = getX86SubSuperRegister(Reg, MVT::i64);
break;
}
unsigned Reg = MI->getOperand(i).getReg();
if (Reg == 0) continue;
- MI->getOperand(i).setReg(getX86SubSuperRegister(Reg, EVT::i64));
+ MI->getOperand(i).setReg(getX86SubSuperRegister(Reg, MVT::i64));
}
}
diff --git a/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp b/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp
index 08f5aa45fefd825de952d55b5fafd1ee643427f9..153f41abf0736993d0438bc0897ad6075f96409d 100644 (file)
unsigned Reg = MO.getReg();
if (Modifier && strncmp(Modifier, "subreg", strlen("subreg")) == 0) {
EVT VT = (strcmp(Modifier,"subreg64") == 0) ?
- EVT::i64 : ((strcmp(Modifier, "subreg32") == 0) ? EVT::i32 :
- ((strcmp(Modifier,"subreg16") == 0) ? EVT::i16 :EVT::i8));
+ MVT::i64 : ((strcmp(Modifier, "subreg32") == 0) ? MVT::i32 :
+ ((strcmp(Modifier,"subreg16") == 0) ? MVT::i16 :MVT::i8));
Reg = getX86SubSuperRegister(Reg, VT);
}
O << TRI->getName(Reg);
switch (Mode) {
default: return true; // Unknown mode.
case 'b': // Print QImode register
- Reg = getX86SubSuperRegister(Reg, EVT::i8);
+ Reg = getX86SubSuperRegister(Reg, MVT::i8);
break;
case 'h': // Print QImode high register
- Reg = getX86SubSuperRegister(Reg, EVT::i8, true);
+ Reg = getX86SubSuperRegister(Reg, MVT::i8, true);
break;
case 'w': // Print HImode register
- Reg = getX86SubSuperRegister(Reg, EVT::i16);
+ Reg = getX86SubSuperRegister(Reg, MVT::i16);
break;
case 'k': // Print SImode register
- Reg = getX86SubSuperRegister(Reg, EVT::i32);
+ Reg = getX86SubSuperRegister(Reg, MVT::i32);
break;
}
index 30466817c7e9a68c4e9c97e3ae17c65ee35d8ec0..b98a9738c64c9380a6c3e9e9a565c95f5121c6bf 100644 (file)
/// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
/// computed in an SSE register, not on the X87 floating point stack.
bool isScalarFPTypeInSSEReg(EVT VT) const {
- return (VT == EVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
- (VT == EVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
+ return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
+ (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
}
bool isTypeLegal(const Type *Ty, EVT &VT, bool AllowI1 = false);
bool X86FastISel::isTypeLegal(const Type *Ty, EVT &VT, bool AllowI1) {
VT = TLI.getValueType(Ty, /*HandleUnknown=*/true);
- if (VT == EVT::Other || !VT.isSimple())
+ if (VT == MVT::Other || !VT.isSimple())
// Unhandled type. Halt "fast" selection and bail.
return false;
// For now, require SSE/SSE2 for performing floating-point operations,
// since x87 requires additional work.
- if (VT == EVT::f64 && !X86ScalarSSEf64)
+ if (VT == MVT::f64 && !X86ScalarSSEf64)
return false;
- if (VT == EVT::f32 && !X86ScalarSSEf32)
+ if (VT == MVT::f32 && !X86ScalarSSEf32)
return false;
// Similarly, no f80 support yet.
- if (VT == EVT::f80)
+ if (VT == MVT::f80)
return false;
// We only handle legal types. For example, on x86-32 the instruction
// selector contains all of the 64-bit instructions from x86-64,
// under the assumption that i64 won't be used if the target doesn't
// support it.
- return (AllowI1 && VT == EVT::i1) || TLI.isTypeLegal(VT);
+ return (AllowI1 && VT == MVT::i1) || TLI.isTypeLegal(VT);
}
#include "X86GenCallingConv.inc"
// Get opcode and regclass of the output for the given load instruction.
unsigned Opc = 0;
const TargetRegisterClass *RC = NULL;
- switch (VT.getSimpleVT()) {
+ switch (VT.getSimpleVT().SimpleTy) {
default: return false;
- case EVT::i8:
+ case MVT::i8:
Opc = X86::MOV8rm;
RC = X86::GR8RegisterClass;
break;
- case EVT::i16:
+ case MVT::i16:
Opc = X86::MOV16rm;
RC = X86::GR16RegisterClass;
break;
- case EVT::i32:
+ case MVT::i32:
Opc = X86::MOV32rm;
RC = X86::GR32RegisterClass;
break;
- case EVT::i64:
+ case MVT::i64:
// Must be in x86-64 mode.
Opc = X86::MOV64rm;
RC = X86::GR64RegisterClass;
break;
- case EVT::f32:
+ case MVT::f32:
if (Subtarget->hasSSE1()) {
Opc = X86::MOVSSrm;
RC = X86::FR32RegisterClass;
RC = X86::RFP32RegisterClass;
}
break;
- case EVT::f64:
+ case MVT::f64:
if (Subtarget->hasSSE2()) {
Opc = X86::MOVSDrm;
RC = X86::FR64RegisterClass;
RC = X86::RFP64RegisterClass;
}
break;
- case EVT::f80:
+ case MVT::f80:
// No f80 support yet.
return false;
}
const X86AddressMode &AM) {
// Get opcode and regclass of the output for the given store instruction.
unsigned Opc = 0;
- switch (VT.getSimpleVT()) {
- case EVT::f80: // No f80 support yet.
+ switch (VT.getSimpleVT().SimpleTy) {
+ case MVT::f80: // No f80 support yet.
default: return false;
- case EVT::i8: Opc = X86::MOV8mr; break;
- case EVT::i16: Opc = X86::MOV16mr; break;
- case EVT::i32: Opc = X86::MOV32mr; break;
- case EVT::i64: Opc = X86::MOV64mr; break; // Must be in x86-64 mode.
- case EVT::f32:
+ case MVT::i8: Opc = X86::MOV8mr; break;
+ case MVT::i16: Opc = X86::MOV16mr; break;
+ case MVT::i32: Opc = X86::MOV32mr; break;
+ case MVT::i64: Opc = X86::MOV64mr; break; // Must be in x86-64 mode.
+ case MVT::f32:
Opc = Subtarget->hasSSE1() ? X86::MOVSSmr : X86::ST_Fp32m;
break;
- case EVT::f64:
+ case MVT::f64:
Opc = Subtarget->hasSSE2() ? X86::MOVSDmr : X86::ST_Fp64m;
break;
}
// If this is a store of a simple constant, fold the constant into the store.
if (ConstantInt *CI = dyn_cast<ConstantInt>(Val)) {
unsigned Opc = 0;
- switch (VT.getSimpleVT()) {
+ switch (VT.getSimpleVT().SimpleTy) {
default: break;
- case EVT::i8: Opc = X86::MOV8mi; break;
- case EVT::i16: Opc = X86::MOV16mi; break;
- case EVT::i32: Opc = X86::MOV32mi; break;
- case EVT::i64:
+ case MVT::i8: Opc = X86::MOV8mi; break;
+ case MVT::i16: Opc = X86::MOV16mi; break;
+ case MVT::i32: Opc = X86::MOV32mi; break;
+ case MVT::i64:
// Must be a 32-bit sign extended value.
if ((int)CI->getSExtValue() == CI->getSExtValue())
Opc = X86::MOV64mi32;
StubAM.GV = GV;
StubAM.GVOpFlags = GVFlags;
- if (TLI.getPointerTy() == EVT::i64) {
+ if (TLI.getPointerTy() == MVT::i64) {
Opc = X86::MOV64rm;
RC = X86::GR64RegisterClass;
}
static unsigned X86ChooseCmpOpcode(EVT VT) {
- switch (VT.getSimpleVT()) {
+ switch (VT.getSimpleVT().SimpleTy) {
default: return 0;
- case EVT::i8: return X86::CMP8rr;
- case EVT::i16: return X86::CMP16rr;
- case EVT::i32: return X86::CMP32rr;
- case EVT::i64: return X86::CMP64rr;
- case EVT::f32: return X86::UCOMISSrr;
- case EVT::f64: return X86::UCOMISDrr;
+ case MVT::i8: return X86::CMP8rr;
+ case MVT::i16: return X86::CMP16rr;
+ case MVT::i32: return X86::CMP32rr;
+ case MVT::i64: return X86::CMP64rr;
+ case MVT::f32: return X86::UCOMISSrr;
+ case MVT::f64: return X86::UCOMISDrr;
}
}
/// of the comparison, return an opcode that works for the compare (e.g.
/// CMP32ri) otherwise return 0.
static unsigned X86ChooseCmpImmediateOpcode(EVT VT, ConstantInt *RHSC) {
- switch (VT.getSimpleVT()) {
+ switch (VT.getSimpleVT().SimpleTy) {
// Otherwise, we can't fold the immediate into this comparison.
default: return 0;
- case EVT::i8: return X86::CMP8ri;
- case EVT::i16: return X86::CMP16ri;
- case EVT::i32: return X86::CMP32ri;
- case EVT::i64:
+ case MVT::i8: return X86::CMP8ri;
+ case MVT::i16: return X86::CMP16ri;
+ case MVT::i32: return X86::CMP32ri;
+ case MVT::i64:
// 64-bit comparisons are only valid if the immediate fits in a 32-bit sext
// field.
if ((int)RHSC->getSExtValue() == RHSC->getSExtValue())
unsigned ResultReg = getRegForValue(I->getOperand(0));
if (ResultReg == 0) return false;
// Set the high bits to zero.
- ResultReg = FastEmitZExtFromI1(EVT::i8, ResultReg);
+ ResultReg = FastEmitZExtFromI1(MVT::i8, ResultReg);
if (ResultReg == 0) return false;
UpdateValueMap(I, ResultReg);
return true;
}
EVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
- if (VT == EVT::Other || !isTypeLegal(I->getType(), VT))
+ if (VT == MVT::Other || !isTypeLegal(I->getType(), VT))
return false;
unsigned Op0Reg = getRegForValue(I->getOperand(0));
bool X86FastISel::X86SelectSelect(Instruction *I) {
EVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
- if (VT == EVT::Other || !isTypeLegal(I->getType(), VT))
+ if (VT == MVT::Other || !isTypeLegal(I->getType(), VT))
return false;
unsigned Opc = 0;
const TargetRegisterClass *RC = NULL;
- if (VT.getSimpleVT() == EVT::i16) {
+ if (VT.getSimpleVT() == MVT::i16) {
Opc = X86::CMOVE16rr;
RC = &X86::GR16RegClass;
- } else if (VT.getSimpleVT() == EVT::i32) {
+ } else if (VT.getSimpleVT() == MVT::i32) {
Opc = X86::CMOVE32rr;
RC = &X86::GR32RegClass;
- } else if (VT.getSimpleVT() == EVT::i64) {
+ } else if (VT.getSimpleVT() == MVT::i64) {
Opc = X86::CMOVE64rr;
RC = &X86::GR64RegClass;
} else {
EVT DstVT = TLI.getValueType(I->getType());
// This code only handles truncation to byte right now.
- if (DstVT != EVT::i8 && DstVT != EVT::i1)
+ if (DstVT != MVT::i8 && DstVT != MVT::i1)
// All other cases should be handled by the tblgen generated code.
return false;
- if (SrcVT != EVT::i16 && SrcVT != EVT::i32)
+ if (SrcVT != MVT::i16 && SrcVT != MVT::i32)
// All other cases should be handled by the tblgen generated code.
return false;
return false;
// First issue a copy to GR16_ABCD or GR32_ABCD.
- unsigned CopyOpc = (SrcVT == EVT::i16) ? X86::MOV16rr : X86::MOV32rr;
- const TargetRegisterClass *CopyRC = (SrcVT == EVT::i16)
+ unsigned CopyOpc = (SrcVT == MVT::i16) ? X86::MOV16rr : X86::MOV32rr;
+ const TargetRegisterClass *CopyRC = (SrcVT == MVT::i16)
? X86::GR16_ABCDRegisterClass : X86::GR32_ABCDRegisterClass;
unsigned CopyReg = createResultReg(CopyRC);
BuildMI(MBB, DL, TII.get(CopyOpc), CopyReg).addReg(InputReg);
// Then issue an extract_subreg.
- unsigned ResultReg = FastEmitInst_extractsubreg(EVT::i8,
+ unsigned ResultReg = FastEmitInst_extractsubreg(MVT::i8,
CopyReg, X86::SUBREG_8BIT);
if (!ResultReg)
return false;
return false;
unsigned OpC = 0;
- if (VT == EVT::i32)
+ if (VT == MVT::i32)
OpC = X86::ADD32rr;
- else if (VT == EVT::i64)
+ else if (VT == MVT::i64)
OpC = X86::ADD64rr;
else
return false;
if (DestReg1 != ResultReg)
ResultReg = DestReg1+1;
else
- ResultReg = createResultReg(TLI.getRegClassFor(EVT::i8));
+ ResultReg = createResultReg(TLI.getRegClassFor(MVT::i8));
unsigned Opc = X86::SETBr;
if (I.getIntrinsicID() == Intrinsic::sadd_with_overflow)
const Type *RetTy = CS.getType();
EVT RetVT;
if (RetTy == Type::VoidTy)
- RetVT = EVT::isVoid;
+ RetVT = MVT::isVoid;
else if (!isTypeLegal(RetTy, RetVT, true))
return false;
// Allow calls which produce i1 results.
bool AndToI1 = false;
- if (RetVT == EVT::i1) {
- RetVT = EVT::i8;
+ if (RetVT == MVT::i1) {
+ RetVT = MVT::i8;
AndToI1 = true;
}
BuildMI(MBB, DL, TII.get(AdjStackUp)).addImm(NumBytes).addImm(0);
// Now handle call return value (if any).
- if (RetVT.getSimpleVT() != EVT::isVoid) {
+ if (RetVT.getSimpleVT().SimpleTy != MVT::isVoid) {
SmallVector<CCValAssign, 16> RVLocs;
CCState CCInfo(CC, false, TM, RVLocs, I->getParent()->getContext());
CCInfo.AnalyzeCallResult(RetVT, RetCC_X86);
if ((RVLocs[0].getLocReg() == X86::ST0 ||
RVLocs[0].getLocReg() == X86::ST1) &&
isScalarFPTypeInSSEReg(RVLocs[0].getValVT())) {
- CopyVT = EVT::f80;
+ CopyVT = MVT::f80;
SrcRC = X86::RSTRegisterClass;
DstRC = X86::RFP80RegisterClass;
}
// register. This is accomplished by storing the F80 value in memory and
// then loading it back. Ewww...
EVT ResVT = RVLocs[0].getValVT();
- unsigned Opc = ResVT == EVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64;
+ unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64;
unsigned MemSize = ResVT.getSizeInBits()/8;
int FI = MFI.CreateStackObject(MemSize, MemSize);
addFrameReference(BuildMI(MBB, DL, TII.get(Opc)), FI).addReg(ResultReg);
- DstRC = ResVT == EVT::f32
+ DstRC = ResVT == MVT::f32
? X86::FR32RegisterClass : X86::FR64RegisterClass;
- Opc = ResVT == EVT::f32 ? X86::MOVSSrm : X86::MOVSDrm;
+ Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm;
ResultReg = createResultReg(DstRC);
addFrameReference(BuildMI(MBB, DL, TII.get(Opc), ResultReg), FI);
}
// Get opcode and regclass of the output for the given load instruction.
unsigned Opc = 0;
const TargetRegisterClass *RC = NULL;
- switch (VT.getSimpleVT()) {
+ switch (VT.getSimpleVT().SimpleTy) {
default: return false;
- case EVT::i8:
+ case MVT::i8:
Opc = X86::MOV8rm;
RC = X86::GR8RegisterClass;
break;
- case EVT::i16:
+ case MVT::i16:
Opc = X86::MOV16rm;
RC = X86::GR16RegisterClass;
break;
- case EVT::i32:
+ case MVT::i32:
Opc = X86::MOV32rm;
RC = X86::GR32RegisterClass;
break;
- case EVT::i64:
+ case MVT::i64:
// Must be in x86-64 mode.
Opc = X86::MOV64rm;
RC = X86::GR64RegisterClass;
break;
- case EVT::f32:
+ case MVT::f32:
if (Subtarget->hasSSE1()) {
Opc = X86::MOVSSrm;
RC = X86::FR32RegisterClass;
RC = X86::RFP32RegisterClass;
}
break;
- case EVT::f64:
+ case MVT::f64:
if (Subtarget->hasSSE2()) {
Opc = X86::MOVSDrm;
RC = X86::FR64RegisterClass;
RC = X86::RFP64RegisterClass;
}
break;
- case EVT::f80:
+ case MVT::f80:
// No f80 support yet.
return false;
}
if (isa<GlobalValue>(C)) {
X86AddressMode AM;
if (X86SelectAddress(C, AM)) {
- if (TLI.getPointerTy() == EVT::i32)
+ if (TLI.getPointerTy() == MVT::i32)
Opc = X86::LEA32r;
else
Opc = X86::LEA64r;
index 4aee4930fc30a2a9100a9df559044070ca9f1f56..1f1b4fecf5ea559b85ad332131b7bb035f8f7e03 100644 (file)
// These are 32-bit even in 64-bit mode since RIP relative offset
// is 32-bit.
if (AM.GV)
- Disp = CurDAG->getTargetGlobalAddress(AM.GV, EVT::i32, AM.Disp,
+ Disp = CurDAG->getTargetGlobalAddress(AM.GV, MVT::i32, AM.Disp,
AM.SymbolFlags);
else if (AM.CP)
- Disp = CurDAG->getTargetConstantPool(AM.CP, EVT::i32,
+ Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i32,
AM.Align, AM.Disp, AM.SymbolFlags);
else if (AM.ES)
- Disp = CurDAG->getTargetExternalSymbol(AM.ES, EVT::i32, AM.SymbolFlags);
+ Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i32, AM.SymbolFlags);
else if (AM.JT != -1)
- Disp = CurDAG->getTargetJumpTable(AM.JT, EVT::i32, AM.SymbolFlags);
+ Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i32, AM.SymbolFlags);
else
- Disp = CurDAG->getTargetConstant(AM.Disp, EVT::i32);
+ Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i32);
if (AM.Segment.getNode())
Segment = AM.Segment;
else
- Segment = CurDAG->getRegister(0, EVT::i32);
+ Segment = CurDAG->getRegister(0, MVT::i32);
}
/// getI8Imm - Return a target constant with the specified value, of type
/// i8.
inline SDValue getI8Imm(unsigned Imm) {
- return CurDAG->getTargetConstant(Imm, EVT::i8);
+ return CurDAG->getTargetConstant(Imm, MVT::i8);
}
/// getI16Imm - Return a target constant with the specified value, of type
/// i16.
inline SDValue getI16Imm(unsigned Imm) {
- return CurDAG->getTargetConstant(Imm, EVT::i16);
+ return CurDAG->getTargetConstant(Imm, MVT::i16);
}
/// getI32Imm - Return a target constant with the specified value, of type
/// i32.
inline SDValue getI32Imm(unsigned Imm) {
- return CurDAG->getTargetConstant(Imm, EVT::i32);
+ return CurDAG->getTargetConstant(Imm, MVT::i32);
}
/// getGlobalBaseReg - Return an SDNode that returns the value of
Ops.push_back(Chain.getOperand(i));
SDValue NewChain =
CurDAG->getNode(ISD::TokenFactor, Load.getDebugLoc(),
- EVT::Other, &Ops[0], Ops.size());
+ MVT::Other, &Ops[0], Ops.size());
Ops.clear();
Ops.push_back(NewChain);
}
}
if (N.getOpcode() == X86ISD::WrapperRIP)
- AM.setBaseReg(CurDAG->getRegister(X86::RIP, EVT::i64));
+ AM.setBaseReg(CurDAG->getRegister(X86::RIP, MVT::i64));
return false;
}
@@ -1001,7 +1001,7 @@ bool X86DAGToDAGISel::MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
RHS.getNode()->getOpcode() == ISD::TRUNCATE ||
RHS.getNode()->getOpcode() == ISD::ANY_EXTEND ||
(RHS.getNode()->getOpcode() == ISD::ZERO_EXTEND &&
- RHS.getNode()->getOperand(0).getValueType() == EVT::i32))
+ RHS.getNode()->getOperand(0).getValueType() == MVT::i32))
++Cost;
// If the base is a register with multiple uses, this
// transformation may save a mov.
@@ -1111,13 +1111,13 @@ bool X86DAGToDAGISel::MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
unsigned ScaleLog = 8 - C1->getZExtValue();
if (ScaleLog > 0 && ScaleLog < 4 &&
C2->getZExtValue() == (UINT64_C(0xff) << ScaleLog)) {
- SDValue Eight = CurDAG->getConstant(8, EVT::i8);
+ SDValue Eight = CurDAG->getConstant(8, MVT::i8);
SDValue Mask = CurDAG->getConstant(0xff, N.getValueType());
SDValue Srl = CurDAG->getNode(ISD::SRL, dl, N.getValueType(),
X, Eight);
SDValue And = CurDAG->getNode(ISD::AND, dl, N.getValueType(),
Srl, Mask);
- SDValue ShlCount = CurDAG->getConstant(ScaleLog, EVT::i8);
+ SDValue ShlCount = CurDAG->getConstant(ScaleLog, MVT::i8);
SDValue Shl = CurDAG->getNode(ISD::SHL, dl, N.getValueType(),
And, ShlCount);
// Set AM.Segment to prevent MatchAddress from using one. LEA doesn't support
// segments.
SDValue Copy = AM.Segment;
- SDValue T = CurDAG->getRegister(0, EVT::i32);
+ SDValue T = CurDAG->getRegister(0, MVT::i32);
AM.Segment = T;
if (MatchAddress(N, AM))
return false;
@@ -1400,11 +1400,11 @@ bool X86DAGToDAGISel::SelectTLSADDRAddr(SDValue Op, SDValue N, SDValue &Base,
AM.Base.Reg = CurDAG->getRegister(0, N.getValueType());
AM.SymbolFlags = GA->getTargetFlags();
- if (N.getValueType() == EVT::i32) {
+ if (N.getValueType() == MVT::i32) {
AM.Scale = 1;
- AM.IndexReg = CurDAG->getRegister(X86::EBX, EVT::i32);
+ AM.IndexReg = CurDAG->getRegister(X86::EBX, MVT::i32);
} else {
- AM.IndexReg = CurDAG->getRegister(0, EVT::i64);
+ AM.IndexReg = CurDAG->getRegister(0, MVT::i64);
}
SDValue Segment;
static SDNode *FindCallStartFromCall(SDNode *Node) {
if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
- assert(Node->getOperand(0).getValueType() == EVT::Other &&
+ assert(Node->getOperand(0).getValueType() == MVT::Other &&
"Node doesn't have a token chain argument!");
return FindCallStartFromCall(Node->getOperand(0).getNode());
}
SDValue LSI = Node->getOperand(4); // MemOperand
const SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, In2L, In2H, LSI, Chain};
return CurDAG->getTargetNode(Opc, Node->getDebugLoc(),
- EVT::i32, EVT::i32, EVT::Other, Ops,
+ MVT::i32, MVT::i32, MVT::Other, Ops,
array_lengthof(Ops));
}
}
unsigned Opc = 0;
- switch (NVT.getSimpleVT()) {
+ switch (NVT.getSimpleVT().SimpleTy) {
default: return 0;
- case EVT::i8:
+ case MVT::i8:
if (isInc)
Opc = X86::LOCK_INC8m;
else if (isDec)
Opc = X86::LOCK_ADD8mr;
}
break;
- case EVT::i16:
+ case MVT::i16:
if (isInc)
Opc = X86::LOCK_INC16m;
else if (isDec)
Opc = X86::LOCK_ADD16mr;
}
break;
- case EVT::i32:
+ case MVT::i32:
if (isInc)
Opc = X86::LOCK_INC32m;
else if (isDec)
Opc = X86::LOCK_ADD32mr;
}
break;
- case EVT::i64:
+ case MVT::i64:
if (isInc)
Opc = X86::LOCK_INC64m;
else if (isDec)
SDValue MemOp = CurDAG->getMemOperand(cast<MemSDNode>(Node)->getMemOperand());
if (isInc || isDec) {
SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, MemOp, Chain };
- SDValue Ret = SDValue(CurDAG->getTargetNode(Opc, dl, EVT::Other, Ops, 7), 0);
+ SDValue Ret = SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 7), 0);
SDValue RetVals[] = { Undef, Ret };
return CurDAG->getMergeValues(RetVals, 2, dl).getNode();
} else {
SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Val, MemOp, Chain };
- SDValue Ret = SDValue(CurDAG->getTargetNode(Opc, dl, EVT::Other, Ops, 8), 0);
+ SDValue Ret = SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 8), 0);
SDValue RetVals[] = { Undef, Ret };
return CurDAG->getMergeValues(RetVals, 2, dl).getNode();
}
bool isSigned = Opcode == ISD::SMUL_LOHI;
if (!isSigned) {
- switch (NVT.getSimpleVT()) {
+ switch (NVT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unsupported VT!");
- case EVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break;
- case EVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break;
- case EVT::i32: Opc = X86::MUL32r; MOpc = X86::MUL32m; break;
- case EVT::i64: Opc = X86::MUL64r; MOpc = X86::MUL64m; break;
+ case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break;
+ case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break;
+ case MVT::i32: Opc = X86::MUL32r; MOpc = X86::MUL32m; break;
+ case MVT::i64: Opc = X86::MUL64r; MOpc = X86::MUL64m; break;
}
} else {
- switch (NVT.getSimpleVT()) {
+ switch (NVT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unsupported VT!");
- case EVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break;
- case EVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break;
- case EVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break;
- case EVT::i64: Opc = X86::IMUL64r; MOpc = X86::IMUL64m; break;
+ case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break;
+ case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break;
+ case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break;
+ case MVT::i64: Opc = X86::IMUL64r; MOpc = X86::IMUL64m; break;
}
}
unsigned LoReg, HiReg;
- switch (NVT.getSimpleVT()) {
+ switch (NVT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unsupported VT!");
- case EVT::i8: LoReg = X86::AL; HiReg = X86::AH; break;
- case EVT::i16: LoReg = X86::AX; HiReg = X86::DX; break;
- case EVT::i32: LoReg = X86::EAX; HiReg = X86::EDX; break;
- case EVT::i64: LoReg = X86::RAX; HiReg = X86::RDX; break;
+ case MVT::i8: LoReg = X86::AL; HiReg = X86::AH; break;
+ case MVT::i16: LoReg = X86::AX; HiReg = X86::DX; break;
+ case MVT::i32: LoReg = X86::EAX; HiReg = X86::EDX; break;
+ case MVT::i64: LoReg = X86::RAX; HiReg = X86::RDX; break;
}
SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
InFlag };
SDNode *CNode =
- CurDAG->getTargetNode(MOpc, dl, EVT::Other, EVT::Flag, Ops,
+ CurDAG->getTargetNode(MOpc, dl, MVT::Other, MVT::Flag, Ops,
array_lengthof(Ops));
InFlag = SDValue(CNode, 1);
// Update the chain.
ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
} else {
InFlag =
- SDValue(CurDAG->getTargetNode(Opc, dl, EVT::Flag, N1, InFlag), 0);
+ SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Flag, N1, InFlag), 0);
}
// Copy the low half of the result, if it is needed.
// Prevent use of AH in a REX instruction by referencing AX instead.
// Shift it down 8 bits.
Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
- X86::AX, EVT::i16, InFlag);
+ X86::AX, MVT::i16, InFlag);
InFlag = Result.getValue(2);
- Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, dl, EVT::i16,
+ Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, dl, MVT::i16,
Result,
- CurDAG->getTargetConstant(8, EVT::i8)), 0);
+ CurDAG->getTargetConstant(8, MVT::i8)), 0);
// Then truncate it down to i8.
- SDValue SRIdx = CurDAG->getTargetConstant(X86::SUBREG_8BIT, EVT::i32);
+ SDValue SRIdx = CurDAG->getTargetConstant(X86::SUBREG_8BIT, MVT::i32);
Result = SDValue(CurDAG->getTargetNode(X86::EXTRACT_SUBREG, dl,
- EVT::i8, Result, SRIdx), 0);
+ MVT::i8, Result, SRIdx), 0);
} else {
Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
HiReg, NVT, InFlag);
bool isSigned = Opcode == ISD::SDIVREM;
if (!isSigned) {
- switch (NVT.getSimpleVT()) {
+ switch (NVT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unsupported VT!");
- case EVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break;
- case EVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break;
- case EVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break;
- case EVT::i64: Opc = X86::DIV64r; MOpc = X86::DIV64m; break;
+ case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break;
+ case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break;
+ case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break;
+ case MVT::i64: Opc = X86::DIV64r; MOpc = X86::DIV64m; break;
}
} else {
- switch (NVT.getSimpleVT()) {
+ switch (NVT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unsupported VT!");
- case EVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break;
- case EVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break;
- case EVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break;
- case EVT::i64: Opc = X86::IDIV64r; MOpc = X86::IDIV64m; break;
+ case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break;
+ case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break;
+ case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break;
+ case MVT::i64: Opc = X86::IDIV64r; MOpc = X86::IDIV64m; break;
}
}
unsigned LoReg, HiReg;
unsigned ClrOpcode, SExtOpcode;
- switch (NVT.getSimpleVT()) {
+ switch (NVT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unsupported VT!");
- case EVT::i8:
+ case MVT::i8:
LoReg = X86::AL; HiReg = X86::AH;
ClrOpcode = 0;
SExtOpcode = X86::CBW;
break;
- case EVT::i16:
+ case MVT::i16:
LoReg = X86::AX; HiReg = X86::DX;
ClrOpcode = X86::MOV16r0;
SExtOpcode = X86::CWD;
break;
- case EVT::i32:
+ case MVT::i32:
LoReg = X86::EAX; HiReg = X86::EDX;
ClrOpcode = X86::MOV32r0;
SExtOpcode = X86::CDQ;
break;
- case EVT::i64:
+ case MVT::i64:
LoReg = X86::RAX; HiReg = X86::RDX;
ClrOpcode = ~0U; // NOT USED.
SExtOpcode = X86::CQO;
bool signBitIsZero = CurDAG->SignBitIsZero(N0);
SDValue InFlag;
- if (NVT == EVT::i8 && (!isSigned || signBitIsZero)) {
+ if (NVT == MVT::i8 && (!isSigned || signBitIsZero)) {
// Special case for div8, just use a move with zero extension to AX to
// clear the upper 8 bits (AH).
SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Move, Chain;
if (TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N0.getOperand(0) };
Move =
- SDValue(CurDAG->getTargetNode(X86::MOVZX16rm8, dl, EVT::i16,
- EVT::Other, Ops,
+ SDValue(CurDAG->getTargetNode(X86::MOVZX16rm8, dl, MVT::i16,
+ MVT::Other, Ops,
array_lengthof(Ops)), 0);
Chain = Move.getValue(1);
ReplaceUses(N0.getValue(1), Chain);
} else {
Move =
- SDValue(CurDAG->getTargetNode(X86::MOVZX16rr8, dl, EVT::i16, N0),0);
+ SDValue(CurDAG->getTargetNode(X86::MOVZX16rr8, dl, MVT::i16, N0),0);
Chain = CurDAG->getEntryNode();
}
Chain = CurDAG->getCopyToReg(Chain, dl, X86::AX, Move, SDValue());
if (isSigned && !signBitIsZero) {
// Sign extend the low part into the high part.
InFlag =
- SDValue(CurDAG->getTargetNode(SExtOpcode, dl, EVT::Flag, InFlag),0);
+ SDValue(CurDAG->getTargetNode(SExtOpcode, dl, MVT::Flag, InFlag),0);
} else {
// Zero out the high part, effectively zero extending the input.
SDValue ClrNode;
- if (NVT.getSimpleVT() == EVT::i64) {
- ClrNode = SDValue(CurDAG->getTargetNode(X86::MOV32r0, dl, EVT::i32),
+ if (NVT.getSimpleVT() == MVT::i64) {
+ ClrNode = SDValue(CurDAG->getTargetNode(X86::MOV32r0, dl, MVT::i32),
0);
// We just did a 32-bit clear, insert it into a 64-bit register to
// clear the whole 64-bit reg.
SDValue Undef =
SDValue(CurDAG->getTargetNode(TargetInstrInfo::IMPLICIT_DEF,
- dl, EVT::i64), 0);
+ dl, MVT::i64), 0);
SDValue SubRegNo =
- CurDAG->getTargetConstant(X86::SUBREG_32BIT, EVT::i32);
+ CurDAG->getTargetConstant(X86::SUBREG_32BIT, MVT::i32);
ClrNode =
SDValue(CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl,
- EVT::i64, Undef, ClrNode, SubRegNo),
+ MVT::i64, Undef, ClrNode, SubRegNo),
0);
} else {
ClrNode = SDValue(CurDAG->getTargetNode(ClrOpcode, dl, NVT), 0);
SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
InFlag };
SDNode *CNode =
- CurDAG->getTargetNode(MOpc, dl, EVT::Other, EVT::Flag, Ops,
+ CurDAG->getTargetNode(MOpc, dl, MVT::Other, MVT::Flag, Ops,
array_lengthof(Ops));
InFlag = SDValue(CNode, 1);
// Update the chain.
ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
} else {
InFlag =
- SDValue(CurDAG->getTargetNode(Opc, dl, EVT::Flag, N1, InFlag), 0);
+ SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Flag, N1, InFlag), 0);
}
// Copy the division (low) result, if it is needed.
// Prevent use of AH in a REX instruction by referencing AX instead.
// Shift it down 8 bits.
Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
- X86::AX, EVT::i16, InFlag);
+ X86::AX, MVT::i16, InFlag);
InFlag = Result.getValue(2);
- Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, dl, EVT::i16,
+ Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, dl, MVT::i16,
Result,
- CurDAG->getTargetConstant(8, EVT::i8)),
+ CurDAG->getTargetConstant(8, MVT::i8)),
0);
// Then truncate it down to i8.
- SDValue SRIdx = CurDAG->getTargetConstant(X86::SUBREG_8BIT, EVT::i32);
+ SDValue SRIdx = CurDAG->getTargetConstant(X86::SUBREG_8BIT, MVT::i32);
Result = SDValue(CurDAG->getTargetNode(X86::EXTRACT_SUBREG, dl,
- EVT::i8, Result, SRIdx), 0);
+ MVT::i8, Result, SRIdx), 0);
} else {
Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
HiReg, NVT, InFlag);
TLI.getPointerTy());
SDValue Ops[] = { Tmp1, Tmp2, Chain };
return CurDAG->getTargetNode(TargetInstrInfo::DECLARE, dl,
- EVT::Other, Ops,
+ MVT::Other, Ops,
array_lengthof(Ops));
}
}
index 855167360fa7e825a838f8e8a4520580d37073ba..02392a38ec6b15c77dd91763698a8bcb8d1db4c8 100644 (file)
// Set up the TargetLowering object.
// X86 is weird, it always uses i8 for shift amounts and setcc results.
- setShiftAmountType(EVT::i8);
+ setShiftAmountType(MVT::i8);
setBooleanContents(ZeroOrOneBooleanContent);
setSchedulingPreference(SchedulingForRegPressure);
setStackPointerRegisterToSaveRestore(X86StackPtr);
}
// Set up the register classes.
- addRegisterClass(EVT::i8, X86::GR8RegisterClass);
- addRegisterClass(EVT::i16, X86::GR16RegisterClass);
- addRegisterClass(EVT::i32, X86::GR32RegisterClass);
+ addRegisterClass(MVT::i8, X86::GR8RegisterClass);
+ addRegisterClass(MVT::i16, X86::GR16RegisterClass);
+ addRegisterClass(MVT::i32, X86::GR32RegisterClass);
if (Subtarget->is64Bit())
- addRegisterClass(EVT::i64, X86::GR64RegisterClass);
+ addRegisterClass(MVT::i64, X86::GR64RegisterClass);
- setLoadExtAction(ISD::SEXTLOAD, EVT::i1, Promote);
+ setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
// We don't accept any truncstore of integer registers.
- setTruncStoreAction(EVT::i64, EVT::i32, Expand);
- setTruncStoreAction(EVT::i64, EVT::i16, Expand);
- setTruncStoreAction(EVT::i64, EVT::i8 , Expand);
- setTruncStoreAction(EVT::i32, EVT::i16, Expand);
- setTruncStoreAction(EVT::i32, EVT::i8 , Expand);
- setTruncStoreAction(EVT::i16, EVT::i8, Expand);
+ setTruncStoreAction(MVT::i64, MVT::i32, Expand);
+ setTruncStoreAction(MVT::i64, MVT::i16, Expand);
+ setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
+ setTruncStoreAction(MVT::i32, MVT::i16, Expand);
+ setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
+ setTruncStoreAction(MVT::i16, MVT::i8, Expand);
// SETOEQ and SETUNE require checking two conditions.
- setCondCodeAction(ISD::SETOEQ, EVT::f32, Expand);
- setCondCodeAction(ISD::SETOEQ, EVT::f64, Expand);
- setCondCodeAction(ISD::SETOEQ, EVT::f80, Expand);
- setCondCodeAction(ISD::SETUNE, EVT::f32, Expand);
- setCondCodeAction(ISD::SETUNE, EVT::f64, Expand);
- setCondCodeAction(ISD::SETUNE, EVT::f80, Expand);
+ setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
+ setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
+ setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
+ setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
+ setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
+ setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
// Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
// operation.
- setOperationAction(ISD::UINT_TO_FP , EVT::i1 , Promote);
- setOperationAction(ISD::UINT_TO_FP , EVT::i8 , Promote);
- setOperationAction(ISD::UINT_TO_FP , EVT::i16 , Promote);
+ setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
+ setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
+ setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
if (Subtarget->is64Bit()) {
- setOperationAction(ISD::UINT_TO_FP , EVT::i32 , Promote);
- setOperationAction(ISD::UINT_TO_FP , EVT::i64 , Expand);
+ setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
+ setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
} else if (!UseSoftFloat) {
if (X86ScalarSSEf64) {
// We have an impenetrably clever algorithm for ui64->double only.
- setOperationAction(ISD::UINT_TO_FP , EVT::i64 , Custom);
+ setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
}
// We have an algorithm for SSE2, and we turn this into a 64-bit
// FILD for other targets.
- setOperationAction(ISD::UINT_TO_FP , EVT::i32 , Custom);
+ setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
}
// Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
// this operation.
- setOperationAction(ISD::SINT_TO_FP , EVT::i1 , Promote);
- setOperationAction(ISD::SINT_TO_FP , EVT::i8 , Promote);
+ setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
+ setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
if (!UseSoftFloat) {
// SSE has no i16 to fp conversion, only i32
if (X86ScalarSSEf32) {
- setOperationAction(ISD::SINT_TO_FP , EVT::i16 , Promote);
+ setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
// f32 and f64 cases are Legal, f80 case is not
- setOperationAction(ISD::SINT_TO_FP , EVT::i32 , Custom);
+ setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
} else {
- setOperationAction(ISD::SINT_TO_FP , EVT::i16 , Custom);
- setOperationAction(ISD::SINT_TO_FP , EVT::i32 , Custom);
+ setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
+ setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
}
} else {
- setOperationAction(ISD::SINT_TO_FP , EVT::i16 , Promote);
- setOperationAction(ISD::SINT_TO_FP , EVT::i32 , Promote);
+ setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
+ setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
}
// In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
// are Legal, f80 is custom lowered.
- setOperationAction(ISD::FP_TO_SINT , EVT::i64 , Custom);
- setOperationAction(ISD::SINT_TO_FP , EVT::i64 , Custom);
+ setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
+ setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
// Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
// this operation.
- setOperationAction(ISD::FP_TO_SINT , EVT::i1 , Promote);
- setOperationAction(ISD::FP_TO_SINT , EVT::i8 , Promote);
+ setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
+ setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
if (X86ScalarSSEf32) {
- setOperationAction(ISD::FP_TO_SINT , EVT::i16 , Promote);
+ setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
// f32 and f64 cases are Legal, f80 case is not
- setOperationAction(ISD::FP_TO_SINT , EVT::i32 , Custom);
+ setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
} else {
- setOperationAction(ISD::FP_TO_SINT , EVT::i16 , Custom);
- setOperationAction(ISD::FP_TO_SINT , EVT::i32 , Custom);
+ setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
+ setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
}
// Handle FP_TO_UINT by promoting the destination to a larger signed
// conversion.
- setOperationAction(ISD::FP_TO_UINT , EVT::i1 , Promote);
- setOperationAction(ISD::FP_TO_UINT , EVT::i8 , Promote);
- setOperationAction(ISD::FP_TO_UINT , EVT::i16 , Promote);
+ setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
+ setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
+ setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
if (Subtarget->is64Bit()) {
- setOperationAction(ISD::FP_TO_UINT , EVT::i64 , Expand);
- setOperationAction(ISD::FP_TO_UINT , EVT::i32 , Promote);
+ setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
+ setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
} else if (!UseSoftFloat) {
if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
// Expand FP_TO_UINT into a select.
// FIXME: We would like to use a Custom expander here eventually to do
// the optimal thing for SSE vs. the default expansion in the legalizer.
- setOperationAction(ISD::FP_TO_UINT , EVT::i32 , Expand);
+ setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
else
// With SSE3 we can use fisttpll to convert to a signed i64; without
// SSE, we're stuck with a fistpll.
- setOperationAction(ISD::FP_TO_UINT , EVT::i32 , Custom);
+ setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
}
// TODO: when we have SSE, these could be more efficient, by using movd/movq.
if (!X86ScalarSSEf64) {
- setOperationAction(ISD::BIT_CONVERT , EVT::f32 , Expand);
- setOperationAction(ISD::BIT_CONVERT , EVT::i32 , Expand);
+ setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
+ setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
}
// Scalar integer divide and remainder are lowered to use operations that
// (low) operations are left as Legal, as there are single-result
// instructions for this in x86. Using the two-result multiply instructions
// when both high and low results are needed must be arranged by dagcombine.
- setOperationAction(ISD::MULHS , EVT::i8 , Expand);
- setOperationAction(ISD::MULHU , EVT::i8 , Expand);
- setOperationAction(ISD::SDIV , EVT::i8 , Expand);
- setOperationAction(ISD::UDIV , EVT::i8 , Expand);
- setOperationAction(ISD::SREM , EVT::i8 , Expand);
- setOperationAction(ISD::UREM , EVT::i8 , Expand);
- setOperationAction(ISD::MULHS , EVT::i16 , Expand);
- setOperationAction(ISD::MULHU , EVT::i16 , Expand);
- setOperationAction(ISD::SDIV , EVT::i16 , Expand);
- setOperationAction(ISD::UDIV , EVT::i16 , Expand);
- setOperationAction(ISD::SREM , EVT::i16 , Expand);
- setOperationAction(ISD::UREM , EVT::i16 , Expand);
- setOperationAction(ISD::MULHS , EVT::i32 , Expand);
- setOperationAction(ISD::MULHU , EVT::i32 , Expand);
- setOperationAction(ISD::SDIV , EVT::i32 , Expand);
- setOperationAction(ISD::UDIV , EVT::i32 , Expand);
- setOperationAction(ISD::SREM , EVT::i32 , Expand);
- setOperationAction(ISD::UREM , EVT::i32 , Expand);
- setOperationAction(ISD::MULHS , EVT::i64 , Expand);
- setOperationAction(ISD::MULHU , EVT::i64 , Expand);
- setOperationAction(ISD::SDIV , EVT::i64 , Expand);
- setOperationAction(ISD::UDIV , EVT::i64 , Expand);
- setOperationAction(ISD::SREM , EVT::i64 , Expand);
- setOperationAction(ISD::UREM , EVT::i64 , Expand);
-
- setOperationAction(ISD::BR_JT , EVT::Other, Expand);
- setOperationAction(ISD::BRCOND , EVT::Other, Custom);
- setOperationAction(ISD::BR_CC , EVT::Other, Expand);
- setOperationAction(ISD::SELECT_CC , EVT::Other, Expand);
+ setOperationAction(ISD::MULHS , MVT::i8 , Expand);
+ setOperationAction(ISD::MULHU , MVT::i8 , Expand);
+ setOperationAction(ISD::SDIV , MVT::i8 , Expand);
+ setOperationAction(ISD::UDIV , MVT::i8 , Expand);
+ setOperationAction(ISD::SREM , MVT::i8 , Expand);
+ setOperationAction(ISD::UREM , MVT::i8 , Expand);
+ setOperationAction(ISD::MULHS , MVT::i16 , Expand);
+ setOperationAction(ISD::MULHU , MVT::i16 , Expand);
+ setOperationAction(ISD::SDIV , MVT::i16 , Expand);
+ setOperationAction(ISD::UDIV , MVT::i16 , Expand);
+ setOperationAction(ISD::SREM , MVT::i16 , Expand);
+ setOperationAction(ISD::UREM , MVT::i16 , Expand);
+ setOperationAction(ISD::MULHS , MVT::i32 , Expand);
+ setOperationAction(ISD::MULHU , MVT::i32 , Expand);
+ setOperationAction(ISD::SDIV , MVT::i32 , Expand);
+ setOperationAction(ISD::UDIV , MVT::i32 , Expand);
+ setOperationAction(ISD::SREM , MVT::i32 , Expand);
+ setOperationAction(ISD::UREM , MVT::i32 , Expand);
+ setOperationAction(ISD::MULHS , MVT::i64 , Expand);
+ setOperationAction(ISD::MULHU , MVT::i64 , Expand);
+ setOperationAction(ISD::SDIV , MVT::i64 , Expand);
+ setOperationAction(ISD::UDIV , MVT::i64 , Expand);
+ setOperationAction(ISD::SREM , MVT::i64 , Expand);
+ setOperationAction(ISD::UREM , MVT::i64 , Expand);
+
+ setOperationAction(ISD::BR_JT , MVT::Other, Expand);
+ setOperationAction(ISD::BRCOND , MVT::Other, Custom);
+ setOperationAction(ISD::BR_CC , MVT::Other, Expand);
+ setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
if (Subtarget->is64Bit())
- setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i32, Legal);
- setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i16 , Legal);
- setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i8 , Legal);
- setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i1 , Expand);
- setOperationAction(ISD::FP_ROUND_INREG , EVT::f32 , Expand);
- setOperationAction(ISD::FREM , EVT::f32 , Expand);
- setOperationAction(ISD::FREM , EVT::f64 , Expand);
- setOperationAction(ISD::FREM , EVT::f80 , Expand);
- setOperationAction(ISD::FLT_ROUNDS_ , EVT::i32 , Custom);
-
- setOperationAction(ISD::CTPOP , EVT::i8 , Expand);
- setOperationAction(ISD::CTTZ , EVT::i8 , Custom);
- setOperationAction(ISD::CTLZ , EVT::i8 , Custom);
- setOperationAction(ISD::CTPOP , EVT::i16 , Expand);
- setOperationAction(ISD::CTTZ , EVT::i16 , Custom);
- setOperationAction(ISD::CTLZ , EVT::i16 , Custom);
- setOperationAction(ISD::CTPOP , EVT::i32 , Expand);
- setOperationAction(ISD::CTTZ , EVT::i32 , Custom);
- setOperationAction(ISD::CTLZ , EVT::i32 , Custom);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
+ setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
+ setOperationAction(ISD::FREM , MVT::f32 , Expand);
+ setOperationAction(ISD::FREM , MVT::f64 , Expand);
+ setOperationAction(ISD::FREM , MVT::f80 , Expand);
+ setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
+
+ setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
+ setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
+ setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
+ setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
+ setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
+ setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
+ setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
+ setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
+ setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
if (Subtarget->is64Bit()) {
- setOperationAction(ISD::CTPOP , EVT::i64 , Expand);
- setOperationAction(ISD::CTTZ , EVT::i64 , Custom);
- setOperationAction(ISD::CTLZ , EVT::i64 , Custom);
+ setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
+ setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
+ setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
}
- setOperationAction(ISD::READCYCLECOUNTER , EVT::i64 , Custom);
- setOperationAction(ISD::BSWAP , EVT::i16 , Expand);
+ setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
+ setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
// These should be promoted to a larger select which is supported.
- setOperationAction(ISD::SELECT , EVT::i1 , Promote);
- setOperationAction(ISD::SELECT , EVT::i8 , Promote);
+ setOperationAction(ISD::SELECT , MVT::i1 , Promote);
+ setOperationAction(ISD::SELECT , MVT::i8 , Promote);
// X86 wants to expand cmov itself.
- setOperationAction(ISD::SELECT , EVT::i16 , Custom);
- setOperationAction(ISD::SELECT , EVT::i32 , Custom);
- setOperationAction(ISD::SELECT , EVT::f32 , Custom);
- setOperationAction(ISD::SELECT , EVT::f64 , Custom);
- setOperationAction(ISD::SELECT , EVT::f80 , Custom);
- setOperationAction(ISD::SETCC , EVT::i8 , Custom);
- setOperationAction(ISD::SETCC , EVT::i16 , Custom);
- setOperationAction(ISD::SETCC , EVT::i32 , Custom);
- setOperationAction(ISD::SETCC , EVT::f32 , Custom);
- setOperationAction(ISD::SETCC , EVT::f64 , Custom);
- setOperationAction(ISD::SETCC , EVT::f80 , Custom);
+ setOperationAction(ISD::SELECT , MVT::i16 , Custom);
+ setOperationAction(ISD::SELECT , MVT::i32 , Custom);
+ setOperationAction(ISD::SELECT , MVT::f32 , Custom);
+ setOperationAction(ISD::SELECT , MVT::f64 , Custom);
+ setOperationAction(ISD::SELECT , MVT::f80 , Custom);
+ setOperationAction(ISD::SETCC , MVT::i8 , Custom);
+ setOperationAction(ISD::SETCC , MVT::i16 , Custom);
+ setOperationAction(ISD::SETCC , MVT::i32 , Custom);
+ setOperationAction(ISD::SETCC , MVT::f32 , Custom);
+ setOperationAction(ISD::SETCC , MVT::f64 , Custom);
+ setOperationAction(ISD::SETCC , MVT::f80 , Custom);
if (Subtarget->is64Bit()) {
- setOperationAction(ISD::SELECT , EVT::i64 , Custom);
- setOperationAction(ISD::SETCC , EVT::i64 , Custom);
+ setOperationAction(ISD::SELECT , MVT::i64 , Custom);
+ setOperationAction(ISD::SETCC , MVT::i64 , Custom);
}
- setOperationAction(ISD::EH_RETURN , EVT::Other, Custom);
+ setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
// Darwin ABI issue.
- setOperationAction(ISD::ConstantPool , EVT::i32 , Custom);
- setOperationAction(ISD::JumpTable , EVT::i32 , Custom);
- setOperationAction(ISD::GlobalAddress , EVT::i32 , Custom);
- setOperationAction(ISD::GlobalTLSAddress, EVT::i32 , Custom);
+ setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
+ setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
+ setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
+ setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
if (Subtarget->is64Bit())
- setOperationAction(ISD::GlobalTLSAddress, EVT::i64, Custom);
- setOperationAction(ISD::ExternalSymbol , EVT::i32 , Custom);
+ setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
+ setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
if (Subtarget->is64Bit()) {
- setOperationAction(ISD::ConstantPool , EVT::i64 , Custom);
- setOperationAction(ISD::JumpTable , EVT::i64 , Custom);
- setOperationAction(ISD::GlobalAddress , EVT::i64 , Custom);
- setOperationAction(ISD::ExternalSymbol, EVT::i64 , Custom);
+ setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
+ setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
+ setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
+ setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
}
// 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
- setOperationAction(ISD::SHL_PARTS , EVT::i32 , Custom);
- setOperationAction(ISD::SRA_PARTS , EVT::i32 , Custom);
- setOperationAction(ISD::SRL_PARTS , EVT::i32 , Custom);
+ setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
+ setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
+ setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
if (Subtarget->is64Bit()) {
- setOperationAction(ISD::SHL_PARTS , EVT::i64 , Custom);
- setOperationAction(ISD::SRA_PARTS , EVT::i64 , Custom);
- setOperationAction(ISD::SRL_PARTS , EVT::i64 , Custom);
+ setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
+ setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
+ setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
}
if (Subtarget->hasSSE1())
- setOperationAction(ISD::PREFETCH , EVT::Other, Legal);
+ setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
if (!Subtarget->hasSSE2())
- setOperationAction(ISD::MEMBARRIER , EVT::Other, Expand);
+ setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
// Expand certain atomics
- setOperationAction(ISD::ATOMIC_CMP_SWAP, EVT::i8, Custom);
- setOperationAction(ISD::ATOMIC_CMP_SWAP, EVT::i16, Custom);
- setOperationAction(ISD::ATOMIC_CMP_SWAP, EVT::i32, Custom);
- setOperationAction(ISD::ATOMIC_CMP_SWAP, EVT::i64, Custom);
+ setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom);
+ setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom);
+ setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
+ setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
- setOperationAction(ISD::ATOMIC_LOAD_SUB, EVT::i8, Custom);
- setOperationAction(ISD::ATOMIC_LOAD_SUB, EVT::i16, Custom);
- setOperationAction(ISD::ATOMIC_LOAD_SUB, EVT::i32, Custom);
- setOperationAction(ISD::ATOMIC_LOAD_SUB, EVT::i64, Custom);
+ setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom);
+ setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom);
+ setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
+ setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
if (!Subtarget->is64Bit()) {
- setOperationAction(ISD::ATOMIC_LOAD_ADD, EVT::i64, Custom);
- setOperationAction(ISD::ATOMIC_LOAD_SUB, EVT::i64, Custom);
- setOperationAction(ISD::ATOMIC_LOAD_AND, EVT::i64, Custom);
- setOperationAction(ISD::ATOMIC_LOAD_OR, EVT::i64, Custom);
- setOperationAction(ISD::ATOMIC_LOAD_XOR, EVT::i64, Custom);
- setOperationAction(ISD::ATOMIC_LOAD_NAND, EVT::i64, Custom);
- setOperationAction(ISD::ATOMIC_SWAP, EVT::i64, Custom);
+ setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
+ setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
+ setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
+ setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
+ setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
+ setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
+ setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
}
// Use the default ISD::DBG_STOPPOINT, ISD::DECLARE expansion.
- setOperationAction(ISD::DBG_STOPPOINT, EVT::Other, Expand);
+ setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
// FIXME - use subtarget debug flags
if (!Subtarget->isTargetDarwin() &&
!Subtarget->isTargetELF() &&
!Subtarget->isTargetCygMing()) {
- setOperationAction(ISD::DBG_LABEL, EVT::Other, Expand);
- setOperationAction(ISD::EH_LABEL, EVT::Other, Expand);
+ setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
+ setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
}
- setOperationAction(ISD::EXCEPTIONADDR, EVT::i64, Expand);
- setOperationAction(ISD::EHSELECTION, EVT::i64, Expand);
- setOperationAction(ISD::EXCEPTIONADDR, EVT::i32, Expand);
- setOperationAction(ISD::EHSELECTION, EVT::i32, Expand);
+ setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
+ setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
+ setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
+ setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
if (Subtarget->is64Bit()) {
setExceptionPointerRegister(X86::RAX);
setExceptionSelectorRegister(X86::RDX);
setExceptionPointerRegister(X86::EAX);
setExceptionSelectorRegister(X86::EDX);
}
- setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, EVT::i32, Custom);
- setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, EVT::i64, Custom);
+ setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
+ setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
- setOperationAction(ISD::TRAMPOLINE, EVT::Other, Custom);
+ setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
- setOperationAction(ISD::TRAP, EVT::Other, Legal);
+ setOperationAction(ISD::TRAP, MVT::Other, Legal);
// VASTART needs to be custom lowered to use the VarArgsFrameIndex
- setOperationAction(ISD::VASTART , EVT::Other, Custom);
- setOperationAction(ISD::VAEND , EVT::Other, Expand);
+ setOperationAction(ISD::VASTART , MVT::Other, Custom);
+ setOperationAction(ISD::VAEND , MVT::Other, Expand);
if (Subtarget->is64Bit()) {
- setOperationAction(ISD::VAARG , EVT::Other, Custom);
- setOperationAction(ISD::VACOPY , EVT::Other, Custom);
+ setOperationAction(ISD::VAARG , MVT::Other, Custom);
+ setOperationAction(ISD::VACOPY , MVT::Other, Custom);
} else {
- setOperationAction(ISD::VAARG , EVT::Other, Expand);
- setOperationAction(ISD::VACOPY , EVT::Other, Expand);
+ setOperationAction(ISD::VAARG , MVT::Other, Expand);
+ setOperationAction(ISD::VACOPY , MVT::Other, Expand);
}
- setOperationAction(ISD::STACKSAVE, EVT::Other, Expand);
- setOperationAction(ISD::STACKRESTORE, EVT::Other, Expand);
+ setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
+ setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
if (Subtarget->is64Bit())
- setOperationAction(ISD::DYNAMIC_STACKALLOC, EVT::i64, Expand);
+ setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
if (Subtarget->isTargetCygMing())
- setOperationAction(ISD::DYNAMIC_STACKALLOC, EVT::i32, Custom);
+ setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
else
- setOperationAction(ISD::DYNAMIC_STACKALLOC, EVT::i32, Expand);
+ setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
if (!UseSoftFloat && X86ScalarSSEf64) {
// f32 and f64 use SSE.
// Set up the FP register classes.
- addRegisterClass(EVT::f32, X86::FR32RegisterClass);
- addRegisterClass(EVT::f64, X86::FR64RegisterClass);
+ addRegisterClass(MVT::f32, X86::FR32RegisterClass);
+ addRegisterClass(MVT::f64, X86::FR64RegisterClass);
// Use ANDPD to simulate FABS.
- setOperationAction(ISD::FABS , EVT::f64, Custom);
- setOperationAction(ISD::FABS , EVT::f32, Custom);
+ setOperationAction(ISD::FABS , MVT::f64, Custom);
+ setOperationAction(ISD::FABS , MVT::f32, Custom);
// Use XORP to simulate FNEG.
- setOperationAction(ISD::FNEG , EVT::f64, Custom);
- setOperationAction(ISD::FNEG , EVT::f32, Custom);
+ setOperationAction(ISD::FNEG , MVT::f64, Custom);
+ setOperationAction(ISD::FNEG , MVT::f32, Custom);
// Use ANDPD and ORPD to simulate FCOPYSIGN.
- setOperationAction(ISD::FCOPYSIGN, EVT::f64, Custom);
- setOperationAction(ISD::FCOPYSIGN, EVT::f32, Custom);
+ setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
+ setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
// We don't support sin/cos/fmod
- setOperationAction(ISD::FSIN , EVT::f64, Expand);
- setOperationAction(ISD::FCOS , EVT::f64, Expand);
- setOperationAction(ISD::FSIN , EVT::f32, Expand);
- setOperationAction(ISD::FCOS , EVT::f32, Expand);
+ setOperationAction(ISD::FSIN , MVT::f64, Expand);
+ setOperationAction(ISD::FCOS , MVT::f64, Expand);
+ setOperationAction(ISD::FSIN , MVT::f32, Expand);
+ setOperationAction(ISD::FCOS , MVT::f32, Expand);
// Expand FP immediates into loads from the stack, except for the special
// cases we handle.
} else if (!UseSoftFloat && X86ScalarSSEf32) {
// Use SSE for f32, x87 for f64.
// Set up the FP register classes.
- addRegisterClass(EVT::f32, X86::FR32RegisterClass);
- addRegisterClass(EVT::f64, X86::RFP64RegisterClass);
+ addRegisterClass(MVT::f32, X86::FR32RegisterClass);
+ addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
// Use ANDPS to simulate FABS.
- setOperationAction(ISD::FABS , EVT::f32, Custom);
+ setOperationAction(ISD::FABS , MVT::f32, Custom);
// Use XORP to simulate FNEG.
- setOperationAction(ISD::FNEG , EVT::f32, Custom);
+ setOperationAction(ISD::FNEG , MVT::f32, Custom);
- setOperationAction(ISD::UNDEF, EVT::f64, Expand);
+ setOperationAction(ISD::UNDEF, MVT::f64, Expand);
// Use ANDPS and ORPS to simulate FCOPYSIGN.
- setOperationAction(ISD::FCOPYSIGN, EVT::f64, Expand);
- setOperationAction(ISD::FCOPYSIGN, EVT::f32, Custom);
+ setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
+ setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
// We don't support sin/cos/fmod
- setOperationAction(ISD::FSIN , EVT::f32, Expand);
- setOperationAction(ISD::FCOS , EVT::f32, Expand);
+ setOperationAction(ISD::FSIN , MVT::f32, Expand);
+ setOperationAction(ISD::FCOS , MVT::f32, Expand);
// Special cases we handle for FP constants.
addLegalFPImmediate(APFloat(+0.0f)); // xorps
addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
if (!UnsafeFPMath) {
- setOperationAction(ISD::FSIN , EVT::f64 , Expand);
- setOperationAction(ISD::FCOS , EVT::f64 , Expand);
+ setOperationAction(ISD::FSIN , MVT::f64 , Expand);
+ setOperationAction(ISD::FCOS , MVT::f64 , Expand);
}
} else if (!UseSoftFloat) {
// f32 and f64 in x87.
// Set up the FP register classes.
- addRegisterClass(EVT::f64, X86::RFP64RegisterClass);
- addRegisterClass(EVT::f32, X86::RFP32RegisterClass);
+ addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
+ addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
- setOperationAction(ISD::UNDEF, EVT::f64, Expand);
- setOperationAction(ISD::UNDEF, EVT::f32, Expand);
- setOperationAction(ISD::FCOPYSIGN, EVT::f64, Expand);
- setOperationAction(ISD::FCOPYSIGN, EVT::f32, Expand);
+ setOperationAction(ISD::UNDEF, MVT::f64, Expand);
+ setOperationAction(ISD::UNDEF, MVT::f32, Expand);
+ setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
+ setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
if (!UnsafeFPMath) {
- setOperationAction(ISD::FSIN , EVT::f64 , Expand);
- setOperationAction(ISD::FCOS , EVT::f64 , Expand);
+ setOperationAction(ISD::FSIN , MVT::f64 , Expand);
+ setOperationAction(ISD::FCOS , MVT::f64 , Expand);
}
addLegalFPImmediate(APFloat(+0.0)); // FLD0
addLegalFPImmediate(APFloat(+1.0)); // FLD1
// Long double always uses X87.
if (!UseSoftFloat) {
- addRegisterClass(EVT::f80, X86::RFP80RegisterClass);
- setOperationAction(ISD::UNDEF, EVT::f80, Expand);
- setOperationAction(ISD::FCOPYSIGN, EVT::f80, Expand);
+ addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
+ setOperationAction(ISD::UNDEF, MVT::f80, Expand);
+ setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
{
bool ignored;
APFloat TmpFlt(+0.0);
}
if (!UnsafeFPMath) {
- setOperationAction(ISD::FSIN , EVT::f80 , Expand);
- setOperationAction(ISD::FCOS , EVT::f80 , Expand);
+ setOperationAction(ISD::FSIN , MVT::f80 , Expand);
+ setOperationAction(ISD::FCOS , MVT::f80 , Expand);
}
}
// Always use a library call for pow.
- setOperationAction(ISD::FPOW , EVT::f32 , Expand);
- setOperationAction(ISD::FPOW , EVT::f64 , Expand);
- setOperationAction(ISD::FPOW , EVT::f80 , Expand);
+ setOperationAction(ISD::FPOW , MVT::f32 , Expand);
+ setOperationAction(ISD::FPOW , MVT::f64 , Expand);
+ setOperationAction(ISD::FPOW , MVT::f80 , Expand);
- setOperationAction(ISD::FLOG, EVT::f80, Expand);
- setOperationAction(ISD::FLOG2, EVT::f80, Expand);
- setOperationAction(ISD::FLOG10, EVT::f80, Expand);
- setOperationAction(ISD::FEXP, EVT::f80, Expand);
- setOperationAction(ISD::FEXP2, EVT::f80, Expand);
+ setOperationAction(ISD::FLOG, MVT::f80, Expand);
+ setOperationAction(ISD::FLOG2, MVT::f80, Expand);
+ setOperationAction(ISD::FLOG10, MVT::f80, Expand);
+ setOperationAction(ISD::FEXP, MVT::f80, Expand);
+ setOperationAction(ISD::FEXP2, MVT::f80, Expand);
// First set operation action for all vector types to either promote
// (for widening) or expand (for scalarization). Then we will selectively
// turn on ones that can be effectively codegen'd.
- for (unsigned VT = (unsigned)EVT::FIRST_VECTOR_VALUETYPE;
- VT <= (unsigned)EVT::LAST_VECTOR_VALUETYPE; ++VT) {
- setOperationAction(ISD::ADD , (EVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::SUB , (EVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::FADD, (EVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::FNEG, (EVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::FSUB, (EVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::MUL , (EVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::FMUL, (EVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::SDIV, (EVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::UDIV, (EVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::FDIV, (EVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::SREM, (EVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::UREM, (EVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::LOAD, (EVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::VECTOR_SHUFFLE, (EVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::EXTRACT_VECTOR_ELT,(EVT::SimpleValueType)VT,Expand);
- setOperationAction(ISD::EXTRACT_SUBVECTOR,(EVT::SimpleValueType)VT,Expand);
- setOperationAction(ISD::INSERT_VECTOR_ELT,(EVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::FABS, (EVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::FSIN, (EVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::FCOS, (EVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::FREM, (EVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::FPOWI, (EVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::FSQRT, (EVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::FCOPYSIGN, (EVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::SMUL_LOHI, (EVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::UMUL_LOHI, (EVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::SDIVREM, (EVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::UDIVREM, (EVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::FPOW, (EVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::CTPOP, (EVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::CTTZ, (EVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::CTLZ, (EVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::SHL, (EVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::SRA, (EVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::SRL, (EVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::ROTL, (EVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::ROTR, (EVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::BSWAP, (EVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::VSETCC, (EVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::FLOG, (EVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::FLOG2, (EVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::FLOG10, (EVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::FEXP, (EVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::FEXP2, (EVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::FP_TO_UINT, (EVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::FP_TO_SINT, (EVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::UINT_TO_FP, (EVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::SINT_TO_FP, (EVT::SimpleValueType)VT, Expand);
+ for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
+ VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
+ setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
+ setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
+ setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
}
// FIXME: In order to prevent SSE instructions being expanded to MMX ones
// with -msoft-float, disable use of MMX as well.
if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) {
- addRegisterClass(EVT::v8i8, X86::VR64RegisterClass);
- addRegisterClass(EVT::v4i16, X86::VR64RegisterClass);
- addRegisterClass(EVT::v2i32, X86::VR64RegisterClass);
- addRegisterClass(EVT::v2f32, X86::VR64RegisterClass);
- addRegisterClass(EVT::v1i64, X86::VR64RegisterClass);
-
- setOperationAction(ISD::ADD, EVT::v8i8, Legal);
- setOperationAction(ISD::ADD, EVT::v4i16, Legal);
- setOperationAction(ISD::ADD, EVT::v2i32, Legal);
- setOperationAction(ISD::ADD, EVT::v1i64, Legal);
-
- setOperationAction(ISD::SUB, EVT::v8i8, Legal);
- setOperationAction(ISD::SUB, EVT::v4i16, Legal);
- setOperationAction(ISD::SUB, EVT::v2i32, Legal);
- setOperationAction(ISD::SUB, EVT::v1i64, Legal);
-
- setOperationAction(ISD::MULHS, EVT::v4i16, Legal);
- setOperationAction(ISD::MUL, EVT::v4i16, Legal);
-
- setOperationAction(ISD::AND, EVT::v8i8, Promote);
- AddPromotedToType (ISD::AND, EVT::v8i8, EVT::v1i64);
- setOperationAction(ISD::AND, EVT::v4i16, Promote);
- AddPromotedToType (ISD::AND, EVT::v4i16, EVT::v1i64);
- setOperationAction(ISD::AND, EVT::v2i32, Promote);
- AddPromotedToType (ISD::AND, EVT::v2i32, EVT::v1i64);
- setOperationAction(ISD::AND, EVT::v1i64, Legal);
-
- setOperationAction(ISD::OR, EVT::v8i8, Promote);
- AddPromotedToType (ISD::OR, EVT::v8i8, EVT::v1i64);
- setOperationAction(ISD::OR, EVT::v4i16, Promote);
- AddPromotedToType (ISD::OR, EVT::v4i16, EVT::v1i64);
- setOperationAction(ISD::OR, EVT::v2i32, Promote);
- AddPromotedToType (ISD::OR, EVT::v2i32, EVT::v1i64);
- setOperationAction(ISD::OR, EVT::v1i64, Legal);
-
- setOperationAction(ISD::XOR, EVT::v8i8, Promote);
- AddPromotedToType (ISD::XOR, EVT::v8i8, EVT::v1i64);
- setOperationAction(ISD::XOR, EVT::v4i16, Promote);
- AddPromotedToType (ISD::XOR, EVT::v4i16, EVT::v1i64);
- setOperationAction(ISD::XOR, EVT::v2i32, Promote);
- AddPromotedToType (ISD::XOR, EVT::v2i32, EVT::v1i64);
- setOperationAction(ISD::XOR, EVT::v1i64, Legal);
-
- setOperationAction(ISD::LOAD, EVT::v8i8, Promote);
- AddPromotedToType (ISD::LOAD, EVT::v8i8, EVT::v1i64);
- setOperationAction(ISD::LOAD, EVT::v4i16, Promote);
- AddPromotedToType (ISD::LOAD, EVT::v4i16, EVT::v1i64);
- setOperationAction(ISD::LOAD, EVT::v2i32, Promote);
- AddPromotedToType (ISD::LOAD, EVT::v2i32, EVT::v1i64);
- setOperationAction(ISD::LOAD, EVT::v2f32, Promote);
- AddPromotedToType (ISD::LOAD, EVT::v2f32, EVT::v1i64);
- setOperationAction(ISD::LOAD, EVT::v1i64, Legal);
-
- setOperationAction(ISD::BUILD_VECTOR, EVT::v8i8, Custom);
- setOperationAction(ISD::BUILD_VECTOR, EVT::v4i16, Custom);
- setOperationAction(ISD::BUILD_VECTOR, EVT::v2i32, Custom);
- setOperationAction(ISD::BUILD_VECTOR, EVT::v2f32, Custom);
- setOperationAction(ISD::BUILD_VECTOR, EVT::v1i64, Custom);
-
- setOperationAction(ISD::VECTOR_SHUFFLE, EVT::v8i8, Custom);
- setOperationAction(ISD::VECTOR_SHUFFLE, EVT::v4i16, Custom);
- setOperationAction(ISD::VECTOR_SHUFFLE, EVT::v2i32, Custom);
- setOperationAction(ISD::VECTOR_SHUFFLE, EVT::v1i64, Custom);
-
- setOperationAction(ISD::SCALAR_TO_VECTOR, EVT::v2f32, Custom);
- setOperationAction(ISD::SCALAR_TO_VECTOR, EVT::v8i8, Custom);
- setOperationAction(ISD::SCALAR_TO_VECTOR, EVT::v4i16, Custom);
- setOperationAction(ISD::SCALAR_TO_VECTOR, EVT::v1i64, Custom);
-
- setOperationAction(ISD::INSERT_VECTOR_ELT, EVT::v4i16, Custom);
-
- setTruncStoreAction(EVT::v8i16, EVT::v8i8, Expand);
- setOperationAction(ISD::TRUNCATE, EVT::v8i8, Expand);
- setOperationAction(ISD::SELECT, EVT::v8i8, Promote);
- setOperationAction(ISD::SELECT, EVT::v4i16, Promote);
- setOperationAction(ISD::SELECT, EVT::v2i32, Promote);
- setOperationAction(ISD::SELECT, EVT::v1i64, Custom);
- setOperationAction(ISD::VSETCC, EVT::v8i8, Custom);
- setOperationAction(ISD::VSETCC, EVT::v4i16, Custom);
- setOperationAction(ISD::VSETCC, EVT::v2i32, Custom);
+ addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
+ addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
+ addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
+ addRegisterClass(MVT::v2f32, X86::VR64RegisterClass);
+ addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
+
+ setOperationAction(ISD::ADD, MVT::v8i8, Legal);
+ setOperationAction(ISD::ADD, MVT::v4i16, Legal);
+ setOperationAction(ISD::ADD, MVT::v2i32, Legal);
+ setOperationAction(ISD::ADD, MVT::v1i64, Legal);
+
+ setOperationAction(ISD::SUB, MVT::v8i8, Legal);
+ setOperationAction(ISD::SUB, MVT::v4i16, Legal);
+ setOperationAction(ISD::SUB, MVT::v2i32, Legal);
+ setOperationAction(ISD::SUB, MVT::v1i64, Legal);
+
+ setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
+ setOperationAction(ISD::MUL, MVT::v4i16, Legal);
+
+ setOperationAction(ISD::AND, MVT::v8i8, Promote);
+ AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
+ setOperationAction(ISD::AND, MVT::v4i16, Promote);
+ AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
+ setOperationAction(ISD::AND, MVT::v2i32, Promote);
+ AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
+ setOperationAction(ISD::AND, MVT::v1i64, Legal);
+
+ setOperationAction(ISD::OR, MVT::v8i8, Promote);
+ AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
+ setOperationAction(ISD::OR, MVT::v4i16, Promote);
+ AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
+ setOperationAction(ISD::OR, MVT::v2i32, Promote);
+ AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
+ setOperationAction(ISD::OR, MVT::v1i64, Legal);
+
+ setOperationAction(ISD::XOR, MVT::v8i8, Promote);
+ AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
+ setOperationAction(ISD::XOR, MVT::v4i16, Promote);
+ AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
+ setOperationAction(ISD::XOR, MVT::v2i32, Promote);
+ AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
+ setOperationAction(ISD::XOR, MVT::v1i64, Legal);
+
+ setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
+ AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
+ setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
+ AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
+ setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
+ AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
+ setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
+ AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64);
+ setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
+
+ setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
+ setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
+ setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
+ setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom);
+ setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
+
+ setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
+ setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
+ setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
+ setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
+
+ setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom);
+ setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
+ setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
+ setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
+
+ setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
+
+ setTruncStoreAction(MVT::v8i16, MVT::v8i8, Expand);
+ setOperationAction(ISD::TRUNCATE, MVT::v8i8, Expand);
+ setOperationAction(ISD::SELECT, MVT::v8i8, Promote);
+ setOperationAction(ISD::SELECT, MVT::v4i16, Promote);
+ setOperationAction(ISD::SELECT, MVT::v2i32, Promote);
+ setOperationAction(ISD::SELECT, MVT::v1i64, Custom);
+ setOperationAction(ISD::VSETCC, MVT::v8i8, Custom);
+ setOperationAction(ISD::VSETCC, MVT::v4i16, Custom);
+ setOperationAction(ISD::VSETCC, MVT::v2i32, Custom);
}
if (!UseSoftFloat && Subtarget->hasSSE1()) {
- addRegisterClass(EVT::v4f32, X86::VR128RegisterClass);
-
- setOperationAction(ISD::FADD, EVT::v4f32, Legal);
- setOperationAction(ISD::FSUB, EVT::v4f32, Legal);
- setOperationAction(ISD::FMUL, EVT::v4f32, Legal);
- setOperationAction(ISD::FDIV, EVT::v4f32, Legal);
- setOperationAction(ISD::FSQRT, EVT::v4f32, Legal);
- setOperationAction(ISD::FNEG, EVT::v4f32, Custom);
- setOperationAction(ISD::LOAD, EVT::v4f32, Legal);
- setOperationAction(ISD::BUILD_VECTOR, EVT::v4f32, Custom);
- setOperationAction(ISD::VECTOR_SHUFFLE, EVT::v4f32, Custom);
- setOperationAction(ISD::EXTRACT_VECTOR_ELT, EVT::v4f32, Custom);
- setOperationAction(ISD::SELECT, EVT::v4f32, Custom);
- setOperationAction(ISD::VSETCC, EVT::v4f32, Custom);
+ addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
+
+ setOperationAction(ISD::FADD, MVT::v4f32, Legal);
+ setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
+ setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
+ setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
+ setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
+ setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
+ setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
+ setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
+ setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
+ setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
+ setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
+ setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
}
if (!UseSoftFloat && Subtarget->hasSSE2()) {
- addRegisterClass(EVT::v2f64, X86::VR128RegisterClass);
+ addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
// FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
// registers cannot be used even for integer operations.
- addRegisterClass(EVT::v16i8, X86::VR128RegisterClass);
- addRegisterClass(EVT::v8i16, X86::VR128RegisterClass);
- addRegisterClass(EVT::v4i32, X86::VR128RegisterClass);
- addRegisterClass(EVT::v2i64, X86::VR128RegisterClass);
-
- setOperationAction(ISD::ADD, EVT::v16i8, Legal);
- setOperationAction(ISD::ADD, EVT::v8i16, Legal);
- setOperationAction(ISD::ADD, EVT::v4i32, Legal);
- setOperationAction(ISD::ADD, EVT::v2i64, Legal);
- setOperationAction(ISD::MUL, EVT::v2i64, Custom);
- setOperationAction(ISD::SUB, EVT::v16i8, Legal);
- setOperationAction(ISD::SUB, EVT::v8i16, Legal);
- setOperationAction(ISD::SUB, EVT::v4i32, Legal);
- setOperationAction(ISD::SUB, EVT::v2i64, Legal);
- setOperationAction(ISD::MUL, EVT::v8i16, Legal);
- setOperationAction(ISD::FADD, EVT::v2f64, Legal);
- setOperationAction(ISD::FSUB, EVT::v2f64, Legal);
- setOperationAction(ISD::FMUL, EVT::v2f64, Legal);
- setOperationAction(ISD::FDIV, EVT::v2f64, Legal);
- setOperationAction(ISD::FSQRT, EVT::v2f64, Legal);
- setOperationAction(ISD::FNEG, EVT::v2f64, Custom);
-
- setOperationAction(ISD::VSETCC, EVT::v2f64, Custom);
- setOperationAction(ISD::VSETCC, EVT::v16i8, Custom);
- setOperationAction(ISD::VSETCC, EVT::v8i16, Custom);
- setOperationAction(ISD::VSETCC, EVT::v4i32, Custom);
-
- setOperationAction(ISD::SCALAR_TO_VECTOR, EVT::v16i8, Custom);
- setOperationAction(ISD::SCALAR_TO_VECTOR, EVT::v8i16, Custom);
- setOperationAction(ISD::INSERT_VECTOR_ELT, EVT::v8i16, Custom);
- setOperationAction(ISD::INSERT_VECTOR_ELT, EVT::v4i32, Custom);
- setOperationAction(ISD::INSERT_VECTOR_ELT, EVT::v4f32, Custom);
+ addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
+ addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
+ addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
+ addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
+
+ setOperationAction(ISD::ADD, MVT::v16i8, Legal);
+ setOperationAction(ISD::ADD, MVT::v8i16, Legal);
+ setOperationAction(ISD::ADD, MVT::v4i32, Legal);
+ setOperationAction(ISD::ADD, MVT::v2i64, Legal);
+ setOperationAction(ISD::MUL, MVT::v2i64, Custom);
+ setOperationAction(ISD::SUB, MVT::v16i8, Legal);
+ setOperationAction(ISD::SUB, MVT::v8i16, Legal);
+ setOperationAction(ISD::SUB, MVT::v4i32, Legal);
+ setOperationAction(ISD::SUB, MVT::v2i64, Legal);
+ setOperationAction(ISD::MUL, MVT::v8i16, Legal);
+ setOperationAction(ISD::FADD, MVT::v2f64, Legal);
+ setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
+ setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
+ setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
+ setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
+ setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
+
+ setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
+ setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
+ setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
+ setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
+
+ setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
+ setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
+ setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
+ setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
+ setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
// Custom lower build_vector, vector_shuffle, and extract_vector_elt.
- for (unsigned i = (unsigned)EVT::v16i8; i != (unsigned)EVT::v2i64; ++i) {
- EVT VT = (EVT::SimpleValueType)i;
+ for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
+ EVT VT = (MVT::SimpleValueType)i;
// Do not attempt to custom lower non-power-of-2 vectors
if (!isPowerOf2_32(VT.getVectorNumElements()))
continue;
// Do not attempt to custom lower non-128-bit vectors
if (!VT.is128BitVector())
continue;
- setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
- setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
- setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
+ setOperationAction(ISD::BUILD_VECTOR,
+ VT.getSimpleVT().SimpleTy, Custom);
+ setOperationAction(ISD::VECTOR_SHUFFLE,
+ VT.getSimpleVT().SimpleTy, Custom);
+ setOperationAction(ISD::EXTRACT_VECTOR_ELT,
+ VT.getSimpleVT().SimpleTy, Custom);
}
- setOperationAction(ISD::BUILD_VECTOR, EVT::v2f64, Custom);
- setOperationAction(ISD::BUILD_VECTOR, EVT::v2i64, Custom);
- setOperationAction(ISD::VECTOR_SHUFFLE, EVT::v2f64, Custom);
- setOperationAction(ISD::VECTOR_SHUFFLE, EVT::v2i64, Custom);
- setOperationAction(ISD::INSERT_VECTOR_ELT, EVT::v2f64, Custom);
- setOperationAction(ISD::EXTRACT_VECTOR_ELT, EVT::v2f64, Custom);
+ setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
+ setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
+ setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
+ setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
+ setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
+ setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
if (Subtarget->is64Bit()) {
- setOperationAction(ISD::INSERT_VECTOR_ELT, EVT::v2i64, Custom);
- setOperationAction(ISD::EXTRACT_VECTOR_ELT, EVT::v2i64, Custom);
+ setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
+ setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
}
// Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
- for (unsigned i = (unsigned)EVT::v16i8; i != (unsigned)EVT::v2i64; i++) {
- EVT::SimpleValueType SVT = (EVT::SimpleValueType)i;
+ for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
+ MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
EVT VT = SVT;
// Do not attempt to promote non-128-bit vectors
continue;
}
setOperationAction(ISD::AND, SVT, Promote);
- AddPromotedToType (ISD::AND, SVT, EVT::v2i64);
+ AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
setOperationAction(ISD::OR, SVT, Promote);
- AddPromotedToType (ISD::OR, SVT, EVT::v2i64);
+ AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
setOperationAction(ISD::XOR, SVT, Promote);
- AddPromotedToType (ISD::XOR, SVT, EVT::v2i64);
+ AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
setOperationAction(ISD::LOAD, SVT, Promote);
- AddPromotedToType (ISD::LOAD, SVT, EVT::v2i64);
+ AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
setOperationAction(ISD::SELECT, SVT, Promote);
- AddPromotedToType (ISD::SELECT, SVT, EVT::v2i64);
+ AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
}
- setTruncStoreAction(EVT::f64, EVT::f32, Expand);
+ setTruncStoreAction(MVT::f64, MVT::f32, Expand);
// Custom lower v2i64 and v2f64 selects.
- setOperationAction(ISD::LOAD, EVT::v2f64, Legal);
- setOperationAction(ISD::LOAD, EVT::v2i64, Legal);
- setOperationAction(ISD::SELECT, EVT::v2f64, Custom);
- setOperationAction(ISD::SELECT, EVT::v2i64, Custom);
+ setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
+ setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
+ setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
+ setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
- setOperationAction(ISD::FP_TO_SINT, EVT::v4i32, Legal);
- setOperationAction(ISD::SINT_TO_FP, EVT::v4i32, Legal);
+ setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
+ setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
if (!DisableMMX && Subtarget->hasMMX()) {
- setOperationAction(ISD::FP_TO_SINT, EVT::v2i32, Custom);
- setOperationAction(ISD::SINT_TO_FP, EVT::v2i32, Custom);
+ setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom);
+ setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
}
}
if (Subtarget->hasSSE41()) {
// FIXME: Do we need to handle scalar-to-vector here?
- setOperationAction(ISD::MUL, EVT::v4i32, Legal);
+ setOperationAction(ISD::MUL, MVT::v4i32, Legal);
// i8 and i16 vectors are custom , because the source register and source
// source memory operand types are not the same width. f32 vectors are
// custom since the immediate controlling the insert encodes additional
// information.
- setOperationAction(ISD::INSERT_VECTOR_ELT, EVT::v16i8, Custom);
- setOperationAction(ISD::INSERT_VECTOR_ELT, EVT::v8i16, Custom);
- setOperationAction(ISD::INSERT_VECTOR_ELT, EVT::v4i32, Custom);
- setOperationAction(ISD::INSERT_VECTOR_ELT, EVT::v4f32, Custom);
+ setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
+ setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
+ setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
+ setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
- setOperationAction(ISD::EXTRACT_VECTOR_ELT, EVT::v16i8, Custom);
- setOperationAction(ISD::EXTRACT_VECTOR_ELT, EVT::v8i16, Custom);
- setOperationAction(ISD::EXTRACT_VECTOR_ELT, EVT::v4i32, Custom);
- setOperationAction(ISD::EXTRACT_VECTOR_ELT, EVT::v4f32, Custom);
+ setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
+ setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
+ setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
+ setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
if (Subtarget->is64Bit()) {
- setOperationAction(ISD::INSERT_VECTOR_ELT, EVT::v2i64, Legal);
- setOperationAction(ISD::EXTRACT_VECTOR_ELT, EVT::v2i64, Legal);
+ setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
+ setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
}
}
if (Subtarget->hasSSE42()) {
- setOperationAction(ISD::VSETCC, EVT::v2i64, Custom);
+ setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
}
if (!UseSoftFloat && Subtarget->hasAVX()) {
- addRegisterClass(EVT::v8f32, X86::VR256RegisterClass);
- addRegisterClass(EVT::v4f64, X86::VR256RegisterClass);
- addRegisterClass(EVT::v8i32, X86::VR256RegisterClass);
- addRegisterClass(EVT::v4i64, X86::VR256RegisterClass);
-
- setOperationAction(ISD::LOAD, EVT::v8f32, Legal);
- setOperationAction(ISD::LOAD, EVT::v8i32, Legal);
- setOperationAction(ISD::LOAD, EVT::v4f64, Legal);
- setOperationAction(ISD::LOAD, EVT::v4i64, Legal);
- setOperationAction(ISD::FADD, EVT::v8f32, Legal);
- setOperationAction(ISD::FSUB, EVT::v8f32, Legal);
- setOperationAction(ISD::FMUL, EVT::v8f32, Legal);
- setOperationAction(ISD::FDIV, EVT::v8f32, Legal);
- setOperationAction(ISD::FSQRT, EVT::v8f32, Legal);
- setOperationAction(ISD::FNEG, EVT::v8f32, Custom);
- //setOperationAction(ISD::BUILD_VECTOR, EVT::v8f32, Custom);
- //setOperationAction(ISD::VECTOR_SHUFFLE, EVT::v8f32, Custom);
- //setOperationAction(ISD::EXTRACT_VECTOR_ELT, EVT::v8f32, Custom);
- //setOperationAction(ISD::SELECT, EVT::v8f32, Custom);
- //setOperationAction(ISD::VSETCC, EVT::v8f32, Custom);
+ addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
+ addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
+ addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
+ addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
+
+ setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
+ setOperationAction(ISD::LOAD, MVT::v8i32, Legal);
+ setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
+ setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
+ setOperationAction(ISD::FADD, MVT::v8f32, Legal);
+ setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
+ setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
+ setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
+ setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
+ setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
+ //setOperationAction(ISD::BUILD_VECTOR, MVT::v8f32, Custom);
+ //setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Custom);
+ //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom);
+ //setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
+ //setOperationAction(ISD::VSETCC, MVT::v8f32, Custom);
// Operations to consider commented out -v16i16 v32i8
- //setOperationAction(ISD::ADD, EVT::v16i16, Legal);
- setOperationAction(ISD::ADD, EVT::v8i32, Custom);
- setOperationAction(ISD::ADD, EVT::v4i64, Custom);
- //setOperationAction(ISD::SUB, EVT::v32i8, Legal);
- //setOperationAction(ISD::SUB, EVT::v16i16, Legal);
- setOperationAction(ISD::SUB, EVT::v8i32, Custom);
- setOperationAction(ISD::SUB, EVT::v4i64, Custom);
- //setOperationAction(ISD::MUL, EVT::v16i16, Legal);
- setOperationAction(ISD::FADD, EVT::v4f64, Legal);
- setOperationAction(ISD::FSUB, EVT::v4f64, Legal);
- setOperationAction(ISD::FMUL, EVT::v4f64, Legal);
- setOperationAction(ISD::FDIV, EVT::v4f64, Legal);
- setOperationAction(ISD::FSQRT, EVT::v4f64, Legal);
- setOperationAction(ISD::FNEG, EVT::v4f64, Custom);
-
- setOperationAction(ISD::VSETCC, EVT::v4f64, Custom);
- // setOperationAction(ISD::VSETCC, EVT::v32i8, Custom);
- // setOperationAction(ISD::VSETCC, EVT::v16i16, Custom);
- setOperationAction(ISD::VSETCC, EVT::v8i32, Custom);
-
- // setOperationAction(ISD::SCALAR_TO_VECTOR, EVT::v32i8, Custom);
- // setOperationAction(ISD::SCALAR_TO_VECTOR, EVT::v16i16, Custom);
- // setOperationAction(ISD::INSERT_VECTOR_ELT, EVT::v16i16, Custom);
- setOperationAction(ISD::INSERT_VECTOR_ELT, EVT::v8i32, Custom);
- setOperationAction(ISD::INSERT_VECTOR_ELT, EVT::v8f32, Custom);
-
- setOperationAction(ISD::BUILD_VECTOR, EVT::v4f64, Custom);
- setOperationAction(ISD::BUILD_VECTOR, EVT::v4i64, Custom);
- setOperationAction(ISD::VECTOR_SHUFFLE, EVT::v4f64, Custom);
- setOperationAction(ISD::VECTOR_SHUFFLE, EVT::v4i64, Custom);
- setOperationAction(ISD::INSERT_VECTOR_ELT, EVT::v4f64, Custom);
- setOperationAction(ISD::EXTRACT_VECTOR_ELT, EVT::v4f64, Custom);
+ //setOperationAction(ISD::ADD, MVT::v16i16, Legal);
+ setOperationAction(ISD::ADD, MVT::v8i32, Custom);
+ setOperationAction(ISD::ADD, MVT::v4i64, Custom);
+ //setOperationAction(ISD::SUB, MVT::v32i8, Legal);
+ //setOperationAction(ISD::SUB, MVT::v16i16, Legal);
+ setOperationAction(ISD::SUB, MVT::v8i32, Custom);
+ setOperationAction(ISD::SUB, MVT::v4i64, Custom);
+ //setOperationAction(ISD::MUL, MVT::v16i16, Legal);
+ setOperationAction(ISD::FADD, MVT::v4f64, Legal);
+ setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
+ setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
+ setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
+ setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
+ setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
+
+ setOperationAction(ISD::VSETCC, MVT::v4f64, Custom);
+ // setOperationAction(ISD::VSETCC, MVT::v32i8, Custom);
+ // setOperationAction(ISD::VSETCC, MVT::v16i16, Custom);
+ setOperationAction(ISD::VSETCC, MVT::v8i32, Custom);
+
+ // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i8, Custom);
+ // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i16, Custom);
+ // setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i16, Custom);
+ setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i32, Custom);
+ setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f32, Custom);
+
+ setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
+ setOperationAction(ISD::BUILD_VECTOR, MVT::v4i64, Custom);
+ setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f64, Custom);
+ setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i64, Custom);
+ setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f64, Custom);
+ setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom);
#if 0
// Not sure we want to do this since there are no 256-bit integer
// Custom lower build_vector, vector_shuffle, and extract_vector_elt.
// This includes 256-bit vectors
- for (unsigned i = (unsigned)EVT::v16i8; i != (unsigned)EVT::v4i64; ++i) {
- EVT VT = (EVT::SimpleValueType)i;
+ for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) {
+ EVT VT = (MVT::SimpleValueType)i;
// Do not attempt to custom lower non-power-of-2 vectors
if (!isPowerOf2_32(VT.getVectorNumElements()))
}
if (Subtarget->is64Bit()) {
- setOperationAction(ISD::INSERT_VECTOR_ELT, EVT::v4i64, Custom);
- setOperationAction(ISD::EXTRACT_VECTOR_ELT, EVT::v4i64, Custom);
+ setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i64, Custom);
+ setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom);
}
#endif
// Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64.
// Including 256-bit vectors
- for (unsigned i = (unsigned)EVT::v16i8; i != (unsigned)EVT::v4i64; i++) {
- EVT VT = (EVT::SimpleValueType)i;
+ for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) {
+ EVT VT = (MVT::SimpleValueType)i;
if (!VT.is256BitVector()) {
continue;
}
setOperationAction(ISD::AND, VT, Promote);
- AddPromotedToType (ISD::AND, VT, EVT::v4i64);
+ AddPromotedToType (ISD::AND, VT, MVT::v4i64);
setOperationAction(ISD::OR, VT, Promote);
- AddPromotedToType (ISD::OR, VT, EVT::v4i64);
+ AddPromotedToType (ISD::OR, VT, MVT::v4i64);
setOperationAction(ISD::XOR, VT, Promote);
- AddPromotedToType (ISD::XOR, VT, EVT::v4i64);
+ AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
setOperationAction(ISD::LOAD, VT, Promote);
- AddPromotedToType (ISD::LOAD, VT, EVT::v4i64);
+ AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
setOperationAction(ISD::SELECT, VT, Promote);
- AddPromotedToType (ISD::SELECT, VT, EVT::v4i64);
+ AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
}
- setTruncStoreAction(EVT::f64, EVT::f32, Expand);
+ setTruncStoreAction(MVT::f64, MVT::f32, Expand);
#endif
}
// We want to custom lower some of our intrinsics.
- setOperationAction(ISD::INTRINSIC_WO_CHAIN, EVT::Other, Custom);
+ setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
// Add/Sub/Mul with overflow operations are custom lowered.
- setOperationAction(ISD::SADDO, EVT::i32, Custom);
- setOperationAction(ISD::SADDO, EVT::i64, Custom);
- setOperationAction(ISD::UADDO, EVT::i32, Custom);
- setOperationAction(ISD::UADDO, EVT::i64, Custom);
- setOperationAction(ISD::SSUBO, EVT::i32, Custom);
- setOperationAction(ISD::SSUBO, EVT::i64, Custom);
- setOperationAction(ISD::USUBO, EVT::i32, Custom);
- setOperationAction(ISD::USUBO, EVT::i64, Custom);
- setOperationAction(ISD::SMULO, EVT::i32, Custom);
- setOperationAction(ISD::SMULO, EVT::i64, Custom);
+ setOperationAction(ISD::SADDO, MVT::i32, Custom);
+ setOperationAction(ISD::SADDO, MVT::i64, Custom);
+ setOperationAction(ISD::UADDO, MVT::i32, Custom);
+ setOperationAction(ISD::UADDO, MVT::i64, Custom);
+ setOperationAction(ISD::SSUBO, MVT::i32, Custom);
+ setOperationAction(ISD::SSUBO, MVT::i64, Custom);
+ setOperationAction(ISD::USUBO, MVT::i32, Custom);
+ setOperationAction(ISD::USUBO, MVT::i64, Custom);
+ setOperationAction(ISD::SMULO, MVT::i32, Custom);
+ setOperationAction(ISD::SMULO, MVT::i64, Custom);
if (!Subtarget->is64Bit()) {
// These libcalls are not available in 32-bit.
}
-EVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const {
- return EVT::i8;
+MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const {
+ return MVT::i8;
}
/// getOptimalMemOpType - Returns the target specific optimal type for load
/// and store operations as a result of memset, memcpy, and memmove
-/// lowering. It returns EVT::iAny if SelectionDAG should be responsible for
+/// lowering. It returns MVT::iAny if SelectionDAG should be responsible for
/// determining it.
EVT
X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align,
bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
if (!NoImplicitFloatOps && Subtarget->getStackAlignment() >= 16) {
if ((isSrcConst || isSrcStr) && Subtarget->hasSSE2() && Size >= 16)
- return EVT::v4i32;
+ return MVT::v4i32;
if ((isSrcConst || isSrcStr) && Subtarget->hasSSE1() && Size >= 16)
- return EVT::v4f32;
+ return MVT::v4f32;
}
if (Subtarget->is64Bit() && Size >= 8)
- return EVT::i64;
- return EVT::i32;
+ return MVT::i64;
+ return MVT::i32;
}
/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
SmallVector<SDValue, 6> RetOps;
RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
// Operand #1 = Bytes To Pop
- RetOps.push_back(DAG.getConstant(getBytesToPopOnReturn(), EVT::i16));
+ RetOps.push_back(DAG.getConstant(getBytesToPopOnReturn(), MVT::i16));
// Copy the result values into the output registers.
for (unsigned i = 0; i != RVLocs.size(); ++i) {
// If this is a copy from an xmm register to ST(0), use an FPExtend to
// change the value to the FP stack register class.
if (isScalarFPTypeInSSEReg(VA.getValVT()))
- ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, EVT::f80, ValToCopy);
+ ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
RetOps.push_back(ValToCopy);
// Don't emit a copytoreg.
continue;
if (Subtarget->is64Bit()) {
EVT ValVT = ValToCopy.getValueType();
if (ValVT.isVector() && ValVT.getSizeInBits() == 64) {
- ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i64, ValToCopy);
+ ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy);
if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1)
- ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, EVT::v2i64, ValToCopy);
+ ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, ValToCopy);
}
}
X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
unsigned Reg = FuncInfo->getSRetReturnReg();
if (!Reg) {
- Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(EVT::i64));
+ Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
FuncInfo->setSRetReturnReg(Reg);
}
SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
RetOps.push_back(Flag);
return DAG.getNode(X86ISD::RET_FLAG, dl,
- EVT::Other, &RetOps[0], RetOps.size());
+ MVT::Other, &RetOps[0], RetOps.size());
}
/// LowerCallResult - Lower the result values of a call into the
EVT CopyVT = VA.getValVT();
// If this is x86-64, and we disabled SSE, we can't return FP values
- if ((CopyVT == EVT::f32 || CopyVT == EVT::f64) &&
+ if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
llvm_report_error("SSE register return with SSE disabled");
}
if ((VA.getLocReg() == X86::ST0 ||
VA.getLocReg() == X86::ST1) &&
isScalarFPTypeInSSEReg(VA.getValVT())) {
- CopyVT = EVT::f80;
+ CopyVT = MVT::f80;
}
SDValue Val;
// For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64.
if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
- EVT::v2i64, InFlag).getValue(1);
+ MVT::v2i64, InFlag).getValue(1);
Val = Chain.getValue(0);
- Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::i64,
- Val, DAG.getConstant(0, EVT::i64));
+ Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
+ Val, DAG.getConstant(0, MVT::i64));
} else {
Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
- EVT::i64, InFlag).getValue(1);
+ MVT::i64, InFlag).getValue(1);
Val = Chain.getValue(0);
}
Val = DAG.getNode(ISD::BIT_CONVERT, dl, CopyVT, Val);
CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
DebugLoc dl) {
- SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), EVT::i32);
+ SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
/*AlwaysInline=*/true, NULL, 0, NULL, 0);
}
if (VA.isRegLoc()) {
EVT RegVT = VA.getLocVT();
TargetRegisterClass *RC = NULL;
- if (RegVT == EVT::i32)
+ if (RegVT == MVT::i32)
RC = X86::GR32RegisterClass;
- else if (Is64Bit && RegVT == EVT::i64)
+ else if (Is64Bit && RegVT == MVT::i64)
RC = X86::GR64RegisterClass;
- else if (RegVT == EVT::f32)
+ else if (RegVT == MVT::f32)
RC = X86::FR32RegisterClass;
- else if (RegVT == EVT::f64)
+ else if (RegVT == MVT::f64)
RC = X86::FR64RegisterClass;
else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
RC = X86::VR128RegisterClass;
if (VA.isExtInLoc()) {
// Handle MMX values passed in XMM regs.
if (RegVT.isVector()) {
- ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::i64,
- ArgValue, DAG.getConstant(0, EVT::i64));
+ ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
+ ArgValue, DAG.getConstant(0, MVT::i64));
ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
} else
ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
unsigned Reg = FuncInfo->getSRetReturnReg();
if (!Reg) {
- Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(EVT::i64));
+ Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
FuncInfo->setSRetReturnReg(Reg);
}
SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Copy, Chain);
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
}
unsigned StackSize = CCInfo.getNextStackOffset();
for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
X86::GR64RegisterClass);
- SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, EVT::i64);
+ SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
SDValue Store =
DAG.getStore(Val.getValue(1), dl, Val, FIN,
PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0);
for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
unsigned VReg = MF.addLiveIn(XMMArgRegs[NumXMMRegs],
X86::VR128RegisterClass);
- SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, EVT::v4f32);
+ SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
SDValue Store =
DAG.getStore(Val.getValue(1), dl, Val, FIN,
PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0);
DAG.getIntPtrConstant(16));
}
if (!MemOps.empty())
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&MemOps[0], MemOps.size());
}
}
int SlotSize = Is64Bit ? 8 : 4;
int NewReturnAddrFI =
MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize);
- EVT VT = Is64Bit ? EVT::i64 : EVT::i32;
+ EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0);
case CCValAssign::AExt:
if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
// Special case: passing MMX values in XMM registers.
- Arg = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i64, Arg);
- Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, EVT::v2i64, Arg);
- Arg = getMOVL(DAG, dl, EVT::v2i64, DAG.getUNDEF(EVT::v2i64), Arg);
+ Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
+ Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
+ Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
} else
Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
break;
}
if (!MemOpChains.empty())
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&MemOpChains[0], MemOpChains.size());
// Build a sequence of copy-to-reg nodes chained together with token chain
&& "SSE registers cannot be used when SSE is disabled");
Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
- DAG.getConstant(NumXMMRegs, EVT::i8), InFlag);
+ DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
InFlag = Chain.getValue(1);
}
}
if (!MemOpChains2.empty())
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&MemOpChains2[0], MemOpChains2.size());
// Copy arguments to their registers.
}
// Returns a chain & a flag for retval copy to use.
- SDVTList NodeTys = DAG.getVTList(EVT::Other, EVT::Flag);
+ SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
SmallVector<SDValue, 8> Ops;
if (isTailCall) {
Ops.push_back(Callee);
if (isTailCall)
- Ops.push_back(DAG.getConstant(FPDiff, EVT::i32));
+ Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
// Add argument registers to the end of the list so that they are known live
// into the call.
// Add an implicit use of AL for x86 vararg functions.
if (Is64Bit && isVarArg)
- Ops.push_back(DAG.getRegister(X86::AL, EVT::i8));
+ Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
if (InFlag.getNode())
Ops.push_back(InFlag);
/// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
/// the second operand.
static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) {
- if (VT == EVT::v4f32 || VT == EVT::v4i32 || VT == EVT::v4i16)
+ if (VT == MVT::v4f32 || VT == MVT::v4i32 || VT == MVT::v4i16)
return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
- if (VT == EVT::v2f64 || VT == EVT::v2i64)
+ if (VT == MVT::v2f64 || VT == MVT::v2i64)
return (Mask[0] < 2 && Mask[1] < 2);
return false;
}
/// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
/// is suitable for input to PSHUFHW.
static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
- if (VT != EVT::v8i16)
+ if (VT != MVT::v8i16)
return false;
// Lower quadword copied in order or undef.
/// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
/// is suitable for input to PSHUFLW.
static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
- if (VT != EVT::v8i16)
+ if (VT != MVT::v8i16)
return false;
// Upper quadword copied in order.
// type. This ensures they get CSE'd.
SDValue Vec;
if (VT.getSizeInBits() == 64) { // MMX
- SDValue Cst = DAG.getTargetConstant(0, EVT::i32);
- Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v2i32, Cst, Cst);
+ SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
+ Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
} else if (HasSSE2) { // SSE2
- SDValue Cst = DAG.getTargetConstant(0, EVT::i32);
- Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32, Cst, Cst, Cst, Cst);
+ SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
+ Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
} else { // SSE1
- SDValue Cst = DAG.getTargetConstantFP(+0.0, EVT::f32);
- Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4f32, Cst, Cst, Cst, Cst);
+ SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
+ Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
}
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
}
// Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
// type. This ensures they get CSE'd.
- SDValue Cst = DAG.getTargetConstant(~0U, EVT::i32);
+ SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
SDValue Vec;
if (VT.getSizeInBits() == 64) // MMX
- Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v2i32, Cst, Cst);
+ Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
else // SSE
- Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32, Cst, Cst, Cst, Cst);
+ Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
}
if (SV->getValueType(0).getVectorNumElements() <= 4)
return SDValue(SV, 0);
- EVT PVT = EVT::v4f32;
+ EVT PVT = MVT::v4f32;
EVT VT = SV->getValueType(0);
DebugLoc dl = SV->getDebugLoc();
SDValue V1 = SV->getOperand(0);
bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
if (ThisIsNonZero && First) {
if (NumZero)
- V = getZeroVector(EVT::v8i16, true, DAG, dl);
+ V = getZeroVector(MVT::v8i16, true, DAG, dl);
else
- V = DAG.getUNDEF(EVT::v8i16);
+ V = DAG.getUNDEF(MVT::v8i16);
First = false;
}
bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
if (LastIsNonZero) {
LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
- EVT::i16, Op.getOperand(i-1));
+ MVT::i16, Op.getOperand(i-1));
}
if (ThisIsNonZero) {
- ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, EVT::i16, Op.getOperand(i));
- ThisElt = DAG.getNode(ISD::SHL, dl, EVT::i16,
- ThisElt, DAG.getConstant(8, EVT::i8));
+ ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
+ ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
+ ThisElt, DAG.getConstant(8, MVT::i8));
if (LastIsNonZero)
- ThisElt = DAG.getNode(ISD::OR, dl, EVT::i16, ThisElt, LastElt);
+ ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
} else
ThisElt = LastElt;
if (ThisElt.getNode())
- V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, EVT::v8i16, V, ThisElt,
+ V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
DAG.getIntPtrConstant(i/2));
}
}
- return DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v16i8, V);
+ return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V);
}
/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
if (isNonZero) {
if (First) {
if (NumZero)
- V = getZeroVector(EVT::v8i16, true, DAG, dl);
+ V = getZeroVector(MVT::v8i16, true, DAG, dl);
else
- V = DAG.getUNDEF(EVT::v8i16);
+ V = DAG.getUNDEF(MVT::v8i16);
First = false;
}
V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
- EVT::v8i16, V, Op.getOperand(i),
+ MVT::v8i16, V, Op.getOperand(i),
DAG.getIntPtrConstant(i));
}
}
unsigned NumBits, SelectionDAG &DAG,
const TargetLowering &TLI, DebugLoc dl) {
bool isMMX = VT.getSizeInBits() == 64;
- EVT ShVT = isMMX ? EVT::v1i64 : EVT::v2i64;
+ EVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64;
unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp);
return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
// Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
// 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
// eliminated on x86-32 hosts.
- if (Op.getValueType() == EVT::v4i32 || Op.getValueType() == EVT::v2i32)
+ if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
return Op;
if (ISD::isBuildVectorAllOnes(Op.getNode()))
// insertion that way. Only do this if the value is non-constant or if the
// value is a constant being inserted into element 0. It is cheaper to do
// a constant pool load than it is to do a movd + shuffle.
- if (ExtVT == EVT::i64 && !Subtarget->is64Bit() &&
+ if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
(!IsAllConstants || Idx == 0)) {
if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
// Handle MMX and SSE both.
- EVT VecVT = VT == EVT::v2i64 ? EVT::v4i32 : EVT::v2i32;
- unsigned VecElts = VT == EVT::v2i64 ? 4 : 2;
+ EVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32;
+ unsigned VecElts = VT == MVT::v2i64 ? 4 : 2;
// Truncate the value (which may itself be a constant) to i32, and
// convert it to a vector with movd (S2V+shuffle to zero extend).
- Item = DAG.getNode(ISD::TRUNCATE, dl, EVT::i32, Item);
+ Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
Item = getShuffleVectorZeroOrUndef(Item, 0, true,
Subtarget->hasSSE2(), DAG);
if (Idx == 0) {
if (NumZero == 0) {
return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
- } else if (ExtVT == EVT::i32 || ExtVT == EVT::f32 || ExtVT == EVT::f64 ||
- (ExtVT == EVT::i64 && Subtarget->is64Bit())) {
+ } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
+ (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
// Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(),
DAG);
- } else if (ExtVT == EVT::i16 || ExtVT == EVT::i8) {
- Item = DAG.getNode(ISD::ZERO_EXTEND, dl, EVT::i32, Item);
- EVT MiddleVT = VT.getSizeInBits() == 64 ? EVT::v2i32 : EVT::v4i32;
+ } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
+ Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
+ EVT MiddleVT = VT.getSizeInBits() == 64 ? MVT::v2i32 : MVT::v4i32;
Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
Item = getShuffleVectorZeroOrUndef(Item, 0, true,
Subtarget->hasSSE2(), DAG);
SmallVector<int, 8> MaskV;
MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
- NewV = DAG.getVectorShuffle(EVT::v2i64, dl,
- DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v2i64, V1),
- DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v2i64, V2), &MaskV[0]);
- NewV = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v8i16, NewV);
+ NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
+ DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1),
+ DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), &MaskV[0]);
+ NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV);
// Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
// source words for the shuffle, to aid later transformations.
// If we've eliminated the use of V2, and the new mask is a pshuflw or
// pshufhw, that's as cheap as it gets. Return the new shuffle.
if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
- return DAG.getVectorShuffle(EVT::v8i16, dl, NewV,
- DAG.getUNDEF(EVT::v8i16), &MaskVals[0]);
+ return DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
+ DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
}
}
for (unsigned i = 0; i != 8; ++i) {
int EltIdx = MaskVals[i] * 2;
if (TwoInputs && (EltIdx >= 16)) {
- pshufbMask.push_back(DAG.getConstant(0x80, EVT::i8));
- pshufbMask.push_back(DAG.getConstant(0x80, EVT::i8));
+ pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
+ pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
continue;
}
- pshufbMask.push_back(DAG.getConstant(EltIdx, EVT::i8));
- pshufbMask.push_back(DAG.getConstant(EltIdx+1, EVT::i8));
+ pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
+ pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
}
- V1 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v16i8, V1);
- V1 = DAG.getNode(X86ISD::PSHUFB, dl, EVT::v16i8, V1,
+ V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V1);
+ V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
DAG.getNode(ISD::BUILD_VECTOR, dl,
- EVT::v16i8, &pshufbMask[0], 16));
+ MVT::v16i8, &pshufbMask[0], 16));
if (!TwoInputs)
- return DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v8i16, V1);
+ return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
// Calculate the shuffle mask for the second input, shuffle it, and
// OR it with the first shuffled input.
for (unsigned i = 0; i != 8; ++i) {
int EltIdx = MaskVals[i] * 2;
if (EltIdx < 16) {
- pshufbMask.push_back(DAG.getConstant(0x80, EVT::i8));
- pshufbMask.push_back(DAG.getConstant(0x80, EVT::i8));
+ pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
+ pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
continue;
}
- pshufbMask.push_back(DAG.getConstant(EltIdx - 16, EVT::i8));
- pshufbMask.push_back(DAG.getConstant(EltIdx - 15, EVT::i8));
+ pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
+ pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
}
- V2 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v16i8, V2);
- V2 = DAG.getNode(X86ISD::PSHUFB, dl, EVT::v16i8, V2,
+ V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V2);
+ V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
DAG.getNode(ISD::BUILD_VECTOR, dl,
- EVT::v16i8, &pshufbMask[0], 16));
- V1 = DAG.getNode(ISD::OR, dl, EVT::v16i8, V1, V2);
- return DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v8i16, V1);
+ MVT::v16i8, &pshufbMask[0], 16));
+ V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
+ return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
}
// If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
}
for (unsigned i = 4; i != 8; ++i)
MaskV.push_back(i);
- NewV = DAG.getVectorShuffle(EVT::v8i16, dl, NewV, DAG.getUNDEF(EVT::v8i16),
+ NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
&MaskV[0]);
}
MaskV.push_back(-1);
}
}
- NewV = DAG.getVectorShuffle(EVT::v8i16, dl, NewV, DAG.getUNDEF(EVT::v8i16),
+ NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
&MaskV[0]);
}
if (EltIdx < 0)
continue;
SDValue ExtOp = (EltIdx < 8)
- ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::i16, V1,
+ ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
DAG.getIntPtrConstant(EltIdx))
- : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::i16, V2,
+ : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
DAG.getIntPtrConstant(EltIdx - 8));
- NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, EVT::v8i16, NewV, ExtOp,
+ NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
DAG.getIntPtrConstant(i));
}
return NewV;
for (unsigned i = 0; i != 16; ++i) {
int EltIdx = MaskVals[i];
if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
- pshufbMask.push_back(DAG.getConstant(0x80, EVT::i8));
+ pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
continue;
}
- pshufbMask.push_back(DAG.getConstant(EltIdx, EVT::i8));
+ pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
}
// If all the elements are from V2, assign it to V1 and return after
// building the first pshufb.
if (V2Only)
V1 = V2;
- V1 = DAG.getNode(X86ISD::PSHUFB, dl, EVT::v16i8, V1,
+ V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
DAG.getNode(ISD::BUILD_VECTOR, dl,
- EVT::v16i8, &pshufbMask[0], 16));
+ MVT::v16i8, &pshufbMask[0], 16));
if (!TwoInputs)
return V1;
for (unsigned i = 0; i != 16; ++i) {
int EltIdx = MaskVals[i];
if (EltIdx < 16) {
- pshufbMask.push_back(DAG.getConstant(0x80, EVT::i8));
+ pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
continue;
}
- pshufbMask.push_back(DAG.getConstant(EltIdx - 16, EVT::i8));
+ pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
}
- V2 = DAG.getNode(X86ISD::PSHUFB, dl, EVT::v16i8, V2,
+ V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
DAG.getNode(ISD::BUILD_VECTOR, dl,
- EVT::v16i8, &pshufbMask[0], 16));
- return DAG.getNode(ISD::OR, dl, EVT::v16i8, V1, V2);
+ MVT::v16i8, &pshufbMask[0], 16));
+ return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
}
// No SSSE3 - Calculate in place words and then fix all out of place words
// With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
// the 16 different words that comprise the two doublequadword input vectors.
- V1 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v8i16, V1);
- V2 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v8i16, V2);
+ V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
+ V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V2);
SDValue NewV = V2Only ? V2 : V1;
for (int i = 0; i != 8; ++i) {
int Elt0 = MaskVals[i*2];
// If Elt0 and Elt1 are defined, are consecutive, and can be load
// using a single extract together, load it and store it.
if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
- InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::i16, Elt1Src,
+ InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
DAG.getIntPtrConstant(Elt1 / 2));
- NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, EVT::v8i16, NewV, InsElt,
+ NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
DAG.getIntPtrConstant(i));
continue;
}
// source byte is not also odd, shift the extracted word left 8 bits
// otherwise clear the bottom 8 bits if we need to do an or.
if (Elt1 >= 0) {
- InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::i16, Elt1Src,
+ InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
DAG.getIntPtrConstant(Elt1 / 2));
if ((Elt1 & 1) == 0)
- InsElt = DAG.getNode(ISD::SHL, dl, EVT::i16, InsElt,
+ InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
DAG.getConstant(8, TLI.getShiftAmountTy()));
else if (Elt0 >= 0)
- InsElt = DAG.getNode(ISD::AND, dl, EVT::i16, InsElt,
- DAG.getConstant(0xFF00, EVT::i16));
+ InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
+ DAG.getConstant(0xFF00, MVT::i16));
}
// If Elt0 is defined, extract it from the appropriate source. If the
// source byte is not also even, shift the extracted word right 8 bits. If
// Elt1 was also defined, OR the extracted values together before
// inserting them in the result.
if (Elt0 >= 0) {
- SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::i16,
+ SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
if ((Elt0 & 1) != 0)
- InsElt0 = DAG.getNode(ISD::SRL, dl, EVT::i16, InsElt0,
+ InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
DAG.getConstant(8, TLI.getShiftAmountTy()));
else if (Elt1 >= 0)
- InsElt0 = DAG.getNode(ISD::AND, dl, EVT::i16, InsElt0,
- DAG.getConstant(0x00FF, EVT::i16));
- InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, EVT::i16, InsElt, InsElt0)
+ InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
+ DAG.getConstant(0x00FF, MVT::i16));
+ InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
: InsElt0;
}
- NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, EVT::v8i16, NewV, InsElt,
+ NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
DAG.getIntPtrConstant(i));
}
- return DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v16i8, NewV);
+ return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, NewV);
}
/// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
SDValue V2 = SVOp->getOperand(1);
unsigned NumElems = VT.getVectorNumElements();
unsigned NewWidth = (NumElems == 4) ? 2 : 4;
- EVT MaskVT = EVT::getIntVectorWithNumElements(NewWidth);
+ EVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
EVT MaskEltVT = MaskVT.getVectorElementType();
EVT NewVT = MaskVT;
- switch (VT.getSimpleVT()) {
+ switch (VT.getSimpleVT().SimpleTy) {
default: assert(false && "Unexpected!");
- case EVT::v4f32: NewVT = EVT::v2f64; break;
- case EVT::v4i32: NewVT = EVT::v2i64; break;
- case EVT::v8i16: NewVT = EVT::v4i32; break;
- case EVT::v16i8: NewVT = EVT::v4i32; break;
+ case MVT::v4f32: NewVT = MVT::v2f64; break;
+ case MVT::v4i32: NewVT = MVT::v2i64; break;
+ case MVT::v8i16: NewVT = MVT::v4i32; break;
+ case MVT::v16i8: NewVT = MVT::v4i32; break;
}
if (NewWidth == 2) {
if (VT.isInteger())
- NewVT = EVT::v2i64;
+ NewVT = MVT::v2i64;
else
- NewVT = EVT::v2f64;
+ NewVT = MVT::v2f64;
}
int Scale = NumElems / NewWidth;
SmallVector<int, 8> MaskVec;
static SDValue getVZextMovL(EVT VT, EVT OpVT,
SDValue SrcOp, SelectionDAG &DAG,
const X86Subtarget *Subtarget, DebugLoc dl) {
- if (VT == EVT::v2f64 || VT == EVT::v4f32) {
+ if (VT == MVT::v2f64 || VT == MVT::v4f32) {
LoadSDNode *LD = NULL;
if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
LD = dyn_cast<LoadSDNode>(SrcOp);
if (!LD) {
// movssrr and movsdrr do not clear top bits. Try to use movd, movq
// instead.
- EVT EVT = (OpVT == EVT::v2f64) ? EVT::i64 : EVT::i32;
- if ((EVT != EVT::i64 || Subtarget->is64Bit()) &&
+ EVT EVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
+ if ((EVT != MVT::i64 || Subtarget->is64Bit()) &&
SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT &&
SrcOp.getOperand(0).getOperand(0).getValueType() == EVT) {
// PR2108
- OpVT = (OpVT == EVT::v2f64) ? EVT::v2i64 : EVT::v4i32;
+ OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
// If the shuffle can be profitably rewritten as a narrower shuffle, then
// do it!
- if (VT == EVT::v8i16 || VT == EVT::v16i8) {
+ if (VT == MVT::v8i16 || VT == MVT::v16i8) {
SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
if (NewOp.getNode())
return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
LowerVECTOR_SHUFFLE(NewOp, DAG));
- } else if ((VT == EVT::v4i32 || (VT == EVT::v4f32 && Subtarget->hasSSE2()))) {
+ } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
// FIXME: Figure out a cleaner way to do this.
// Try to make use of movq to zero out the top part.
if (ISD::isBuildVectorAllZeros(V2.getNode())) {
return Op;
// Handle v8i16 specifically since SSE can do byte extraction and insertion.
- if (VT == EVT::v8i16) {
+ if (VT == MVT::v8i16) {
SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(SVOp, DAG, *this);
if (NewOp.getNode())
return NewOp;
}
- if (VT == EVT::v16i8) {
+ if (VT == MVT::v16i8) {
SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
if (NewOp.getNode())
return NewOp;
EVT VT = Op.getValueType();
DebugLoc dl = Op.getDebugLoc();
if (VT.getSizeInBits() == 8) {
- SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, EVT::i32,
+ SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
Op.getOperand(0), Op.getOperand(1));
- SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EVT::i32, Extract,
+ SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
DAG.getValueType(VT));
return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
} else if (VT.getSizeInBits() == 16) {
unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
// If Idx is 0, it's cheaper to do a move instead of a pextrw.
if (Idx == 0)
- return DAG.getNode(ISD::TRUNCATE, dl, EVT::i16,
- DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::i32,
+ return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
+ DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
DAG.getNode(ISD::BIT_CONVERT, dl,
- EVT::v4i32,
+ MVT::v4i32,
Op.getOperand(0)),
Op.getOperand(1)));
- SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EVT::i32,
+ SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
Op.getOperand(0), Op.getOperand(1));
- SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EVT::i32, Extract,
+ SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
DAG.getValueType(VT));
return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
- } else if (VT == EVT::f32) {
+ } else if (VT == MVT::f32) {
// EXTRACTPS outputs to a GPR32 register which will require a movd to copy
// the result back to FR32 register. It's only worth matching if the
// result has a single use which is a store or a bitcast to i32. And in
(isa<ConstantSDNode>(Op.getOperand(1)) &&
cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
(User->getOpcode() != ISD::BIT_CONVERT ||
- User->getValueType(0) != EVT::i32))
+ User->getValueType(0) != MVT::i32))
return SDValue();
- SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::i32,
- DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v4i32,
+ SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
+ DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32,
Op.getOperand(0)),
Op.getOperand(1));
- return DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, Extract);
- } else if (VT == EVT::i32) {
+ return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract);
+ } else if (VT == MVT::i32) {
// ExtractPS works with constant index.
if (isa<ConstantSDNode>(Op.getOperand(1)))
return Op;
SDValue Vec = Op.getOperand(0);
unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
if (Idx == 0)
- return DAG.getNode(ISD::TRUNCATE, dl, EVT::i16,
- DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::i32,
+ return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
+ DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
DAG.getNode(ISD::BIT_CONVERT, dl,
- EVT::v4i32, Vec),
+ MVT::v4i32, Vec),
Op.getOperand(1)));
// Transform it so it match pextrw which produces a 32-bit result.
- EVT EVT = (EVT::SimpleValueType)(VT.getSimpleVT()+1);
+ EVT EVT = (MVT::SimpleValueType)(VT.getSimpleVT().SimpleTy+1);
SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EVT,
Op.getOperand(0), Op.getOperand(1));
SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EVT, Extract,
@@ -4379,12 +4382,12 @@ X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){
: X86ISD::PINSRW;
// Transform it so it match pinsr{b,w} which expects a GR32 as its second
// argument.
- if (N1.getValueType() != EVT::i32)
- N1 = DAG.getNode(ISD::ANY_EXTEND, dl, EVT::i32, N1);
- if (N2.getValueType() != EVT::i32)
+ if (N1.getValueType() != MVT::i32)
+ N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
+ if (N2.getValueType() != MVT::i32)
N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
return DAG.getNode(Opc, dl, VT, N0, N1, N2);
- } else if (EVT == EVT::f32 && isa<ConstantSDNode>(N2)) {
+ } else if (EVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
// Bits [7:6] of the constant are the source select. This will always be
// zero here. The DAG Combiner may combine an extract_elt index into these
// bits. For example (insert (extract, 3), 2) could be matched by putting
@@ -4395,9 +4398,9 @@ X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){
// combine either bitwise AND or insert of float 0.0 to set these bits.
N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
// Create this as a scalar to vector..
- N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, EVT::v4f32, N1);
+ N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
- } else if (EVT == EVT::i32 && isa<ConstantSDNode>(N2)) {
+ } else if (EVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
// PINSR* works with constant index.
return Op;
}
if (Subtarget->hasSSE41())
return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
- if (EVT == EVT::i8)
+ if (EVT == MVT::i8)
return SDValue();
DebugLoc dl = Op.getDebugLoc();
if (EVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
// Transform it so it match pinsrw which expects a 16-bit value in a GR32
// as its second argument.
- if (N1.getValueType() != EVT::i32)
- N1 = DAG.getNode(ISD::ANY_EXTEND, dl, EVT::i32, N1);
- if (N2.getValueType() != EVT::i32)
+ if (N1.getValueType() != MVT::i32)
+ N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
+ if (N2.getValueType() != MVT::i32)
N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
}
SDValue
X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
DebugLoc dl = Op.getDebugLoc();
- if (Op.getValueType() == EVT::v2f32)
- return DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v2f32,
- DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, EVT::v2i32,
- DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32,
+ if (Op.getValueType() == MVT::v2f32)
+ return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f32,
+ DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i32,
+ DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32,
Op.getOperand(0))));
- if (Op.getValueType() == EVT::v1i64 && Op.getOperand(0).getValueType() == EVT::i64)
- return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, EVT::v1i64, Op.getOperand(0));
+ if (Op.getValueType() == MVT::v1i64 && Op.getOperand(0).getValueType() == MVT::i64)
+ return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
- SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, EVT::i32, Op.getOperand(0));
- EVT VT = EVT::v2i32;
- switch (Op.getValueType().getSimpleVT()) {
+ SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
+ EVT VT = MVT::v2i32;
+ switch (Op.getValueType().getSimpleVT().SimpleTy) {
default: break;
- case EVT::v16i8:
- case EVT::v8i16:
- VT = EVT::v4i32;
+ case MVT::v16i8:
+ case MVT::v8i16:
+ VT = MVT::v4i32;
break;
}
return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(),
GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
unsigned char OperandFlags) {
- SDVTList NodeTys = DAG.getVTList(EVT::Other, EVT::Flag);
+ SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
DebugLoc dl = GA->getDebugLoc();
SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
GA->getValueType(0),
@@ -4675,7 +4678,7 @@ static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress,
DebugLoc::getUnknownLoc(), PtrVT,
DAG.getRegister(is64Bit? X86::FS : X86::GS,
- EVT::i32));
+ MVT::i32));
SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base,
NULL, 0);
SDValue ShOpHi = Op.getOperand(1);
SDValue ShAmt = Op.getOperand(2);
SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
- DAG.getConstant(VTBits - 1, EVT::i8))
+ DAG.getConstant(VTBits - 1, MVT::i8))
: DAG.getConstant(0, VT);
SDValue Tmp2, Tmp3;
Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
}
- SDValue AndNode = DAG.getNode(ISD::AND, dl, EVT::i8, ShAmt,
- DAG.getConstant(VTBits, EVT::i8));
+ SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
+ DAG.getConstant(VTBits, MVT::i8));
SDValue Cond = DAG.getNode(X86ISD::CMP, dl, VT,
- AndNode, DAG.getConstant(0, EVT::i8));
+ AndNode, DAG.getConstant(0, MVT::i8));
SDValue Hi, Lo;
- SDValue CC = DAG.getConstant(X86::COND_NE, EVT::i8);
+ SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
EVT SrcVT = Op.getOperand(0).getValueType();
if (SrcVT.isVector()) {
- if (SrcVT == EVT::v2i32 && Op.getValueType() == EVT::v2f64) {
+ if (SrcVT == MVT::v2i32 && Op.getValueType() == MVT::v2f64) {
return Op;
}
return SDValue();
}
- assert(SrcVT.getSimpleVT() <= EVT::i64 && SrcVT.getSimpleVT() >= EVT::i16 &&
+ assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
"Unknown SINT_TO_FP to lower!");
// These are really Legal; return the operand so the caller accepts it as
// Legal.
- if (SrcVT == EVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
+ if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
return Op;
- if (SrcVT == EVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
+ if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
Subtarget->is64Bit()) {
return Op;
}
SDVTList Tys;
bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
if (useSSE)
- Tys = DAG.getVTList(EVT::f64, EVT::Other, EVT::Flag);
+ Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
else
- Tys = DAG.getVTList(Op.getValueType(), EVT::Other);
+ Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
SmallVector<SDValue, 8> Ops;
Ops.push_back(Chain);
Ops.push_back(StackSlot);
MachineFunction &MF = DAG.getMachineFunction();
int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
- Tys = DAG.getVTList(EVT::Other);
+ Tys = DAG.getVTList(MVT::Other);
SmallVector<SDValue, 8> Ops;
Ops.push_back(Chain);
Ops.push_back(Result);
@@ -4923,31 +4926,31 @@ SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) {
Constant *C1 = ConstantVector::get(CV1);
SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
- SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, EVT::v4i32,
- DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32,
+ SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
+ DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
Op.getOperand(0),
DAG.getIntPtrConstant(1)));
- SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, EVT::v4i32,
- DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32,
+ SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
+ DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
Op.getOperand(0),
DAG.getIntPtrConstant(0)));
- SDValue Unpck1 = getUnpackl(DAG, dl, EVT::v4i32, XR1, XR2);
- SDValue CLod0 = DAG.getLoad(EVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
+ SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
+ SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
PseudoSourceValue::getConstantPool(), 0,
false, 16);
- SDValue Unpck2 = getUnpackl(DAG, dl, EVT::v4i32, Unpck1, CLod0);
- SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v2f64, Unpck2);
- SDValue CLod1 = DAG.getLoad(EVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
+ SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
+ SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2);
+ SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
PseudoSourceValue::getConstantPool(), 0,
false, 16);
- SDValue Sub = DAG.getNode(ISD::FSUB, dl, EVT::v2f64, XR2F, CLod1);
+ SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
// Add the halves; easiest way is to swap them into another reg first.
int ShufMask[2] = { 1, -1 };
- SDValue Shuf = DAG.getVectorShuffle(EVT::v2f64, dl, Sub,
- DAG.getUNDEF(EVT::v2f64), ShufMask);
- SDValue Add = DAG.getNode(ISD::FADD, dl, EVT::v2f64, Shuf, Sub);
- return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::f64, Add,
+ SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
+ DAG.getUNDEF(MVT::v2f64), ShufMask);
+ SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
+ return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
DAG.getIntPtrConstant(0));
}
@@ -4956,40 +4959,40 @@ SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) {
DebugLoc dl = Op.getDebugLoc();
// FP constant to bias correct the final result.
SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
- EVT::f64);
+ MVT::f64);
// Load the 32-bit value into an XMM register.
- SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, EVT::v4i32,
- DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32,
+ SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
+ DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
Op.getOperand(0),
DAG.getIntPtrConstant(0)));
- Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::f64,
- DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v2f64, Load),
+ Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
+ DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load),
DAG.getIntPtrConstant(0));
// Or the load with the bias.
- SDValue Or = DAG.getNode(ISD::OR, dl, EVT::v2i64,
- DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v2i64,
+ SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
+ DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
- EVT::v2f64, Load)),
- DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v2i64,
+ MVT::v2f64, Load)),
+ DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
- EVT::v2f64, Bias)));
- Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::f64,
- DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v2f64, Or),
+ MVT::v2f64, Bias)));
+ Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
+ DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or),
DAG.getIntPtrConstant(0));
// Subtract the bias.
- SDValue Sub = DAG.getNode(ISD::FSUB, dl, EVT::f64, Or, Bias);
+ SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
// Handle final rounding.
EVT DestVT = Op.getValueType();
- if (DestVT.bitsLT(EVT::f64)) {
+ if (DestVT.bitsLT(MVT::f64)) {
return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
DAG.getIntPtrConstant(0));
- } else if (DestVT.bitsGT(EVT::f64)) {
+ } else if (DestVT.bitsGT(MVT::f64)) {
return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
}
return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
EVT SrcVT = N0.getValueType();
- if (SrcVT == EVT::i64) {
+ if (SrcVT == MVT::i64) {
// We only handle SSE2 f64 target here; caller can expand the rest.
- if (Op.getValueType() != EVT::f64 || !X86ScalarSSEf64)
+ if (Op.getValueType() != MVT::f64 || !X86ScalarSSEf64)
return SDValue();
return LowerUINT_TO_FP_i64(Op, DAG);
- } else if (SrcVT == EVT::i32 && X86ScalarSSEf64) {
+ } else if (SrcVT == MVT::i32 && X86ScalarSSEf64) {
return LowerUINT_TO_FP_i32(Op, DAG);
}
- assert(SrcVT == EVT::i32 && "Unknown UINT_TO_FP to lower!");
+ assert(SrcVT == MVT::i32 && "Unknown UINT_TO_FP to lower!");
// Make a 64-bit buffer, and use it to build an FILD.
- SDValue StackSlot = DAG.CreateStackTemporary(EVT::i64);
+ SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
SDValue WordOff = DAG.getConstant(4, getPointerTy());
SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
getPointerTy(), StackSlot, WordOff);
SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
StackSlot, NULL, 0);
- SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, EVT::i32),
+ SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
OffsetSlot, NULL, 0);
- return BuildFILD(Op, EVT::i64, Store2, StackSlot, DAG);
+ return BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
}
std::pair<SDValue,SDValue> X86TargetLowering::
EVT DstTy = Op.getValueType();
if (!IsSigned) {
- assert(DstTy == EVT::i32 && "Unexpected FP_TO_UINT");
- DstTy = EVT::i64;
+ assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
+ DstTy = MVT::i64;
}
- assert(DstTy.getSimpleVT() <= EVT::i64 &&
- DstTy.getSimpleVT() >= EVT::i16 &&
+ assert(DstTy.getSimpleVT() <= MVT::i64 &&
+ DstTy.getSimpleVT() >= MVT::i16 &&
"Unknown FP_TO_SINT to lower!");
// These are really Legal.
- if (DstTy == EVT::i32 &&
+ if (DstTy == MVT::i32 &&
isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
return std::make_pair(SDValue(), SDValue());
if (Subtarget->is64Bit() &&
- DstTy == EVT::i64 &&
+ DstTy == MVT::i64 &&
isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
return std::make_pair(SDValue(), SDValue());
SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
unsigned Opc;
- switch (DstTy.getSimpleVT()) {
+ switch (DstTy.getSimpleVT().SimpleTy) {
default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
- case EVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
- case EVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
- case EVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
+ case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
+ case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
+ case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
}
SDValue Chain = DAG.getEntryNode();
SDValue Value = Op.getOperand(0);
if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
- assert(DstTy == EVT::i64 && "Invalid FP_TO_SINT to lower!");
+ assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
Chain = DAG.getStore(Chain, dl, Value, StackSlot,
PseudoSourceValue::getFixedStack(SSFI), 0);
- SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), EVT::Other);
+ SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
SDValue Ops[] = {
Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
};
// Build the FP_TO_INT*_IN_MEM
SDValue Ops[] = { Chain, Value, StackSlot };
- SDValue FIST = DAG.getNode(Opc, dl, EVT::Other, Ops, 3);
+ SDValue FIST = DAG.getNode(Opc, dl, MVT::Other, Ops, 3);
return std::make_pair(FIST, StackSlot);
}
SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
if (Op.getValueType().isVector()) {
- if (Op.getValueType() == EVT::v2i32 &&
- Op.getOperand(0).getValueType() == EVT::v2f64) {
+ if (Op.getValueType() == MVT::v2i32 &&
+ Op.getOperand(0).getValueType() == MVT::v2f64) {
return Op;
}
return SDValue();
if (VT.isVector())
EltVT = VT.getVectorElementType();
std::vector<Constant*> CV;
- if (EltVT == EVT::f64) {
+ if (EltVT == MVT::f64) {
Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
CV.push_back(C);
CV.push_back(C);
EltNum = VT.getVectorNumElements();
}
std::vector<Constant*> CV;
- if (EltVT == EVT::f64) {
+ if (EltVT == MVT::f64) {
Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
CV.push_back(C);
CV.push_back(C);
false, 16);
if (VT.isVector()) {
return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
- DAG.getNode(ISD::XOR, dl, EVT::v2i64,
- DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v2i64,
+ DAG.getNode(ISD::XOR, dl, MVT::v2i64,
+ DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
Op.getOperand(0)),
- DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v2i64, Mask)));
+ DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask)));
} else {
return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
}
// First get the sign bit of second operand.
std::vector<Constant*> CV;
- if (SrcVT == EVT::f64) {
+ if (SrcVT == MVT::f64) {
CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
} else {
// Shift sign bit right or left if the two operands have different types.
if (SrcVT.bitsGT(VT)) {
- // Op0 is EVT::f32, Op1 is EVT::f64.
- SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, EVT::v2f64, SignBit);
- SignBit = DAG.getNode(X86ISD::FSRL, dl, EVT::v2f64, SignBit,
- DAG.getConstant(32, EVT::i32));
- SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v4f32, SignBit);
- SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::f32, SignBit,
+ // Op0 is MVT::f32, Op1 is MVT::f64.
+ SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
+ SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
+ DAG.getConstant(32, MVT::i32));
+ SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit);
+ SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
DAG.getIntPtrConstant(0));
}
// Clear first operand sign bit.
CV.clear();
- if (VT == EVT::f64) {
+ if (VT == MVT::f64) {
CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
} else {
break;
}
if (Opcode != 0) {
- SDVTList VTs = DAG.getVTList(Op.getValueType(), EVT::i32);
+ SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
SmallVector<SDValue, 4> Ops;
for (unsigned i = 0; i != NumOperands; ++i)
Ops.push_back(Op.getOperand(i));
}
// Otherwise just emit a CMP with 0, which is the TEST pattern.
- return DAG.getNode(X86ISD::CMP, dl, EVT::i32, Op,
+ return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
DAG.getConstant(0, Op.getValueType()));
}
@@ -5366,11 +5369,11 @@ SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
return EmitTest(Op0, X86CC, DAG);
DebugLoc dl = Op0.getDebugLoc();
- return DAG.getNode(X86ISD::CMP, dl, EVT::i32, Op0, Op1);
+ return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
}
SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
- assert(Op.getValueType() == EVT::i8 && "SetCC type must be 8-bit integer");
+ assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
SDValue Op0 = Op.getOperand(0);
SDValue Op1 = Op.getOperand(1);
DebugLoc dl = Op.getDebugLoc();
// instruction. Since the shift amount is in-range-or-undefined, we know
// that doing a bittest on the i16 value is ok. We extend to i32 because
// the encoding for the i16 version is larger than the i32 version.
- if (LHS.getValueType() == EVT::i8)
- LHS = DAG.getNode(ISD::ANY_EXTEND, dl, EVT::i32, LHS);
+ if (LHS.getValueType() == MVT::i8)
+ LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
// If the operand types disagree, extend the shift amount to match. Since
// BT ignores high bits (like shifts) we can use anyextend.
if (LHS.getValueType() != RHS.getValueType())
RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
- SDValue BT = DAG.getNode(X86ISD::BT, dl, EVT::i32, LHS, RHS);
+ SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
- return DAG.getNode(X86ISD::SETCC, dl, EVT::i8,
- DAG.getConstant(Cond, EVT::i8), BT);
+ return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
+ DAG.getConstant(Cond, MVT::i8), BT);
}
}
unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG);
- return DAG.getNode(X86ISD::SETCC, dl, EVT::i8,
- DAG.getConstant(X86CC, EVT::i8), Cond);
+ return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
+ DAG.getConstant(X86CC, MVT::i8), Cond);
}
SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
if (isFP) {
unsigned SSECC = 8;
EVT VT0 = Op0.getValueType();
- assert(VT0 == EVT::v4f32 || VT0 == EVT::v2f64);
- unsigned Opc = VT0 == EVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
+ assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
+ unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
bool Swap = false;
switch (SetCCOpcode) {
if (SSECC == 8) {
if (SetCCOpcode == ISD::SETUEQ) {
SDValue UNORD, EQ;
- UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, EVT::i8));
- EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, EVT::i8));
+ UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
+ EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
}
else if (SetCCOpcode == ISD::SETONE) {
SDValue ORD, NEQ;
- ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, EVT::i8));
- NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, EVT::i8));
+ ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
+ NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
}
llvm_unreachable("Illegal FP comparison");
}
// Handle all other FP comparisons here.
- return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, EVT::i8));
+ return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
}
// We are handling one of the integer comparisons here. Since SSE only has
unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
bool Swap = false, Invert = false, FlipSigns = false;
- switch (VT.getSimpleVT()) {
+ switch (VT.getSimpleVT().SimpleTy) {
default: break;
- case EVT::v8i8:
- case EVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
- case EVT::v4i16:
- case EVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
- case EVT::v2i32:
- case EVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
- case EVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
+ case MVT::v8i8:
+ case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
+ case MVT::v4i16:
+ case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
+ case MVT::v2i32:
+ case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
+ case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
}
switch (SetCCOpcode) {
}
if (addTest) {
- CC = DAG.getConstant(X86::COND_NE, EVT::i8);
+ CC = DAG.getConstant(X86::COND_NE, MVT::i8);
Cond = EmitTest(Cond, X86::COND_NE, DAG);
}
- SDVTList VTs = DAG.getVTList(Op.getValueType(), EVT::Flag);
+ SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
SmallVector<SDValue, 4> Ops;
// X86ISD::CMOV means set the result (which is operand 1) to the RHS if
// condition is true.
X86::CondCode CCode =
(X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
CCode = X86::GetOppositeBranchCondition(CCode);
- CC = DAG.getConstant(CCode, EVT::i8);
+ CC = DAG.getConstant(CCode, MVT::i8);
SDValue User = SDValue(*Op.getNode()->use_begin(), 0);
// Look for an unconditional branch following this conditional branch.
// We need this because we need to reverse the successors in order
X86::CondCode CCode =
(X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
CCode = X86::GetOppositeBranchCondition(CCode);
- CC = DAG.getConstant(CCode, EVT::i8);
+ CC = DAG.getConstant(CCode, MVT::i8);
Cond = Cmp;
addTest = false;
}
X86::CondCode CCode =
(X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
CCode = X86::GetOppositeBranchCondition(CCode);
- CC = DAG.getConstant(CCode, EVT::i8);
+ CC = DAG.getConstant(CCode, MVT::i8);
Cond = Cond.getOperand(0).getOperand(1);
addTest = false;
}
}
if (addTest) {
- CC = DAG.getConstant(X86::COND_NE, EVT::i8);
+ CC = DAG.getConstant(X86::COND_NE, MVT::i8);
Cond = EmitTest(Cond, X86::COND_NE, DAG);
}
return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
SDValue Flag;
EVT IntPtr = getPointerTy();
- EVT SPTy = Subtarget->is64Bit() ? EVT::i64 : EVT::i32;
+ EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag);
Flag = Chain.getValue(1);
- SDVTList NodeTys = DAG.getVTList(EVT::Other, EVT::Flag);
+ SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
SDValue Ops[] = { Chain,
DAG.getTargetExternalSymbol("_alloca", IntPtr),
DAG.getRegister(X86::EAX, IntPtr),
// If the value is a constant, then we can potentially use larger sets.
switch (Align & 3) {
case 2: // WORD aligned
- AVT = EVT::i16;
+ AVT = MVT::i16;
ValReg = X86::AX;
Val = (Val << 8) | Val;
break;
case 0: // DWORD aligned
- AVT = EVT::i32;
+ AVT = MVT::i32;
ValReg = X86::EAX;
Val = (Val << 8) | Val;
Val = (Val << 16) | Val;
if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned
- AVT = EVT::i64;
+ AVT = MVT::i64;
ValReg = X86::RAX;
Val = (Val << 32) | Val;
}
break;
default: // Byte aligned
- AVT = EVT::i8;
+ AVT = MVT::i8;
ValReg = X86::AL;
Count = DAG.getIntPtrConstant(SizeVal);
break;
}
- if (AVT.bitsGT(EVT::i8)) {
+ if (AVT.bitsGT(MVT::i8)) {
unsigned UBytes = AVT.getSizeInBits() / 8;
Count = DAG.getIntPtrConstant(SizeVal / UBytes);
BytesLeft = SizeVal % UBytes;
InFlag);
InFlag = Chain.getValue(1);
} else {
- AVT = EVT::i8;
+ AVT = MVT::i8;
Count = DAG.getIntPtrConstant(SizeVal);
Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag);
InFlag = Chain.getValue(1);
Dst, InFlag);
InFlag = Chain.getValue(1);
- SDVTList Tys = DAG.getVTList(EVT::Other, EVT::Flag);
+ SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
SmallVector<SDValue, 8> Ops;
Ops.push_back(Chain);
Ops.push_back(DAG.getValueType(AVT));
Count = Size;
EVT CVT = Count.getValueType();
SDValue Left = DAG.getNode(ISD::AND, dl, CVT, Count,
- DAG.getConstant((AVT == EVT::i64) ? 7 : 3, CVT));
- Chain = DAG.getCopyToReg(Chain, dl, (CVT == EVT::i64) ? X86::RCX :
+ DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
+ Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX :
X86::ECX,
Left, InFlag);
InFlag = Chain.getValue(1);
- Tys = DAG.getVTList(EVT::Other, EVT::Flag);
+ Tys = DAG.getVTList(MVT::Other, MVT::Flag);
Ops.clear();
Ops.push_back(Chain);
- Ops.push_back(DAG.getValueType(EVT::i8));
+ Ops.push_back(DAG.getValueType(MVT::i8));
Ops.push_back(InFlag);
Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, &Ops[0], Ops.size());
} else if (BytesLeft) {
return SDValue();
// DWORD aligned
- EVT AVT = EVT::i32;
+ EVT AVT = MVT::i32;
if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) // QWORD aligned
- AVT = EVT::i64;
+ AVT = MVT::i64;
unsigned UBytes = AVT.getSizeInBits() / 8;
unsigned CountVal = SizeVal / UBytes;
Src, InFlag);
InFlag = Chain.getValue(1);
- SDVTList Tys = DAG.getVTList(EVT::Other, EVT::Flag);
+ SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
SmallVector<SDValue, 8> Ops;
Ops.push_back(Chain);
Ops.push_back(DAG.getValueType(AVT));
SrcSV, SrcSVOff + Offset));
}
- return DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&Results[0], Results.size());
}
SDValue FIN = Op.getOperand(1);
// Store gp_offset
SDValue Store = DAG.getStore(Op.getOperand(0), dl,
- DAG.getConstant(VarArgsGPOffset, EVT::i32),
+ DAG.getConstant(VarArgsGPOffset, MVT::i32),
FIN, SV, 0);
MemOps.push_back(Store);
FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
FIN, DAG.getIntPtrConstant(4));
Store = DAG.getStore(Op.getOperand(0), dl,
- DAG.getConstant(VarArgsFPOffset, EVT::i32),
+ DAG.getConstant(VarArgsFPOffset, MVT::i32),
FIN, SV, 0);
MemOps.push_back(Store);
SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
Store = DAG.getStore(Op.getOperand(0), dl, RSFIN, FIN, SV, 0);
MemOps.push_back(Store);
- return DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&MemOps[0], MemOps.size());
}
SDValue LHS = Op.getOperand(1);
SDValue RHS = Op.getOperand(2);
unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
- SDValue Cond = DAG.getNode(Opc, dl, EVT::i32, LHS, RHS);
- SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, EVT::i8,
- DAG.getConstant(X86CC, EVT::i8), Cond);
- return DAG.getNode(ISD::ZERO_EXTEND, dl, EVT::i32, SetCC);
+ SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
+ SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
+ DAG.getConstant(X86CC, MVT::i8), Cond);
+ return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
}
// ptest intrinsics. The intrinsic these come from are designed to return
// an integer value, not just an instruction so lower it to the ptest
SDValue LHS = Op.getOperand(1);
SDValue RHS = Op.getOperand(2);
- SDValue Test = DAG.getNode(X86ISD::PTEST, dl, EVT::i32, LHS, RHS);
- SDValue CC = DAG.getConstant(X86CC, EVT::i8);
- SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, EVT::i8, CC, Test);
- return DAG.getNode(ISD::ZERO_EXTEND, dl, EVT::i32, SetCC);
+ SDValue Test = DAG.getNode(X86ISD::PTEST, dl, MVT::i32, LHS, RHS);
+ SDValue CC = DAG.getConstant(X86CC, MVT::i8);
+ SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
+ return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
}
// Fix vector shift instructions where the last operand is a non-immediate
return SDValue();
unsigned NewIntNo = 0;
- EVT ShAmtVT = EVT::v4i32;
+ EVT ShAmtVT = MVT::v4i32;
switch (IntNo) {
case Intrinsic::x86_sse2_pslli_w:
NewIntNo = Intrinsic::x86_sse2_psll_w;
NewIntNo = Intrinsic::x86_sse2_psra_d;
break;
default: {
- ShAmtVT = EVT::v2i32;
+ ShAmtVT = MVT::v2i32;
switch (IntNo) {
case Intrinsic::x86_mmx_pslli_w:
NewIntNo = Intrinsic::x86_mmx_psll_w;
ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT,
DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, ShAmtVT, ShAmt));
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
- DAG.getConstant(NewIntNo, EVT::i32),
+ DAG.getConstant(NewIntNo, MVT::i32),
Op.getOperand(1), ShAmt);
}
}
SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
SDValue Offset =
DAG.getConstant(TD->getPointerSize(),
- Subtarget->is64Bit() ? EVT::i64 : EVT::i32);
+ Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
DAG.getNode(ISD::ADD, dl, getPointerTy(),
FrameAddr, Offset),
MF.getRegInfo().addLiveOut(StoreAddrReg);
return DAG.getNode(X86ISD::EH_RETURN, dl,
- EVT::Other,
+ MVT::Other,
Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
}
// Load the pointer to the nested function into R11.
unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
SDValue Addr = Trmp;
- OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, EVT::i16),
+ OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
Addr, TrmpAddr, 0);
- Addr = DAG.getNode(ISD::ADD, dl, EVT::i64, Trmp,
- DAG.getConstant(2, EVT::i64));
+ Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
+ DAG.getConstant(2, MVT::i64));
OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, TrmpAddr, 2, false, 2);
// Load the 'nest' parameter value into R10.
// R10 is specified in X86CallingConv.td
OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
- Addr = DAG.getNode(ISD::ADD, dl, EVT::i64, Trmp,
- DAG.getConstant(10, EVT::i64));
- OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, EVT::i16),
+ Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
+ DAG.getConstant(10, MVT::i64));
+ OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
Addr, TrmpAddr, 10);
- Addr = DAG.getNode(ISD::ADD, dl, EVT::i64, Trmp,
- DAG.getConstant(12, EVT::i64));
+ Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
+ DAG.getConstant(12, MVT::i64));
OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 12, false, 2);
// Jump to the nested function.
OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
- Addr = DAG.getNode(ISD::ADD, dl, EVT::i64, Trmp,
- DAG.getConstant(20, EVT::i64));
- OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, EVT::i16),
+ Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
+ DAG.getConstant(20, MVT::i64));
+ OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
Addr, TrmpAddr, 20);
unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
- Addr = DAG.getNode(ISD::ADD, dl, EVT::i64, Trmp,
- DAG.getConstant(22, EVT::i64));
- OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, EVT::i8), Addr,
+ Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
+ DAG.getConstant(22, MVT::i64));
+ OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
TrmpAddr, 22);
SDValue Ops[] =
- { Trmp, DAG.getNode(ISD::TokenFactor, dl, EVT::Other, OutChains, 6) };
+ { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
return DAG.getMergeValues(Ops, 2, dl);
} else {
const Function *Func =
SDValue OutChains[4];
SDValue Addr, Disp;
- Addr = DAG.getNode(ISD::ADD, dl, EVT::i32, Trmp,
- DAG.getConstant(10, EVT::i32));
- Disp = DAG.getNode(ISD::SUB, dl, EVT::i32, FPtr, Addr);
+ Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
+ DAG.getConstant(10, MVT::i32));
+ Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri);
const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
OutChains[0] = DAG.getStore(Root, dl,
- DAG.getConstant(MOV32ri|N86Reg, EVT::i8),
+ DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
Trmp, TrmpAddr, 0);
- Addr = DAG.getNode(ISD::ADD, dl, EVT::i32, Trmp,
- DAG.getConstant(1, EVT::i32));
+ Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
+ DAG.getConstant(1, MVT::i32));
OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1, false, 1);
const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP);
- Addr = DAG.getNode(ISD::ADD, dl, EVT::i32, Trmp,
- DAG.getConstant(5, EVT::i32));
- OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, EVT::i8), Addr,
+ Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
+ DAG.getConstant(5, MVT::i32));
+ OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
TrmpAddr, 5, false, 1);
- Addr = DAG.getNode(ISD::ADD, dl, EVT::i32, Trmp,
- DAG.getConstant(6, EVT::i32));
+ Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
+ DAG.getConstant(6, MVT::i32));
OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, TrmpAddr, 6, false, 1);
SDValue Ops[] =
- { Trmp, DAG.getNode(ISD::TokenFactor, dl, EVT::Other, OutChains, 4) };
+ { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
return DAG.getMergeValues(Ops, 2, dl);
}
}
@@ -6559,30 +6562,30 @@ SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment);
SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
- SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, EVT::Other,
+ SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, MVT::Other,
DAG.getEntryNode(), StackSlot);
// Load FP Control Word from stack slot
- SDValue CWD = DAG.getLoad(EVT::i16, dl, Chain, StackSlot, NULL, 0);
+ SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot, NULL, 0);
// Transform as necessary
SDValue CWD1 =
- DAG.getNode(ISD::SRL, dl, EVT::i16,
- DAG.getNode(ISD::AND, dl, EVT::i16,
- CWD, DAG.getConstant(0x800, EVT::i16)),
- DAG.getConstant(11, EVT::i8));
+ DAG.getNode(ISD::SRL, dl, MVT::i16,
+ DAG.getNode(ISD::AND, dl, MVT::i16,
+ CWD, DAG.getConstant(0x800, MVT::i16)),
+ DAG.getConstant(11, MVT::i8));
SDValue CWD2 =
- DAG.getNode(ISD::SRL, dl, EVT::i16,
- DAG.getNode(ISD::AND, dl, EVT::i16,
- CWD, DAG.getConstant(0x400, EVT::i16)),
- DAG.getConstant(9, EVT::i8));
+ DAG.getNode(ISD::SRL, dl, MVT::i16,
+ DAG.getNode(ISD::AND, dl, MVT::i16,
+ CWD, DAG.getConstant(0x400, MVT::i16)),
+ DAG.getConstant(9, MVT::i8));
SDValue RetVal =
- DAG.getNode(ISD::AND, dl, EVT::i16,
- DAG.getNode(ISD::ADD, dl, EVT::i16,
- DAG.getNode(ISD::OR, dl, EVT::i16, CWD1, CWD2),
- DAG.getConstant(1, EVT::i16)),
- DAG.getConstant(3, EVT::i16));
+ DAG.getNode(ISD::AND, dl, MVT::i16,
+ DAG.getNode(ISD::ADD, dl, MVT::i16,
+ DAG.getNode(ISD::OR, dl, MVT::i16, CWD1, CWD2),
+ DAG.getConstant(1, MVT::i16)),
+ DAG.getConstant(3, MVT::i16));
return DAG.getNode((VT.getSizeInBits() < 16 ?
DebugLoc dl = Op.getDebugLoc();
Op = Op.getOperand(0);
- if (VT == EVT::i8) {
+ if (VT == MVT::i8) {
// Zero extend to i32 since there is not an i8 bsr.
- OpVT = EVT::i32;
+ OpVT = MVT::i32;
Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
}
// Issue a bsr (scan bits in reverse) which also sets EFLAGS.
- SDVTList VTs = DAG.getVTList(OpVT, EVT::i32);
+ SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
// If src is zero (i.e. bsr sets ZF), returns NumBits.
SmallVector<SDValue, 4> Ops;
Ops.push_back(Op);
Ops.push_back(DAG.getConstant(NumBits+NumBits-1, OpVT));
- Ops.push_back(DAG.getConstant(X86::COND_E, EVT::i8));
+ Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
Ops.push_back(Op.getValue(1));
Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, &Ops[0], 4);
// Finally xor with NumBits-1.
Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
- if (VT == EVT::i8)
- Op = DAG.getNode(ISD::TRUNCATE, dl, EVT::i8, Op);
+ if (VT == MVT::i8)
+ Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
return Op;
}
DebugLoc dl = Op.getDebugLoc();
Op = Op.getOperand(0);
- if (VT == EVT::i8) {
- OpVT = EVT::i32;
+ if (VT == MVT::i8) {
+ OpVT = MVT::i32;
Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
}
// Issue a bsf (scan bits forward) which also sets EFLAGS.
- SDVTList VTs = DAG.getVTList(OpVT, EVT::i32);
+ SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
// If src is zero (i.e. bsf sets ZF), returns NumBits.
SmallVector<SDValue, 4> Ops;
Ops.push_back(Op);
Ops.push_back(DAG.getConstant(NumBits, OpVT));
- Ops.push_back(DAG.getConstant(X86::COND_E, EVT::i8));
+ Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
Ops.push_back(Op.getValue(1));
Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, &Ops[0], 4);
- if (VT == EVT::i8)
- Op = DAG.getNode(ISD::TRUNCATE, dl, EVT::i8, Op);
+ if (VT == MVT::i8)
+ Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
return Op;
}
SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) {
EVT VT = Op.getValueType();
- assert(VT == EVT::v2i64 && "Only know how to lower V2I64 multiply");
+ assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
DebugLoc dl = Op.getDebugLoc();
// ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
SDValue B = Op.getOperand(1);
SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
- DAG.getConstant(Intrinsic::x86_sse2_psrli_q, EVT::i32),
- A, DAG.getConstant(32, EVT::i32));
+ DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
+ A, DAG.getConstant(32, MVT::i32));
SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
- DAG.getConstant(Intrinsic::x86_sse2_psrli_q, EVT::i32),
- B, DAG.getConstant(32, EVT::i32));
+ DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
+ B, DAG.getConstant(32, MVT::i32));
SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
- DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, EVT::i32),
+ DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
A, B);
SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
- DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, EVT::i32),
+ DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
A, Bhi);
SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
- DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, EVT::i32),
+ DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
Ahi, B);
AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
- DAG.getConstant(Intrinsic::x86_sse2_pslli_q, EVT::i32),
- AloBhi, DAG.getConstant(32, EVT::i32));
+ DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
+ AloBhi, DAG.getConstant(32, MVT::i32));
AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
- DAG.getConstant(Intrinsic::x86_sse2_pslli_q, EVT::i32),
- AhiBlo, DAG.getConstant(32, EVT::i32));
+ DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
+ AhiBlo, DAG.getConstant(32, MVT::i32));
SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
return Res;
}
// Also sets EFLAGS.
- SDVTList VTs = DAG.getVTList(N->getValueType(0), EVT::i32);
+ SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS);
SDValue SetCC =
DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1),
- DAG.getConstant(Cond, EVT::i32), SDValue(Sum.getNode(), 1));
+ DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1));
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
return Sum;
DebugLoc dl = Op.getDebugLoc();
unsigned Reg = 0;
unsigned size = 0;
- switch(T.getSimpleVT()) {
+ switch(T.getSimpleVT().SimpleTy) {
default:
assert(false && "Invalid value type!");
- case EVT::i8: Reg = X86::AL; size = 1; break;
- case EVT::i16: Reg = X86::AX; size = 2; break;
- case EVT::i32: Reg = X86::EAX; size = 4; break;
- case EVT::i64:
+ case MVT::i8: Reg = X86::AL; size = 1; break;
+ case MVT::i16: Reg = X86::AX; size = 2; break;
+ case MVT::i32: Reg = X86::EAX; size = 4; break;
+ case MVT::i64:
assert(Subtarget->is64Bit() && "Node not type legal!");
Reg = X86::RAX; size = 8;
break;
SDValue Ops[] = { cpIn.getValue(0),
Op.getOperand(1),
Op.getOperand(3),
- DAG.getTargetConstant(size, EVT::i8),
+ DAG.getTargetConstant(size, MVT::i8),
cpIn.getValue(1) };
- SDVTList Tys = DAG.getVTList(EVT::Other, EVT::Flag);
+ SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5);
SDValue cpOut =
DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1));
SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
SelectionDAG &DAG) {
assert(Subtarget->is64Bit() && "Result not type legalized?");
- SDVTList Tys = DAG.getVTList(EVT::Other, EVT::Flag);
+ SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
SDValue TheChain = Op.getOperand(0);
DebugLoc dl = Op.getDebugLoc();
SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
- SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, EVT::i64, rd.getValue(1));
- SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, EVT::i64,
+ SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
+ SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
rax.getValue(2));
- SDValue Tmp = DAG.getNode(ISD::SHL, dl, EVT::i64, rdx,
- DAG.getConstant(32, EVT::i8));
+ SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
+ DAG.getConstant(32, MVT::i8));
SDValue Ops[] = {
- DAG.getNode(ISD::OR, dl, EVT::i64, rax, Tmp),
+ DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
rdx.getValue(1)
};
return DAG.getMergeValues(Ops, 2, dl);
SelectionDAG &DAG, unsigned NewOp) {
EVT T = Node->getValueType(0);
DebugLoc dl = Node->getDebugLoc();
- assert (T == EVT::i64 && "Only know how to expand i64 atomics");
+ assert (T == MVT::i64 && "Only know how to expand i64 atomics");
SDValue Chain = Node->getOperand(0);
SDValue In1 = Node->getOperand(1);
- SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32,
+ SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
Node->getOperand(2), DAG.getIntPtrConstant(0));
- SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32,
+ SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
Node->getOperand(2), DAG.getIntPtrConstant(1));
// This is a generalized SDNode, not an AtomicSDNode, so it doesn't
// have a MemOperand. Pass the info through as a normal operand.
SDValue LSI = DAG.getMemOperand(cast<MemSDNode>(Node)->getMemOperand());
SDValue Ops[] = { Chain, In1, In2L, In2H, LSI };
- SDVTList Tys = DAG.getVTList(EVT::i32, EVT::i32, EVT::Other);
+ SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
SDValue Result = DAG.getNode(NewOp, dl, Tys, Ops, 5);
SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
- Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, EVT::i64, OpsF, 2));
+ Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
Results.push_back(Result.getValue(2));
}
return;
}
case ISD::READCYCLECOUNTER: {
- SDVTList Tys = DAG.getVTList(EVT::Other, EVT::Flag);
+ SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
SDValue TheChain = N->getOperand(0);
SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
- SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, EVT::i32,
+ SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
rd.getValue(1));
- SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, EVT::i32,
+ SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
eax.getValue(2));
// Use a buildpair to merge the two 32-bit values into a 64-bit one.
SDValue Ops[] = { eax, edx };
- Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, EVT::i64, Ops, 2));
+ Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
Results.push_back(edx.getValue(1));
return;
}
case ISD::ATOMIC_CMP_SWAP: {
EVT T = N->getValueType(0);
- assert (T == EVT::i64 && "Only know how to expand i64 Cmp and Swap");
+ assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
SDValue cpInL, cpInH;
- cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32, N->getOperand(2),
- DAG.getConstant(0, EVT::i32));
- cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32, N->getOperand(2),
- DAG.getConstant(1, EVT::i32));
+ cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
+ DAG.getConstant(0, MVT::i32));
+ cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
+ DAG.getConstant(1, MVT::i32));
cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue());
cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH,
cpInL.getValue(1));
SDValue swapInL, swapInH;
- swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32, N->getOperand(3),
- DAG.getConstant(0, EVT::i32));
- swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32, N->getOperand(3),
- DAG.getConstant(1, EVT::i32));
+ swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
+ DAG.getConstant(0, MVT::i32));
+ swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
+ DAG.getConstant(1, MVT::i32));
swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL,
cpInH.getValue(1));
swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH,
SDValue Ops[] = { swapInH.getValue(0),
N->getOperand(1),
swapInH.getValue(1) };
- SDVTList Tys = DAG.getVTList(EVT::Other, EVT::Flag);
+ SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3);
SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX,
- EVT::i32, Result.getValue(1));
+ MVT::i32, Result.getValue(1));
SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX,
- EVT::i32, cpOutL.getValue(2));
+ MVT::i32, cpOutL.getValue(2));
SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
- Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, EVT::i64, OpsF, 2));
+ Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
Results.push_back(cpOutH.getValue(1));
return;
}
@@ -7161,12 +7164,12 @@ bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
// x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
- return VT1 == EVT::i32 && VT2 == EVT::i64 && Subtarget->is64Bit();
+ return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
}
bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
// i16 instructions are longer (0x66 prefix) and potentially slower.
- return !(VT1 == EVT::i32 && VT2 == EVT::i16);
+ return !(VT1 == MVT::i32 && VT2 == MVT::i16);
}
/// isShuffleMaskLegal - Targets can use this to indicate that they only
LD->getSrcValue(), LD->getSrcValueOffset(),
LD->isVolatile(), LD->getAlignment());
} else if (NumElems == 4 && LastLoadedElt == 1) {
- SDVTList Tys = DAG.getVTList(EVT::v2i64, EVT::Other);
+ SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
SDValue Ops[] = { LD->getChain(), LD->getBasePtr() };
SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2);
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, ResNode);
// If we have SSE[12] support, try to form min/max nodes.
if (Subtarget->hasSSE2() &&
- (LHS.getValueType() == EVT::f32 || LHS.getValueType() == EVT::f64) &&
+ (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
Cond.getOpcode() == ISD::SETCC) {
ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
unsigned ShAmt = TrueC->getAPIntValue().logBase2();
return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
- DAG.getConstant(ShAmt, EVT::i8));
+ DAG.getConstant(ShAmt, MVT::i8));
}
// Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
// Optimize cases that will turn into an LEA instruction. This requires
// an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
- if (N->getValueType(0) == EVT::i32 || N->getValueType(0) == EVT::i64) {
+ if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
- if (N->getValueType(0) == EVT::i32) Diff = (unsigned)Diff;
+ if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
bool isFastMultiplier = false;
if (Diff < 10) {
// shift amount.
if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
SDValue Cond = N->getOperand(3);
- Cond = DAG.getNode(X86ISD::SETCC, DL, EVT::i8,
- DAG.getConstant(CC, EVT::i8), Cond);
+ Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
+ DAG.getConstant(CC, MVT::i8), Cond);
// Zero extend the condition if needed.
Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
unsigned ShAmt = TrueC->getAPIntValue().logBase2();
Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
- DAG.getConstant(ShAmt, EVT::i8));
+ DAG.getConstant(ShAmt, MVT::i8));
if (N->getNumValues() == 2) // Dead flag value?
return DCI.CombineTo(N, Cond, SDValue());
return Cond;
// for any integer data type, including i8/i16.
if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
SDValue Cond = N->getOperand(3);
- Cond = DAG.getNode(X86ISD::SETCC, DL, EVT::i8,
- DAG.getConstant(CC, EVT::i8), Cond);
+ Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
+ DAG.getConstant(CC, MVT::i8), Cond);
// Zero extend the condition if needed.
Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
// Optimize cases that will turn into an LEA instruction. This requires
// an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
- if (N->getValueType(0) == EVT::i32 || N->getValueType(0) == EVT::i64) {
+ if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
- if (N->getValueType(0) == EVT::i32) Diff = (unsigned)Diff;
+ if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
bool isFastMultiplier = false;
if (Diff < 10) {
if (isFastMultiplier) {
APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
SDValue Cond = N->getOperand(3);
- Cond = DAG.getNode(X86ISD::SETCC, DL, EVT::i8,
- DAG.getConstant(CC, EVT::i8), Cond);
+ Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
+ DAG.getConstant(CC, MVT::i8), Cond);
// Zero extend the condition if needed.
Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
Cond);
return SDValue();
EVT VT = N->getValueType(0);
- if (VT != EVT::i64)
+ if (VT != MVT::i64)
return SDValue();
ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
SDValue NewMul;
if (isPowerOf2_64(MulAmt1))
NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
- DAG.getConstant(Log2_64(MulAmt1), EVT::i8));
+ DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
else
NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
DAG.getConstant(MulAmt1, VT));
if (isPowerOf2_64(MulAmt2))
NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
- DAG.getConstant(Log2_64(MulAmt2), EVT::i8));
+ DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
else
NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
DAG.getConstant(MulAmt2, VT));
return SDValue();
EVT VT = N->getValueType(0);
- if (VT != EVT::v2i64 && VT != EVT::v4i32 && VT != EVT::v8i16)
+ if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
return SDValue();
SDValue ShAmtOp = N->getOperand(1);
} else
return SDValue();
- if (EltVT.bitsGT(EVT::i32))
- BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, EVT::i32, BaseShAmt);
- else if (EltVT.bitsLT(EVT::i32))
- BaseShAmt = DAG.getNode(ISD::ANY_EXTEND, DL, EVT::i32, BaseShAmt);
+ if (EltVT.bitsGT(MVT::i32))
+ BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
+ else if (EltVT.bitsLT(MVT::i32))
+ BaseShAmt = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, BaseShAmt);
// The shift amount is identical so we can do a vector shift.
SDValue ValOp = N->getOperand(0);
llvm_unreachable("Unknown shift opcode!");
break;
case ISD::SHL:
- if (VT == EVT::v2i64)
+ if (VT == MVT::v2i64)
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
- DAG.getConstant(Intrinsic::x86_sse2_pslli_q, EVT::i32),
+ DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
ValOp, BaseShAmt);
- if (VT == EVT::v4i32)
+ if (VT == MVT::v4i32)
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
- DAG.getConstant(Intrinsic::x86_sse2_pslli_d, EVT::i32),
+ DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
ValOp, BaseShAmt);
- if (VT == EVT::v8i16)
+ if (VT == MVT::v8i16)
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
- DAG.getConstant(Intrinsic::x86_sse2_pslli_w, EVT::i32),
+ DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
ValOp, BaseShAmt);
break;
case ISD::SRA:
- if (VT == EVT::v4i32)
+ if (VT == MVT::v4i32)
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
- DAG.getConstant(Intrinsic::x86_sse2_psrai_d, EVT::i32),
+ DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
ValOp, BaseShAmt);
- if (VT == EVT::v8i16)
+ if (VT == MVT::v8i16)
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
- DAG.getConstant(Intrinsic::x86_sse2_psrai_w, EVT::i32),
+ DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
ValOp, BaseShAmt);
break;
case ISD::SRL:
- if (VT == EVT::v2i64)
+ if (VT == MVT::v2i64)
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
- DAG.getConstant(Intrinsic::x86_sse2_psrli_q, EVT::i32),
+ DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
ValOp, BaseShAmt);
- if (VT == EVT::v4i32)
+ if (VT == MVT::v4i32)
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
- DAG.getConstant(Intrinsic::x86_sse2_psrli_d, EVT::i32),
+ DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
ValOp, BaseShAmt);
- if (VT == EVT::v8i16)
+ if (VT == MVT::v8i16)
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
- DAG.getConstant(Intrinsic::x86_sse2_psrli_w, EVT::i32),
+ DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
ValOp, BaseShAmt);
break;
}
bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
&& Subtarget->hasSSE2();
if ((VT.isVector() ||
- (VT == EVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
+ (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
isa<LoadSDNode>(St->getValue()) &&
!cast<LoadSDNode>(St->getValue())->isVolatile() &&
St->getChain().hasOneUse() && !St->isVolatile()) {
// Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
// pair instead.
if (Subtarget->is64Bit() || F64IsLegal) {
- EVT LdVT = Subtarget->is64Bit() ? EVT::i64 : EVT::f64;
+ EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(),
Ld->getBasePtr(), Ld->getSrcValue(),
Ld->getSrcValueOffset(), Ld->isVolatile(),
SDValue NewChain = NewLd.getValue(1);
if (TokenFactorIndex != -1) {
Ops.push_back(NewChain);
- NewChain = DAG.getNode(ISD::TokenFactor, LdDL, EVT::Other, &Ops[0],
+ NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
Ops.size());
}
return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
// Otherwise, lower to two pairs of 32-bit loads / stores.
SDValue LoAddr = Ld->getBasePtr();
- SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, EVT::i32, LoAddr,
- DAG.getConstant(4, EVT::i32));
+ SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
+ DAG.getConstant(4, MVT::i32));
- SDValue LoLd = DAG.getLoad(EVT::i32, LdDL, Ld->getChain(), LoAddr,
+ SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
Ld->getSrcValue(), Ld->getSrcValueOffset(),
Ld->isVolatile(), Ld->getAlignment());
- SDValue HiLd = DAG.getLoad(EVT::i32, LdDL, Ld->getChain(), HiAddr,
+ SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
Ld->isVolatile(),
MinAlign(Ld->getAlignment(), 4));
if (TokenFactorIndex != -1) {
Ops.push_back(LoLd);
Ops.push_back(HiLd);
- NewChain = DAG.getNode(ISD::TokenFactor, LdDL, EVT::Other, &Ops[0],
+ NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
Ops.size());
}
LoAddr = St->getBasePtr();
- HiAddr = DAG.getNode(ISD::ADD, StDL, EVT::i32, LoAddr,
- DAG.getConstant(4, EVT::i32));
+ HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
+ DAG.getConstant(4, MVT::i32));
SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
St->getSrcValue(), St->getSrcValueOffset(),
St->getSrcValueOffset() + 4,
St->isVolatile(),
MinAlign(St->getAlignment(), 4));
- return DAG.getNode(ISD::TokenFactor, StDL, EVT::Other, LoSt, HiSt);
+ return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
}
return SDValue();
}
const ConstantInt *CI = C->getConstantIntValue();
if (CI->isValueValidForType(Type::Int32Ty, C->getSExtValue())) {
// Widen to 64 bits here to get it sign extended.
- Result = DAG.getTargetConstant(C->getSExtValue(), EVT::i64);
+ Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
break;
}
// FIXME gcc accepts some relocatable values here too, but only in certain
// Literal immediates are always ok.
if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
// Widen to 64 bits here to get it sign extended.
- Result = DAG.getTargetConstant(CST->getSExtValue(), EVT::i64);
+ Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
break;
}
default: break; // Unknown constraint letter
case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
if (Subtarget->is64Bit()) {
- if (VT == EVT::i32)
+ if (VT == MVT::i32)
return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
X86::ESI, X86::EDI, X86::R8D, X86::R9D,
X86::R10D,X86::R11D,X86::R12D,
X86::R13D,X86::R14D,X86::R15D,
X86::EBP, X86::ESP, 0);
- else if (VT == EVT::i16)
+ else if (VT == MVT::i16)
return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
X86::SI, X86::DI, X86::R8W,X86::R9W,
X86::R10W,X86::R11W,X86::R12W,
X86::R13W,X86::R14W,X86::R15W,
X86::BP, X86::SP, 0);
- else if (VT == EVT::i8)
+ else if (VT == MVT::i8)
return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL,
X86::SIL, X86::DIL, X86::R8B,X86::R9B,
X86::R10B,X86::R11B,X86::R12B,
X86::R13B,X86::R14B,X86::R15B,
X86::BPL, X86::SPL, 0);
- else if (VT == EVT::i64)
+ else if (VT == MVT::i64)
return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX,
X86::RSI, X86::RDI, X86::R8, X86::R9,
X86::R10, X86::R11, X86::R12,
}
// 32-bit fallthrough
case 'Q': // Q_REGS
- if (VT == EVT::i32)
+ if (VT == MVT::i32)
return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
- else if (VT == EVT::i16)
+ else if (VT == MVT::i16)
return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
- else if (VT == EVT::i8)
+ else if (VT == MVT::i8)
return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
- else if (VT == EVT::i64)
+ else if (VT == MVT::i64)
return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
break;
}
@@ -9042,19 +9045,19 @@ X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
case 'r': // GENERAL_REGS
case 'R': // LEGACY_REGS
case 'l': // INDEX_REGS
- if (VT == EVT::i8)
+ if (VT == MVT::i8)
return std::make_pair(0U, X86::GR8RegisterClass);
- if (VT == EVT::i16)
+ if (VT == MVT::i16)
return std::make_pair(0U, X86::GR16RegisterClass);
- if (VT == EVT::i32 || !Subtarget->is64Bit())
+ if (VT == MVT::i32 || !Subtarget->is64Bit())
return std::make_pair(0U, X86::GR32RegisterClass);
return std::make_pair(0U, X86::GR64RegisterClass);
case 'f': // FP Stack registers.
// If SSE is enabled for this VT, use f80 to ensure the isel moves the
// value to the correct fpstack register class.
- if (VT == EVT::f32 && !isScalarFPTypeInSSEReg(VT))
+ if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
return std::make_pair(0U, X86::RFP32RegisterClass);
- if (VT == EVT::f64 && !isScalarFPTypeInSSEReg(VT))
+ if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
return std::make_pair(0U, X86::RFP64RegisterClass);
return std::make_pair(0U, X86::RFP80RegisterClass);
case 'y': // MMX_REGS if MMX allowed.
@@ -9066,22 +9069,22 @@ X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
case 'x': // SSE_REGS if SSE1 allowed
if (!Subtarget->hasSSE1()) break;
- switch (VT.getSimpleVT()) {
+ switch (VT.getSimpleVT().SimpleTy) {
default: break;
// Scalar SSE types.
- case EVT::f32:
- case EVT::i32:
+ case MVT::f32:
+ case MVT::i32:
return std::make_pair(0U, X86::FR32RegisterClass);
- case EVT::f64:
- case EVT::i64:
+ case MVT::f64:
+ case MVT::i64:
return std::make_pair(0U, X86::FR64RegisterClass);
// Vector types.
- case EVT::v16i8:
- case EVT::v8i16:
- case EVT::v4i32:
- case EVT::v2i64:
- case EVT::v4f32:
- case EVT::v2f64:
+ case MVT::v16i8:
+ case MVT::v8i16:
+ case MVT::v4i32:
+ case MVT::v2i64:
+ case MVT::v4f32:
+ case MVT::v2f64:
return std::make_pair(0U, X86::VR128RegisterClass);
}
break;
@@ -9119,7 +9122,7 @@ X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
// really want an 8-bit or 32-bit register, map to the appropriate register
// class and return the appropriate register.
if (Res.second == X86::GR16RegisterClass) {
- if (VT == EVT::i8) {
+ if (VT == MVT::i8) {
unsigned DestReg = 0;
switch (Res.first) {
default: break;
@@ -9132,7 +9135,7 @@ X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
Res.first = DestReg;
Res.second = X86::GR8RegisterClass;
}
- } else if (VT == EVT::i32) {
+ } else if (VT == MVT::i32) {
unsigned DestReg = 0;
switch (Res.first) {
default: break;
@@ -9149,7 +9152,7 @@ X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
Res.first = DestReg;
Res.second = X86::GR32RegisterClass;
}
- } else if (VT == EVT::i64) {
+ } else if (VT == MVT::i64) {
unsigned DestReg = 0;
switch (Res.first) {
default: break;
@@ -9174,9 +9177,9 @@ X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
// wrong class. This can happen with constraints like {xmm0} where the
// target independent register mapper will just pick the first match it can
// find, ignoring the required type.
- if (VT == EVT::f32)
+ if (VT == MVT::f32)
Res.second = X86::FR32RegisterClass;
- else if (VT == EVT::f64)
+ else if (VT == MVT::f64)
Res.second = X86::FR64RegisterClass;
else if (X86::VR128RegisterClass->hasType(VT))
Res.second = X86::VR128RegisterClass;
@@ -9191,7 +9194,7 @@ X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
/// getWidenVectorType: given a vector type, returns the type to widen
/// to (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
-/// If there is no vector type that we want to widen to, returns EVT::Other
+/// If there is no vector type that we want to widen to, returns MVT::Other
/// When and where to widen is target dependent based on the cost of
/// scalarizing vs using the wider vector type.
// On X86, it make sense to widen any vector wider than 1
if (NElts <= 1)
- return EVT::Other;
+ return MVT::Other;
- for (unsigned nVT = EVT::FIRST_VECTOR_VALUETYPE;
- nVT <= EVT::LAST_VECTOR_VALUETYPE; ++nVT) {
- EVT SVT = (EVT::SimpleValueType)nVT;
+ for (unsigned nVT = MVT::FIRST_VECTOR_VALUETYPE;
+ nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
+ EVT SVT = (MVT::SimpleValueType)nVT;
if (isTypeLegal(SVT) &&
SVT.getVectorElementType() == EltVT &&
SVT.getVectorNumElements() > NElts)
return SVT;
}
- return EVT::Other;
+ return MVT::Other;
}
index d9c745b3b30f21fb60eb1fe142fe0aecf514b095..9e6cd819e1646a6b8a2fe80801df45ecc5e93a9f 100644 (file)
virtual const char *getTargetNodeName(unsigned Opcode) const;
/// getSetCCResultType - Return the ISD::SETCC ValueType
- virtual EVT::SimpleValueType getSetCCResultType(EVT VT) const;
+ virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const;
/// computeMaskedBitsForTargetNode - Determine which of the bits specified
/// in Mask are known to be either zero or one and return them in the
// Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
// expensive than a straight movsd. On the other hand, it's important to
// shrink long double fp constant since fldt is very slow.
- return !X86ScalarSSEf64 || VT == EVT::f80;
+ return !X86ScalarSSEf64 || VT == MVT::f80;
}
/// IsEligibleForTailCallOptimization - Check whether the call is eligible
/// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
/// computed in an SSE register, not on the X87 floating point stack.
bool isScalarFPTypeInSSEReg(EVT VT) const {
- return (VT == EVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
- (VT == EVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
+ return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
+ (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
}
/// getWidenVectorType: given a vector type, returns the type to widen
index 1b1c093e4eb863a097328b8abd154cfdc2219550..297c4dd175c4b366dcf77989f4930595aa12a82a 100644 (file)
bool isAligned = (RI.getStackAlignment() >= 16) ||
RI.needsStackRealignment(MF);
Load = DAG.getTargetNode(getLoadRegOpcode(0, RC, isAligned, TM), dl,
- VT, EVT::Other, &AddrOps[0], AddrOps.size());
+ VT, MVT::Other, &AddrOps[0], AddrOps.size());
NewNodes.push_back(Load);
}
}
for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
EVT VT = N->getValueType(i);
- if (VT != EVT::Other && i >= (unsigned)TID.getNumDefs())
+ if (VT != MVT::Other && i >= (unsigned)TID.getNumDefs())
VTs.push_back(VT);
}
if (Load)
RI.needsStackRealignment(MF);
SDNode *Store = DAG.getTargetNode(getStoreRegOpcode(0, DstRC,
isAligned, TM),
- dl, EVT::Other,
+ dl, MVT::Other,
&AddrOps[0], AddrOps.size());
NewNodes.push_back(Store);
}
index 09457a13b8677878303391e5c75206c947427926..757451635bdde9573cde6d9245d1e94d03f1bffd 100644 (file)
namespace llvm {
unsigned getX86SubSuperRegister(unsigned Reg, EVT VT, bool High) {
- switch (VT.getSimpleVT()) {
+ switch (VT.getSimpleVT().SimpleTy) {
default: return Reg;
- case EVT::i8:
+ case MVT::i8:
if (High) {
switch (Reg) {
default: return 0;
return X86::R15B;
}
}
- case EVT::i16:
+ case MVT::i16:
switch (Reg) {
default: return Reg;
case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
return X86::R15W;
}
- case EVT::i32:
+ case MVT::i32:
switch (Reg) {
default: return Reg;
case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
return X86::R15D;
}
- case EVT::i64:
+ case MVT::i64:
switch (Reg) {
default: return Reg;
case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
index 750747d7d205990ad026954747f69d1e687eaa80..5d6702b4dadd3aba66562b287b447fcd80d1a446 100644 (file)
/// getI32Imm - Return a target constant with the specified value, of type
/// i32.
inline SDValue getI32Imm(unsigned Imm) {
- return CurDAG->getTargetConstant(Imm, EVT::i32);
+ return CurDAG->getTargetConstant(Imm, MVT::i32);
}
// Complex Pattern Selectors.
SDValue &Base, SDValue &Offset) {
FrameIndexSDNode *FIN = 0;
if ((FIN = dyn_cast<FrameIndexSDNode>(Addr))) {
- Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), EVT::i32);
- Offset = CurDAG->getTargetConstant(0, EVT::i32);
+ Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
+ Offset = CurDAG->getTargetConstant(0, MVT::i32);
return true;
}
if (Addr.getOpcode() == ISD::ADD) {
&& (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
&& (CN->getSExtValue() % 4 == 0 && CN->getSExtValue() >= 0)) {
// Constant positive word offset from frame index
- Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), EVT::i32);
- Offset = CurDAG->getTargetConstant(CN->getSExtValue(), EVT::i32);
+ Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
+ Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32);
return true;
}
}
SDValue &Base, SDValue &Offset) {
if (Addr.getOpcode() == XCoreISD::DPRelativeWrapper) {
Base = Addr.getOperand(0);
- Offset = CurDAG->getTargetConstant(0, EVT::i32);
+ Offset = CurDAG->getTargetConstant(0, MVT::i32);
return true;
}
if (Addr.getOpcode() == ISD::ADD) {
&& (CN->getSExtValue() % 4 == 0)) {
// Constant word offset from a object in the data region
Base = Addr.getOperand(0).getOperand(0);
- Offset = CurDAG->getTargetConstant(CN->getSExtValue(), EVT::i32);
+ Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32);
return true;
}
}
SDValue &Base, SDValue &Offset) {
if (Addr.getOpcode() == XCoreISD::CPRelativeWrapper) {
Base = Addr.getOperand(0);
- Offset = CurDAG->getTargetConstant(0, EVT::i32);
+ Offset = CurDAG->getTargetConstant(0, MVT::i32);
return true;
}
if (Addr.getOpcode() == ISD::ADD) {
&& (CN->getSExtValue() % 4 == 0)) {
// Constant word offset from a object in the data region
Base = Addr.getOperand(0).getOperand(0);
- Offset = CurDAG->getTargetConstant(CN->getSExtValue(), EVT::i32);
+ Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32);
return true;
}
}
SDNode *N = Op.getNode();
DebugLoc dl = N->getDebugLoc();
EVT NVT = N->getValueType(0);
- if (NVT == EVT::i32) {
+ if (NVT == MVT::i32) {
switch (N->getOpcode()) {
default: break;
case ISD::Constant: {
if (Predicate_immMskBitp(N)) {
SDValue MskSize = Transform_msksize_xform(N);
- return CurDAG->getTargetNode(XCore::MKMSK_rus, dl, EVT::i32, MskSize);
+ return CurDAG->getTargetNode(XCore::MKMSK_rus, dl, MVT::i32, MskSize);
}
else if (! Predicate_immU16(N)) {
unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
SDValue CPIdx =
CurDAG->getTargetConstantPool(ConstantInt::get(Type::Int32Ty, Val),
TLI.getPointerTy());
- return CurDAG->getTargetNode(XCore::LDWCP_lru6, dl, EVT::i32,
- EVT::Other, CPIdx,
+ return CurDAG->getTargetNode(XCore::LDWCP_lru6, dl, MVT::i32,
+ MVT::Other, CPIdx,
CurDAG->getEntryNode());
}
break;
case ISD::SMUL_LOHI: {
// FIXME fold addition into the macc instruction
if (!Subtarget.isXS1A()) {
- SDValue Zero(CurDAG->getTargetNode(XCore::LDC_ru6, dl, EVT::i32,
- CurDAG->getTargetConstant(0, EVT::i32)), 0);
+ SDValue Zero(CurDAG->getTargetNode(XCore::LDC_ru6, dl, MVT::i32,
+ CurDAG->getTargetConstant(0, MVT::i32)), 0);
SDValue Ops[] = { Zero, Zero, Op.getOperand(0), Op.getOperand(1) };
SDNode *ResNode = CurDAG->getTargetNode(XCore::MACCS_l4r, dl,
- EVT::i32, EVT::i32, Ops, 4);
+ MVT::i32, MVT::i32, Ops, 4);
ReplaceUses(SDValue(N, 0), SDValue(ResNode, 1));
ReplaceUses(SDValue(N, 1), SDValue(ResNode, 0));
return NULL;
}
case ISD::UMUL_LOHI: {
// FIXME fold addition into the macc / lmul instruction
- SDValue Zero(CurDAG->getTargetNode(XCore::LDC_ru6, dl, EVT::i32,
- CurDAG->getTargetConstant(0, EVT::i32)), 0);
+ SDValue Zero(CurDAG->getTargetNode(XCore::LDC_ru6, dl, MVT::i32,
+ CurDAG->getTargetConstant(0, MVT::i32)), 0);
SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
Zero, Zero };
- SDNode *ResNode = CurDAG->getTargetNode(XCore::LMUL_l6r, dl, EVT::i32,
- EVT::i32, Ops, 4);
+ SDNode *ResNode = CurDAG->getTargetNode(XCore::LMUL_l6r, dl, MVT::i32,
+ MVT::i32, Ops, 4);
ReplaceUses(SDValue(N, 0), SDValue(ResNode, 1));
ReplaceUses(SDValue(N, 1), SDValue(ResNode, 0));
return NULL;
if (!Subtarget.isXS1A()) {
SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
Op.getOperand(2) };
- return CurDAG->getTargetNode(XCore::LADD_l5r, dl, EVT::i32, EVT::i32,
+ return CurDAG->getTargetNode(XCore::LADD_l5r, dl, MVT::i32, MVT::i32,
Ops, 3);
}
break;
if (!Subtarget.isXS1A()) {
SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
Op.getOperand(2) };
- return CurDAG->getTargetNode(XCore::LSUB_l5r, dl, EVT::i32, EVT::i32,
+ return CurDAG->getTargetNode(XCore::LSUB_l5r, dl, MVT::i32, MVT::i32,
Ops, 3);
}
break;
index cc1f1f71055d54598928961f478f7a4a1f2307f9..25077c748d79ee71cb63fbd13e766f3d4dd628de 100644 (file)
Subtarget(*XTM.getSubtargetImpl()) {
// Set up the register classes.
- addRegisterClass(EVT::i32, XCore::GRRegsRegisterClass);
+ addRegisterClass(MVT::i32, XCore::GRRegsRegisterClass);
// Compute derived properties from the register classes
computeRegisterProperties();
// Division is expensive
setIntDivIsCheap(false);
- setShiftAmountType(EVT::i32);
+ setShiftAmountType(MVT::i32);
setStackPointerRegisterToSaveRestore(XCore::SP);
setSchedulingPreference(SchedulingForRegPressure);
setBooleanContents(ZeroOrOneBooleanContent);
// XCore does not have the NodeTypes below.
- setOperationAction(ISD::BR_CC, EVT::Other, Expand);
- setOperationAction(ISD::SELECT_CC, EVT::i32, Custom);
- setOperationAction(ISD::ADDC, EVT::i32, Expand);
- setOperationAction(ISD::ADDE, EVT::i32, Expand);
- setOperationAction(ISD::SUBC, EVT::i32, Expand);
- setOperationAction(ISD::SUBE, EVT::i32, Expand);
+ setOperationAction(ISD::BR_CC, MVT::Other, Expand);
+ setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
+ setOperationAction(ISD::ADDC, MVT::i32, Expand);
+ setOperationAction(ISD::ADDE, MVT::i32, Expand);
+ setOperationAction(ISD::SUBC, MVT::i32, Expand);
+ setOperationAction(ISD::SUBE, MVT::i32, Expand);
// Stop the combiner recombining select and set_cc
- setOperationAction(ISD::SELECT_CC, EVT::Other, Expand);
+ setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
// 64bit
if (!Subtarget.isXS1A()) {
- setOperationAction(ISD::ADD, EVT::i64, Custom);
- setOperationAction(ISD::SUB, EVT::i64, Custom);
+ setOperationAction(ISD::ADD, MVT::i64, Custom);
+ setOperationAction(ISD::SUB, MVT::i64, Custom);
}
if (Subtarget.isXS1A()) {
- setOperationAction(ISD::SMUL_LOHI, EVT::i32, Expand);
+ setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
}
- setOperationAction(ISD::MULHS, EVT::i32, Expand);
- setOperationAction(ISD::MULHU, EVT::i32, Expand);
- setOperationAction(ISD::SHL_PARTS, EVT::i32, Expand);
- setOperationAction(ISD::SRA_PARTS, EVT::i32, Expand);
- setOperationAction(ISD::SRL_PARTS, EVT::i32, Expand);
+ setOperationAction(ISD::MULHS, MVT::i32, Expand);
+ setOperationAction(ISD::MULHU, MVT::i32, Expand);
+ setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
+ setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
+ setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
// Bit Manipulation
- setOperationAction(ISD::CTPOP, EVT::i32, Expand);
- setOperationAction(ISD::ROTL , EVT::i32, Expand);
- setOperationAction(ISD::ROTR , EVT::i32, Expand);
+ setOperationAction(ISD::CTPOP, MVT::i32, Expand);
+ setOperationAction(ISD::ROTL , MVT::i32, Expand);
+ setOperationAction(ISD::ROTR , MVT::i32, Expand);
- setOperationAction(ISD::TRAP, EVT::Other, Legal);
+ setOperationAction(ISD::TRAP, MVT::Other, Legal);
// Expand jump tables for now
- setOperationAction(ISD::BR_JT, EVT::Other, Expand);
- setOperationAction(ISD::JumpTable, EVT::i32, Custom);
+ setOperationAction(ISD::BR_JT, MVT::Other, Expand);
+ setOperationAction(ISD::JumpTable, MVT::i32, Custom);
- setOperationAction(ISD::GlobalAddress, EVT::i32, Custom);
+ setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
// Thread Local Storage
- setOperationAction(ISD::GlobalTLSAddress, EVT::i32, Custom);
+ setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
// Conversion of i64 -> double produces constantpool nodes
- setOperationAction(ISD::ConstantPool, EVT::i32, Custom);
+ setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
// Loads
- setLoadExtAction(ISD::EXTLOAD, EVT::i1, Promote);
- setLoadExtAction(ISD::ZEXTLOAD, EVT::i1, Promote);
- setLoadExtAction(ISD::SEXTLOAD, EVT::i1, Promote);
+ setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
+ setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
+ setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
- setLoadExtAction(ISD::SEXTLOAD, EVT::i8, Expand);
- setLoadExtAction(ISD::ZEXTLOAD, EVT::i16, Expand);
+ setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
+ setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Expand);
// Custom expand misaligned loads / stores.
- setOperationAction(ISD::LOAD, EVT::i32, Custom);
- setOperationAction(ISD::STORE, EVT::i32, Custom);
+ setOperationAction(ISD::LOAD, MVT::i32, Custom);
+ setOperationAction(ISD::STORE, MVT::i32, Custom);
// Varargs
- setOperationAction(ISD::VAEND, EVT::Other, Expand);
- setOperationAction(ISD::VACOPY, EVT::Other, Expand);
- setOperationAction(ISD::VAARG, EVT::Other, Custom);
- setOperationAction(ISD::VASTART, EVT::Other, Custom);
+ setOperationAction(ISD::VAEND, MVT::Other, Expand);
+ setOperationAction(ISD::VACOPY, MVT::Other, Expand);
+ setOperationAction(ISD::VAARG, MVT::Other, Custom);
+ setOperationAction(ISD::VASTART, MVT::Other, Custom);
// Dynamic stack
- setOperationAction(ISD::STACKSAVE, EVT::Other, Expand);
- setOperationAction(ISD::STACKRESTORE, EVT::Other, Expand);
- setOperationAction(ISD::DYNAMIC_STACKALLOC, EVT::i32, Expand);
+ setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
+ setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
+ setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
// Debug
- setOperationAction(ISD::DBG_STOPPOINT, EVT::Other, Expand);
- setOperationAction(ISD::DEBUG_LOC, EVT::Other, Expand);
+ setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
+ setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
maxStoresPerMemset = 4;
maxStoresPerMemmove = maxStoresPerMemcpy = 2;
LowerSELECT_CC(SDValue Op, SelectionDAG &DAG)
{
DebugLoc dl = Op.getDebugLoc();
- SDValue Cond = DAG.getNode(ISD::SETCC, dl, EVT::i32, Op.getOperand(2),
+ SDValue Cond = DAG.getNode(ISD::SETCC, dl, MVT::i32, Op.getOperand(2),
Op.getOperand(3), Op.getOperand(4));
- return DAG.getNode(ISD::SELECT, dl, EVT::i32, Cond, Op.getOperand(0),
+ return DAG.getNode(ISD::SELECT, dl, MVT::i32, Cond, Op.getOperand(0),
Op.getOperand(1));
}
// FIXME there is no actual debug info here
DebugLoc dl = GA.getDebugLoc();
if (isa<Function>(GV)) {
- return DAG.getNode(XCoreISD::PCRelativeWrapper, dl, EVT::i32, GA);
+ return DAG.getNode(XCoreISD::PCRelativeWrapper, dl, MVT::i32, GA);
} else if (!Subtarget.isXS1A()) {
const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
if (!GVar) {
}
bool isConst = GVar && GVar->isConstant();
if (isConst) {
- return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, EVT::i32, GA);
+ return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, GA);
}
}
- return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, EVT::i32, GA);
+ return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, MVT::i32, GA);
}
SDValue XCoreTargetLowering::
LowerGlobalAddress(SDValue Op, SelectionDAG &DAG)
{
GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
- SDValue GA = DAG.getTargetGlobalAddress(GV, EVT::i32);
+ SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
// If it's a debug information descriptor, don't mess with it.
if (DAG.isVerifiedDebugInfoDesc(Op))
return GA;
}
static inline SDValue BuildGetId(SelectionDAG &DAG, DebugLoc dl) {
- return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, EVT::i32,
- DAG.getConstant(Intrinsic::xcore_getid, EVT::i32));
+ return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
+ DAG.getConstant(Intrinsic::xcore_getid, MVT::i32));
}
static inline bool isZeroLengthArray(const Type *Ty) {
DebugLoc dl = Op.getDebugLoc();
// transform to label + getid() * size
GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
- SDValue GA = DAG.getTargetGlobalAddress(GV, EVT::i32);
+ SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
if (!GVar) {
// If GV is an alias then use the aliasee to determine size
SDValue base = getGlobalAddressWrapper(GA, GV, DAG);
const TargetData *TD = TM.getTargetData();
unsigned Size = TD->getTypeAllocSize(Ty);
- SDValue offset = DAG.getNode(ISD::MUL, dl, EVT::i32, BuildGetId(DAG, dl),
- DAG.getConstant(Size, EVT::i32));
- return DAG.getNode(ISD::ADD, dl, EVT::i32, base, offset);
+ SDValue offset = DAG.getNode(ISD::MUL, dl, MVT::i32, BuildGetId(DAG, dl),
+ DAG.getConstant(Size, MVT::i32));
+ return DAG.getNode(ISD::ADD, dl, MVT::i32, base, offset);
}
SDValue XCoreTargetLowering::
Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
CP->getAlignment());
}
- return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, EVT::i32, Res);
+ return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, Res);
}
}
EVT PtrVT = Op.getValueType();
JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
- return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, EVT::i32, JTI);
+ return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, MVT::i32, JTI);
}
static bool
{
LoadSDNode *LD = cast<LoadSDNode>(Op);
assert(LD->getExtensionType() == ISD::NON_EXTLOAD && "Unexpected extension type");
- assert(LD->getMemoryVT() == EVT::i32 && "Unexpected load EVT");
+ assert(LD->getMemoryVT() == MVT::i32 && "Unexpected load EVT");
if (allowsUnalignedMemoryAccesses()) {
return SDValue();
}
// shr low_shifted, low, (offset & 0x3) * 8
// shl high_shifted, high, 32 - (offset & 0x3) * 8
// or result, low_shifted, high_shifted
- SDValue LowOffset = DAG.getConstant(Offset & ~0x3, EVT::i32);
- SDValue HighOffset = DAG.getConstant((Offset & ~0x3) + 4, EVT::i32);
- SDValue LowShift = DAG.getConstant((Offset & 0x3) * 8, EVT::i32);
- SDValue HighShift = DAG.getConstant(32 - (Offset & 0x3) * 8, EVT::i32);
+ SDValue LowOffset = DAG.getConstant(Offset & ~0x3, MVT::i32);
+ SDValue HighOffset = DAG.getConstant((Offset & ~0x3) + 4, MVT::i32);
+ SDValue LowShift = DAG.getConstant((Offset & 0x3) * 8, MVT::i32);
+ SDValue HighShift = DAG.getConstant(32 - (Offset & 0x3) * 8, MVT::i32);
- SDValue LowAddr = DAG.getNode(ISD::ADD, dl, EVT::i32, Base, LowOffset);
- SDValue HighAddr = DAG.getNode(ISD::ADD, dl, EVT::i32, Base, HighOffset);
+ SDValue LowAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, Base, LowOffset);
+ SDValue HighAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, Base, HighOffset);
SDValue Low = DAG.getLoad(getPointerTy(), dl, Chain,
LowAddr, NULL, 4);
SDValue High = DAG.getLoad(getPointerTy(), dl, Chain,
HighAddr, NULL, 4);
- SDValue LowShifted = DAG.getNode(ISD::SRL, dl, EVT::i32, Low, LowShift);
- SDValue HighShifted = DAG.getNode(ISD::SHL, dl, EVT::i32, High, HighShift);
- SDValue Result = DAG.getNode(ISD::OR, dl, EVT::i32, LowShifted, HighShifted);
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Low.getValue(1),
+ SDValue LowShifted = DAG.getNode(ISD::SRL, dl, MVT::i32, Low, LowShift);
+ SDValue HighShifted = DAG.getNode(ISD::SHL, dl, MVT::i32, High, HighShift);
+ SDValue Result = DAG.getNode(ISD::OR, dl, MVT::i32, LowShifted, HighShifted);
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Low.getValue(1),
High.getValue(1));
SDValue Ops[] = { Result, Chain };
return DAG.getMergeValues(Ops, 2, dl);
if (LD->getAlignment() == 2) {
int SVOffset = LD->getSrcValueOffset();
- SDValue Low = DAG.getExtLoad(ISD::ZEXTLOAD, dl, EVT::i32, Chain,
- BasePtr, LD->getSrcValue(), SVOffset, EVT::i16,
+ SDValue Low = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, Chain,
+ BasePtr, LD->getSrcValue(), SVOffset, MVT::i16,
LD->isVolatile(), 2);
- SDValue HighAddr = DAG.getNode(ISD::ADD, dl, EVT::i32, BasePtr,
- DAG.getConstant(2, EVT::i32));
- SDValue High = DAG.getExtLoad(ISD::EXTLOAD, dl, EVT::i32, Chain,
+ SDValue HighAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, BasePtr,
+ DAG.getConstant(2, MVT::i32));
+ SDValue High = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::i32, Chain,
HighAddr, LD->getSrcValue(), SVOffset + 2,
- EVT::i16, LD->isVolatile(), 2);
- SDValue HighShifted = DAG.getNode(ISD::SHL, dl, EVT::i32, High,
- DAG.getConstant(16, EVT::i32));
- SDValue Result = DAG.getNode(ISD::OR, dl, EVT::i32, Low, HighShifted);
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Low.getValue(1),
+ MVT::i16, LD->isVolatile(), 2);
+ SDValue HighShifted = DAG.getNode(ISD::SHL, dl, MVT::i32, High,
+ DAG.getConstant(16, MVT::i32));
+ SDValue Result = DAG.getNode(ISD::OR, dl, MVT::i32, Low, HighShifted);
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Low.getValue(1),
High.getValue(1));
SDValue Ops[] = { Result, Chain };
return DAG.getMergeValues(Ops, 2, dl);
{
StoreSDNode *ST = cast<StoreSDNode>(Op);
assert(!ST->isTruncatingStore() && "Unexpected store type");
- assert(ST->getMemoryVT() == EVT::i32 && "Unexpected store EVT");
+ assert(ST->getMemoryVT() == MVT::i32 && "Unexpected store EVT");
if (allowsUnalignedMemoryAccesses()) {
return SDValue();
}
if (ST->getAlignment() == 2) {
int SVOffset = ST->getSrcValueOffset();
SDValue Low = Value;
- SDValue High = DAG.getNode(ISD::SRL, dl, EVT::i32, Value,
- DAG.getConstant(16, EVT::i32));
+ SDValue High = DAG.getNode(ISD::SRL, dl, MVT::i32, Value,
+ DAG.getConstant(16, MVT::i32));
SDValue StoreLow = DAG.getTruncStore(Chain, dl, Low, BasePtr,
- ST->getSrcValue(), SVOffset, EVT::i16,
+ ST->getSrcValue(), SVOffset, MVT::i16,
ST->isVolatile(), 2);
- SDValue HighAddr = DAG.getNode(ISD::ADD, dl, EVT::i32, BasePtr,
- DAG.getConstant(2, EVT::i32));
+ SDValue HighAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, BasePtr,
+ DAG.getConstant(2, MVT::i32));
SDValue StoreHigh = DAG.getTruncStore(Chain, dl, High, HighAddr,
ST->getSrcValue(), SVOffset + 2,
- EVT::i16, ST->isVolatile(), 2);
- return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, StoreLow, StoreHigh);
+ MVT::i16, ST->isVolatile(), 2);
+ return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, StoreLow, StoreHigh);
}
// Lower to a call to __misaligned_store(BasePtr, Value).
SDValue XCoreTargetLowering::
ExpandADDSUB(SDNode *N, SelectionDAG &DAG)
{
- assert(N->getValueType(0) == EVT::i64 &&
+ assert(N->getValueType(0) == MVT::i64 &&
(N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) &&
"Unknown operand to lower!");
assert(!Subtarget.isXS1A() && "Cannot custom lower ADD/SUB on xs1a");
DebugLoc dl = N->getDebugLoc();
// Extract components
- SDValue LHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32,
- N->getOperand(0), DAG.getConstant(0, EVT::i32));
- SDValue LHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32,
- N->getOperand(0), DAG.getConstant(1, EVT::i32));
- SDValue RHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32,
- N->getOperand(1), DAG.getConstant(0, EVT::i32));
- SDValue RHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32,
- N->getOperand(1), DAG.getConstant(1, EVT::i32));
+ SDValue LHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
+ N->getOperand(0), DAG.getConstant(0, MVT::i32));
+ SDValue LHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
+ N->getOperand(0), DAG.getConstant(1, MVT::i32));
+ SDValue RHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
+ N->getOperand(1), DAG.getConstant(0, MVT::i32));
+ SDValue RHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
+ N->getOperand(1), DAG.getConstant(1, MVT::i32));
// Expand
unsigned Opcode = (N->getOpcode() == ISD::ADD) ? XCoreISD::LADD :
XCoreISD::LSUB;
- SDValue Zero = DAG.getConstant(0, EVT::i32);
- SDValue Carry = DAG.getNode(Opcode, dl, DAG.getVTList(EVT::i32, EVT::i32),
+ SDValue Zero = DAG.getConstant(0, MVT::i32);
+ SDValue Carry = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32),
LHSL, RHSL, Zero);
SDValue Lo(Carry.getNode(), 1);
- SDValue Ignored = DAG.getNode(Opcode, dl, DAG.getVTList(EVT::i32, EVT::i32),
+ SDValue Ignored = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32),
LHSH, RHSH, Carry);
SDValue Hi(Ignored.getNode(), 1);
// Merge the pieces
- return DAG.getNode(ISD::BUILD_PAIR, dl, EVT::i64, Lo, Hi);
+ return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
}
SDValue XCoreTargetLowering::
// memory location argument
MachineFunction &MF = DAG.getMachineFunction();
XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
- SDValue Addr = DAG.getFrameIndex(XFI->getVarArgsFrameIndex(), EVT::i32);
+ SDValue Addr = DAG.getFrameIndex(XFI->getVarArgsFrameIndex(), MVT::i32);
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
return DAG.getStore(Op.getOperand(0), dl, Addr, Op.getOperand(1), SV, 0);
}
MachineFunction &MF = DAG.getMachineFunction();
const TargetRegisterInfo *RegInfo = getTargetMachine().getRegisterInfo();
return DAG.getCopyFromReg(DAG.getEntryNode(), dl,
- RegInfo->getFrameRegister(MF), EVT::i32);
+ RegInfo->getFrameRegister(MF), MVT::i32);
}
//===----------------------------------------------------------------------===//
int Offset = VA.getLocMemOffset();
- MemOpChains.push_back(DAG.getNode(XCoreISD::STWSP, dl, EVT::Other,
+ MemOpChains.push_back(DAG.getNode(XCoreISD::STWSP, dl, MVT::Other,
Chain, Arg,
- DAG.getConstant(Offset/4, EVT::i32)));
+ DAG.getConstant(Offset/4, MVT::i32)));
}
}
// Transform all store nodes into one single node because
// all store nodes are independent of each other.
if (!MemOpChains.empty())
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&MemOpChains[0], MemOpChains.size());
// Build a sequence of copy-to-reg nodes chained together with token
// turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
// Likewise ExternalSymbol -> TargetExternalSymbol.
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
- Callee = DAG.getTargetGlobalAddress(G->getGlobal(), EVT::i32);
+ Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
- Callee = DAG.getTargetExternalSymbol(E->getSymbol(), EVT::i32);
+ Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
// XCoreBranchLink = #chain, #target_address, #opt_in_flags...
// = Chain, Callee, Reg#1, Reg#2, ...
//
// Returns a chain & a flag for retval copy to use.
- SDVTList NodeTys = DAG.getVTList(EVT::Other, EVT::Flag);
+ SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
SmallVector<SDValue, 8> Ops;
Ops.push_back(Chain);
Ops.push_back(Callee);
if (VA.isRegLoc()) {
// Arguments passed in registers
EVT RegVT = VA.getLocVT();
- switch (RegVT.getSimpleVT()) {
+ switch (RegVT.getSimpleVT().SimpleTy) {
default:
{
#ifndef NDEBUG
errs() << "LowerFormalArguments Unhandled argument type: "
- << RegVT.getSimpleVT() << "\n";
+ << RegVT.getSimpleVT().SimpleTy << "\n";
#endif
llvm_unreachable(0);
}
- case EVT::i32:
+ case MVT::i32:
unsigned VReg = RegInfo.createVirtualRegister(
XCore::GRRegsRegisterClass);
RegInfo.addLiveIn(VA.getLocReg(), VReg);
unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
if (ObjSize > StackSlotSize) {
errs() << "LowerFormalArguments Unhandled argument type: "
- << VA.getLocVT().getSimpleVT()
+ << (unsigned)VA.getLocVT().getSimpleVT().SimpleTy
<< "\n";
}
// Create the frame index object for this incoming parameter...
// Create the SelectionDAG nodes corresponding to a load
//from this parameter
- SDValue FIN = DAG.getFrameIndex(FI, EVT::i32);
+ SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN, NULL, 0));
}
}
XFI->setVarArgsFrameIndex(FI);
}
offset -= StackSlotSize;
- SDValue FIN = DAG.getFrameIndex(FI, EVT::i32);
+ SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
// Move argument from phys reg -> virt reg
unsigned VReg = RegInfo.createVirtualRegister(
XCore::GRRegsRegisterClass);
RegInfo.addLiveIn(ArgRegs[i], VReg);
- SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, EVT::i32);
+ SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
// Move argument from virt reg -> stack
SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
MemOps.push_back(Store);
}
if (!MemOps.empty())
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&MemOps[0], MemOps.size());
} else {
// This will point to the next argument passed via stack.
// Return on XCore is always a "retsp 0"
if (Flag.getNode())
- return DAG.getNode(XCoreISD::RETSP, dl, EVT::Other,
- Chain, DAG.getConstant(0, EVT::i32), Flag);
+ return DAG.getNode(XCoreISD::RETSP, dl, MVT::Other,
+ Chain, DAG.getConstant(0, MVT::i32), Flag);
else // Return Void
- return DAG.getNode(XCoreISD::RETSP, dl, EVT::Other,
- Chain, DAG.getConstant(0, EVT::i32));
+ return DAG.getNode(XCoreISD::RETSP, dl, MVT::Other,
+ Chain, DAG.getConstant(0, MVT::i32));
}
//===----------------------------------------------------------------------===//
Chain.reachesChainWithoutSideEffects(SDValue(LD, 1))) {
return DAG.getMemmove(Chain, dl, ST->getBasePtr(),
LD->getBasePtr(),
- DAG.getConstant(StoreBits/8, EVT::i32),
+ DAG.getConstant(StoreBits/8, MVT::i32),
Alignment, ST->getSrcValue(),
ST->getSrcValueOffset(), LD->getSrcValue(),
LD->getSrcValueOffset());
index de3b6400a790734b58894613eb5aa0d12db333e6..952d225b509e547a6c90789dcd7c9dca849dcc1e 100644 (file)
/// getEVTString - This function returns value type as a string, e.g. "i32".
std::string EVT::getEVTString() const {
- switch (V) {
+ switch (V.SimpleTy) {
default:
if (isVector())
return "v" + utostr(getVectorNumElements()) +
return "i" + utostr(getSizeInBits());
llvm_unreachable("Invalid EVT!");
return "?";
- case EVT::i1: return "i1";
- case EVT::i8: return "i8";
- case EVT::i16: return "i16";
- case EVT::i32: return "i32";
- case EVT::i64: return "i64";
- case EVT::i128: return "i128";
- case EVT::f32: return "f32";
- case EVT::f64: return "f64";
- case EVT::f80: return "f80";
- case EVT::f128: return "f128";
- case EVT::ppcf128: return "ppcf128";
- case EVT::isVoid: return "isVoid";
- case EVT::Other: return "ch";
- case EVT::Flag: return "flag";
- case EVT::v2i8: return "v2i8";
- case EVT::v4i8: return "v4i8";
- case EVT::v8i8: return "v8i8";
- case EVT::v16i8: return "v16i8";
- case EVT::v32i8: return "v32i8";
- case EVT::v2i16: return "v2i16";
- case EVT::v4i16: return "v4i16";
- case EVT::v8i16: return "v8i16";
- case EVT::v16i16: return "v16i16";
- case EVT::v2i32: return "v2i32";
- case EVT::v4i32: return "v4i32";
- case EVT::v8i32: return "v8i32";
- case EVT::v1i64: return "v1i64";
- case EVT::v2i64: return "v2i64";
- case EVT::v4i64: return "v4i64";
- case EVT::v2f32: return "v2f32";
- case EVT::v4f32: return "v4f32";
- case EVT::v8f32: return "v8f32";
- case EVT::v2f64: return "v2f64";
- case EVT::v4f64: return "v4f64";
+ case MVT::i1: return "i1";
+ case MVT::i8: return "i8";
+ case MVT::i16: return "i16";
+ case MVT::i32: return "i32";
+ case MVT::i64: return "i64";
+ case MVT::i128: return "i128";
+ case MVT::f32: return "f32";
+ case MVT::f64: return "f64";
+ case MVT::f80: return "f80";
+ case MVT::f128: return "f128";
+ case MVT::ppcf128: return "ppcf128";
+ case MVT::isVoid: return "isVoid";
+ case MVT::Other: return "ch";
+ case MVT::Flag: return "flag";
+ case MVT::v2i8: return "v2i8";
+ case MVT::v4i8: return "v4i8";
+ case MVT::v8i8: return "v8i8";
+ case MVT::v16i8: return "v16i8";
+ case MVT::v32i8: return "v32i8";
+ case MVT::v2i16: return "v2i16";
+ case MVT::v4i16: return "v4i16";
+ case MVT::v8i16: return "v8i16";
+ case MVT::v16i16: return "v16i16";
+ case MVT::v2i32: return "v2i32";
+ case MVT::v4i32: return "v4i32";
+ case MVT::v8i32: return "v8i32";
+ case MVT::v1i64: return "v1i64";
+ case MVT::v2i64: return "v2i64";
+ case MVT::v4i64: return "v4i64";
+ case MVT::v2f32: return "v2f32";
+ case MVT::v4f32: return "v4f32";
+ case MVT::v8f32: return "v8f32";
+ case MVT::v2f64: return "v2f64";
+ case MVT::v4f64: return "v4f64";
}
}
/// specified EVT. For integer types, this returns an unsigned type. Note
/// that this will abort for types that cannot be represented.
const Type *EVT::getTypeForEVT() const {
- switch (V) {
+ switch (V.SimpleTy) {
default:
assert(isExtended() && "Type is not extended!");
return LLVMTy;
- case EVT::isVoid: return Type::VoidTy;
- case EVT::i1: return Type::Int1Ty;
- case EVT::i8: return Type::Int8Ty;
- case EVT::i16: return Type::Int16Ty;
- case EVT::i32: return Type::Int32Ty;
- case EVT::i64: return Type::Int64Ty;
- case EVT::i128: return IntegerType::get(128);
- case EVT::f32: return Type::FloatTy;
- case EVT::f64: return Type::DoubleTy;
- case EVT::f80: return Type::X86_FP80Ty;
- case EVT::f128: return Type::FP128Ty;
- case EVT::ppcf128: return Type::PPC_FP128Ty;
- case EVT::v2i8: return VectorType::get(Type::Int8Ty, 2);
- case EVT::v4i8: return VectorType::get(Type::Int8Ty, 4);
- case EVT::v8i8: return VectorType::get(Type::Int8Ty, 8);
- case EVT::v16i8: return VectorType::get(Type::Int8Ty, 16);
- case EVT::v32i8: return VectorType::get(Type::Int8Ty, 32);
- case EVT::v2i16: return VectorType::get(Type::Int16Ty, 2);
- case EVT::v4i16: return VectorType::get(Type::Int16Ty, 4);
- case EVT::v8i16: return VectorType::get(Type::Int16Ty, 8);
- case EVT::v16i16: return VectorType::get(Type::Int16Ty, 16);
- case EVT::v2i32: return VectorType::get(Type::Int32Ty, 2);
- case EVT::v4i32: return VectorType::get(Type::Int32Ty, 4);
- case EVT::v8i32: return VectorType::get(Type::Int32Ty, 8);
- case EVT::v1i64: return VectorType::get(Type::Int64Ty, 1);
- case EVT::v2i64: return VectorType::get(Type::Int64Ty, 2);
- case EVT::v4i64: return VectorType::get(Type::Int64Ty, 4);
- case EVT::v2f32: return VectorType::get(Type::FloatTy, 2);
- case EVT::v4f32: return VectorType::get(Type::FloatTy, 4);
- case EVT::v8f32: return VectorType::get(Type::FloatTy, 8);
- case EVT::v2f64: return VectorType::get(Type::DoubleTy, 2);
- case EVT::v4f64: return VectorType::get(Type::DoubleTy, 4);
+ case MVT::isVoid: return Type::VoidTy;
+ case MVT::i1: return Type::Int1Ty;
+ case MVT::i8: return Type::Int8Ty;
+ case MVT::i16: return Type::Int16Ty;
+ case MVT::i32: return Type::Int32Ty;
+ case MVT::i64: return Type::Int64Ty;
+ case MVT::i128: return IntegerType::get(128);
+ case MVT::f32: return Type::FloatTy;
+ case MVT::f64: return Type::DoubleTy;
+ case MVT::f80: return Type::X86_FP80Ty;
+ case MVT::f128: return Type::FP128Ty;
+ case MVT::ppcf128: return Type::PPC_FP128Ty;
+ case MVT::v2i8: return VectorType::get(Type::Int8Ty, 2);
+ case MVT::v4i8: return VectorType::get(Type::Int8Ty, 4);
+ case MVT::v8i8: return VectorType::get(Type::Int8Ty, 8);
+ case MVT::v16i8: return VectorType::get(Type::Int8Ty, 16);
+ case MVT::v32i8: return VectorType::get(Type::Int8Ty, 32);
+ case MVT::v2i16: return VectorType::get(Type::Int16Ty, 2);
+ case MVT::v4i16: return VectorType::get(Type::Int16Ty, 4);
+ case MVT::v8i16: return VectorType::get(Type::Int16Ty, 8);
+ case MVT::v16i16: return VectorType::get(Type::Int16Ty, 16);
+ case MVT::v2i32: return VectorType::get(Type::Int32Ty, 2);
+ case MVT::v4i32: return VectorType::get(Type::Int32Ty, 4);
+ case MVT::v8i32: return VectorType::get(Type::Int32Ty, 8);
+ case MVT::v1i64: return VectorType::get(Type::Int64Ty, 1);
+ case MVT::v2i64: return VectorType::get(Type::Int64Ty, 2);
+ case MVT::v4i64: return VectorType::get(Type::Int64Ty, 4);
+ case MVT::v2f32: return VectorType::get(Type::FloatTy, 2);
+ case MVT::v4f32: return VectorType::get(Type::FloatTy, 4);
+ case MVT::v8f32: return VectorType::get(Type::FloatTy, 8);
+ case MVT::v2f64: return VectorType::get(Type::DoubleTy, 2);
+ case MVT::v4f64: return VectorType::get(Type::DoubleTy, 4);
}
}
/// getEVT - Return the value type corresponding to the specified type. This
-/// returns all pointers as EVT::iPTR. If HandleUnknown is true, unknown types
+/// returns all pointers as MVT::iPTR. If HandleUnknown is true, unknown types
/// are returned as Other, otherwise they are invalid.
EVT EVT::getEVT(const Type *Ty, bool HandleUnknown){
switch (Ty->getTypeID()) {
default:
- if (HandleUnknown) return EVT::Other;
+ if (HandleUnknown) return MVT(MVT::Other);
llvm_unreachable("Unknown type!");
- return EVT::isVoid;
+ return MVT(MVT::isVoid);
case Type::VoidTyID:
- return EVT::isVoid;
+ return MVT(MVT::isVoid);
case Type::IntegerTyID:
return getIntegerVT(cast<IntegerType>(Ty)->getBitWidth());
- case Type::FloatTyID: return EVT::f32;
- case Type::DoubleTyID: return EVT::f64;
- case Type::X86_FP80TyID: return EVT::f80;
- case Type::FP128TyID: return EVT::f128;
- case Type::PPC_FP128TyID: return EVT::ppcf128;
- case Type::PointerTyID: return EVT::iPTR;
+ case Type::FloatTyID: return MVT(MVT::f32);
+ case Type::DoubleTyID: return MVT(MVT::f64);
+ case Type::X86_FP80TyID: return MVT(MVT::f80);
+ case Type::FP128TyID: return MVT(MVT::f128);
+ case Type::PPC_FP128TyID: return MVT(MVT::ppcf128);
+ case Type::PointerTyID: return MVT(MVT::iPTR);
case Type::VectorTyID: {
const VectorType *VTy = cast<VectorType>(Ty);
return getVectorVT(getEVT(VTy->getElementType(), false),
index ca099525cd7456443dcc45066f00af2aec208da4..62a0a9fefa2147c894f0e5cc76f86b192671eb51 100644 (file)
--- a/lib/VMCore/Verifier.cpp
+++ b/lib/VMCore/Verifier.cpp
@@ -1559,7 +1559,7 @@ bool Verifier::PerformTypeCheck(Intrinsic::ID ID, Function *F, const Type *Ty,
return false;
}
}
- } else if (VT == EVT::iAny) {
+ } else if (VT == MVT::iAny) {
if (!EltTy->isInteger()) {
CheckFailed(IntrinsicParam(ArgNo, NumRets) + " is not "
"an integer type.", F);
@@ -1584,7 +1584,7 @@ bool Verifier::PerformTypeCheck(Intrinsic::ID ID, Function *F, const Type *Ty,
}
break;
}
- } else if (VT == EVT::fAny) {
+ } else if (VT == MVT::fAny) {
if (!EltTy->isFloatingPoint()) {
CheckFailed(IntrinsicParam(ArgNo, NumRets) + " is not "
"a floating-point type.", F);
@@ -1597,19 +1597,19 @@ bool Verifier::PerformTypeCheck(Intrinsic::ID ID, Function *F, const Type *Ty,
Suffix += "v" + utostr(NumElts);
Suffix += EVT::getEVT(EltTy).getEVTString();
- } else if (VT == EVT::vAny) {
+ } else if (VT == MVT::vAny) {
if (!VTy) {
CheckFailed(IntrinsicParam(ArgNo, NumRets) + " is not a vector type.", F);
return false;
}
Suffix += ".v" + utostr(NumElts) + EVT::getEVT(EltTy).getEVTString();
- } else if (VT == EVT::iPTR) {
+ } else if (VT == MVT::iPTR) {
if (!isa<PointerType>(Ty)) {
CheckFailed(IntrinsicParam(ArgNo, NumRets) + " is not a "
"pointer and a pointer is required.", F);
return false;
}
- } else if (VT == EVT::iPTRAny) {
+ } else if (VT == MVT::iPTRAny) {
// Outside of TableGen, we don't distinguish iPTRAny (to any address space)
// and iPTR. In the verifier, we can not distinguish which case we have so
// allow either case to be legal.
@@ -1621,8 +1621,8 @@ bool Verifier::PerformTypeCheck(Intrinsic::ID ID, Function *F, const Type *Ty,
"pointer and a pointer is required.", F);
return false;
}
- } else if (EVT((EVT::SimpleValueType)VT).isVector()) {
- EVT VVT = EVT((EVT::SimpleValueType)VT);
+ } else if (EVT((MVT::SimpleValueType)VT).isVector()) {
+ EVT VVT = EVT((MVT::SimpleValueType)VT);
// If this is a vector argument, verify the number and type of elements.
if (VVT.getVectorElementType() != EVT::getEVT(EltTy)) {
@@ -1635,7 +1635,7 @@ bool Verifier::PerformTypeCheck(Intrinsic::ID ID, Function *F, const Type *Ty,
"vector elements!", F);
return false;
}
- } else if (EVT((EVT::SimpleValueType)VT).getTypeForEVT() != EltTy) {
+ } else if (EVT((MVT::SimpleValueType)VT).getTypeForEVT() != EltTy) {
CheckFailed(IntrinsicParam(ArgNo, NumRets) + " is wrong!", F);
return false;
} else if (EltTy != Ty) {
}
for (unsigned ArgNo = 0; ArgNo < RetNum; ++ArgNo) {
- int VT = va_arg(VA, int); // An EVT::SimpleValueType when non-negative.
+ int VT = va_arg(VA, int); // An MVT::SimpleValueType when non-negative.
if (ST) Ty = ST->getElementType(ArgNo);
// Verify the parameter types.
for (unsigned ArgNo = 0; ArgNo < ParamNum; ++ArgNo) {
- int VT = va_arg(VA, int); // An EVT::SimpleValueType when non-negative.
+ int VT = va_arg(VA, int); // An MVT::SimpleValueType when non-negative.
- if (VT == EVT::isVoid && ArgNo > 0) {
+ if (VT == MVT::isVoid && ArgNo > 0) {
if (!FTy->isVarArg())
CheckFailed("Intrinsic prototype has no '...'!", F);
break;
index af72b93fd309ead009e06fa5fcf583dd85e1ce30..29b41a243bd0f4ecb0c0dd259f4d88abf299edcd 100644 (file)
/// FilterVTs - Filter a list of VT's according to a predicate.
///
template<typename T>
-static std::vector<EVT::SimpleValueType>
-FilterVTs(const std::vector<EVT::SimpleValueType> &InVTs, T Filter) {
- std::vector<EVT::SimpleValueType> Result;
+static std::vector<MVT::SimpleValueType>
+FilterVTs(const std::vector<MVT::SimpleValueType> &InVTs, T Filter) {
+ std::vector<MVT::SimpleValueType> Result;
for (unsigned i = 0, e = InVTs.size(); i != e; ++i)
if (Filter(InVTs[i]))
Result.push_back(InVTs[i]);
FilterEVTs(const std::vector<unsigned char> &InVTs, T Filter) {
std::vector<unsigned char> Result;
for (unsigned i = 0, e = InVTs.size(); i != e; ++i)
- if (Filter((EVT::SimpleValueType)InVTs[i]))
+ if (Filter((MVT::SimpleValueType)InVTs[i]))
Result.push_back(InVTs[i]);
return Result;
}
static std::vector<unsigned char>
-ConvertVTs(const std::vector<EVT::SimpleValueType> &InVTs) {
+ConvertVTs(const std::vector<MVT::SimpleValueType> &InVTs) {
std::vector<unsigned char> Result;
for (unsigned i = 0, e = InVTs.size(); i != e; ++i)
Result.push_back(InVTs[i]);
return Result;
}
-static inline bool isInteger(EVT::SimpleValueType VT) {
+static inline bool isInteger(MVT::SimpleValueType VT) {
return EVT(VT).isInteger();
}
-static inline bool isFloatingPoint(EVT::SimpleValueType VT) {
+static inline bool isFloatingPoint(MVT::SimpleValueType VT) {
return EVT(VT).isFloatingPoint();
}
-static inline bool isVector(EVT::SimpleValueType VT) {
+static inline bool isVector(MVT::SimpleValueType VT) {
return EVT(VT).isVector();
}
return NodeToApply->UpdateNodeType(x.SDTCisVT_Info.VT, TP);
case SDTCisPtrTy: {
// Operand must be same as target pointer type.
- return NodeToApply->UpdateNodeType(EVT::iPTR, TP);
+ return NodeToApply->UpdateNodeType(MVT::iPTR, TP);
}
case SDTCisInt: {
// If there is only one integer type supported, this must be it.
- std::vector<EVT::SimpleValueType> IntVTs =
+ std::vector<MVT::SimpleValueType> IntVTs =
FilterVTs(CGT.getLegalValueTypes(), isInteger);
// If we found exactly one supported integer type, apply it.
}
case SDTCisFP: {
// If there is only one FP type supported, this must be it.
- std::vector<EVT::SimpleValueType> FPVTs =
+ std::vector<MVT::SimpleValueType> FPVTs =
FilterVTs(CGT.getLegalValueTypes(), isFloatingPoint);
// If we found exactly one supported FP type, apply it.
!static_cast<DefInit*>(NodeToApply->getLeafValue())->getDef()
->isSubClassOf("ValueType"))
TP.error(N->getOperator()->getName() + " expects a VT operand!");
- EVT::SimpleValueType VT =
+ MVT::SimpleValueType VT =
getValueType(static_cast<DefInit*>(NodeToApply->getLeafValue())->getDef());
if (!isInteger(VT))
TP.error(N->getOperator()->getName() + " VT operand must be integer!");
// types at this point.
assert(OtherNode->getExtTypes().size() == 1 && "Node has too many types!");
if (OtherNode->hasTypeSet() && OtherNode->getTypeNum(0) <= VT)
- OtherNode->UpdateNodeType(EVT::Other, TP); // Throw an error.
+ OtherNode->UpdateNodeType(MVT::Other, TP); // Throw an error.
return false;
}
case SDTCisOpSmallerThanOp: {
else if (EEVT::isExtFloatingPointInVTs(BigOperand->getExtTypes()))
MadeChange |= NodeToApply->UpdateNodeType(EEVT::isFP, TP);
- std::vector<EVT::SimpleValueType> VTs = CGT.getLegalValueTypes();
+ std::vector<MVT::SimpleValueType> VTs = CGT.getLegalValueTypes();
if (EEVT::isExtIntegerInVTs(NodeToApply->getExtTypes())) {
VTs = FilterVTs(VTs, isInteger);
case 0: break; // No info yet.
case 1:
// Only one VT of this flavor. Cannot ever satisfy the constraints.
- return NodeToApply->UpdateNodeType(EVT::Other, TP); // throw
+ return NodeToApply->UpdateNodeType(MVT::Other, TP); // throw
case 2:
// If we have exactly two possible types, the little operand must be the
// small one, the big operand should be the big one. Common with
TP.error(N->getOperator()->getName() + " VT operand must be a vector!");
EVT IVT = OtherOperand->getTypeNum(0);
IVT = IVT.getVectorElementType();
- return NodeToApply->UpdateNodeType(IVT.getSimpleVT(), TP);
+ return NodeToApply->UpdateNodeType(IVT.getSimpleVT().SimpleTy, TP);
}
return false;
}
return true;
}
- if (getExtTypeNum(0) == EVT::iPTR || getExtTypeNum(0) == EVT::iPTRAny) {
- if (ExtVTs[0] == EVT::iPTR || ExtVTs[0] == EVT::iPTRAny ||
+ if (getExtTypeNum(0) == MVT::iPTR || getExtTypeNum(0) == MVT::iPTRAny) {
+ if (ExtVTs[0] == MVT::iPTR || ExtVTs[0] == MVT::iPTRAny ||
ExtVTs[0] == EEVT::isInt)
return false;
if (EEVT::isExtIntegerInVTs(ExtVTs)) {
}
}
- if ((ExtVTs[0] == EEVT::isInt || ExtVTs[0] == EVT::iAny) &&
+ if ((ExtVTs[0] == EEVT::isInt || ExtVTs[0] == MVT::iAny) &&
EEVT::isExtIntegerInVTs(getExtTypes())) {
assert(hasTypeSet() && "should be handled above!");
std::vector<unsigned char> FVTs = FilterEVTs(getExtTypes(), isInteger);
setTypes(FVTs);
return true;
}
- if ((ExtVTs[0] == EVT::iPTR || ExtVTs[0] == EVT::iPTRAny) &&
+ if ((ExtVTs[0] == MVT::iPTR || ExtVTs[0] == MVT::iPTRAny) &&
EEVT::isExtIntegerInVTs(getExtTypes())) {
//assert(hasTypeSet() && "should be handled above!");
std::vector<unsigned char> FVTs = FilterEVTs(getExtTypes(), isInteger);
return true;
}
}
- if ((ExtVTs[0] == EEVT::isFP || ExtVTs[0] == EVT::fAny) &&
+ if ((ExtVTs[0] == EEVT::isFP || ExtVTs[0] == MVT::fAny) &&
EEVT::isExtFloatingPointInVTs(getExtTypes())) {
assert(hasTypeSet() && "should be handled above!");
std::vector<unsigned char> FVTs =
setTypes(FVTs);
return true;
}
- if (ExtVTs[0] == EVT::vAny && EEVT::isExtVectorInVTs(getExtTypes())) {
+ if (ExtVTs[0] == MVT::vAny && EEVT::isExtVectorInVTs(getExtTypes())) {
assert(hasTypeSet() && "should be handled above!");
std::vector<unsigned char> FVTs = FilterEVTs(getExtTypes(), isVector);
if (getExtTypes() == FVTs)
@@ -516,17 +516,17 @@ bool TreePatternNode::UpdateNodeType(const std::vector<unsigned char> &ExtVTs,
//
// Similarly, we should probably set the type here to the intersection of
// {isInt|isFP} and ExtVTs
- if (((getExtTypeNum(0) == EEVT::isInt || getExtTypeNum(0) == EVT::iAny) &&
+ if (((getExtTypeNum(0) == EEVT::isInt || getExtTypeNum(0) == MVT::iAny) &&
EEVT::isExtIntegerInVTs(ExtVTs)) ||
- ((getExtTypeNum(0) == EEVT::isFP || getExtTypeNum(0) == EVT::fAny) &&
+ ((getExtTypeNum(0) == EEVT::isFP || getExtTypeNum(0) == MVT::fAny) &&
EEVT::isExtFloatingPointInVTs(ExtVTs)) ||
- (getExtTypeNum(0) == EVT::vAny &&
+ (getExtTypeNum(0) == MVT::vAny &&
EEVT::isExtVectorInVTs(ExtVTs))) {
setTypes(ExtVTs);
return true;
}
if (getExtTypeNum(0) == EEVT::isInt &&
- (ExtVTs[0] == EVT::iPTR || ExtVTs[0] == EVT::iPTRAny)) {
+ (ExtVTs[0] == MVT::iPTR || ExtVTs[0] == MVT::iPTRAny)) {
setTypes(ExtVTs);
return true;
}
// FIXME: At some point we should handle printing all the value types for
// nodes that are multiply typed.
switch (getExtTypeNum(0)) {
- case EVT::Other: OS << ":Other"; break;
+ case MVT::Other: OS << ":Other"; break;
case EEVT::isInt: OS << ":isInt"; break;
case EEVT::isFP : OS << ":isFP"; break;
case EEVT::isUnknown: ; /*OS << ":?";*/ break;
- case EVT::iPTR: OS << ":iPTR"; break;
- case EVT::iPTRAny: OS << ":iPTRAny"; break;
+ case MVT::iPTR: OS << ":iPTR"; break;
+ case MVT::iPTRAny: OS << ":iPTRAny"; break;
default: {
std::string VTName = llvm::getName(getTypeNum(0));
// Strip off EVT:: prefix if present.
- if (VTName.substr(0,5) == "EVT::")
+ if (VTName.substr(0,5) == "MVT::")
VTName = VTName.substr(5);
OS << ":" << VTName;
break;
TreePattern &TP) {
// Some common return values
std::vector<unsigned char> Unknown(1, EEVT::isUnknown);
- std::vector<unsigned char> Other(1, EVT::Other);
+ std::vector<unsigned char> Other(1, MVT::Other);
// Check to see if this is a register or a register class...
if (R->isSubClassOf("RegisterClass")) {
ComplexPat(1, TP.getDAGPatterns().getComplexPattern(R).getValueType());
return ComplexPat;
} else if (R->isSubClassOf("PointerLikeRegClass")) {
- Other[0] = EVT::iPTR;
+ Other[0] = MVT::iPTR;
return Other;
} else if (R->getName() == "node" || R->getName() == "srcvalue" ||
R->getName() == "zero_reg") {
@@ -827,12 +827,12 @@ bool TreePatternNode::ApplyTypeConstraints(TreePattern &TP, bool NotRegisters) {
// multiple types. Assert here that it does not, so we revisit this
// code when appropriate.
assert(getExtTypes().size() >= 1 && "TreePattern doesn't have a type!");
- EVT::SimpleValueType VT = getTypeNum(0);
+ MVT::SimpleValueType VT = getTypeNum(0);
for (unsigned i = 1, e = getExtTypes().size(); i != e; ++i)
assert(getTypeNum(i) == VT && "TreePattern has too many types!");
VT = getTypeNum(0);
- if (VT != EVT::iPTR && VT != EVT::iPTRAny) {
+ if (VT != MVT::iPTR && VT != MVT::iPTRAny) {
unsigned Size = EVT(VT).getSizeInBits();
// Make sure that the value is representable for this type.
if (Size < 32) {
@@ -873,7 +873,7 @@ bool TreePatternNode::ApplyTypeConstraints(TreePattern &TP, bool NotRegisters) {
TP);
MadeChange |= getChild(NC-1)->UpdateNodeType(getChild(i)->getExtTypes(),
TP);
- MadeChange |= UpdateNodeType(EVT::isVoid, TP);
+ MadeChange |= UpdateNodeType(MVT::isVoid, TP);
}
return MadeChange;
} else if (getOperator()->getName() == "implicit" ||
@@ -881,7 +881,7 @@ bool TreePatternNode::ApplyTypeConstraints(TreePattern &TP, bool NotRegisters) {
bool MadeChange = false;
for (unsigned i = 0; i < getNumChildren(); ++i)
MadeChange = getChild(i)->ApplyTypeConstraints(TP, NotRegisters);
- MadeChange |= UpdateNodeType(EVT::isVoid, TP);
+ MadeChange |= UpdateNodeType(MVT::isVoid, TP);
return MadeChange;
} else if (getOperator()->getName() == "COPY_TO_REGCLASS") {
bool MadeChange = false;
@@ -905,10 +905,10 @@ bool TreePatternNode::ApplyTypeConstraints(TreePattern &TP, bool NotRegisters) {
utostr(getNumChildren() - 1) + " operands!");
// Apply type info to the intrinsic ID.
- MadeChange |= getChild(0)->UpdateNodeType(EVT::iPTR, TP);
+ MadeChange |= getChild(0)->UpdateNodeType(MVT::iPTR, TP);
for (unsigned i = NumRetVTs, e = getNumChildren(); i != e; ++i) {
- EVT::SimpleValueType OpVT = Int->IS.ParamVTs[i - NumRetVTs];
+ MVT::SimpleValueType OpVT = Int->IS.ParamVTs[i - NumRetVTs];
MadeChange |= getChild(i)->UpdateNodeType(OpVT, TP);
MadeChange |= getChild(i)->ApplyTypeConstraints(TP, NotRegisters);
}
@@ -922,7 +922,7 @@ bool TreePatternNode::ApplyTypeConstraints(TreePattern &TP, bool NotRegisters) {
// Branch, etc. do not produce results and top-level forms in instr pattern
// must have void types.
if (NI.getNumResults() == 0)
- MadeChange |= UpdateNodeType(EVT::isVoid, TP);
+ MadeChange |= UpdateNodeType(MVT::isVoid, TP);
return MadeChange;
} else if (getOperator()->isSubClassOf("Instruction")) {
@@ -937,13 +937,13 @@ bool TreePatternNode::ApplyTypeConstraints(TreePattern &TP, bool NotRegisters) {
CDP.getTargetInfo().getInstruction(getOperator()->getName());
// Apply the result type to the node
if (NumResults == 0 || InstInfo.NumDefs == 0) {
- MadeChange = UpdateNodeType(EVT::isVoid, TP);
+ MadeChange = UpdateNodeType(MVT::isVoid, TP);
} else {
Record *ResultNode = Inst.getResult(0);
if (ResultNode->isSubClassOf("PointerLikeRegClass")) {
std::vector<unsigned char> VT;
- VT.push_back(EVT::iPTR);
+ VT.push_back(MVT::iPTR);
MadeChange = UpdateNodeType(VT, TP);
} else if (ResultNode->getName() == "unknown") {
std::vector<unsigned char> VT;
@@ -976,7 +976,7 @@ bool TreePatternNode::ApplyTypeConstraints(TreePattern &TP, bool NotRegisters) {
TP.error("Instruction '" + getOperator()->getName() +
"' expects more operands than were provided.");
- EVT::SimpleValueType VT;
+ MVT::SimpleValueType VT;
TreePatternNode *Child = getChild(ChildNo++);
if (OperandNode->isSubClassOf("RegisterClass")) {
const CodeGenRegisterClass &RC =
@@ -986,7 +986,7 @@ bool TreePatternNode::ApplyTypeConstraints(TreePattern &TP, bool NotRegisters) {
VT = getValueType(OperandNode->getValueAsDef("Type"));
MadeChange |= Child->UpdateNodeType(VT, TP);
} else if (OperandNode->isSubClassOf("PointerLikeRegClass")) {
- MadeChange |= Child->UpdateNodeType(EVT::iPTR, TP);
+ MadeChange |= Child->UpdateNodeType(MVT::iPTR, TP);
} else if (OperandNode->getName() == "unknown") {
MadeChange |= Child->UpdateNodeType(EEVT::isUnknown, TP);
} else {
// If this intrinsic returns void, it must have side-effects and thus a
// chain.
- if (Int.IS.RetVTs[0] == EVT::isVoid) {
+ if (Int.IS.RetVTs[0] == MVT::isVoid) {
Operator = getDAGPatterns().get_intrinsic_void_sdnode();
} else if (Int.ModRef != CodeGenIntrinsic::NoMem) {
// Has side-effects, requires chain.
// If this is not a set, verify that the children nodes are not void typed,
// and recurse.
for (unsigned i = 0, e = Pat->getNumChildren(); i != e; ++i) {
- if (Pat->getChild(i)->getExtTypeNum(0) == EVT::isVoid)
+ if (Pat->getChild(i)->getExtTypeNum(0) == MVT::isVoid)
I->error("Cannot have void nodes inside of patterns!");
FindPatternInputsAndOutputs(I, Pat->getChild(i), InstInputs, InstResults,
InstImpInputs, InstImpResults);
// fill in the InstResults map.
for (unsigned j = 0, e = I->getNumTrees(); j != e; ++j) {
TreePatternNode *Pat = I->getTree(j);
- if (Pat->getExtTypeNum(0) != EVT::isVoid)
+ if (Pat->getExtTypeNum(0) != MVT::isVoid)
I->error("Top-level forms in instruction pattern should have"
" void types");
index 6dbc7596c631d7af88843f4c310aeb3577a8e849..7c2791d4406e8b8d040f307d64c022e9b6ab70fd 100644 (file)
class ComplexPattern;
/// EEVT::DAGISelGenValueType - These are some extended forms of
-/// EVT::SimpleValueType that we use as lattice values during type inference.
+/// MVT::SimpleValueType that we use as lattice values during type inference.
namespace EEVT {
enum DAGISelGenValueType {
- isFP = EVT::LAST_VALUETYPE,
+ isFP = MVT::LAST_VALUETYPE,
isInt,
isUnknown
};
bool isLeaf() const { return Val != 0; }
bool hasTypeSet() const {
- return (Types[0] < EVT::LAST_VALUETYPE) || (Types[0] == EVT::iPTR) ||
- (Types[0] == EVT::iPTRAny);
+ return (Types[0] < MVT::LAST_VALUETYPE) || (Types[0] == MVT::iPTR) ||
+ (Types[0] == MVT::iPTRAny);
}
bool isTypeCompletelyUnknown() const {
return Types[0] == EEVT::isUnknown;
}
bool isTypeDynamicallyResolved() const {
- return (Types[0] == EVT::iPTR) || (Types[0] == EVT::iPTRAny);
+ return (Types[0] == MVT::iPTR) || (Types[0] == MVT::iPTRAny);
}
- EVT::SimpleValueType getTypeNum(unsigned Num) const {
+ MVT::SimpleValueType getTypeNum(unsigned Num) const {
assert(hasTypeSet() && "Doesn't have a type yet!");
assert(Types.size() > Num && "Type num out of range!");
- return (EVT::SimpleValueType)Types[Num];
+ return (MVT::SimpleValueType)Types[Num];
}
unsigned char getExtTypeNum(unsigned Num) const {
assert(Types.size() > Num && "Extended type num out of range!");
index 685e141f99bfdec805c9063c2b7d6160a1671c69..7e7bdf989acf8c17f35cb92300c9a5fde9642341 100644 (file)
/// continues from there through the parameter list. This is useful for
/// "matching" types.
struct IntrinsicSignature {
- /// RetVTs - The EVT::SimpleValueType for each return type. Note that this
+ /// RetVTs - The MVT::SimpleValueType for each return type. Note that this
/// list is only populated when in the context of a target .td file. When
/// building Intrinsics.td, this isn't available, because we don't know
/// the target pointer size.
- std::vector<EVT::SimpleValueType> RetVTs;
+ std::vector<MVT::SimpleValueType> RetVTs;
/// RetTypeDefs - The records for each return type.
std::vector<Record*> RetTypeDefs;
- /// ParamVTs - The EVT::SimpleValueType for each parameter type. Note that
+ /// ParamVTs - The MVT::SimpleValueType for each parameter type. Note that
/// this list is only populated when in the context of a target .td file.
/// When building Intrinsics.td, this isn't available, because we don't
/// know the target pointer size.
- std::vector<EVT::SimpleValueType> ParamVTs;
+ std::vector<MVT::SimpleValueType> ParamVTs;
/// ParamTypeDefs - The records for each parameter type.
std::vector<Record*> ParamTypeDefs;
index a52da6e50b753a2ab4dae142ec6318a629c3db2e..6f8682be59d3d42fa9b423a30441ea778ef7d3ae 100644 (file)
Record *TheDef;
std::string Namespace;
std::vector<Record*> Elements;
- std::vector<EVT::SimpleValueType> VTs;
+ std::vector<MVT::SimpleValueType> VTs;
unsigned SpillSize;
unsigned SpillAlignment;
int CopyCost;
std::string MethodProtos, MethodBodies;
const std::string &getName() const;
- const std::vector<EVT::SimpleValueType> &getValueTypes() const {return VTs;}
+ const std::vector<MVT::SimpleValueType> &getValueTypes() const {return VTs;}
unsigned getNumValueTypes() const { return VTs.size(); }
- EVT::SimpleValueType getValueTypeNum(unsigned VTNum) const {
+ MVT::SimpleValueType getValueTypeNum(unsigned VTNum) const {
if (VTNum < VTs.size())
return VTs[VTNum];
assert(0 && "VTNum greater than number of ValueTypes in RegClass!");
index 9b639ecd8d7739cef0ae42701d94de8cc507da88..a3ec8dc41d0e5dfcaf55f1f98e535b464721fbc3 100644 (file)
AsmWriterNum("asmwriternum", cl::init(0),
cl::desc("Make -gen-asm-writer emit assembly writer #N"));
-/// getValueType - Return the EVT::SimpleValueType that the specified TableGen
+/// getValueType - Return the MVT::SimpleValueType that the specified TableGen
/// record corresponds to.
-EVT::SimpleValueType llvm::getValueType(Record *Rec) {
- return (EVT::SimpleValueType)Rec->getValueAsInt("Value");
+MVT::SimpleValueType llvm::getValueType(Record *Rec) {
+ return (MVT::SimpleValueType)Rec->getValueAsInt("Value");
}
-std::string llvm::getName(EVT::SimpleValueType T) {
+std::string llvm::getName(MVT::SimpleValueType T) {
switch (T) {
- case EVT::Other: return "UNKNOWN";
- case EVT::iPTR: return "TLI.getPointerTy()";
- case EVT::iPTRAny: return "TLI.getPointerTy()";
+ case MVT::Other: return "UNKNOWN";
+ case MVT::iPTR: return "TLI.getPointerTy()";
+ case MVT::iPTRAny: return "TLI.getPointerTy()";
default: return getEnumName(T);
}
}
-std::string llvm::getEnumName(EVT::SimpleValueType T) {
+std::string llvm::getEnumName(MVT::SimpleValueType T) {
switch (T) {
- case EVT::Other: return "EVT::Other";
- case EVT::i1: return "EVT::i1";
- case EVT::i8: return "EVT::i8";
- case EVT::i16: return "EVT::i16";
- case EVT::i32: return "EVT::i32";
- case EVT::i64: return "EVT::i64";
- case EVT::i128: return "EVT::i128";
- case EVT::iAny: return "EVT::iAny";
- case EVT::fAny: return "EVT::fAny";
- case EVT::vAny: return "EVT::vAny";
- case EVT::f32: return "EVT::f32";
- case EVT::f64: return "EVT::f64";
- case EVT::f80: return "EVT::f80";
- case EVT::f128: return "EVT::f128";
- case EVT::ppcf128: return "EVT::ppcf128";
- case EVT::Flag: return "EVT::Flag";
- case EVT::isVoid:return "EVT::isVoid";
- case EVT::v2i8: return "EVT::v2i8";
- case EVT::v4i8: return "EVT::v4i8";
- case EVT::v8i8: return "EVT::v8i8";
- case EVT::v16i8: return "EVT::v16i8";
- case EVT::v32i8: return "EVT::v32i8";
- case EVT::v2i16: return "EVT::v2i16";
- case EVT::v4i16: return "EVT::v4i16";
- case EVT::v8i16: return "EVT::v8i16";
- case EVT::v16i16: return "EVT::v16i16";
- case EVT::v2i32: return "EVT::v2i32";
- case EVT::v4i32: return "EVT::v4i32";
- case EVT::v8i32: return "EVT::v8i32";
- case EVT::v1i64: return "EVT::v1i64";
- case EVT::v2i64: return "EVT::v2i64";
- case EVT::v4i64: return "EVT::v4i64";
- case EVT::v2f32: return "EVT::v2f32";
- case EVT::v4f32: return "EVT::v4f32";
- case EVT::v8f32: return "EVT::v8f32";
- case EVT::v2f64: return "EVT::v2f64";
- case EVT::v4f64: return "EVT::v4f64";
- case EVT::Metadata: return "EVT::Metadata";
- case EVT::iPTR: return "EVT::iPTR";
- case EVT::iPTRAny: return "EVT::iPTRAny";
+ case MVT::Other: return "MVT::Other";
+ case MVT::i1: return "MVT::i1";
+ case MVT::i8: return "MVT::i8";
+ case MVT::i16: return "MVT::i16";
+ case MVT::i32: return "MVT::i32";
+ case MVT::i64: return "MVT::i64";
+ case MVT::i128: return "MVT::i128";
+ case MVT::iAny: return "MVT::iAny";
+ case MVT::fAny: return "MVT::fAny";
+ case MVT::vAny: return "MVT::vAny";
+ case MVT::f32: return "MVT::f32";
+ case MVT::f64: return "MVT::f64";
+ case MVT::f80: return "MVT::f80";
+ case MVT::f128: return "MVT::f128";
+ case MVT::ppcf128: return "MVT::ppcf128";
+ case MVT::Flag: return "MVT::Flag";
+ case MVT::isVoid:return "MVT::isVoid";
+ case MVT::v2i8: return "MVT::v2i8";
+ case MVT::v4i8: return "MVT::v4i8";
+ case MVT::v8i8: return "MVT::v8i8";
+ case MVT::v16i8: return "MVT::v16i8";
+ case MVT::v32i8: return "MVT::v32i8";
+ case MVT::v2i16: return "MVT::v2i16";
+ case MVT::v4i16: return "MVT::v4i16";
+ case MVT::v8i16: return "MVT::v8i16";
+ case MVT::v16i16: return "MVT::v16i16";
+ case MVT::v2i32: return "MVT::v2i32";
+ case MVT::v4i32: return "MVT::v4i32";
+ case MVT::v8i32: return "MVT::v8i32";
+ case MVT::v1i64: return "MVT::v1i64";
+ case MVT::v2i64: return "MVT::v2i64";
+ case MVT::v4i64: return "MVT::v4i64";
+ case MVT::v2f32: return "MVT::v2f32";
+ case MVT::v4f32: return "MVT::v4f32";
+ case MVT::v8f32: return "MVT::v8f32";
+ case MVT::v2f64: return "MVT::v2f64";
+ case MVT::v4f64: return "MVT::v4f64";
+ case MVT::Metadata: return "MVT::Metadata";
+ case MVT::iPTR: return "MVT::iPTR";
+ case MVT::iPTRAny: return "MVT::iPTRAny";
default: assert(0 && "ILLEGAL VALUE TYPE!"); return "";
}
}
const CodeGenRegisterClass &RC = RegisterClasses[i];
for (unsigned ei = 0, ee = RC.Elements.size(); ei != ee; ++ei) {
if (R == RC.Elements[ei]) {
- const std::vector<EVT::SimpleValueType> &InVTs = RC.getValueTypes();
+ const std::vector<MVT::SimpleValueType> &InVTs = RC.getValueTypes();
for (unsigned i = 0, e = InVTs.size(); i != e; ++i)
Result.push_back(InVTs[i]);
}
}
// Parse the list of return types.
- std::vector<EVT::SimpleValueType> OverloadedVTs;
+ std::vector<MVT::SimpleValueType> OverloadedVTs;
ListInit *TypeList = R->getValueAsListInit("RetTypes");
for (unsigned i = 0, e = TypeList->getSize(); i != e; ++i) {
Record *TyEl = TypeList->getElementAsRecord(i);
assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!");
- EVT::SimpleValueType VT;
+ MVT::SimpleValueType VT;
if (TyEl->isSubClassOf("LLVMMatchType")) {
unsigned MatchTy = TyEl->getValueAsInt("Number");
assert(MatchTy < OverloadedVTs.size() &&
// overloaded, all the types can be specified directly.
assert(((!TyEl->isSubClassOf("LLVMExtendedElementVectorType") &&
!TyEl->isSubClassOf("LLVMTruncatedElementVectorType")) ||
- VT == EVT::iAny || VT == EVT::vAny) &&
+ VT == MVT::iAny || VT == MVT::vAny) &&
"Expected iAny or vAny type");
} else {
VT = getValueType(TyEl->getValueAsDef("VT"));
for (unsigned i = 0, e = TypeList->getSize(); i != e; ++i) {
Record *TyEl = TypeList->getElementAsRecord(i);
assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!");
- EVT::SimpleValueType VT;
+ MVT::SimpleValueType VT;
if (TyEl->isSubClassOf("LLVMMatchType")) {
unsigned MatchTy = TyEl->getValueAsInt("Number");
assert(MatchTy < OverloadedVTs.size() &&
// overloaded, all the types can be specified directly.
assert(((!TyEl->isSubClassOf("LLVMExtendedElementVectorType") &&
!TyEl->isSubClassOf("LLVMTruncatedElementVectorType")) ||
- VT == EVT::iAny || VT == EVT::vAny) &&
+ VT == MVT::iAny || VT == MVT::vAny) &&
"Expected iAny or vAny type");
} else
VT = getValueType(TyEl->getValueAsDef("VT"));
index d18df4f9c502dc21537fb5b2619f35c7c7da0a74..e763795ce0be92d4d45ad84e2ec58e8dc233ca22 100644 (file)
// ComplexPattern attributes.
enum CPAttr { CPAttrParentAsRoot };
-/// getValueType - Return the EVT::SimpleValueType that the specified TableGen
+/// getValueType - Return the MVT::SimpleValueType that the specified TableGen
/// record corresponds to.
-EVT::SimpleValueType getValueType(Record *Rec);
+MVT::SimpleValueType getValueType(Record *Rec);
-std::string getName(EVT::SimpleValueType T);
-std::string getEnumName(EVT::SimpleValueType T);
+std::string getName(MVT::SimpleValueType T);
+std::string getEnumName(MVT::SimpleValueType T);
/// getQualifiedName - Return the name of the specified record, with a
/// namespace qualifier if the record contains one.
mutable std::map<std::string, CodeGenInstruction> Instructions;
mutable std::vector<CodeGenRegister> Registers;
mutable std::vector<CodeGenRegisterClass> RegisterClasses;
- mutable std::vector<EVT::SimpleValueType> LegalValueTypes;
+ mutable std::vector<MVT::SimpleValueType> LegalValueTypes;
void ReadRegisters() const;
void ReadRegisterClasses() const;
void ReadInstructions() const;
/// specified physical register.
std::vector<unsigned char> getRegisterVTs(Record *R) const;
- const std::vector<EVT::SimpleValueType> &getLegalValueTypes() const {
+ const std::vector<MVT::SimpleValueType> &getLegalValueTypes() const {
if (LegalValueTypes.empty()) ReadLegalValueTypes();
return LegalValueTypes;
}
/// isLegalValueType - Return true if the specified value type is natively
/// supported by the target (i.e. there are registers that directly hold it).
- bool isLegalValueType(EVT::SimpleValueType VT) const {
- const std::vector<EVT::SimpleValueType> &LegalVTs = getLegalValueTypes();
+ bool isLegalValueType(MVT::SimpleValueType VT) const {
+ const std::vector<MVT::SimpleValueType> &LegalVTs = getLegalValueTypes();
for (unsigned i = 0, e = LegalVTs.size(); i != e; ++i)
if (LegalVTs[i] == VT) return true;
return false;
/// ComplexPattern - ComplexPattern info, corresponding to the ComplexPattern
/// tablegen class in TargetSelectionDAG.td
class ComplexPattern {
- EVT::SimpleValueType Ty;
+ MVT::SimpleValueType Ty;
unsigned NumOperands;
std::string SelectFunc;
std::vector<Record*> RootNodes;
ComplexPattern() : NumOperands(0) {};
ComplexPattern(Record *R);
- EVT::SimpleValueType getValueType() const { return Ty; }
+ MVT::SimpleValueType getValueType() const { return Ty; }
unsigned getNumOperands() const { return NumOperands; }
const std::string &getSelectFunc() const { return SelectFunc; }
const std::vector<Record*> &getRootNodes() const {
index 4bdb4d953e2f36387eb53787758f2430339a1568..b116aa20c3b645329c47d0e82c1c09a40392dc63 100644 (file)
static unsigned getPatternSize(TreePatternNode *P, CodeGenDAGPatterns &CGP) {
assert((EEVT::isExtIntegerInVTs(P->getExtTypes()) ||
EEVT::isExtFloatingPointInVTs(P->getExtTypes()) ||
- P->getExtTypeNum(0) == EVT::isVoid ||
- P->getExtTypeNum(0) == EVT::Flag ||
- P->getExtTypeNum(0) == EVT::iPTR ||
- P->getExtTypeNum(0) == EVT::iPTRAny) &&
+ P->getExtTypeNum(0) == MVT::isVoid ||
+ P->getExtTypeNum(0) == MVT::Flag ||
+ P->getExtTypeNum(0) == MVT::iPTR ||
+ P->getExtTypeNum(0) == MVT::iPTRAny) &&
"Not a valid pattern node to size!");
unsigned Size = 3; // The node itself.
// If the root node is a ConstantSDNode, increases its size.
// Count children in the count if they are also nodes.
for (unsigned i = 0, e = P->getNumChildren(); i != e; ++i) {
TreePatternNode *Child = P->getChild(i);
- if (!Child->isLeaf() && Child->getExtTypeNum(0) != EVT::Other)
+ if (!Child->isLeaf() && Child->getExtTypeNum(0) != MVT::Other)
Size += getPatternSize(Child, CGP);
else if (Child->isLeaf()) {
if (dynamic_cast<IntInit*>(Child->getLeafValue()))
/// getRegisterValueType - Look up and return the ValueType of the specified
/// register. If the register is a member of multiple register classes which
-/// have different associated types, return EVT::Other.
-static EVT::SimpleValueType getRegisterValueType(Record *R, const CodeGenTarget &T) {
+/// have different associated types, return MVT::Other.
+static MVT::SimpleValueType getRegisterValueType(Record *R, const CodeGenTarget &T) {
bool FoundRC = false;
- EVT::SimpleValueType VT = EVT::Other;
+ MVT::SimpleValueType VT = MVT::Other;
const std::vector<CodeGenRegisterClass> &RCs = T.getRegisterClasses();
std::vector<CodeGenRegisterClass>::const_iterator RC;
std::vector<Record*>::const_iterator Element;
} else {
// In multiple RC's
if (VT != (*RC).getValueTypeNum(0)) {
- // Types of the RC's do not agree. Return EVT::Other. The
+ // Types of the RC's do not agree. Return MVT::Other. The
// target is responsible for handling this.
- return EVT::Other;
+ return MVT::Other;
}
}
}
} else if (LeafRec->isSubClassOf("ValueType")) {
// Make sure this is the specified value type.
emitCheck("cast<VTSDNode>(" + RootName +
- ")->getVT() == EVT::" + LeafRec->getName());
+ ")->getVT() == MVT::" + LeafRec->getName());
} else if (LeafRec->isSubClassOf("CondCode")) {
// Make sure this is the specified cond code.
emitCheck("cast<CondCodeSDNode>(" + RootName +
errs() << "Cannot handle " << getEnumName(N->getTypeNum(0))
<< " type as an immediate constant. Aborting\n";
abort();
- case EVT::i1: CastType = "bool"; break;
- case EVT::i8: CastType = "unsigned char"; break;
- case EVT::i16: CastType = "unsigned short"; break;
- case EVT::i32: CastType = "unsigned"; break;
- case EVT::i64: CastType = "uint64_t"; break;
+ case MVT::i1: CastType = "bool"; break;
+ case MVT::i8: CastType = "unsigned char"; break;
+ case MVT::i16: CastType = "unsigned short"; break;
+ case MVT::i32: CastType = "unsigned"; break;
+ case MVT::i64: CastType = "uint64_t"; break;
}
emitCode("SDValue " + TmpVar +
" = CurDAG->getTargetConstant(((" + CastType +
emitCode("SDValue Tmp" + utostr(ResNo) +
" = CurDAG->getTargetConstant(" +
getQualifiedName(DI->getDef()) + "RegClassID, " +
- "EVT::i32);");
+ "MVT::i32);");
NodeOps.push_back("Tmp" + utostr(ResNo));
return NodeOps;
}
if (NodeHasOptInFlag) {
emitCode("bool HasInFlag = "
- "(N.getOperand(N.getNumOperands()-1).getValueType() == EVT::Flag);");
+ "(N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);");
}
if (IsVariadic)
emitCode("SmallVector<SDValue, 8> Ops" + utostr(OpcNo) + ";");
// How many results is this pattern expected to produce?
unsigned NumPatResults = 0;
for (unsigned i = 0, e = Pattern->getExtTypes().size(); i != e; i++) {
- EVT::SimpleValueType VT = Pattern->getTypeNum(i);
- if (VT != EVT::isVoid && VT != EVT::Flag)
+ MVT::SimpleValueType VT = Pattern->getTypeNum(i);
+ if (VT != MVT::isVoid && VT != MVT::Flag)
NumPatResults++;
}
}
emitCode("InChains.push_back(" + ChainName + ");");
emitCode(ChainName + " = CurDAG->getNode(ISD::TokenFactor, "
- "N.getDebugLoc(), EVT::Other, "
+ "N.getDebugLoc(), MVT::Other, "
"&InChains[0], InChains.size());");
if (GenDebug) {
emitCode("CurDAG->setSubgraphColor(" + ChainName +".getNode(), \"yellow\");");
// Output order: results, chain, flags
// Result types.
- if (NumResults > 0 && N->getTypeNum(0) != EVT::isVoid) {
+ if (NumResults > 0 && N->getTypeNum(0) != MVT::isVoid) {
Code += ", VT" + utostr(VTNo);
emitVT(getEnumName(N->getTypeNum(0)));
}
for (unsigned i = 0; i < NumDstRegs; i++) {
Record *RR = DstRegs[i];
if (RR->isSubClassOf("Register")) {
- EVT::SimpleValueType RVT = getRegisterValueType(RR, CGT);
+ MVT::SimpleValueType RVT = getRegisterValueType(RR, CGT);
Code += ", " + getEnumName(RVT);
}
}
if (NodeHasChain)
- Code += ", EVT::Other";
+ Code += ", MVT::Other";
if (NodeHasOutFlag)
- Code += ", EVT::Flag";
+ Code += ", MVT::Flag";
// Inputs.
if (IsVariadic) {
Record *RR = DI->getDef();
if (RR->isSubClassOf("Register")) {
- EVT::SimpleValueType RVT = getRegisterValueType(RR, T);
- if (RVT == EVT::Flag) {
+ MVT::SimpleValueType RVT = getRegisterValueType(RR, T);
+ if (RVT == MVT::Flag) {
if (!InFlagDecled) {
emitCode("SDValue InFlag = " + RootName + utostr(OpNo) + ";");
InFlagDecled = true;
assert(!PatternsOfOp.empty() && "No patterns but map has entry?");
// Split them into groups by type.
- std::map<EVT::SimpleValueType,
+ std::map<MVT::SimpleValueType,
std::vector<const PatternToMatch*> > PatternsByType;
for (unsigned i = 0, e = PatternsOfOp.size(); i != e; ++i) {
const PatternToMatch *Pat = PatternsOfOp[i];
PatternsByType[SrcPat->getTypeNum(0)].push_back(Pat);
}
- for (std::map<EVT::SimpleValueType,
+ for (std::map<MVT::SimpleValueType,
std::vector<const PatternToMatch*> >::iterator
II = PatternsByType.begin(), EE = PatternsByType.end(); II != EE;
++II) {
- EVT::SimpleValueType OpVT = II->first;
+ MVT::SimpleValueType OpVT = II->first;
std::vector<const PatternToMatch*> &Patterns = II->second;
typedef std::pair<unsigned, std::string> CodeLine;
typedef std::vector<CodeLine> CodeList;
// Print function.
std::string OpVTStr;
- if (OpVT == EVT::iPTR) {
+ if (OpVT == MVT::iPTR) {
OpVTStr = "_iPTR";
- } else if (OpVT == EVT::iPTRAny) {
+ } else if (OpVT == MVT::iPTRAny) {
OpVTStr = "_iPTRAny";
- } else if (OpVT == EVT::isVoid) {
+ } else if (OpVT == MVT::isVoid) {
// Nodes with a void result actually have a first result type of either
// Other (a chain) or Flag. Since there is no one-to-one mapping from
// void to this case, we handle it specially here.
} else {
- OpVTStr = "_" + getEnumName(OpVT).substr(5); // Skip 'EVT::'
+ OpVTStr = "_" + getEnumName(OpVT).substr(5); // Skip 'MVT::'
}
std::map<std::string, std::vector<std::string> >::iterator OpVTI =
OpcodeVTMap.find(OpName);
<< " SelectInlineAsmMemoryOperands(Ops);\n\n"
<< " std::vector<EVT> VTs;\n"
- << " VTs.push_back(EVT::Other);\n"
- << " VTs.push_back(EVT::Flag);\n"
+ << " VTs.push_back(MVT::Other);\n"
+ << " VTs.push_back(MVT::Flag);\n"
<< " SDValue New = CurDAG->getNode(ISD::INLINEASM, N.getDebugLoc(), "
"VTs, &Ops[0], Ops.size());\n"
<< " return New.getNode();\n"
OS << "SDNode *Select_DBG_LABEL(const SDValue &N) {\n"
<< " SDValue Chain = N.getOperand(0);\n"
<< " unsigned C = cast<LabelSDNode>(N)->getLabelID();\n"
- << " SDValue Tmp = CurDAG->getTargetConstant(C, EVT::i32);\n"
+ << " SDValue Tmp = CurDAG->getTargetConstant(C, MVT::i32);\n"
<< " return CurDAG->SelectNodeTo(N.getNode(), TargetInstrInfo::DBG_LABEL,\n"
- << " EVT::Other, Tmp, Chain);\n"
+ << " MVT::Other, Tmp, Chain);\n"
<< "}\n\n";
OS << "SDNode *Select_EH_LABEL(const SDValue &N) {\n"
<< " SDValue Chain = N.getOperand(0);\n"
<< " unsigned C = cast<LabelSDNode>(N)->getLabelID();\n"
- << " SDValue Tmp = CurDAG->getTargetConstant(C, EVT::i32);\n"
+ << " SDValue Tmp = CurDAG->getTargetConstant(C, MVT::i32);\n"
<< " return CurDAG->SelectNodeTo(N.getNode(), TargetInstrInfo::EH_LABEL,\n"
- << " EVT::Other, Tmp, Chain);\n"
+ << " MVT::Other, Tmp, Chain);\n"
<< "}\n\n";
OS << "SDNode *Select_DECLARE(const SDValue &N) {\n"
<< " SDValue Tmp2 = "
<< "CurDAG->getTargetGlobalAddress(GV, TLI.getPointerTy());\n"
<< " return CurDAG->SelectNodeTo(N.getNode(), TargetInstrInfo::DECLARE,\n"
- << " EVT::Other, Tmp1, Tmp2, Chain);\n"
+ << " MVT::Other, Tmp1, Tmp2, Chain);\n"
<< "}\n\n";
OS << "// The main instruction selector code.\n"
<< "SDNode *SelectCode(SDValue N) {\n"
- << " EVT::SimpleValueType NVT = N.getNode()->getValueType(0).getSimpleVT();\n"
+ << " MVT::SimpleValueType NVT = N.getNode()->getValueType(0).getSimpleVT().SimpleTy;\n"
<< " switch (N.getOpcode()) {\n"
<< " default:\n"
<< " assert(!N.isMachineOpcode() && \"Node already selected!\");\n"
HasPtrPattern = true;
continue;
}
- OS << " case EVT::" << VTStr.substr(1) << ":\n"
+ OS << " case MVT::" << VTStr.substr(1) << ":\n"
<< " return Select_" << getLegalCName(OpName)
<< VTStr << "(N);\n";
}
OS << "void CannotYetSelectIntrinsic(SDValue N) DISABLE_INLINE {\n"
<< " cerr << \"Cannot yet select: \";\n"
<< " unsigned iid = cast<ConstantSDNode>(N.getOperand("
- << "N.getOperand(0).getValueType() == EVT::Other))->getZExtValue();\n"
+ << "N.getOperand(0).getValueType() == MVT::Other))->getZExtValue();\n"
<< " llvm_report_error(\"Cannot yet select: intrinsic %\" +\n"
<< "Intrinsic::getName((Intrinsic::ID)iid));\n"
<< "}\n\n";
index e955675026a03295c70669fd3eef4e5fb0f3749a..bf92a9a0237be938b60f5b355832767dc24ec32e 100644 (file)
///
bool initialize(TreePatternNode *InstPatNode,
const CodeGenTarget &Target,
- EVT::SimpleValueType VT) {
+ MVT::SimpleValueType VT) {
if (!InstPatNode->isLeaf() &&
InstPatNode->getOperator()->getName() == "imm") {
Operands.push_back("i");
class FastISelMap {
typedef std::map<std::string, InstructionMemo> PredMap;
- typedef std::map<EVT::SimpleValueType, PredMap> RetPredMap;
- typedef std::map<EVT::SimpleValueType, RetPredMap> TypeRetPredMap;
+ typedef std::map<MVT::SimpleValueType, PredMap> RetPredMap;
+ typedef std::map<MVT::SimpleValueType, RetPredMap> TypeRetPredMap;
typedef std::map<std::string, TypeRetPredMap> OpcodeTypeRetPredMap;
typedef std::map<OperandsSignature, OpcodeTypeRetPredMap> OperandsOpcodeTypeRetPredMap;
Record *InstPatOp = InstPatNode->getOperator();
std::string OpcodeName = getOpcodeName(InstPatOp, CGP);
- EVT::SimpleValueType RetVT = InstPatNode->getTypeNum(0);
- EVT::SimpleValueType VT = RetVT;
+ MVT::SimpleValueType RetVT = InstPatNode->getTypeNum(0);
+ MVT::SimpleValueType VT = RetVT;
if (InstPatNode->getNumChildren())
VT = InstPatNode->getChild(0)->getTypeNum(0);
// Emit one function for each opcode,type pair.
for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end();
TI != TE; ++TI) {
- EVT::SimpleValueType VT = TI->first;
+ MVT::SimpleValueType VT = TI->first;
const RetPredMap &RM = TI->second;
if (RM.size() != 1) {
for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end();
RI != RE; ++RI) {
- EVT::SimpleValueType RetVT = RI->first;
+ MVT::SimpleValueType RetVT = RI->first;
const PredMap &PM = RI->second;
bool HasPred = false;
<< getLegalCName(Opcode) << "_"
<< getLegalCName(getName(VT)) << "_";
Operands.PrintManglingSuffix(OS);
- OS << "(EVT::SimpleValueType RetVT";
+ OS << "(MVT RetVT";
if (!Operands.empty())
OS << ", ";
Operands.PrintParameters(OS);
- OS << ") {\nswitch (RetVT) {\n";
+ OS << ") {\nswitch (RetVT.SimpleTy) {\n";
for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end();
RI != RE; ++RI) {
- EVT::SimpleValueType RetVT = RI->first;
+ MVT::SimpleValueType RetVT = RI->first;
OS << " case " << getName(RetVT) << ": return FastEmit_"
<< getLegalCName(Opcode) << "_" << getLegalCName(getName(VT))
<< "_" << getLegalCName(getName(RetVT)) << "_";
<< getLegalCName(Opcode) << "_"
<< getLegalCName(getName(VT)) << "_";
Operands.PrintManglingSuffix(OS);
- OS << "(EVT::SimpleValueType RetVT";
+ OS << "(MVT RetVT";
if (!Operands.empty())
OS << ", ";
Operands.PrintParameters(OS);
OS << ") {\n";
- OS << " if (RetVT != " << getName(RM.begin()->first)
+ OS << " if (RetVT.SimpleTy != " << getName(RM.begin()->first)
<< ")\n return 0;\n";
const PredMap &PM = RM.begin()->second;
OS << "unsigned FastEmit_"
<< getLegalCName(Opcode) << "_";
Operands.PrintManglingSuffix(OS);
- OS << "(EVT::SimpleValueType VT, EVT::SimpleValueType RetVT";
+ OS << "(MVT VT, MVT RetVT";
if (!Operands.empty())
OS << ", ";
Operands.PrintParameters(OS);
OS << ") {\n";
- OS << " switch (VT) {\n";
+ OS << " switch (VT.SimpleTy) {\n";
for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end();
TI != TE; ++TI) {
- EVT::SimpleValueType VT = TI->first;
+ MVT::SimpleValueType VT = TI->first;
std::string TypeName = getName(VT);
OS << " case " << TypeName << ": return FastEmit_"
<< getLegalCName(Opcode) << "_" << getLegalCName(TypeName) << "_";
// on opcode and type.
OS << "unsigned FastEmit_";
Operands.PrintManglingSuffix(OS);
- OS << "(EVT::SimpleValueType VT, EVT::SimpleValueType RetVT, ISD::NodeType Opcode";
+ OS << "(MVT VT, MVT RetVT, ISD::NodeType Opcode";
if (!Operands.empty())
OS << ", ";
Operands.PrintParameters(OS);
index 79874b1629b2292778db3ebf6025ea7eb2f6df18..1497e9029d36e9c02b4c560d8fb1ddd7fc74d5f6 100644 (file)
OS << "#endif\n\n";
}
-static void EmitTypeForValueType(raw_ostream &OS, EVT::SimpleValueType VT) {
+static void EmitTypeForValueType(raw_ostream &OS, MVT::SimpleValueType VT) {
if (EVT(VT).isInteger()) {
unsigned BitWidth = EVT(VT).getSizeInBits();
OS << "IntegerType::get(" << BitWidth << ")";
- } else if (VT == EVT::Other) {
- // EVT::OtherVT is used to mean the empty struct type here.
+ } else if (VT == MVT::Other) {
+ // MVT::OtherVT is used to mean the empty struct type here.
OS << "StructType::get(Context)";
- } else if (VT == EVT::f32) {
+ } else if (VT == MVT::f32) {
OS << "Type::FloatTy";
- } else if (VT == EVT::f64) {
+ } else if (VT == MVT::f64) {
OS << "Type::DoubleTy";
- } else if (VT == EVT::f80) {
+ } else if (VT == MVT::f80) {
OS << "Type::X86_FP80Ty";
- } else if (VT == EVT::f128) {
+ } else if (VT == MVT::f128) {
OS << "Type::FP128Ty";
- } else if (VT == EVT::ppcf128) {
+ } else if (VT == MVT::ppcf128) {
OS << "Type::PPC_FP128Ty";
- } else if (VT == EVT::isVoid) {
+ } else if (VT == MVT::isVoid) {
OS << "Type::VoidTy";
- } else if (VT == EVT::Metadata) {
+ } else if (VT == MVT::Metadata) {
OS << "Type::MetadataTy";
} else {
assert(false && "Unsupported ValueType!");
static void EmitTypeGenerate(raw_ostream &OS, const Record *ArgType,
unsigned &ArgNo) {
- EVT::SimpleValueType VT = getValueType(ArgType->getValueAsDef("VT"));
+ MVT::SimpleValueType VT = getValueType(ArgType->getValueAsDef("VT"));
if (ArgType->isSubClassOf("LLVMMatchType")) {
unsigned Number = ArgType->getValueAsInt("Number");
<< "(dyn_cast<VectorType>(Tys[" << Number << "]))";
else
OS << "Tys[" << Number << "]";
- } else if (VT == EVT::iAny || VT == EVT::fAny || VT == EVT::vAny) {
+ } else if (VT == MVT::iAny || VT == MVT::fAny || VT == MVT::vAny) {
// NOTE: The ArgNo variable here is not the absolute argument number, it is
// the index of the "arbitrary" type in the Tys array passed to the
// Intrinsic::getDeclaration function. Consequently, we only want to
} else if (EVT(VT).isVector()) {
EVT VVT = VT;
OS << "VectorType::get(";
- EmitTypeForValueType(OS, VVT.getVectorElementType().getSimpleVT());
+ EmitTypeForValueType(OS, VVT.getVectorElementType().getSimpleVT().SimpleTy);
OS << ", " << VVT.getVectorNumElements() << ")";
- } else if (VT == EVT::iPTR) {
+ } else if (VT == MVT::iPTR) {
OS << "PointerType::getUnqual(";
EmitTypeGenerate(OS, ArgType->getValueAsDef("ElTy"), ArgNo);
OS << ")";
- } else if (VT == EVT::iPTRAny) {
+ } else if (VT == MVT::iPTRAny) {
// Make sure the user has passed us an argument type to overload. If not,
// treat it as an ordinary (not overloaded) intrinsic.
OS << "(" << ArgNo << " < numTys) ? Tys[" << ArgNo
EmitTypeGenerate(OS, ArgType->getValueAsDef("ElTy"), ArgNo);
OS << ")";
++ArgNo;
- } else if (VT == EVT::isVoid) {
+ } else if (VT == MVT::isVoid) {
if (ArgNo == 0)
OS << "Type::VoidTy";
else
- // EVT::isVoid is used to mean varargs here.
+ // MVT::isVoid is used to mean varargs here.
OS << "...";
} else {
EmitTypeForValueType(OS, VT);
@@ -326,13 +326,13 @@ void IntrinsicEmitter::EmitVerifier(const std::vector<CodeGenIntrinsic> &Ints,
else
OS << "~" << Number;
} else {
- EVT::SimpleValueType VT = getValueType(ArgType->getValueAsDef("VT"));
+ MVT::SimpleValueType VT = getValueType(ArgType->getValueAsDef("VT"));
OS << getEnumName(VT);
if (EVT(VT).isOverloaded())
OverloadedTypeIndices.push_back(j);
- if (VT == EVT::isVoid && j != 0 && j != je - 1)
+ if (VT == MVT::isVoid && j != 0 && j != je - 1)
throw "Var arg type not last argument";
}
}
@@ -354,13 +354,13 @@ void IntrinsicEmitter::EmitVerifier(const std::vector<CodeGenIntrinsic> &Ints,
else
OS << "~" << Number;
} else {
- EVT::SimpleValueType VT = getValueType(ArgType->getValueAsDef("VT"));
+ MVT::SimpleValueType VT = getValueType(ArgType->getValueAsDef("VT"));
OS << getEnumName(VT);
if (EVT(VT).isOverloaded())
OverloadedTypeIndices.push_back(j + RetTys.size());
- if (VT == EVT::isVoid && j != 0 && j != je - 1)
+ if (VT == MVT::isVoid && j != 0 && j != je - 1)
throw "Var arg type not last argument";
}
}
unsigned N = ParamTys.size();
if (N > 1 &&
- getValueType(ParamTys[N - 1]->getValueAsDef("VT")) == EVT::isVoid) {
+ getValueType(ParamTys[N - 1]->getValueAsDef("VT")) == MVT::isVoid) {
OS << " IsVarArg = true;\n";
--N;
}
index 41ed56bd12f9ba8850a6ddccc2a5656b676158dc..a9bb2a13e301e7c183f9d2ea54a641c4cf2acd78 100644 (file)
<< "[] = {\n ";
for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i)
OS << getEnumName(RC.VTs[i]) << ", ";
- OS << "EVT::Other\n };\n\n";
+ OS << "MVT::Other\n };\n\n";
}
OS << "} // end anonymous namespace\n\n";