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raw | patch | inline | side by side (parent: c5142c5)
author | Matt Arsenault <Matthew.Arsenault@amd.com> | |
Sun, 10 Nov 2013 01:04:02 +0000 (01:04 +0000) | ||
committer | Matt Arsenault <Matthew.Arsenault@amd.com> | |
Sun, 10 Nov 2013 01:04:02 +0000 (01:04 +0000) |
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194340 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/R600/SIRegisterInfo.cpp | patch | blob | history | |
lib/Target/R600/SIRegisterInfo.h | patch | blob | history |
index 7f69ef6f2868c8efafc998bcafc5393903185a67..536ac9a7a2b2154386895e54fd8e052958a61bc2 100644 (file)
return NULL;
}
-bool SIRegisterInfo::isSGPRClass(const TargetRegisterClass *RC) const {
+bool SIRegisterInfo::isSGPRClass(const TargetRegisterClass *RC) {
if (!RC) {
return false;
}
index ffc57973e052f94a3e6cea36729aef3483499730..0880a898983d1e47abe4a3246a08fdadcfaa5af3 100644 (file)
const TargetRegisterClass *getPhysRegClass(unsigned Reg) const;
/// \returns true if this class contains only SGPR registers
- bool isSGPRClass(const TargetRegisterClass *RC) const;
+ static bool isSGPRClass(const TargetRegisterClass *RC);
};
} // End namespace llvm