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raw | patch | inline | side by side (parent: 2ca8b98)
raw | patch | inline | side by side (parent: 2ca8b98)
author | Kevin Enderby <enderby@apple.com> | |
Wed, 26 Mar 2014 19:35:40 +0000 (19:35 +0000) | ||
committer | Kevin Enderby <enderby@apple.com> | |
Wed, 26 Mar 2014 19:35:40 +0000 (19:35 +0000) |
size 16 double-spaced registers instruction printing.
This:
vld4.16 {d17[1], d19[1], d21[1], d23[1]}, [r7]!
was being printed as:
vld4.16 {d17[1], d18[1], d19[1], d20[1]}, [r7]!
rdar://16435096
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204847 91177308-0d34-0410-b5e6-96231b3b80d8
This:
vld4.16 {d17[1], d19[1], d21[1], d23[1]}, [r7]!
was being printed as:
vld4.16 {d17[1], d18[1], d19[1], d20[1]}, [r7]!
rdar://16435096
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204847 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/ARM/AsmParser/ARMAsmParser.cpp | patch | blob | history | |
test/MC/ARM/neon-vld-encoding.s | patch | blob | history |
index d5897720b1f49098abae47641aa91d055aca1dd1..74c4604405a2251b86a179d02289106b98c0e1f3 100644 (file)
case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
- case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNq16_UPD;
+ case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
index 648e91705782c5932d3fc36886df516f69f1b7ce..3fcbe3e902758d761358829a3de3af1786d8fe06 100644 (file)
@ CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1:32]! @ encoding: [0x3d,0x03,0xe1,0xf4]
@ CHECK: vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2:64]! @ encoding: [0x5d,0x07,0xe2,0xf4]
@ CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3:128]! @ encoding: [0xad,0x0b,0xe3,0xf4]
-@ CHECK: vld4.16 {d17[1], d18[1], d19[1], d20[1]}, [r7]! @ encoding: [0x6d,0x17,0xe7,0xf4]
+@ CHECK: vld4.16 {d17[1], d19[1], d21[1], d23[1]}, [r7]! @ encoding: [0x6d,0x17,0xe7,0xf4]
@ CHECK: vld4.32 {d16[1], d18[1], d20[1], d22[1]}, [r8]! @ encoding: [0xcd,0x0b,0xe8,0xf4]
@ CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1:32], r8 @ encoding: [0x38,0x03,0xe1,0xf4]
@ CHECK: vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2], r7 @ encoding: [0x47,0x07,0xe2,0xf4]