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raw | patch | inline | side by side (parent: fd52de3)
author | Adam Nemet <anemet@apple.com> | |
Tue, 5 Aug 2014 17:22:55 +0000 (17:22 +0000) | ||
committer | Adam Nemet <anemet@apple.com> | |
Tue, 5 Aug 2014 17:22:55 +0000 (17:22 +0000) |
They have different semantics (valign is interlane while palingr is intralane)
and palingr is still needed even in the AVX512 context. According to the
latest spec AVX512BW provides these.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214887 91177308-0d34-0410-b5e6-96231b3b80d8
and palingr is still needed even in the AVX512 context. According to the
latest spec AVX512BW provides these.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214887 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/X86/X86ISelLowering.cpp | patch | blob | history | |
lib/Target/X86/X86ISelLowering.h | patch | blob | history | |
lib/Target/X86/X86InstrFragmentsSIMD.td | patch | blob | history |
index 3b1daf74d0b15d58907f1ee36fa8c8aff84f6ac4..10867ef31116307501f60c2a40dfd3b94969af93 100644 (file)
case X86ISD::PACKSS: return "X86ISD::PACKSS";
case X86ISD::PACKUS: return "X86ISD::PACKUS";
case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
+ case X86ISD::VALIGN: return "X86ISD::VALIGN";
case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
index f0e4cf8280b1b07d265c9acaa93106a76a67bf53..a384009d9ce7cd351f10911bbd3e28ab6f2c9166 100644 (file)
// Several flavors of instructions with vector shuffle behaviors.
PACKSS,
PACKUS,
+ // Intra-lane alignr
PALIGNR,
+ // AVX512 inter-lane alignr
+ VALIGN,
PSHUFD,
PSHUFHW,
PSHUFLW,
index f5758f89a1898f25fc5250d79de1015b74b2b27f..d94dcee6f62fad846115c118e85543b833fa67fe 100644 (file)
SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
def X86PAlignr : SDNode<"X86ISD::PALIGNR", SDTShuff3OpI>;
+def X86VAlign : SDNode<"X86ISD::VALIGN", SDTShuff3OpI>;
def X86PShufd : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>;
def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>;