[Hexagon] Converting subclass members to an implicit operand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223264 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Hexagon/HexagonAsmPrinter.cpp b/lib/Target/Hexagon/HexagonAsmPrinter.cpp
index 75c2db0b8ee87683e1d4b848c794b7aa32820653..50f2eca636931d47c6997e9890237be39ec1583e 100644 (file)
--- a/lib/Target/Hexagon/HexagonAsmPrinter.cpp
+++ b/lib/Target/Hexagon/HexagonAsmPrinter.cpp
@@ -174,7 +174,7 @@ bool HexagonAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
 ///
 void HexagonAsmPrinter::EmitInstruction(const MachineInstr *MI) {
   if (MI->isBundle()) {
-    std::vector<const MachineInstr*> BundleMIs;
+    std::vector<MachineInstr const *> BundleMIs;
 
     const MachineBasicBlock *MBB = MI->getParent();
     MachineBasicBlock::const_instr_iterator MII = MI;
@@ -183,33 +183,35 @@ void HexagonAsmPrinter::EmitInstruction(const MachineInstr *MI) {
     while (MII != MBB->end() && MII->isInsideBundle()) {
       const MachineInstr *MInst = MII;
       if (MInst->getOpcode() == TargetOpcode::DBG_VALUE ||
-          MInst->getOpcode() == TargetOpcode::IMPLICIT_DEF) {
-          IgnoreCount++;
-          ++MII;
-          continue;
+        MInst->getOpcode() == TargetOpcode::IMPLICIT_DEF) {
+        IgnoreCount++;
+        ++MII;
+        continue;
       }
-      //BundleMIs.push_back(&*MII);
+      // BundleMIs.push_back(&*MII);
       BundleMIs.push_back(MInst);
       ++MII;
     }
     unsigned Size = BundleMIs.size();
-    assert((Size+IgnoreCount) == MI->getBundleSize() && "Corrupt Bundle!");
+    assert((Size + IgnoreCount) == MI->getBundleSize() && "Corrupt Bundle!");
     for (unsigned Index = 0; Index < Size; Index++) {
       HexagonMCInst MCI;
-      MCI.setPacketBegin(Index == 0);
-      MCI.setPacketEnd(Index == (Size-1));
 
       HexagonLowerToMC(BundleMIs[Index], MCI, *this);
+      HexagonMCInst::AppendImplicitOperands(MCI);
+      MCI.setPacketBegin(Index == 0);
+      MCI.setPacketEnd(Index == (Size - 1));
       EmitToStreamer(OutStreamer, MCI);
     }
   }
   else {
     HexagonMCInst MCI;
+    HexagonLowerToMC(MI, MCI, *this);
+    HexagonMCInst::AppendImplicitOperands(MCI);
     if (MI->getOpcode() == Hexagon::ENDLOOP0) {
       MCI.setPacketBegin(true);
       MCI.setPacketEnd(true);
     }
-    HexagonLowerToMC(MI, MCI, *this);
     EmitToStreamer(OutStreamer, MCI);
   }
 

diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCInst.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonMCInst.cpp
index 6072527cfc88cca0e02a12f0fa136181cd5e21d0..18a596e9b67a70759bd9fd7d37c344d1ac25f7f5 100644 (file)
--- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCInst.cpp
+++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCInst.cpp
@@ -18,15 +18,47 @@
 
 using namespace llvm;
 
-HexagonMCInst::HexagonMCInst()
-    : MCInst(), MCID(nullptr), packetBegin(0), packetEnd(0){}
-HexagonMCInst::HexagonMCInst(MCInstrDesc const &mcid)
-    : MCInst(), MCID(&mcid), packetBegin(0), packetEnd(0){}
-
-bool HexagonMCInst::isPacketBegin() const { return (packetBegin); }
-bool HexagonMCInst::isPacketEnd() const { return (packetEnd); }
-void HexagonMCInst::setPacketBegin(bool Y) { packetBegin = Y; }
-void HexagonMCInst::setPacketEnd(bool Y) { packetEnd = Y; }
+HexagonMCInst::HexagonMCInst() : MCInst(), MCID(nullptr) {}
+HexagonMCInst::HexagonMCInst(MCInstrDesc const &mcid) : MCInst(), MCID(&mcid) {}
+
+void HexagonMCInst::AppendImplicitOperands(MCInst &MCI) {
+  MCI.addOperand(MCOperand::CreateImm(0));
+  MCI.addOperand(MCOperand::CreateInst(nullptr));
+}
+
+std::bitset<16> HexagonMCInst::GetImplicitBits(MCInst const &MCI) {
+  SanityCheckImplicitOperands(MCI);
+  std::bitset<16> Bits(MCI.getOperand(MCI.getNumOperands() - 2).getImm());
+  return Bits;
+}
+
+void HexagonMCInst::SetImplicitBits(MCInst &MCI, std::bitset<16> Bits) {
+  SanityCheckImplicitOperands(MCI);
+  MCI.getOperand(MCI.getNumOperands() - 2).setImm(Bits.to_ulong());
+}
+
+void HexagonMCInst::setPacketBegin(bool f) {
+  std::bitset<16> Bits(GetImplicitBits(*this));
+  Bits.set(packetBeginIndex, f);
+  SetImplicitBits(*this, Bits);
+}
+
+bool HexagonMCInst::isPacketBegin() const {
+  std::bitset<16> Bits(GetImplicitBits(*this));
+  return Bits.test(packetBeginIndex);
+}
+
+void HexagonMCInst::setPacketEnd(bool f) {
+  std::bitset<16> Bits(GetImplicitBits(*this));
+  Bits.set(packetEndIndex, f);
+  SetImplicitBits(*this, Bits);
+}
+
+bool HexagonMCInst::isPacketEnd() const {
+  std::bitset<16> Bits(GetImplicitBits(*this));
+  return Bits.test(packetEndIndex);
+}
+
 void HexagonMCInst::resetPacket() {
   setPacketBegin(false);
   setPacketEnd(false);

diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCInst.h b/lib/Target/Hexagon/MCTargetDesc/HexagonMCInst.h
index 5d46ce283ae5ed2fb4bc92eb213a7eab8249388e..f9acab70a9e6e60120c6ab4da50880515fef08d8 100644 (file)
--- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCInst.h
+++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCInst.h
@@ -26,17 +26,27 @@ class HexagonMCInst : public MCInst {
   // use in checking MC instruction properties.
   const MCInstrDesc *MCID;
 
-  // Packet start and end markers
-  unsigned packetBegin : 1, packetEnd : 1;
-
 public:
   explicit HexagonMCInst();
   HexagonMCInst(const MCInstrDesc &mcid);
 
-  bool isPacketBegin() const;
-  bool isPacketEnd() const;
+  static void AppendImplicitOperands(MCInst &MCI);
+  static std::bitset<16> GetImplicitBits(MCInst const &MCI);
+  static void SetImplicitBits(MCInst &MCI, std::bitset<16> Bits);
+  static void SanityCheckImplicitOperands(MCInst const &MCI) {
+    assert(MCI.getNumOperands() >= 2 && "At least the two implicit operands");
+    assert(MCI.getOperand(MCI.getNumOperands() - 1).isInst() &&
+           "Implicit bits and flags");
+    assert(MCI.getOperand(MCI.getNumOperands() - 2).isImm() &&
+           "Parent pointer");
+  }
+
   void setPacketBegin(bool Y);
+  bool isPacketBegin() const;
+  size_t const packetBeginIndex = 0;
   void setPacketEnd(bool Y);
+  bool isPacketEnd() const;
+  size_t const packetEndIndex = 1;
   void resetPacket();
 
   // Return the slots used by the insn.