[X86][SSE] Vector integer/float conversion memory folding (cvttps2dq / cvttpd2dq)

Fixed an issue with the (v)cvttps2dq and (v)cvttpd2dq instructions being incorrectly put in the 2 source operand folding tables instead of the 1 source operand and added the missing SSE/AVX versions.

Also added missing (v)cvtps2dq and (v)cvtpd2dq instructions to the folding tables.

Differential Revision: http://reviews.llvm.org/D6001

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221489 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index a49dcc7d160cf40f64c0750bc01d3a72fd604947..68c5ff44ca9ffaa8ff31dec4dc9513c16814fdce 100644 (file)
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -449,6 +449,8 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
     { X86::CVTSS2SI64rr,    X86::CVTSS2SI64rm,        0 },
     { X86::CVTSS2SIrr,      X86::CVTSS2SIrm,          0 },
     { X86::CVTDQ2PSrr,      X86::CVTDQ2PSrm,          TB_ALIGN_16 },
+    { X86::CVTPD2DQrr,      X86::CVTPD2DQrm,          TB_ALIGN_16 },
+    { X86::CVTPS2DQrr,      X86::CVTPS2DQrm,          TB_ALIGN_16 },
     { X86::CVTTPD2DQrr,     X86::CVTTPD2DQrm,         TB_ALIGN_16 },
     { X86::CVTTPS2DQrr,     X86::CVTTPS2DQrm,         TB_ALIGN_16 },
     { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm,  0 },
@@ -528,6 +530,10 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
     { X86::VCVTSS2SI64rr,   X86::VCVTSS2SI64rm,       0 },
     { X86::VCVTSS2SIrr,     X86::VCVTSS2SIrm,         0 },
     { X86::VCVTDQ2PSrr,     X86::VCVTDQ2PSrm,         0 },
+    { X86::VCVTPD2DQrr,     X86::VCVTPD2DQXrm,        0 },
+    { X86::VCVTPS2DQrr,     X86::VCVTPS2DQrm,         0 },
+    { X86::VCVTTPD2DQrr,    X86::VCVTTPD2DQXrm,       0 },
+    { X86::VCVTTPS2DQrr,    X86::VCVTTPS2DQrm,        0 },
     { X86::VMOV64toPQIrr,   X86::VMOVQI2PQIrm,        0 },
     { X86::VMOV64toSDrr,    X86::VMOV64toSDrm,        0 },
     { X86::VMOVAPDrr,       X86::VMOVAPDrm,           TB_ALIGN_16 },
@@ -562,6 +568,10 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
 
     // AVX 256-bit foldable instructions
     { X86::VCVTDQ2PSYrr,    X86::VCVTDQ2PSYrm,        0 },
+    { X86::VCVTPD2DQYrr,    X86::VCVTPD2DQYrm,        0 },
+    { X86::VCVTPS2DQYrr,    X86::VCVTPS2DQYrm,        0 },
+    { X86::VCVTTPD2DQYrr,   X86::VCVTTPD2DQYrm,       0 },
+    { X86::VCVTTPS2DQYrr,   X86::VCVTTPS2DQYrm,       0 },
     { X86::VMOVAPDYrr,      X86::VMOVAPDYrm,          TB_ALIGN_32 },
     { X86::VMOVAPSYrr,      X86::VMOVAPSYrm,          TB_ALIGN_32 },
     { X86::VMOVDQAYrr,      X86::VMOVDQAYrm,          TB_ALIGN_32 },
@@ -933,8 +943,6 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
     { X86::Int_VCVTSI2SSrr,   X86::Int_VCVTSI2SSrm,    0 },
     { X86::VCVTSS2SDrr,       X86::VCVTSS2SDrm,        0 },
     { X86::Int_VCVTSS2SDrr,   X86::Int_VCVTSS2SDrm,    0 },
-    { X86::VCVTTPD2DQrr,      X86::VCVTTPD2DQXrm,      0 },
-    { X86::VCVTTPS2DQrr,      X86::VCVTTPS2DQrm,       0 },
     { X86::VRSQRTSSr,         X86::VRSQRTSSm,          0 },
     { X86::VSQRTSDr,          X86::VSQRTSDm,           0 },
     { X86::VSQRTSSr,          X86::VSQRTSSm,           0 },

diff --git a/test/CodeGen/X86/avx1-stack-reload-folding.ll b/test/CodeGen/X86/avx1-stack-reload-folding.ll
index 7b232026ec1008a358727a384124065896054509..2e669b0fe125e62a3d810fa308d776223d46926a 100644 (file)
--- a/test/CodeGen/X86/avx1-stack-reload-folding.ll
+++ b/test/CodeGen/X86/avx1-stack-reload-folding.ll
@@ -10,7 +10,9 @@ target triple = "x86_64-unknown-unknown"
 ; being tested - the load-execute version of the instruction from the tables would be matched instead.\r
 \r
 define void @stack_fold_vmulpd(<64 x double>* %a, <64 x double>* %b, <64 x double>* %c) {\r
+  ;CHECK-LABEL: stack_fold_vmulpd\r
   ;CHECK:       vmulpd {{[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload\r
+\r
   %1 = load <64 x double>* %a\r
   %2 = load <64 x double>* %b\r
   %3 = fadd <64 x double> %1, %2\r
@@ -21,7 +23,9 @@ define void @stack_fold_vmulpd(<64 x double>* %a, <64 x double>* %b, <64 x doubl
 }\r
 \r
 define void @stack_fold_cvtdq2ps(<128 x i32>* %a, <128 x i32>* %b, <128 x float>* %c) {\r
+  ;CHECK-LABEL: stack_fold_cvtdq2ps\r
   ;CHECK:   vcvtdq2ps {{[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload\r
+\r
   %1 = load <128 x i32>* %a\r
   %2 = load <128 x i32>* %b\r
   %3 = and <128 x i32> %1, %2\r
@@ -32,3 +36,33 @@ define void @stack_fold_cvtdq2ps(<128 x i32>* %a, <128 x i32>* %b, <128 x float>
   store <128 x float> %7, <128 x float>* %c\r
   ret void\r
 }\r
+\r
+define void @stack_fold_cvttpd2dq(<64 x double>* %a, <64 x double>* %b, <64 x i32>* %c) #0 {\r
+  ;CHECK-LABEL: stack_fold_cvttpd2dq\r
+  ;CHECK:  vcvttpd2dqy {{[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload\r
+\r
+  %1 = load <64 x double>* %a\r
+  %2 = load <64 x double>* %b\r
+  %3 = fadd <64 x double> %1, %2\r
+  %4 = fsub <64 x double> %1, %2\r
+  %5 = fptosi <64 x double> %3 to <64 x i32>\r
+  %6 = fptosi <64 x double> %4 to <64 x i32>\r
+  %7 = or <64 x i32> %5, %6\r
+  store <64 x i32> %7, <64 x i32>* %c\r
+  ret void\r
+}\r
+\r
+define void @stack_fold_cvttps2dq(<128 x float>* %a, <128 x float>* %b, <128 x i32>* %c) #0 {\r
+  ;CHECK-LABEL: stack_fold_cvttps2dq\r
+  ;CHECK:   vcvttps2dq {{[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload\r
+\r
+  %1 = load <128 x float>* %a\r
+  %2 = load <128 x float>* %b\r
+  %3 = fadd <128 x float> %1, %2\r
+  %4 = fsub <128 x float> %1, %2\r
+  %5 = fptosi <128 x float> %3 to <128 x i32>\r
+  %6 = fptosi <128 x float> %4 to <128 x i32>\r
+  %7 = or <128 x i32> %5, %6\r
+  store <128 x i32> %7, <128 x i32>* %c\r
+  ret void\r
+}\r