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raw | patch | inline | side by side (parent: 8fe9488)
author | Colin LeMahieu <colinl@codeaurora.org> | |
Tue, 16 Dec 2014 17:44:49 +0000 (17:44 +0000) | ||
committer | Colin LeMahieu <colinl@codeaurora.org> | |
Tue, 16 Dec 2014 17:44:49 +0000 (17:44 +0000) |
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224346 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/Hexagon/HexagonInstrInfo.td | patch | blob | history | |
test/MC/Disassembler/Hexagon/xtype_alu.txt | patch | blob | history | |
test/MC/Disassembler/Hexagon/xtype_bit.txt | patch | blob | history |
index b5711c27fee1183619c8ad2544275dcbf3a0c241..8a86ae98402fe31cc6f6c6c4a30310a4c336b3eb 100644 (file)
"$dst = not($src1)",
[(set (i64 DoubleRegs:$dst), (not (i64 DoubleRegs:$src1)))]>;
+
+//===----------------------------------------------------------------------===//
+// STYPE/ALU -
+//===----------------------------------------------------------------------===//
+
let hasSideEffects = 0 in
class T_S2op_1 <string mnemonic, bits<4> RegTyBits, RegisterClass RCOut,
RegisterClass RCIn, bits<2> MajOp, bits<3> MinOp, bit isSat>
def: Pat <(i64 (sext I32:$src)), (A2_sxtw I32:$src)>;
-//===----------------------------------------------------------------------===//
-// STYPE/ALU -
-//===----------------------------------------------------------------------===//
-
-
// Swizzle the bytes of a word
let isCodeGenOnly = 0 in
def A2_swiz : T_S2op_1_ii <"swiz", 0b10, 0b111>;
def A2_satuh : T_S2op_1_ii <"satuh", 0b11, 0b101>;
}
+let Itinerary = S_2op_tc_2_SLOT23, isCodeGenOnly = 0 in {
+ // Absolute value word
+ def A2_abs : T_S2op_1_ii <"abs", 0b10, 0b100>;
+
+ let Defs = [USR_OVF] in
+ def A2_abssat : T_S2op_1_ii <"abs", 0b10, 0b101, 1>;
+
+ // Negate with saturation
+ let Defs = [USR_OVF] in
+ def A2_negsat : T_S2op_1_ii <"neg", 0b10, 0b110, 1>;
+}
+
+def: Pat<(i32 (select (i1 (setlt (i32 IntRegs:$src), 0)),
+ (i32 (sub 0, (i32 IntRegs:$src))),
+ (i32 IntRegs:$src))),
+ (A2_abs IntRegs:$src)>;
+
+let AddedComplexity = 50 in
+def: Pat<(i32 (xor (add (sra (i32 IntRegs:$src), (i32 31)),
+ (i32 IntRegs:$src)),
+ (sra (i32 IntRegs:$src), (i32 31)))),
+ (A2_abs IntRegs:$src)>;
+
+
//===----------------------------------------------------------------------===//
// STYPE/BIT +
//===----------------------------------------------------------------------===//
diff --git a/test/MC/Disassembler/Hexagon/xtype_alu.txt b/test/MC/Disassembler/Hexagon/xtype_alu.txt
index 66bdc4379010c5307b8b196dffc78f98cd9cbe4e..4603432d17367be2f902dfb468bad48346a1488f 100644 (file)
# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
+0x91 0xc0 0x95 0x8c
+# CHECK: r17 = abs(r21)
+0xb1 0xc0 0x95 0x8c
+# CHECK: r17 = abs(r21):sat
0xf1 0xc2 0x15 0xe2
# CHECK: r17 += add(r21, #23)
0xf1 0xc2 0x95 0xe2
# CHECK: r17:16 = add(r21:20, r31:30):raw:hi
0x10 0xde 0xf4 0xd3
# CHECK: r17:16 = and(r21:20, r31:30)
+0x50 0xde 0xf4 0xd3
+# CHECK: r17:16 = or(r21:20, r31:30)
0x71 0xdf 0x95 0xef
# CHECK: r17 ^= xor(r21, r31)
0x11 0xdf 0xd5 0xd5
# CHECK: r17:16 = min(r21:20, r31:30)
0xf0 0xd4 0xbe 0xd3
# CHECK: r17:16 = minu(r21:20, r31:30)
-0x50 0xde 0xf4 0xd3
-# CHECK: r17:16 = or(r21:20, r31:30)
+0xd1 0xc0 0x95 0x8c
+# CHECK: r17 = neg(r21):sat
0x71 0xd5 0x1f 0xef
# CHECK: r17 += sub(r21, r31)
0x11 0xd5 0x3f 0xd5
diff --git a/test/MC/Disassembler/Hexagon/xtype_bit.txt b/test/MC/Disassembler/Hexagon/xtype_bit.txt
index d0f63770d6b87e6cc65fb197c26c22aa1f3cda70..021631dde55a56af5a22820652249387974b5450 100644 (file)
# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
0x11 0xde 0x14 0xd0
-# CHECK: r17 = parity(r21:20, r31:30)
\ No newline at end of file
+# CHECK: r17 = parity(r21:20, r31:30)