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raw | patch | inline | side by side (parent: ad4ffce)
| author | Richard Osborne <richard@xmos.com> | |
| Thu, 27 Feb 2014 14:24:13 +0000 (14:24 +0000) | ||
| committer | Richard Osborne <richard@xmos.com> | |
| Thu, 27 Feb 2014 14:24:13 +0000 (14:24 +0000) |
These are causing test failures, revert for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202398 91177308-0d34-0410-b5e6-96231b3b80d8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202398 91177308-0d34-0410-b5e6-96231b3b80d8
index e149e6d9ec20bde6734c737f9ebc8d9f5c42fbc4..b20d71f49cfd6c403934d02570ec6857994d5ded 100644 (file)
//===----------------------------------------------------------------------===//
def RetCC_XCore : CallingConv<[
// i32 are returned in registers R0, R1, R2, R3
- CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
-
- // Integer values get stored in stack slots that are 4 bytes in
- // size and 4-byte aligned.
- CCIfType<[i32], CCAssignToStack<4, 4>>
+ CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>
]>;
//===----------------------------------------------------------------------===//
index 67dc19b0aa52888dc16bfef20803c75e528ff3ea..450f0771d908a011e02695a5cc64039eee62e8d0 100644 (file)
case XCoreISD::PCRelativeWrapper : return "XCoreISD::PCRelativeWrapper";
case XCoreISD::DPRelativeWrapper : return "XCoreISD::DPRelativeWrapper";
case XCoreISD::CPRelativeWrapper : return "XCoreISD::CPRelativeWrapper";
- case XCoreISD::LDWSP : return "XCoreISD::LDWSP";
case XCoreISD::STWSP : return "XCoreISD::STWSP";
case XCoreISD::RETSP : return "XCoreISD::RETSP";
case XCoreISD::LADD : return "XCoreISD::LADD";
}
}
-/// LowerCallResult - Lower the result values of a call into the
-/// appropriate copies out of appropriate physical registers / memory locations.
-static SDValue
-LowerCallResult(SDValue Chain, SDValue InFlag,
- const SmallVectorImpl<CCValAssign> &RVLocs,
- SDLoc dl, SelectionDAG &DAG,
- SmallVectorImpl<SDValue> &InVals) {
- SmallVector<std::pair<int, unsigned>, 4> ResultMemLocs;
- // Copy results out of physical registers.
- for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
- const CCValAssign &VA = RVLocs[i];
- if (VA.isRegLoc()) {
- Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getValVT(),
- InFlag).getValue(1);
- InFlag = Chain.getValue(2);
- InVals.push_back(Chain.getValue(0));
- } else {
- assert(VA.isMemLoc());
- ResultMemLocs.push_back(std::make_pair(VA.getLocMemOffset(),
- InVals.size()));
- // Reserve space for this result.
- InVals.push_back(SDValue());
- }
- }
-
- // Copy results out of memory.
- SmallVector<SDValue, 4> MemOpChains;
- for (unsigned i = 0, e = ResultMemLocs.size(); i != e; ++i) {
- int offset = ResultMemLocs[i].first;
- unsigned index = ResultMemLocs[i].second;
- SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other);
- SDValue Ops[] = { Chain, DAG.getConstant(offset / 4, MVT::i32) };
- SDValue load = DAG.getNode(XCoreISD::LDWSP, dl, VTs, Ops, 2);
- InVals[index] = load;
- MemOpChains.push_back(load.getValue(1));
- }
-
- // Transform all loads nodes into one single node because
- // all load nodes are independent of each other.
- if (!MemOpChains.empty())
- Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
- &MemOpChains[0], MemOpChains.size());
-
- return Chain;
-}
-
/// LowerCCCCallTo - functions arguments are copied from virtual
/// regs to (physical regs)/(stack frame), CALLSEQ_START and
/// CALLSEQ_END are emitted.
CCInfo.AnalyzeCallOperands(Outs, CC_XCore);
- SmallVector<CCValAssign, 16> RVLocs;
- // Analyze return values to determine the number of bytes of stack required.
- CCState RetCCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
- getTargetMachine(), RVLocs, *DAG.getContext());
- RetCCInfo.AllocateStack(CCInfo.getNextStackOffset(), 4);
- RetCCInfo.AnalyzeCallResult(Ins, RetCC_XCore);
-
// Get a count of how many bytes are to be pushed on the stack.
- unsigned NumBytes = RetCCInfo.getNextStackOffset();
+ unsigned NumBytes = CCInfo.getNextStackOffset();
Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes,
getPointerTy(), true), dl);
// Handle result values, copying them out of physregs into vregs that we
// return.
- return LowerCallResult(Chain, InFlag, RVLocs, dl, DAG, InVals);
+ return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
+ Ins, dl, DAG, InVals);
+}
+
+/// LowerCallResult - Lower the result values of a call into the
+/// appropriate copies out of appropriate physical registers.
+SDValue
+XCoreTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
+ CallingConv::ID CallConv, bool isVarArg,
+ const SmallVectorImpl<ISD::InputArg> &Ins,
+ SDLoc dl, SelectionDAG &DAG,
+ SmallVectorImpl<SDValue> &InVals) const {
+
+ // Assign locations to each value returned by this call.
+ SmallVector<CCValAssign, 16> RVLocs;
+ CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
+ getTargetMachine(), RVLocs, *DAG.getContext());
+
+ CCInfo.AnalyzeCallResult(Ins, RetCC_XCore);
+
+ // Copy all of the result registers out of their specified physreg.
+ for (unsigned i = 0; i != RVLocs.size(); ++i) {
+ Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
+ RVLocs[i].getValVT(), InFlag).getValue(1);
+ InFlag = Chain.getValue(2);
+ InVals.push_back(Chain.getValue(0));
+ }
+
+ return Chain;
}
//===----------------------------------------------------------------------===//
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo *MFI = MF.getFrameInfo();
MachineRegisterInfo &RegInfo = MF.getRegInfo();
- XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
// Assign locations to all of the incoming arguments.
SmallVector<CCValAssign, 16> ArgLocs;
unsigned LRSaveSize = StackSlotSize;
- if (!isVarArg)
- XFI->setReturnStackOffset(CCInfo.getNextStackOffset() + LRSaveSize);
-
// All getCopyFromReg ops must precede any getMemcpys to prevent the
// scheduler clobbering a register before it has been copied.
// The stages are:
LLVMContext &Context) const {
SmallVector<CCValAssign, 16> RVLocs;
CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), RVLocs, Context);
- if (!CCInfo.CheckReturn(Outs, RetCC_XCore))
- return false;
- if (CCInfo.getNextStackOffset() != 0 && isVarArg)
- return false;
- return true;
+ return CCInfo.CheckReturn(Outs, RetCC_XCore);
}
SDValue
const SmallVectorImpl<SDValue> &OutVals,
SDLoc dl, SelectionDAG &DAG) const {
- XCoreFunctionInfo *XFI =
- DAG.getMachineFunction().getInfo<XCoreFunctionInfo>();
- MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
-
// CCValAssign - represent the assignment of
// the return value to a location
SmallVector<CCValAssign, 16> RVLocs;
getTargetMachine(), RVLocs, *DAG.getContext());
// Analyze return values.
- if (!isVarArg)
- CCInfo.AllocateStack(XFI->getReturnStackOffset(), 4);
-
CCInfo.AnalyzeReturn(Outs, RetCC_XCore);
SDValue Flag;
// Return on XCore is always a "retsp 0"
RetOps.push_back(DAG.getConstant(0, MVT::i32));
- SmallVector<SDValue, 4> MemOpChains;
- // Handle return values that must be copied to memory.
- for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
+ // Copy the result values into the output registers.
+ for (unsigned i = 0; i != RVLocs.size(); ++i) {
CCValAssign &VA = RVLocs[i];
- if (VA.isRegLoc())
- continue;
- assert(VA.isMemLoc());
- if (isVarArg) {
- report_fatal_error("Can't return value from vararg function in memory");
- }
+ assert(VA.isRegLoc() && "Can only return in registers!");
- int Offset = VA.getLocMemOffset();
- unsigned ObjSize = VA.getLocVT().getSizeInBits() / 8;
- // Create the frame index object for the memory location.
- int FI = MFI->CreateFixedObject(ObjSize, Offset, false);
-
- // Create a SelectionDAG node corresponding to a store
- // to this memory location.
- SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
- MemOpChains.push_back(DAG.getStore(Chain, dl, OutVals[i], FIN,
- MachinePointerInfo::getFixedStack(FI), false, false,
- 0));
- }
-
- // Transform all store nodes into one single node because
- // all stores are independent of each other.
- if (!MemOpChains.empty())
- Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
- &MemOpChains[0], MemOpChains.size());
-
- // Now handle return values copied to registers.
- for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
- CCValAssign &VA = RVLocs[i];
- if (!VA.isRegLoc())
- continue;
- // Copy the result values into the output registers.
- Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
+ Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
+ OutVals[i], Flag);
// guarantee that all emitted copies are
// stuck together, avoiding something bad
index 65e2bad4f08a749c01ec4ac0688b6b1e336f9a67..e05068f773adf6a2e01ac2e97bea902fe92d6178 100644 (file)
// cp relative address
CPRelativeWrapper,
- // Load word from stack
- LDWSP,
-
// Store word to stack
STWSP,
const SmallVectorImpl<ISD::InputArg> &Ins,
SDLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const;
+ SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
+ CallingConv::ID CallConv, bool isVarArg,
+ const SmallVectorImpl<ISD::InputArg> &Ins,
+ SDLoc dl, SelectionDAG &DAG,
+ SmallVectorImpl<SDValue> &InVals) const;
SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
SDValue getGlobalAddressWrapper(SDValue GA, const GlobalValue *GV,
SelectionDAG &DAG) const;
index b6906569aa390f4bc38b434481ef1eb72893eabc..b243ee3510a90e5b8de8a414a970c82494ed1f55 100644 (file)
def XCoreStwsp : SDNode<"XCoreISD::STWSP", SDT_XCoreStwsp,
[SDNPHasChain, SDNPMayStore]>;
-def SDT_XCoreLdwsp : SDTypeProfile<1, 1, [SDTCisInt<1>]>;
-def XCoreLdwsp : SDNode<"XCoreISD::LDWSP", SDT_XCoreLdwsp,
- [SDNPHasChain, SDNPMayLoad]>;
-
// These are target-independent nodes, but have target-specific formats.
def SDT_XCoreCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
def SDT_XCoreCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
let mayLoad=1 in {
def LDWSP_ru6 : _FRU6<0b010111, (outs RRegs:$a), (ins i32imm:$b),
- "ldw $a, sp[$b]",
- [(set RRegs:$a, (XCoreLdwsp immU6:$b))]>;
+ "ldw $a, sp[$b]", []>;
def LDWSP_lru6 : _FLRU6<0b010111, (outs RRegs:$a), (ins i32imm:$b),
- "ldw $a, sp[$b]",
- [(set RRegs:$a, (XCoreLdwsp immU16:$b))]>;
+ "ldw $a, sp[$b]", []>;
}
let neverHasSideEffects = 1 in {
diff --git a/lib/Target/XCore/XCoreMachineFunctionInfo.h b/lib/Target/XCore/XCoreMachineFunctionInfo.h
index 2649300b44d5df8469655a105e81942dc2377617..f1777a87e114171cd318d11c407eb1e0eb218210 100644 (file)
int FPSpillSlot;
bool EHSpillSlotSet;
int EHSpillSlot[2];
- unsigned ReturnStackOffset;
- bool ReturnStackOffsetSet;
int VarArgsFrameIndex;
mutable int CachedEStackSize;
std::vector<std::pair<MCSymbol*, CalleeSavedInfo> > SpillLabels;
LRSpillSlotSet(false),
FPSpillSlotSet(false),
EHSpillSlotSet(false),
- ReturnStackOffsetSet(false),
VarArgsFrameIndex(0),
CachedEStackSize(-1) {}
return EHSpillSlot;
}
- void setReturnStackOffset(unsigned value) {
- assert(!ReturnStackOffsetSet && "Return stack offset set twice");
- ReturnStackOffset = value;
- ReturnStackOffsetSet = true;
- }
-
- unsigned getReturnStackOffset() const {
- assert(ReturnStackOffsetSet && "Return stack offset not set");
- return ReturnStackOffset;
- }
-
bool isLargeFrame(const MachineFunction &MF) const;
std::vector<std::pair<MCSymbol*, CalleeSavedInfo> > &getSpillLabels() {
index 567b3720919595b5f0000ab8faaf3aac4704da65..877c57140a1dbe0c7ea3663707bb36058315f422 100644 (file)
%0 = type { i32, i32, i32, i32 }
%1 = type { i32, i32, i32, i32, i32 }
-; Structs of 4 words are returned in registers
-define internal %0 @ReturnBigStruct() nounwind readnone {
+; Structs of 4 words can be returned in registers
+define internal fastcc %0 @ReturnBigStruct() nounwind readnone {
entry:
%0 = insertvalue %0 zeroinitializer, i32 12, 0
%1 = insertvalue %0 %0, i32 24, 1
; CHECK: ldc r3, 24601
; CHECK: retsp 0
-; Structs of more than 4 words are partially returned in memory so long as the
-; function is not variadic.
-define { i32, i32, i32, i32, i32} @f(i32, i32, i32, i32, i32) nounwind readnone {
-; CHECK-LABEL: f:
-; CHECK: ldc [[REGISTER:r[0-9]+]], 5
-; CHECK-NEXT: stw [[REGISTER]], sp[2]
-; CHECK-NEXT: retsp 0
-body:
- ret { i32, i32, i32, i32, i32} { i32 undef, i32 undef, i32 undef, i32 undef, i32 5}
-}
-
-@x = external global i32
-@y = external global i32
-
-; Check we call a function returning more than 4 words correctly.
-define i32 @g() nounwind {
-; CHECK-LABEL: g:
-; CHECK: entsp 3
-; CHECK: ldc [[REGISTER:r[0-9]+]], 0
-; CHECK: stw [[REGISTER]], sp[1]
-; CHECK: bl f
-; CHECK-NEXT: ldw r0, sp[2]
-; CHECK-NEXT: retsp 3
-;
-body:
- %0 = call { i32, i32, i32, i32, i32 } @f(i32 0, i32 0, i32 0, i32 0, i32 0)
- %1 = extractvalue { i32, i32, i32, i32, i32 } %0, 4
- ret i32 %1
-}
-
-; Variadic functions return structs bigger than 4 words via a hidden
-; sret-parameter
-define internal %1 @ReturnBigStruct2(i32 %dummy, ...) nounwind readnone {
+; Structs bigger than 4 words are returned via a hidden hidden sret-parameter
+define internal fastcc %1 @ReturnBigStruct2() nounwind readnone {
entry:
%0 = insertvalue %1 zeroinitializer, i32 12, 0
%1 = insertvalue %1 %0, i32 24, 1