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Updates to sync with changes in upstream.
[opencl/llvm.git] / lib / Target / R600 /
2015-01-21 Matt ArsenaultR600/SI: Custom lower fround
2015-01-20 Tom StellardR600/SI: Add subtarget feature to enable VGPR spilling...
2015-01-20 Tom StellardR600/SI: Fix simple-loop.ll test
2015-01-20 Tom StellardR600/SI: Remove stray debugging code from r226586
2015-01-20 Tom StellardR600/SI: Use external symbols for scratch buffer
2015-01-20 Tom StellardR600/SI: Add kill flag when copying scratch offset...
2015-01-20 Tom StellardR600/SI: Don't store scratch buffer frame index in...
2015-01-20 Tom StellardR600/SI: Update SIInstrInfo:verifyInstruction() after...
2015-01-19 Rafael EspindolaAdd r224985 back with fixes.
2015-01-18 David Blaikiestd::unique_ptrify the MCStreamer argument to createAsm...
2015-01-15 Matt ArsenaultR600/SI: Add patterns for v_cvt_{flr|rpi}_i32_f32
2015-01-15 Matt ArsenaultR600/SI: Fix trailing comma with modifiers
2015-01-15 Marek OlsakR600/SI: Unify VOP2 instructions which are VOP3-only...
2015-01-15 Marek OlsakR600/SI: Use 64-bit encoding by default for opcodes...
2015-01-15 Marek OlsakR600/SI: Add V_READLANE_B32 and V_WRITELANE_B32 for VI
2015-01-15 Marek OlsakR600/SI: Don't shrink instructions whose e32 encoding...
2015-01-15 Marek OlsakR600/SI: Add common class VOPAnyCommon
2015-01-15 Marek OlsakR600/SI: Don't select SI-only VOP3 opcodes on VI
2015-01-14 Rafael EspindolaRevert "Add r224985 back with two fixes."
2015-01-14 Tom StellardR600/SI: Use IMPLICIT_DEF and KILL when failing to...
2015-01-14 Tom StellardR600/SI: Spill VGPRs to scratch space for compute shaders
2015-01-14 Chandler Carruth[cleanup] Re-sort all the #include lines in LLVM using
2015-01-14 Matt ArsenaultR600/SI: Fix bad code with unaligned byte vector loads
2015-01-14 Matt ArsenaultImplement new way of expanding extloads.
2015-01-14 Tom StellardR600/SI: Define a schedule model
2015-01-13 Tom StellardR600/SI: Add pattern for bitcasting fp immediates to...
2015-01-13 Matt ArsenaultR600: Implement getRecipEstimate
2015-01-13 Matt ArsenaultR600: Implement getRsqrtEstimate
2015-01-13 Matt ArsenaultR600: Make cttz / ctlz cheap to speculate
2015-01-12 Matt ArsenaultR600/SI: Remove redundant setting expand on f64 vectors
2015-01-12 Tom StellardR600/SI: Use RegisterOperands to specify which operands...
2015-01-12 Rafael EspindolaAdd r224985 back with two fixes.
2015-01-08 Tom StellardR600/SI: Remove SIISelLowering::legalizeOperands()
2015-01-08 Ahmed Bougacha[SelectionDAG] Allow targets to specify legality of...
2015-01-07 Tom StellardR600/SI: Commute instructions to enable more folding...
2015-01-07 Tom StellardR600/SI: Only fold immediates that have one use
2015-01-07 Tom StellardR600/SI: Remove VReg_32 register class
2015-01-07 Tom StellardR600/SI: Add a V_MOV_B64 pseudo instruction
2015-01-07 Tom StellardR600/SI: Teach SIFoldOperands to split 64-bit constants...
2015-01-07 Tom StellardR600/SI: Refactor SIFoldOperands to simplify immediate...
2015-01-06 Matt ArsenaultR600/SI: Add combine for isinfinite pattern
2015-01-06 Matt ArsenaultR600/SI: Pattern match isinf to v_cmp_class instructions
2015-01-06 Matt ArsenaultR600/SI: Add basic DAG combines for fp_class
2015-01-06 Matt ArsenaultR600/SI: Add class intrinsic
2015-01-06 Tom StellardR600/SI: Insert s_waitcnt before s_barrier instructions.
2015-01-06 Tom StellardR600/SI: Fix dependency calculation for DS writes instr...
2015-01-06 Tom StellardR600/SI: Add a stub GCNTargetMachine
2015-01-06 Tom StellardR600/SI: Remove MachineFunction dump from AsmPrinter
2015-01-06 Lang HamesRevert r225048: It broke ObjC on AArch64.
2015-01-03 Craig TopperMinor cleanup to all the switches after MatchInstructio...
2014-12-31 Rafael EspindolaAdd r224985 back with a fix.
2014-12-31 Rafael EspindolaRevert "Remove doesSectionRequireSymbols."
2014-12-30 Rafael EspindolaRemove doesSectionRequireSymbols.
2014-12-21 Matt ArsenaultEnable (sext x) == C --> x == (trunc C) combine
2014-12-19 Matt ArsenaultR600: Remove outdated comment
2014-12-19 Matt ArsenaultR600/SI: Only form min/max with 1 use.
2014-12-19 Tom StellardR600/SI: isLegalOperand() shouldn't check constant...
2014-12-19 Tom StellardR600/SI: Make sure non-inline constants aren't folded...
2014-12-17 Matt ArsenaultR600/SI: Fix f64 inline immediates
2014-12-12 Matt ArsenaultR600: Fix min/max matching problems with unordered...
2014-12-12 Matt ArsenaultR600/SI: fmin/fmax_legacy are not associative
2014-12-12 Matt ArsenaultR600/SI: Don't promote f32 select to i32
2014-12-12 Matt ArsenaultAdd target hook for whether it is profitable to reduce...
2014-12-11 Matt ArsenaultR600/SI: Handle physical registers in getOpRegClass
2014-12-11 Matt ArsenaultR600/SI: Don't verify constant bus usage of flag ops
2014-12-11 Matt ArsenaultR600/SI: Use unordered equal instructions
2014-12-11 Matt ArsenaultR600/SI: Make more unordered comparisons legal
2014-12-11 Matt ArsenaultR600/SI: Use unordered not equal instructions
2014-12-11 Matthias Braun[CodeGen] Add print and verify pass after each MachineF...
2014-12-11 Rafael EspindolaThis reverts commit r224043 and r224042.
2014-12-11 Matthias Braun[CodeGen] Add print and verify pass after each MachineF...
2014-12-10 Marek OlsakR600/SI: Use getTargetConstant in AdjustRegClass
2014-12-09 Tom StellardR600/SI: Set MayStore = 0 on MUBUF loads
2014-12-09 Tom StellardR600/SI: Move setting of the lds bit to the base MUBUF...
2014-12-08 Matt ArsenaultR600/SI: Move continue after checking s_mov_b32.
2014-12-07 Marek OlsakR600/SI: Disable VMEM and SMEM clauses by breaking...
2014-12-07 Marek OlsakR600/SI: Set 20-bit immediate byte offset for SMRD...
2014-12-07 Marek OlsakR600/SI: Update instruction conversions for VI
2014-12-07 Marek OlsakR600/SI: Add VI instructions
2014-12-07 Marek OlsakR600/SI: Add SCC Defs/Uses to SOP1 and SOP2 opcodes
2014-12-06 Tom StellardR600/SI: Restore PrivateGlobalPrefix to the default...
2014-12-04 Matt ArsenaultAllow target to specify prefix for labels
2014-12-03 Tom StellardR600/SI: Move SIInsertWaits into AMDGPUPassConfig:...
2014-12-03 Tom StellardR600/SI: Don't run SI passes on R600 subtargets
2014-12-03 Aaron BallmanSilencing a 32-bit implicit conversion warning in MSVC...
2014-12-03 Matt ArsenaultR600/SI: Fix SIFixSGPRCopies for copies to physical...
2014-12-03 Matt ArsenaultR600/SI: Remove incorrect assertion
2014-12-03 Matt ArsenaultR600/SI: Remove i1 pseudo VALU ops
2014-12-03 Matt ArsenaultR600/SI: Fix suspicious indexing
2014-12-03 Matt ArsenaultR600/SI: Fix running SILowerI1Copies a second time
2014-12-03 Matt ArsenaultR600/SI: Fix live range error hidden by SIFoldOperands
2014-12-03 Tom StellardR600/SI: Enable inline assembly
2014-12-03 Matt ArsenaultR600/SI: Change mubuf offsets to print as decimal
2014-12-02 Tom StellardR600/SI: Emit amd_kernel_code_t header for AMDGPU envir...
2014-12-02 Tom StellardR600/SI: Move more information into SIProgramInfo struct
2014-12-02 Tom StellardR600/SI: Refactor AMDGPUAsmPrinter::EmitProgramInfoSI()
2014-12-02 Tom StellardR600/SI: Set correct number of user sgprs for HSA runtime
2014-12-02 Tom StellardR600/SI: Set the ATC bit on all resource descriptors...
2014-12-01 Matt ArsenaultR600/SI: Various instruction format bit test cleanups
2014-11-28 Matt ArsenaultR600/SI: Fix assertion on sign extend of 3 vectors
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