opencl/llvm.git
7 years agoclarify comment
Adrian Prantl [Wed, 2 Apr 2014 15:49:45 +0000 (15:49 +0000)]
clarify comment

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205429 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agofix a comment to use ASCII aprostrophes.
Adrian Prantl [Wed, 2 Apr 2014 15:49:37 +0000 (15:49 +0000)]
fix a comment to use ASCII aprostrophes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205428 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoARM64: use GOT for weak symbols & PIC.
Tim Northover [Wed, 2 Apr 2014 14:39:11 +0000 (14:39 +0000)]
ARM64: use GOT for weak symbols & PIC.

Weak symbols cannot use the small code model's usual ADRP sequences since the
instruction simply may not be able to encode a value of 0.

This redirects them to use the GOT, which hopefully linkers are able to cope
with even in the static relocation model.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205426 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoARM64: fix lowering of fp128 fptosi/fptoui
Tim Northover [Wed, 2 Apr 2014 14:39:07 +0000 (14:39 +0000)]
ARM64: fix lowering of fp128 fptosi/fptoui

We were creating libcall nodes that returned an MVT::f128, when these
particular operations actually return an int of some stripe.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205425 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoSLPVectorizer: compare entire intrinsic for SLP compatibility.
Tim Northover [Wed, 2 Apr 2014 14:39:02 +0000 (14:39 +0000)]
SLPVectorizer: compare entire intrinsic for SLP compatibility.

Some Intrinsics are overloaded to the extent that return type equality (all
that's been checked up to now) does not guarantee that the arguments are the
same. In these cases SLP vectorizer should not recurse into the operands, which
can be achieved by comparing them as "Function *" rather than simply the ID.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205424 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoARM64: make sure first argument to INSERT_SUBVECTOR has right type.
Tim Northover [Wed, 2 Apr 2014 14:38:58 +0000 (14:38 +0000)]
ARM64: make sure first argument to INSERT_SUBVECTOR has right type.

Again, coalescing and other optimisations swiftly made the MachineInstrs
consistent again, but when compiled at -O0 a bad INSERT_SUBREGISTER was
produced.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205423 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoARM64: convert fp16 narrowing ISel to pseudo-instruction
Tim Northover [Wed, 2 Apr 2014 14:38:54 +0000 (14:38 +0000)]
ARM64: convert fp16 narrowing ISel to pseudo-instruction

The previous attempt was fine with optimisations, but was actually rather
cavalier with its types. When compiled at -O0, it produced invalid COPY
MachineInstrs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205422 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMark FPB as a reserved register when needed.
Job Noorman [Wed, 2 Apr 2014 13:13:56 +0000 (13:13 +0000)]
Mark FPB as a reserved register when needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205421 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoWork around gold bug http://sourceware.org/PR16794.
Rafael Espindola [Wed, 2 Apr 2014 12:15:20 +0000 (12:15 +0000)]
Work around gold bug sourceware.org/PR16794.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205416 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRemove duplicated DMB instructions
Renato Golin [Wed, 2 Apr 2014 09:03:43 +0000 (09:03 +0000)]
Remove duplicated DMB instructions

ARM specific optimiztion, finding places in ARM machine code where 2 dmbs
follow one another, and eliminating one of them.

Patch by Reinoud Elhorst.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205409 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdded isTargetWindowsMSVC(), renamed isTargetMingw() to isTargetWindowsGNU()
Yaron Keren [Wed, 2 Apr 2014 04:27:51 +0000 (04:27 +0000)]
Added isTargetWindowsMSVC(), renamed isTargetMingw() to isTargetWindowsGNU()
and isTargetCygwin() to isTargetWindowsCygwin() to be consistent with the
four Windows environments in Triple.h.

Suggestion by Saleem Abdulrasool!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205393 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[LoopVectorizer] Count dependencies of consecutive pointers as uniforms
Hal Finkel [Wed, 2 Apr 2014 02:34:49 +0000 (02:34 +0000)]
[LoopVectorizer] Count dependencies of consecutive pointers as uniforms

For the purpose of calculating the cost of the loop at various vectorization
factors, we need to count dependencies of consecutive pointers as uniforms
(which means that the VF = 1 cost is used for all overall VF values).

For example, the TSVC benchmark function s173 has:
  ...
  %3 = add nsw i64 %indvars.iv, 16000
  %arrayidx8 = getelementptr inbounds %struct.GlobalData* @global_data, i64 0, i32 0, i64 %3
  ...
and we must realize that the add will be a scalar in order to correctly deduce
it to be profitable to vectorize this on PowerPC with VSX enabled. In fact, all
dependencies of a consecutive pointer must be a scalar (uniform), and so we
simply need to add all consecutive pointers to the worklist that currently
detects collects uniforms.

Fixes PR19296.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205387 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdjust comments regarding non-relocated abbrev offset in debug_info.dwo
David Blaikie [Wed, 2 Apr 2014 02:04:51 +0000 (02:04 +0000)]
Adjust comments regarding non-relocated abbrev offset in debug_info.dwo

I'm not sure the comment in the implementation really adds a lot of
value (it's clear that we emit zero when no symbol is provided, but it
doesn't explain why we would do that). Happy to iterate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205386 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoSplit debug_loc and debug_loc.dwo emission into two separate functions
David Blaikie [Wed, 2 Apr 2014 01:50:20 +0000 (01:50 +0000)]
Split debug_loc and debug_loc.dwo emission into two separate functions

Based on code review feedback from Eric Christopher on r204697

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205385 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoDebugInfo: Introduce DebugLocList to encapsulate a list of DebugLocEntries and an...
David Blaikie [Wed, 2 Apr 2014 01:43:18 +0000 (01:43 +0000)]
DebugInfo: Introduce DebugLocList to encapsulate a list of DebugLocEntries and an MC Label to refer to them

This removes the magic-number-esque code creating/retrieving the same
label for a debug_loc entry from two places and removes the last small
piece of reusable logic from emitDebugLoc so that there will be less
duplication when refactoring it into two functions (one for debug_loc,
the other for debug_loc.dwo).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205382 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM64][CollectLOH] Add some comments to explain how the LOHs
Quentin Colombet [Wed, 2 Apr 2014 01:02:28 +0000 (01:02 +0000)]
[ARM64][CollectLOH] Add some comments to explain how the LOHs
framework works (for the compiler part), since the design
document is not available.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205379 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd a doxygen comment to DebugLocEntry::Merge.
Adrian Prantl [Tue, 1 Apr 2014 23:34:45 +0000 (23:34 +0000)]
Add a doxygen comment to DebugLocEntry::Merge.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205374 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoDebugLocEntry: Actually merge the loc entry when returning true.
David Blaikie [Tue, 1 Apr 2014 23:19:23 +0000 (23:19 +0000)]
DebugLocEntry: Actually merge the loc entry when returning true.

Seems we didn't have any test coverage for merging... awesome. So I
added some - but hit an llvm-objdump bug while I was there. I'm choosing
not to shave that yak right now.

Code review feedback/bug catch by Adrian Prantl in r205360.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205373 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix accidental fallthrough in DebugLocEntry::hasSameValueOrLocation
David Blaikie [Tue, 1 Apr 2014 22:25:09 +0000 (22:25 +0000)]
Fix accidental fallthrough in DebugLocEntry::hasSameValueOrLocation

No test case (this would invoke UB by examining uninitialized members,
etc, at best - and this code is apparently untested anyway - I'm about
to fix that)

Code review feedback from Adrian Prantl on r205360.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205367 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRemove unused function DebugLocEntry::isEmpty
David Blaikie [Tue, 1 Apr 2014 22:06:18 +0000 (22:06 +0000)]
Remove unused function DebugLocEntry::isEmpty

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205365 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRefactor out the comparison of the location/value in a DebugLocEntry
David Blaikie [Tue, 1 Apr 2014 22:04:07 +0000 (22:04 +0000)]
Refactor out the comparison of the location/value in a DebugLocEntry

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205364 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd inequality operator for MachineLocation.
David Blaikie [Tue, 1 Apr 2014 21:54:52 +0000 (21:54 +0000)]
Add inequality operator for MachineLocation.

Fixes the build I broke in r205360

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205361 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoDebugInfo: Split DebugLocEntry into its own file.
David Blaikie [Tue, 1 Apr 2014 21:49:04 +0000 (21:49 +0000)]
DebugInfo: Split DebugLocEntry into its own file.

It seems big enough that it deserves its own file - but it is header
only, so there's no need for another cpp file, etc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205360 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd a comment about the DIDescriptor class hierarchy.
Adrian Prantl [Tue, 1 Apr 2014 21:04:24 +0000 (21:04 +0000)]
Add a comment about the DIDescriptor class hierarchy.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205358 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoDwarfDebug: Prevent DebugLocEntry merging from coalescing two different
Adrian Prantl [Tue, 1 Apr 2014 21:04:18 +0000 (21:04 +0000)]
DwarfDebug: Prevent DebugLocEntry merging from coalescing two different
constants into only the first one.

rdar://14874886.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205357 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[PowerPC] Add some missing VSX bitcast patterns
Hal Finkel [Tue, 1 Apr 2014 19:24:27 +0000 (19:24 +0000)]
[PowerPC] Add some missing VSX bitcast patterns

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205352 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoIf isKnownWindowsMSVCEnvironment then getOS == Triple::Win32 and
Yaron Keren [Tue, 1 Apr 2014 18:52:55 +0000 (18:52 +0000)]
If isKnownWindowsMSVCEnvironment then getOS == Triple::Win32 and
Environment == Triple::MSVC so it will never be MinGW or Cygwin.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205349 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoImplement X86TTI::getUnrollingPreferences
Hal Finkel [Tue, 1 Apr 2014 18:50:34 +0000 (18:50 +0000)]
Implement X86TTI::getUnrollingPreferences

This provides an initial implementation of getUnrollingPreferences for x86.
getUnrollingPreferences is used by the generic (concatenation) unroller, which
is distinct from the unrolling done by the loop vectorizer. Many modern x86
cores have some kind of uop cache and loop-stream detector (LSD) used to
efficiently dispatch small loops, and taking full advantage of this requires
unrolling small loops (small here means 10s of uops).

These caches also have limits on the number of taken branches in the loop, and
so we also cap the loop unrolling factor based on the maximum "depth" of the
loop. This is currently calculated with a partial DFS traversal (partial
because it will stop early if the path length grows too much). This is still an
approximation, and one that is both conservative (because it does not account
for branches eliminated via block placement) and optimistic (because it is only
recording the maximum depth over minimum paths). Nevertheless, because the
loops that fit in these uop caches are so small, it is not clear how much the
details matter.

The original set of patches posted for review produced the following test-suite
performance results (from the TSVC benchmark) at that time:
  ControlLoops-dbl - 13% speedup
  ControlLoops-flt - 15% speedup
  Reductions-dbl - 7.5% speedup

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205348 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd some additional fields to TTI::UnrollingPreferences
Hal Finkel [Tue, 1 Apr 2014 18:50:30 +0000 (18:50 +0000)]
Add some additional fields to TTI::UnrollingPreferences

In preparation for an upcoming commit implementing unrolling preferences for
x86, this adds additional fields to the UnrollingPreferences structure:

 - PartialThreshold and PartialOptSizeThreshold - Like Threshold and
   OptSizeThreshold, but used when not fully unrolling. These are necessary
   because we need different thresholds for full unrolling from those used when
   partially unrolling (the full unrolling thresholds are generally going to be
   larger).

 - MaxCount - A cap on the unrolling factor when partially unrolling. This can
   be used by a target to prevent the unrolled loop from exceeding some
   resource limit independent of the loop size (such as number of branches).

There should be no functionality change for any in-tree targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205347 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoUse TopTTI->getGEPCost from within getUserCost
Hal Finkel [Tue, 1 Apr 2014 18:50:06 +0000 (18:50 +0000)]
Use TopTTI->getGEPCost from within getUserCost

The implementation of getUserCost had duplicated (and hard-coded) the default
logic in getGEPCost. Instead, it is better to use getGEPCost directly, which
limits the default logic to the implementation of one function, and allows
targets to override the behavior.

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205346 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[mips] Add Octeon cnMips instructions mtmX and mtpX
Kai Nacke [Tue, 1 Apr 2014 18:35:26 +0000 (18:35 +0000)]
[mips] Add Octeon cnMips instructions mtmX and mtpX

Adds the Octeon cnMips instructions "load multiplier register MPLx" and "load product register Px".
Includes tests.

Reviews by: Daniel.Sanders@imgtec.com

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205343 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoSupport segmented stacks on Win64
Reid Kleckner [Tue, 1 Apr 2014 18:34:21 +0000 (18:34 +0000)]
Support segmented stacks on Win64

Identical to Win32 method except the GS segment register is used for TLS
instead of FS and pvArbitrary is at TEB offset 0x28 instead of 0x14.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205342 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix missing RUN line in test
Matt Arsenault [Tue, 1 Apr 2014 18:34:13 +0000 (18:34 +0000)]
Fix missing RUN line in test

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205341 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoisTargetWindows() renamed to isTargetKnownWindowsMSVC()
Yaron Keren [Tue, 1 Apr 2014 18:15:34 +0000 (18:15 +0000)]
isTargetWindows() renamed to isTargetKnownWindowsMSVC()
to reflect its current functionality.

Based on Takumi NAKAMURA suggestion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205338 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMake isSetCCEquivalent respect the TargetBooleanContents
Matt Arsenault [Tue, 1 Apr 2014 18:13:26 +0000 (18:13 +0000)]
Make isSetCCEquivalent respect the TargetBooleanContents

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205336 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd helpers for checking if a value is a target boolean constant.
Matt Arsenault [Tue, 1 Apr 2014 18:13:22 +0000 (18:13 +0000)]
Add helpers for checking if a value is a target boolean constant.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205335 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoDebugInfo: Factor out common functionality for rendering debug_loc and debug_loc...
David Blaikie [Tue, 1 Apr 2014 16:17:41 +0000 (16:17 +0000)]
DebugInfo: Factor out common functionality for rendering debug_loc and debug_loc.dwo location list entries

In preparation for refactoring this function into two, one for
debug_loc, one for debug_loc.dwo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205324 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoCleanup remaining use of removed variable to fix the build
David Blaikie [Tue, 1 Apr 2014 16:13:29 +0000 (16:13 +0000)]
Cleanup remaining use of removed variable to fix the build

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205323 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoSimplify debug_loc.dwo handling slightly.
David Blaikie [Tue, 1 Apr 2014 16:09:49 +0000 (16:09 +0000)]
Simplify debug_loc.dwo handling slightly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205322 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoARM: rename ARMle/ARMbe with ARMLE/ARMBE, and Thumble/Thumbbe with ThumbLE/ThumbBE
Christian Pirker [Tue, 1 Apr 2014 15:19:30 +0000 (15:19 +0000)]
ARM: rename ARMle/ARMbe with ARMLE/ARMBE, and Thumble/Thumbbe with ThumbLE/ThumbBE

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205317 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoARM: teach LLVM that Cortex-A7 is very similar to A8.
Tim Northover [Tue, 1 Apr 2014 14:10:07 +0000 (14:10 +0000)]
ARM: teach LLVM that Cortex-A7 is very similar to A8.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205314 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAttempting to fix r205124, which had failed asserts when built with MSVC.
Aaron Ballman [Tue, 1 Apr 2014 13:56:35 +0000 (13:56 +0000)]
Attempting to fix r205124, which had failed asserts when built with MSVC.

Suggestion from Yaron Keren.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205313 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoARM: add cyclone CPU with ZeroCycleZeroing feature.
Tim Northover [Tue, 1 Apr 2014 13:22:02 +0000 (13:22 +0000)]
ARM: add cyclone CPU with ZeroCycleZeroing feature.

The Cyclone CPU is similar to swift for most LLVM purposes, but does have two
preferred instructions for zeroing a VFP register. This teaches LLVM about
them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205309 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[mips] Renamed ParseAnyRegisterWithoutDollar to MatchAnyRegisterWithoutDollar
Daniel Sanders [Tue, 1 Apr 2014 12:35:23 +0000 (12:35 +0000)]
[mips] Renamed ParseAnyRegisterWithoutDollar to MatchAnyRegisterWithoutDollar

This is for consistency with other functions. The Parse* functions consume
tokens and the Match* functions don't.

No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205305 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFixing an MSVC warning about widening the result of a 32-bit shift implicitly. No...
Aaron Ballman [Tue, 1 Apr 2014 12:24:25 +0000 (12:24 +0000)]
Fixing an MSVC warning about widening the result of a 32-bit shift implicitly. No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205304 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoARM64: add intrinsic for pmull (p64 x p64 = p128) operations.
Tim Northover [Tue, 1 Apr 2014 12:22:37 +0000 (12:22 +0000)]
ARM64: add intrinsic for pmull (p64 x p64 = p128) operations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205302 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFixing warnings in the MSVC build. No functional changes intended.
Aaron Ballman [Tue, 1 Apr 2014 12:22:20 +0000 (12:22 +0000)]
Fixing warnings in the MSVC build. No functional changes intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205301 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[mips] Extend ParseJumpTarget to support the full symbol expression syntax.
Daniel Sanders [Tue, 1 Apr 2014 10:41:48 +0000 (10:41 +0000)]
[mips] Extend ParseJumpTarget to support the full symbol expression syntax.

Summary:
This should fix the issues the D3222 caused in lld. Testcase is based on
the one that failed in the buildbot.

Depends on D3233

Reviewers: matheusalmeida, vmedic

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D3234

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205298 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[mips] Use AsmLexer::peekTok() to resolve the conflict between $reg and $sym
Daniel Sanders [Tue, 1 Apr 2014 10:40:14 +0000 (10:40 +0000)]
[mips] Use AsmLexer::peekTok() to resolve the conflict between $reg and $sym

Summary:
Parsing registers no longer consume the $ token before it's confirmed whether it really has a register or not, therefore it's no longer impossible to match symbols if registers were tried first.

Depends on D3232

Reviewers: matheusalmeida, vmedic

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D3233

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205297 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[mips] Hoist Parser.Lex() calls out of MatchAnyRegisterNameWithoutDollar()
Daniel Sanders [Tue, 1 Apr 2014 10:37:46 +0000 (10:37 +0000)]
[mips] Hoist Parser.Lex() calls out of MatchAnyRegisterNameWithoutDollar()

Summary:
No functional change

Depends on D3222

Reviewers: matheusalmeida, vmedic

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D3232

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205295 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoARM64: add patterns for more lane-wise ld1/st1 operations.
Tim Northover [Tue, 1 Apr 2014 10:37:09 +0000 (10:37 +0000)]
ARM64: add patterns for more lane-wise ld1/st1 operations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205294 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoARM64: fix bug in ld3r (1d) SelectionDAG.
Tim Northover [Tue, 1 Apr 2014 10:37:03 +0000 (10:37 +0000)]
ARM64: fix bug in ld3r (1d) SelectionDAG.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205293 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[mips] Rewrite MipsAsmParser and MipsOperand.
Daniel Sanders [Tue, 1 Apr 2014 10:35:28 +0000 (10:35 +0000)]
[mips] Rewrite MipsAsmParser and MipsOperand.

Summary:
Highlights:
- Registers are resolved much later (by the render method).
  Prior to that point, GPR32's/GPR64's are GPR's regardless of register
  size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register
  size or FR mode. Numeric registers can be anything.
- All registers are parsed the same way everywhere (even when handling
  symbol aliasing)
  - One consequence is that all registers can be specified numerically
    almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing
    but that can be easily resolved.
- Removes the need for the hasConsumedDollar hack
- Parenthesis and Bracket suffixes are handled generically
- Micromips instructions are parsed directly instead of going through the
  standard encodings first.
- rdhwr accepts all 32 registers, and the following instructions that previously
  xfailed now work:
    ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d,
    c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1
- Diagnostics involving registers point at the correct character (the $)
- There's only one kind of immediate in MipsOperand. LSA immediates are handled
  by the predicate and renderer.

Lowlights:
- Hardcoded '$zero' in the div patterns is handled with a hack.
  MipsOperand::isReg() will return true for a k_RegisterIndex token
  with Index == 0 and getReg() will return ZERO for this case. Note that it
  doesn't return ZERO_64 on isGP64() targets.
- I haven't cleaned up all of the now-unused functions.
  Some more of the generic parser could be removed too (integers and relocs
  for example).
- insve.df needed a custom decoder to handle the implicit fourth operand that
  was needed to make it parse correctly. The difficulty was that the matcher
  expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this.

Reviewers: matheusalmeida, vmedic

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D3222

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205292 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRecover TableGen/LangRef, make it official
Renato Golin [Tue, 1 Apr 2014 09:51:49 +0000 (09:51 +0000)]
Recover TableGen/LangRef, make it official

Making the new TableGen documentation official and marking the old file as
"Moved". Also, reverting the original LangRef as the normative formal
description of the language, while keeping the "new" LangRef as LangIntro
for the less inlcined to reading language grammars.

We should remove TableGenFundamentals.rst one day, but for now, just a
warning that it moved will have to do, while we make sure there are no more
links to it from elsewhere.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205289 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[x86] Do not convert to cmp32 for Atom arch by Sergey Okunev
Alexey Volkov [Tue, 1 Apr 2014 08:13:07 +0000 (08:13 +0000)]
[x86] Do not convert to cmp32 for Atom arch by Sergey Okunev

Differential Revision: http://llvm-reviews.chandlerc.com/D2824

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205288 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoDebugInfo: Avoid creating unnecessary/empty line tables and remove the special case...
David Blaikie [Tue, 1 Apr 2014 08:07:52 +0000 (08:07 +0000)]
DebugInfo: Avoid creating unnecessary/empty line tables and remove the special case of '0' in DwarfCompileUnit::initStmtList by just always using a label difference

This moves one case of raw text checking down into the MCStreamer
interfaces in the form of a virtual function, even if we ultimately end
up consolidating on the one-or-many line tables issue one day, this is
nicer in the interim. This just generally streamlines a bunch of use
cases into a common code path.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205287 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoDebugInfo: Emit relocation to debug_line section when emitting asm for asm
David Blaikie [Tue, 1 Apr 2014 07:35:52 +0000 (07:35 +0000)]
DebugInfo: Emit relocation to debug_line section when emitting asm for asm

I don't think this is reachable by any frontend (why would you transform
asm to asm+debug info?) but it helps tidy up some of this code, avoid
the weird special case of "emit the first CU, store the label, then emit
the rest" in MCDwarfLineTable::Emit by instead having the
DWARF-for-assembly case use the same codepath as DwarfDebug.cpp, by
registering the label of the debug_line section, thus causing it to be
emitted. (with a special case in asm output to just emit the label since
asm output uses the .loc directives, etc, rather than the debug_loc
directly)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205286 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRemove FIXMEs. The scope of a Variable is always a lexical scope; there is
Adrian Prantl [Tue, 1 Apr 2014 03:50:01 +0000 (03:50 +0000)]
Remove FIXMEs. The scope of a Variable is always a lexical scope; there is
nothing to be gained from switching this over to a DIScopeRef.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205281 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoLTO type uniquing: store the Decl field of a DIImportedEntity as a DIRef.
Adrian Prantl [Tue, 1 Apr 2014 03:41:04 +0000 (03:41 +0000)]
LTO type uniquing: store the Decl field of a DIImportedEntity as a DIRef.
No other functionality changes, DIBuilder testcase is included in a paired
CFE commit.

This relaxes the assertion in isScopeRef to also accept subclasses of
DIScope.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205279 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd a comment about type-uniquing ObjC types.
Adrian Prantl [Tue, 1 Apr 2014 03:40:59 +0000 (03:40 +0000)]
Add a comment about type-uniquing ObjC types.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205277 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoComment to describe the debug_loc.dwo constants
David Blaikie [Mon, 31 Mar 2014 23:50:20 +0000 (23:50 +0000)]
Comment to describe the debug_loc.dwo constants

Code review feedback from Eric Christopher on r204697

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205268 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMCJIT: ensure that cygwin is identified properly
Saleem Abdulrasool [Mon, 31 Mar 2014 23:42:23 +0000 (23:42 +0000)]
MCJIT: ensure that cygwin is identified properly

Cygwin is now a proper environment rather than an OS.  This updates the MCJIT
tests to avoid execution on Cygwin.  This fixes native cygwin tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205266 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMove partial/runtime unrolling late in the pipeline
Hal Finkel [Mon, 31 Mar 2014 23:23:51 +0000 (23:23 +0000)]
Move partial/runtime unrolling late in the pipeline

The generic (concatenation) loop unroller is currently placed early in the
standard optimization pipeline. This is a good place to perform full unrolling,
but not the right place to perform partial/runtime unrolling. However, most
targets don't enable partial/runtime unrolling, so this never mattered.

However, even some x86 cores benefit from partial/runtime unrolling of very
small loops, and follow-up commits will enable this. First, we need to move
partial/runtime unrolling late in the optimization pipeline (importantly, this
is after SLP and loop vectorization, as vectorization can drastically change
the size of a loop), while keeping the full unrolling where it is now. This
change does just that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205264 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agolit: Set a base directory for compiler-rt tests
Duncan P. N. Exon Smith [Mon, 31 Mar 2014 23:14:10 +0000 (23:14 +0000)]
lit: Set a base directory for compiler-rt tests

Setting this parameter enables llvm-lit to run on source directories for
compiler-rt test suites that implement magic in their lit.cfg.

<rdar://problem/16458307>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205262 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRevert "SLPVectorizer: Ignore users that are insertelements we can reschedule them"
Arnold Schwaighofer [Mon, 31 Mar 2014 23:05:56 +0000 (23:05 +0000)]
Revert "SLPVectorizer: Ignore users that are insertelements we can reschedule them"

This reverts commit r205018.

Conflicts:
lib/Transforms/Vectorize/SLPVectorizer.cpp
test/Transforms/SLPVectorizer/X86/insert-element-build-vector.ll

This is breaking libclc build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205260 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoShifting into the sign bit is UB as discussed on IRC. Explicitly use the
Joerg Sonnenberger [Mon, 31 Mar 2014 22:53:57 +0000 (22:53 +0000)]
Shifting into the sign bit is UB as discussed on IRC. Explicitly use the
BitWord type for the constants to avoid this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205257 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Stackmaps] Update the stackmap format to use 64-bit relocations for the function...
Juergen Ributzka [Mon, 31 Mar 2014 22:14:04 +0000 (22:14 +0000)]
[Stackmaps] Update the stackmap format to use 64-bit relocations for the function address and properly align all entries.

This commit updates the stackmap format to version 1 to indicate the
reorganizaion of several fields. This was done in order to align stackmap
entries to their natural alignment and to minimize padding.

Fixes <rdar://problem/16005902>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205254 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Adjust cost of FP_TO_UINT v4f64->v4i32 as well
Adam Nemet [Mon, 31 Mar 2014 21:54:48 +0000 (21:54 +0000)]
[X86] Adjust cost of FP_TO_UINT v4f64->v4i32 as well

Pretty obvious follow-on to r205159 to also handle conversion from double
besides float.

Fixes <rdar://problem/16373208>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205253 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoR600/SI: Remove leftover pattern splitting 64-bit ors.
Matt Arsenault [Mon, 31 Mar 2014 21:46:46 +0000 (21:46 +0000)]
R600/SI: Remove leftover pattern splitting 64-bit ors.

It's now matched to the scalar 64-bit or and split later if
necessary.'

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205252 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRegister allocator: set CSRFirstUseCost to 5 for ARM64.
Manman Ren [Mon, 31 Mar 2014 21:06:36 +0000 (21:06 +0000)]
Register allocator: set CSRFirstUseCost to 5 for ARM64.

A value of 5 means if we have a split or spill option that has a really
low cost (1 << 14 is the entry frequency), we will choose to spill
or split the really cold path before using a callee-saved register.

This gives us the performance benefit on SPECInt2k and is also conservative.

rdar://16162005

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205248 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoChange shouldSplitVectorElementType to better match the description.
Matt Arsenault [Mon, 31 Mar 2014 20:54:58 +0000 (20:54 +0000)]
Change shouldSplitVectorElementType to better match the description.

Pass the entire vector type, and not just the element.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205247 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix MSVC warning.
Rui Ueyama [Mon, 31 Mar 2014 20:04:37 +0000 (20:04 +0000)]
Fix MSVC warning.

This patch is to fix the following warning when compiled with MSVC 64 bit.

  warning C4334: '<<' : result of 32-bit shift implicitly converted to 64
  bits (was 64-bit shift intended?)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205245 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoR600/SI: Implement shouldConvertConstantLoadToIntImm
Matt Arsenault [Mon, 31 Mar 2014 19:54:27 +0000 (19:54 +0000)]
R600/SI: Implement shouldConvertConstantLoadToIntImm

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205244 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd an optional ability to expand larger BUILD_VECTORs with shuffles
Hal Finkel [Mon, 31 Mar 2014 19:42:55 +0000 (19:42 +0000)]
Add an optional ability to expand larger BUILD_VECTORs with shuffles

This adds the ability to expand large (meaning with more than two unique
defined values) BUILD_VECTOR nodes in terms of SCALAR_TO_VECTOR and (legal)
vector shuffles. There is now no limit of the size we are capable of expanding
this way, although we don't currently do this for vectors with many unique
values because of the default implementation of TLI's
shouldExpandBuildVectorWithShuffles function.

There is currently no functional change to any existing targets because the new
capabilities are not used unless some target overrides the TLI
shouldExpandBuildVectorWithShuffles function. As a result, I've not included a
test case for the new functionality in this commit, but regression tests will
(at least) be added soon when I commit support for the PPC QPX vector
instruction set.

The benefit of committing this now is that it makes the
shouldExpandBuildVectorWithShuffles callback, which had to be added for other
reasons regardless, fully functional. I suspect that other targets will
also benefit from tuning the heuristic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205243 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoR600: Compute masked bits for min and max
Matt Arsenault [Mon, 31 Mar 2014 19:35:33 +0000 (19:35 +0000)]
R600: Compute masked bits for min and max

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205242 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoDon't relocate with sections if there might be a paired relocation.
Rafael Espindola [Mon, 31 Mar 2014 19:00:23 +0000 (19:00 +0000)]
Don't relocate with sections if there might be a paired relocation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205240 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRevert: [mips] Rewrite MipsAsmParser and MipsOperand.' due to buildbot errors in...
Daniel Sanders [Mon, 31 Mar 2014 18:51:43 +0000 (18:51 +0000)]
Revert: [mips] Rewrite MipsAsmParser and MipsOperand.' due to buildbot errors in lld tests.

It's currently unable to parse 'sym + imm' without surrounding parenthesis.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205237 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoR600: Add BFE, BFI, and BFM intrinsics to help with writing tests.
Matt Arsenault [Mon, 31 Mar 2014 18:21:18 +0000 (18:21 +0000)]
R600: Add BFE, BFI, and BFM intrinsics to help with writing tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205236 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoR600: Add target nodes for BFM and BFI
Matt Arsenault [Mon, 31 Mar 2014 18:21:13 +0000 (18:21 +0000)]
R600: Add target nodes for BFM and BFI

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205235 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoARM: fix typo
Saleem Abdulrasool [Mon, 31 Mar 2014 18:09:10 +0000 (18:09 +0000)]
ARM: fix typo

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205233 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoNow that this test is assembly, make the checks a bit stronger.
Rafael Espindola [Mon, 31 Mar 2014 18:01:50 +0000 (18:01 +0000)]
Now that this test is assembly, make the checks a bit stronger.

This will be used for a followup patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205232 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[PowerPC] Don't ever expand BUILD_VECTOR of v2i64 with shuffles
Hal Finkel [Mon, 31 Mar 2014 17:48:16 +0000 (17:48 +0000)]
[PowerPC] Don't ever expand BUILD_VECTOR of v2i64 with shuffles

If we have two unique values for a v2i64 build vector, this will always result
in two vector loads if we expand using shuffles. Only one is necessary.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205231 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd a TLI hook to control when BUILD_VECTOR might be expanded using shuffles
Hal Finkel [Mon, 31 Mar 2014 17:48:10 +0000 (17:48 +0000)]
Add a TLI hook to control when BUILD_VECTOR might be expanded using shuffles

There are two general methods for expanding a BUILD_VECTOR node:
  1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle
     them together.
  2. Build the vector on the stack and then load it.

Currently, we use a fixed heuristic: If there are only one or two unique
defined values, then we attempt an expansion in terms of SCALAR_TO_VECTOR and
vector shuffles (provided that the required shuffle mask is legal). Otherwise,
always expand via the stack. Even when SCALAR_TO_VECTOR is not legal, this
can still be a good idea depending on what tricks the target can play when
lowering the resulting shuffle. If the target can't do anything special,
however, and if SCALAR_TO_VECTOR is expanded via the stack, this heuristic
leads to sub-optimal code (two stack loads instead of one).

Because only the target knows whether the SCALAR_TO_VECTORs and shuffles for a
build vector of a particular type are likely to be optimial, this adds a new
TLI function: shouldExpandBuildVectorWithShuffles which takes the vector type
and the count of unique defined values. If this function returns true, then
method (1) will be used, subject to the constraint that all of the necessary
shuffles are legal (as determined by isShuffleMaskLegal). If this function
returns false, then method (2) is always used.

This commit does not enhance the current code to support expanding a
build_vector with more than two unique values using shuffles, but I'll commit
an implementation of the more-general case shortly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205230 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[mips] Rewrite MipsAsmParser and MipsOperand.
Daniel Sanders [Mon, 31 Mar 2014 17:43:46 +0000 (17:43 +0000)]
[mips] Rewrite MipsAsmParser and MipsOperand.

Summary:
Highlights:
- Registers are resolved much later (by the render method).
  Prior to that point, GPR32's/GPR64's are GPR's regardless of register
  size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register
  size or FR mode. Numeric registers can be anything.
- All registers are parsed the same way everywhere (even when handling
  symbol aliasing)
  - One consequence is that all registers can be specified numerically
    almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing
    but that can be easily resolved.
- Removes the need for the hasConsumedDollar hack
- Parenthesis and Bracket suffixes are handled generically
- Micromips instructions are parsed directly instead of going through the
  standard encodings first.
- rdhwr accepts all 32 registers, and the following instructions that previously
  xfailed now work:
    ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d,
    c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1
- Diagnostics involving registers point at the correct character (the $)
- There's only one kind of immediate in MipsOperand. LSA immediates are handled
  by the predicate and renderer.

Lowlights:
- Hardcoded '$zero' in the div patterns is handled with a hack.
  MipsOperand::isReg() will return true for a k_RegisterIndex token
  with Index == 0 and getReg() will return ZERO for this case. Note that it
  doesn't return ZERO_64 on isGP64() targets.
- I haven't cleaned up all of the now-unused functions.
  Some more of the generic parser could be removed too (integers and relocs
  for example).
- insve.df needed a custom decoder to handle the implicit fourth operand that
  was needed to make it parse correctly. The difficulty was that the matcher
  expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this.

Reviewers: matheusalmeida, vmedic

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D3222

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205229 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoDisable each MachineFunctionPass for 'optnone' functions, unless that
Paul Robinson [Mon, 31 Mar 2014 17:43:35 +0000 (17:43 +0000)]
Disable each MachineFunctionPass for 'optnone' functions, unless that
pass normally runs at optimization level None, or is part of the
register allocation pipeline.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205228 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoTwo updated tests for MinGW 32 and 64 exception handling code generation.
Yaron Keren [Mon, 31 Mar 2014 17:34:15 +0000 (17:34 +0000)]
Two updated tests for MinGW 32 and 64 exception handling code generation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205227 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[PowerPC] Correct P7 dispatch unit allocation for vector instructions
Hal Finkel [Mon, 31 Mar 2014 17:02:10 +0000 (17:02 +0000)]
[PowerPC] Correct P7 dispatch unit allocation for vector instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205222 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoThis patch fixes LTO's RecordStreamer so that it records symbols in the MCExpr
Tom Roeder [Mon, 31 Mar 2014 16:59:13 +0000 (16:59 +0000)]
This patch fixes LTO's RecordStreamer so that it records symbols in the MCExpr
part of an asm .symver directive as being used. This prevents referenced
functions from being internalized and deleted.

Without the patch to LTOModule.cpp, the test case will produce the error:

LLVM ERROR: A @@ version cannot be undefined.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205221 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoSupport: generalise object type handling for Windows
Saleem Abdulrasool [Mon, 31 Mar 2014 16:34:41 +0000 (16:34 +0000)]
Support: generalise object type handling for Windows

This generalises the object file type parsing to all Windows environments.  This
is used by cygwin as well as MSVC environments for MCJIT.  This also makes the
triple more similar to Chandler's suggestion of a separate field for the object
file format.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205219 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoPR19099 - revert r203483
Eli Bendersky [Mon, 31 Mar 2014 16:11:57 +0000 (16:11 +0000)]
PR19099 - revert r203483

Now that r205212 was committed, r203483 is no longer necessary; it was a
temporary workaround that only handled a small number of the problematic cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205216 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoARM: change parameter names of the ELFARMAsmBackend constructor
Christian Pirker [Mon, 31 Mar 2014 16:06:39 +0000 (16:06 +0000)]
ARM: change parameter names of the ELFARMAsmBackend constructor

I removed the underscore at the beginning of the parameter name,
because of a comment from Tim.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205215 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoTest commit.
Robert Khasanov [Mon, 31 Mar 2014 16:01:38 +0000 (16:01 +0000)]
Test commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205214 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[mips] Fix use of uninitialized value reported by the sanitizer-x86_64-linux-bootstra...
Daniel Sanders [Mon, 31 Mar 2014 15:58:58 +0000 (15:58 +0000)]
[mips] Fix use of uninitialized value reported by the sanitizer-x86_64-linux-bootstrap buildbot

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205213 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix for PR19099 - NVPTX produces invalid symbol names.
Eli Bendersky [Mon, 31 Mar 2014 15:56:26 +0000 (15:56 +0000)]
Fix for PR19099 - NVPTX produces invalid symbol names.

This is a more thorough fix for the issue than r203483. An IR pass will run
before NVPTX codegen to make sure there are no invalid symbol names that can't
be consumed by the ptxas assembler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205212 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoARM64: add extra patterns for scalar shifts
Tim Northover [Mon, 31 Mar 2014 15:46:46 +0000 (15:46 +0000)]
ARM64: add extra patterns for scalar shifts

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205209 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoARM64: add extra scalar neg pattern & tests.
Tim Northover [Mon, 31 Mar 2014 15:46:42 +0000 (15:46 +0000)]
ARM64: add extra scalar neg pattern & tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205208 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoARM64: add patterns for scalar sqdmlal & sqdmlsl.
Tim Northover [Mon, 31 Mar 2014 15:46:38 +0000 (15:46 +0000)]
ARM64: add patterns for scalar sqdmlal & sqdmlsl.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205207 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoARM64: add more patterns for commuted fmsub operations.
Tim Northover [Mon, 31 Mar 2014 15:46:34 +0000 (15:46 +0000)]
ARM64: add more patterns for commuted fmsub operations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205206 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoARM64: shuffle patterns around for fmin/fmax & add tests.
Tim Northover [Mon, 31 Mar 2014 15:46:30 +0000 (15:46 +0000)]
ARM64: shuffle patterns around for fmin/fmax & add tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205205 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoARM64: add more scalar patterns for usqadd & suqadd.
Tim Northover [Mon, 31 Mar 2014 15:46:26 +0000 (15:46 +0000)]
ARM64: add more scalar patterns for usqadd & suqadd.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205204 91177308-0d34-0410-b5e6-96231b3b80d8