opencl/llvm.git
7 years agoImprove performance of calculateDbgValueHistory.
Adrian Prantl [Wed, 6 Aug 2014 18:41:24 +0000 (18:41 +0000)]
Improve performance of calculateDbgValueHistory.

In r210492 the logic of calculateDbgValueHistory was changed to end
register variable live ranges at the end of MBB conditionally on
the fact that the register was or not clobbered by the function body.

This requires an initial scan of all the operands of the function
to collect all clobbered registers. In a second pass over all
instructions, we compare this set with the set of clobbered
registers for the current MachineInstruction. This modification
incurred a compilation time regression on some benchmarks: the
debug info emission phase takes ~10% more time.

While a small performance hit is unavoidable due to the initial
scan requirement, we can improve the situation by avoiding to
create too many temporary sets and just use lambdas to work directly
on the result of the initial scan.

Fixes <rdar://problem/17884104>

Patch by Frederic Riss!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214987 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoCleanup collectChangingRegs
Adrian Prantl [Wed, 6 Aug 2014 18:41:19 +0000 (18:41 +0000)]
Cleanup collectChangingRegs

The handling of the epilogue is best expressed as an early exit and
there is no reason to look for register defs in DbgValue MIs.

Patch by Frederic Riss!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214986 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoDebugInfo: Fix ranges+gmlt test case to actually exercise the gmlt situation.
David Blaikie [Wed, 6 Aug 2014 18:24:19 +0000 (18:24 +0000)]
DebugInfo: Fix ranges+gmlt test case to actually exercise the gmlt situation.

Originally this test case tested the specified behavior (that -gmlt
would not produce DW_AT_ranges and that when no CU DW_AT_ranges were
produced, no debug_ranges section (not even an empty list) would be
produced) but then the ranges emission code was improved not to create
ranges of a single element (instead favoring high_pc/low_pc) and so this
test case no longer exercised the -gmlt portion of the behavior.

This caused me some confusion when reading the comments and trying to
update this test case for future changes to -gmlt. I've made this test
resilient to those changes (by using the {{DW_TAG|NULL}} pattern to
block the end of the attribute search at the end of the CU's attribute
list without mandating that it must (or must not) be followed by another
tag (the future changes to -gmlt should produce no subprograms in this
CU))

Fix the test case to have two functions in distinct sections to force
the use of DW_AT_ranges.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214985 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd a triple to this test to get the right IR mangling
Reid Kleckner [Wed, 6 Aug 2014 18:09:15 +0000 (18:09 +0000)]
Add a triple to this test to get the right IR mangling

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214982 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoDon't count inreg params when mangling fastcall functions
Reid Kleckner [Wed, 6 Aug 2014 18:09:04 +0000 (18:09 +0000)]
Don't count inreg params when mangling fastcall functions

This is consistent with MSVC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214981 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRound up the size of byval arguments to MinAlign
Reid Kleckner [Wed, 6 Aug 2014 17:57:23 +0000 (17:57 +0000)]
Round up the size of byval arguments to MinAlign

Otherwise we can end up with an argument frame size that is not a
multiple of stack slot size, which is very awkward.

This fixes PR20547, which was a bug in x86_64 Sys V vararg handling.
However, it's much easier to test this with x86 callee-cleanup
functions, which previously ended in "retl $6" instead of "retl $8".

This does affect behavior of all backends, but it presumably fixes the
same bug in all of them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214980 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoUseListOrder: Use std::vector
Duncan P. N. Exon Smith [Wed, 6 Aug 2014 17:36:08 +0000 (17:36 +0000)]
UseListOrder: Use std::vector

I initially used a `SmallVector<>` for `UseListOrder::Shuffle`, which
was a silly choice.  When I realized my error I quickly rolled a custom
data structure.

This commit simplifies it to a `std::vector<>`.  Now that I've had a
chance to measure performance, this data structure isn't part of a
bottleneck, so the additional complexity is unnecessary.

This is part of PR5680.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214979 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AArch64] Add a few isTarget* API to AArch64 Subtarget.
Chad Rosier [Wed, 6 Aug 2014 16:56:58 +0000 (16:56 +0000)]
[AArch64] Add a few isTarget* API to AArch64 Subtarget.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214977 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd test case omitted in r214974.
Chad Rosier [Wed, 6 Aug 2014 16:06:41 +0000 (16:06 +0000)]
Add test case omitted in r214974.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214975 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AArch64] Fix OS ABI flag for aarch64-linux-gnu target.
Chad Rosier [Wed, 6 Aug 2014 16:05:02 +0000 (16:05 +0000)]
[AArch64] Fix OS ABI flag for aarch64-linux-gnu target.

For triple aarch64-linux-gnu we were incorrectly setting IRIX.
For triple aarch64 we are correctly setting SYSV.

Patch by Ana Pazos <apazos@codeaurora.org>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214974 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agouse register iterators that include self to reduce code duplication in CriticalAntiDe...
Sanjay Patel [Wed, 6 Aug 2014 15:58:15 +0000 (15:58 +0000)]
use register iterators that include self to reduce code duplication in CriticalAntiDepBreaker

This patch addresses 2 FIXME comments that I added to CriticalAntiDepBreaker while fixing PR20020.

Initialize an MCSubRegIterator and an MCRegAliasIterator to include the self reg.

Assuming that works as advertised, there should be functional difference with this patch, just less code.

Also, remove the associated asserts - we're setting those values just before, so the asserts don't do anything meaningful.

Differential Revision: http://reviews.llvm.org/D4566

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214973 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AVX512] Added load/store instructions to Register2Memory opcode tables.
Robert Khasanov [Wed, 6 Aug 2014 15:40:34 +0000 (15:40 +0000)]
[AVX512] Added load/store instructions to Register2Memory opcode tables.
Added lowering tests for load/store.

Reviewed by Elena Demikhovsky <elena.demikhovsky@intel.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214972 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AArch64] Add a testcase for r214957.
James Molloy [Wed, 6 Aug 2014 13:31:32 +0000 (13:31 +0000)]
[AArch64] Add a testcase for r214957.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214965 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd a new option -run-slp-after-loop-vectorization.
James Molloy [Wed, 6 Aug 2014 12:56:19 +0000 (12:56 +0000)]
Add a new option -run-slp-after-loop-vectorization.

This swaps the order of the loop vectorizer and the SLP/BB vectorizers. It is disabled by default so we can do performance testing - ideally we want to change to having the loop vectorizer running first, and the SLP vectorizer using its leftovers instead of the other way around.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214963 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoARM: do not generate BLX instructions on Cortex-M CPUs.
Tim Northover [Wed, 6 Aug 2014 11:13:14 +0000 (11:13 +0000)]
ARM: do not generate BLX instructions on Cortex-M CPUs.

Particularly on MachO, we were generating "blx _dest" instructions on M-class
CPUs, which don't actually exist. They happen to get fixed up by the linker
into valid "bl _dest" instructions (which is why such a massive issue has
remained largely undetected), but we shouldn't rely on that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214959 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoARM-MachO: materialize callee address correctly on v4t.
Tim Northover [Wed, 6 Aug 2014 11:13:06 +0000 (11:13 +0000)]
ARM-MachO: materialize callee address correctly on v4t.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214958 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AArch64] Conditional selects are expensive on out-of-order cores.
James Molloy [Wed, 6 Aug 2014 10:42:18 +0000 (10:42 +0000)]
[AArch64] Conditional selects are expensive on out-of-order cores.

Specifically Cortex-A57. This probably applies to Cyclone too but I haven't enabled it for that as I can't test it.

This gives ~4% improvement on SPEC 174.vpr, and ~1% in 471.omnetpp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214957 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[x86] Fix two independent miscompiles in the process of getting the same
Chandler Carruth [Wed, 6 Aug 2014 10:16:36 +0000 (10:16 +0000)]
[x86] Fix two independent miscompiles in the process of getting the same
test case to actually generate correct code.

The primary miscompile fixed here is that we weren't correctly handling
in-place elements in one half of a single-input v8i16 shuffle when
moving a dword of elements from that half to the other half. Some times,
we would clobber the in-place elements in forming the dword to move
across halves.

The fix to this involves forcibly marking the in-place inputs even when
there is no need to gather them into a dword, and to much more carefully
re-arrange the elements when grouping them into a dword to move across
halves. With these two changes we would generate correct shuffles for
the test case, but found another miscompile. There are also some random
perturbations of the generated shuffle pattern in SSE2. It looks like
a wash; more instructions in some cases fewer in others.

The second miscompile would corrupt the results into nonsense. This is
a buggy pattern in one of the added DAG combines. Mapping elements
through a PSHUFD when pairing redundant half-shuffles is *much* harder
than this code makes it out to be -- it requires reasoning about *all*
of where the input is used in the PSHUFD, not just one part of where it
is used. Plus, we can't combine a half shuffle *into* a PSHUFD but the
code didn't guard against it. I think this was just a bad idea and I've
just removed that aspect of the combine. No tests regress as
a consequence so seems OK.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214954 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[x86] Switch to a formulation of a for loop that is much more obviously
Chandler Carruth [Wed, 6 Aug 2014 10:16:33 +0000 (10:16 +0000)]
[x86] Switch to a formulation of a for loop that is much more obviously
not corrupting the mask by mutating it more times than intended. No
functionality changed (the results were non-overlapping so the old
version "worked" but was non-obvious).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214953 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Fixes commit r214890 to match the posted patch
Adam Nemet [Wed, 6 Aug 2014 07:13:12 +0000 (07:13 +0000)]
[X86] Fixes commit r214890 to match the posted patch

This was another fallout from my local rebase where something went wrong :(

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214951 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoCorrect comment
Matt Arsenault [Wed, 6 Aug 2014 00:44:25 +0000 (00:44 +0000)]
Correct comment

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214945 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[dfsan] Try not to create too many additional basic blocks in functions which
Peter Collingbourne [Wed, 6 Aug 2014 00:33:40 +0000 (00:33 +0000)]
[dfsan] Try not to create too many additional basic blocks in functions which
already have a large number of blocks. Works around a performance issue with
the greedy register allocator.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214944 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoR600: Increase nearby load scheduling threshold.
Matt Arsenault [Wed, 6 Aug 2014 00:29:49 +0000 (00:29 +0000)]
R600: Increase nearby load scheduling threshold.

This partially fixes weird looking load scheduling
in memcpy test. The load clustering doesn't seem
particularly smart, but this method seems to be partially
deprecated so it might not be worth trying to fix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214943 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoR600/SI: Implement areLoadsFromSameBasePtr
Matt Arsenault [Wed, 6 Aug 2014 00:29:43 +0000 (00:29 +0000)]
R600/SI: Implement areLoadsFromSameBasePtr

This currently has a noticable effect on the kernel argument loads.
LDS and global loads are more problematic, I think because of how copies
are currently inserted to ensure that the address is a VGPR.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214942 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86][SchedModel] Fixed some wrong scheduling model found by code inspection.
Quentin Colombet [Wed, 6 Aug 2014 00:22:39 +0000 (00:22 +0000)]
[X86][SchedModel] Fixed some wrong scheduling model found by code inspection.
Source: Agner Fog's Instruction tables.

Related to <rdar://problem/15607571>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214940 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoDebugInfo: Assert that any CU for which debug_loc lists are emitted, has at least...
David Blaikie [Wed, 6 Aug 2014 00:21:25 +0000 (00:21 +0000)]
DebugInfo: Assert that any CU for which debug_loc lists are emitted, has at least one range.

This was coming in weird debug info that had variables (and hence
debug_locs) but was in GMLT mode (because it was missing the 13th field
of the compile_unit metadata) so no ranges were constructed. We should
always have at least one range for any CU with a debug_loc in it -
because the range should cover the debug_loc.

The assertion just ensures that the "!= 1" range case inside the
subsequent loop doesn't get entered for the case where there are no
ranges at all, which should never reach here in the first place.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214939 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoDebugInfo: Fix a bunch of tests that, owing to their compile_unit metadata not includ...
David Blaikie [Tue, 5 Aug 2014 23:57:31 +0000 (23:57 +0000)]
DebugInfo: Fix a bunch of tests that, owing to their compile_unit metadata not including a 13th field, had some subtle behavior.

Without the 13th field, the "emission kind" field defaults to 0 (which
is not equal to either of the values of the emission kind enum (1 ==
full debug info, 2 == line tables only)).

In this particular instance, the comparison with "FullDebugInfo" was
done when adding elements to the ranges list - so for these test cases
no values were added to the ranges list.

This got weirder when emitting debug_loc entries as the addresses should
be relative to the range of the CU if the CU has only one range (the
reasonable assumption is that if we're emitting debug_loc lists for a CU
that CU has at least one range - but due to the above situation, it has
zero) so the ranges were emitted relative to the start of the section
rather than relative to the start of the CU's singular range.

Fix these tests by accounting for the difference in the description of
debug_loc entries (in some cases making the test ignorant to these
differences, in others adding the extra label difference expression,
etc) or the presence/absence of high/low_pc on the CU, and add the 13th
field to their CUs to enable proper "full debug info" emission here.

In a future commit I'll fix up a bunch of other test cases that are not
so rigorously depending on this behavior, but still doing similarly
weird things due to the missing 13th field.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214937 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoR600/SI: Add definitions for ds_read2st64_ / ds_write2st64_
Matt Arsenault [Tue, 5 Aug 2014 23:53:20 +0000 (23:53 +0000)]
R600/SI: Add definitions for ds_read2st64_ / ds_write2st64_

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214936 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix typos in comments and doc
JF Bastien [Tue, 5 Aug 2014 23:27:34 +0000 (23:27 +0000)]
Fix typos in comments and doc

Committing http://reviews.llvm.org/D4798 for Robin Morisset (morisset@google.com)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214934 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoDebugInfo: Move the reference to the CU from the location list entry to the list...
David Blaikie [Tue, 5 Aug 2014 23:14:16 +0000 (23:14 +0000)]
DebugInfo: Move the reference to the CU from the location list entry to the list itself, since it is constant across an entire list.

This simplifies construction and usage while making the data structure
smaller. It was a holdover from the days when we didn't have a separate
DebugLocList and all we had was a flat list of DebugLocEntries.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214933 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRemove a virtual function from TargetMachine. NFC.
Rafael Espindola [Tue, 5 Aug 2014 22:10:21 +0000 (22:10 +0000)]
Remove a virtual function from TargetMachine. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214929 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRe-apply r214881: Fix return sequence on armv4 thumb
Jonathan Roelofs [Tue, 5 Aug 2014 21:32:21 +0000 (21:32 +0000)]
Re-apply r214881: Fix return sequence on armv4 thumb

This reverts r214893, re-applying r214881 with the test case relaxed a bit to
satiate the build bots.

POP on armv4t cannot be used to change thumb state (unilke later non-m-class
architectures), therefore we need a different return sequence that uses 'bx'
instead:

  POP {r3}
  ADD sp, #offset
  BX r3

This patch also fixes an issue where the return value in r3 would get clobbered
for functions that return 128 bits of data. In that case, we generate this
sequence instead:

  MOV ip, r3
  POP {r3}
  ADD sp, #offset
  MOV lr, r3
  MOV r3, ip
  BX lr

http://reviews.llvm.org/D4748

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214928 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[MCJIT] Make llvm-rtdyld check RuntimeDyld's error state when running in -verify
Lang Hames [Tue, 5 Aug 2014 20:51:46 +0000 (20:51 +0000)]
[MCJIT] Make llvm-rtdyld check RuntimeDyld's error state when running in -verify
mode.

This will cause -verify mode to report failure when RuntimeDyld encounters an
internal error (e.g. overflows in relocation computations). Previously we had
let these errors slip past unreported.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214925 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[PowerPC] Swap arguments and adjust shift count for vsldoi on little endian
Bill Schmidt [Tue, 5 Aug 2014 20:47:25 +0000 (20:47 +0000)]
[PowerPC] Swap arguments and adjust shift count for vsldoi on little endian

Commits r213915 and r214718 fix recognition of shuffle masks for vmrg*
and vpku*um instructions for a little-endian target, by swapping the
input arguments.  The vsldoi instruction requires similar treatment,
and also needs its shift count adjusted for little endian.

Reviewed by Ulrich Weigand.

This is a bug fix candidate for release 3.5 (and hopefully the last of
those for PowerPC).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214923 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoImproved test cases that were added with r214892.
Sanjay Patel [Tue, 5 Aug 2014 20:16:35 +0000 (20:16 +0000)]
Improved test cases that were added with r214892.

1. Added ':' to CHECK-LABELs
2. Added more CHECKs
3. Added CHECK-NEXTs
4. Added verbose hex immediate comments to CHECKs

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214921 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoDon't internalize all but main by default.
Rafael Espindola [Tue, 5 Aug 2014 20:10:38 +0000 (20:10 +0000)]
Don't internalize all but main by default.

This is mostly a cleanup, but it changes a fairly old behavior.

Every "real" LTO user was already disabling the silly internalize pass
and creating the internalize pass itself. The difference with this
patch is for "opt -std-link-opts" and the C api.

Now to get a usable behavior out of opt one doesn't need the funny
looking command line:

opt -internalize -disable-internalize -internalize-public-api-list=foo,bar -std-link-opts

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214919 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd a test showing the interaction of linker scripts and plugin.
Rafael Espindola [Tue, 5 Aug 2014 19:56:53 +0000 (19:56 +0000)]
Add a test showing the interaction of linker scripts and plugin.

In particular, the linker script is processed early enough for function g
to be internalized.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214916 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[x86] Fix a crasher due to shuffles which cancel each other out and add
Chandler Carruth [Tue, 5 Aug 2014 18:45:49 +0000 (18:45 +0000)]
[x86] Fix a crasher due to shuffles which cancel each other out and add
a test case.

We also miscompile this test case which is showing a serious flaw in the
single-input v8i16 shuffle code. I've left the specific instruction
checks FIXME-ed out until I can address the bug in the single-input
code, but I wanted to separate out a significant functionality change to
produce correct code from a very simple and targeted crasher fix.

The miscompile problem stems from keeping track of inputs by value
rather than by index. As a consequence of doing this, we can't reliably
update those inputs because they might swap and we can't detect this
without copying the mask.

The blend code now uses indices for the input lists and this seems
strictly better. It also should make it easier to sort things and do
other cleanups. I think the time has come to simplify The Great Lambda
here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214914 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRemove dead code in condition
Duncan P. N. Exon Smith [Tue, 5 Aug 2014 18:22:58 +0000 (18:22 +0000)]
Remove dead code in condition

Whether or not it's appropriate, labels have been first-class types
since r51511.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214908 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoX86CodeEmitter.cpp: Add SEH_Epilogue to ignored list for legacy JIT, corresponding...
NAKAMURA Takumi [Tue, 5 Aug 2014 18:04:15 +0000 (18:04 +0000)]
X86CodeEmitter.cpp: Add SEH_Epilogue to ignored list for legacy JIT, corresponding to r214775.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214905 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Improve comments for r214888
Adam Nemet [Tue, 5 Aug 2014 17:58:49 +0000 (17:58 +0000)]
[X86] Improve comments for r214888

A rebase somehow ate my comments. This restores them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214903 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoR600/SI: Use register class instead of list of registers
Matt Arsenault [Tue, 5 Aug 2014 17:52:40 +0000 (17:52 +0000)]
R600/SI: Use register class instead of list of registers

I'm not sure if this has any consequence or not.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214902 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoR600/SI: Add exec_lo and exec_hi subregisters.
Matt Arsenault [Tue, 5 Aug 2014 17:52:37 +0000 (17:52 +0000)]
R600/SI: Add exec_lo and exec_hi subregisters.

This allows accessing an SReg subregister with a normal subregister
index, instead of getting a machine verifier error.

Also be sure to include all of these subregisters in SReg_32.
This fixes inferring SGPR instead of SReg when finding a
super register class.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214901 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoBitcodeReader: Fix non-determinism in use-list order
Duncan P. N. Exon Smith [Tue, 5 Aug 2014 17:49:48 +0000 (17:49 +0000)]
BitcodeReader: Fix non-determinism in use-list order

`BasicBlockFwdRefs` (and `BlockAddrFwdRefs` before it) was being emptied
in a non-deterministic order.  When predicting use-list order I've
worked around this another way, but even when parsing lazily (and we
can't recreate use-list order) use-lists should be deterministic.

Make them so by using a side-queue of functions with forward-referenced
blocks that gets visited in order.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214899 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRemove dead zero store to calloc initialized memory
Philip Reames [Tue, 5 Aug 2014 17:48:20 +0000 (17:48 +0000)]
Remove dead zero store to calloc initialized memory

Optimize the following IR:

%1 = tail call noalias i8* @calloc(i64 1, i64 4)
%2 = bitcast i8* %1 to i32*
; This store is dead and should be removed
store i32 0, i32* %2, align 4

Memory returned by calloc is guaranteed to be zero initialized. If the value being stored is the constant zero (and the store is not otherwise observable across threads), we can delete the store.  If the store is to an out of bounds address, it is undefined and thus also removable.

Reviewed By: nicholas

Differential Revision: http://reviews.llvm.org/D3942

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214897 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRevert r214881 because it broke lots of build-bots
Jonathan Roelofs [Tue, 5 Aug 2014 17:36:05 +0000 (17:36 +0000)]
Revert r214881 because it broke lots of build-bots

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214893 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoOptimize vector fabs of bitcasted constant integer values.
Sanjay Patel [Tue, 5 Aug 2014 17:35:22 +0000 (17:35 +0000)]
Optimize vector fabs of bitcasted constant integer values.

Allow vector fabs operations on bitcasted constant integer values to be optimized
in the same way that we already optimize scalar fabs.

So for code like this:
%bitcast = bitcast i64 18446744069414584320 to <2 x float> ; 0xFFFF_FFFF_0000_0000
%fabs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %bitcast)
%ret = bitcast <2 x float> %fabs to i64

Instead of generating something like this:

movabsq (constant pool loadi of mask for sign bits)
vmovq   (move from integer register to vector/fp register)
vandps  (mask off sign bits)
vmovq   (move vector/fp register back to integer return register)

We should generate:

mov     (put constant value in return register)

I have also removed a redundant clause in the first 'if' statement:
N0.getOperand(0).getValueType().isInteger()

is the same thing as:
IntVT.isInteger()

Testcases for x86 and ARM added to existing files that deal with vector fabs.
One existing testcase for x86 removed because it is no longer ideal.

For more background, please see:
http://reviews.llvm.org/D4770

And:
http://llvm.org/bugs/show_bug.cgi?id=20354

Differential Revision: http://reviews.llvm.org/D4785

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214892 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AVX512] Add masking variant and intrinsics for valignd/q
Adam Nemet [Tue, 5 Aug 2014 17:23:04 +0000 (17:23 +0000)]
[AVX512] Add masking variant and intrinsics for valignd/q

This is similar to what I did with the two-source permutation recently.  (It's
almost too similar so that we should consider generating the masking variants
with some tablegen help.)

Both encoding and intrinsic tests are added as well.  For the latter, this is
what the IR that the intrinsic test on the clang side generates.

Part of <rdar://problem/17688758>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214890 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Increase X86_MAX_OPERANDS from 5 to 6
Adam Nemet [Tue, 5 Aug 2014 17:23:01 +0000 (17:23 +0000)]
[X86] Increase X86_MAX_OPERANDS from 5 to 6

This controls the number of operands in the disassembler's x86OperandSets
table.  The entries describe how the operand is encoded and its type.

Not to surprisingly 5 operands is insufficient for AVX512.  Consider
VALIGNDrrik in the next patch.  These are its operand specifiers:

  { /* 328 */
    { ENCODING_DUP, TYPE_DUP1 },
    { ENCODING_REG, TYPE_XMM512 },
    { ENCODING_WRITEMASK, TYPE_VK8 },
    { ENCODING_VVVV, TYPE_XMM512 },
    { ENCODING_RM_CD64, TYPE_XMM512 },
    { ENCODING_IB, TYPE_IMM8 },
  },

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214889 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Add lowering to VALIGN
Adam Nemet [Tue, 5 Aug 2014 17:22:59 +0000 (17:22 +0000)]
[X86] Add lowering to VALIGN

This was currently part of lowering to PALIGNR with some special-casing to
make interlane shifting work.  Since AVX512F has interlane alignr (valignd/q)
and AVX512BW has vpalignr we need to support both of these *at the same time*,
e.g. for SKX.

This patch breaks out the common code and then add support to check both of
these lowering options from LowerVECTOR_SHUFFLE.

I also added some FIXMEs where I think the AVX512BW and AVX512VL additions
should probably go.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214888 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Separate DAG node for valign and palignr
Adam Nemet [Tue, 5 Aug 2014 17:22:55 +0000 (17:22 +0000)]
[X86] Separate DAG node for valign and palignr

They have different semantics (valign is interlane while palingr is intralane)
and palingr is still needed even in the AVX512 context.  According to the
latest spec AVX512BW provides these.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214887 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AVX512] alignr: Use suffix rather than name argument to multiclass
Adam Nemet [Tue, 5 Aug 2014 17:22:52 +0000 (17:22 +0000)]
[AVX512] alignr: Use suffix rather than name argument to multiclass

Again no functional change.  This prepares for the suffix to be used with the
intrinsic matching.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214886 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AVX512] Pull everything alignr-related into the multiclass
Adam Nemet [Tue, 5 Aug 2014 17:22:50 +0000 (17:22 +0000)]
[AVX512] Pull everything alignr-related into the multiclass

The packed integer pattern becomes the DAG pattern for rri and the packed
float, another Pat<> inside the multiclass.

No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214885 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoWrap long lines
Adam Nemet [Tue, 5 Aug 2014 17:22:47 +0000 (17:22 +0000)]
Wrap long lines

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214884 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix return sequence on armv4 thumb
Jonathan Roelofs [Tue, 5 Aug 2014 17:13:17 +0000 (17:13 +0000)]
Fix return sequence on armv4 thumb

POP on armv4t cannot be used to change thumb state (unilke later non-m-class
architectures), therefore we need a different return sequence that uses 'bx'
instead:

  POP {r3}
  ADD sp, #offset
  BX r3

This patch also fixes an issue where the return value in r3 would get clobbered
for functions that return 128 bits of data. In that case, we generate this
sequence instead:

  MOV ip, r3
  POP {r3}
  ADD sp, #offset
  MOV lr, r3
  MOV r3, ip
  BX lr

http://reviews.llvm.org/D4748

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214881 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoPartially revert r214761 that asserted that all concrete debug info variables had...
David Blaikie [Tue, 5 Aug 2014 16:47:23 +0000 (16:47 +0000)]
Partially revert r214761 that asserted that all concrete debug info variables had DIEs, due to a failure on Darwin.

I'll work on a reduction and fix after this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214880 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoImprove test for merged global debug info by using llvm-dwarfdump.
David Blaikie [Tue, 5 Aug 2014 16:20:25 +0000 (16:20 +0000)]
Improve test for merged global debug info by using llvm-dwarfdump.

It's a bit of a tradeoff, since llvm-dwarfdump doesn't print the name of
the global symbol being used as an address in the addressing mode, but
this avoids the dependence on hardcoded set labels that keep changing
(5+ commits over the last few years that each update the set label as it
changes due to other, unrelated differences in output). This could've,
instead, been changed to match the set name then match the name in the
string pool but that would present other issues (needing to skip over
the sets that weren't of interest, etc) and checking that the addresses
(granted, without relocations applied - so it's not the whole story)
match in the two variable location descriptions seems sufficient and
fairly stable here.

There are a few similar other tests with similar label dependence that
I'll update soonish.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214878 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd accessors for the PPC 403 bank registers.
Joerg Sonnenberger [Tue, 5 Aug 2014 15:45:15 +0000 (15:45 +0000)]
Add accessors for the PPC 403 bank registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214875 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd tests for cp10/cp11 on ARMv5/6
Renato Golin [Tue, 5 Aug 2014 15:29:41 +0000 (15:29 +0000)]
Add tests for cp10/cp11 on ARMv5/6

Tests for ARMv7/8 are already on diagnostics.s

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214872 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoSpecify that the thumb setend and blx <immed> instructions are not valid on an m...
Keith Walker [Tue, 5 Aug 2014 15:11:59 +0000 (15:11 +0000)]
Specify that the thumb setend and blx <immed> instructions are not valid on an m-class target

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214871 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoDefine stc2/stc2l/ldc2/ldc2l as thumb2 instructions
Keith Walker [Tue, 5 Aug 2014 14:58:05 +0000 (14:58 +0000)]
Define stc2/stc2l/ldc2/ldc2l as thumb2 instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214868 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAccessors for SSR2 and SSR3 on PPC 403.
Joerg Sonnenberger [Tue, 5 Aug 2014 14:53:05 +0000 (14:53 +0000)]
Accessors for SSR2 and SSR3 on PPC 403.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214867 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoR600/SI: Update MUBUF assembly string to match AMD proprietary compiler
Tom Stellard [Tue, 5 Aug 2014 14:48:12 +0000 (14:48 +0000)]
R600/SI: Update MUBUF assembly string to match AMD proprietary compiler

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214866 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoR600/SI: Avoid generating REGISTER_LOAD instructions.
Tom Stellard [Tue, 5 Aug 2014 14:40:52 +0000 (14:40 +0000)]
R600/SI: Avoid generating REGISTER_LOAD instructions.

SI doesn't use REGISTER_LOAD anymore, but it was still hitting this code
path for 8-bit and 16-bit private loads.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214865 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd dci/ici instructions for PPC 476 and friends.
Joerg Sonnenberger [Tue, 5 Aug 2014 14:40:32 +0000 (14:40 +0000)]
Add dci/ici instructions for PPC 476 and friends.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214864 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd mftblo and mftbhi for PPC 4xx.
Joerg Sonnenberger [Tue, 5 Aug 2014 14:18:16 +0000 (14:18 +0000)]
Add mftblo and mftbhi for PPC 4xx.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214863 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd lswi / stswi for assembler use with a warning to not add patterns
Joerg Sonnenberger [Tue, 5 Aug 2014 13:34:01 +0000 (13:34 +0000)]
Add lswi / stswi for assembler use with a warning to not add patterns
for them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214862 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAArch64: Add support for instruction prefetch intrinsic
Yi Kong [Tue, 5 Aug 2014 12:46:47 +0000 (12:46 +0000)]
AArch64: Add support for instruction prefetch intrinsic

Instruction prefetch is not implemented for AArch64, it is incorrectly
translated into data prefetch instruction.

Differential Revision: http://reviews.llvm.org/D4777

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214860 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoTeach the SLP Vectorizer that keeping some values live over a callsite can have a...
James Molloy [Tue, 5 Aug 2014 12:30:34 +0000 (12:30 +0000)]
Teach the SLP Vectorizer that keeping some values live over a callsite can have a cost.

Some types, such as 128-bit vector types on AArch64, don't have any callee-saved registers. So if a value needs to stay live over a callsite, it must be spilled and refilled. This cost is now taken into account.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214859 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[x86] Reformat some code I moved around in a prior commit but left
Chandler Carruth [Tue, 5 Aug 2014 10:35:30 +0000 (10:35 +0000)]
[x86] Reformat some code I moved around in a prior commit but left
poorly formatted. Sorry about that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214853 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAllow binary and for tblgen math.
Joerg Sonnenberger [Tue, 5 Aug 2014 09:43:25 +0000 (09:43 +0000)]
Allow binary and for tblgen math.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214851 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[x86] Fix a crash and wrong-code bug in the new vector lowering all
Chandler Carruth [Tue, 5 Aug 2014 08:19:21 +0000 (08:19 +0000)]
[x86] Fix a crash and wrong-code bug in the new vector lowering all
found by a single test reduced out of a failure on llvm-stress.

The start of the problem (and the crash) came when we tried to use
a find of a non-used slot in the move-to half of the move-mask as the
target for two bad-half inputs. While if lucky this will be the first of
a pair of slots which we can place the bad-half inputs into, it isn't
actually guaranteed. This really isn't surprising, not sure what I was
thinking. The correct way to find the two unused slots is to look for
one of the *used* slots. We know it isn't that pair, and we can use some
modular arithmetic to find the other pair by masking off the odd bit and
adding 2 modulo 4. With this, we reliably found a viable pair of slots
for the bad-half inputs.

Sadly, that wasn't enough. We also had a wrong code bug that surfaced
when I reduced the test case for this where we would use the same slot
twice for the two bad inputs. This is because both of the bad inputs
could be in odd slots originally and thus the mod-2 mapping would
actually be the same. The whole point of the weird indexing into the
pair of empty slots was to try to leverage when the end result needed
the two bad-half inputs to be paired in a dword and pre-pair them in the
correct orrientation. This is less important with the powerful combining
we're now doing, and also easier and more reliable to achieve be noting
that we add the bad-half inputs in order. Thus, if they are in a dword
pair, the low part of that will be the first input in the sequence.
Always putting that in the low element will just do the right thing in
addition to computing the correct result.

Test case added. =]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214849 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[FastIsel][AArch64] Fix previous commit r214844 (Don't perform sign-/zero-extension...
Juergen Ributzka [Tue, 5 Aug 2014 07:31:30 +0000 (07:31 +0000)]
[FastIsel][AArch64] Fix previous commit r214844 (Don't perform sign-/zero-extension for function arguments that have already been sign-/zero-extended.)

The original code would fail for unsupported value types like i1, i8, and i16.
This fix changes the code to only create a sub-register copy for i64 value types
and all other types (i1/i8/i16/i32) just use the source register without any
modifications.

getRegClassFor() is now guarded by the i64 value type check, that guarantees
that we always request a register for a valid value type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214848 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[FastISel][AArch64] Implement the FastLowerArguments hook.
Juergen Ributzka [Tue, 5 Aug 2014 05:43:48 +0000 (05:43 +0000)]
[FastISel][AArch64] Implement the FastLowerArguments hook.

This implements basic argument lowering for AArch64 in FastISel. It only
handles a small subset of the C calling convention. It supports simple
arguments that can be passed in GPR and FPR registers.

This should cover most of the trivial cases without falling back to
SelectionDAG.

This fixes <rdar://problem/17890986>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214846 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRevert "r214832 - MachineCombiner Pass for selecting faster instruction"
Kevin Qin [Tue, 5 Aug 2014 05:43:47 +0000 (05:43 +0000)]
Revert "r214832 - MachineCombiner Pass for selecting faster instruction"

It broke compiling of most Benchmark and internal test, as clang got
clashed by segmentation fault or assertion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214845 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[FastISel][AArch64] Don't perform sign-/zero-extension for function arguments that...
Juergen Ributzka [Tue, 5 Aug 2014 05:43:44 +0000 (05:43 +0000)]
[FastISel][AArch64] Don't perform sign-/zero-extension for function arguments that have already been sign-/zero-extended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214844 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoProvide convenient access to the zext/sext attributes of function arguments. NFC.
Juergen Ributzka [Tue, 5 Aug 2014 05:43:41 +0000 (05:43 +0000)]
Provide convenient access to the zext/sext attributes of function arguments. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214843 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoHave MachineFunction cache a pointer to the subtarget to make lookups
Eric Christopher [Tue, 5 Aug 2014 02:39:49 +0000 (02:39 +0000)]
Have MachineFunction cache a pointer to the subtarget to make lookups
shorter/easier and have the DAG use that to do the same lookup. This
can be used in the future for TargetMachine based caching lookups from
the MachineFunction easily.

Update the MIPS subtarget switching machinery to update this pointer
at the same time it runs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214838 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMachineCombiner Pass for selecting faster instruction
Gerolf Hoflehner [Tue, 5 Aug 2014 01:16:13 +0000 (01:16 +0000)]
MachineCombiner Pass for selecting faster instruction
 sequence on AArch64

Re-commit of r214669 without changes to test cases
LLVM::CodeGen/AArch64/arm64-neon-mul-div.ll and
LLVM:: CodeGen/AArch64/dp-3source.ll
This resolves the reported compfails of the original commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214832 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd TCR register access
Joerg Sonnenberger [Mon, 4 Aug 2014 23:53:42 +0000 (23:53 +0000)]
Add TCR register access

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214826 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd PPC 603's tlbld and tlbli instructions.
Joerg Sonnenberger [Mon, 4 Aug 2014 23:49:45 +0000 (23:49 +0000)]
Add PPC 603's tlbld and tlbli instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214825 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAllow CP10/CP11 operations on ARMv5/v6
Renato Golin [Mon, 4 Aug 2014 23:21:56 +0000 (23:21 +0000)]
Allow CP10/CP11 operations on ARMv5/v6

Those registers are VFP/NEON and vector instructions should be used instead,
but old cores rely on those co-processors to enable VFP unwinding. This change
was prompted by the libc++abi's unwinding routine and is also present in many
legacy low-level bare-metal code that we ought to compile/assemble.

Fixing bug PR20025 and allowing PR20529 to proceed with a fix in libc++abi.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214802 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[PPC64LE] Fix wrong IR for vec_sld and vec_vsldoi
Bill Schmidt [Mon, 4 Aug 2014 23:21:01 +0000 (23:21 +0000)]
[PPC64LE] Fix wrong IR for vec_sld and vec_vsldoi

My original LE implementation of the vsldoi instruction, with its
altivec.h interfaces vec_sld and vec_vsldoi, produces incorrect
shufflevector operations in the LLVM IR.  Correct code is generated
because the back end handles the incorrect shufflevector in a
consistent manner.

This patch and a companion patch for Clang correct this problem by
removing the fixup from altivec.h and the corresponding fixup from the
PowerPC back end.  Several test cases are also modified to reflect the
now-correct LLVM IR.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214800 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoEnable Darwin vararg parameters support in assembler macros.
Kevin Enderby [Mon, 4 Aug 2014 23:14:37 +0000 (23:14 +0000)]
Enable Darwin vararg parameters support in assembler macros.

Duplicate the vararg tests for linux and add a tests which mixed
vararg arguments with darwin positional parameters.

Patch by: Janne Grunau <j@jannau.net>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214799 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoChanged the liveness tracking in the RegisterScavenger
Pedro Artigas [Mon, 4 Aug 2014 23:07:49 +0000 (23:07 +0000)]
Changed the liveness tracking in the RegisterScavenger
to use register units instead of registers.

reviewed by Jakob Stoklund Olesen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214798 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd simplified aliases for access to DCCR, ICCR, DEAR and ESR
Joerg Sonnenberger [Mon, 4 Aug 2014 22:56:42 +0000 (22:56 +0000)]
Add simplified aliases for access to DCCR, ICCR, DEAR and ESR

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214797 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix SmallDenseMap assignment operator.
Andrew Trick [Mon, 4 Aug 2014 22:18:25 +0000 (22:18 +0000)]
Fix SmallDenseMap assignment operator.

Self assignment would lead to buckets of garbage, causing quadratic probing to hang.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214790 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[FastISel][AArch64] Fix shift lowering for i8 and i16 value types.
Juergen Ributzka [Mon, 4 Aug 2014 21:49:51 +0000 (21:49 +0000)]
[FastISel][AArch64] Fix shift lowering for i8 and i16 value types.

This fix changes the parameters #r and #s that are passed to the UBFM/SBFM
instruction to get the zero/sign-extension for free.

The original problem was that the shift left would use the 32-bit shift even for
i8/i16 value types, which could leave the upper bits set with "garbage" values.

The arithmetic shift right on the other side would use the wrong MSB as sign-bit
to determine what bits to shift into the value.

This fixes <rdar://problem/17907720>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214788 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoIR: Fix up doxygen comment for LLVMContext::diagnose
Justin Bogner [Mon, 4 Aug 2014 21:49:15 +0000 (21:49 +0000)]
IR: Fix up doxygen comment for LLVMContext::diagnose

This comment was referring to the DiagnosticSeverity with RS_
prefixes, but they're actually DS_. I've also modernized the comment
style since I was changing it anyway.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214787 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SDAG] Fix a really, really terrible bug in the DAG combiner.
Chandler Carruth [Mon, 4 Aug 2014 21:29:59 +0000 (21:29 +0000)]
[SDAG] Fix a really, really terrible bug in the DAG combiner.

This code is completely wrong. It is also dead, as if it were to *ever*
run, it would crash. Fortunately, after my work to the combiner, it is
at least *possible* to reach the code, and llvm-stress has found a test
case. Thanks to Patrick for reporting.

It would be really good if anyone who remembers how this code works and
what it was intended to do could add some more obvious test coverage
instead of my completely contrived and reduced test case. My test case
was so brittle I left a bread crumb comment in it to help the next
person to stumble on it and not know what it was actually testing for.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214785 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agotlbre / tlbwe / tlbsx / tlbsx. variants for the PPC 4xx CPUs.
Joerg Sonnenberger [Mon, 4 Aug 2014 21:28:22 +0000 (21:28 +0000)]
tlbre / tlbwe / tlbsx / tlbsx. variants for the PPC 4xx CPUs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214784 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoReorder to keep data and routines separate and to keep a couple of
Eric Christopher [Mon, 4 Aug 2014 21:25:44 +0000 (21:25 +0000)]
Reorder to keep data and routines separate and to keep a couple of
similar routines close to each other.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214782 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRemove the TargetMachine forwards for TargetSubtargetInfo based
Eric Christopher [Mon, 4 Aug 2014 21:25:23 +0000 (21:25 +0000)]
Remove the TargetMachine forwards for TargetSubtargetInfo based
information and update all callers. No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214781 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoReimplement the temporary non-const getSubtargetImpl routine so
Eric Christopher [Mon, 4 Aug 2014 21:24:07 +0000 (21:24 +0000)]
Reimplement the temporary non-const getSubtargetImpl routine so
that we can avoid implementing it on every target. Thanks to Richard
Smith for the suggestions!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214780 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AArch64] Extend the number of scalar instructions supported in the AdvSIMD
Chad Rosier [Mon, 4 Aug 2014 21:20:25 +0000 (21:20 +0000)]
[AArch64] Extend the number of scalar instructions supported in the AdvSIMD
scalar integer instruction pass.

This is a patch I had lying around from a few months ago.  The pass is
currently disabled by default, so nothing to interesting.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214779 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMC uses .lcomm now, so adjust.
Joerg Sonnenberger [Mon, 4 Aug 2014 21:06:00 +0000 (21:06 +0000)]
MC uses .lcomm now, so adjust.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214776 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix failure to invoke exception handler on Win64
Reid Kleckner [Mon, 4 Aug 2014 21:05:27 +0000 (21:05 +0000)]
Fix failure to invoke exception handler on Win64

When the last instruction prior to a function epilogue is a call, we
need to emit a nop so that the return address is not in the epilogue IP
range.  This is consistent with MSVC's behavior, and may be a workaround
for a bug in the Win64 unwinder.

Differential Revision: http://reviews.llvm.org/D4751

Patch by Vadim Chugunov!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214775 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoCorrect the emission kind constants committed in r214771
David Blaikie [Mon, 4 Aug 2014 20:36:00 +0000 (20:36 +0000)]
Correct the emission kind constants committed in r214771

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214772 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoDocument the "emission kind" field of the DICompileUnit in LLVM's Source Level Debugg...
David Blaikie [Mon, 4 Aug 2014 20:32:48 +0000 (20:32 +0000)]
Document the "emission kind" field of the DICompileUnit in LLVM's Source Level Debugging metadata.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214771 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRecognize mftbl as alias for mftb, for symmetry with mttb.
Joerg Sonnenberger [Mon, 4 Aug 2014 20:28:34 +0000 (20:28 +0000)]
Recognize mftbl as alias for mftb, for symmetry with mttb.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214769 91177308-0d34-0410-b5e6-96231b3b80d8