opencl/llvm.git
6 years ago[cmake] Unbreak LLVM-Config.cmake / llvm_expand_dependencies.
Peter Zotov [Thu, 18 Dec 2014 23:56:52 +0000 (23:56 +0000)]
[cmake] Unbreak LLVM-Config.cmake / llvm_expand_dependencies.

The algorithm for sorting libraries in topological order, as
previously implemented, had a few issues:
  * It didn't make any sense.
  * It didn't actually sort libraries in topological order.
  * It hung on some inputs, e.g. "LLVMipo".

This commit replaces the old algorithm with a straightforward port
from llvm-config.cpp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224554 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoConstantFold: Shifting undef by zero results in undef
David Majnemer [Thu, 18 Dec 2014 23:54:43 +0000 (23:54 +0000)]
ConstantFold: Shifting undef by zero results in undef

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224553 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoReverting 224550, was not ready for commit.
Colin LeMahieu [Thu, 18 Dec 2014 23:36:15 +0000 (23:36 +0000)]
Reverting 224550, was not ready for commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224552 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoRemove an extra ';' on line 1120 include/llvm/Support/MachO.h .
Kevin Enderby [Thu, 18 Dec 2014 23:34:16 +0000 (23:34 +0000)]
Remove an extra ';' on line 1120 include/llvm/Support/MachO.h .

Caught by Mike Edwards!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224551 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[Hexagon] Adding loop0/1 sp0/1/2loop0 instructions.
Colin LeMahieu [Thu, 18 Dec 2014 23:27:51 +0000 (23:27 +0000)]
[Hexagon] Adding loop0/1 sp0/1/2loop0 instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224550 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoAdd printing the LC_SUB_UMBRELLA load command with llvm-objdump’s -private-headers.
Kevin Enderby [Thu, 18 Dec 2014 23:13:26 +0000 (23:13 +0000)]
Add printing the LC_SUB_UMBRELLA load command with llvm-objdump’s -private-headers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224548 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoInstead of explicitely comparing both lowercase and uppercase variants.
Roman Divacky [Thu, 18 Dec 2014 23:12:34 +0000 (23:12 +0000)]
Instead of explicitely comparing both lowercase and uppercase variants.
.lower() the Name and compare only the lowecase. Removing 81 compares/lines of
code. This changes the accepted string to be mixed lower/upper case but it
should be ok.

Discussed with Jim Grosbach.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224547 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agofix formatting; NFC
Sanjay Patel [Thu, 18 Dec 2014 21:11:09 +0000 (21:11 +0000)]
fix formatting; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224542 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoHave llvm-c-test only use libLLVM if libLLVM has all the right components.
Chris Bieneman [Thu, 18 Dec 2014 21:03:49 +0000 (21:03 +0000)]
Have llvm-c-test only use libLLVM if libLLVM has all the right components.

Summary: We should only have llvm-c-test use libLLVM if the library is built with the default set of components or if LLVM_DYLIB_COMPONENTS includes all the LLVM_LINK_COMPONENTS required for llvm-c-test. Making libLLVM always used causes build failures if libLLVM doesn't include all

Reviewers: chapuni, ributzka

Reviewed By: ributzka

Subscribers: ributzka, llvm-commits

Differential Revision: http://reviews.llvm.org/D6668

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224541 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[NFC] Removing extra semicolon.
Colin LeMahieu [Thu, 18 Dec 2014 20:15:32 +0000 (20:15 +0000)]
[NFC] Removing extra semicolon.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224539 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoLiveIntervalAnalysis: Cleanup computeDeadValues
Matthias Braun [Thu, 18 Dec 2014 19:58:52 +0000 (19:58 +0000)]
LiveIntervalAnalysis: Cleanup computeDeadValues

- This also fixes a bug introduced in r223880 where values were not
  correctly marked as Dead anymore.
- Cleanup computeDeadValues(): split up SubRange code variant, simplify
  arguments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224538 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoAdd myself as SystemZ code owner
Ulrich Weigand [Thu, 18 Dec 2014 19:27:50 +0000 (19:27 +0000)]
Add myself as SystemZ code owner

As agreed with Richard Sandiford, I'm taking over code ownership
for the SystemZ back end from him.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224535 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoAdd printing the LC_SUB_FRAMEWORK load command with llvm-objdump’s -private-headers.
Kevin Enderby [Thu, 18 Dec 2014 19:24:35 +0000 (19:24 +0000)]
Add printing the LC_SUB_FRAMEWORK load command with llvm-objdump’s -private-headers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224534 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoAdd missing implementation of 'sys::path::is_other' to the support library.
Juergen Ributzka [Thu, 18 Dec 2014 18:19:47 +0000 (18:19 +0000)]
Add missing implementation of 'sys::path::is_other' to the support library.

The header claims that this function exists, but the linker wasn't too happy
about it not being in the library.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224527 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[mips][microMIPS] Fix bugs related to atomic SC/LL instructions
Jozef Kolek [Thu, 18 Dec 2014 16:39:29 +0000 (16:39 +0000)]
[mips][microMIPS] Fix bugs related to atomic SC/LL instructions

Fix bugs related to atomic microMIPS SC/LL instructions: While expanding atomic
operations the mips32r2 encoding was emitted instead of microMIPS.

Differential Revision: http://reviews.llvm.org/D6659

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224524 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoARM: fix an off-by-one in the register list access
Saleem Abdulrasool [Thu, 18 Dec 2014 16:16:53 +0000 (16:16 +0000)]
ARM: fix an off-by-one in the register list access

Fix an off-by-one access introduced in 224502 for push.w and pop.w with single
register operands.  Add test cases for both scenarios.

Thanks to Asiri Rathnayake for pointing out the failure!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224521 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[mips] Clean up the CodeGen/Mips/inlineasmmemop.ll test. NFC.
Toma Tabacu [Thu, 18 Dec 2014 13:03:51 +0000 (13:03 +0000)]
[mips] Clean up the CodeGen/Mips/inlineasmmemop.ll test. NFC.

Summary:
Improve comments and remove a redundant attribute list.
There are no functional changes (to the CHECK's or to the code).

Part of these changes were suggested in http://reviews.llvm.org/D6637.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D6705

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224517 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[AVX512] Enable FP arithmetic lowering for AVX512VL subsets.
Robert Khasanov [Thu, 18 Dec 2014 12:28:22 +0000 (12:28 +0000)]
[AVX512] Enable FP arithmetic lowering for AVX512VL subsets.
Added RegOp2MemOpTable4 to transform 4th operand from register to memory in merge-masked versions of instructions.
Added lowering tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224516 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[Msan] Generalize instrumentation code to support FreeBSD mapping
Viktor Kutuzov [Thu, 18 Dec 2014 12:12:59 +0000 (12:12 +0000)]
[Msan] Generalize instrumentation code to support FreeBSD mapping
Differential Revision: http://reviews.llvm.org/D6666

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224514 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoFix Visual C++ error "'llvm::make_unique' : ambiguous call to overloaded function".
Yaron Keren [Thu, 18 Dec 2014 10:03:35 +0000 (10:03 +0000)]
Fix Visual C++ error "'llvm::make_unique' : ambiguous call to overloaded function".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224506 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoARM: improve instruction validation for thumb mode
Saleem Abdulrasool [Thu, 18 Dec 2014 05:24:38 +0000 (05:24 +0000)]
ARM: improve instruction validation for thumb mode

The ARM Architecture Reference Manual states the following:
  LDM{,IA,DB}:
    The SP cannot be in the list.
    The PC can be in the list.
    If the PC is in the list:
      • the LR must not be in the list
      • the instruction must be either outside any IT block, or the last
        instruction in an IT block.
  POP:
    The PC can be in the list.
    If the PC is in the list:
      • the LR must not be in the list
      • the instruction must be either outside any IT block, or the last
        instruction in an IT block.
  PUSH:
    The SP and PC can be in the list in ARM instructions, but not in Thumb
    instructions.
  STM:{,IA,DB}:
    The SP and PC can be in the list in ARM instructions, but not in Thumb
    instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224502 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agotest: avoid unnecessary temporary files
Saleem Abdulrasool [Thu, 18 Dec 2014 05:24:32 +0000 (05:24 +0000)]
test: avoid unnecessary temporary files

Use pipes and redirect the error output to FileCheck directly.  NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224501 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[SROA] Cleanup - remove the use of std::mem_fun_ref nonsense and use
Chandler Carruth [Thu, 18 Dec 2014 05:19:47 +0000 (05:19 +0000)]
[SROA] Cleanup - remove the use of std::mem_fun_ref nonsense and use
a lambda now that we have them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224500 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoModernize the getStreamedBitcodeModule interface a bit. NFC.
Rafael Espindola [Thu, 18 Dec 2014 05:08:43 +0000 (05:08 +0000)]
Modernize the getStreamedBitcodeModule interface a bit. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224499 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[PowerPC] Use MCPhysReg for tables of registers. Const-correct the tables. Only put...
Craig Topper [Thu, 18 Dec 2014 05:02:14 +0000 (05:02 +0000)]
[PowerPC] Use MCPhysReg for tables of registers. Const-correct the tables. Only put the anonymous namespace around classes. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224498 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Use correct opsize on indirect call and jump aliases.
Craig Topper [Thu, 18 Dec 2014 05:02:12 +0000 (05:02 +0000)]
[X86] Use correct opsize on indirect call and jump aliases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224497 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Don't use PS prefix on LDMXCSR/STMXCSR.
Craig Topper [Thu, 18 Dec 2014 05:02:10 +0000 (05:02 +0000)]
[X86] Don't use PS prefix on LDMXCSR/STMXCSR.

Near as I can tell prefixes are ignored on these instructions except for a comment in the Intel docs about 0xf3. Binutils disassembler seems to ignore prefixes on these instructions. Our disassembler still doesn't distinguish PS and "no prefix" well enough for this to make a functional change, but it helps with experiments I'm doing on a potential new disassembler table builder.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224496 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Remove unnecessary 'In64BitMode' predicate for instructions that already indica...
Craig Topper [Thu, 18 Dec 2014 05:02:08 +0000 (05:02 +0000)]
[X86] Remove unnecessary 'In64BitMode' predicate for instructions that already indicate use of REX.W.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224495 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoAdd a corresponding '@LOCAL' parse to match r224415.
Justin Hibbits [Thu, 18 Dec 2014 03:06:37 +0000 (03:06 +0000)]
Add a corresponding '@LOCAL' parse to match r224415.

Pointed out by Jim Grosbach.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224494 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoAdd a new string member to the TargetOptions struct for the name
Eric Christopher [Thu, 18 Dec 2014 02:20:58 +0000 (02:20 +0000)]
Add a new string member to the TargetOptions struct for the name
of the abi we should be using. For targets that don't use the
option there's no change, otherwise this allows external users
to set the ABI via string and avoid some of the -backend-option
pain in clang.

Use this option to move the ABI for the ARM port from the
Subtarget to the TargetMachine and update the testcases
accordingly since it's no longer valid to set via -mattr.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224492 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoModel ARM backend ABI selection after the front end code doing the
Eric Christopher [Thu, 18 Dec 2014 02:08:45 +0000 (02:08 +0000)]
Model ARM backend ABI selection after the front end code doing the
same. This will change the "bare metal" ABI from APCS to AAPCS.

The only difference between the front and back end code is that
the code for Triple::GNU was added for environment. That will migrate
to the front end shortly.

Tests updated with the ABI they were originally testing in the case
of bare metal (e.g. -mtriple armv7) or with a -gnu for arm-linux
triples.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224489 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoReapply "Linker: Drop superseded subprograms"
Duncan P. N. Exon Smith [Thu, 18 Dec 2014 01:05:33 +0000 (01:05 +0000)]
Reapply "Linker: Drop superseded subprograms"

This reverts commit r224416, reapplying r224389.  The buildbots hadn't
recovered after my revert, waiting until David reverted a couple of his
commits.  It looks like it was just bad timing (where we were both
modifying code related to the same assertion).  Trying again...

Here's the original text:

    When a function gets replaced by `ModuleLinker`, drop superseded
    subprograms.  This ensures that the "first" subprogram pointing at a
    function is the same one that `!dbg` references point at.

    This is a stop-gap fix for PR21910.  Notably, this fixes Release+Asserts
    bootstraps that are currently asserting out in
    `LexicalScopes::initialize()` due to the explicit instantiations in
    `lib/IR/Dominators.cpp` eventually getting replaced by -argpromotion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224487 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoIR: Make DICompositeType mutators private
Duncan P. N. Exon Smith [Thu, 18 Dec 2014 00:54:39 +0000 (00:54 +0000)]
IR: Make DICompositeType mutators private

Make `DICompositeType` mutators private to prevent misuse.  All calls to
`setArrays()` and `setContainingType()` should go through
`DIBuilder::replaceArrays()` and `DIBuilder::replaceVTableHolder()`.

This is a follow-up to r224482 (now that clang has been updated in
r224483).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224486 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoAdd printing the LC_LINKER_OPTION load command with llvm-objdump’s -private-headers.
Kevin Enderby [Thu, 18 Dec 2014 00:53:40 +0000 (00:53 +0000)]
Add printing the LC_LINKER_OPTION load command with llvm-objdump’s -private-headers.
Also corrected the name of the load command to not end in an ’S’ as well as corrected
the name of the MachO::linker_option_command struct and other places that had the
word option as plural which did not match the Mac OS X headers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224485 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoIR: Handle self-referencing DICompositeTypes in DIBuilder
Duncan P. N. Exon Smith [Thu, 18 Dec 2014 00:46:16 +0000 (00:46 +0000)]
IR: Handle self-referencing DICompositeTypes in DIBuilder

Add API to DIBuilder to handle self-referencing `DICompositeType`s.

Self-references aren't expected in the debug info graph, and we take
advantage of that by only calling `resolveCycles()` on nodes that were
once forward declarations (otherwise, DIBuilder needs an expensive
tracking reference to every unresolved node it creates, which in cyclic
graphs is *all of them*).

However, clang seems to create self-referencing `DICompositeType`s.  Add
API to manage this safely.  The paired commit to clang will include the
regression test.

I'll make the `DICompositeType` API `private` in a follow-up to prevent
misuse (I've separated that to prevent build failures from missing the
clang commit).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224482 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[dsymutil] Fix missing member initializer.
Alexey Samsonov [Thu, 18 Dec 2014 00:45:32 +0000 (00:45 +0000)]
[dsymutil] Fix missing member initializer.

This bug was found by the MSan bootstrap bot:
http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-bootstrap/builds/5330/steps/check-llvm%20msan/logs/stdio

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224481 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoLTO: Lazy-load LTOModule in local contexts
Duncan P. N. Exon Smith [Wed, 17 Dec 2014 22:05:42 +0000 (22:05 +0000)]
LTO: Lazy-load LTOModule in local contexts

Start lazy-loading `LTOModule`s that own their contexts.  These can only
really be used for parsing symbols, so its unnecessary to ever
materialize their functions.

I looked into using `IRObjectFile::create()` and optionally calling
`materializAllPermanently()` afterwards, but this turned out to be
awkward.

  - The default target triple and data layout logic needs to happen
    *before* the call to `IRObjectFile::IRObjectFile()`, but after
    `Module` was created.

  - I tried passing a lambda in to do the module initialization, but
    this seemed to require threading the error message from
    `TargetRegistry::lookupTarget()` through `std::error_code`.

  - I also looked at setting `errMsg` directly from within the lambda,
    but this didn't look any better.

(I guess there's a reason we weren't already using that function.)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224466 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[sanitizer] allow -fsanitize-coverage=N w/ -fsanitize=leak, llvm part
Kostya Serebryany [Wed, 17 Dec 2014 21:50:04 +0000 (21:50 +0000)]
[sanitizer] allow -fsanitize-coverage=N w/ -fsanitize=leak, llvm part

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224463 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoRegisterCoalescer: Fix stripCopies() picking up main range instead of subregister...
Matthias Braun [Wed, 17 Dec 2014 21:25:20 +0000 (21:25 +0000)]
RegisterCoalescer: Fix stripCopies() picking up main range instead of subregister range

This fixes a problem where stripCopies() would switch to values in the
main liverange when it crossed a copy instruction. However when joining
subranges we need to stay in the respective subregister ranges.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224461 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoR600/SI: Fix f64 inline immediates
Matt Arsenault [Wed, 17 Dec 2014 21:04:08 +0000 (21:04 +0000)]
R600/SI: Fix f64 inline immediates

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224458 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[Hexagon] Reconfiguring register alternate names.
Colin LeMahieu [Wed, 17 Dec 2014 20:35:11 +0000 (20:35 +0000)]
[Hexagon] Reconfiguring register alternate names.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224455 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoEnable the P8Model entry
Will Schmidt [Wed, 17 Dec 2014 19:56:29 +0000 (19:56 +0000)]
Enable the P8Model entry

This was missed last time around, for the P8 Instruction Scheduling
changes (223257). This will hook the P8Model entry in so those
changes will actually be used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224452 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoExecutionDepsFix: Correctly handle wide registers.
Matthias Braun [Wed, 17 Dec 2014 19:13:47 +0000 (19:13 +0000)]
ExecutionDepsFix: Correctly handle wide registers.

The ExecutionDepsFix previously mapped each register to 1 or zero
registers of the register class it was called with and therefore
simulating liveness for.  This was problematic for cases involving wider
registers like Q0 on ARM where ExecutionDepsFix gets invoked for the Dxx
registers. In these cases the wide register would get mapped to the last
matching D register, while it should have been all matching D registers.
This commit changes the AliasMap to use a SmallVector to map registers
to potentially multiple destination regclass registers. This is required
to avoid regressions with subregister liveness tracking enabled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224447 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoRandom Number Generator Refactoring (removing from Module)
JF Bastien [Wed, 17 Dec 2014 18:12:10 +0000 (18:12 +0000)]
Random Number Generator Refactoring (removing from Module)

This patch removes the RNG from Module. Passes should instead create a new RNG for their use as needed.

Patch by Stephen Crane @rinon.

Differential revision: http://reviews.llvm.org/D4377

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224444 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[NVPTX] Fix bugs related to isSingleValueType
Jingyue Wu [Wed, 17 Dec 2014 17:59:04 +0000 (17:59 +0000)]
[NVPTX] Fix bugs related to isSingleValueType

Summary:
With isSingleValueType starting to treat vector types as single-value types,
code that uses this interface needs to be updated.

Test Plan:
vector-global.ll
nvcl-param-align.ll

Reviewers: jholewinski

Reviewed By: jholewinski

Subscribers: llvm-commits, meheff, eliben, jholewinski

Differential Revision: http://reviews.llvm.org/D6573

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224440 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoFix CR/LF line endings in test case
Timur Iskhodzhanov [Wed, 17 Dec 2014 17:52:12 +0000 (17:52 +0000)]
Fix CR/LF line endings in test case

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224437 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoARM: correct an off-by-one in an assert
Saleem Abdulrasool [Wed, 17 Dec 2014 16:17:44 +0000 (16:17 +0000)]
ARM: correct an off-by-one in an assert

The assert was off-by-one, resulting in failures for valid input.

Thanks to Asiri Rathnayake for pointing out the failure!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224432 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[DAGCombine] Slightly improve lowering of BUILD_VECTOR into a shuffle.
Michael Kuperstein [Wed, 17 Dec 2014 12:32:17 +0000 (12:32 +0000)]
[DAGCombine] Slightly improve lowering of BUILD_VECTOR into a shuffle.

This handles the case of a BUILD_VECTOR being constructed out of elements extracted from a vector twice the size of the result vector. Previously this was always scalarized. Now, we try to construct a shuffle node that feeds on extract_subvectors.

This fixes PR15872 and provides a partial fix for PR21711.

Differential Revision: http://reviews.llvm.org/D6678

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224429 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoMipsABIInfo class is used in different libraries. Moving the files to MCTargetDesc...
Vladimir Medic [Wed, 17 Dec 2014 11:49:56 +0000 (11:49 +0000)]
MipsABIInfo class is used in different libraries. Moving the files to MCTargetDesc folder(LLVMMipsDesc library) prevents linkage errors. There are no functional changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224427 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[mips] Set GCC-compatible MIPS asssembler options before inline asm blocks.
Toma Tabacu [Wed, 17 Dec 2014 10:56:16 +0000 (10:56 +0000)]
[mips] Set GCC-compatible MIPS asssembler options before inline asm blocks.

Summary:
When generating MIPS assembly, LLVM always overrides the default assembler options by emitting the '.set noreorder', '.set nomacro' and '.set noat' directives,
while GCC uses the default options if an assembly-level function contains inline assembly code.

This becomes a problem when the code generated by LLVM is interleaved with inline assembly which assumes GCC-like assembler options (from Linux, for example).

This patch fixes these conflicts by setting the appropriate assembler options at the beginning of an inline asm block and popping them at the end.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D6637

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224425 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoRevert 224119 "This patch recognizes (+ (+ v0, v1) (+ v2, v3)), reorders them for...
Suyog Sarda [Wed, 17 Dec 2014 10:34:27 +0000 (10:34 +0000)]
Revert 224119 "This patch recognizes (+ (+ v0, v1) (+ v2, v3)), reorders them for bundling into vector of loads,
and vectorizes it."

This was re-ordering floating point data types resulting in mismatch in output.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224424 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoTeach lit.cfg to recognize -windows-gnu in addition to -mingw32.
Yaron Keren [Wed, 17 Dec 2014 09:55:15 +0000 (09:55 +0000)]
Teach lit.cfg to recognize -windows-gnu in addition to -mingw32.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224421 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoAdded 5 more tests related to sink store revision 224247
Elena Demikhovsky [Wed, 17 Dec 2014 08:12:59 +0000 (08:12 +0000)]
Added 5 more tests related to sink store revision 224247
- by Ella Bolshinsky

http://reviews.llvm.org/D6420

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224418 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoStrength reduce intrinsics with overflow into regular arithmetic operations if possible.
Erik Eckstein [Wed, 17 Dec 2014 07:29:19 +0000 (07:29 +0000)]
Strength reduce intrinsics with overflow into regular arithmetic operations if possible.

Some intrinsics, like s/uadd.with.overflow and umul.with.overflow, are already strength reduced.
This change adds other arithmetic intrinsics: s/usub.with.overflow, smul.with.overflow.
It completes the work on PR20194.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224417 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoRevert "Linker: Drop superseded subprograms"
Duncan P. N. Exon Smith [Wed, 17 Dec 2014 07:27:31 +0000 (07:27 +0000)]
Revert "Linker: Drop superseded subprograms"

This reverts commit r224389.  Based on feedback from the bots, the
assertion seems to be going off *more* often, not less (previously I was
just seeing it in an internal bootstrap, now it's happening in public
builds too).

http://lab.llvm.org:8080/green/job/clang-stage2-configure-Rlto_build/936/
http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-bootstrap/builds/5325

Reverting in order to investigate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224416 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoAdd parsing of 'foo@local".
Justin Hibbits [Wed, 17 Dec 2014 06:23:35 +0000 (06:23 +0000)]
Add parsing of 'foo@local".

Summary:
Currently, it supports generating, but not parsing, this expression.
Test added as well.

Test Plan: New test added, no regressions due to this.

Reviewers: hfinkel

Reviewed By: hfinkel

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D6672

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224415 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoRemove a debugging assert.
Rafael Espindola [Wed, 17 Dec 2014 03:38:04 +0000 (03:38 +0000)]
Remove a debugging assert.

Sorry for the noise, I have no idea how it survived to the final version.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224414 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoRemove unused includes and out of date comment. NFC.
Rafael Espindola [Wed, 17 Dec 2014 03:07:20 +0000 (03:07 +0000)]
Remove unused includes and out of date comment. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224413 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoFix the windows build.
Rafael Espindola [Wed, 17 Dec 2014 02:42:20 +0000 (02:42 +0000)]
Fix the windows build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224412 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoRefactor and simplify the code reading /proc/cpuinfo. NFC.
Rafael Espindola [Wed, 17 Dec 2014 02:32:44 +0000 (02:32 +0000)]
Refactor and simplify the code reading /proc/cpuinfo. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224410 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoRegisterCoalescer: Sprinkle some const modifiers.
Matthias Braun [Wed, 17 Dec 2014 02:18:13 +0000 (02:18 +0000)]
RegisterCoalescer: Sprinkle some const modifiers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224409 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agollvm-lto: Add testing coverage for local contexts
Duncan P. N. Exon Smith [Wed, 17 Dec 2014 02:00:38 +0000 (02:00 +0000)]
llvm-lto: Add testing coverage for local contexts

Add coverage in `llvm-lto` for the API exposed by libLTO to create
modules in local contexts.

The goal here isn't to test the symbol-related API extensively, just to
confirm that these modules work at all.  (I'll be shifting code around
soon that should be NFC and I realized there was no test coverage.)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224408 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoDelete debugging cruft that crept in with r223802.
Nick Lewycky [Wed, 17 Dec 2014 01:56:51 +0000 (01:56 +0000)]
Delete debugging cruft that crept in with r223802.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224407 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoInstSimplify: shl nsw/nuw undef, %V -> undef
David Majnemer [Wed, 17 Dec 2014 01:54:33 +0000 (01:54 +0000)]
InstSimplify: shl nsw/nuw undef, %V -> undef

We can always choose an value for undef which might cause %V to shift
out an important bit except for one case, when %V is zero.

However, shl behaves like an identity function when the right hand side
is zero.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224405 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoMake ValueEnumerator::print use OS for metadata too. Noticed by inspection.
Nick Lewycky [Wed, 17 Dec 2014 01:52:08 +0000 (01:52 +0000)]
Make ValueEnumerator::print use OS for metadata too. Noticed by inspection.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224404 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[CodeGenPrepare] Reapply r224351 with a fix for the assertion failure:
Quentin Colombet [Wed, 17 Dec 2014 01:36:17 +0000 (01:36 +0000)]
[CodeGenPrepare] Reapply r224351 with a fix for the assertion failure:
The type promotion helper does not support vector type, so when make
such it does not kick in in such cases.

Original commit message:
[CodeGenPrepare] Move sign/zero extensions near loads using type promotion.

This patch extends the optimization in CodeGenPrepare that moves a sign/zero
extension near a load when the target can combine them. The optimization may
promote any operations between the extension and the load to make that possible.

Although this optimization may be beneficial for all targets, in particular
AArch64, this is enabled for X86 only as I have not benchmarked it for other
targets yet.

** Context **

Most targets feature extended loads, i.e., loads that perform a zero or sign
extension for free. In that context it is interesting to expose such pattern in
CodeGenPrepare so that the instruction selection pass can form such loads.
Sometimes, this pattern is blocked because of instructions between the load and
the extension. When those instructions are promotable to the extended type, we
can expose this pattern.

** Motivating Example **

Let us consider an example:
define void @foo(i8* %addr1, i32* %addr2, i8 %a, i32 %b) {
  %ld = load i8* %addr1
  %zextld = zext i8 %ld to i32
  %ld2 = load i32* %addr2
  %add = add nsw i32 %ld2, %zextld
  %sextadd = sext i32 %add to i64
  %zexta = zext i8 %a to i32
  %addza = add nsw i32 %zexta, %zextld
  %sextaddza = sext i32 %addza to i64
  %addb = add nsw i32 %b, %zextld
  %sextaddb = sext i32 %addb to i64
  call void @dummy(i64 %sextadd, i64 %sextaddza, i64 %sextaddb)
  ret void
}

As it is, this IR generates the following assembly on x86_64:
[...]
  movzbl  (%rdi), %eax   # zero-extended load
  movl  (%rsi), %es      # plain load
  addl  %eax, %esi       # 32-bit add
  movslq  %esi, %rdi     # sign extend the result of add
  movzbl  %dl, %edx      # zero extend the first argument
  addl  %eax, %edx       # 32-bit add
  movslq  %edx, %rsi     # sign extend the result of add
  addl  %eax, %ecx       # 32-bit add
  movslq  %ecx, %rdx     # sign extend the result of add
[...]
The throughput of this sequence is 7.45 cycles on Ivy Bridge according to IACA.

Now, by promoting the additions to form more extended loads we would generate:
[...]
  movzbl  (%rdi), %eax   # zero-extended load
  movslq  (%rsi), %rdi   # sign-extended load
  addq  %rax, %rdi       # 64-bit add
  movzbl  %dl, %esi      # zero extend the first argument
  addq  %rax, %rsi       # 64-bit add
  movslq  %ecx, %rdx     # sign extend the second argument
  addq  %rax, %rdx       # 64-bit add
[...]
The throughput of this sequence is 6.15 cycles on Ivy Bridge according to IACA.

This kind of sequences happen a lot on code using 32-bit indexes on 64-bit
architectures.

Note: The throughput numbers are similar on Sandy Bridge and Haswell.

** Proposed Solution **

To avoid the penalty of all these sign/zero extensions, we merge them in the
loads at the beginning of the chain of computation by promoting all the chain of
computation on the extended type. The promotion is done if and only if we do not
introduce new extensions, i.e., if we do not degrade the code quality.
To achieve this, we extend the existing “move ext to load” optimization with the
promotion mechanism introduced to match larger patterns for addressing mode
(r200947).
The idea of this extension is to perform the following transformation:
ext(promotableInst1(...(promotableInstN(load))))
=>
promotedInst1(...(promotedInstN(ext(load))))

The promotion mechanism in that optimization is enabled by a new TargetLowering
switch, which is off by default. In other words, by default, the optimization
performs the “move ext to load” optimization as it was before this patch.

** Performance **

Configuration: x86_64: Ivy Bridge fixed at 2900MHz running OS X 10.10.
Tested Optimization Levels: O3/Os
Tests: llvm-testsuite + externals.
Results:
- No regression beside noise.
- Improvements:
CINT2006/473.astar:  ~2%
Benchmarks/PAQ8p: ~2%
Misc/perlin: ~3%

The results are consistent for both O3 and Os.

<rdar://problem/18310086>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224402 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoAdd printing the LC_ENCRYPTION_INFO_64 load command with llvm-objdump’s -private...
Kevin Enderby [Wed, 17 Dec 2014 01:01:30 +0000 (01:01 +0000)]
Add printing the LC_ENCRYPTION_INFO_64 load command with llvm-objdump’s -private-headers
and add tests for the two AArch64 binaries.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224400 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoPR21875: codegen for non-type template parameters of nullptr_t type
David Blaikie [Wed, 17 Dec 2014 00:43:22 +0000 (00:43 +0000)]
PR21875: codegen for non-type template parameters of nullptr_t type

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224399 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoRevert "[CodeGenPrepare] Move sign/zero extensions near loads using type promotion."
Reid Kleckner [Wed, 17 Dec 2014 00:29:23 +0000 (00:29 +0000)]
Revert "[CodeGenPrepare] Move sign/zero extensions near loads using type promotion."

This reverts commit r224351. It causes assertion failures when building
ICU.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224397 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoSelectionDAG switch lowering: use 'unsigned' to count destination popularity
Hans Wennborg [Tue, 16 Dec 2014 23:41:59 +0000 (23:41 +0000)]
SelectionDAG switch lowering: use 'unsigned' to count destination popularity

SwitchInst::getNumCases() returns unsinged, so using uint64_t to count cases
seems unnecessary.

Also fix a missing CHECK in the test case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224393 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[Hexagon] Updating doubleword shift usages to new versions.
Colin LeMahieu [Tue, 16 Dec 2014 23:36:15 +0000 (23:36 +0000)]
[Hexagon] Updating doubleword shift usages to new versions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224391 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoAdd printing the LC_ENCRYPTION_INFO load command with llvm-objdump’s -private-headers.
Kevin Enderby [Tue, 16 Dec 2014 23:25:52 +0000 (23:25 +0000)]
Add printing the LC_ENCRYPTION_INFO load command with llvm-objdump’s -private-headers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224390 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoLinker: Drop superseded subprograms
Duncan P. N. Exon Smith [Tue, 16 Dec 2014 23:23:41 +0000 (23:23 +0000)]
Linker: Drop superseded subprograms

When a function gets replaced by `ModuleLinker`, drop superseded
subprograms.  This ensures that the "first" subprogram pointing at a
function is the same one that `!dbg` references point at.

This is a stop-gap fix for PR21910.  Notably, this fixes Release+Asserts
bootstraps that are currently asserting out in
`LexicalScopes::initialize()` due to the explicit instantiations in
`lib/IR/Dominators.cpp` eventually getting replaced by -argpromotion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224389 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agofix typo, add spaces; NFC
Sanjay Patel [Tue, 16 Dec 2014 22:48:42 +0000 (22:48 +0000)]
fix typo, add spaces; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224384 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86][SSE] Vector double -> float conversion memory folding (cvtpd2ps)
Simon Pilgrim [Tue, 16 Dec 2014 22:30:10 +0000 (22:30 +0000)]
[X86][SSE] Vector double -> float conversion memory folding (cvtpd2ps)

Added a missing memory folding relationship for the (V)CVTPD2PS instruction - we can safely fold these for stack reloads.

Differential Revision: http://reviews.llvm.org/D6663

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224383 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoMake the assert a bit stronger.
Rafael Espindola [Tue, 16 Dec 2014 22:29:43 +0000 (22:29 +0000)]
Make the assert a bit stronger.

We should get no declarations in here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224382 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[Hexagon] Removing old XTYPE/BIT instructions and replacing usages.
Colin LeMahieu [Tue, 16 Dec 2014 22:17:09 +0000 (22:17 +0000)]
[Hexagon] Removing old XTYPE/BIT instructions and replacing usages.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224381 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agomerge consecutive loads that are offset from a base address
Sanjay Patel [Tue, 16 Dec 2014 21:57:18 +0000 (21:57 +0000)]
merge consecutive loads that are offset from a base address

SelectionDAG::isConsecutiveLoad() was not detecting consecutive loads
when the first load was offset from a base address.

This patch recognizes that pattern and subtracts the offset before comparing
the second load to see if it is consecutive.

The codegen change in the new test case improves from:

vmovsd 32(%rdi), %xmm0
vmovsd 48(%rdi), %xmm1
vmovhpd 56(%rdi), %xmm1, %xmm1
vmovhpd 40(%rdi), %xmm0, %xmm0
vinsertf128 $1, %xmm1, %ymm0, %ymm0

To:

vmovups 32(%rdi), %ymm0

An existing test case is also improved from:

vmovsd (%rdi), %xmm0
vmovsd 16(%rdi), %xmm1
vmovsd 24(%rdi), %xmm2
vunpcklpd %xmm2, %xmm0, %xmm0 ## xmm0 = xmm0[0],xmm2[0]
vmovhpd 8(%rdi), %xmm1, %xmm3

To:

vmovsd (%rdi), %xmm0
vmovsd 16(%rdi), %xmm1
vmovhpd 24(%rdi), %xmm0, %xmm0
vmovhpd 8(%rdi), %xmm1, %xmm1

This patch fixes PR21771 ( http://llvm.org/bugs/show_bug.cgi?id=21771 ).

Differential Revision: http://reviews.llvm.org/D6642

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224379 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoFix a bug in llvm-objdump’s -private-headers for the LC_VERSION_MIN_IPHONEOS
Kevin Enderby [Tue, 16 Dec 2014 21:48:27 +0000 (21:48 +0000)]
Fix a bug in llvm-objdump’s -private-headers for the LC_VERSION_MIN_IPHONEOS
load command not getting printed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224376 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[Hexagon] Adding tstbit/bitclr/bitset instructions.
Colin LeMahieu [Tue, 16 Dec 2014 21:28:58 +0000 (21:28 +0000)]
[Hexagon] Adding tstbit/bitclr/bitset instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224374 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[sanitizer] prevent function call merging for sanitizer-coverage callbacks
Kostya Serebryany [Tue, 16 Dec 2014 21:24:15 +0000 (21:24 +0000)]
[sanitizer] prevent function call merging for sanitizer-coverage callbacks

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224372 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoFix another use of PRIx32 that should have been PRIx64.
Kevin Enderby [Tue, 16 Dec 2014 21:00:25 +0000 (21:00 +0000)]
Fix another use of PRIx32 that should have been PRIx64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224368 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[Hexagon] Adding bit count and twiddling instructions.
Colin LeMahieu [Tue, 16 Dec 2014 20:57:56 +0000 (20:57 +0000)]
[Hexagon] Adding bit count and twiddling instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224367 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[Hexagon] Adding asr/lsr/asl reg/imm, asl with saturation, asr with rounding. Double...
Colin LeMahieu [Tue, 16 Dec 2014 20:40:23 +0000 (20:40 +0000)]
[Hexagon] Adding asr/lsr/asl reg/imm, asl with saturation, asr with rounding.  Doubleword abs/neg/not.  Interleave and deinterleave instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224365 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[dsymutil] Pass the verbosity flag down to the processing. NFC for now.
Frederic Riss [Tue, 16 Dec 2014 20:22:11 +0000 (20:22 +0000)]
[dsymutil] Pass the verbosity flag down to the processing. NFC for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224361 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[dsymutil] Avoid calling getStringTableData() for each symbol. NFC.
Frederic Riss [Tue, 16 Dec 2014 20:21:34 +0000 (20:21 +0000)]
[dsymutil] Avoid calling getStringTableData() for each symbol. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224360 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agox86-32: PUSHF/POPF use/def EFLAGS
JF Bastien [Tue, 16 Dec 2014 20:15:45 +0000 (20:15 +0000)]
x86-32: PUSHF/POPF use/def EFLAGS

Summary: As a side-quest for D6629 jvoung pointed out that I should use -verify-machineinstrs and this found a bug in x86-32's handling of EFLAGS for PUSHF/POPF. This patch fixes the use/def, and adds -verify-machineinstrs to all x86 tests which contain 'EFLAGS'. One exception: this patch leaves inline-asm-fpstack.ll as-is because it fails -verify-machineinstrs in a way unrelated to EFLAGS. This patch also modifies cmpxchg-clobber-flags.ll along the lines of what D6629 already does by also testing i386.

Test Plan: ninja check

Reviewers: t.p.northover, jvoung

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D6687

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224359 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoUse CastInst::castIsValid to simplify the verifier.
Rafael Espindola [Tue, 16 Dec 2014 19:29:29 +0000 (19:29 +0000)]
Use CastInst::castIsValid to simplify the verifier.

Also delete a dead member variable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224356 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoNVPTX: Remove duplicate of AsmPrinter::lowerConstant
Matt Arsenault [Tue, 16 Dec 2014 19:16:17 +0000 (19:16 +0000)]
NVPTX: Remove duplicate of AsmPrinter::lowerConstant

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224355 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoMove lowerConstant to AsmPrinter
Matt Arsenault [Tue, 16 Dec 2014 19:16:14 +0000 (19:16 +0000)]
Move lowerConstant to AsmPrinter

This was a static function before, and NVPTX duplicated it
because it wasn't exposed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224354 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[CodeGenPrepare] Move sign/zero extensions near loads using type promotion.
Quentin Colombet [Tue, 16 Dec 2014 19:09:03 +0000 (19:09 +0000)]
[CodeGenPrepare] Move sign/zero extensions near loads using type promotion.

This patch extends the optimization in CodeGenPrepare that moves a sign/zero
extension near a load when the target can combine them. The optimization may
promote any operations between the extension and the load to make that possible.

Although this optimization may be beneficial for all targets, in particular
AArch64, this is enabled for X86 only as I have not benchmarked it for other
targets yet.

** Context **

Most targets feature extended loads, i.e., loads that perform a zero or sign
extension for free. In that context it is interesting to expose such pattern in
CodeGenPrepare so that the instruction selection pass can form such loads.
Sometimes, this pattern is blocked because of instructions between the load and
the extension. When those instructions are promotable to the extended type, we
can expose this pattern.

** Motivating Example **

Let us consider an example:
define void @foo(i8* %addr1, i32* %addr2, i8 %a, i32 %b) {
  %ld = load i8* %addr1
  %zextld = zext i8 %ld to i32
  %ld2 = load i32* %addr2
  %add = add nsw i32 %ld2, %zextld
  %sextadd = sext i32 %add to i64
  %zexta = zext i8 %a to i32
  %addza = add nsw i32 %zexta, %zextld
  %sextaddza = sext i32 %addza to i64
  %addb = add nsw i32 %b, %zextld
  %sextaddb = sext i32 %addb to i64
  call void @dummy(i64 %sextadd, i64 %sextaddza, i64 %sextaddb)
  ret void
}

As it is, this IR generates the following assembly on x86_64:
[...]
  movzbl  (%rdi), %eax   # zero-extended load
  movl  (%rsi), %es      # plain load
  addl  %eax, %esi       # 32-bit add
  movslq  %esi, %rdi     # sign extend the result of add
  movzbl  %dl, %edx      # zero extend the first argument
  addl  %eax, %edx       # 32-bit add
  movslq  %edx, %rsi     # sign extend the result of add
  addl  %eax, %ecx       # 32-bit add
  movslq  %ecx, %rdx     # sign extend the result of add
[...]
The throughput of this sequence is 7.45 cycles on Ivy Bridge according to IACA.

Now, by promoting the additions to form more extended loads we would generate:
[...]
  movzbl  (%rdi), %eax   # zero-extended load
  movslq  (%rsi), %rdi   # sign-extended load
  addq  %rax, %rdi       # 64-bit add
  movzbl  %dl, %esi      # zero extend the first argument
  addq  %rax, %rsi       # 64-bit add
  movslq  %ecx, %rdx     # sign extend the second argument
  addq  %rax, %rdx       # 64-bit add
[...]
The throughput of this sequence is 6.15 cycles on Ivy Bridge according to IACA.

This kind of sequences happen a lot on code using 32-bit indexes on 64-bit
architectures.

Note: The throughput numbers are similar on Sandy Bridge and Haswell.

** Proposed Solution **

To avoid the penalty of all these sign/zero extensions, we merge them in the
loads at the beginning of the chain of computation by promoting all the chain of
computation on the extended type. The promotion is done if and only if we do not
introduce new extensions, i.e., if we do not degrade the code quality.
To achieve this, we extend the existing “move ext to load” optimization with the
promotion mechanism introduced to match larger patterns for addressing mode
(r200947).
The idea of this extension is to perform the following transformation:
ext(promotableInst1(...(promotableInstN(load))))
=>
promotedInst1(...(promotedInstN(ext(load))))

The promotion mechanism in that optimization is enabled by a new TargetLowering
switch, which is off by default. In other words, by default, the optimization
performs the “move ext to load” optimization as it was before this patch.

** Performance **

Configuration: x86_64: Ivy Bridge fixed at 2900MHz running OS X 10.10.
Tested Optimization Levels: O3/Os
Tests: llvm-testsuite + externals.
Results:
- No regression beside noise.
- Improvements:
CINT2006/473.astar:  ~2%
Benchmarks/PAQ8p: ~2%
Misc/perlin: ~3%

The results are consistent for both O3 and Os.

<rdar://problem/18310086>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224351 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoFix the arm build bots for a test that was added. A printing routine was incorrectly...
Kevin Enderby [Tue, 16 Dec 2014 18:58:11 +0000 (18:58 +0000)]
Fix the arm build bots for a test that was added.  A printing routine was incorrectly using PRIx32
when it should have been using PRIx64 for the value that was passed as uint64_t .

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224350 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[AVX512] Enable integer arithmetic lowering for AVX512BW/VL subsets.
Robert Khasanov [Tue, 16 Dec 2014 18:24:07 +0000 (18:24 +0000)]
[AVX512] Enable integer arithmetic lowering for AVX512BW/VL subsets.
Added lowering tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224349 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoOn behalf of Matthew Wahab:
Evgeny Astigeevich [Tue, 16 Dec 2014 18:16:17 +0000 (18:16 +0000)]
On behalf of Matthew Wahab:

An instruction alias defined with InstAlias and an optional operand in the
middle of the AsmString field, "..${a} <operands>", would get the final
"}" printed in the instruction disassembly. This wouldn't happen if the optional
operand appeared as the last item in the AsmString which is how the current
backends avoided the problem.

There don't appear to be any tests for this part of Tablegen but it passes the
pre-commit tests. Manually tested the change by enabling the generic alias
printer in the ARM backend and checking the output.

Differential Revision: http://reviews.llvm.org/D6529

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224348 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[MC] Reset the MCInst in the matcher function before adding opcode/operands.
Ahmed Bougacha [Tue, 16 Dec 2014 18:05:28 +0000 (18:05 +0000)]
[MC] Reset the MCInst in the matcher function before adding opcode/operands.

On X86, the Intel asm parser tries to match all memory operand sizes when
none is explicitly specified.  For LEA, which doesn't really have a memory
operand (just a pointer one), this results in multiple successful matches,
one for each memory size.  There's no error because it's same opcode, so
really, it's just one match.  However, the tablegen'd matcher function
adds opcode/operands to the passed MCInst, and this results in multiple
duplicated operands.

This commit clears the MCInst in the tablegen'd matcher function.
We sometimes clear it when the match failed, so there's no expectation of
keeping the previous content anyway.

Differential Revision: http://reviews.llvm.org/D6670

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224347 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[Hexagon] Adding absolute value, and negate with saturation
Colin LeMahieu [Tue, 16 Dec 2014 17:44:49 +0000 (17:44 +0000)]
[Hexagon] Adding absolute value, and negate with saturation

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224346 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agocombine consecutive subvector 16-byte loads into one 32-byte load
Sanjay Patel [Tue, 16 Dec 2014 16:30:01 +0000 (16:30 +0000)]
combine consecutive subvector 16-byte loads into one 32-byte load

This is a fix for PR21709 ( http://llvm.org/bugs/show_bug.cgi?id=21709 ).
When we have 2 consecutive 16-byte loads that are merged into one 32-byte vector,
we can use a single 32-byte load instead.
But we don't do this for SandyBridge / IvyBridge because they have slower 32-byte memops.
We also don't bother using 32-byte *integer* loads on a machine that only has AVX1 (btver2)
because those operands would have to be split in half anyway since there is no support for
32-byte integer math ops.

Differential Revision: http://reviews.llvm.org/D6492

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224344 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[Hexagon] Adding saturate and swizzle instructions.
Colin LeMahieu [Tue, 16 Dec 2014 16:27:17 +0000 (16:27 +0000)]
[Hexagon] Adding saturate and swizzle instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224343 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[AVX512] Add a comment for avx512_broadcast_pat multiclass
Robert Khasanov [Tue, 16 Dec 2014 16:12:11 +0000 (16:12 +0000)]
[AVX512] Add a comment for avx512_broadcast_pat multiclass

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224341 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[Hexagon] Removing old multiply defs and updating references to new versions.
Colin LeMahieu [Tue, 16 Dec 2014 16:10:01 +0000 (16:10 +0000)]
[Hexagon] Removing old multiply defs and updating references to new versions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224340 91177308-0d34-0410-b5e6-96231b3b80d8