opencl/llvm.git
7 years agoRevert "Follow-up to r205973: change the return type to const MDNode*."
Adrian Prantl [Thu, 10 Apr 2014 18:37:53 +0000 (18:37 +0000)]
Revert "Follow-up to r205973: change the return type to const MDNode*."

This reverts commit r205974, it turns out that this wasn't such a great idea
after all. Using DIVariable as return value is self-documenting and marginally
more type safe.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205979 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFollow-up to r205973: change the return type to const MDNode*.
Adrian Prantl [Thu, 10 Apr 2014 17:50:30 +0000 (17:50 +0000)]
Follow-up to r205973: change the return type to const MDNode*.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205974 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoDebug info: Factor the retrieving of the DIVariable from a MachineInstr
Adrian Prantl [Thu, 10 Apr 2014 17:39:48 +0000 (17:39 +0000)]
Debug info: Factor the retrieving of the DIVariable from a MachineInstr
into a function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205973 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAddLLVM: Mute the prefix "lib" in SHARED on win32.
NAKAMURA Takumi [Thu, 10 Apr 2014 15:47:04 +0000 (15:47 +0000)]
AddLLVM: Mute the prefix "lib" in SHARED on win32.

  - LLVMSupport.dll
  - libLLVMSupport.dll.a

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205969 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[mips] NotMips64 predicate is really a test for 32-bit GPR's.
Daniel Sanders [Thu, 10 Apr 2014 15:00:28 +0000 (15:00 +0000)]
[mips] NotMips64 predicate is really a test for 32-bit GPR's.

Summary:
Similarly, the HasMips64 on the 64-bit move InstAlias is a test for 64-bit
GPR's.

No functional change.

Reviewers: matheusalmeida

Reviewed By: matheusalmeida

Differential Revision: http://reviews.llvm.org/D3263

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205968 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoReapply "SLPVectorizer: Ignore users that are insertelements we can reschedule them"
Arnold Schwaighofer [Thu, 10 Apr 2014 13:41:35 +0000 (13:41 +0000)]
Reapply "SLPVectorizer: Ignore users that are insertelements we can reschedule them"

This commit reapplies 205018. After 205855 we should correctly vectorize
intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205965 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[mips] Switch the MIPS-III and MIPS-IV assembler tests to use -mcpu=mips4.
Daniel Sanders [Thu, 10 Apr 2014 13:16:49 +0000 (13:16 +0000)]
[mips] Switch the MIPS-III and MIPS-IV assembler tests to use -mcpu=mips4.

Summary:
It is now the smallest superset for these ISA's.

FeatureMips4 now contains FeatureFPIdx since [ls][dw]xc1 were added in MIPS-IV.
Made the FPIdx feature bit lowercase so that it can be used in the -mattr option.

Depends on D3274

Reviewers: matheusalmeida

Reviewed By: matheusalmeida

Differential Revision: http://reviews.llvm.org/D3275

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205964 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoARM64/*/LLVMBuild.txt: Prune redundant deps.
NAKAMURA Takumi [Thu, 10 Apr 2014 12:46:13 +0000 (12:46 +0000)]
ARM64/*/LLVMBuild.txt: Prune redundant deps.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205963 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoLLVMBuild.txt: Add missing dependencies.
NAKAMURA Takumi [Thu, 10 Apr 2014 11:16:47 +0000 (11:16 +0000)]
LLVMBuild.txt: Add missing dependencies.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205962 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoLLVMBuild.txt: Reformat.
NAKAMURA Takumi [Thu, 10 Apr 2014 11:16:17 +0000 (11:16 +0000)]
LLVMBuild.txt: Reformat.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205961 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoSaveAndRestore: fix coding style and Doxygenify comments
Dmitri Gribenko [Thu, 10 Apr 2014 09:44:32 +0000 (09:44 +0000)]
SaveAndRestore: fix coding style and Doxygenify comments

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205959 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoYAMLIO: Allow scalars to dictate quotation rules
David Majnemer [Thu, 10 Apr 2014 07:37:33 +0000 (07:37 +0000)]
YAMLIO: Allow scalars to dictate quotation rules

Introduce ScalarTraits::mustQuote which determines whether or not a
StringRef needs quoting before it is acceptable to output.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205955 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoUse range-based for loops. No functionality change.
Simon Atanasyan [Thu, 10 Apr 2014 06:02:49 +0000 (06:02 +0000)]
Use range-based for loops. No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205953 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix abuse of StringRef on ARM64SysReg::MRSMapper::toString(Val, Valid).
NAKAMURA Takumi [Thu, 10 Apr 2014 03:05:59 +0000 (03:05 +0000)]
Fix abuse of StringRef on ARM64SysReg::MRSMapper::toString(Val, Valid).

FIXME: Could we use SmallString here?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205950 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoARM64: add an explicit cast to silence a silly warning
Saleem Abdulrasool [Thu, 10 Apr 2014 02:48:10 +0000 (02:48 +0000)]
ARM64: add an explicit cast to silence a silly warning

GCC 4.8 complains with:
  warning: enumeral and non-enumeral type in conditional expression

Although this is silly and harmless in this case, add an explicit cast to
silence the warning.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205949 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM64] Fix immediate cost calculation for types larger than i64.
Juergen Ributzka [Thu, 10 Apr 2014 01:36:59 +0000 (01:36 +0000)]
[ARM64] Fix immediate cost calculation for types larger than i64.

The immediate cost calculation code was hitting an assertion in the included
test case, because APInt was still internally 128-bits. Truncating it to 64-bits
fixed the issue.

Fixes <rdar://problem/16572521>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205947 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRevert "For the ARM integrated assembler add checking of the alignments on vld/vst...
Reid Kleckner [Thu, 10 Apr 2014 00:52:14 +0000 (00:52 +0000)]
Revert "For the ARM integrated assembler add checking of the alignments on vld/vst instructions.  And report errors for alignments that are not supported."

It doesn't build with MSVC 2012, because MSVC doesn't allow union
members that have non-trivial default constructors.  This change added
'SMLoc AlignmentLoc' to MemoryOp, which made MemoryOp's default ctor
non-trivial.

This reverts commit r205930.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205944 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix to support properly cleaning up failed address sinking against constants
Jim Grosbach [Thu, 10 Apr 2014 00:27:45 +0000 (00:27 +0000)]
Fix to support properly cleaning up failed address sinking against constants

As it turns out the source of the sunkaddr can be a constant, in which case
there is not an instruction to delete, causing the cleanup code introduced in
r204833 to crash. This patch adds a dynamic check to ensure the deleted value is
in fact an instruction and not a constant.

Patch by Louis Gerbarg <lgg@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205941 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoX86: Tighten up test.
Jim Grosbach [Thu, 10 Apr 2014 00:27:43 +0000 (00:27 +0000)]
X86: Tighten up test.

llc CPU autodection bites again. Speculative fix for bot failures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205940 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd support for load folding of avx1 logical instructions
Jim Grosbach [Wed, 9 Apr 2014 23:39:25 +0000 (23:39 +0000)]
Add support for load folding of avx1 logical instructions

AVX supports logical operations using an operand from memory. Unfortunately
because integer operations were not added until AVX2 the AVX1 logical
operation's types were preventing the isel from folding the loads. In a limited
number of cases the peephole optimizer would fold the loads, but most were
missed. This patch adds explicit patterns with appropriate casts in order for
these loads to be folded.

The included test cases run on reduced examples and disable the peephole
optimizer to ensure the folds are being pattern matched.

Patch by Louis Gerbarg <lgg@apple.com>

rdar://16355124

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205938 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoSelectionDAG: Don't constant fold target-specific nodes.
Jim Grosbach [Wed, 9 Apr 2014 23:28:11 +0000 (23:28 +0000)]
SelectionDAG: Don't constant fold target-specific nodes.

FoldConstantArithmetic() only knows how to deal with a few target independent
ISD opcodes. Bail early if it sees a target-specific ISD node. These node do
funny things with operand types which may break the assumptions of the code
that follows, and there's no actual folding that can be done anyway. For example,
non-constant 256 bit vector shifts on X86 have a shift-amount operand that's a
128-bit v4i32 vector regardless of what the first operand type is and that breaks
the assumption that the operand types must match.

rdar://16530923

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205937 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFor the ARM integrated assembler add checking of the
Kevin Enderby [Wed, 9 Apr 2014 21:32:59 +0000 (21:32 +0000)]
For the ARM integrated assembler add checking of the
alignments on vld/vst instructions.  And report errors for
alignments that are not supported.

While this is a large diff and an big test case, the changes
are very straight forward.  But pretty much had to touch
all vld/vst instructions changing the addrmode to one of the
new ones that where added will do the proper checking for
the specific instruction.

rdar://11312406

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205930 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AArch64] Implement the isZExtFree APIs.
Chad Rosier [Wed, 9 Apr 2014 20:51:21 +0000 (20:51 +0000)]
[AArch64] Implement the isZExtFree APIs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205926 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AArch64] Implement the isTruncateFree API.
Chad Rosier [Wed, 9 Apr 2014 20:43:40 +0000 (20:43 +0000)]
[AArch64] Implement the isTruncateFree API.

In AArch64 i64 to i32 truncate operation is a subregister access.

This allows more opportunities for LSR optmization to eliminate
variables of different types (i32 and i64).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205925 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[DAGCombiner] DAG combine does not know how to combine indexed loads with
Quentin Colombet [Wed, 9 Apr 2014 20:03:05 +0000 (20:03 +0000)]
[DAGCombiner] DAG combine does not know how to combine indexed loads with
sign/zero/any extensions. However a few places were not checking properly the
property of the load and were turning an indexed load into a regular extended
load. Therefore the indexed value was lost during the process and this was
triggering an assertion.

<rdar://problem/16389332>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205923 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoSimple fix for build failures resulting from r205867.
Bob Wilson [Wed, 9 Apr 2014 18:34:45 +0000 (18:34 +0000)]
Simple fix for build failures resulting from r205867.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205918 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRevert "Revert "YAMLIO: Encode ambiguous hex strings explicitly""
David Majnemer [Wed, 9 Apr 2014 17:04:27 +0000 (17:04 +0000)]
Revert "Revert "YAMLIO: Encode ambiguous hex strings explicitly""

Don't quote octal compatible strings if they are only two wide, they
aren't ambiguous.

This reverts commit r205857 which reverted r205857.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205914 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoobj2yaml: Don't crash if the characteristics field is zero
David Majnemer [Wed, 9 Apr 2014 16:38:15 +0000 (16:38 +0000)]
obj2yaml: Don't crash if the characteristics field is zero

obj2yaml would fail when seeing a Weak External auxiliary record with a
characteristics field holding zero instead of one of
IMAGE_WEAK_EXTERN_SEARCH_NOLIBRARY, IMAGE_WEAK_EXTERN_SEARCH_NOLIBRARY,
or IMAGE_WEAK_EXTERN_SEARCH_NOLIBRARY.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205911 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[NVPTX] Add preliminary intrinsics and codegen support for textures/surfaces
Justin Holewinski [Wed, 9 Apr 2014 15:39:15 +0000 (15:39 +0000)]
[NVPTX] Add preliminary intrinsics and codegen support for textures/surfaces

This commit adds intrinsics and codegen support for the surface read/write and texture read instructions that take an explicit sampler parameter. Codegen operates on image handles at the PTX level, but falls back to direct replacement of handles with kernel arguments if image handles are not enabled. Note that image handles are explicitly disabled for all target architectures in this change (to be enabled later).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205907 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[NVPTX] Add support for addrspacecast in global variable initializers, including...
Justin Holewinski [Wed, 9 Apr 2014 15:39:11 +0000 (15:39 +0000)]
[NVPTX] Add support for addrspacecast in global variable initializers, including emitting generic() when casting to address space 0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205906 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[NVPTX] Add query support for read-write images and managed variables
Justin Holewinski [Wed, 9 Apr 2014 15:38:52 +0000 (15:38 +0000)]
[NVPTX] Add query support for read-write images and managed variables

This also fixes a bug in the annotation cache where the cache will not be cleared between modules if multiple modules are compiled in the same process.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205905 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix some doc and comment typos
Alp Toker [Wed, 9 Apr 2014 14:47:27 +0000 (14:47 +0000)]
Fix some doc and comment typos

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205899 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM64] Change SYS without a register to an alias to make disassembling more consistant.
Bradley Smith [Wed, 9 Apr 2014 14:44:58 +0000 (14:44 +0000)]
[ARM64] Change SYS without a register to an alias to make disassembling more consistant.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205898 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM64] Correctly disassemble ISB operand as ISB not DBarrier.
Bradley Smith [Wed, 9 Apr 2014 14:44:54 +0000 (14:44 +0000)]
[ARM64] Correctly disassemble ISB operand as ISB not DBarrier.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205897 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM64] Properly support both apple and standard syntax for FMOV
Bradley Smith [Wed, 9 Apr 2014 14:44:49 +0000 (14:44 +0000)]
[ARM64] Properly support both apple and standard syntax for FMOV

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205896 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM64] Flag setting logical/add/sub immediate instructions don't use SP.
Bradley Smith [Wed, 9 Apr 2014 14:44:44 +0000 (14:44 +0000)]
[ARM64] Flag setting logical/add/sub immediate instructions don't use SP.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205895 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM64] Conditional branches must always print their condition code, even AL.
Bradley Smith [Wed, 9 Apr 2014 14:44:39 +0000 (14:44 +0000)]
[ARM64] Conditional branches must always print their condition code, even AL.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205894 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM64] Fix disassembly logic for extended loads/stores with 32-bit registers.
Bradley Smith [Wed, 9 Apr 2014 14:44:36 +0000 (14:44 +0000)]
[ARM64] Fix disassembly logic for extended loads/stores with 32-bit registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205893 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM64] When printing a pre-indexed address with #0, the ', #0' is not optional.
Bradley Smith [Wed, 9 Apr 2014 14:44:31 +0000 (14:44 +0000)]
[ARM64] When printing a pre-indexed address with #0, the ', #0' is not optional.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205892 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM64] Add missing shifted register MVN alias to ORN
Bradley Smith [Wed, 9 Apr 2014 14:44:26 +0000 (14:44 +0000)]
[ARM64] Add missing shifted register MVN alias to ORN

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205891 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM64] SXTW/UXTW are only valid aliases for 32-bit operations.
Bradley Smith [Wed, 9 Apr 2014 14:44:22 +0000 (14:44 +0000)]
[ARM64] SXTW/UXTW are only valid aliases for 32-bit operations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205890 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM64] Fix canonicalisation of MOVs. MOV is too complex to be modelled by a dumb...
Bradley Smith [Wed, 9 Apr 2014 14:44:18 +0000 (14:44 +0000)]
[ARM64] Fix canonicalisation of MOVs. MOV is too complex to be modelled by a dumb alias.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205889 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM64] Fixup ADR/ADRP parsing such that they accept immediates and all labels types
Bradley Smith [Wed, 9 Apr 2014 14:44:12 +0000 (14:44 +0000)]
[ARM64] Fixup ADR/ADRP parsing such that they accept immediates and all labels types

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205888 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM64] Ensure sp is decoded as SP, not XZR in LD1 instructions.
Bradley Smith [Wed, 9 Apr 2014 14:44:07 +0000 (14:44 +0000)]
[ARM64] Ensure sp is decoded as SP, not XZR in LD1 instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205887 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM64] Tighten up the special casing in emitting arithmetic extends. UXTW should...
Bradley Smith [Wed, 9 Apr 2014 14:44:03 +0000 (14:44 +0000)]
[ARM64] Tighten up the special casing in emitting arithmetic extends. UXTW should only be translated when the instruction uses WSP, not SP. Vice versa for UXTX and 64-bit instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205886 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM64] Rename LR to the UAL-compliant 'X30'.
Bradley Smith [Wed, 9 Apr 2014 14:43:59 +0000 (14:43 +0000)]
[ARM64] Rename LR to the UAL-compliant 'X30'.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205885 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM64] Rename FP to the UAL-compliant 'X29'.
Bradley Smith [Wed, 9 Apr 2014 14:43:50 +0000 (14:43 +0000)]
[ARM64] Rename FP to the UAL-compliant 'X29'.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205884 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM64] Add a PostEncoderMethod to FCMP - the Rm field should canonically be zero...
Bradley Smith [Wed, 9 Apr 2014 14:43:40 +0000 (14:43 +0000)]
[ARM64] Add a PostEncoderMethod to FCMP - the Rm field should canonically be zero but should be decoded/disassembled with any value.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205883 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM64] SCVTF and FCVTZS/U are undefined if scale<5> == 0.
Bradley Smith [Wed, 9 Apr 2014 14:43:35 +0000 (14:43 +0000)]
[ARM64] SCVTF and FCVTZS/U are undefined if scale<5> == 0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205882 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM64] EXT and EXTR instructions on v8i8 and W regs respectively must have the top...
Bradley Smith [Wed, 9 Apr 2014 14:43:31 +0000 (14:43 +0000)]
[ARM64] EXT and EXTR instructions on v8i8 and W regs respectively must have the top bit of their immediate clear.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205881 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM64] Scaled fixed-point FCVTZSs should also have bit 29 set to zero.
Bradley Smith [Wed, 9 Apr 2014 14:43:27 +0000 (14:43 +0000)]
[ARM64] Scaled fixed-point FCVTZSs should also have bit 29 set to zero.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205880 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM64] UBFM/BFM is undefined on w registers when imms<5> or immr<5> is 1.
Bradley Smith [Wed, 9 Apr 2014 14:43:24 +0000 (14:43 +0000)]
[ARM64] UBFM/BFM is undefined on w registers when imms<5> or immr<5> is 1.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205879 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM64] Floating point to fixed point scaled conversions are only available on fcvtzs...
Bradley Smith [Wed, 9 Apr 2014 14:43:20 +0000 (14:43 +0000)]
[ARM64] Floating point to fixed point scaled conversions are only available on fcvtzs and fcvtzu.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205878 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM64] Port over the PostEncoderMethod fix for SMULH/UMULH from AArch64.
Bradley Smith [Wed, 9 Apr 2014 14:43:15 +0000 (14:43 +0000)]
[ARM64] Port over the PostEncoderMethod fix for SMULH/UMULH from AArch64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205877 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM64] Add missing tlbi operands and error for extra/missing register on tlbi aliases.
Bradley Smith [Wed, 9 Apr 2014 14:43:11 +0000 (14:43 +0000)]
[ARM64] Add missing tlbi operands and error for extra/missing register on tlbi aliases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205876 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM64] Rework system register parsing to overcome SPSel clash in MSR variants.
Bradley Smith [Wed, 9 Apr 2014 14:43:06 +0000 (14:43 +0000)]
[ARM64] Rework system register parsing to overcome SPSel clash in MSR variants.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205875 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM64] Port over the PostEncoderMethod from AArch64 for exclusive loads and stores...
Bradley Smith [Wed, 9 Apr 2014 14:43:01 +0000 (14:43 +0000)]
[ARM64] Port over the PostEncoderMethod from AArch64 for exclusive loads and stores, so the unused register fields are set to all-ones canonically but are recognised with any value.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205874 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM64] Use PStateMapper to ensure that MSRcpsr operands are validated during disasse...
Bradley Smith [Wed, 9 Apr 2014 14:42:56 +0000 (14:42 +0000)]
[ARM64] Use PStateMapper to ensure that MSRcpsr operands are validated during disassembly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205873 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM64] Remove PrefetchOp and use ARM64PRFM instead.
Bradley Smith [Wed, 9 Apr 2014 14:42:53 +0000 (14:42 +0000)]
[ARM64] Remove PrefetchOp and use ARM64PRFM instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205872 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM64] Add WZR to isGPR32Register, since every use needs to check for this anyway.
Bradley Smith [Wed, 9 Apr 2014 14:42:49 +0000 (14:42 +0000)]
[ARM64] Add WZR to isGPR32Register, since every use needs to check for this anyway.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205871 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM64] Remove ARM64SYS.
Bradley Smith [Wed, 9 Apr 2014 14:42:45 +0000 (14:42 +0000)]
[ARM64] Remove ARM64SYS.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205870 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM64] Move CPSRField and DBarrier operands over to AArch64-style disassembly and...
Bradley Smith [Wed, 9 Apr 2014 14:42:42 +0000 (14:42 +0000)]
[ARM64] Move CPSRField and DBarrier operands over to AArch64-style disassembly and assembly. This removes the last users of namespace ARM64SYS.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205869 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM64] Switch the decoder, disassembler, instprinter and asmparser over to using...
Bradley Smith [Wed, 9 Apr 2014 14:42:36 +0000 (14:42 +0000)]
[ARM64] Switch the decoder, disassembler, instprinter and asmparser over to using AArch64-style system registers, and fix up test failures discovered in the process.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205868 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM64] Move ARM64BaseInfo.{cpp,h} into a Utils/ subdirectory, a la AArch64. These...
Bradley Smith [Wed, 9 Apr 2014 14:42:27 +0000 (14:42 +0000)]
[ARM64] Move ARM64BaseInfo.{cpp,h} into a Utils/ subdirectory, a la AArch64. These files are required in the decoder, disassembler and parser, and a layering violation was imminent.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205867 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM64] Copy the named immediate operand mapping logic and enums from AArch64. AArch6...
Bradley Smith [Wed, 9 Apr 2014 14:42:16 +0000 (14:42 +0000)]
[ARM64] Copy the named immediate operand mapping logic and enums from AArch64. AArch64's named immediate mapping and parsing is much more advanced than ARM64's. No functionality change - they're currently living side by side while I switch uses over.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205866 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM64] Shifted register ALU ops are reserved if sf=0 and imm6<5>=1, and also (for...
Bradley Smith [Wed, 9 Apr 2014 14:42:11 +0000 (14:42 +0000)]
[ARM64] Shifted register ALU ops are reserved if sf=0 and imm6<5>=1, and also (for add/sub only) if shift=11.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205865 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM64] Add support for NV condition code (exists only for valid assembly/disassembly...
Bradley Smith [Wed, 9 Apr 2014 14:42:07 +0000 (14:42 +0000)]
[ARM64] Add support for NV condition code (exists only for valid assembly/disassembly, equivilant to AL)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205864 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM64] Add missing 1Q -> 1q vector kind alias
Bradley Smith [Wed, 9 Apr 2014 14:42:01 +0000 (14:42 +0000)]
[ARM64] Add missing 1Q -> 1q vector kind alias

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205863 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM64] Add parsing for vector lists such as {v0.8b-v3.8b}
Bradley Smith [Wed, 9 Apr 2014 14:41:58 +0000 (14:41 +0000)]
[ARM64] Add parsing for vector lists such as {v0.8b-v3.8b}

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205862 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM64] Correctly alias LSL to UXTW for 32bit instruction variants, rather than UXTX
Bradley Smith [Wed, 9 Apr 2014 14:41:53 +0000 (14:41 +0000)]
[ARM64] Correctly alias LSL to UXTW for 32bit instruction variants, rather than UXTX

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205861 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM64] STRHro and STRBro were not being decoded at all.
Bradley Smith [Wed, 9 Apr 2014 14:41:49 +0000 (14:41 +0000)]
[ARM64] STRHro and STRBro were not being decoded at all.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205860 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM64] MOVK with sf=0 and hw<1>=1 is unallocated. Shift amount for ADD/SUB instructi...
Bradley Smith [Wed, 9 Apr 2014 14:41:45 +0000 (14:41 +0000)]
[ARM64] MOVK with sf=0 and hw<1>=1 is unallocated. Shift amount for ADD/SUB instructions is unallocated if shift > 4.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205859 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM64] Register-offset loads and stores with the 'option' field equal to 00x or...
Bradley Smith [Wed, 9 Apr 2014 14:41:38 +0000 (14:41 +0000)]
[ARM64] Register-offset loads and stores with the 'option' field equal to 00x or 10x are undefined.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205858 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRevert "YAMLIO: Encode ambiguous hex strings explicitly"
Filipe Cabecinhas [Wed, 9 Apr 2014 14:35:17 +0000 (14:35 +0000)]
Revert "YAMLIO: Encode ambiguous hex strings explicitly"

This reverts commit r205839.

It broke several tests in lld.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205857 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoSLPVectorizer: Only vectorize intrinsics whose operands are widened equally
Arnold Schwaighofer [Wed, 9 Apr 2014 14:20:47 +0000 (14:20 +0000)]
SLPVectorizer: Only vectorize intrinsics whose operands are widened equally

The vectorizer only knows how to vectorize intrinics by widening all operands by
the same factor.

Patch by Tyler Nowicki!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205855 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAVX-512: insert element to mask vector; store i1 data
Elena Demikhovsky [Wed, 9 Apr 2014 12:37:50 +0000 (12:37 +0000)]
AVX-512: insert element to mask vector; store i1 data

Implemented INSERT_VECTOR_ELT operation for v16i1 and v8i1 vectors;
Implemented "store" for i1 type

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205850 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd support for building LLVM on FreeBSD 9.2
Viktor Kutuzov [Wed, 9 Apr 2014 11:43:34 +0000 (11:43 +0000)]
Add support for building LLVM on FreeBSD 9.2

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205847 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRe-commit: [mips] abs.[ds], and neg.[ds] should be allowed regardless of -enable...
Daniel Sanders [Wed, 9 Apr 2014 09:56:43 +0000 (09:56 +0000)]
Re-commit: [mips] abs.[ds], and neg.[ds] should be allowed regardless of -enable-no-nans-fp-math

Summary:
They behave in accordance with the Has2008 and ABS2008 configuration bits of the processor which are used to select between the 1985 and 2008 versions of IEEE 754. In 1985 mode, these instructions are arithmetic (i.e. they raise invalid operation exceptions when given NaN), in 2008 mode they are non-arithmetic (i.e. they are copies).

nmadd.[ds], and nmsub.[ds] are still subject to -enable-no-nans-fp-math because the ISA spec does not explicitly state that they obey Has2008 and ABS2008.

Fixed the issue with the previous version of this patch (r205628). A pre-existing 'let Predicate =' statement was removing some predicates that were necessary for FP64 to behave correctly.

Reviewers: matheusalmeida

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D3274

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205844 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoYAMLIO: Encode ambiguous hex strings explicitly
David Majnemer [Wed, 9 Apr 2014 07:56:27 +0000 (07:56 +0000)]
YAMLIO: Encode ambiguous hex strings explicitly

YAMLIO would turn a BinaryRef into the string 0000000004000000.
However, the leading zero causes parsers to interpret it as being an
octal number instead of a hexadecimal one.

Instead, escape such strings as needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205839 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoDelinearize: Extend informationin -analyze output
Tobias Grosser [Wed, 9 Apr 2014 07:53:49 +0000 (07:53 +0000)]
Delinearize: Extend informationin -analyze output

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205838 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoR600/SI: Match not instruction.
Matt Arsenault [Wed, 9 Apr 2014 07:16:16 +0000 (07:16 +0000)]
R600/SI: Match not instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205837 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoARM64: scalarize v1i64 mul operation
Tim Northover [Wed, 9 Apr 2014 07:07:02 +0000 (07:07 +0000)]
ARM64: scalarize v1i64 mul operation

This is the second part of fixing PR19367.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205836 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoARM64: add pattern for <1 x i64> custom not node.
Tim Northover [Wed, 9 Apr 2014 06:55:39 +0000 (06:55 +0000)]
ARM64: add pattern for <1 x i64> custom not node.

This should fix PR19367.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205835 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoObject: add type names for ARM/COFF relocations
Saleem Abdulrasool [Wed, 9 Apr 2014 06:18:28 +0000 (06:18 +0000)]
Object: add type names for ARM/COFF relocations

Add type name mappings for the ARM COFF relocations.  This allows for objdump to
provide a more useful description of relocations in disassembly inline form.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205834 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoARM MC: 80 column
Saleem Abdulrasool [Wed, 9 Apr 2014 06:18:26 +0000 (06:18 +0000)]
ARM MC: 80 column

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205833 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoARM MC: sort source files in CMakeLists
Saleem Abdulrasool [Wed, 9 Apr 2014 06:18:23 +0000 (06:18 +0000)]
ARM MC: sort source files in CMakeLists

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205832 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[C++11] More 'nullptr' conversion or in some cases just using a boolean check instead...
Craig Topper [Wed, 9 Apr 2014 06:08:46 +0000 (06:08 +0000)]
[C++11] More 'nullptr' conversion or in some cases just using a boolean check instead of comparing to nullptr.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205831 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[C++11] Make use of 'nullptr' in TableGen library.
Craig Topper [Wed, 9 Apr 2014 04:50:04 +0000 (04:50 +0000)]
[C++11] Make use of 'nullptr' in TableGen library.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205830 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[C++11] Replace some comparisons with 'nullptr' with simple boolean checks to reduce...
Craig Topper [Wed, 9 Apr 2014 04:20:00 +0000 (04:20 +0000)]
[C++11] Replace some comparisons with 'nullptr' with simple boolean checks to reduce verbosity.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205829 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoWinCOFF: Emit common symbols as specified in the COFF spec
David Majnemer [Tue, 8 Apr 2014 22:33:40 +0000 (22:33 +0000)]
WinCOFF: Emit common symbols as specified in the COFF spec

Summary:
Local common symbols were properly inserted into the .bss section.
However, putting external common symbols in the .bss section would give
them a strong definition.

Instead, encode them as undefined, external symbols who's symbol value
is equivalent to their size.

Reviewers: Bigcheese, rafael, rnk

CC: llvm-commits
Differential Revision: http://reviews.llvm.org/D3324

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205811 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoBug 19348: Check for legal ExtLoad operation before folding
Matt Arsenault [Tue, 8 Apr 2014 21:40:37 +0000 (21:40 +0000)]
Bug 19348: Check for legal ExtLoad operation before folding

(aext (zextload x)) -> (aext (truncate (*extload x)))

Patch by Stanislav Mekhanoshin!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205805 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agodivide by the result of the gcd
Sebastian Pop [Tue, 8 Apr 2014 21:21:13 +0000 (21:21 +0000)]
divide by the result of the gcd

used to fail with 'Step should divide Start with no remainder.'

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205802 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agohandle special cases when findGCD returns 1
Sebastian Pop [Tue, 8 Apr 2014 21:21:10 +0000 (21:21 +0000)]
handle special cases when findGCD returns 1

used to fail with 'Step should divide Start with no remainder.'

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205801 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoin findGCD of multiply expr return the gcd
Sebastian Pop [Tue, 8 Apr 2014 21:21:05 +0000 (21:21 +0000)]
in findGCD of multiply expr return the gcd

we used to return 1 instead of the gcd

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205800 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[docs] VCS contains a record of authorship
Sean Silva [Tue, 8 Apr 2014 21:12:56 +0000 (21:12 +0000)]
[docs] VCS contains a record of authorship

No need to explicitly mention the author in the document.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205793 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[docs] Fix up some links to the preferred style.
Sean Silva [Tue, 8 Apr 2014 21:06:22 +0000 (21:06 +0000)]
[docs] Fix up some links to the preferred style.

:doc:`...` and :ref:`...` links help Sphinx keep track the dependencies
between documents and ensure that they are not pointing to nowhere.

Raw HTML links work just fine and are easier for people less familiar
with reST/Sphinx. They are easy to change over to the :doc:/:ref: style
after the fact so this is not a problem.

This commit doesn't fix all of them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205792 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Constant Hoisting][ARM64] Enable constant hoisting for ARM64.
Juergen Ributzka [Tue, 8 Apr 2014 20:39:59 +0000 (20:39 +0000)]
[Constant Hoisting][ARM64] Enable constant hoisting for ARM64.

This implements the target-hooks for ARM64 to enable constant hoisting.

This fixes <rdar://problem/14774662> and <rdar://problem/16381500>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205791 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRegAlloc: Account for a variable entry block frequency
Duncan P. N. Exon Smith [Tue, 8 Apr 2014 19:18:56 +0000 (19:18 +0000)]
RegAlloc: Account for a variable entry block frequency

Until r197284, the entry frequency was constant -- i.e., set to 2^14.
Although current ToT still has a constant entry frequency, since r197284
that has been an implementation detail (which is soon going to change).

  - r204690 made the wrong assumption for the CSRCost metric.  Adjust
    callee-saved register cost based on entry frequency.

  - r185393 made the wrong assumption (although it was valid at the
    time).  Update SpillPlacement.cpp::Threshold to be relative to the
    entry frequency.

Since ToT still has 2^14 entry frequency, this should have no observable
functionality change.

<rdar://problem/14292693>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205789 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[PowerPC] Don't return false from PPC::isVSLDOIShuffleMask
Hal Finkel [Tue, 8 Apr 2014 19:00:27 +0000 (19:00 +0000)]
[PowerPC] Don't return false from PPC::isVSLDOIShuffleMask

PPC::isVSLDOIShuffleMask should return -1, not false, when the shuffle
predicate should be false.

Noticed by inspection; no test case (yet).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205787 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix the ARM VLD3 (single 3-element structure to all lanes)
Kevin Enderby [Tue, 8 Apr 2014 18:00:52 +0000 (18:00 +0000)]
Fix the ARM VLD3 (single 3-element structure to all lanes)
size 16 double-spaced registers instruction printing.

This:
vld3.16 {d0[], d2[], d4[]}, [r4]!

was being printed as:

vld3.16 {d0[], d1[], d2[]}, [r4]!

rdar://16531387

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205779 91177308-0d34-0410-b5e6-96231b3b80d8