author | Gaurav Mitra <gaurav@ti.com> | |
Thu, 31 Jan 2019 19:47:04 +0000 (13:47 -0600) | ||
committer | Gaurav Mitra <gaurav@ti.com> | |
Thu, 31 Jan 2019 21:09:01 +0000 (15:09 -0600) | ||
commit | ed3f3bcf7bd62dbd3b32513fda36f60e1a188e19 | |
tree | b4a5b5c1db9f5408653c4f8daab647c0497cb0f6 | tree | snapshot (tar.xz tar.gz zip) |
parent | 23c7104cb23400d563858590231234a18152ef5e | commit | diff |
Errata Advisory fix for C6678, C6657, C6670: Read exception and data corruption
ERRATA ADVISORY 28 (C6678), 14 (C6657), 33 (C6670) OVERVIEW:
* C6678 Errata 28: Page 43 of http://www.ti.com/lit/er/sprz334h/sprz334h.pdf
* C6657 Errata 14: Page 24 of http://www.ti.com/lit/er/sprz381c/sprz381c.pdf
* C6670 Errata 33: Page 58 of http://www.ti.com/lit/er/sprz332f/sprz332f.pdf
* Summary: Under specific circumstances, a pre-fetch for a cacheable
data access (program prefetches are not affected) that bypasses L2
can result in a read exception and/or data corruption.
* Solution: Disable prefetch for MSMC SRAM for C6678, C6657 and C6670
OTHER:
* Update CoreSDK version
* Cleanup whitespace
(MCT-1114)
ERRATA ADVISORY 28 (C6678), 14 (C6657), 33 (C6670) OVERVIEW:
* C6678 Errata 28: Page 43 of http://www.ti.com/lit/er/sprz334h/sprz334h.pdf
* C6657 Errata 14: Page 24 of http://www.ti.com/lit/er/sprz381c/sprz381c.pdf
* C6670 Errata 33: Page 58 of http://www.ti.com/lit/er/sprz332f/sprz332f.pdf
* Summary: Under specific circumstances, a pre-fetch for a cacheable
data access (program prefetches are not affected) that bypasses L2
can result in a read exception and/or data corruption.
* Solution: Disable prefetch for MSMC SRAM for C6678, C6657 and C6670
OTHER:
* Update CoreSDK version
* Cleanup whitespace
(MCT-1114)