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raw | patch | inline | side by side (parent: 6890f08)
author | Vitaly Andrianov <vitalya@ti.com> | |
Fri, 5 Jun 2015 12:45:08 +0000 (08:45 -0400) | ||
committer | Vitaly Andrianov <vitalya@ti.com> | |
Fri, 5 Jun 2015 12:45:08 +0000 (08:45 -0400) |
Setting the fast-boot RBL entry point for ARM0 prevents RBL to perform a
normal boot sequence when kernel issues the reboot command. We need to
leave the CORE_N_BASE_ADDR for ARM0 unmodified to allow it to perform normal
RBL boot.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
normal boot sequence when kernel issues the reboot command. We need to
leave the CORE_N_BASE_ADDR for ARM0 unmodified to allow it to perform normal
RBL boot.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
sec/skern.c | patch | blob | history |
diff --git a/sec/skern.c b/sec/skern.c
index ea8466cc0de8fe132633b2eeeb18c676be3ebc54..b86d338d3a86a85a3a2992c7dad6bcea852f02fc 100644 (file)
--- a/sec/skern.c
+++ b/sec/skern.c
/* hard code the arch timer frquency now */
skernel_cpu_data.arch_timer_freq = freq;
- for (i = 0; i < ARM_CLUSTER_NUM_CPUS; i++) {
+ for (i = 1; i < ARM_CLUSTER_NUM_CPUS; i++) {
addr[i * 2] = (void*)_skern_123_init;
}