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raw | patch | inline | side by side (parent: 859fea1)
raw | patch | inline | side by side (parent: 859fea1)
author | Murali Karicheri <m-karicheri2@ti.com> | |
Thu, 31 Jan 2013 20:17:45 +0000 (15:17 -0500) | ||
committer | Murali Karicheri <m-karicheri2@ti.com> | |
Thu, 31 Jan 2013 22:15:31 +0000 (17:15 -0500) |
Enable l2 tag latency and enable VFP
Enable group0 for all interrupts in GIC
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Enable group0 for all interrupts in GIC
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
sec/skern.c | patch | blob | history | |
sec/skernel.S | patch | blob | history |
diff --git a/sec/skern.c b/sec/skern.c
index 2f3ffceedee13b0df5fd25ec0b1b98ec7b933d2d..b246e385e2ff673994308fe3c8f2a9642e5f08e9 100644 (file)
--- a/sec/skern.c
+++ b/sec/skern.c
return error;
}
+void a15_setup_l2_latency(void)
+{
+ asm volatile (
+ /* L2CTLR (w in ns 0) */
+ "mrc p15, 1, r0, c9, c0, 2\n"
+ /* DRS (2 S) <A1>Vslices: #2 */
+ "orr r0, r0, #(2 << 10)\n"
+ /* TRL (2 c) <A1>V Tag ram latency : 2 cycles */
+ "orr r0, r0, #(1 << 6)\n"
+ /* DRL (4 c) <A1>V Data Ram latency : 4cycles */
+ "orr r0, r0, #(3 << 0)\n"
+ "mcr p15, 1, r0, c9, c0, 2\n"
+ "isb\n"
+ "dsb\n"
+ :
+ :
+ : "cc", "r0", "memory"
+ );
+}
+
+void a15_setup_cp15(void)
+{
+ asm volatile (
+ /* enable VFP and NEON for non-sec and sec */
+ "mrc p15, 0, r0, c1, c1, 2\n"
+ "orr r0, r0, #(3 << 10)\n"
+ "bic r0, r0, #(3 << 14)\n"
+ "mcr p15, 0, r0, c1, c1, 2\n"
+ "isb\n"
+ "dsb\n"
+ "mov r0, #0x00f00000\n"
+ "mcr p15, 0, r0, c1, c0, 2\n"
+ "isb\n"
+ "dsb\n"
+ "mov r0, #0x40000000\n"
+ /* vmsr FPEXC, r0 */
+ ".inst 0xeee80a10\n"
+ :
+ :
+ : "cc", "r0", "memory");
+}
+
void *skern_init(unsigned int (*fcn_p()), unsigned int from,
unsigned int freq)
{
if (i != cpu_id)
addr[i] = SECONDARY_ENTRY_PTR;
}
+
+ /* initialize the GIC, registers to enable group1 irqs */
+ addr = (unsigned int*)GIC_XXX;
+ for (i = 1; i < 16; i++)
+ addr[i] = 0;
}
+ /* setup L2 latency values */
+ a15_setup_l2_latency();
+
+ /* set up basic A15 features or configurations */
+ a15_setup_cp15();
+
/* set the CNTFREQ */
asm volatile ("mcr p15, 0, %0, c14, c0, 0"
: /* No output operands */
diff --git a/sec/skernel.S b/sec/skernel.S
index 0b0dc2482e40c113294b31dd51007d4979ec5ae5..a60b637cc19bce5ea479956178c227f1709b2c67 100644 (file)
--- a/sec/skernel.S
+++ b/sec/skernel.S
push {r2}
cmp r0, r1
ble loop1
- mrc p15, 1, r0, c9, c0, 2 @ L2CTLR (w in ns 0)
- orr r0, r0, #(0x2 << 10) @ DRS (2 S) <A1>Vslices: #2
- orr r0, r0, #(0x1 << 6) @ TRL (2 c) <A1>V Tag ram latency : 2 cycles
- orr r0, r0, #(0x3 << 0) @ DRL (4 c) <A1>V Data Ram latency : 4cycles
- mcr p15, 1, r0, c9, c0, 2
- isb
- dsb
ldmfd r13!, {r0-r3, lr}
mov pc, lr