common.h: Make AM65_BOARDCFG_RM_RESASG_ENTRIES generic
[processor-firmware/system-firmware-image-gen.git] / common.h
1 /*
2  * K3 System Firmware Board Configuration Data Structures
3  *
4  * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
5  *      Andreas Dannenberg <dannenberg@ti.com>
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  *
11  *    Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  *
14  *    Redistributions in binary form must reproduce the above copyright
15  *    notice, this list of conditions and the following disclaimer in the
16  *    documentation and/or other materials provided with the
17  *    distribution.
18  *
19  *    Neither the name of Texas Instruments Incorporated nor the names of
20  *    its contributors may be used to endorse or promote products derived
21  *    from this software without specific prior written permission.
22  *
23  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
24  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
25  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
26  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
27  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
28  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
29  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
30  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
31  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34  */
36 #ifndef COMMON_H
37 #define COMMON_H
39 #include <sysfw_img_cfg.h>
41 /**
42  * Standard Linux Kernel integer types
43  */
44 typedef signed char s8;
45 typedef unsigned char u8;
47 typedef signed short s16;
48 typedef unsigned short u16;
50 typedef signed int s32;
51 typedef unsigned int u32;
53 typedef signed long long s64;
54 typedef unsigned long long u64;
56 /**
57  * Fault tolerant boolean type (specific to SYSFW)
58  */
59 typedef u8 ftbool;
61 /**
62  * Basic bit operations
63  */
64 #define BIT(n)          (1UL << (n))
66 /**
67  * Various definitions as expected by the 'struct' declarations below
68  */
69 #define BOARDCFG_RM_HOST_CFG_MAGIC_NUM          0x4C41
70 #define BOARDCFG_RM_RESASG_MAGIC_NUM            0x7B25
71 #define BOARDCFG_CONTROL_MAGIC_NUM              0xC1D3
72 #define BOARDCFG_SECPROXY_MAGIC_NUM             0x1207
73 #define BOARDCFG_MSMC_MAGIC_NUM                 0xA5C3
74 #define BOARDCFG_PROC_ACL_MAGIC_NUM             0xF1EA
75 #define BOARDCFG_HOST_HIERARCHY_MAGIC_NUM       0x8D27
76 #define BOARDCFG_RESASG_MAGIC_NUM               0x4C41
77 #define BOARDCFG_DBG_CFG_MAGIC_NUM              0x020C
78 #define BOARDCFG_PMIC_CFG_MAGIC_NUM             0x3172
80 struct boardcfg_substructure_header {
81         u16     magic;
82         u16     size;
83 } __attribute__((__packed__));
85 struct boardcfg_abi_rev {
86         u8      boardcfg_abi_maj;
87         u8      boardcfg_abi_min;
88 } __attribute__((__packed__));
90 /**
91  * Definitions, types, etc. as used for general board configuration
92  */
93 struct boardcfg_control {
94         struct boardcfg_substructure_header     subhdr;
95         ftbool                                  main_isolation_enable;
96         u16                                     main_isolation_hostid;
97 } __attribute__((__packed__));
99 struct boardcfg_secproxy {
100         struct boardcfg_substructure_header     subhdr;
101         u8                                      scaling_factor;
102         u8                                      scaling_profile;
103         u8                                      disable_main_nav_secure_proxy;
104 } __attribute__((__packed__));
106 struct boardcfg_msmc {
107         struct boardcfg_substructure_header     subhdr;
108         u8                                      msmc_cache_size;
109 } __attribute__((__packed__));
112 #define BOARDCFG_TRACE_DST_UART0                BIT(0)
113 #define BOARDCFG_TRACE_DST_ITM                  BIT(2)
114 #define BOARDCFG_TRACE_DST_MEM                  BIT(3)
116 #define BOARDCFG_TRACE_SRC_PM                   BIT(0)
117 #define BOARDCFG_TRACE_SRC_RM                   BIT(1)
118 #define BOARDCFG_TRACE_SRC_SEC                  BIT(2)
119 #define BOARDCFG_TRACE_SRC_BASE                 BIT(3)
120 #define BOARDCFG_TRACE_SRC_USER                 BIT(4)
121 #define BOARDCFG_TRACE_SRC_SUPR                 BIT(5)
123 struct boardcfg_dbg_cfg {
124         struct boardcfg_substructure_header     subhdr;
125         u16                                     trace_dst_enables;
126         u16                                     trace_src_enables;
127 } __attribute__((__packed__));
129 struct k3_boardcfg {
130         struct boardcfg_abi_rev                 rev;
131         struct boardcfg_control                 control;
132         struct boardcfg_secproxy                secproxy;
133         struct boardcfg_msmc                    msmc;
134         struct boardcfg_dbg_cfg                 debug_cfg;
135 } __attribute__((__packed__));
137 /**
138  * Definitions, types, etc. as used for resource assignment
139  */
140 #define HOST_ID_DMSC                            0
141 #define HOST_ID_R5_0                            3
142 #define HOST_ID_R5_1                            4
143 #define HOST_ID_R5_2                            5
144 #define HOST_ID_R5_3                            6
145 #define HOST_ID_A53_0                           10
146 #define HOST_ID_A53_1                           11
147 #define HOST_ID_A53_2                           12
148 #define HOST_ID_A53_3                           13
149 #define HOST_ID_A53_4                           14
150 #define HOST_ID_A53_5                           15
151 #define HOST_ID_A53_6                           16
152 #define HOST_ID_A53_7                           17
153 #define HOST_ID_GPU_0                           30
154 #define HOST_ID_GPU_1                           31
155 #define HOST_ID_ICSSG_0                         50
156 #define HOST_ID_ICSSG_1                         51
157 #define HOST_ID_ICSSG_2                         52
159 struct boardcfg_rm_host_cfg_entry {
160         u8      host_id;
161         u8      allowed_atype;
162         u16     allowed_qos;
163         u32     allowed_orderid;
164         u16     allowed_priority;
165         u8      allowed_sched_priority;
166 } __attribute__((__packed__));
168 #define BOARDCFG_RM_HOST_CFG_ENTRIES (32U)
170 struct boardcfg_rm_host_cfg {
171         struct boardcfg_substructure_header     subhdr;
172         struct boardcfg_rm_host_cfg_entry
173                                  host_cfg_entries[BOARDCFG_RM_HOST_CFG_ENTRIES];
174 };
176 #define RESASG_TYPE_SHIFT                       0x0006
177 #define RESASG_TYPE_MASK                        0xFFC0
178 #define RESASG_SUBTYPE_SHIFT                    0x0000
179 #define RESASG_SUBTYPE_MASK                     0x003F
181 #define RESASG_UTYPE(type, subtype) \
182         (((type << RESASG_TYPE_SHIFT) & RESASG_TYPE_MASK) | \
183          ((subtype << RESASG_SUBTYPE_SHIFT) & RESASG_SUBTYPE_MASK))
185 enum resasg_types {
186         RESASG_TYPE_MAIN_NAV_UDMASS_IA0 = 0x000,
187         RESASG_TYPE_MAIN_NAV_MODSS_IA0 = 0x001,
188         RESASG_TYPE_MAIN_NAV_MODSS_IA1 = 0x002,
189         RESASG_TYPE_MCU_NAV_UDMASS_IA0 = 0x003,
190         RESASG_TYPE_MAIN_NAV_MCRC = 0x004,
191         RESASG_TYPE_MCU_NAV_MCRC = 0x005,
192         RESASG_TYPE_MAIN_NAV_UDMAP = 0x006,
193         RESASG_TYPE_MCU_NAV_UDMAP = 0x007,
194         RESASG_TYPE_MSMC = 0x008,
195         RESASG_TYPE_MAIN_NAV_RA = 0x009,
196         RESASG_TYPE_MCU_NAV_RA = 0x00A,
197         RESASG_TYPE_GIC_IRQ = 0x00B,
198         RESASG_TYPE_PULSAR_C0_IRQ = 0x00C,
199         RESASG_TYPE_PULSAR_C1_IRQ = 0x00D,
200         RESASG_TYPE_ICSSG0_IRQ = 0x00E,
201         RESASG_TYPE_ICSSG1_IRQ = 0x00F,
202         RESASG_TYPE_ICSSG2_IRQ = 0x010,
203         RESASG_TYPE_MAX = 0x3FF
204 };
206 enum resasg_subtype_main_nav_udmass_ia0 {
207         RESASG_SUBTYPE_MAIN_NAV_UDMASS_IA0_VINT = 0x00,
208         RESASG_SUBTYPE_MAIN_NAV_UDMASS_IA0_SEVI = 0x01,
209         RESASG_SUBTYPE_MAIN_NAV_UDMASS_IA0_MEVI = 0x02,
210         RESASG_SUBTYPE_MAIN_NAV_UDMASS_IA0_GEVI = 0x03,
211         RESASG_SUBYTPE_MAIN_NAV_UDMASS_IA0_CNT = 0x04,
212 };
214 enum resasg_subtype_main_nav_modss_ia0 {
215         RESASG_SUBTYPE_MAIN_NAV_MODSS_IA0_VINT = 0x00,
216         RESASG_SUBTYPE_MAIN_NAV_MODSS_IA0_SEVI = 0x01,
217         RESASG_SUBYTPE_MAIN_NAV_MODSS_IA0_CNT = 0x02,
218 };
220 enum resasg_subtype_main_nav_modss_ia1 {
221         RESASG_SUBTYPE_MAIN_NAV_MODSS_IA1_VINT = 0x00,
222         RESASG_SUBTYPE_MAIN_NAV_MODSS_IA1_SEVI = 0x01,
223         RESASG_SUBYTPE_MAIN_NAV_MODSS_IA1_CNT = 0x02,
224 };
226 enum resasg_subtype_mcu_nav_udmass_ia0 {
227         RESASG_SUBTYPE_MCU_NAV_UDMASS_IA0_VINT = 0x00,
228         RESASG_SUBTYPE_MCU_NAV_UDMASS_IA0_SEVI = 0x01,
229         RESASG_SUBTYPE_MCU_NAV_UDMASS_IA0_MEVI = 0x02,
230         RESASG_SUBTYPE_MCU_NAV_UDMASS_IA0_GEVI = 0x03,
231         RESASG_SUBYTPE_MCU_NAV_UDMASS_IA0_CNT = 0x04,
232 };
234 enum resasg_subtype_main_nav_mcrc {
235         RESASG_SUBTYPE_MAIN_NAV_MCRC_LEVI = 0x00,
236         RESASG_SUBYTPE_MAIN_NAV_MCRC_CNT = 0x01,
237 };
239 enum resasg_subtype_mcu_nav_mcrc {
240         RESASG_SUBTYPE_MCU_NAV_MCRC_LEVI = 0x00,
241         RESASG_SUBYTPE_MCU_NAV_MCRC_CNT = 0x01,
242 };
244 enum resasg_subtype_main_nav_udmap {
245         RESASG_SUBTYPE_MAIN_NAV_UDMAP_TRIGGER = 0x00,
246         RESASG_SUBTYPE_MAIN_NAV_UDMAP_TX_HCHAN = 0x01,
247         RESASG_SUBTYPE_MAIN_NAV_UDMAP_TX_CHAN = 0x02,
248         RESASG_SUBTYPE_MAIN_NAV_UDMAP_TX_ECHAN = 0x03,
249         RESASG_SUBTYPE_MAIN_NAV_UDMAP_RX_HCHAN = 0x04,
250         RESASG_SUBTYPE_MAIN_NAV_UDMAP_RX_CHAN = 0x05,
251         RESASG_SUBTYPE_MAIN_NAV_UDMAP_RX_FLOW_COMMON = 0x06,
252         RESASG_SUBTYPE_MAIN_NAV_UDMAP_INVALID_FLOW_OES = 0x07,
253         RESASG_SUBYTPE_MAIN_NAV_UDMAP_CNT = 0x08,
254 };
256 enum resasg_subtype_mcu_nav_udmap {
257         RESASG_SUBTYPE_MCU_NAV_UDMAP_TRIGGER = 0x00,
258         RESASG_SUBTYPE_MCU_NAV_UDMAP_TX_HCHAN = 0x01,
259         RESASG_SUBTYPE_MCU_NAV_UDMAP_TX_CHAN = 0x02,
260         RESASG_SUBTYPE_MCU_NAV_UDMAP_RX_HCHAN = 0x03,
261         RESASG_SUBTYPE_MCU_NAV_UDMAP_RX_CHAN = 0x04,
262         RESASG_SUBTYPE_MCU_NAV_UDMAP_RX_FLOW_COMMON = 0x05,
263         RESASG_SUBTYPE_MCU_NAV_UDMAP_INVALID_FLOW_OES = 0x06,
264         RESASG_SUBYTPE_MCU_NAV_UDMAP_CNT = 0x07,
265 };
267 enum resasg_subtype_msmc {
268         RESASG_SUBTYPE_MSMC_DRU = 0x00,
269         RESASG_SUBYTPE_MSMC_CNT = 0x01,
270 };
272 enum resasg_subtype_main_nav_ra {
273         RESASG_SUBTYPE_MAIN_NAV_RA_RING_UDMAP_TX = 0x00,
274         RESASG_SUBTYPE_MAIN_NAV_RA_RING_UDMAP_RX = 0x01,
275         RESASG_SUBTYPE_MAIN_NAV_RA_RING_GP = 0x02,
276         RESASG_SUBTYPE_MAIN_NAV_RA_ERROR_OES = 0x03,
277         RESASG_SUBYTPE_MAIN_NAV_RA_CNT = 0x04,
278 };
280 enum resasg_subtype_mcu_nav_ra {
281         RESASG_SUBTYPE_MCU_NAV_RA_RING_UDMAP_TX = 0x00,
282         RESASG_SUBTYPE_MCU_NAV_RA_RING_UDMAP_RX = 0x01,
283         RESASG_SUBTYPE_MCU_NAV_RA_RING_GP = 0x02,
284         RESASG_SUBTYPE_MCU_NAV_RA_ERROR_OES = 0x03,
285         RESASG_SUBYTPE_MCU_NAV_RA_CNT = 0x04,
286 };
288 enum resasg_subtype_gic_irq {
289         RESASG_SUBTYPE_GIC_IRQ_MAIN_NAV_SET0 = 0x00,
290         RESASG_SUBTYPE_GIC_IRQ_MAIN_GPIO = 0x01,
291         RESASG_SUBTYPE_GIC_IRQ_MAIN_NAV_SET1 = 0x02,
292         RESASG_SUBTYPE_GIC_IRQ_COMP_EVT = 0x03,
293         RESASG_SUBTYPE_GIC_IRQ_WKUP_GPIO = 0x04,
294         RESASG_SUBYTPE_GIC_IRQ_CNT = 0x05,
295 };
297 enum resasg_subtype_pulsar_c0_irq {
298         RESASG_SUBTYPE_PULSAR_C0_IRQ_MCU_NAV = 0x00,
299         RESASG_SUBTYPE_PULSAR_C0_IRQ_WKUP_GPIO = 0x01,
300         RESASG_SUBTYPE_PULSAR_C0_IRQ_MAIN2MCU_LVL = 0x02,
301         RESASG_SUBTYPE_PULSAR_C0_IRQ_MAIN2MCU_PLS = 0x03,
302         RESASG_SUBYTPE_PULSAR_C0_IRQ_CNT = 0x04,
303 };
305 enum resasg_subtype_pulsar_c1_irq {
306         RESASG_SUBTYPE_PULSAR_C1_IRQ_MCU_NAV = 0x00,
307         RESASG_SUBTYPE_PULSAR_C1_IRQ_WKUP_GPIO = 0x01,
308         RESASG_SUBTYPE_PULSAR_C1_IRQ_MAIN2MCU_LVL = 0x02,
309         RESASG_SUBTYPE_PULSAR_C1_IRQ_MAIN2MCU_PLS = 0x03,
310         RESASG_SUBYTPE_PULSAR_C1_IRQ_CNT = 0x04,
311 };
313 enum resasg_subtype_icssg0_irq {
314         RESASG_SUBTYPE_ICSSG0_IRQ_MAIN_NAV = 0x00,
315         RESASG_SUBTYPE_ICSSG0_IRQ_MAIN_GPIO = 0x01,
316         RESASG_SUBYTPE_ICSSG0_IRQ_CNT = 0x02,
317 };
319 enum resasg_subtype_icssg1_irq {
320         RESASG_SUBTYPE_ICSSG1_IRQ_MAIN_NAV = 0x00,
321         RESASG_SUBTYPE_ICSSG1_IRQ_MAIN_GPIO = 0x01,
322         RESASG_SUBYTPE_ICSSG1_IRQ_CNT = 0x02,
323 };
325 enum resasg_subtype_icssg2_irq {
326         RESASG_SUBTYPE_ICSSG2_IRQ_MAIN_NAV = 0x00,
327         RESASG_SUBTYPE_ICSSG2_IRQ_MAIN_GPIO = 0x01,
328         RESASG_SUBYTPE_ICSSG2_IRQ_CNT = 0x02,
329 };
331 struct boardcfg_rm_resasg_entry {
332         u16                                     start_resource;
333         u16                                     num_resource;
334         u16                                     type;
335         u8                                      host_id;
336         u8                                      reserved;
337 };
339 struct boardcfg_rm_resasg {
340         struct boardcfg_substructure_header     subhdr;
341         u16                                     resasg_entries_size;
342         u16                                     reserved;
343         struct boardcfg_rm_resasg_entry         resasg_entries[];
344 } __attribute__((__packed__));
346 struct k3_boardcfg_rm {
347         struct boardcfg_abi_rev                 rev;
348         struct boardcfg_rm_host_cfg             host_cfg;
349         struct boardcfg_rm_resasg               resasg;
350 } __attribute__((__packed__));
352 /*
353  * This is essentially 'struct k3_boardcfg_rm', but modified to pull
354  * .resasg_entries which is a member of 'struct boardcfg_rm_resasg' into
355  * the outer structure for easier explicit initialization.
356  */
357 struct am65_boardcfg_rm_local {
358         struct k3_boardcfg_rm                   rm_boardcfg;
359         struct boardcfg_rm_resasg_entry
360                                 resasg_entries[BOARDCFG_RM_RESASG_ENTRIES];
361 } __attribute__((__packed__));
363 /**
364  * Definitions, types, etc. as used for the security configuration
365  */
366 #define PROCESSOR_ACL_SECONDARY_MASTERS_MAX     3
368 struct boardcfg_proc_acl_entry {
369         u8                                      processor_id;
370         u8                                      proc_access_master;
371         u8           proc_access_secondary[PROCESSOR_ACL_SECONDARY_MASTERS_MAX];
372 } __attribute__((__packed__));
374 #define PROCESSOR_ACL_ENTRIES                   32
376 struct boardcfg_proc_acl {
377         struct boardcfg_substructure_header     subhdr;
378         struct boardcfg_proc_acl_entry  proc_acl_entries[PROCESSOR_ACL_ENTRIES];
379 } __attribute__((__packed__));
381 struct boardcfg_host_hierarchy_entry {
382         u8                                      host_id;
383         u8                                      supervisor_host_id;
384 } __attribute__((__packed__));
386 #define HOST_HIERARCHY_ENTRIES                  32
388 struct boardcfg_host_hierarchy {
389         struct boardcfg_substructure_header     subhdr;
390         struct boardcfg_host_hierarchy_entry
391                                  host_hierarchy_entries[HOST_HIERARCHY_ENTRIES];
392 } __attribute__((__packed__));
394 struct k3_boardcfg_security {
395         struct boardcfg_abi_rev                 rev;
396         struct boardcfg_proc_acl                processor_acl_list;
397         struct boardcfg_host_hierarchy          host_hierarchy;
398 } __attribute__((__packed__));
400 /**
401  * Definitions, types, etc. as used for PM configuration
402  */
403 struct k3_boardcfg_pm {
404         struct boardcfg_abi_rev                 rev;
405 } __attribute__((__packed__));
407 /**
408  * Export different board configuration structures
409  */
410 extern const struct k3_boardcfg am65_boardcfg_data;
411 extern const struct am65_boardcfg_rm_local am65_boardcfg_rm_data;
412 extern const struct k3_boardcfg_security am65_boardcfg_security_data;
413 extern const struct k3_boardcfg_pm am65_boardcfg_pm_data;
415 #endif /* COMMON_H */