common: Add basic BIT(x) macro defininiton
[processor-firmware/system-firmware-image-gen.git] / common.h
1 /*
2  * K3 System Firmware Board Configuration Data Structures
3  *
4  * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
5  *      Andreas Dannenberg <dannenberg@ti.com>
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  *
11  *    Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  *
14  *    Redistributions in binary form must reproduce the above copyright
15  *    notice, this list of conditions and the following disclaimer in the
16  *    documentation and/or other materials provided with the
17  *    distribution.
18  *
19  *    Neither the name of Texas Instruments Incorporated nor the names of
20  *    its contributors may be used to endorse or promote products derived
21  *    from this software without specific prior written permission.
22  *
23  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
24  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
25  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
26  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
27  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
28  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
29  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
30  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
31  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34  */
36 /**
37  * Standard Linux Kernel integer types
38  */
39 typedef signed char s8;
40 typedef unsigned char u8;
42 typedef signed short s16;
43 typedef unsigned short u16;
45 typedef signed int s32;
46 typedef unsigned int u32;
48 typedef signed long long s64;
49 typedef unsigned long long u64;
51 /**
52  * Fault tolerant boolean type (specific to SYSFW)
53  */
54 typedef u8 ftbool;
56 /**
57  * Basic bit operations
58  */
59 #define BIT(n)          (1UL << (n))
61 /**
62  * Various definitions as expected by the 'struct' declarations below
63  */
64 #define BOARDCFG_RM_HOST_CFG_MAGIC_NUM          0x4C41
65 #define BOARDCFG_RM_RESASG_MAGIC_NUM            0x7B25
66 #define BOARDCFG_CONTROL_MAGIC_NUM              0xC1D3
67 #define BOARDCFG_SECPROXY_MAGIC_NUM             0x1207
68 #define BOARDCFG_MSMC_MAGIC_NUM                 0xA5C3
69 #define BOARDCFG_PROC_ACL_MAGIC_NUM             0xF1EA
70 #define BOARDCFG_HOST_HIERARCHY_MAGIC_NUM       0x8D27
71 #define BOARDCFG_RESASG_MAGIC_NUM               0x4C41
72 #define BOARDCFG_DBG_CFG_MAGIC_NUM              0x020C
73 #define BOARDCFG_PMIC_CFG_MAGIC_NUM             0x3172
75 struct boardcfg_substructure_header {
76         u16     magic;
77         u16     size;
78 } __attribute__((__packed__));
80 struct boardcfg_abi_rev {
81         u8      boardcfg_abi_maj;
82         u8      boardcfg_abi_min;
83 } __attribute__((__packed__));
85 /**
86  * Definitions, types, etc. as used for general board configuration
87  */
88 struct boardcfg_control {
89         struct boardcfg_substructure_header     subhdr;
90         ftbool                                  main_isolation_enable;
91         u16                                     main_isolation_hostid;
92 } __attribute__((__packed__));
94 struct boardcfg_secproxy {
95         struct boardcfg_substructure_header     subhdr;
96         u8                                      scaling_factor;
97         u8                                      scaling_profile;
98         u8                                      disable_main_nav_secure_proxy;
99 } __attribute__((__packed__));
101 struct boardcfg_msmc {
102         struct boardcfg_substructure_header     subhdr;
103         u8                                      msmc_cache_size;
104 } __attribute__((__packed__));
107 #define BOARDCFG_TRACE_DST_UART0                BIT(0)
108 #define BOARDCFG_TRACE_DST_ITM                  BIT(2)
109 #define BOARDCFG_TRACE_DST_MEM                  BIT(3)
111 #define BOARDCFG_TRACE_SRC_PM                   BIT(0)
112 #define BOARDCFG_TRACE_SRC_RM                   BIT(1)
113 #define BOARDCFG_TRACE_SRC_SEC                  BIT(2)
114 #define BOARDCFG_TRACE_SRC_BASE                 BIT(3)
115 #define BOARDCFG_TRACE_SRC_USER                 BIT(4)
116 #define BOARDCFG_TRACE_SRC_SUPR                 BIT(5)
118 struct boardcfg_dbg_cfg {
119         struct boardcfg_substructure_header     subhdr;
120         u16                                     trace_dst_enables;
121         u16                                     trace_src_enables;
122 } __attribute__((__packed__));
124 struct k3_boardcfg {
125         struct boardcfg_abi_rev                 rev;
126         struct boardcfg_control                 control;
127         struct boardcfg_secproxy                secproxy;
128         struct boardcfg_msmc                    msmc;
129         struct boardcfg_dbg_cfg                 debug_cfg;
130 } __attribute__((__packed__));
132 /**
133  * Definitions, types, etc. as used for resource assignment
134  */
135 #define HOST_ID_DMSC                            0
136 #define HOST_ID_R5_0                            3
137 #define HOST_ID_R5_1                            4
138 #define HOST_ID_R5_2                            5
139 #define HOST_ID_R5_3                            6
140 #define HOST_ID_A53_0                           10
141 #define HOST_ID_A53_1                           11
142 #define HOST_ID_A53_2                           12
143 #define HOST_ID_A53_3                           13
144 #define HOST_ID_A53_4                           14
145 #define HOST_ID_A53_5                           15
146 #define HOST_ID_A53_6                           16
147 #define HOST_ID_A53_7                           17
148 #define HOST_ID_GPU_0                           30
149 #define HOST_ID_GPU_1                           31
150 #define HOST_ID_ICSSG_0                         50
151 #define HOST_ID_ICSSG_1                         51
152 #define HOST_ID_ICSSG_2                         52
154 struct boardcfg_rm_host_cfg_entry {
155         u8      host_id;
156         u8      allowed_atype;
157         u16     allowed_qos;
158         u32     allowed_orderid;
159         u16     allowed_priority;
160         u8      allowed_sched_priority;
161 } __attribute__((__packed__));
163 #define BOARDCFG_RM_HOST_CFG_ENTRIES (32U)
165 struct boardcfg_rm_host_cfg {
166         struct boardcfg_substructure_header     subhdr;
167         struct boardcfg_rm_host_cfg_entry
168                                  host_cfg_entries[BOARDCFG_RM_HOST_CFG_ENTRIES];
169 };
171 #define RESASG_TYPE_SHIFT                       0x0006
172 #define RESASG_TYPE_MASK                        0xFFC0
173 #define RESASG_SUBTYPE_SHIFT                    0x0000
174 #define RESASG_SUBTYPE_MASK                     0x003F
176 #define RESASG_UTYPE(type, subtype) \
177         (((type << RESASG_TYPE_SHIFT) & RESASG_TYPE_MASK) | \
178          ((subtype << RESASG_SUBTYPE_SHIFT) & RESASG_SUBTYPE_MASK))
180 enum resasg_types {
181         RESASG_TYPE_MAIN_NAV_UDMASS_IA0 = 0x000,
182         RESASG_TYPE_MAIN_NAV_MODSS_IA0 = 0x001,
183         RESASG_TYPE_MAIN_NAV_MODSS_IA1 = 0x002,
184         RESASG_TYPE_MCU_NAV_UDMASS_IA0 = 0x003,
185         RESASG_TYPE_MAIN_NAV_MCRC = 0x004,
186         RESASG_TYPE_MCU_NAV_MCRC = 0x005,
187         RESASG_TYPE_MAIN_NAV_UDMAP = 0x006,
188         RESASG_TYPE_MCU_NAV_UDMAP = 0x007,
189         RESASG_TYPE_MSMC = 0x008,
190         RESASG_TYPE_MAIN_NAV_RA = 0x009,
191         RESASG_TYPE_MCU_NAV_RA = 0x00A,
192         RESASG_TYPE_GIC_IRQ = 0x00B,
193         RESASG_TYPE_PULSAR_C0_IRQ = 0x00C,
194         RESASG_TYPE_PULSAR_C1_IRQ = 0x00D,
195         RESASG_TYPE_ICSSG0_IRQ = 0x00E,
196         RESASG_TYPE_ICSSG1_IRQ = 0x00F,
197         RESASG_TYPE_ICSSG2_IRQ = 0x010,
198         RESASG_TYPE_MAX = 0x3FF
199 };
201 enum resasg_subtype_main_nav_udmass_ia0 {
202         RESASG_SUBTYPE_MAIN_NAV_UDMASS_IA0_VINT = 0x00,
203         RESASG_SUBTYPE_MAIN_NAV_UDMASS_IA0_SEVI = 0x01,
204         RESASG_SUBTYPE_MAIN_NAV_UDMASS_IA0_MEVI = 0x02,
205         RESASG_SUBTYPE_MAIN_NAV_UDMASS_IA0_GEVI = 0x03,
206         RESASG_SUBYTPE_MAIN_NAV_UDMASS_IA0_CNT = 0x04,
207 };
209 enum resasg_subtype_main_nav_modss_ia0 {
210         RESASG_SUBTYPE_MAIN_NAV_MODSS_IA0_VINT = 0x00,
211         RESASG_SUBTYPE_MAIN_NAV_MODSS_IA0_SEVI = 0x01,
212         RESASG_SUBYTPE_MAIN_NAV_MODSS_IA0_CNT = 0x02,
213 };
215 enum resasg_subtype_main_nav_modss_ia1 {
216         RESASG_SUBTYPE_MAIN_NAV_MODSS_IA1_VINT = 0x00,
217         RESASG_SUBTYPE_MAIN_NAV_MODSS_IA1_SEVI = 0x01,
218         RESASG_SUBYTPE_MAIN_NAV_MODSS_IA1_CNT = 0x02,
219 };
221 enum resasg_subtype_mcu_nav_udmass_ia0 {
222         RESASG_SUBTYPE_MCU_NAV_UDMASS_IA0_VINT = 0x00,
223         RESASG_SUBTYPE_MCU_NAV_UDMASS_IA0_SEVI = 0x01,
224         RESASG_SUBTYPE_MCU_NAV_UDMASS_IA0_MEVI = 0x02,
225         RESASG_SUBTYPE_MCU_NAV_UDMASS_IA0_GEVI = 0x03,
226         RESASG_SUBYTPE_MCU_NAV_UDMASS_IA0_CNT = 0x04,
227 };
229 enum resasg_subtype_main_nav_mcrc {
230         RESASG_SUBTYPE_MAIN_NAV_MCRC_LEVI = 0x00,
231         RESASG_SUBYTPE_MAIN_NAV_MCRC_CNT = 0x01,
232 };
234 enum resasg_subtype_mcu_nav_mcrc {
235         RESASG_SUBTYPE_MCU_NAV_MCRC_LEVI = 0x00,
236         RESASG_SUBYTPE_MCU_NAV_MCRC_CNT = 0x01,
237 };
239 enum resasg_subtype_main_nav_udmap {
240         RESASG_SUBTYPE_MAIN_NAV_UDMAP_TRIGGER = 0x00,
241         RESASG_SUBTYPE_MAIN_NAV_UDMAP_TX_HCHAN = 0x01,
242         RESASG_SUBTYPE_MAIN_NAV_UDMAP_TX_CHAN = 0x02,
243         RESASG_SUBTYPE_MAIN_NAV_UDMAP_TX_ECHAN = 0x03,
244         RESASG_SUBTYPE_MAIN_NAV_UDMAP_RX_HCHAN = 0x04,
245         RESASG_SUBTYPE_MAIN_NAV_UDMAP_RX_CHAN = 0x05,
246         RESASG_SUBTYPE_MAIN_NAV_UDMAP_RX_FLOW_COMMON = 0x06,
247         RESASG_SUBTYPE_MAIN_NAV_UDMAP_INVALID_FLOW_OES = 0x07,
248         RESASG_SUBYTPE_MAIN_NAV_UDMAP_CNT = 0x08,
249 };
251 enum resasg_subtype_mcu_nav_udmap {
252         RESASG_SUBTYPE_MCU_NAV_UDMAP_TRIGGER = 0x00,
253         RESASG_SUBTYPE_MCU_NAV_UDMAP_TX_HCHAN = 0x01,
254         RESASG_SUBTYPE_MCU_NAV_UDMAP_TX_CHAN = 0x02,
255         RESASG_SUBTYPE_MCU_NAV_UDMAP_RX_HCHAN = 0x03,
256         RESASG_SUBTYPE_MCU_NAV_UDMAP_RX_CHAN = 0x04,
257         RESASG_SUBTYPE_MCU_NAV_UDMAP_RX_FLOW_COMMON = 0x05,
258         RESASG_SUBTYPE_MCU_NAV_UDMAP_INVALID_FLOW_OES = 0x06,
259         RESASG_SUBYTPE_MCU_NAV_UDMAP_CNT = 0x07,
260 };
262 enum resasg_subtype_msmc {
263         RESASG_SUBTYPE_MSMC_DRU = 0x00,
264         RESASG_SUBYTPE_MSMC_CNT = 0x01,
265 };
267 enum resasg_subtype_main_nav_ra {
268         RESASG_SUBTYPE_MAIN_NAV_RA_RING_UDMAP_TX = 0x00,
269         RESASG_SUBTYPE_MAIN_NAV_RA_RING_UDMAP_RX = 0x01,
270         RESASG_SUBTYPE_MAIN_NAV_RA_RING_GP = 0x02,
271         RESASG_SUBTYPE_MAIN_NAV_RA_ERROR_OES = 0x03,
272         RESASG_SUBYTPE_MAIN_NAV_RA_CNT = 0x04,
273 };
275 enum resasg_subtype_mcu_nav_ra {
276         RESASG_SUBTYPE_MCU_NAV_RA_RING_UDMAP_TX = 0x00,
277         RESASG_SUBTYPE_MCU_NAV_RA_RING_UDMAP_RX = 0x01,
278         RESASG_SUBTYPE_MCU_NAV_RA_RING_GP = 0x02,
279         RESASG_SUBTYPE_MCU_NAV_RA_ERROR_OES = 0x03,
280         RESASG_SUBYTPE_MCU_NAV_RA_CNT = 0x04,
281 };
283 enum resasg_subtype_gic_irq {
284         RESASG_SUBTYPE_GIC_IRQ_MAIN_NAV_SET0 = 0x00,
285         RESASG_SUBTYPE_GIC_IRQ_MAIN_GPIO = 0x01,
286         RESASG_SUBTYPE_GIC_IRQ_MAIN_NAV_SET1 = 0x02,
287         RESASG_SUBTYPE_GIC_IRQ_COMP_EVT = 0x03,
288         RESASG_SUBTYPE_GIC_IRQ_WKUP_GPIO = 0x04,
289         RESASG_SUBYTPE_GIC_IRQ_CNT = 0x05,
290 };
292 enum resasg_subtype_pulsar_c0_irq {
293         RESASG_SUBTYPE_PULSAR_C0_IRQ_MCU_NAV = 0x00,
294         RESASG_SUBTYPE_PULSAR_C0_IRQ_WKUP_GPIO = 0x01,
295         RESASG_SUBTYPE_PULSAR_C0_IRQ_MAIN2MCU_LVL = 0x02,
296         RESASG_SUBTYPE_PULSAR_C0_IRQ_MAIN2MCU_PLS = 0x03,
297         RESASG_SUBYTPE_PULSAR_C0_IRQ_CNT = 0x04,
298 };
300 enum resasg_subtype_pulsar_c1_irq {
301         RESASG_SUBTYPE_PULSAR_C1_IRQ_MCU_NAV = 0x00,
302         RESASG_SUBTYPE_PULSAR_C1_IRQ_WKUP_GPIO = 0x01,
303         RESASG_SUBTYPE_PULSAR_C1_IRQ_MAIN2MCU_LVL = 0x02,
304         RESASG_SUBTYPE_PULSAR_C1_IRQ_MAIN2MCU_PLS = 0x03,
305         RESASG_SUBYTPE_PULSAR_C1_IRQ_CNT = 0x04,
306 };
308 enum resasg_subtype_icssg0_irq {
309         RESASG_SUBTYPE_ICSSG0_IRQ_MAIN_NAV = 0x00,
310         RESASG_SUBTYPE_ICSSG0_IRQ_MAIN_GPIO = 0x01,
311         RESASG_SUBYTPE_ICSSG0_IRQ_CNT = 0x02,
312 };
314 enum resasg_subtype_icssg1_irq {
315         RESASG_SUBTYPE_ICSSG1_IRQ_MAIN_NAV = 0x00,
316         RESASG_SUBTYPE_ICSSG1_IRQ_MAIN_GPIO = 0x01,
317         RESASG_SUBYTPE_ICSSG1_IRQ_CNT = 0x02,
318 };
320 enum resasg_subtype_icssg2_irq {
321         RESASG_SUBTYPE_ICSSG2_IRQ_MAIN_NAV = 0x00,
322         RESASG_SUBTYPE_ICSSG2_IRQ_MAIN_GPIO = 0x01,
323         RESASG_SUBYTPE_ICSSG2_IRQ_CNT = 0x02,
324 };
326 struct boardcfg_rm_resasg_entry {
327         u16                                     start_resource;
328         u16                                     num_resource;
329         u16                                     type;
330         u8                                      host_id;
331         u8                                      reserved;
332 };
334 struct boardcfg_rm_resasg {
335         struct boardcfg_substructure_header     subhdr;
336         u16                                     resasg_entries_size;
337         u16                                     reserved;
338         struct boardcfg_rm_resasg_entry         resasg_entries[];
339 } __attribute__((__packed__));
341 struct k3_boardcfg_rm {
342         struct boardcfg_abi_rev                 rev;
343         struct boardcfg_rm_host_cfg             host_cfg;
344         struct boardcfg_rm_resasg               resasg;
345 } __attribute__((__packed__));
347 #define AM65_BOARDCFG_RM_RESASG_ENTRIES         59
349 /*
350  * This is essentially 'struct k3_boardcfg_rm', but modified to pull
351  * .resasg_entries which is a member of 'struct boardcfg_rm_resasg' into
352  * the outer structure for easier explicit initialization.
353  */
354 struct am65_boardcfg_rm_local {
355         struct k3_boardcfg_rm                   rm_boardcfg;
356         struct boardcfg_rm_resasg_entry
357                                 resasg_entries[AM65_BOARDCFG_RM_RESASG_ENTRIES];
358 } __attribute__((__packed__));
360 /**
361  * Definitions, types, etc. as used for the security configuration
362  */
363 #define PROCESSOR_ACL_SECONDARY_MASTERS_MAX     3
365 struct boardcfg_proc_acl_entry {
366         u8                                      processor_id;
367         u8                                      proc_access_master;
368         u8           proc_access_secondary[PROCESSOR_ACL_SECONDARY_MASTERS_MAX];
369 } __attribute__((__packed__));
371 #define PROCESSOR_ACL_ENTRIES                   32
373 struct boardcfg_proc_acl {
374         struct boardcfg_substructure_header     subhdr;
375         struct boardcfg_proc_acl_entry  proc_acl_entries[PROCESSOR_ACL_ENTRIES];
376 } __attribute__((__packed__));
378 struct boardcfg_host_hierarchy_entry {
379         u8                                      host_id;
380         u8                                      supervisor_host_id;
381 } __attribute__((__packed__));
383 #define HOST_HIERARCHY_ENTRIES                  32
385 struct boardcfg_host_hierarchy {
386         struct boardcfg_substructure_header     subhdr;
387         struct boardcfg_host_hierarchy_entry
388                                  host_hierarchy_entries[HOST_HIERARCHY_ENTRIES];
389 } __attribute__((__packed__));
391 struct k3_boardcfg_security {
392         struct boardcfg_abi_rev                 rev;
393         struct boardcfg_proc_acl                processor_acl_list;
394         struct boardcfg_host_hierarchy          host_hierarchy;
395 } __attribute__((__packed__));
397 /**
398  * Definitions, types, etc. as used for PM configuration
399  */
400 struct k3_boardcfg_pm {
401         struct boardcfg_abi_rev                 rev;
402 } __attribute__((__packed__));
404 /**
405  * Export different board configuration structures
406  */
407 extern const struct k3_boardcfg am65_boardcfg_data;
408 extern const struct am65_boardcfg_rm_local am65_boardcfg_rm_data;
409 extern const struct k3_boardcfg_security am65_boardcfg_security_data;
410 extern const struct k3_boardcfg_pm am65_boardcfg_pm_data;