build: Add support for HS devices
[processor-firmware/system-firmware-image-gen.git] / common.h
1 /*
2  * K3 System Firmware Board Configuration Data Structures
3  *
4  * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
5  *      Andreas Dannenberg <dannenberg@ti.com>
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  *
11  *    Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  *
14  *    Redistributions in binary form must reproduce the above copyright
15  *    notice, this list of conditions and the following disclaimer in the
16  *    documentation and/or other materials provided with the
17  *    distribution.
18  *
19  *    Neither the name of Texas Instruments Incorporated nor the names of
20  *    its contributors may be used to endorse or promote products derived
21  *    from this software without specific prior written permission.
22  *
23  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
24  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
25  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
26  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
27  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
28  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
29  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
30  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
31  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34  */
36 /**
37  * Standard Linux Kernel integer types
38  */
39 typedef signed char s8;
40 typedef unsigned char u8;
42 typedef signed short s16;
43 typedef unsigned short u16;
45 typedef signed int s32;
46 typedef unsigned int u32;
48 typedef signed long long s64;
49 typedef unsigned long long u64;
51 /**
52  * Fault tolerant boolean type (specific to SYSFW)
53  */
54 typedef u8 ftbool;
56 /**
57  * Various definitions as expected by the 'struct' declarations below
58  */
59 #define BOARDCFG_RM_HOST_CFG_MAGIC_NUM          0x4C41
60 #define BOARDCFG_RM_RESASG_MAGIC_NUM            0x7B25
61 #define BOARDCFG_CONTROL_MAGIC_NUM              0xC1D3
62 #define BOARDCFG_SECPROXY_MAGIC_NUM             0x1207
63 #define BOARDCFG_MSMC_MAGIC_NUM                 0xA5C3
64 #define BOARDCFG_PROC_ACL_MAGIC_NUM             0xF1EA
65 #define BOARDCFG_HOST_HIERARCHY_MAGIC_NUM       0x8D27
66 #define BOARDCFG_RESASG_MAGIC_NUM               0x4C41
67 #define BOARDCFG_DBG_CFG_MAGIC_NUM              0x020C
68 #define BOARDCFG_PMIC_CFG_MAGIC_NUM             0x3172
70 struct boardcfg_substructure_header {
71         u16     magic;
72         u16     size;
73 } __attribute__((__packed__));
75 struct boardcfg_abi_rev {
76         u8      boardcfg_abi_maj;
77         u8      boardcfg_abi_min;
78 } __attribute__((__packed__));
80 /**
81  * Definitions, types, etc. as used for general board configuration
82  */
83 struct boardcfg_control {
84         struct boardcfg_substructure_header     subhdr;
85         ftbool                                  main_isolation_enable;
86         u16                                     main_isolation_hostid;
87 } __attribute__((__packed__));
89 struct boardcfg_secproxy {
90         struct boardcfg_substructure_header     subhdr;
91         u8                                      scaling_factor;
92         u8                                      scaling_profile;
93         u8                                      disable_main_nav_secure_proxy;
94 } __attribute__((__packed__));
96 struct boardcfg_msmc {
97         struct boardcfg_substructure_header     subhdr;
98         u8                                      msmc_cache_size;
99 } __attribute__((__packed__));
102 #define BOARDCFG_TRACE_DST_UART0                BIT(0)
103 #define BOARDCFG_TRACE_DST_ITM                  BIT(2)
104 #define BOARDCFG_TRACE_DST_MEM                  BIT(3)
106 #define BOARDCFG_TRACE_SRC_PM                   BIT(0)
107 #define BOARDCFG_TRACE_SRC_RM                   BIT(1)
108 #define BOARDCFG_TRACE_SRC_SEC                  BIT(2)
109 #define BOARDCFG_TRACE_SRC_BASE                 BIT(3)
110 #define BOARDCFG_TRACE_SRC_USER                 BIT(4)
111 #define BOARDCFG_TRACE_SRC_SUPR                 BIT(5)
113 struct boardcfg_dbg_cfg {
114         struct boardcfg_substructure_header     subhdr;
115         u16                                     trace_dst_enables;
116         u16                                     trace_src_enables;
117 } __attribute__((__packed__));
119 struct k3_boardcfg {
120         struct boardcfg_abi_rev                 rev;
121         struct boardcfg_control                 control;
122         struct boardcfg_secproxy                secproxy;
123         struct boardcfg_msmc                    msmc;
124         struct boardcfg_dbg_cfg                 debug_cfg;
125 } __attribute__((__packed__));
127 /**
128  * Definitions, types, etc. as used for resource assignment
129  */
130 #define HOST_ID_DMSC                            0
131 #define HOST_ID_R5_0                            3
132 #define HOST_ID_R5_1                            4
133 #define HOST_ID_R5_2                            5
134 #define HOST_ID_R5_3                            6
135 #define HOST_ID_A53_0                           10
136 #define HOST_ID_A53_1                           11
137 #define HOST_ID_A53_2                           12
138 #define HOST_ID_A53_3                           13
139 #define HOST_ID_A53_4                           14
140 #define HOST_ID_A53_5                           15
141 #define HOST_ID_A53_6                           16
142 #define HOST_ID_A53_7                           17
143 #define HOST_ID_GPU_0                           30
144 #define HOST_ID_GPU_1                           31
145 #define HOST_ID_ICSSG_0                         50
146 #define HOST_ID_ICSSG_1                         51
147 #define HOST_ID_ICSSG_2                         52
149 struct boardcfg_rm_host_cfg_entry {
150         u8      host_id;
151         u8      allowed_atype;
152         u16     allowed_qos;
153         u32     allowed_orderid;
154         u16     allowed_priority;
155         u8      allowed_sched_priority;
156 } __attribute__((__packed__));
158 #define BOARDCFG_RM_HOST_CFG_ENTRIES (32U)
160 struct boardcfg_rm_host_cfg {
161         struct boardcfg_substructure_header     subhdr;
162         struct boardcfg_rm_host_cfg_entry
163                                  host_cfg_entries[BOARDCFG_RM_HOST_CFG_ENTRIES];
164 };
166 #define RESASG_TYPE_SHIFT                       0x0006
167 #define RESASG_TYPE_MASK                        0xFFC0
168 #define RESASG_SUBTYPE_SHIFT                    0x0000
169 #define RESASG_SUBTYPE_MASK                     0x003F
171 #define RESASG_UTYPE(type, subtype) \
172         (((type << RESASG_TYPE_SHIFT) & RESASG_TYPE_MASK) | \
173          ((subtype << RESASG_SUBTYPE_SHIFT) & RESASG_SUBTYPE_MASK))
175 enum resasg_types {
176         RESASG_TYPE_MAIN_NAV_UDMASS_IA0 = 0x000,
177         RESASG_TYPE_MAIN_NAV_MODSS_IA0 = 0x001,
178         RESASG_TYPE_MAIN_NAV_MODSS_IA1 = 0x002,
179         RESASG_TYPE_MCU_NAV_UDMASS_IA0 = 0x003,
180         RESASG_TYPE_MAIN_NAV_MCRC = 0x004,
181         RESASG_TYPE_MCU_NAV_MCRC = 0x005,
182         RESASG_TYPE_MAIN_NAV_UDMAP = 0x006,
183         RESASG_TYPE_MCU_NAV_UDMAP = 0x007,
184         RESASG_TYPE_MSMC = 0x008,
185         RESASG_TYPE_MAIN_NAV_RA = 0x009,
186         RESASG_TYPE_MCU_NAV_RA = 0x00A,
187         RESASG_TYPE_GIC_IRQ = 0x00B,
188         RESASG_TYPE_PULSAR_C0_IRQ = 0x00C,
189         RESASG_TYPE_PULSAR_C1_IRQ = 0x00D,
190         RESASG_TYPE_ICSSG0_IRQ = 0x00E,
191         RESASG_TYPE_ICSSG1_IRQ = 0x00F,
192         RESASG_TYPE_ICSSG2_IRQ = 0x010,
193         RESASG_TYPE_MAX = 0x3FF
194 };
196 enum resasg_subtype_main_nav_udmass_ia0 {
197         RESASG_SUBTYPE_MAIN_NAV_UDMASS_IA0_VINT = 0x00,
198         RESASG_SUBTYPE_MAIN_NAV_UDMASS_IA0_SEVI = 0x01,
199         RESASG_SUBTYPE_MAIN_NAV_UDMASS_IA0_MEVI = 0x02,
200         RESASG_SUBTYPE_MAIN_NAV_UDMASS_IA0_GEVI = 0x03,
201         RESASG_SUBYTPE_MAIN_NAV_UDMASS_IA0_CNT = 0x04,
202 };
204 enum resasg_subtype_main_nav_modss_ia0 {
205         RESASG_SUBTYPE_MAIN_NAV_MODSS_IA0_VINT = 0x00,
206         RESASG_SUBTYPE_MAIN_NAV_MODSS_IA0_SEVI = 0x01,
207         RESASG_SUBYTPE_MAIN_NAV_MODSS_IA0_CNT = 0x02,
208 };
210 enum resasg_subtype_main_nav_modss_ia1 {
211         RESASG_SUBTYPE_MAIN_NAV_MODSS_IA1_VINT = 0x00,
212         RESASG_SUBTYPE_MAIN_NAV_MODSS_IA1_SEVI = 0x01,
213         RESASG_SUBYTPE_MAIN_NAV_MODSS_IA1_CNT = 0x02,
214 };
216 enum resasg_subtype_mcu_nav_udmass_ia0 {
217         RESASG_SUBTYPE_MCU_NAV_UDMASS_IA0_VINT = 0x00,
218         RESASG_SUBTYPE_MCU_NAV_UDMASS_IA0_SEVI = 0x01,
219         RESASG_SUBTYPE_MCU_NAV_UDMASS_IA0_MEVI = 0x02,
220         RESASG_SUBTYPE_MCU_NAV_UDMASS_IA0_GEVI = 0x03,
221         RESASG_SUBYTPE_MCU_NAV_UDMASS_IA0_CNT = 0x04,
222 };
224 enum resasg_subtype_main_nav_mcrc {
225         RESASG_SUBTYPE_MAIN_NAV_MCRC_LEVI = 0x00,
226         RESASG_SUBYTPE_MAIN_NAV_MCRC_CNT = 0x01,
227 };
229 enum resasg_subtype_mcu_nav_mcrc {
230         RESASG_SUBTYPE_MCU_NAV_MCRC_LEVI = 0x00,
231         RESASG_SUBYTPE_MCU_NAV_MCRC_CNT = 0x01,
232 };
234 enum resasg_subtype_main_nav_udmap {
235         RESASG_SUBTYPE_MAIN_NAV_UDMAP_TRIGGER = 0x00,
236         RESASG_SUBTYPE_MAIN_NAV_UDMAP_TX_HCHAN = 0x01,
237         RESASG_SUBTYPE_MAIN_NAV_UDMAP_TX_CHAN = 0x02,
238         RESASG_SUBTYPE_MAIN_NAV_UDMAP_TX_ECHAN = 0x03,
239         RESASG_SUBTYPE_MAIN_NAV_UDMAP_RX_HCHAN = 0x04,
240         RESASG_SUBTYPE_MAIN_NAV_UDMAP_RX_CHAN = 0x05,
241         RESASG_SUBTYPE_MAIN_NAV_UDMAP_RX_FLOW_COMMON = 0x06,
242         RESASG_SUBTYPE_MAIN_NAV_UDMAP_INVALID_FLOW_OES = 0x07,
243         RESASG_SUBYTPE_MAIN_NAV_UDMAP_CNT = 0x08,
244 };
246 enum resasg_subtype_mcu_nav_udmap {
247         RESASG_SUBTYPE_MCU_NAV_UDMAP_TRIGGER = 0x00,
248         RESASG_SUBTYPE_MCU_NAV_UDMAP_TX_HCHAN = 0x01,
249         RESASG_SUBTYPE_MCU_NAV_UDMAP_TX_CHAN = 0x02,
250         RESASG_SUBTYPE_MCU_NAV_UDMAP_RX_HCHAN = 0x03,
251         RESASG_SUBTYPE_MCU_NAV_UDMAP_RX_CHAN = 0x04,
252         RESASG_SUBTYPE_MCU_NAV_UDMAP_RX_FLOW_COMMON = 0x05,
253         RESASG_SUBTYPE_MCU_NAV_UDMAP_INVALID_FLOW_OES = 0x06,
254         RESASG_SUBYTPE_MCU_NAV_UDMAP_CNT = 0x07,
255 };
257 enum resasg_subtype_msmc {
258         RESASG_SUBTYPE_MSMC_DRU = 0x00,
259         RESASG_SUBYTPE_MSMC_CNT = 0x01,
260 };
262 enum resasg_subtype_main_nav_ra {
263         RESASG_SUBTYPE_MAIN_NAV_RA_RING_UDMAP_TX = 0x00,
264         RESASG_SUBTYPE_MAIN_NAV_RA_RING_UDMAP_RX = 0x01,
265         RESASG_SUBTYPE_MAIN_NAV_RA_RING_GP = 0x02,
266         RESASG_SUBTYPE_MAIN_NAV_RA_ERROR_OES = 0x03,
267         RESASG_SUBYTPE_MAIN_NAV_RA_CNT = 0x04,
268 };
270 enum resasg_subtype_mcu_nav_ra {
271         RESASG_SUBTYPE_MCU_NAV_RA_RING_UDMAP_TX = 0x00,
272         RESASG_SUBTYPE_MCU_NAV_RA_RING_UDMAP_RX = 0x01,
273         RESASG_SUBTYPE_MCU_NAV_RA_RING_GP = 0x02,
274         RESASG_SUBTYPE_MCU_NAV_RA_ERROR_OES = 0x03,
275         RESASG_SUBYTPE_MCU_NAV_RA_CNT = 0x04,
276 };
278 enum resasg_subtype_gic_irq {
279         RESASG_SUBTYPE_GIC_IRQ_MAIN_NAV_SET0 = 0x00,
280         RESASG_SUBTYPE_GIC_IRQ_MAIN_GPIO = 0x01,
281         RESASG_SUBTYPE_GIC_IRQ_MAIN_NAV_SET1 = 0x02,
282         RESASG_SUBTYPE_GIC_IRQ_COMP_EVT = 0x03,
283         RESASG_SUBTYPE_GIC_IRQ_WKUP_GPIO = 0x04,
284         RESASG_SUBYTPE_GIC_IRQ_CNT = 0x05,
285 };
287 enum resasg_subtype_pulsar_c0_irq {
288         RESASG_SUBTYPE_PULSAR_C0_IRQ_MCU_NAV = 0x00,
289         RESASG_SUBTYPE_PULSAR_C0_IRQ_WKUP_GPIO = 0x01,
290         RESASG_SUBTYPE_PULSAR_C0_IRQ_MAIN2MCU_LVL = 0x02,
291         RESASG_SUBTYPE_PULSAR_C0_IRQ_MAIN2MCU_PLS = 0x03,
292         RESASG_SUBYTPE_PULSAR_C0_IRQ_CNT = 0x04,
293 };
295 enum resasg_subtype_pulsar_c1_irq {
296         RESASG_SUBTYPE_PULSAR_C1_IRQ_MCU_NAV = 0x00,
297         RESASG_SUBTYPE_PULSAR_C1_IRQ_WKUP_GPIO = 0x01,
298         RESASG_SUBTYPE_PULSAR_C1_IRQ_MAIN2MCU_LVL = 0x02,
299         RESASG_SUBTYPE_PULSAR_C1_IRQ_MAIN2MCU_PLS = 0x03,
300         RESASG_SUBYTPE_PULSAR_C1_IRQ_CNT = 0x04,
301 };
303 enum resasg_subtype_icssg0_irq {
304         RESASG_SUBTYPE_ICSSG0_IRQ_MAIN_NAV = 0x00,
305         RESASG_SUBTYPE_ICSSG0_IRQ_MAIN_GPIO = 0x01,
306         RESASG_SUBYTPE_ICSSG0_IRQ_CNT = 0x02,
307 };
309 enum resasg_subtype_icssg1_irq {
310         RESASG_SUBTYPE_ICSSG1_IRQ_MAIN_NAV = 0x00,
311         RESASG_SUBTYPE_ICSSG1_IRQ_MAIN_GPIO = 0x01,
312         RESASG_SUBYTPE_ICSSG1_IRQ_CNT = 0x02,
313 };
315 enum resasg_subtype_icssg2_irq {
316         RESASG_SUBTYPE_ICSSG2_IRQ_MAIN_NAV = 0x00,
317         RESASG_SUBTYPE_ICSSG2_IRQ_MAIN_GPIO = 0x01,
318         RESASG_SUBYTPE_ICSSG2_IRQ_CNT = 0x02,
319 };
321 struct boardcfg_rm_resasg_entry {
322         u16                                     start_resource;
323         u16                                     num_resource;
324         u16                                     type;
325         u8                                      host_id;
326         u8                                      reserved;
327 };
329 struct boardcfg_rm_resasg {
330         struct boardcfg_substructure_header     subhdr;
331         u16                                     resasg_entries_size;
332         u16                                     reserved;
333         struct boardcfg_rm_resasg_entry         resasg_entries[];
334 } __attribute__((__packed__));
336 struct k3_boardcfg_rm {
337         struct boardcfg_abi_rev                 rev;
338         struct boardcfg_rm_host_cfg             host_cfg;
339         struct boardcfg_rm_resasg               resasg;
340 } __attribute__((__packed__));
342 #define AM65_BOARDCFG_RM_RESASG_ENTRIES         59
344 /*
345  * This is essentially 'struct k3_boardcfg_rm', but modified to pull
346  * .resasg_entries which is a member of 'struct boardcfg_rm_resasg' into
347  * the outer structure for easier explicit initialization.
348  */
349 struct am65_boardcfg_rm_local {
350         struct k3_boardcfg_rm                   rm_boardcfg;
351         struct boardcfg_rm_resasg_entry
352                                 resasg_entries[AM65_BOARDCFG_RM_RESASG_ENTRIES];
353 } __attribute__((__packed__));
355 /**
356  * Definitions, types, etc. as used for the security configuration
357  */
358 #define PROCESSOR_ACL_SECONDARY_MASTERS_MAX     3
360 struct boardcfg_proc_acl_entry {
361         u8                                      processor_id;
362         u8                                      proc_access_master;
363         u8           proc_access_secondary[PROCESSOR_ACL_SECONDARY_MASTERS_MAX];
364 } __attribute__((__packed__));
366 #define PROCESSOR_ACL_ENTRIES                   32
368 struct boardcfg_proc_acl {
369         struct boardcfg_substructure_header     subhdr;
370         struct boardcfg_proc_acl_entry  proc_acl_entries[PROCESSOR_ACL_ENTRIES];
371 } __attribute__((__packed__));
373 struct boardcfg_host_hierarchy_entry {
374         u8                                      host_id;
375         u8                                      supervisor_host_id;
376 } __attribute__((__packed__));
378 #define HOST_HIERARCHY_ENTRIES                  32
380 struct boardcfg_host_hierarchy {
381         struct boardcfg_substructure_header     subhdr;
382         struct boardcfg_host_hierarchy_entry
383                                  host_hierarchy_entries[HOST_HIERARCHY_ENTRIES];
384 } __attribute__((__packed__));
386 struct k3_boardcfg_security {
387         struct boardcfg_abi_rev                 rev;
388         struct boardcfg_proc_acl                processor_acl_list;
389         struct boardcfg_host_hierarchy          host_hierarchy;
390 } __attribute__((__packed__));
392 /**
393  * Definitions, types, etc. as used for PM configuration
394  */
395 struct k3_boardcfg_pm {
396         struct boardcfg_abi_rev                 rev;
397 } __attribute__((__packed__));
399 /**
400  * Export different board configuration structures
401  */
402 extern const struct k3_boardcfg am65_boardcfg_data;
403 extern const struct am65_boardcfg_rm_local am65_boardcfg_rm_data;
404 extern const struct k3_boardcfg_security am65_boardcfg_security_data;
405 extern const struct k3_boardcfg_pm am65_boardcfg_pm_data;