NOTICE OF RELOCATION
[processor-firmware/system-firmware-image-gen.git] / include / soc / am65x / devices.h
1 /*
2  * K3 System Firmware Board Configuration Data Definitions
3  *
4  * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  *
10  *    Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  *
13  *    Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the
16  *    distribution.
17  *
18  *    Neither the name of Texas Instruments Incorporated nor the names of
19  *    its contributors may be used to endorse or promote products derived
20  *    from this software without specific prior written permission.
21  *
22  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33  */
35 #ifndef SOC_AM6_DEVICES_H
36 #define SOC_AM6_DEVICES_H
38 #define AM6_DEV_DCC4 13
39 #define AM6_DEV_DCC6 15
40 #define AM6_DEV_DCC0 9
41 #define AM6_DEV_MCU_DCC2 19
42 #define AM6_DEV_DCC5 14
43 #define AM6_DEV_MCU_DCC0 17
44 #define AM6_DEV_MCU_DCC1 18
45 #define AM6_DEV_DCC1 10
46 #define AM6_DEV_DCC3 12
47 #define AM6_DEV_DCC7 16
48 #define AM6_DEV_DCC2 11
49 #define AM6_DEV_MCU_I2C0 114
50 #define AM6_DEV_I2C3 113
51 #define AM6_DEV_I2C2 112
52 #define AM6_DEV_WKUP_I2C0 115
53 #define AM6_DEV_I2C0 110
54 #define AM6_DEV_I2C1 111
55 #define AM6_DEV_TIMER5 30
56 #define AM6_DEV_TIMER6 31
57 #define AM6_DEV_TIMER7 32
58 #define AM6_DEV_MCU_TIMER0 35
59 #define AM6_DEV_TIMER8 33
60 #define AM6_DEV_TIMER2 27
61 #define AM6_DEV_MCU_TIMER1 36
62 #define AM6_DEV_MCU_TIMER2 37
63 #define AM6_DEV_TIMER4 29
64 #define AM6_DEV_TIMER3 28
65 #define AM6_DEV_TIMER9 34
66 #define AM6_DEV_TIMER11 26
67 #define AM6_DEV_TIMER10 25
68 #define AM6_DEV_TIMER0 23
69 #define AM6_DEV_MCU_TIMER3 38
70 #define AM6_DEV_TIMER1 24
71 #define AM6_DEV_WKUP_PSC0 79
72 #define AM6_DEV_CBASS0 82
73 #define AM6_DEV_PLL_MMR0 101
74 #define AM6_DEV_MCU_CPT2_AGGR0 7
75 #define AM6_DEV_CPT2_AGGR0 6
76 #define AM6_DEV_DEBUGSS0 68
77 #define AM6_DEV_EHRPWM4 44
78 #define AM6_DEV_EHRPWM1 41
79 #define AM6_DEV_EHRPWM0 40
80 #define AM6_DEV_EHRPWM3 43
81 #define AM6_DEV_EHRPWM5 45
82 #define AM6_DEV_EHRPWM2 42
83 #define AM6_DEV_ELM0 46
84 #define AM6_DEV_MCU_UART0 149
85 #define AM6_DEV_WKUP_UART0 150
86 #define AM6_DEV_UART1 147
87 #define AM6_DEV_UART0 146
88 #define AM6_DEV_UART2 148
89 #define AM6_DEV_SA2_UL0 136
90 #define AM6_DEV_CAL0 2
91 #define AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMLO_4 206
92 #define AM6_DEV_CPT2_PROBE_VBUSM_MCU_FSS_S1_3 207
93 #define AM6_DEV_CPT2_PROBE_VBUSM_MCU_EXPORT_SLV_0 208
94 #define AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMHI_3 209
95 #define AM6_DEV_CPT2_PROBE_VBUSM_MCU_SRAM_SLV_1 210
96 #define AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRHI_5 211
97 #define AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRLO_6 212
98 #define AM6_DEV_CPT2_PROBE_VBUSM_MAIN_CAL0_0 213
99 #define AM6_DEV_CPT2_PROBE_VBUSM_MAIN_DSS_2 214
100 #define AM6_DEV_CPT2_PROBE_VBUSM_MCU_FSS_S0_2 215
101 #define AM6_DEV_PBIST0 73
102 #define AM6_DEV_PBIST1 74
103 #define AM6_DEV_MCU_PBIST0 75
104 #define AM6_DEV_NAVSS0 118
105 #define AM6_DEV_DSS0 67
106 #define AM6_DEV_GPMC0 60
107 #define AM6_DEV_MMCSD1 48
108 #define AM6_DEV_WKUP_PLLCTRL0 77
109 #define AM6_DEV_PLLCTRL0 76
110 #define AM6_DEV_USB3SS1 152
111 #define AM6_DEV_USB3SS0 151
112 #define AM6_DEV_MCU_MCSPI0 142
113 #define AM6_DEV_MCSPI2 139
114 #define AM6_DEV_MCU_MCSPI2 144
115 #define AM6_DEV_MCSPI0 137
116 #define AM6_DEV_MCSPI1 138
117 #define AM6_DEV_MCSPI4 141
118 #define AM6_DEV_MCSPI3 140
119 #define AM6_DEV_MCU_MCSPI1 143
120 #define AM6_DEV_DEBUGSS_WRAP0 21
121 #define AM6_DEV_CBASS_INFRA0 85
122 #define AM6_DEV_STM0 8
123 #define AM6_DEV_MCU_RTI1 135
124 #define AM6_DEV_RTI0 130
125 #define AM6_DEV_RTI3 133
126 #define AM6_DEV_RTI1 131
127 #define AM6_DEV_MCU_RTI0 134
128 #define AM6_DEV_RTI2 132
129 #define AM6_DEV_PSRAMECC0 128
130 #define AM6_DEV_EFUSE0 69
131 #define AM6_DEV_MCASP0 104
132 #define AM6_DEV_MCASP1 105
133 #define AM6_DEV_MCASP2 106
134 #define AM6_DEV_MCU_ARMSS0 129
135 #define AM6_DEV_MCU_ARMSS0_CPU0 159
136 #define AM6_DEV_MCU_ARMSS0_CPU1 245
137 #define AM6_DEV_CCDEBUGSS0 66
138 #define AM6_DEV_WKUP_CTRL_MMR0 155
139 #define AM6_DEV_MCU_CBASS_FW0 91
140 #define AM6_DEV_MCU_CPSW0 5
141 #define AM6_DEV_SERDES0 153
142 #define AM6_DEV_SERDES1 154
143 #define AM6_DEV_OLDI_TX_CORE_MAIN_0 216
144 #define AM6_DEV_MCU_ADC1 1
145 #define AM6_DEV_MCU_ADC0 0
146 #define AM6_DEV_WKUP_DMSC0 22
147 #define AM6_DEV_MCU_PLL_MMR0 108
148 #define AM6_DEV_MCU_SEC_MMR0 109
149 #define AM6_DEV_GIC0 56
150 #define AM6_DEV_MCU_DEBUGSS0 71
151 #define AM6_DEV_EQEP0 49
152 #define AM6_DEV_EQEP2 51
153 #define AM6_DEV_EQEP1 50
154 #define AM6_DEV_WKUP_GPIO0 59
155 #define AM6_DEV_GPIO0 57
156 #define AM6_DEV_GPIO1 58
157 #define AM6_DEV_COMPUTE_CLUSTER_MSMC0 196
158 #define AM6_DEV_COMPUTE_CLUSTER_PBIST0 197
159 #define AM6_DEV_COMPUTE_CLUSTER_CPAC0 198
160 #define AM6_DEV_COMPUTE_CLUSTER_CPAC_PBIST0 199
161 #define AM6_DEV_COMPUTE_CLUSTER_CPAC1 200
162 #define AM6_DEV_COMPUTE_CLUSTER_CPAC_PBIST1 201
163 #define AM6_DEV_COMPUTE_CLUSTER_A53_0 202
164 #define AM6_DEV_COMPUTE_CLUSTER_A53_1 203
165 #define AM6_DEV_COMPUTE_CLUSTER_A53_2 204
166 #define AM6_DEV_COMPUTE_CLUSTER_A53_3 205
167 #define AM6_DEV_WKUP_CBASS0 94
168 #define AM6_DEV_MCU_ROM0 78
169 #define AM6_DEV_K3_ARM_ATB_FUNNEL_3_32_MCU_0 217
170 #define AM6_DEV_ESM0 52
171 #define AM6_DEV_PRU_ICSSG2 64
172 #define AM6_DEV_PRU_ICSSG0 62
173 #define AM6_DEV_PRU_ICSSG1 63
174 #define AM6_DEV_MCU_ESM0 53
175 #define AM6_DEV_ECAP0 39
176 #define AM6_DEV_WKUP_ESM0 54
177 #define AM6_DEV_MCU_EFUSE0 72
178 #define AM6_DEV_MCU_CTRL_MMR0 107
179 #define AM6_DEV_PSC0 70
180 #define AM6_DEV_CTRL_MMR0 99
181 #define AM6_DEV_MCU_MCAN0 102
182 #define AM6_DEV_MCU_MCAN1 103
183 #define AM6_DEV_DDRSS0 20
184 #define AM6_DEV_MCU_NAVSS0 119
185 #define AM6_DEV_MCU_FSS0 55
186 #define AM6_DEV_DFTSS0 117
187 #define AM6_DEV_WKUP_GPIOMUX_INTRTR0 156
188 #define AM6_DEV_GPIOMUX_INTRTR0 100
189 #define AM6_DEV_MAIN2MCU_LVL_INTRTR0 97
190 #define AM6_DEV_MAIN2MCU_PLS_INTRTR0 98
191 #define AM6_DEV_ICEMELTER_WKUP_0 218
192 #define AM6_DEV_GPU0 65
193 #define AM6_DEV_PDMA_DEBUG0 122
194 #define AM6_DEV_PDMA0 123
195 #define AM6_DEV_PDMA1 124
196 #define AM6_DEV_MCU_PDMA0 125
197 #define AM6_DEV_MCU_PDMA1 126
198 #define AM6_DEV_MCU_MSRAM0 116
199 #define AM6_DEV_CMPEVENT_INTRTR0 3
200 #define AM6_DEV_DEBUGSUSPENDRTR0 81
201 #define AM6_DEV_TIMESYNC_INTRTR0 145
202 #define AM6_DEV_CBASS_DEBUG0 83
203 #define AM6_DEV_CBASS_FW0 84
204 #define AM6_DEV_MCU_CBASS_DEBUG0 90
205 #define AM6_DEV_WKUP_CBASS_FW0 96
206 #define AM6_DEV_PCIE0 120
207 #define AM6_DEV_PCIE1 121
208 #define AM6_DEV_GTC0 61
209 #define AM6_DEV_K3_LED_MAIN_0 219
210 #define AM6_DEV_WKUP_VTM0 80
211 #define AM6_DEV_MMCSD0 47
212 #define AM6_DEV_MCU_ECC_AGGR0 92
213 #define AM6_DEV_ECC_AGGR1 87
214 #define AM6_DEV_ECC_AGGR2 88
215 #define AM6_DEV_MCU_ECC_AGGR1 93
216 #define AM6_DEV_WKUP_ECC_AGGR0 95
217 #define AM6_DEV_VDC_DATA_VBUSM_32B_REF_WKUP2MCU 220
218 #define AM6_DEV_VDC_DATA_VBUSM_32B_REF_MCU2WKUP 221
219 #define AM6_DEV_VDC_DATA_VBUSM_64B_REF_MAIN2MCU 222
220 #define AM6_DEV_VDC_DATA_VBUSM_64B_REF_MCU2MAIN 223
221 #define AM6_DEV_VDC_DMSC_DBG_VBUSP_32B_REF_DBG2DMSC 224
222 #define AM6_DEV_VDC_INFRA_VBUSP_32B_REF_WKUP2MAIN_INFRA 225
223 #define AM6_DEV_VDC_INFRA_VBUSP_32B_REF_MCU2MAIN_INFRA 226
224 #define AM6_DEV_VDC_SOC_FW_VBUSP_32B_REF_FWWKUP2MCU 227
225 #define AM6_DEV_VDC_SOC_FW_VBUSP_32B_REF_FWMCU2MAIN 228
226 #define AM6_DEV_VDC_MCU_DBG_VBUSP_32B_REF_DBGMAIN2MCU 229
227 #define AM6_DEV_ECC_AGGR0 86
228 #define AM6_DEV_VDC_NAV_PSIL_128B_REF_MAIN2MCU 230
229 #define AM6_DEV_MCU_PSRAM0 127
230 #define AM6_DEV_GS80PRG_SOC_WRAP_WKUP_0 231
231 #define AM6_DEV_GS80PRG_MCU_WRAP_WKUP_0 232
232 #define AM6_DEV_MCU_CBASS0 89
233 #define AM6_DEV_MX_WAKEUP_RESET_SYNC_WKUP_0 233
234 #define AM6_DEV_MX_EFUSE_MAIN_CHAIN_MAIN_0 234
235 #define AM6_DEV_MX_EFUSE_MCU_CHAIN_MCU_0 235
236 #define AM6_DEV_DUMMY_IP_LPSC_WKUP2MCU 236
237 #define AM6_DEV_DUMMY_IP_LPSC_WKUP2MAIN_INFRA 237
238 #define AM6_DEV_DUMMY_IP_LPSC_DEBUG2DMSC 238
239 #define AM6_DEV_DUMMY_IP_LPSC_DMSC 239
240 #define AM6_DEV_DUMMY_IP_LPSC_MCU2MAIN_INFRA 240
241 #define AM6_DEV_DUMMY_IP_LPSC_MCU2MAIN 241
242 #define AM6_DEV_DUMMY_IP_LPSC_MCU2WKUP 242
243 #define AM6_DEV_DUMMY_IP_LPSC_MAIN2MCU 243
244 #define AM6_DEV_DUMMY_IP_LPSC_EMIF_DATA 244
245 #define AM6_DEV_BOARD0 157
246 #define AM6_DEV_WKUP_DMSC0_CORTEX_M3_0 161
247 #define AM6_DEV_WKUP_DMSC0_INTR_AGGR_0 162
248 #define AM6_DEV_NAVSS0_CPTS0 163
249 #define AM6_DEV_NAVSS0_INTR_ROUTER_0 182
250 #define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER0 164
251 #define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER1 165
252 #define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER2 166
253 #define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER3 167
254 #define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER4 168
255 #define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER5 169
256 #define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER6 170
257 #define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER7 171
258 #define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER8 172
259 #define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER9 173
260 #define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER10 174
261 #define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER11 175
262 #define AM6_DEV_NAVSS0_MCRC0 176
263 #define AM6_DEV_NAVSS0_MODSS_INTA0 180
264 #define AM6_DEV_NAVSS0_MODSS_INTA1 181
265 #define AM6_DEV_NAVSS0_PROXY0 185
266 #define AM6_DEV_NAVSS0_PVU0 177
267 #define AM6_DEV_NAVSS0_PVU1 178
268 #define AM6_DEV_NAVSS0_RINGACC0 187
269 #define AM6_DEV_NAVSS0_SEC_PROXY0 186
270 #define AM6_DEV_NAVSS0_TIMER_MGR0 183
271 #define AM6_DEV_NAVSS0_TIMER_MGR1 184
272 #define AM6_DEV_NAVSS0_UDMAP0 188
273 #define AM6_DEV_NAVSS0_UDMASS_INTA0 179
274 #define AM6_DEV_MCU_NAVSS0_INTR_AGGR_0 189
275 #define AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0 190
276 #define AM6_DEV_MCU_NAVSS0_MCRC0 193
277 #define AM6_DEV_MCU_NAVSS0_PROXY0 191
278 #define AM6_DEV_MCU_NAVSS0_RINGACC0 195
279 #define AM6_DEV_MCU_NAVSS0_SEC_PROXY0 192
280 #define AM6_DEV_MCU_NAVSS0_UDMAP0 194
282 #endif /* SOC_AM6_DEVICES_H */