common.h: Drop all AM65x specific header definitions
[processor-firmware/system-firmware-image-gen.git] / common.h
index 912a524074c6f27e0d3daaeff628ce211fc79105..83c900cab1e986bd6b551ee36a99324668fa0866 100644 (file)
--- a/common.h
+++ b/common.h
@@ -37,6 +37,9 @@
 #define COMMON_H
 
 #include <sysfw_img_cfg.h>
+#include <devices.h>
+#include <hosts.h>
+#include <resasg_types.h>
 
 /**
  * Standard Linux Kernel integer types
@@ -134,28 +137,6 @@ struct boardcfg {
        struct boardcfg_dbg_cfg                 debug_cfg;
 } __attribute__((__packed__));
 
-/**
- * Definitions, types, etc. as used for resource assignment
- */
-#define HOST_ID_DMSC                           0
-#define HOST_ID_R5_0                           3
-#define HOST_ID_R5_1                           4
-#define HOST_ID_R5_2                           5
-#define HOST_ID_R5_3                           6
-#define HOST_ID_A53_0                          10
-#define HOST_ID_A53_1                          11
-#define HOST_ID_A53_2                          12
-#define HOST_ID_A53_3                          13
-#define HOST_ID_A53_4                          14
-#define HOST_ID_A53_5                          15
-#define HOST_ID_A53_6                          16
-#define HOST_ID_A53_7                          17
-#define HOST_ID_GPU_0                          30
-#define HOST_ID_GPU_1                          31
-#define HOST_ID_ICSSG_0                                50
-#define HOST_ID_ICSSG_1                                51
-#define HOST_ID_ICSSG_2                                52
-
 struct boardcfg_rm_host_cfg_entry {
        u8      host_id;
        u8      allowed_atype;
@@ -173,161 +154,6 @@ struct boardcfg_rm_host_cfg {
                                 host_cfg_entries[BOARDCFG_RM_HOST_CFG_ENTRIES];
 };
 
-#define RESASG_TYPE_SHIFT                      0x0006
-#define RESASG_TYPE_MASK                       0xFFC0
-#define RESASG_SUBTYPE_SHIFT                   0x0000
-#define RESASG_SUBTYPE_MASK                    0x003F
-
-#define RESASG_UTYPE(type, subtype) \
-       (((type << RESASG_TYPE_SHIFT) & RESASG_TYPE_MASK) | \
-        ((subtype << RESASG_SUBTYPE_SHIFT) & RESASG_SUBTYPE_MASK))
-
-enum resasg_types {
-       RESASG_TYPE_MAIN_NAV_UDMASS_IA0 = 0x000,
-       RESASG_TYPE_MAIN_NAV_MODSS_IA0 = 0x001,
-       RESASG_TYPE_MAIN_NAV_MODSS_IA1 = 0x002,
-       RESASG_TYPE_MCU_NAV_UDMASS_IA0 = 0x003,
-       RESASG_TYPE_MAIN_NAV_MCRC = 0x004,
-       RESASG_TYPE_MCU_NAV_MCRC = 0x005,
-       RESASG_TYPE_MAIN_NAV_UDMAP = 0x006,
-       RESASG_TYPE_MCU_NAV_UDMAP = 0x007,
-       RESASG_TYPE_MSMC = 0x008,
-       RESASG_TYPE_MAIN_NAV_RA = 0x009,
-       RESASG_TYPE_MCU_NAV_RA = 0x00A,
-       RESASG_TYPE_GIC_IRQ = 0x00B,
-       RESASG_TYPE_PULSAR_C0_IRQ = 0x00C,
-       RESASG_TYPE_PULSAR_C1_IRQ = 0x00D,
-       RESASG_TYPE_ICSSG0_IRQ = 0x00E,
-       RESASG_TYPE_ICSSG1_IRQ = 0x00F,
-       RESASG_TYPE_ICSSG2_IRQ = 0x010,
-       RESASG_TYPE_MAX = 0x3FF
-};
-
-enum resasg_subtype_main_nav_udmass_ia0 {
-       RESASG_SUBTYPE_MAIN_NAV_UDMASS_IA0_VINT = 0x00,
-       RESASG_SUBTYPE_MAIN_NAV_UDMASS_IA0_SEVI = 0x01,
-       RESASG_SUBTYPE_MAIN_NAV_UDMASS_IA0_MEVI = 0x02,
-       RESASG_SUBTYPE_MAIN_NAV_UDMASS_IA0_GEVI = 0x03,
-       RESASG_SUBYTPE_MAIN_NAV_UDMASS_IA0_CNT = 0x04,
-};
-
-enum resasg_subtype_main_nav_modss_ia0 {
-       RESASG_SUBTYPE_MAIN_NAV_MODSS_IA0_VINT = 0x00,
-       RESASG_SUBTYPE_MAIN_NAV_MODSS_IA0_SEVI = 0x01,
-       RESASG_SUBYTPE_MAIN_NAV_MODSS_IA0_CNT = 0x02,
-};
-
-enum resasg_subtype_main_nav_modss_ia1 {
-       RESASG_SUBTYPE_MAIN_NAV_MODSS_IA1_VINT = 0x00,
-       RESASG_SUBTYPE_MAIN_NAV_MODSS_IA1_SEVI = 0x01,
-       RESASG_SUBYTPE_MAIN_NAV_MODSS_IA1_CNT = 0x02,
-};
-
-enum resasg_subtype_mcu_nav_udmass_ia0 {
-       RESASG_SUBTYPE_MCU_NAV_UDMASS_IA0_VINT = 0x00,
-       RESASG_SUBTYPE_MCU_NAV_UDMASS_IA0_SEVI = 0x01,
-       RESASG_SUBTYPE_MCU_NAV_UDMASS_IA0_MEVI = 0x02,
-       RESASG_SUBTYPE_MCU_NAV_UDMASS_IA0_GEVI = 0x03,
-       RESASG_SUBYTPE_MCU_NAV_UDMASS_IA0_CNT = 0x04,
-};
-
-enum resasg_subtype_main_nav_mcrc {
-       RESASG_SUBTYPE_MAIN_NAV_MCRC_LEVI = 0x00,
-       RESASG_SUBYTPE_MAIN_NAV_MCRC_CNT = 0x01,
-};
-
-enum resasg_subtype_mcu_nav_mcrc {
-       RESASG_SUBTYPE_MCU_NAV_MCRC_LEVI = 0x00,
-       RESASG_SUBYTPE_MCU_NAV_MCRC_CNT = 0x01,
-};
-
-enum resasg_subtype_main_nav_udmap {
-       RESASG_SUBTYPE_MAIN_NAV_UDMAP_TRIGGER = 0x00,
-       RESASG_SUBTYPE_MAIN_NAV_UDMAP_TX_HCHAN = 0x01,
-       RESASG_SUBTYPE_MAIN_NAV_UDMAP_TX_CHAN = 0x02,
-       RESASG_SUBTYPE_MAIN_NAV_UDMAP_TX_ECHAN = 0x03,
-       RESASG_SUBTYPE_MAIN_NAV_UDMAP_RX_HCHAN = 0x04,
-       RESASG_SUBTYPE_MAIN_NAV_UDMAP_RX_CHAN = 0x05,
-       RESASG_SUBTYPE_MAIN_NAV_UDMAP_RX_FLOW_COMMON = 0x06,
-       RESASG_SUBTYPE_MAIN_NAV_UDMAP_INVALID_FLOW_OES = 0x07,
-       RESASG_SUBYTPE_MAIN_NAV_UDMAP_CNT = 0x08,
-};
-
-enum resasg_subtype_mcu_nav_udmap {
-       RESASG_SUBTYPE_MCU_NAV_UDMAP_TRIGGER = 0x00,
-       RESASG_SUBTYPE_MCU_NAV_UDMAP_TX_HCHAN = 0x01,
-       RESASG_SUBTYPE_MCU_NAV_UDMAP_TX_CHAN = 0x02,
-       RESASG_SUBTYPE_MCU_NAV_UDMAP_RX_HCHAN = 0x03,
-       RESASG_SUBTYPE_MCU_NAV_UDMAP_RX_CHAN = 0x04,
-       RESASG_SUBTYPE_MCU_NAV_UDMAP_RX_FLOW_COMMON = 0x05,
-       RESASG_SUBTYPE_MCU_NAV_UDMAP_INVALID_FLOW_OES = 0x06,
-       RESASG_SUBYTPE_MCU_NAV_UDMAP_CNT = 0x07,
-};
-
-enum resasg_subtype_msmc {
-       RESASG_SUBTYPE_MSMC_DRU = 0x00,
-       RESASG_SUBYTPE_MSMC_CNT = 0x01,
-};
-
-enum resasg_subtype_main_nav_ra {
-       RESASG_SUBTYPE_MAIN_NAV_RA_RING_UDMAP_TX = 0x00,
-       RESASG_SUBTYPE_MAIN_NAV_RA_RING_UDMAP_RX = 0x01,
-       RESASG_SUBTYPE_MAIN_NAV_RA_RING_GP = 0x02,
-       RESASG_SUBTYPE_MAIN_NAV_RA_ERROR_OES = 0x03,
-       RESASG_SUBYTPE_MAIN_NAV_RA_CNT = 0x04,
-};
-
-enum resasg_subtype_mcu_nav_ra {
-       RESASG_SUBTYPE_MCU_NAV_RA_RING_UDMAP_TX = 0x00,
-       RESASG_SUBTYPE_MCU_NAV_RA_RING_UDMAP_RX = 0x01,
-       RESASG_SUBTYPE_MCU_NAV_RA_RING_GP = 0x02,
-       RESASG_SUBTYPE_MCU_NAV_RA_ERROR_OES = 0x03,
-       RESASG_SUBYTPE_MCU_NAV_RA_CNT = 0x04,
-};
-
-enum resasg_subtype_gic_irq {
-       RESASG_SUBTYPE_GIC_IRQ_MAIN_NAV_SET0 = 0x00,
-       RESASG_SUBTYPE_GIC_IRQ_MAIN_GPIO = 0x01,
-       RESASG_SUBTYPE_GIC_IRQ_MAIN_NAV_SET1 = 0x02,
-       RESASG_SUBTYPE_GIC_IRQ_COMP_EVT = 0x03,
-       RESASG_SUBTYPE_GIC_IRQ_WKUP_GPIO = 0x04,
-       RESASG_SUBYTPE_GIC_IRQ_CNT = 0x05,
-};
-
-enum resasg_subtype_pulsar_c0_irq {
-       RESASG_SUBTYPE_PULSAR_C0_IRQ_MCU_NAV = 0x00,
-       RESASG_SUBTYPE_PULSAR_C0_IRQ_WKUP_GPIO = 0x01,
-       RESASG_SUBTYPE_PULSAR_C0_IRQ_MAIN2MCU_LVL = 0x02,
-       RESASG_SUBTYPE_PULSAR_C0_IRQ_MAIN2MCU_PLS = 0x03,
-       RESASG_SUBYTPE_PULSAR_C0_IRQ_CNT = 0x04,
-};
-
-enum resasg_subtype_pulsar_c1_irq {
-       RESASG_SUBTYPE_PULSAR_C1_IRQ_MCU_NAV = 0x00,
-       RESASG_SUBTYPE_PULSAR_C1_IRQ_WKUP_GPIO = 0x01,
-       RESASG_SUBTYPE_PULSAR_C1_IRQ_MAIN2MCU_LVL = 0x02,
-       RESASG_SUBTYPE_PULSAR_C1_IRQ_MAIN2MCU_PLS = 0x03,
-       RESASG_SUBYTPE_PULSAR_C1_IRQ_CNT = 0x04,
-};
-
-enum resasg_subtype_icssg0_irq {
-       RESASG_SUBTYPE_ICSSG0_IRQ_MAIN_NAV = 0x00,
-       RESASG_SUBTYPE_ICSSG0_IRQ_MAIN_GPIO = 0x01,
-       RESASG_SUBYTPE_ICSSG0_IRQ_CNT = 0x02,
-};
-
-enum resasg_subtype_icssg1_irq {
-       RESASG_SUBTYPE_ICSSG1_IRQ_MAIN_NAV = 0x00,
-       RESASG_SUBTYPE_ICSSG1_IRQ_MAIN_GPIO = 0x01,
-       RESASG_SUBYTPE_ICSSG1_IRQ_CNT = 0x02,
-};
-
-enum resasg_subtype_icssg2_irq {
-       RESASG_SUBTYPE_ICSSG2_IRQ_MAIN_NAV = 0x00,
-       RESASG_SUBTYPE_ICSSG2_IRQ_MAIN_GPIO = 0x01,
-       RESASG_SUBYTPE_ICSSG2_IRQ_CNT = 0x02,
-};
-
 struct boardcfg_rm_resasg_entry {
        u16                                     start_resource;
        u16                                     num_resource;